[PATCH-for-6.0] target/mips: Correct the license text

[Philippe Mathieu-Daudé]

The license is the 'GNU General Public License v2.0 or later',
not 'and':

  This program is free software; you can redistribute it and/ori
  modify it under the terms of the GNU General Public License as
  published by the Free Software Foundation; either version 2 of
  the License, or (at your option) any later version.

Fix the license comment.

Fixes: 3f7a927847a ("target/mips: LSA/DLSA R6 decodetree helpers")
Signed-off-by: Philippe Mathieu-Daudé 
---
Commit introduced after 5.2 release, during the 6.0 cycle.
Harmless and useful for 6.0-rc4 IMHO.
---
 target/mips/rel6_translate.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/target/mips/rel6_translate.c b/target/mips/rel6_translate.c
index 139a7524eea..c5843cbc5e2 100644
--- a/target/mips/rel6_translate.c
+++ b/target/mips/rel6_translate.c
@@ -6,7 +6,7 @@
  *  Copyright (c) 2006 Thiemo Seufer (MIPS32R2 support)
  *  Copyright (c) 2020 Philippe Mathieu-Daudé
  *
- * This code is licensed under the GNU GPLv2 and later.
+ * This work is licensed under the terms of the GNU GPL, version 2 or later.
  */
 
 #include "qemu/osdep.h"
-- 
2.26.3

Re: any remaining for-6.0 issues?

[Mark Cave-Ayland]

On 17/04/2021 20:46, Peter Maydell wrote:


On 14/04/2021 13:48, Thomas Huth wrote:

I've seen some intermittend, non-reproducible crashes with usermode QEMU in 
some of
my CI runs, e.g.:

https://gitlab.com/thuth/qemu/-/jobs/1178256498#L3876

https://gitlab.com/thuth/qemu/-/jobs/1146276208#L3241

This was only with ccache enabled, so I thought that it might be related to my
work-in-progress ccache patches...

... but now Cornelia reported that she has seen such a crash in one of her 
branches,
too (which is completely unrelated to my ccache patches):

https://gitlab.com/cohuck/qemu/-/jobs/1178860927#L3867

That makes me wonder whether we currently have a real problem with user-mode in 
the
master branch? Did anybody else see such problems?


I've definitely seen the same issue as Cornelia in my Gitlab CI builds for the 
ESP
security fixes (first version of which appeared just before rc0). The user 
builds
always fail on "run-tcg-tests-s390x-linux-user" for me.


Do we have any better understanding yet of the cause here?
(I ask because I think we're going to need an rc4 for other reasons,
so if there's a ready-to-go fix then we could consider it.)


I don't think so. I tried a run with a possible candidate patch reverted (see 
https://lists.gnu.org/archive/html/qemu-devel/2021-04/msg02345.html) but Cornelia's 
response indicates that the result is still inconclusive :(



ATB,

Mark.

[PATCH v5 1/1] docs/devel: Add VFIO device migration documentation

[Tarun Gupta]

Document interfaces used for VFIO device migration. Added flow of state changes
during live migration with VFIO device.

Reviewed-by: Cornelia Huck 
Co-developed-by: Kirti Wankhede 
Signed-off-by: Kirti Wankhede 
Signed-off-by: Tarun Gupta 
---
Tested by building docs with new vfio-migration.rst file

v5:
- Fixed meta issues in commit message

v4:
- Added info about vfio_listener_log_global_[start|stop]
- Added info about `save_state` callback.
- Incorporated comments from v3.

v3:
- Add introductory line about VM migration in general.
- Remove occurcences of vfio_pin_pages() to describe pinning.
- Incorporated comments from v2

v2:
- Included the new vfio-migration.rst file in index.rst
- Updated dirty page tracking section, also added details about
  'pre-copy-dirty-page-tracking' opt-out option.
- Incorporated comments around wording of doc.

---
 MAINTAINERS   |   1 +
 docs/devel/index.rst  |   1 +
 docs/devel/vfio-migration.rst | 150 ++
 3 files changed, 152 insertions(+)
 create mode 100644 docs/devel/vfio-migration.rst

diff --git a/MAINTAINERS b/MAINTAINERS
index 36055f14c5..dea85faccf 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -1823,6 +1823,7 @@ S: Supported
 F: hw/vfio/*
 F: include/hw/vfio/
 F: docs/igd-assign.txt
+F: docs/devel/vfio-migration.rst
 
 vfio-ccw
 M: Cornelia Huck 
diff --git a/docs/devel/index.rst b/docs/devel/index.rst
index 6cf7e2d233..e6e4f7907e 100644
--- a/docs/devel/index.rst
+++ b/docs/devel/index.rst
@@ -42,3 +42,4 @@ Contents:
qom
block-coroutine-wrapper
multi-process
+   vfio-migration
diff --git a/docs/devel/vfio-migration.rst b/docs/devel/vfio-migration.rst
new file mode 100644
index 00..9ff6163c88
--- /dev/null
+++ b/docs/devel/vfio-migration.rst
@@ -0,0 +1,150 @@
+=
+VFIO device Migration
+=
+
+Migration of virtual machine involves saving the state for each device that
+the guest is running on source host and restoring this saved state on the
+destination host. This document details how saving and restoring of VFIO
+devices is done in QEMU.
+
+Migration of VFIO devices consists of two phases: the optional pre-copy phase,
+and the stop-and-copy phase. The pre-copy phase is iterative and allows to
+accommodate VFIO devices that have a large amount of data that needs to be
+transferred. The iterative pre-copy phase of migration allows for the guest to
+continue whilst the VFIO device state is transferred to the destination, this
+helps to reduce the total downtime of the VM. VFIO devices can choose to skip
+the pre-copy phase of migration by returning pending_bytes as zero during the
+pre-copy phase.
+
+A detailed description of the UAPI for VFIO device migration can be found in
+the comment for the ``vfio_device_migration_info`` structure in the header
+file linux-headers/linux/vfio.h.
+
+VFIO implements the device hooks for the iterative approach as follows:
+
+* A ``save_setup`` function that sets up the migration region and sets _SAVING
+  flag in the VFIO device state.
+
+* A ``load_setup`` function that sets up the migration region on the
+  destination and sets _RESUMING flag in the VFIO device state.
+
+* A ``save_live_pending`` function that reads pending_bytes from the vendor
+  driver, which indicates the amount of data that the vendor driver has yet to
+  save for the VFIO device.
+
+* A ``save_live_iterate`` function that reads the VFIO device's data from the
+  vendor driver through the migration region during iterative phase.
+
+* A ``save_state`` function to save the device config space if it is present.
+
+* A ``save_live_complete_precopy`` function that resets _RUNNING flag from the
+  VFIO device state and iteratively copies the remaining data for the VFIO
+  device until the vendor driver indicates that no data remains (pending bytes
+  is zero).
+
+* A ``load_state`` function that loads the config section and the data
+  sections that are generated by the save functions above
+
+* ``cleanup`` functions for both save and load that perform any migration
+  related cleanup, including unmapping the migration region
+
+
+The VFIO migration code uses a VM state change handler to change the VFIO
+device state when the VM state changes from running to not-running, and
+vice versa.
+
+Similarly, a migration state change handler is used to trigger a transition of
+the VFIO device state when certain changes of the migration state occur. For
+example, the VFIO device state is transitioned back to _RUNNING in case a
+migration failed or was canceled.
+
+System memory dirty pages tracking
+--
+
+A ``log_global_start`` and ``log_global_stop`` memory listener callback informs
+the VFIO IOMMU module to start and stop dirty page tracking. A ``log_sync``
+memory listener callback marks those system memory pages as dirty which are
+used for DMA by the VFIO device. The dirty pages bitmap is queried per
+container. All page

[Bug 1924912] [NEW] VirtIO drivers don't work on Windows: "GLib: Too many handles to wait for!" crash

[kleines Filmröllchen]

Public bug reported:

I ran SerenityOS  out of WSL2
with native Windows QEMU. The system runs fine on the Linux QEMU (with
Windows X-Server). However, with Windows QEMU I get a hard crash after
the following output:

```
[#0 colonel(0:0)]: Scheduler[0]: idle loop running
[init_stage2(2:2)]: PCI [:00:00:00] PCI::ID [8086:1237]
[init_stage2(2:2)]: PCI [:00:01:00] PCI::ID [8086:7000]
[init_stage2(2:2)]: PCI [:00:01:01] PCI::ID [8086:7010]
[init_stage2(2:2)]: PCI [:00:01:02] PCI::ID [8086:7020]
[init_stage2(2:2)]: PCI [:00:01:03] PCI::ID [8086:7113]
[init_stage2(2:2)]: PCI [:00:02:00] PCI::ID [1234:]
[init_stage2(2:2)]: PCI [:00:03:00] PCI::ID [8086:2922]
[init_stage2(2:2)]: PCI [:00:04:00] PCI::ID [1af4:1003]
[init_stage2(2:2)]: PCI [:00:05:00] PCI::ID [1af4:1005]
[init_stage2(2:2)]: PCI [:00:06:00] PCI::ID [8086:100e]
[#0 init_stage2(2:2)]: BXVGA: framebuffer @ P0xf800
[#0 init_stage2(2:2)]: BXVGADevice resolution set to 1024x768 (pitch=4096)
[init_stage2(2:2)]: UHCI: Controller found PCI::ID [8086:7020] @ PCI 
[:00:01:02]
[init_stage2(2:2)]: UHCI: I/O base IO c080
[init_stage2(2:2)]: UHCI: Interrupt line: 11
[#0 init_stage2(2:2)]: UHCI: Allocated framelist at physical address P0x00e4
[#0 init_stage2(2:2)]: UHCI: Framelist is at virtual address V0xc115d000
[#0 init_stage2(2:2)]: UHCI: QH(0xc115f000) @ 14946304: link_ptr=14946338, 
element_link_ptr=1
[#0 init_stage2(2:2)]: UHCI: QH(0xc115f020) @ 14946336: link_ptr=14946370, 
element_link_ptr=1
[#0 init_stage2(2:2)]: UHCI: QH(0xc115f040) @ 14946368: link_ptr=14946402, 
element_link_ptr=1
[#0 init_stage2(2:2)]: UHCI: QH(0xc115f060) @ 14946400: link_ptr=14946434, 
element_link_ptr=1
[#0 init_stage2(2:2)]: UHCI: QH(0xc115f080) @ 14946432: link_ptr=14958593, 
element_link_ptr=1
[#0 init_stage2(2:2)]: UHCI: Reset completed
[#0 init_stage2(2:2)]: UHCI: Started
[#0 init_stage2(2:2)]: DMIExpose: SMBIOS 32bit Entry point @ P0x000f5870
[#0 init_stage2(2:2)]: DMIExpose: Data table @ P0x000f5890
[#0 init_stage2(2:2)]: VirtIOConsole: Found @ PCI [:00:04:00]
[#0 init_stage2(2:2)]: Trying to unregister unused handler (?)
[#0 init_stage2(2:2)]: VirtIOConsole: Multi port is not yet supported!
[#0 init_stage2(2:2)]: VirtIOConsole: cols: 0, rows: 0, max nr ports 0
qemu-system-i386.exe: warning: GLib: Too many handles to wait for!
```

The lines starting with [ are SerenityOS output; QEMU warns "GLib: Too
many handles to wait for!" and crashes right after (can't even Ctrl-C in
the WSL command line, force-close in Windows necessary). A window is
still spawned but as the OS already switched out of text mode, just a
black screen is visible as QEMU crashes.

I first thought this to be an issue with SerenityOS and reported it over
there: . The kernel
devs pointed out that this seems to be a VirtIO driver/device issue on
the Windows build of QEMU, because the Serenity kernel tries to
initialize VirtIO devices which apparently crashes QEMU. There will be
mitigations from the SerenityOS side (by allowing to disable VirtIO on
boot) but it would of course be great if QEMU handled this properly.

Version info: Both QEMU 6.0.0-rc3 and 5.2.0 exhibit this issue. Windows
release is 20H2, WSL2 is running Debian 10.9. SerenityOS has no proper
version but it was reproduced on the most current commits as of
18/04/2021.

** Affects: qemu
 Importance: Undecided
 Status: New


** Tags: windows

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Title:
  VirtIO drivers don't work on Windows: "GLib: Too many handles to wait
  for!" crash

Status in QEMU:
  New

Bug description:
  I ran SerenityOS  out of WSL2
  with native Windows QEMU. The system runs fine on the Linux QEMU (with
  Windows X-Server). However, with Windows QEMU I get a hard crash after
  the following output:

  ```
  [#0 colonel(0:0)]: Scheduler[0]: idle loop running
  [init_stage2(2:2)]: PCI [:00:00:00] PCI::ID [8086:1237]
  [init_stage2(2:2)]: PCI [:00:01:00] PCI::ID [8086:7000]
  [init_stage2(2:2)]: PCI [:00:01:01] PCI::ID [8086:7010]
  [init_stage2(2:2)]: PCI [:00:01:02] PCI::ID [8086:7020]
  [init_stage2(2:2)]: PCI [:00:01:03] PCI::ID [8086:7113]
  [init_stage2(2:2)]: PCI [:00:02:00] PCI::ID [1234:]
  [init_stage2(2:2)]: PCI [:00:03:00] PCI::ID [8086:2922]
  [init_stage2(2:2)]: PCI [:00:04:00] PCI::ID [1af4:1003]
  [init_stage2(2:2)]: PCI [:00:05:00] PCI::ID [1af4:1005]
  [init_stage2(2:2)]: PCI [:00:06:00] PCI::ID [8086:100e]
  [#0 init_stage2(2:2)]: BXVGA: framebuffer @ P0xf800
  [#0 init_stage2(2:2)]: BXVGADevice resolution set to 1024x768 (pitch=4096)
  [init_stage2(2:2)]: UHCI: Controller found PCI::ID [8086:7020] @ PCI 
[:00:01:02]
  [init_stage2(2:2)]: UHCI: I/O base IO c0

[Bug 1924914] [NEW] Running sway in a QEMU VM results in a GPU hang of the guest (virtio-gpu driver)

[Diego Viola]

Public bug reported:

System is Arch Linux (guest and host OS).

Problem:

Basically, when using sway on a guest and running certain applications
via Xwayland (on the guest), the GUI will freeze and won't be usable
anymore, I can still ssh to the guest and run commands.

This is the command I use to run my guest:

qemu-system-x86_64 -enable-kvm -cdrom
~/Downloads/linux/archlinux/archlinux-2021.04.01-x86_64.iso -m 4G -vga
virtio -nic user,hostfwd=tcp::10022-:22

This doesn't happen when I use X with i3-wm.

** Affects: qemu
 Importance: Undecided
 Status: New

** Attachment added: "dmesg of the guest VM when the crash occurs"
   
https://bugs.launchpad.net/bugs/1924914/+attachment/5489500/+files/dmesg-sway-qemu-crash

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Title:
  Running sway in a QEMU VM results in a GPU hang of the guest (virtio-
  gpu driver)

Status in QEMU:
  New

Bug description:
  System is Arch Linux (guest and host OS).

  Problem:

  Basically, when using sway on a guest and running certain applications
  via Xwayland (on the guest), the GUI will freeze and won't be usable
  anymore, I can still ssh to the guest and run commands.

  This is the command I use to run my guest:

  qemu-system-x86_64 -enable-kvm -cdrom
  ~/Downloads/linux/archlinux/archlinux-2021.04.01-x86_64.iso -m 4G -vga
  virtio -nic user,hostfwd=tcp::10022-:22

  This doesn't happen when I use X with i3-wm.

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[Bug 1924912] Re: VirtIO drivers don't work on Windows: "GLib: Too many handles to wait for!" crash

[Stefan Weil]

Did you build your own Windows binary based on the official sources? Or
did you use a precompiled binary? If yes, which one?

Please describe the exact steps to reproduce the issue.

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Title:
  VirtIO drivers don't work on Windows: "GLib: Too many handles to wait
  for!" crash

Status in QEMU:
  New

Bug description:
  I ran SerenityOS  out of WSL2
  with native Windows QEMU. The system runs fine on the Linux QEMU (with
  Windows X-Server). However, with Windows QEMU I get a hard crash after
  the following output:

  ```
  [#0 colonel(0:0)]: Scheduler[0]: idle loop running
  [init_stage2(2:2)]: PCI [:00:00:00] PCI::ID [8086:1237]
  [init_stage2(2:2)]: PCI [:00:01:00] PCI::ID [8086:7000]
  [init_stage2(2:2)]: PCI [:00:01:01] PCI::ID [8086:7010]
  [init_stage2(2:2)]: PCI [:00:01:02] PCI::ID [8086:7020]
  [init_stage2(2:2)]: PCI [:00:01:03] PCI::ID [8086:7113]
  [init_stage2(2:2)]: PCI [:00:02:00] PCI::ID [1234:]
  [init_stage2(2:2)]: PCI [:00:03:00] PCI::ID [8086:2922]
  [init_stage2(2:2)]: PCI [:00:04:00] PCI::ID [1af4:1003]
  [init_stage2(2:2)]: PCI [:00:05:00] PCI::ID [1af4:1005]
  [init_stage2(2:2)]: PCI [:00:06:00] PCI::ID [8086:100e]
  [#0 init_stage2(2:2)]: BXVGA: framebuffer @ P0xf800
  [#0 init_stage2(2:2)]: BXVGADevice resolution set to 1024x768 (pitch=4096)
  [init_stage2(2:2)]: UHCI: Controller found PCI::ID [8086:7020] @ PCI 
[:00:01:02]
  [init_stage2(2:2)]: UHCI: I/O base IO c080
  [init_stage2(2:2)]: UHCI: Interrupt line: 11
  [#0 init_stage2(2:2)]: UHCI: Allocated framelist at physical address 
P0x00e4
  [#0 init_stage2(2:2)]: UHCI: Framelist is at virtual address V0xc115d000
  [#0 init_stage2(2:2)]: UHCI: QH(0xc115f000) @ 14946304: link_ptr=14946338, 
element_link_ptr=1
  [#0 init_stage2(2:2)]: UHCI: QH(0xc115f020) @ 14946336: link_ptr=14946370, 
element_link_ptr=1
  [#0 init_stage2(2:2)]: UHCI: QH(0xc115f040) @ 14946368: link_ptr=14946402, 
element_link_ptr=1
  [#0 init_stage2(2:2)]: UHCI: QH(0xc115f060) @ 14946400: link_ptr=14946434, 
element_link_ptr=1
  [#0 init_stage2(2:2)]: UHCI: QH(0xc115f080) @ 14946432: link_ptr=14958593, 
element_link_ptr=1
  [#0 init_stage2(2:2)]: UHCI: Reset completed
  [#0 init_stage2(2:2)]: UHCI: Started
  [#0 init_stage2(2:2)]: DMIExpose: SMBIOS 32bit Entry point @ P0x000f5870
  [#0 init_stage2(2:2)]: DMIExpose: Data table @ P0x000f5890
  [#0 init_stage2(2:2)]: VirtIOConsole: Found @ PCI [:00:04:00]
  [#0 init_stage2(2:2)]: Trying to unregister unused handler (?)
  [#0 init_stage2(2:2)]: VirtIOConsole: Multi port is not yet supported!
  [#0 init_stage2(2:2)]: VirtIOConsole: cols: 0, rows: 0, max nr ports 0
  qemu-system-i386.exe: warning: GLib: Too many handles to wait for!
  ```

  The lines starting with [ are SerenityOS output; QEMU warns "GLib: Too
  many handles to wait for!" and crashes right after (can't even Ctrl-C
  in the WSL command line, force-close in Windows necessary). A window
  is still spawned but as the OS already switched out of text mode, just
  a black screen is visible as QEMU crashes.

  I first thought this to be an issue with SerenityOS and reported it
  over there: . The
  kernel devs pointed out that this seems to be a VirtIO driver/device
  issue on the Windows build of QEMU, because the Serenity kernel tries
  to initialize VirtIO devices which apparently crashes QEMU. There will
  be mitigations from the SerenityOS side (by allowing to disable VirtIO
  on boot) but it would of course be great if QEMU handled this
  properly.

  Version info: Both QEMU 6.0.0-rc3 and 5.2.0 exhibit this issue.
  Windows release is 20H2, WSL2 is running Debian 10.9. SerenityOS has
  no proper version but it was reproduced on the most current commits as
  of 18/04/2021.

To manage notifications about this bug go to:
https://bugs.launchpad.net/qemu/+bug/1924912/+subscriptions

[Bug 1924914] Re: Running sway in a QEMU VM results in a GPU hang of the guest (virtio-gpu driver)

[Diego Viola]

I can't get it to happen with -vga qxl.

-- 
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Title:
  Running sway in a QEMU VM results in a GPU hang of the guest (virtio-
  gpu driver)

Status in QEMU:
  New

Bug description:
  System is Arch Linux (guest and host OS).

  Problem:

  Basically, when using sway on a guest and running certain applications
  via Xwayland (on the guest), the GUI will freeze and won't be usable
  anymore, I can still ssh to the guest and run commands.

  This is the command I use to run my guest:

  qemu-system-x86_64 -enable-kvm -cdrom
  ~/Downloads/linux/archlinux/archlinux-2021.04.01-x86_64.iso -m 4G -vga
  virtio -nic user,hostfwd=tcp::10022-:22

  This doesn't happen when I use X with i3-wm.

To manage notifications about this bug go to:
https://bugs.launchpad.net/qemu/+bug/1924914/+subscriptions

[Bug 1924912] Re: VirtIO drivers don't work on Windows: "GLib: Too many handles to wait for!" crash

[kleines Filmröllchen]

I used the pre-built binaries with the versions described above. I did
not change any install options so this can be reproduced after using the
official install binaries for each version.

-- 
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Title:
  VirtIO drivers don't work on Windows: "GLib: Too many handles to wait
  for!" crash

Status in QEMU:
  New

Bug description:
  I ran SerenityOS  out of WSL2
  with native Windows QEMU. The system runs fine on the Linux QEMU (with
  Windows X-Server). However, with Windows QEMU I get a hard crash after
  the following output:

  ```
  [#0 colonel(0:0)]: Scheduler[0]: idle loop running
  [init_stage2(2:2)]: PCI [:00:00:00] PCI::ID [8086:1237]
  [init_stage2(2:2)]: PCI [:00:01:00] PCI::ID [8086:7000]
  [init_stage2(2:2)]: PCI [:00:01:01] PCI::ID [8086:7010]
  [init_stage2(2:2)]: PCI [:00:01:02] PCI::ID [8086:7020]
  [init_stage2(2:2)]: PCI [:00:01:03] PCI::ID [8086:7113]
  [init_stage2(2:2)]: PCI [:00:02:00] PCI::ID [1234:]
  [init_stage2(2:2)]: PCI [:00:03:00] PCI::ID [8086:2922]
  [init_stage2(2:2)]: PCI [:00:04:00] PCI::ID [1af4:1003]
  [init_stage2(2:2)]: PCI [:00:05:00] PCI::ID [1af4:1005]
  [init_stage2(2:2)]: PCI [:00:06:00] PCI::ID [8086:100e]
  [#0 init_stage2(2:2)]: BXVGA: framebuffer @ P0xf800
  [#0 init_stage2(2:2)]: BXVGADevice resolution set to 1024x768 (pitch=4096)
  [init_stage2(2:2)]: UHCI: Controller found PCI::ID [8086:7020] @ PCI 
[:00:01:02]
  [init_stage2(2:2)]: UHCI: I/O base IO c080
  [init_stage2(2:2)]: UHCI: Interrupt line: 11
  [#0 init_stage2(2:2)]: UHCI: Allocated framelist at physical address 
P0x00e4
  [#0 init_stage2(2:2)]: UHCI: Framelist is at virtual address V0xc115d000
  [#0 init_stage2(2:2)]: UHCI: QH(0xc115f000) @ 14946304: link_ptr=14946338, 
element_link_ptr=1
  [#0 init_stage2(2:2)]: UHCI: QH(0xc115f020) @ 14946336: link_ptr=14946370, 
element_link_ptr=1
  [#0 init_stage2(2:2)]: UHCI: QH(0xc115f040) @ 14946368: link_ptr=14946402, 
element_link_ptr=1
  [#0 init_stage2(2:2)]: UHCI: QH(0xc115f060) @ 14946400: link_ptr=14946434, 
element_link_ptr=1
  [#0 init_stage2(2:2)]: UHCI: QH(0xc115f080) @ 14946432: link_ptr=14958593, 
element_link_ptr=1
  [#0 init_stage2(2:2)]: UHCI: Reset completed
  [#0 init_stage2(2:2)]: UHCI: Started
  [#0 init_stage2(2:2)]: DMIExpose: SMBIOS 32bit Entry point @ P0x000f5870
  [#0 init_stage2(2:2)]: DMIExpose: Data table @ P0x000f5890
  [#0 init_stage2(2:2)]: VirtIOConsole: Found @ PCI [:00:04:00]
  [#0 init_stage2(2:2)]: Trying to unregister unused handler (?)
  [#0 init_stage2(2:2)]: VirtIOConsole: Multi port is not yet supported!
  [#0 init_stage2(2:2)]: VirtIOConsole: cols: 0, rows: 0, max nr ports 0
  qemu-system-i386.exe: warning: GLib: Too many handles to wait for!
  ```

  The lines starting with [ are SerenityOS output; QEMU warns "GLib: Too
  many handles to wait for!" and crashes right after (can't even Ctrl-C
  in the WSL command line, force-close in Windows necessary). A window
  is still spawned but as the OS already switched out of text mode, just
  a black screen is visible as QEMU crashes.

  I first thought this to be an issue with SerenityOS and reported it
  over there: . The
  kernel devs pointed out that this seems to be a VirtIO driver/device
  issue on the Windows build of QEMU, because the Serenity kernel tries
  to initialize VirtIO devices which apparently crashes QEMU. There will
  be mitigations from the SerenityOS side (by allowing to disable VirtIO
  on boot) but it would of course be great if QEMU handled this
  properly.

  Version info: Both QEMU 6.0.0-rc3 and 5.2.0 exhibit this issue.
  Windows release is 20H2, WSL2 is running Debian 10.9. SerenityOS has
  no proper version but it was reproduced on the most current commits as
  of 18/04/2021.

To manage notifications about this bug go to:
https://bugs.launchpad.net/qemu/+bug/1924912/+subscriptions

Re: [PATCH RFC] migration: warn about non-migratable configurations unless '--no-migration' was specified

[Peter Maydell]

On Thu, 15 Apr 2021 at 16:46, Vitaly Kuznetsov  wrote:
> When a migration blocker is added nothing is reported to the user,
> inability to migrate such guest may come as a late surprise. As a bare
> minimum, we can print a warning. To not pollute the output for those, who
> have no intention to migrate their guests, introduce '--no-migration'
> option which both block the migration and eliminates warning from

I'm not a fan. For a lot of people and configurations this
is going to be "add an extra complaint from QEMU to a previously
working configuration". We add too many of those already.

thanks
-- PMM

[PATCH 00/26] target/mips: Re-org to allow KVM-only builds

[Philippe Mathieu-Daudé]

TL;DR:

This series restrict TCG-specific objects by moving them to
the tcg/ subdir. Code is moved around to satisfy 3 cases:
{ generic sysemu / tcg sysemu / tcg user}.

Hi,

This series move the MIPS TCG files under target/mips/tcg/.
tcg/ is split into {sysemu and user}, and code common to
both user/sysemu is left under tcg/ root.

Non-user code is moved to sysemu/ (common to TCG and KVM).

- Patches 1 & 6 are Meson generic
- Patches 2 to 5 move generic symbols around to satisfly KVM linking
- Patch 8 introduces tcg-internal.h where we'll move TCG specific
  prototypes from the current big internal.h
- Patches 9-24 move code by topic (first user, then sysemu, then tcg)
- Patch 25 restrict TCG specific machines to TCG (to actually
  only build malta/loongson3-virt machines when restricted to KVM)
- Patch 26 finally add a CI job with "KVM-only" config:
  https://gitlab.com/philmd/qemu/-/jobs/1189874868 (12min 5sec)

Diffstat is not that bad, and many #ifdef'ry removed.

Please review,

Phil.

Based-on: <20210413081008.3409459-1-f4...@amsat.org>
  "exec: Remove accel/tcg/ from include paths"

Philippe Mathieu-Daudé (26):
  target/mips: Simplify meson TCG rules
  target/mips: Move IEEE rounding mode array to new source file
  target/mips: Move msa_reset() to new source file
  target/mips: Make CPU/FPU regnames[] arrays global
  target/mips: Restrict mips_cpu_dump_state() to cpu.c
  target/mips: Extract load/store helpers to ldst_helper.c
  meson: Introduce meson_user_arch source set for arch-specific
user-mode
  target/mips: Introduce tcg-internal.h for TCG specific declarations
  target/mips: Add simple user-mode mips_cpu_do_interrupt()
  target/mips: Add simple user-mode mips_cpu_tlb_fill()
  target/mips: Move cpu_signal_handler definition around
  target/mips: Move sysemu specific files under sysemu/ subfolder
  target/mips: Move code related to physical addressing to sysemu/phys.c
  target/mips: Move sysemu TCG-specific code to tcg/sysemu/ subfolder
  target/mips: Restrict mmu_init() to TCG
  target/mips: Move tlb_helper.c to tcg/sysemu/
  target/mips: Restrict CPUMIPSTLBContext::map_address() handlers scope
  target/mips: Move Special opcodes to tcg/sysemu/special_helper.c
  target/mips: Move helper_cache() to tcg/sysemu/special_helper.c
  target/mips: Move TLB management helpers to tcg/sysemu/tlb_helper.c
  target/mips: Move exception management code to exception.c
  target/mips: Move CP0 helpers to sysemu/cp0.c
  target/mips: Move helper.h -> tcg/helper.h.inc
  target/mips: Move TCG source files under tcg/ sub directory
  hw/mips: Restrict non-virtualized machines to TCG
  gitlab-ci: Add KVM mips64el cross-build jobs

 meson.build  |6 +
 target/mips/helper.h |  787 +---
 target/mips/internal.h   |   97 +-
 target/mips/tcg/tcg-internal.h   |   64 +
 target/mips/tcg/helper.h.inc |  613 +
 target/mips/{ => tcg}/msa_helper.h.inc   |0
 target/mips/tcg/sysemu_helper.h.inc  |  184 +++
 target/mips/{ => tcg}/mips32r6.decode|0
 target/mips/{ => tcg}/mips64r6.decode|0
 target/mips/{ => tcg}/msa32.decode   |0
 target/mips/{ => tcg}/msa64.decode   |0
 target/mips/{ => tcg}/tx79.decode|0
 target/mips/cpu.c|  307 ++---
 target/mips/fpu.c|   25 +
 target/mips/msa.c|   60 +
 target/mips/op_helper.c  | 1210 --
 target/mips/{ => sysemu}/addr.c  |0
 target/mips/sysemu/cp0.c |  123 ++
 target/mips/{ => sysemu}/cp0_timer.c |0
 target/mips/{ => sysemu}/machine.c   |0
 target/mips/sysemu/physaddr.c|  257 
 target/mips/{ => tcg}/dsp_helper.c   |0
 target/mips/tcg/exception.c  |  169 +++
 target/mips/{ => tcg}/fpu_helper.c   |8 -
 target/mips/tcg/ldst_helper.c|  304 +
 target/mips/{ => tcg}/lmmi_helper.c  |0
 target/mips/{ => tcg}/msa_helper.c   |   36 -
 target/mips/{ => tcg}/msa_translate.c|0
 target/mips/{ => tcg}/mxu_translate.c|0
 target/mips/tcg/op_helper.c  |  421 ++
 target/mips/{ => tcg}/rel6_translate.c   |0
 target/mips/{ => tcg/sysemu}/cp0_helper.c|0
 target/mips/{ => tcg/sysemu}/mips-semi.c |0
 target/mips/tcg/sysemu/special_helper.c  |  183 +++
 target/mips/{ => tcg/sysemu}/tlb_helper.c|  612 +
 target/mips/{ => tcg}/translate.c|   91 --
 target/mips/{ => tcg}/translate_addr_const.c |0
 target/mips/{ => tcg}/tx79_translate.c   |0
 target/mips/{ => tcg}/txx9_translate.c   |0
 target/mips/tcg/user/helper.c|   64 +
 target/mips/tcg/user/stubs.c |   29 +
 .gitlab-ci.d/crossbuilds.yml  

[PATCH 01/26] target/mips: Simplify meson TCG rules

[Philippe Mathieu-Daudé]

We already have the mips_tcg_ss source set for TCG-specific files,
use it for mxu_translate.c and tx79_translate.c to simplify a bit.

Signed-off-by: Philippe Mathieu-Daudé 
---
 target/mips/meson.build | 5 ++---
 1 file changed, 2 insertions(+), 3 deletions(-)

diff --git a/target/mips/meson.build b/target/mips/meson.build
index 3b131c4a7f6..3733d1200f7 100644
--- a/target/mips/meson.build
+++ b/target/mips/meson.build
@@ -26,10 +26,9 @@
   'translate_addr_const.c',
   'txx9_translate.c',
 ))
-mips_ss.add(when: ['CONFIG_TCG', 'TARGET_MIPS64'], if_true: files(
+mips_tcg_ss.add(when: 'TARGET_MIPS64', if_true: files(
   'tx79_translate.c',
-))
-mips_tcg_ss.add(when: 'TARGET_MIPS64', if_false: files(
+), if_false: files(
   'mxu_translate.c',
 ))
 
-- 
2.26.3

Re: [PULL 0/7] queue of proposed rc4 fixes

[Alex Bennée]

Peter Maydell  writes:

> This pullreq contains fixes for the remaining "not fixed yet" issues
> in the 6.0 Planning page:
>  * Fix compile failures of C++ files with new glib headers
>  * mps3-an547: Use correct Cortex-M55 CPU and don't disable its FPU
>  * accel/tcg: Fix assertion failure executing from non-RAM with -icount
>
> None of these are 100% rc4-worthy on their own, but taken all together
> I think they justify rolling another release candidate.

If you are rolling it would be nice to include:

  checkpatch: Fix use of uninitialized value
  Message-Id: <161786467973.295167.5612704777283969903.st...@bahia.lan>

just to avoid the messy warning in the CI checkpatch check.

>
> thanks
> -- PMM
>
> The following changes since commit 8fe9f1f891eff4e37f82622b7480ee748bf4af74:
>
>   Update version for v6.0.0-rc3 release (2021-04-14 22:06:18 +0100)
>
> are available in the Git repository at:
>
>   https://git.linaro.org/people/pmaydell/qemu-arm.git 
> tags/pull-target-arm-20210417
>
> for you to fetch changes up to 277aed998ac2cd3649bf0e13b22f47769519eb61:
>
>   accel/tcg: avoid re-translating one-shot instructions (2021-04-17 18:51:14 
> +0100)
>
> 
> Fixes for rc4:
>  * Fix compile failures of C++ files with new glib headers
>  * mps3-an547: Use correct Cortex-M55 CPU and don't disable its FPU
>  * accel/tcg: Fix assertion failure executing from non-RAM with -icount
>
> 
> Alex Bennée (2):
>   target/arm: drop CF_LAST_IO/dc->condjump check
>   accel/tcg: avoid re-translating one-shot instructions
>
> Paolo Bonzini (2):
>   osdep: include glib-compat.h before other QEMU headers
>   osdep: protect qemu/osdep.h with extern "C"
>
> Peter Maydell (3):
>   include/qemu/osdep.h: Move system includes to top
>   hw/arm/armsse: Give SSE-300 its own Property array
>   hw/arm/armsse: Make SSE-300 use Cortex-M55
>
>  include/qemu/compiler.h   |  6 ++
>  include/qemu/osdep.h  | 38 +-
>  accel/tcg/translate-all.c |  2 +-
>  hw/arm/armsse.c   | 24 +++-
>  target/arm/translate.c|  5 -
>  disas/arm-a64.cc  |  2 +-
>  disas/nanomips.cpp|  2 +-
>  7 files changed, 57 insertions(+), 22 deletions(-)


-- 
Alex Bennée

[PATCH 04/26] target/mips: Make CPU/FPU regnames[] arrays global

[Philippe Mathieu-Daudé]

The CPU/FPU regnames[] arrays is used in mips_tcg_init() and
mips_cpu_dump_state(), which while being in translate.c is
not specific to TCG.

To be able to move mips_cpu_dump_state() to cpu.c, which is
compiled for all accelerator, we need to make the regnames[]
arrays global to target/mips/ by declaring them in "internal.h".

Signed-off-by: Philippe Mathieu-Daudé 
---
 target/mips/internal.h  |  3 +++
 target/mips/cpu.c   |  7 +++
 target/mips/fpu.c   |  7 +++
 target/mips/translate.c | 14 --
 4 files changed, 17 insertions(+), 14 deletions(-)

diff --git a/target/mips/internal.h b/target/mips/internal.h
index 99264b8bf6a..a8644f754a6 100644
--- a/target/mips/internal.h
+++ b/target/mips/internal.h
@@ -71,6 +71,9 @@ struct mips_def_t {
 int32_t SAARP;
 };
 
+extern const char * const regnames[32];
+extern const char * const fregnames[32];
+
 extern const struct mips_def_t mips_defs[];
 extern const int mips_defs_number;
 
diff --git a/target/mips/cpu.c b/target/mips/cpu.c
index dce1e166bde..f354d18aec4 100644
--- a/target/mips/cpu.c
+++ b/target/mips/cpu.c
@@ -35,6 +35,13 @@
 #include "qapi/qapi-commands-machine-target.h"
 #include "fpu_helper.h"
 
+const char * const regnames[32] = {
+"r0", "at", "v0", "v1", "a0", "a1", "a2", "a3",
+"t0", "t1", "t2", "t3", "t4", "t5", "t6", "t7",
+"s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7",
+"t8", "t9", "k0", "k1", "gp", "sp", "s8", "ra",
+};
+
 #if !defined(CONFIG_USER_ONLY)
 
 /* Called for updates to CP0_Status.  */
diff --git a/target/mips/fpu.c b/target/mips/fpu.c
index 39a2f7fd22e..1447dba3fa3 100644
--- a/target/mips/fpu.c
+++ b/target/mips/fpu.c
@@ -16,3 +16,10 @@ const FloatRoundMode ieee_rm[4] = {
 float_round_up,
 float_round_down
 };
+
+const char * const fregnames[32] = {
+"f0",  "f1",  "f2",  "f3",  "f4",  "f5",  "f6",  "f7",
+"f8",  "f9",  "f10", "f11", "f12", "f13", "f14", "f15",
+"f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23",
+"f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31",
+};
diff --git a/target/mips/translate.c b/target/mips/translate.c
index 71fa5ec1973..f99d4d4016d 100644
--- a/target/mips/translate.c
+++ b/target/mips/translate.c
@@ -1267,13 +1267,6 @@ TCGv_i64 fpu_f64[32];
 #define DISAS_STOP   DISAS_TARGET_0
 #define DISAS_EXIT   DISAS_TARGET_1
 
-static const char * const regnames[] = {
-"r0", "at", "v0", "v1", "a0", "a1", "a2", "a3",
-"t0", "t1", "t2", "t3", "t4", "t5", "t6", "t7",
-"s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7",
-"t8", "t9", "k0", "k1", "gp", "sp", "s8", "ra",
-};
-
 static const char * const regnames_HI[] = {
 "HI0", "HI1", "HI2", "HI3",
 };
@@ -1282,13 +1275,6 @@ static const char * const regnames_LO[] = {
 "LO0", "LO1", "LO2", "LO3",
 };
 
-static const char * const fregnames[] = {
-"f0",  "f1",  "f2",  "f3",  "f4",  "f5",  "f6",  "f7",
-"f8",  "f9",  "f10", "f11", "f12", "f13", "f14", "f15",
-"f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23",
-"f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31",
-};
-
 /* General purpose registers moves. */
 void gen_load_gpr(TCGv t, int reg)
 {
-- 
2.26.3

[PATCH 03/26] target/mips: Move msa_reset() to new source file

[Philippe Mathieu-Daudé]

mips_cpu_reset() is used by all accelerators, and calls
msa_reset(), which is defined in msa_helper.c.

Beside msa_reset(), the rest of msa_helper.c is only useful
to the TCG accelerator. To be able to restrict this helper
file to TCG, we need to move msa_reset() out of it.

Signed-off-by: Philippe Mathieu-Daudé 
---
 target/mips/msa.c| 60 
 target/mips/msa_helper.c | 36 
 target/mips/meson.build  |  1 +
 3 files changed, 61 insertions(+), 36 deletions(-)
 create mode 100644 target/mips/msa.c

diff --git a/target/mips/msa.c b/target/mips/msa.c
new file mode 100644
index 000..61f1a9a5936
--- /dev/null
+++ b/target/mips/msa.c
@@ -0,0 +1,60 @@
+/*
+ * MIPS SIMD Architecture Module Instruction emulation helpers for QEMU.
+ *
+ * Copyright (c) 2014 Imagination Technologies
+ *
+ * This library is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU Lesser General Public
+ * License as published by the Free Software Foundation; either
+ * version 2.1 of the License, or (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
+ * Lesser General Public License for more details.
+ *
+ * You should have received a copy of the GNU Lesser General Public
+ * License along with this library; if not, see .
+ */
+
+#include "qemu/osdep.h"
+#include "cpu.h"
+#include "internal.h"
+#include "fpu/softfloat.h"
+#include "fpu_helper.h"
+
+void msa_reset(CPUMIPSState *env)
+{
+if (!ase_msa_available(env)) {
+return;
+}
+
+#ifdef CONFIG_USER_ONLY
+/* MSA access enabled */
+env->CP0_Config5 |= 1 << CP0C5_MSAEn;
+env->CP0_Status |= (1 << CP0St_CU1) | (1 << CP0St_FR);
+#endif
+
+/*
+ * MSA CSR:
+ * - non-signaling floating point exception mode off (NX bit is 0)
+ * - Cause, Enables, and Flags are all 0
+ * - round to nearest / ties to even (RM bits are 0)
+ */
+env->active_tc.msacsr = 0;
+
+restore_msa_fp_status(env);
+
+/* tininess detected after rounding.*/
+set_float_detect_tininess(float_tininess_after_rounding,
+  &env->active_tc.msa_fp_status);
+
+/* clear float_status exception flags */
+set_float_exception_flags(0, &env->active_tc.msa_fp_status);
+
+/* clear float_status nan mode */
+set_default_nan_mode(0, &env->active_tc.msa_fp_status);
+
+/* set proper signanling bit meaning ("1" means "quiet") */
+set_snan_bit_is_one(0, &env->active_tc.msa_fp_status);
+}
diff --git a/target/mips/msa_helper.c b/target/mips/msa_helper.c
index 4caefe29ad7..04af54f66d1 100644
--- a/target/mips/msa_helper.c
+++ b/target/mips/msa_helper.c
@@ -8595,39 +8595,3 @@ void helper_msa_st_d(CPUMIPSState *env, uint32_t wd,
 cpu_stq_data(env, addr + (1 << DF_DOUBLE), pwd->d[1]);
 #endif
 }
-
-void msa_reset(CPUMIPSState *env)
-{
-if (!ase_msa_available(env)) {
-return;
-}
-
-#ifdef CONFIG_USER_ONLY
-/* MSA access enabled */
-env->CP0_Config5 |= 1 << CP0C5_MSAEn;
-env->CP0_Status |= (1 << CP0St_CU1) | (1 << CP0St_FR);
-#endif
-
-/*
- * MSA CSR:
- * - non-signaling floating point exception mode off (NX bit is 0)
- * - Cause, Enables, and Flags are all 0
- * - round to nearest / ties to even (RM bits are 0)
- */
-env->active_tc.msacsr = 0;
-
-restore_msa_fp_status(env);
-
-/* tininess detected after rounding.*/
-set_float_detect_tininess(float_tininess_after_rounding,
-  &env->active_tc.msa_fp_status);
-
-/* clear float_status exception flags */
-set_float_exception_flags(0, &env->active_tc.msa_fp_status);
-
-/* clear float_status nan mode */
-set_default_nan_mode(0, &env->active_tc.msa_fp_status);
-
-/* set proper signanling bit meaning ("1" means "quiet") */
-set_snan_bit_is_one(0, &env->active_tc.msa_fp_status);
-}
diff --git a/target/mips/meson.build b/target/mips/meson.build
index 5fcb211ca9a..daf5f1d55bc 100644
--- a/target/mips/meson.build
+++ b/target/mips/meson.build
@@ -11,6 +11,7 @@
   'cpu.c',
   'fpu.c',
   'gdbstub.c',
+  'msa.c',
 ))
 mips_tcg_ss = ss.source_set()
 mips_tcg_ss.add(gen)
-- 
2.26.3

[PATCH 02/26] target/mips: Move IEEE rounding mode array to new source file

[Philippe Mathieu-Daudé]

restore_msa_fp_status() is declared inlined in fpu_helper.h,
and uses the ieee_rm[] array. Therefore any code calling
restore_msa_fp_status() must have access to this ieee_rm[] array.

kvm_mips_get_fpu_registers(), which is in target/mips/kvm.c,
calls restore_msa_fp_status.

Except this tiny array, the rest of fpu_helper.c is only useful
for the TCG accelerator.

To be able to restrict fpu_helper.c to TCG, we need to move the
ieee_rm[] array to a new source file.

Signed-off-by: Philippe Mathieu-Daudé 
---
 target/mips/fpu.c| 18 ++
 target/mips/fpu_helper.c |  8 
 target/mips/meson.build  |  1 +
 3 files changed, 19 insertions(+), 8 deletions(-)
 create mode 100644 target/mips/fpu.c

diff --git a/target/mips/fpu.c b/target/mips/fpu.c
new file mode 100644
index 000..39a2f7fd22e
--- /dev/null
+++ b/target/mips/fpu.c
@@ -0,0 +1,18 @@
+/*
+ * Helpers for emulation of FPU-related MIPS instructions.
+ *
+ *  Copyright (C) 2004-2005  Jocelyn Mayer
+ *
+ * SPDX-License-Identifier: LGPL-2.1-or-later
+ */
+#include "qemu/osdep.h"
+#include "fpu/softfloat-helpers.h"
+#include "fpu_helper.h"
+
+/* convert MIPS rounding mode in FCR31 to IEEE library */
+const FloatRoundMode ieee_rm[4] = {
+float_round_nearest_even,
+float_round_to_zero,
+float_round_up,
+float_round_down
+};
diff --git a/target/mips/fpu_helper.c b/target/mips/fpu_helper.c
index 6dd853259e2..8ce56ed7c81 100644
--- a/target/mips/fpu_helper.c
+++ b/target/mips/fpu_helper.c
@@ -38,14 +38,6 @@
 #define FP_TO_INT32_OVERFLOW 0x7fff
 #define FP_TO_INT64_OVERFLOW 0x7fffULL
 
-/* convert MIPS rounding mode in FCR31 to IEEE library */
-const FloatRoundMode ieee_rm[4] = {
-float_round_nearest_even,
-float_round_to_zero,
-float_round_up,
-float_round_down
-};
-
 target_ulong helper_cfc1(CPUMIPSState *env, uint32_t reg)
 {
 target_ulong arg1 = 0;
diff --git a/target/mips/meson.build b/target/mips/meson.build
index 3733d1200f7..5fcb211ca9a 100644
--- a/target/mips/meson.build
+++ b/target/mips/meson.build
@@ -9,6 +9,7 @@
 mips_ss = ss.source_set()
 mips_ss.add(files(
   'cpu.c',
+  'fpu.c',
   'gdbstub.c',
 ))
 mips_tcg_ss = ss.source_set()
-- 
2.26.3

[PATCH 05/26] target/mips: Restrict mips_cpu_dump_state() to cpu.c

[Philippe Mathieu-Daudé]

As mips_cpu_dump_state() is only used once to initialize the
CPUClass::dump_state handler, we can move it to cpu.c to keep
it symbol local.
Beside, this handler is used by all accelerators, while the
translate.c file targets TCG.

Signed-off-by: Philippe Mathieu-Daudé 
---
 target/mips/internal.h  |  1 -
 target/mips/cpu.c   | 77 +
 target/mips/translate.c | 77 -
 3 files changed, 77 insertions(+), 78 deletions(-)

diff --git a/target/mips/internal.h b/target/mips/internal.h
index a8644f754a6..1c5674935aa 100644
--- a/target/mips/internal.h
+++ b/target/mips/internal.h
@@ -79,7 +79,6 @@ extern const int mips_defs_number;
 
 void mips_cpu_do_interrupt(CPUState *cpu);
 bool mips_cpu_exec_interrupt(CPUState *cpu, int int_req);
-void mips_cpu_dump_state(CPUState *cpu, FILE *f, int flags);
 hwaddr mips_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr);
 int mips_cpu_gdb_read_register(CPUState *cpu, GByteArray *buf, int reg);
 int mips_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg);
diff --git a/target/mips/cpu.c b/target/mips/cpu.c
index f354d18aec4..ac38a3262ca 100644
--- a/target/mips/cpu.c
+++ b/target/mips/cpu.c
@@ -145,6 +145,83 @@ void cpu_mips_store_cause(CPUMIPSState *env, target_ulong 
val)
 
 #endif /* !CONFIG_USER_ONLY */
 
+static void fpu_dump_state(CPUMIPSState *env, FILE * f, int flags)
+{
+int i;
+int is_fpu64 = !!(env->hflags & MIPS_HFLAG_F64);
+
+#define printfpr(fp)\
+do {\
+if (is_fpu64)   \
+qemu_fprintf(f, "w:%08x d:%016" PRIx64  \
+ " fd:%13g fs:%13g psu: %13g\n",\
+ (fp)->w[FP_ENDIAN_IDX], (fp)->d,   \
+ (double)(fp)->fd,  \
+ (double)(fp)->fs[FP_ENDIAN_IDX],   \
+ (double)(fp)->fs[!FP_ENDIAN_IDX]); \
+else {  \
+fpr_t tmp;  \
+tmp.w[FP_ENDIAN_IDX] = (fp)->w[FP_ENDIAN_IDX];  \
+tmp.w[!FP_ENDIAN_IDX] = ((fp) + 1)->w[FP_ENDIAN_IDX];   \
+qemu_fprintf(f, "w:%08x d:%016" PRIx64  \
+ " fd:%13g fs:%13g psu:%13g\n", \
+ tmp.w[FP_ENDIAN_IDX], tmp.d,   \
+ (double)tmp.fd,\
+ (double)tmp.fs[FP_ENDIAN_IDX], \
+ (double)tmp.fs[!FP_ENDIAN_IDX]);   \
+}   \
+} while (0)
+
+
+qemu_fprintf(f,
+ "CP1 FCR0 0x%08x  FCR31 0x%08x  SR.FR %d  fp_status 0x%02x\n",
+ env->active_fpu.fcr0, env->active_fpu.fcr31, is_fpu64,
+ get_float_exception_flags(&env->active_fpu.fp_status));
+for (i = 0; i < 32; (is_fpu64) ? i++ : (i += 2)) {
+qemu_fprintf(f, "%3s: ", fregnames[i]);
+printfpr(&env->active_fpu.fpr[i]);
+}
+
+#undef printfpr
+}
+
+static void mips_cpu_dump_state(CPUState *cs, FILE *f, int flags)
+{
+MIPSCPU *cpu = MIPS_CPU(cs);
+CPUMIPSState *env = &cpu->env;
+int i;
+
+qemu_fprintf(f, "pc=0x" TARGET_FMT_lx " HI=0x" TARGET_FMT_lx
+ " LO=0x" TARGET_FMT_lx " ds %04x "
+ TARGET_FMT_lx " " TARGET_FMT_ld "\n",
+ env->active_tc.PC, env->active_tc.HI[0], env->active_tc.LO[0],
+ env->hflags, env->btarget, env->bcond);
+for (i = 0; i < 32; i++) {
+if ((i & 3) == 0) {
+qemu_fprintf(f, "GPR%02d:", i);
+}
+qemu_fprintf(f, " %s " TARGET_FMT_lx,
+ regnames[i], env->active_tc.gpr[i]);
+if ((i & 3) == 3) {
+qemu_fprintf(f, "\n");
+}
+}
+
+qemu_fprintf(f, "CP0 Status  0x%08x Cause   0x%08x EPC0x"
+ TARGET_FMT_lx "\n",
+ env->CP0_Status, env->CP0_Cause, env->CP0_EPC);
+qemu_fprintf(f, "Config0 0x%08x Config1 0x%08x LLAddr 0x%016"
+ PRIx64 "\n",
+ env->CP0_Config0, env->CP0_Config1, env->CP0_LLAddr);
+qemu_fprintf(f, "Config2 0x%08x Config3 0x%08x\n",
+ env->CP0_Config2, env->CP0_Config3);
+qemu_fprintf(f, "Config4 0x%08x Config5 0x%08x\n",
+ env->CP0_Config4, env->CP0_Config5);
+if ((flags & CPU_DUMP_FPU) && (env->hflags & MIPS_HFLAG_FPU)) {
+fpu_dump_state(env, f, flags);
+}
+}
+
 static const char * const excp_names[EXCP_LAST + 1] = {
 [EXCP_RESET] = "reset",
   

[PATCH 06/26] target/mips: Extract load/store helpers to ldst_helper.c

[Philippe Mathieu-Daudé]

Signed-off-by: Philippe Mathieu-Daudé 
---
 target/mips/ldst_helper.c | 304 ++
 target/mips/op_helper.c   | 274 --
 target/mips/meson.build   |   1 +
 3 files changed, 305 insertions(+), 274 deletions(-)
 create mode 100644 target/mips/ldst_helper.c

diff --git a/target/mips/ldst_helper.c b/target/mips/ldst_helper.c
new file mode 100644
index 000..3fbcc3509ab
--- /dev/null
+++ b/target/mips/ldst_helper.c
@@ -0,0 +1,304 @@
+/*
+ *  MIPS emulation load/store helpers for QEMU.
+ *
+ *  Copyright (c) 2004-2005 Jocelyn Mayer
+ *
+ * SPDX-License-Identifier: LGPL-2.1-or-later
+ *
+ * This library is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU Lesser General Public
+ * License as published by the Free Software Foundation; either
+ * version 2.1 of the License, or (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
+ * Lesser General Public License for more details.
+ *
+ * You should have received a copy of the GNU Lesser General Public
+ * License along with this library; if not, see .
+ *
+ */
+
+#include "qemu/osdep.h"
+#include "cpu.h"
+#include "exec/helper-proto.h"
+#include "exec/exec-all.h"
+#include "exec/memop.h"
+#include "internal.h"
+
+#ifndef CONFIG_USER_ONLY
+
+static inline hwaddr do_translate_address(CPUMIPSState *env,
+  target_ulong address,
+  MMUAccessType access_type,
+  uintptr_t retaddr)
+{
+hwaddr paddr;
+CPUState *cs = env_cpu(env);
+
+paddr = cpu_mips_translate_address(env, address, access_type);
+
+if (paddr == -1LL) {
+cpu_loop_exit_restore(cs, retaddr);
+} else {
+return paddr;
+}
+}
+
+#define HELPER_LD_ATOMIC(name, insn, almask, do_cast) \
+target_ulong helper_##name(CPUMIPSState *env, target_ulong arg, int mem_idx)  \
+{ \
+if (arg & almask) {   \
+if (!(env->hflags & MIPS_HFLAG_DM)) { \
+env->CP0_BadVAddr = arg;  \
+} \
+do_raise_exception(env, EXCP_AdEL, GETPC());  \
+} \
+env->CP0_LLAddr = do_translate_address(env, arg, MMU_DATA_LOAD, GETPC()); \
+env->lladdr = arg;\
+env->llval = do_cast cpu_##insn##_mmuidx_ra(env, arg, mem_idx, GETPC());  \
+return env->llval;\
+}
+HELPER_LD_ATOMIC(ll, ldl, 0x3, (target_long)(int32_t))
+#ifdef TARGET_MIPS64
+HELPER_LD_ATOMIC(lld, ldq, 0x7, (target_ulong))
+#endif
+#undef HELPER_LD_ATOMIC
+
+#endif /* !CONFIG_USER_ONLY */
+
+#ifdef TARGET_WORDS_BIGENDIAN
+#define GET_LMASK(v) ((v) & 3)
+#define GET_OFFSET(addr, offset) (addr + (offset))
+#else
+#define GET_LMASK(v) (((v) & 3) ^ 3)
+#define GET_OFFSET(addr, offset) (addr - (offset))
+#endif
+
+void helper_swl(CPUMIPSState *env, target_ulong arg1, target_ulong arg2,
+int mem_idx)
+{
+cpu_stb_mmuidx_ra(env, arg2, (uint8_t)(arg1 >> 24), mem_idx, GETPC());
+
+if (GET_LMASK(arg2) <= 2) {
+cpu_stb_mmuidx_ra(env, GET_OFFSET(arg2, 1), (uint8_t)(arg1 >> 16),
+  mem_idx, GETPC());
+}
+
+if (GET_LMASK(arg2) <= 1) {
+cpu_stb_mmuidx_ra(env, GET_OFFSET(arg2, 2), (uint8_t)(arg1 >> 8),
+  mem_idx, GETPC());
+}
+
+if (GET_LMASK(arg2) == 0) {
+cpu_stb_mmuidx_ra(env, GET_OFFSET(arg2, 3), (uint8_t)arg1,
+  mem_idx, GETPC());
+}
+}
+
+void helper_swr(CPUMIPSState *env, target_ulong arg1, target_ulong arg2,
+int mem_idx)
+{
+cpu_stb_mmuidx_ra(env, arg2, (uint8_t)arg1, mem_idx, GETPC());
+
+if (GET_LMASK(arg2) >= 1) {
+cpu_stb_mmuidx_ra(env, GET_OFFSET(arg2, -1), (uint8_t)(arg1 >> 8),
+  mem_idx, GETPC());
+}
+
+if (GET_LMASK(arg2) >= 2) {
+cpu_stb_mmuidx_ra(env, GET_OFFSET(arg2, -2), (uint8_t)(arg1 >> 16),
+  mem_idx, GETPC());
+}
+
+if (GET_LMASK(arg2) == 3) {
+cpu_stb_mmuidx_ra(env, GET_OFFSET(arg2, -3), (uint8_t)(arg1 >> 24),
+  mem_idx, GETPC());
+}
+}
+
+#if defined(TARGET_MIPS64)
+/*
+ * "half" load and stores.  We must do the memory access inline,
+ * or fault handling won't work.
+ */
+#ifdef

[PATCH 09/26] target/mips: Add simple user-mode mips_cpu_do_interrupt()

[Philippe Mathieu-Daudé]

The #ifdef'ry hides that the user-mode implementation of
mips_cpu_do_interrupt() simply sets exception_index = EXCP_NONE.

Add this simple implementation to tcg/user/helper.c, and the
corresponding Meson machinery to build this file when user
emulation is configured.

Signed-off-by: Philippe Mathieu-Daudé 
---
 target/mips/tcg/user/helper.c| 28 
 target/mips/tlb_helper.c |  5 -
 target/mips/meson.build  |  5 +
 target/mips/tcg/meson.build  |  3 +++
 target/mips/tcg/user/meson.build |  3 +++
 5 files changed, 39 insertions(+), 5 deletions(-)
 create mode 100644 target/mips/tcg/user/helper.c
 create mode 100644 target/mips/tcg/meson.build
 create mode 100644 target/mips/tcg/user/meson.build

diff --git a/target/mips/tcg/user/helper.c b/target/mips/tcg/user/helper.c
new file mode 100644
index 000..453b9e9b930
--- /dev/null
+++ b/target/mips/tcg/user/helper.c
@@ -0,0 +1,28 @@
+/*
+ * MIPS TLB (Translation lookaside buffer) helpers.
+ *
+ *  Copyright (c) 2004-2005 Jocelyn Mayer
+ *
+ * This library is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU Lesser General Public
+ * License as published by the Free Software Foundation; either
+ * version 2.1 of the License, or (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
+ * Lesser General Public License for more details.
+ *
+ * You should have received a copy of the GNU Lesser General Public
+ * License along with this library; if not, see .
+ */
+#include "qemu/osdep.h"
+
+#include "cpu.h"
+#include "exec/exec-all.h"
+#include "internal.h"
+
+void mips_cpu_do_interrupt(CPUState *cs)
+{
+cs->exception_index = EXCP_NONE;
+}
diff --git a/target/mips/tlb_helper.c b/target/mips/tlb_helper.c
index 8d3ea497803..46e9555c9ab 100644
--- a/target/mips/tlb_helper.c
+++ b/target/mips/tlb_helper.c
@@ -964,11 +964,8 @@ static inline void set_badinstr_registers(CPUMIPSState 
*env)
 }
 }
 
-#endif /* !CONFIG_USER_ONLY */
-
 void mips_cpu_do_interrupt(CPUState *cs)
 {
-#if !defined(CONFIG_USER_ONLY)
 MIPSCPU *cpu = MIPS_CPU(cs);
 CPUMIPSState *env = &cpu->env;
 bool update_badinstr = 0;
@@ -1271,11 +1268,9 @@ void mips_cpu_do_interrupt(CPUState *cs)
  env->CP0_Status, env->CP0_Cause, env->CP0_BadVAddr,
  env->CP0_DEPC);
 }
-#endif
 cs->exception_index = EXCP_NONE;
 }
 
-#if !defined(CONFIG_USER_ONLY)
 void r4k_invalidate_tlb(CPUMIPSState *env, int idx, int use_extra)
 {
 CPUState *cs = env_cpu(env);
diff --git a/target/mips/meson.build b/target/mips/meson.build
index 15c2f835c68..ca3cc62cf7a 100644
--- a/target/mips/meson.build
+++ b/target/mips/meson.build
@@ -6,6 +6,7 @@
   decodetree.process('tx79.decode', extra_args: '--static-decode=decode_tx79'),
 ]
 
+mips_user_ss = ss.source_set()
 mips_ss = ss.source_set()
 mips_ss.add(files(
   'cpu.c',
@@ -34,6 +35,9 @@
 ), if_false: files(
   'mxu_translate.c',
 ))
+if 'CONFIG_TCG' in config_all
+  subdir('tcg')
+endif
 
 mips_ss.add(when: 'CONFIG_KVM', if_true: files('kvm.c'))
 
@@ -52,3 +56,4 @@
 
 target_arch += {'mips': mips_ss}
 target_softmmu_arch += {'mips': mips_softmmu_ss}
+target_user_arch += {'mips': mips_user_ss}
diff --git a/target/mips/tcg/meson.build b/target/mips/tcg/meson.build
new file mode 100644
index 000..b74fa04303e
--- /dev/null
+++ b/target/mips/tcg/meson.build
@@ -0,0 +1,3 @@
+if have_user
+  subdir('user')
+endif
diff --git a/target/mips/tcg/user/meson.build b/target/mips/tcg/user/meson.build
new file mode 100644
index 000..2fe2062a73b
--- /dev/null
+++ b/target/mips/tcg/user/meson.build
@@ -0,0 +1,3 @@
+mips_user_ss.add(files(
+  'helper.c',
+))
-- 
2.26.3

[PATCH 11/26] target/mips: Move cpu_signal_handler definition around

[Philippe Mathieu-Daudé]

We have 2 blocks guarded with #ifdef for sysemu, which
are simply separated by the cpu_signal_handler definition.

To simplify the following commits which involve various
changes in internal.h, first join the sysemu-guarded blocks.

Signed-off-by: Philippe Mathieu-Daudé 
---
 target/mips/internal.h | 9 -
 1 file changed, 4 insertions(+), 5 deletions(-)

diff --git a/target/mips/internal.h b/target/mips/internal.h
index b3427fcc517..294560c9d2f 100644
--- a/target/mips/internal.h
+++ b/target/mips/internal.h
@@ -151,14 +151,13 @@ void mips_cpu_do_transaction_failed(CPUState *cs, hwaddr 
physaddr,
 MemTxResult response, uintptr_t retaddr);
 hwaddr cpu_mips_translate_address(CPUMIPSState *env, target_ulong address,
   MMUAccessType access_type);
-#endif
+
+extern const VMStateDescription vmstate_mips_cpu;
+
+#endif /* !CONFIG_USER_ONLY */
 
 #define cpu_signal_handler cpu_mips_signal_handler
 
-#ifndef CONFIG_USER_ONLY
-extern const VMStateDescription vmstate_mips_cpu;
-#endif
-
 static inline bool cpu_mips_hw_interrupts_enabled(CPUMIPSState *env)
 {
 return (env->CP0_Status & (1 << CP0St_IE)) &&
-- 
2.26.3

[PATCH 10/26] target/mips: Add simple user-mode mips_cpu_tlb_fill()

[Philippe Mathieu-Daudé]

tlb_helper.c's #ifdef'ry hides a quite simple user-mode
implementation of mips_cpu_tlb_fill().

Copy the user-mode implementation (without #ifdef'ry) to
tcg/user/helper.c and simplify tlb_helper.c's #ifdef'ry.

This will allow us to restrict tlb_helper.c to sysemu.

Signed-off-by: Philippe Mathieu-Daudé 
---
 target/mips/tcg/user/helper.c | 36 +++
 target/mips/tlb_helper.c  | 10 --
 2 files changed, 36 insertions(+), 10 deletions(-)

diff --git a/target/mips/tcg/user/helper.c b/target/mips/tcg/user/helper.c
index 453b9e9b930..b835144b820 100644
--- a/target/mips/tcg/user/helper.c
+++ b/target/mips/tcg/user/helper.c
@@ -22,6 +22,42 @@
 #include "exec/exec-all.h"
 #include "internal.h"
 
+static void raise_mmu_exception(CPUMIPSState *env, target_ulong address,
+MMUAccessType access_type)
+{
+CPUState *cs = env_cpu(env);
+
+env->error_code = 0;
+if (access_type == MMU_INST_FETCH) {
+env->error_code |= EXCP_INST_NOTAVAIL;
+}
+
+/* Reference to kernel address from user mode or supervisor mode */
+/* Reference to supervisor address from user mode */
+if (access_type == MMU_DATA_STORE) {
+cs->exception_index = EXCP_AdES;
+} else {
+cs->exception_index = EXCP_AdEL;
+}
+
+/* Raise exception */
+if (!(env->hflags & MIPS_HFLAG_DM)) {
+env->CP0_BadVAddr = address;
+}
+}
+
+bool mips_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
+   MMUAccessType access_type, int mmu_idx,
+   bool probe, uintptr_t retaddr)
+{
+MIPSCPU *cpu = MIPS_CPU(cs);
+CPUMIPSState *env = &cpu->env;
+
+/* data access */
+raise_mmu_exception(env, address, access_type);
+do_raise_exception_err(env, cs->exception_index, env->error_code, retaddr);
+}
+
 void mips_cpu_do_interrupt(CPUState *cs)
 {
 cs->exception_index = EXCP_NONE;
diff --git a/target/mips/tlb_helper.c b/target/mips/tlb_helper.c
index 46e9555c9ab..bb4b503ff72 100644
--- a/target/mips/tlb_helper.c
+++ b/target/mips/tlb_helper.c
@@ -403,8 +403,6 @@ void cpu_mips_tlb_flush(CPUMIPSState *env)
 env->tlb->tlb_in_use = env->tlb->nb_tlb;
 }
 
-#endif /* !CONFIG_USER_ONLY */
-
 static void raise_mmu_exception(CPUMIPSState *env, target_ulong address,
 MMUAccessType access_type, int tlb_error)
 {
@@ -484,8 +482,6 @@ static void raise_mmu_exception(CPUMIPSState *env, 
target_ulong address,
 env->error_code = error_code;
 }
 
-#if !defined(CONFIG_USER_ONLY)
-
 hwaddr mips_cpu_get_phys_page_debug(CPUState *cs, vaddr addr)
 {
 MIPSCPU *cpu = MIPS_CPU(cs);
@@ -833,7 +829,6 @@ refill:
 return true;
 }
 #endif
-#endif /* !CONFIG_USER_ONLY */
 
 bool mips_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
MMUAccessType access_type, int mmu_idx,
@@ -841,14 +836,11 @@ bool mips_cpu_tlb_fill(CPUState *cs, vaddr address, int 
size,
 {
 MIPSCPU *cpu = MIPS_CPU(cs);
 CPUMIPSState *env = &cpu->env;
-#if !defined(CONFIG_USER_ONLY)
 hwaddr physical;
 int prot;
-#endif
 int ret = TLBRET_BADADDR;
 
 /* data access */
-#if !defined(CONFIG_USER_ONLY)
 /* XXX: put correct access by using cpu_restore_state() correctly */
 ret = get_physical_address(env, &physical, &prot, address,
access_type, mmu_idx);
@@ -896,13 +888,11 @@ bool mips_cpu_tlb_fill(CPUState *cs, vaddr address, int 
size,
 if (probe) {
 return false;
 }
-#endif
 
 raise_mmu_exception(env, address, access_type, ret);
 do_raise_exception_err(env, cs->exception_index, env->error_code, retaddr);
 }
 
-#ifndef CONFIG_USER_ONLY
 hwaddr cpu_mips_translate_address(CPUMIPSState *env, target_ulong address,
   MMUAccessType access_type)
 {
-- 
2.26.3

[PATCH 07/26] meson: Introduce meson_user_arch source set for arch-specific user-mode

[Philippe Mathieu-Daudé]

Similarly to the 'target_softmmu_arch' source set which allows
to restrict target-specific sources to system emulation, add
the equivalent 'meson_user_arch' set for user emulation.

Signed-off-by: Philippe Mathieu-Daudé 
---
Cc: Paolo Bonzini 
---
 meson.build | 6 ++
 1 file changed, 6 insertions(+)

diff --git a/meson.build b/meson.build
index d8bb1ec5aa9..1ffdc9e6c4e 100644
--- a/meson.build
+++ b/meson.build
@@ -1751,6 +1751,7 @@
 hw_arch = {}
 target_arch = {}
 target_softmmu_arch = {}
+target_user_arch = {}
 
 ###
 # Trace files #
@@ -2168,6 +2169,11 @@
 abi = config_target['TARGET_ABI_DIR']
 target_type='user'
 qemu_target_name = 'qemu-' + target_name
+if arch in target_user_arch
+  t = target_user_arch[arch].apply(config_target, strict: false)
+  arch_srcs += t.sources()
+  arch_deps += t.dependencies()
+endif
 if 'CONFIG_LINUX_USER' in config_target
   base_dir = 'linux-user'
   target_inc += include_directories('linux-user/host/' / 
config_host['ARCH'])
-- 
2.26.3

[PATCH 12/26] target/mips: Move sysemu specific files under sysemu/ subfolder

[Philippe Mathieu-Daudé]

Move sysemu-specific files under the new sysemu/ subfolder
and adapt the Meson machinery.

Signed-off-by: Philippe Mathieu-Daudé 
---
 target/mips/{ => sysemu}/addr.c  |  0
 target/mips/{ => sysemu}/cp0_timer.c |  0
 target/mips/{ => sysemu}/machine.c   |  0
 target/mips/meson.build  | 12 ++--
 target/mips/sysemu/meson.build   |  5 +
 5 files changed, 11 insertions(+), 6 deletions(-)
 rename target/mips/{ => sysemu}/addr.c (100%)
 rename target/mips/{ => sysemu}/cp0_timer.c (100%)
 rename target/mips/{ => sysemu}/machine.c (100%)
 create mode 100644 target/mips/sysemu/meson.build

diff --git a/target/mips/addr.c b/target/mips/sysemu/addr.c
similarity index 100%
rename from target/mips/addr.c
rename to target/mips/sysemu/addr.c
diff --git a/target/mips/cp0_timer.c b/target/mips/sysemu/cp0_timer.c
similarity index 100%
rename from target/mips/cp0_timer.c
rename to target/mips/sysemu/cp0_timer.c
diff --git a/target/mips/machine.c b/target/mips/sysemu/machine.c
similarity index 100%
rename from target/mips/machine.c
rename to target/mips/sysemu/machine.c
diff --git a/target/mips/meson.build b/target/mips/meson.build
index ca3cc62cf7a..9a507937ece 100644
--- a/target/mips/meson.build
+++ b/target/mips/meson.build
@@ -7,6 +7,7 @@
 ]
 
 mips_user_ss = ss.source_set()
+mips_softmmu_ss = ss.source_set()
 mips_ss = ss.source_set()
 mips_ss.add(files(
   'cpu.c',
@@ -14,6 +15,11 @@
   'gdbstub.c',
   'msa.c',
 ))
+
+if have_system
+  subdir('sysemu')
+endif
+
 mips_tcg_ss = ss.source_set()
 mips_tcg_ss.add(gen)
 mips_tcg_ss.add(files(
@@ -41,12 +47,6 @@
 
 mips_ss.add(when: 'CONFIG_KVM', if_true: files('kvm.c'))
 
-mips_softmmu_ss = ss.source_set()
-mips_softmmu_ss.add(files(
-  'addr.c',
-  'cp0_timer.c',
-  'machine.c',
-))
 mips_softmmu_ss.add(when: 'CONFIG_TCG', if_true: files(
   'cp0_helper.c',
   'mips-semi.c',
diff --git a/target/mips/sysemu/meson.build b/target/mips/sysemu/meson.build
new file mode 100644
index 000..f2a1ff46081
--- /dev/null
+++ b/target/mips/sysemu/meson.build
@@ -0,0 +1,5 @@
+mips_softmmu_ss.add(files(
+  'addr.c',
+  'cp0_timer.c',
+  'machine.c',
+))
-- 
2.26.3

[PATCH 14/26] target/mips: Move sysemu TCG-specific code to tcg/sysemu/ subfolder

[Philippe Mathieu-Daudé]

Declare cpu_mips_get_random() and update_pagemask() on local scope,
and move cp0_helper.c and mips-semi.c to the new tcg/sysemu/ folder,
adapting the Meson machinery.

Move the opcode definitions to tcg/sysemu_helper.h.inc.

Signed-off-by: Philippe Mathieu-Daudé 
---
 target/mips/helper.h  | 166 +
 target/mips/internal.h|   4 -
 target/mips/tcg/tcg-internal.h|   9 ++
 target/mips/tcg/sysemu_helper.h.inc   | 168 ++
 target/mips/{ => tcg/sysemu}/cp0_helper.c |   0
 target/mips/{ => tcg/sysemu}/mips-semi.c  |   0
 target/mips/meson.build   |   5 -
 target/mips/tcg/meson.build   |   3 +
 target/mips/tcg/sysemu/meson.build|   4 +
 9 files changed, 188 insertions(+), 171 deletions(-)
 create mode 100644 target/mips/tcg/sysemu_helper.h.inc
 rename target/mips/{ => tcg/sysemu}/cp0_helper.c (100%)
 rename target/mips/{ => tcg/sysemu}/mips-semi.c (100%)
 create mode 100644 target/mips/tcg/sysemu/meson.build

diff --git a/target/mips/helper.h b/target/mips/helper.h
index 709494445dd..bc308e5db13 100644
--- a/target/mips/helper.h
+++ b/target/mips/helper.h
@@ -2,10 +2,6 @@ DEF_HELPER_3(raise_exception_err, noreturn, env, i32, int)
 DEF_HELPER_2(raise_exception, noreturn, env, i32)
 DEF_HELPER_1(raise_exception_debug, noreturn, env)
 
-#ifndef CONFIG_USER_ONLY
-DEF_HELPER_1(do_semihosting, void, env)
-#endif
-
 #ifdef TARGET_MIPS64
 DEF_HELPER_4(sdl, void, env, tl, tl, int)
 DEF_HELPER_4(sdr, void, env, tl, tl, int)
@@ -42,164 +38,6 @@ DEF_HELPER_FLAGS_1(dbitswap, TCG_CALL_NO_RWG_SE, tl, tl)
 
 DEF_HELPER_FLAGS_4(rotx, TCG_CALL_NO_RWG_SE, tl, tl, i32, i32, i32)
 
-#ifndef CONFIG_USER_ONLY
-/* CP0 helpers */
-DEF_HELPER_1(mfc0_mvpcontrol, tl, env)
-DEF_HELPER_1(mfc0_mvpconf0, tl, env)
-DEF_HELPER_1(mfc0_mvpconf1, tl, env)
-DEF_HELPER_1(mftc0_vpecontrol, tl, env)
-DEF_HELPER_1(mftc0_vpeconf0, tl, env)
-DEF_HELPER_1(mfc0_random, tl, env)
-DEF_HELPER_1(mfc0_tcstatus, tl, env)
-DEF_HELPER_1(mftc0_tcstatus, tl, env)
-DEF_HELPER_1(mfc0_tcbind, tl, env)
-DEF_HELPER_1(mftc0_tcbind, tl, env)
-DEF_HELPER_1(mfc0_tcrestart, tl, env)
-DEF_HELPER_1(mftc0_tcrestart, tl, env)
-DEF_HELPER_1(mfc0_tchalt, tl, env)
-DEF_HELPER_1(mftc0_tchalt, tl, env)
-DEF_HELPER_1(mfc0_tccontext, tl, env)
-DEF_HELPER_1(mftc0_tccontext, tl, env)
-DEF_HELPER_1(mfc0_tcschedule, tl, env)
-DEF_HELPER_1(mftc0_tcschedule, tl, env)
-DEF_HELPER_1(mfc0_tcschefback, tl, env)
-DEF_HELPER_1(mftc0_tcschefback, tl, env)
-DEF_HELPER_1(mfc0_count, tl, env)
-DEF_HELPER_1(mfc0_saar, tl, env)
-DEF_HELPER_1(mfhc0_saar, tl, env)
-DEF_HELPER_1(mftc0_entryhi, tl, env)
-DEF_HELPER_1(mftc0_status, tl, env)
-DEF_HELPER_1(mftc0_cause, tl, env)
-DEF_HELPER_1(mftc0_epc, tl, env)
-DEF_HELPER_1(mftc0_ebase, tl, env)
-DEF_HELPER_2(mftc0_configx, tl, env, tl)
-DEF_HELPER_1(mfc0_lladdr, tl, env)
-DEF_HELPER_1(mfc0_maar, tl, env)
-DEF_HELPER_1(mfhc0_maar, tl, env)
-DEF_HELPER_2(mfc0_watchlo, tl, env, i32)
-DEF_HELPER_2(mfc0_watchhi, tl, env, i32)
-DEF_HELPER_2(mfhc0_watchhi, tl, env, i32)
-DEF_HELPER_1(mfc0_debug, tl, env)
-DEF_HELPER_1(mftc0_debug, tl, env)
-#ifdef TARGET_MIPS64
-DEF_HELPER_1(dmfc0_tcrestart, tl, env)
-DEF_HELPER_1(dmfc0_tchalt, tl, env)
-DEF_HELPER_1(dmfc0_tccontext, tl, env)
-DEF_HELPER_1(dmfc0_tcschedule, tl, env)
-DEF_HELPER_1(dmfc0_tcschefback, tl, env)
-DEF_HELPER_1(dmfc0_lladdr, tl, env)
-DEF_HELPER_1(dmfc0_maar, tl, env)
-DEF_HELPER_2(dmfc0_watchlo, tl, env, i32)
-DEF_HELPER_2(dmfc0_watchhi, tl, env, i32)
-DEF_HELPER_1(dmfc0_saar, tl, env)
-#endif /* TARGET_MIPS64 */
-
-DEF_HELPER_2(mtc0_index, void, env, tl)
-DEF_HELPER_2(mtc0_mvpcontrol, void, env, tl)
-DEF_HELPER_2(mtc0_vpecontrol, void, env, tl)
-DEF_HELPER_2(mttc0_vpecontrol, void, env, tl)
-DEF_HELPER_2(mtc0_vpeconf0, void, env, tl)
-DEF_HELPER_2(mttc0_vpeconf0, void, env, tl)
-DEF_HELPER_2(mtc0_vpeconf1, void, env, tl)
-DEF_HELPER_2(mtc0_yqmask, void, env, tl)
-DEF_HELPER_2(mtc0_vpeopt, void, env, tl)
-DEF_HELPER_2(mtc0_entrylo0, void, env, tl)
-DEF_HELPER_2(mtc0_tcstatus, void, env, tl)
-DEF_HELPER_2(mttc0_tcstatus, void, env, tl)
-DEF_HELPER_2(mtc0_tcbind, void, env, tl)
-DEF_HELPER_2(mttc0_tcbind, void, env, tl)
-DEF_HELPER_2(mtc0_tcrestart, void, env, tl)
-DEF_HELPER_2(mttc0_tcrestart, void, env, tl)
-DEF_HELPER_2(mtc0_tchalt, void, env, tl)
-DEF_HELPER_2(mttc0_tchalt, void, env, tl)
-DEF_HELPER_2(mtc0_tccontext, void, env, tl)
-DEF_HELPER_2(mttc0_tccontext, void, env, tl)
-DEF_HELPER_2(mtc0_tcschedule, void, env, tl)
-DEF_HELPER_2(mttc0_tcschedule, void, env, tl)
-DEF_HELPER_2(mtc0_tcschefback, void, env, tl)
-DEF_HELPER_2(mttc0_tcschefback, void, env, tl)
-DEF_HELPER_2(mtc0_entrylo1, void, env, tl)
-DEF_HELPER_2(mtc0_context, void, env, tl)
-DEF_HELPER_2(mtc0_memorymapid, void, env, tl)
-DEF_HELPER_2(mtc0_pagemask, void, env, tl)
-DEF_HELPER_2(mtc0_pagegrain, void, env, tl)
-DEF_HELPER_2(mtc0_segctl0, void, env, tl)
-DEF_HELPER_2(mtc0_segctl1, void, env, tl)
-DEF_HELPER_2(

[PATCH 17/26] target/mips: Restrict CPUMIPSTLBContext::map_address() handlers scope

[Philippe Mathieu-Daudé]

The 3 map_address() handlers are local to tlb_helper.c,
no need to have their prototype declared publically.

Signed-off-by: Philippe Mathieu-Daudé 
---
 target/mips/internal.h  |  6 --
 target/mips/tcg/sysemu/tlb_helper.c | 13 +++--
 2 files changed, 7 insertions(+), 12 deletions(-)

diff --git a/target/mips/internal.h b/target/mips/internal.h
index b1b1681bf8d..2fdb7d9cd12 100644
--- a/target/mips/internal.h
+++ b/target/mips/internal.h
@@ -152,12 +152,6 @@ struct CPUMIPSTLBContext {
 } mmu;
 };
 
-int no_mmu_map_address(CPUMIPSState *env, hwaddr *physical, int *prot,
-   target_ulong address, MMUAccessType access_type);
-int fixed_mmu_map_address(CPUMIPSState *env, hwaddr *physical, int *prot,
-  target_ulong address, MMUAccessType access_type);
-int r4k_map_address(CPUMIPSState *env, hwaddr *physical, int *prot,
-target_ulong address, MMUAccessType access_type);
 void r4k_helper_tlbwi(CPUMIPSState *env);
 void r4k_helper_tlbwr(CPUMIPSState *env);
 void r4k_helper_tlbp(CPUMIPSState *env);
diff --git a/target/mips/tcg/sysemu/tlb_helper.c 
b/target/mips/tcg/sysemu/tlb_helper.c
index 82cfb0a9135..cbb4ccf0dac 100644
--- a/target/mips/tcg/sysemu/tlb_helper.c
+++ b/target/mips/tcg/sysemu/tlb_helper.c
@@ -26,8 +26,8 @@
 #include "hw/mips/cpudevs.h"
 
 /* no MMU emulation */
-int no_mmu_map_address(CPUMIPSState *env, hwaddr *physical, int *prot,
-   target_ulong address, MMUAccessType access_type)
+static int no_mmu_map_address(CPUMIPSState *env, hwaddr *physical, int *prot,
+  target_ulong address, MMUAccessType access_type)
 {
 *physical = address;
 *prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC;
@@ -35,8 +35,9 @@ int no_mmu_map_address(CPUMIPSState *env, hwaddr *physical, 
int *prot,
 }
 
 /* fixed mapping MMU emulation */
-int fixed_mmu_map_address(CPUMIPSState *env, hwaddr *physical, int *prot,
-  target_ulong address, MMUAccessType access_type)
+static int fixed_mmu_map_address(CPUMIPSState *env, hwaddr *physical,
+ int *prot, target_ulong address,
+ MMUAccessType access_type)
 {
 if (address <= (int32_t)0x7FFFUL) {
 if (!(env->CP0_Status & (1 << CP0St_ERL))) {
@@ -55,8 +56,8 @@ int fixed_mmu_map_address(CPUMIPSState *env, hwaddr 
*physical, int *prot,
 }
 
 /* MIPS32/MIPS64 R4000-style MMU emulation */
-int r4k_map_address(CPUMIPSState *env, hwaddr *physical, int *prot,
-target_ulong address, MMUAccessType access_type)
+static int r4k_map_address(CPUMIPSState *env, hwaddr *physical, int *prot,
+   target_ulong address, MMUAccessType access_type)
 {
 uint16_t ASID = env->CP0_EntryHi & env->CP0_EntryHi_ASID_mask;
 uint32_t MMID = env->CP0_MemoryMapID;
-- 
2.26.3

[PATCH 08/26] target/mips: Introduce tcg-internal.h for TCG specific declarations

[Philippe Mathieu-Daudé]

We will gradually move TCG-specific declarations to a new local
header: "tcg-internal.h". To keep review simple, first add this
header with 2 TCG prototypes, which we are going to move in the
next 2 commits.

Signed-off-by: Philippe Mathieu-Daudé 
---
 target/mips/internal.h |  7 +++
 target/mips/tcg/tcg-internal.h | 20 
 2 files changed, 23 insertions(+), 4 deletions(-)
 create mode 100644 target/mips/tcg/tcg-internal.h

diff --git a/target/mips/internal.h b/target/mips/internal.h
index 1c5674935aa..b3427fcc517 100644
--- a/target/mips/internal.h
+++ b/target/mips/internal.h
@@ -9,6 +9,9 @@
 #define MIPS_INTERNAL_H
 
 #include "exec/memattrs.h"
+#ifdef CONFIG_TCG
+#include "tcg/tcg-internal.h"
+#endif
 
 /*
  * MMU types, the first four entries have the same layout as the
@@ -77,7 +80,6 @@ extern const char * const fregnames[32];
 extern const struct mips_def_t mips_defs[];
 extern const int mips_defs_number;
 
-void mips_cpu_do_interrupt(CPUState *cpu);
 bool mips_cpu_exec_interrupt(CPUState *cpu, int int_req);
 hwaddr mips_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr);
 int mips_cpu_gdb_read_register(CPUState *cpu, GByteArray *buf, int reg);
@@ -212,9 +214,6 @@ void cpu_mips_stop_count(CPUMIPSState *env);
 
 /* helper.c */
 void mmu_init(CPUMIPSState *env, const mips_def_t *def);
-bool mips_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
-   MMUAccessType access_type, int mmu_idx,
-   bool probe, uintptr_t retaddr);
 
 /* op_helper.c */
 void update_pagemask(CPUMIPSState *env, target_ulong arg1, int32_t *pagemask);
diff --git a/target/mips/tcg/tcg-internal.h b/target/mips/tcg/tcg-internal.h
new file mode 100644
index 000..24438667f47
--- /dev/null
+++ b/target/mips/tcg/tcg-internal.h
@@ -0,0 +1,20 @@
+/*
+ * MIPS internal definitions and helpers (TCG accelerator)
+ *
+ * SPDX-License-Identifier: GPL-2.0-or-later
+ *
+ * This work is licensed under the terms of the GNU GPL, version 2 or later.
+ * See the COPYING file in the top-level directory.
+ */
+
+#ifndef MIPS_TCG_INTERNAL_H
+#define MIPS_TCG_INTERNAL_H
+
+#include "hw/core/cpu.h"
+
+void mips_cpu_do_interrupt(CPUState *cpu);
+bool mips_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
+   MMUAccessType access_type, int mmu_idx,
+   bool probe, uintptr_t retaddr);
+
+#endif
-- 
2.26.3

[PATCH 13/26] target/mips: Move code related to physical addressing to sysemu/phys.c

[Philippe Mathieu-Daudé]

Declare get_physical_address() with local scope and move it along
with mips_cpu_get_phys_page_debug() to sysemu/phys.c new file.

Signed-off-by: Philippe Mathieu-Daudé 
---
 target/mips/internal.h |  25 +++-
 target/mips/sysemu/physaddr.c  | 257 +
 target/mips/tlb_helper.c   | 254 
 target/mips/sysemu/meson.build |   1 +
 4 files changed, 282 insertions(+), 255 deletions(-)
 create mode 100644 target/mips/sysemu/physaddr.c

diff --git a/target/mips/internal.h b/target/mips/internal.h
index 294560c9d2f..51a45bd397a 100644
--- a/target/mips/internal.h
+++ b/target/mips/internal.h
@@ -81,15 +81,38 @@ extern const struct mips_def_t mips_defs[];
 extern const int mips_defs_number;
 
 bool mips_cpu_exec_interrupt(CPUState *cpu, int int_req);
-hwaddr mips_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr);
 int mips_cpu_gdb_read_register(CPUState *cpu, GByteArray *buf, int reg);
 int mips_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg);
 void mips_cpu_do_unaligned_access(CPUState *cpu, vaddr addr,
   MMUAccessType access_type,
   int mmu_idx, uintptr_t retaddr);
 
+#define USEG_LIMIT  ((target_ulong)(int32_t)0x7FFFUL)
+#define KSEG0_BASE  ((target_ulong)(int32_t)0x8000UL)
+#define KSEG1_BASE  ((target_ulong)(int32_t)0xA000UL)
+#define KSEG2_BASE  ((target_ulong)(int32_t)0xC000UL)
+#define KSEG3_BASE  ((target_ulong)(int32_t)0xE000UL)
+
+#define KVM_KSEG0_BASE  ((target_ulong)(int32_t)0x4000UL)
+#define KVM_KSEG2_BASE  ((target_ulong)(int32_t)0x6000UL)
+
 #if !defined(CONFIG_USER_ONLY)
 
+enum {
+TLBRET_XI = -6,
+TLBRET_RI = -5,
+TLBRET_DIRTY = -4,
+TLBRET_INVALID = -3,
+TLBRET_NOMATCH = -2,
+TLBRET_BADADDR = -1,
+TLBRET_MATCH = 0
+};
+
+int get_physical_address(CPUMIPSState *env, hwaddr *physical,
+ int *prot, target_ulong real_address,
+ MMUAccessType access_type, int mmu_idx);
+hwaddr mips_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr);
+
 typedef struct r4k_tlb_t r4k_tlb_t;
 struct r4k_tlb_t {
 target_ulong VPN;
diff --git a/target/mips/sysemu/physaddr.c b/target/mips/sysemu/physaddr.c
new file mode 100644
index 000..1918633aa1c
--- /dev/null
+++ b/target/mips/sysemu/physaddr.c
@@ -0,0 +1,257 @@
+/*
+ * MIPS TLB (Translation lookaside buffer) helpers.
+ *
+ *  Copyright (c) 2004-2005 Jocelyn Mayer
+ *
+ * This library is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU Lesser General Public
+ * License as published by the Free Software Foundation; either
+ * version 2.1 of the License, or (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
+ * Lesser General Public License for more details.
+ *
+ * You should have received a copy of the GNU Lesser General Public
+ * License along with this library; if not, see .
+ */
+#include "qemu/osdep.h"
+#include "cpu.h"
+#include "exec/exec-all.h"
+#include "../internal.h"
+
+static int is_seg_am_mapped(unsigned int am, bool eu, int mmu_idx)
+{
+/*
+ * Interpret access control mode and mmu_idx.
+ *   AdE? TLB?
+ *  AM  K S U E  K S U E
+ * UK0  0 1 1 0  0 - - 0
+ * MK1  0 1 1 0  1 - - !eu
+ * MSK   2  0 0 1 0  1 1 - !eu
+ * MUSK  3  0 0 0 0  1 1 1 !eu
+ * MUSUK 4  0 0 0 0  0 1 1 0
+ * USK   5  0 0 1 0  0 0 - 0
+ * - 6  - - - -  - - - -
+ * UUSK  7  0 0 0 0  0 0 0 0
+ */
+int32_t adetlb_mask;
+
+switch (mmu_idx) {
+case 3: /* ERL */
+/* If EU is set, always unmapped */
+if (eu) {
+return 0;
+}
+/* fall through */
+case MIPS_HFLAG_KM:
+/* Never AdE, TLB mapped if AM={1,2,3} */
+adetlb_mask = 0x7000;
+goto check_tlb;
+
+case MIPS_HFLAG_SM:
+/* AdE if AM={0,1}, TLB mapped if AM={2,3,4} */
+adetlb_mask = 0xc038;
+goto check_ade;
+
+case MIPS_HFLAG_UM:
+/* AdE if AM={0,1,2,5}, TLB mapped if AM={3,4} */
+adetlb_mask = 0xe418;
+/* fall through */
+check_ade:
+/* does this AM cause AdE in current execution mode */
+if ((adetlb_mask << am) < 0) {
+return TLBRET_BADADDR;
+}
+adetlb_mask <<= 8;
+/* fall through */
+check_tlb:
+/* is this AM mapped in current execution mode */
+return ((adetlb_mask << am) < 0);
+default:
+assert(0);
+return TLBRET_BADADDR;
+};
+}
+
+static int get_seg_physical_address(CPUMIPSState *env, hwaddr *physical,
+int *prot, target_ulong real_address,
+  

[PATCH 15/26] target/mips: Restrict mmu_init() to TCG

[Philippe Mathieu-Daudé]

mmu_init() is only required by TCG accelerator.
Restrict its declaration and call to TCG.

Signed-off-by: Philippe Mathieu-Daudé 
---
 target/mips/internal.h | 3 ---
 target/mips/tcg/tcg-internal.h | 2 ++
 target/mips/cpu.c  | 2 +-
 3 files changed, 3 insertions(+), 4 deletions(-)

diff --git a/target/mips/internal.h b/target/mips/internal.h
index 59c2c22cd0a..13f8e421662 100644
--- a/target/mips/internal.h
+++ b/target/mips/internal.h
@@ -233,9 +233,6 @@ void cpu_mips_store_compare(CPUMIPSState *env, uint32_t 
value);
 void cpu_mips_start_count(CPUMIPSState *env);
 void cpu_mips_stop_count(CPUMIPSState *env);
 
-/* helper.c */
-void mmu_init(CPUMIPSState *env, const mips_def_t *def);
-
 static inline void restore_pamask(CPUMIPSState *env)
 {
 if (env->hflags & MIPS_HFLAG_ELPA) {
diff --git a/target/mips/tcg/tcg-internal.h b/target/mips/tcg/tcg-internal.h
index b65580af211..70655bab45c 100644
--- a/target/mips/tcg/tcg-internal.h
+++ b/target/mips/tcg/tcg-internal.h
@@ -20,6 +20,8 @@ bool mips_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
 
 #if !defined(CONFIG_USER_ONLY)
 
+void mmu_init(CPUMIPSState *env, const mips_def_t *def);
+
 void update_pagemask(CPUMIPSState *env, target_ulong arg1, int32_t *pagemask);
 
 uint32_t cpu_mips_get_random(CPUMIPSState *env);
diff --git a/target/mips/cpu.c b/target/mips/cpu.c
index ac38a3262ca..bfc927dd9cd 100644
--- a/target/mips/cpu.c
+++ b/target/mips/cpu.c
@@ -718,7 +718,7 @@ static void mips_cpu_realizefn(DeviceState *dev, Error 
**errp)
 
 env->exception_base = (int32_t)0xBFC0;
 
-#ifndef CONFIG_USER_ONLY
+#if defined(CONFIG_TCG) && !defined(CONFIG_USER_ONLY)
 mmu_init(env, env->cpu_model);
 #endif
 fpu_init(env, env->cpu_model);
-- 
2.26.3

[PATCH 20/26] target/mips: Move TLB management helpers to tcg/sysemu/tlb_helper.c

[Philippe Mathieu-Daudé]

Move TLB management helpers to tcg/sysemu/tlb_helper.c.

Signed-off-by: Philippe Mathieu-Daudé 
---
4 checkpatch errors:

  ERROR: space prohibited after that '&' (ctx:WxW)
  #414: FILE: target/mips/tcg/sysemu/tlb_helper.c:71:
  +tlb->XI0 = (env->CP0_EntryLo0 >> CP0EnLo_XI) & 1;
^

  ERROR: space prohibited after that '&' (ctx:WxW)
  #415: FILE: target/mips/tcg/sysemu/tlb_helper.c:72:
  +tlb->RI0 = (env->CP0_EntryLo0 >> CP0EnLo_RI) & 1;
^

  ERROR: space prohibited after that '&' (ctx:WxW)
  #420: FILE: target/mips/tcg/sysemu/tlb_helper.c:77:
  +tlb->XI1 = (env->CP0_EntryLo1 >> CP0EnLo_XI) & 1;
^

  ERROR: space prohibited after that '&' (ctx:WxW)
  #421: FILE: target/mips/tcg/sysemu/tlb_helper.c:78:
  +tlb->RI1 = (env->CP0_EntryLo1 >> CP0EnLo_RI) & 1;
^

  total: 4 errors, 0 warnings, 688 lines checked

Signed-off-by: Philippe Mathieu-Daudé 
---
 target/mips/helper.h|  10 -
 target/mips/internal.h  |   7 -
 target/mips/tcg/sysemu_helper.h.inc |   9 +
 target/mips/op_helper.c | 333 
 target/mips/tcg/sysemu/tlb_helper.c | 331 +++
 5 files changed, 340 insertions(+), 350 deletions(-)

diff --git a/target/mips/helper.h b/target/mips/helper.h
index 4ee7916d8b2..8f2ba0a92f8 100644
--- a/target/mips/helper.h
+++ b/target/mips/helper.h
@@ -202,16 +202,6 @@ FOP_PROTO(sune)
 FOP_PROTO(sne)
 #undef FOP_PROTO
 
-/* Special functions */
-#ifndef CONFIG_USER_ONLY
-DEF_HELPER_1(tlbwi, void, env)
-DEF_HELPER_1(tlbwr, void, env)
-DEF_HELPER_1(tlbp, void, env)
-DEF_HELPER_1(tlbr, void, env)
-DEF_HELPER_1(tlbinv, void, env)
-DEF_HELPER_1(tlbinvf, void, env)
-DEF_HELPER_3(ginvt, void, env, tl, i32)
-#endif /* !CONFIG_USER_ONLY */
 DEF_HELPER_1(rdhwr_cpunum, tl, env)
 DEF_HELPER_1(rdhwr_synci_step, tl, env)
 DEF_HELPER_1(rdhwr_cc, tl, env)
diff --git a/target/mips/internal.h b/target/mips/internal.h
index 2fdb7d9cd12..b3f945f6cad 100644
--- a/target/mips/internal.h
+++ b/target/mips/internal.h
@@ -152,13 +152,6 @@ struct CPUMIPSTLBContext {
 } mmu;
 };
 
-void r4k_helper_tlbwi(CPUMIPSState *env);
-void r4k_helper_tlbwr(CPUMIPSState *env);
-void r4k_helper_tlbp(CPUMIPSState *env);
-void r4k_helper_tlbr(CPUMIPSState *env);
-void r4k_helper_tlbinv(CPUMIPSState *env);
-void r4k_helper_tlbinvf(CPUMIPSState *env);
-
 void mips_cpu_do_transaction_failed(CPUState *cs, hwaddr physaddr,
 vaddr addr, unsigned size,
 MMUAccessType access_type,
diff --git a/target/mips/tcg/sysemu_helper.h.inc 
b/target/mips/tcg/sysemu_helper.h.inc
index 38e55cbf118..f309429b4e8 100644
--- a/target/mips/tcg/sysemu_helper.h.inc
+++ b/target/mips/tcg/sysemu_helper.h.inc
@@ -167,6 +167,15 @@ DEF_HELPER_1(evpe, tl, env)
 DEF_HELPER_1(dvp, tl, env)
 DEF_HELPER_1(evp, tl, env)
 
+/* TLB */
+DEF_HELPER_1(tlbwi, void, env)
+DEF_HELPER_1(tlbwr, void, env)
+DEF_HELPER_1(tlbp, void, env)
+DEF_HELPER_1(tlbr, void, env)
+DEF_HELPER_1(tlbinv, void, env)
+DEF_HELPER_1(tlbinvf, void, env)
+DEF_HELPER_3(ginvt, void, env, tl, i32)
+
 /* Special */
 DEF_HELPER_1(di, tl, env)
 DEF_HELPER_1(ei, tl, env)
diff --git a/target/mips/op_helper.c b/target/mips/op_helper.c
index 659c4d15668..c6373d1de3f 100644
--- a/target/mips/op_helper.c
+++ b/target/mips/op_helper.c
@@ -325,339 +325,6 @@ target_ulong helper_yield(CPUMIPSState *env, target_ulong 
arg)
 return env->CP0_YQMask;
 }
 
-#ifndef CONFIG_USER_ONLY
-/* TLB management */
-static void r4k_mips_tlb_flush_extra(CPUMIPSState *env, int first)
-{
-/* Discard entries from env->tlb[first] onwards.  */
-while (env->tlb->tlb_in_use > first) {
-r4k_invalidate_tlb(env, --env->tlb->tlb_in_use, 0);
-}
-}
-
-static inline uint64_t get_tlb_pfn_from_entrylo(uint64_t entrylo)
-{
-#if defined(TARGET_MIPS64)
-return extract64(entrylo, 6, 54);
-#else
-return extract64(entrylo, 6, 24) | /* PFN */
-   (extract64(entrylo, 32, 32) << 24); /* PFNX */
-#endif
-}
-
-static void r4k_fill_tlb(CPUMIPSState *env, int idx)
-{
-r4k_tlb_t *tlb;
-uint64_t mask = env->CP0_PageMask >> (TARGET_PAGE_BITS + 1);
-
-/* XXX: detect conflicting TLBs and raise a MCHECK exception when needed */
-tlb = &env->tlb->mmu.r4k.tlb[idx];
-if (env->CP0_EntryHi & (1 << CP0EnHi_EHINV)) {
-tlb->EHINV = 1;
-return;
-}
-tlb->EHINV = 0;
-tlb->VPN = env->CP0_EntryHi & (TARGET_PAGE_MASK << 1);
-#if defined(TARGET_MIPS64)
-tlb->VPN &= env->SEGMask;
-#endif
-tlb->ASID = env->CP0_EntryHi & env->CP0_EntryHi_ASID_mask;
-tlb->MMID = env->CP0_MemoryMapID;
-tlb->PageMask = env->CP0_PageMask;
-tlb->G = env->CP0_EntryLo0 & env->CP0_EntryLo1 & 1;
-tlb->V0 = (env->CP0_EntryLo0 & 2) != 0;
-tlb->D0 = (en

[PATCH 23/26] target/mips: Move helper.h -> tcg/helper.h.inc

[Philippe Mathieu-Daudé]

TCG frontend "exec/helper-head.h" expects each target to declare
its helpers in 'target/$TARGET/helper.h'. To ease maintenance we
rather to have all TCG specific files under our tcg/ sub directory.

Move the current 'helper.h' there, and add a one-line 'helper.h'
which re-include it.

Signed-off-by: Philippe Mathieu-Daudé 
---
 target/mips/helper.h | 614 +--
 target/mips/tcg/helper.h.inc | 613 ++
 2 files changed, 614 insertions(+), 613 deletions(-)
 create mode 100644 target/mips/tcg/helper.h.inc

diff --git a/target/mips/helper.h b/target/mips/helper.h
index 8f2ba0a92f8..8cd8dbd956a 100644
--- a/target/mips/helper.h
+++ b/target/mips/helper.h
@@ -1,613 +1 @@
-DEF_HELPER_3(raise_exception_err, noreturn, env, i32, int)
-DEF_HELPER_2(raise_exception, noreturn, env, i32)
-DEF_HELPER_1(raise_exception_debug, noreturn, env)
-
-#ifdef TARGET_MIPS64
-DEF_HELPER_4(sdl, void, env, tl, tl, int)
-DEF_HELPER_4(sdr, void, env, tl, tl, int)
-#endif
-DEF_HELPER_4(swl, void, env, tl, tl, int)
-DEF_HELPER_4(swr, void, env, tl, tl, int)
-
-#ifndef CONFIG_USER_ONLY
-DEF_HELPER_3(ll, tl, env, tl, int)
-#ifdef TARGET_MIPS64
-DEF_HELPER_3(lld, tl, env, tl, int)
-#endif
-#endif
-
-DEF_HELPER_3(muls, tl, env, tl, tl)
-DEF_HELPER_3(mulsu, tl, env, tl, tl)
-DEF_HELPER_3(macc, tl, env, tl, tl)
-DEF_HELPER_3(maccu, tl, env, tl, tl)
-DEF_HELPER_3(msac, tl, env, tl, tl)
-DEF_HELPER_3(msacu, tl, env, tl, tl)
-DEF_HELPER_3(mulhi, tl, env, tl, tl)
-DEF_HELPER_3(mulhiu, tl, env, tl, tl)
-DEF_HELPER_3(mulshi, tl, env, tl, tl)
-DEF_HELPER_3(mulshiu, tl, env, tl, tl)
-DEF_HELPER_3(macchi, tl, env, tl, tl)
-DEF_HELPER_3(macchiu, tl, env, tl, tl)
-DEF_HELPER_3(msachi, tl, env, tl, tl)
-DEF_HELPER_3(msachiu, tl, env, tl, tl)
-
-DEF_HELPER_FLAGS_1(bitswap, TCG_CALL_NO_RWG_SE, tl, tl)
-#ifdef TARGET_MIPS64
-DEF_HELPER_FLAGS_1(dbitswap, TCG_CALL_NO_RWG_SE, tl, tl)
-#endif
-
-DEF_HELPER_FLAGS_4(rotx, TCG_CALL_NO_RWG_SE, tl, tl, i32, i32, i32)
-
-/* microMIPS functions */
-DEF_HELPER_4(lwm, void, env, tl, tl, i32)
-DEF_HELPER_4(swm, void, env, tl, tl, i32)
-#ifdef TARGET_MIPS64
-DEF_HELPER_4(ldm, void, env, tl, tl, i32)
-DEF_HELPER_4(sdm, void, env, tl, tl, i32)
-#endif
-
-DEF_HELPER_2(fork, void, tl, tl)
-DEF_HELPER_2(yield, tl, env, tl)
-
-/* CP1 functions */
-DEF_HELPER_2(cfc1, tl, env, i32)
-DEF_HELPER_4(ctc1, void, env, tl, i32, i32)
-
-DEF_HELPER_2(float_cvtd_s, i64, env, i32)
-DEF_HELPER_2(float_cvtd_w, i64, env, i32)
-DEF_HELPER_2(float_cvtd_l, i64, env, i64)
-DEF_HELPER_2(float_cvtps_pw, i64, env, i64)
-DEF_HELPER_2(float_cvtpw_ps, i64, env, i64)
-DEF_HELPER_2(float_cvts_d, i32, env, i64)
-DEF_HELPER_2(float_cvts_w, i32, env, i32)
-DEF_HELPER_2(float_cvts_l, i32, env, i64)
-DEF_HELPER_2(float_cvts_pl, i32, env, i32)
-DEF_HELPER_2(float_cvts_pu, i32, env, i32)
-
-DEF_HELPER_3(float_addr_ps, i64, env, i64, i64)
-DEF_HELPER_3(float_mulr_ps, i64, env, i64, i64)
-
-DEF_HELPER_FLAGS_2(float_class_s, TCG_CALL_NO_RWG_SE, i32, env, i32)
-DEF_HELPER_FLAGS_2(float_class_d, TCG_CALL_NO_RWG_SE, i64, env, i64)
-
-#define FOP_PROTO(op) \
-DEF_HELPER_4(float_ ## op ## _s, i32, env, i32, i32, i32) \
-DEF_HELPER_4(float_ ## op ## _d, i64, env, i64, i64, i64)
-FOP_PROTO(maddf)
-FOP_PROTO(msubf)
-#undef FOP_PROTO
-
-#define FOP_PROTO(op)\
-DEF_HELPER_3(float_ ## op ## _s, i32, env, i32, i32) \
-DEF_HELPER_3(float_ ## op ## _d, i64, env, i64, i64)
-FOP_PROTO(max)
-FOP_PROTO(maxa)
-FOP_PROTO(min)
-FOP_PROTO(mina)
-#undef FOP_PROTO
-
-#define FOP_PROTO(op)\
-DEF_HELPER_2(float_ ## op ## _l_s, i64, env, i32) \
-DEF_HELPER_2(float_ ## op ## _l_d, i64, env, i64) \
-DEF_HELPER_2(float_ ## op ## _w_s, i32, env, i32) \
-DEF_HELPER_2(float_ ## op ## _w_d, i32, env, i64)
-FOP_PROTO(cvt)
-FOP_PROTO(round)
-FOP_PROTO(trunc)
-FOP_PROTO(ceil)
-FOP_PROTO(floor)
-FOP_PROTO(cvt_2008)
-FOP_PROTO(round_2008)
-FOP_PROTO(trunc_2008)
-FOP_PROTO(ceil_2008)
-FOP_PROTO(floor_2008)
-#undef FOP_PROTO
-
-#define FOP_PROTO(op)\
-DEF_HELPER_2(float_ ## op ## _s, i32, env, i32)  \
-DEF_HELPER_2(float_ ## op ## _d, i64, env, i64)
-FOP_PROTO(sqrt)
-FOP_PROTO(rsqrt)
-FOP_PROTO(recip)
-FOP_PROTO(rint)
-#undef FOP_PROTO
-
-#define FOP_PROTO(op)   \
-DEF_HELPER_1(float_ ## op ## _s, i32, i32)  \
-DEF_HELPER_1(float_ ## op ## _d, i64, i64)  \
-DEF_HELPER_1(float_ ## op ## _ps, i64, i64)
-FOP_PROTO(abs)
-FOP_PROTO(chs)
-#undef FOP_PROTO
-
-#define FOP_PROTO(op)\
-DEF_HELPER_2(float_ ## op ## _s, i32, env, i32)  \
-DEF_HELPER_2(float_ ## op ## _d, i64, env, i64)  \
-DEF_HELPER_2(float_ ## op ## _ps, i64, env, i64)
-FOP_PROTO(recip1)
-FOP_PROTO(rsqrt1)
-#undef FOP_PROTO
-
-#define FOP_PROTO(op)  \
-DEF_HELPER_3(float_ ## op ## _s, i32, env, i32, i32)   \
-DEF_HELPER_3(float_ ## op ## _d, i64, env, i64, i64)   \
-DEF_HELPER_3(float

[PATCH 16/26] target/mips: Move tlb_helper.c to tcg/sysemu/

[Philippe Mathieu-Daudé]

Move tlb_helper.c to the tcg/sysemu/ subdir, along with
the following 3 declarations to tcg-internal.h:
- cpu_mips_tlb_flush()
- cpu_mips_translate_address()
- r4k_invalidate_tlb()

Simplify tlb_helper.c #ifdef'ry because files in tcg/sysemu/
are only build when sysemu mode is configured.

Signed-off-by: Philippe Mathieu-Daudé 
---
 target/mips/internal.h| 5 -
 target/mips/tcg/tcg-internal.h| 5 +
 target/mips/{ => tcg/sysemu}/tlb_helper.c | 3 ---
 target/mips/meson.build   | 1 -
 target/mips/tcg/sysemu/meson.build| 1 +
 5 files changed, 6 insertions(+), 9 deletions(-)
 rename target/mips/{ => tcg/sysemu}/tlb_helper.c (99%)

diff --git a/target/mips/internal.h b/target/mips/internal.h
index 13f8e421662..b1b1681bf8d 100644
--- a/target/mips/internal.h
+++ b/target/mips/internal.h
@@ -164,16 +164,12 @@ void r4k_helper_tlbp(CPUMIPSState *env);
 void r4k_helper_tlbr(CPUMIPSState *env);
 void r4k_helper_tlbinv(CPUMIPSState *env);
 void r4k_helper_tlbinvf(CPUMIPSState *env);
-void r4k_invalidate_tlb(CPUMIPSState *env, int idx, int use_extra);
 
 void mips_cpu_do_transaction_failed(CPUState *cs, hwaddr physaddr,
 vaddr addr, unsigned size,
 MMUAccessType access_type,
 int mmu_idx, MemTxAttrs attrs,
 MemTxResult response, uintptr_t retaddr);
-hwaddr cpu_mips_translate_address(CPUMIPSState *env, target_ulong address,
-  MMUAccessType access_type);
-
 extern const VMStateDescription vmstate_mips_cpu;
 
 #endif /* !CONFIG_USER_ONLY */
@@ -413,7 +409,6 @@ static inline void compute_hflags(CPUMIPSState *env)
 }
 }
 
-void cpu_mips_tlb_flush(CPUMIPSState *env);
 void sync_c0_status(CPUMIPSState *env, CPUMIPSState *cpu, int tc);
 void cpu_mips_store_status(CPUMIPSState *env, target_ulong val);
 void cpu_mips_store_cause(CPUMIPSState *env, target_ulong val);
diff --git a/target/mips/tcg/tcg-internal.h b/target/mips/tcg/tcg-internal.h
index 70655bab45c..6615151cba2 100644
--- a/target/mips/tcg/tcg-internal.h
+++ b/target/mips/tcg/tcg-internal.h
@@ -24,8 +24,13 @@ void mmu_init(CPUMIPSState *env, const mips_def_t *def);
 
 void update_pagemask(CPUMIPSState *env, target_ulong arg1, int32_t *pagemask);
 
+void r4k_invalidate_tlb(CPUMIPSState *env, int idx, int use_extra);
 uint32_t cpu_mips_get_random(CPUMIPSState *env);
 
+hwaddr cpu_mips_translate_address(CPUMIPSState *env, target_ulong address,
+  MMUAccessType access_type);
+void cpu_mips_tlb_flush(CPUMIPSState *env);
+
 #endif /* !CONFIG_USER_ONLY */
 
 #endif
diff --git a/target/mips/tlb_helper.c b/target/mips/tcg/sysemu/tlb_helper.c
similarity index 99%
rename from target/mips/tlb_helper.c
rename to target/mips/tcg/sysemu/tlb_helper.c
index 2304fff4c42..82cfb0a9135 100644
--- a/target/mips/tlb_helper.c
+++ b/target/mips/tcg/sysemu/tlb_helper.c
@@ -25,8 +25,6 @@
 #include "exec/log.h"
 #include "hw/mips/cpudevs.h"
 
-#if !defined(CONFIG_USER_ONLY)
-
 /* no MMU emulation */
 int no_mmu_map_address(CPUMIPSState *env, hwaddr *physical, int *prot,
target_ulong address, MMUAccessType access_type)
@@ -1071,4 +1069,3 @@ void r4k_invalidate_tlb(CPUMIPSState *env, int idx, int 
use_extra)
 }
 }
 }
-#endif /* !CONFIG_USER_ONLY */
diff --git a/target/mips/meson.build b/target/mips/meson.build
index a55af1cd6cf..ff5eb210dfd 100644
--- a/target/mips/meson.build
+++ b/target/mips/meson.build
@@ -31,7 +31,6 @@
   'msa_translate.c',
   'op_helper.c',
   'rel6_translate.c',
-  'tlb_helper.c',
   'translate.c',
   'translate_addr_const.c',
   'txx9_translate.c',
diff --git a/target/mips/tcg/sysemu/meson.build 
b/target/mips/tcg/sysemu/meson.build
index 5c3024e7760..73ab9571ba6 100644
--- a/target/mips/tcg/sysemu/meson.build
+++ b/target/mips/tcg/sysemu/meson.build
@@ -1,4 +1,5 @@
 mips_softmmu_ss.add(files(
   'cp0_helper.c',
   'mips-semi.c',
+  'tlb_helper.c',
 ))
-- 
2.26.3

[PATCH 18/26] target/mips: Move Special opcodes to tcg/sysemu/special_helper.c

[Philippe Mathieu-Daudé]

Move the Special opcodes helpers to tcg/sysemu/special_helper.c.

Since mips_io_recompile_replay_branch() is set as
CPUClass::io_recompile_replay_branch handler in cpu.c,
we need to declare its prototype in "tcg-internal.h".

Signed-off-by: Philippe Mathieu-Daudé 
---
 target/mips/helper.h|   5 -
 target/mips/tcg/tcg-internal.h  |   3 +
 target/mips/tcg/sysemu_helper.h.inc |   7 ++
 target/mips/cpu.c   |  17 ---
 target/mips/op_helper.c | 110 -
 target/mips/tcg/sysemu/special_helper.c | 150 
 target/mips/tcg/sysemu/meson.build  |   1 +
 7 files changed, 161 insertions(+), 132 deletions(-)
 create mode 100644 target/mips/tcg/sysemu/special_helper.c

diff --git a/target/mips/helper.h b/target/mips/helper.h
index bc308e5db13..4ee7916d8b2 100644
--- a/target/mips/helper.h
+++ b/target/mips/helper.h
@@ -210,11 +210,6 @@ DEF_HELPER_1(tlbp, void, env)
 DEF_HELPER_1(tlbr, void, env)
 DEF_HELPER_1(tlbinv, void, env)
 DEF_HELPER_1(tlbinvf, void, env)
-DEF_HELPER_1(di, tl, env)
-DEF_HELPER_1(ei, tl, env)
-DEF_HELPER_1(eret, void, env)
-DEF_HELPER_1(eretnc, void, env)
-DEF_HELPER_1(deret, void, env)
 DEF_HELPER_3(ginvt, void, env, tl, i32)
 #endif /* !CONFIG_USER_ONLY */
 DEF_HELPER_1(rdhwr_cpunum, tl, env)
diff --git a/target/mips/tcg/tcg-internal.h b/target/mips/tcg/tcg-internal.h
index 6615151cba2..e507dd1630f 100644
--- a/target/mips/tcg/tcg-internal.h
+++ b/target/mips/tcg/tcg-internal.h
@@ -10,6 +10,7 @@
 #ifndef MIPS_TCG_INTERNAL_H
 #define MIPS_TCG_INTERNAL_H
 
+#include "tcg/tcg.h"
 #include "hw/core/cpu.h"
 #include "cpu.h"
 
@@ -27,6 +28,8 @@ void update_pagemask(CPUMIPSState *env, target_ulong arg1, 
int32_t *pagemask);
 void r4k_invalidate_tlb(CPUMIPSState *env, int idx, int use_extra);
 uint32_t cpu_mips_get_random(CPUMIPSState *env);
 
+bool mips_io_recompile_replay_branch(CPUState *cs, const TranslationBlock *tb);
+
 hwaddr cpu_mips_translate_address(CPUMIPSState *env, target_ulong address,
   MMUAccessType access_type);
 void cpu_mips_tlb_flush(CPUMIPSState *env);
diff --git a/target/mips/tcg/sysemu_helper.h.inc 
b/target/mips/tcg/sysemu_helper.h.inc
index d136c4160a7..38e55cbf118 100644
--- a/target/mips/tcg/sysemu_helper.h.inc
+++ b/target/mips/tcg/sysemu_helper.h.inc
@@ -166,3 +166,10 @@ DEF_HELPER_1(evpe, tl, env)
 /* R6 Multi-threading */
 DEF_HELPER_1(dvp, tl, env)
 DEF_HELPER_1(evp, tl, env)
+
+/* Special */
+DEF_HELPER_1(di, tl, env)
+DEF_HELPER_1(ei, tl, env)
+DEF_HELPER_1(eret, void, env)
+DEF_HELPER_1(eretnc, void, env)
+DEF_HELPER_1(deret, void, env)
diff --git a/target/mips/cpu.c b/target/mips/cpu.c
index bfc927dd9cd..e756d75667f 100644
--- a/target/mips/cpu.c
+++ b/target/mips/cpu.c
@@ -352,23 +352,6 @@ static void mips_cpu_synchronize_from_tb(CPUState *cs,
 env->hflags &= ~MIPS_HFLAG_BMASK;
 env->hflags |= tb->flags & MIPS_HFLAG_BMASK;
 }
-
-# ifndef CONFIG_USER_ONLY
-static bool mips_io_recompile_replay_branch(CPUState *cs,
-const TranslationBlock *tb)
-{
-MIPSCPU *cpu = MIPS_CPU(cs);
-CPUMIPSState *env = &cpu->env;
-
-if ((env->hflags & MIPS_HFLAG_BMASK) != 0
-&& env->active_tc.PC != tb->pc) {
-env->active_tc.PC -= (env->hflags & MIPS_HFLAG_B16 ? 2 : 4);
-env->hflags &= ~MIPS_HFLAG_BMASK;
-return true;
-}
-return false;
-}
-# endif /* !CONFIG_USER_ONLY */
 #endif /* CONFIG_TCG */
 
 static bool mips_cpu_has_work(CPUState *cs)
diff --git a/target/mips/op_helper.c b/target/mips/op_helper.c
index 0b54072378c..3903545831f 100644
--- a/target/mips/op_helper.c
+++ b/target/mips/op_helper.c
@@ -656,116 +656,6 @@ void helper_ginvt(CPUMIPSState *env, target_ulong arg, 
uint32_t type)
 }
 }
 
-/* Specials */
-target_ulong helper_di(CPUMIPSState *env)
-{
-target_ulong t0 = env->CP0_Status;
-
-env->CP0_Status = t0 & ~(1 << CP0St_IE);
-return t0;
-}
-
-target_ulong helper_ei(CPUMIPSState *env)
-{
-target_ulong t0 = env->CP0_Status;
-
-env->CP0_Status = t0 | (1 << CP0St_IE);
-return t0;
-}
-
-static void debug_pre_eret(CPUMIPSState *env)
-{
-if (qemu_loglevel_mask(CPU_LOG_EXEC)) {
-qemu_log("ERET: PC " TARGET_FMT_lx " EPC " TARGET_FMT_lx,
-env->active_tc.PC, env->CP0_EPC);
-if (env->CP0_Status & (1 << CP0St_ERL)) {
-qemu_log(" ErrorEPC " TARGET_FMT_lx, env->CP0_ErrorEPC);
-}
-if (env->hflags & MIPS_HFLAG_DM) {
-qemu_log(" DEPC " TARGET_FMT_lx, env->CP0_DEPC);
-}
-qemu_log("\n");
-}
-}
-
-static void debug_post_eret(CPUMIPSState *env)
-{
-if (qemu_loglevel_mask(CPU_LOG_EXEC)) {
-qemu_log("  =>  PC " TARGET_FMT_lx " EPC " TARGET_FMT_lx,
-env->active_tc.PC, env->CP0_EPC);
-if (env->CP0_Status & (1 << CP0St_ERL)) {
-qemu_log(" ErrorEPC " TARGET_FMT_lx, env->CP0_ErrorEPC);
-}
-  

[PATCH 22/26] target/mips: Move CP0 helpers to sysemu/cp0.c

[Philippe Mathieu-Daudé]

Opcodes accessing Coprocessor 0 are privileged.
Move the CP0 helpers to sysemu/ and simplify the #ifdef'ry.

Signed-off-by: Philippe Mathieu-Daudé 
---
 target/mips/internal.h |   9 +--
 target/mips/cpu.c  | 103 ---
 target/mips/sysemu/cp0.c   | 123 +
 target/mips/sysemu/meson.build |   1 +
 4 files changed, 129 insertions(+), 107 deletions(-)
 create mode 100644 target/mips/sysemu/cp0.c

diff --git a/target/mips/internal.h b/target/mips/internal.h
index 1e085b0625c..57eec83384a 100644
--- a/target/mips/internal.h
+++ b/target/mips/internal.h
@@ -156,6 +156,11 @@ void mips_cpu_do_transaction_failed(CPUState *cs, hwaddr 
physaddr,
 MMUAccessType access_type,
 int mmu_idx, MemTxAttrs attrs,
 MemTxResult response, uintptr_t retaddr);
+
+void sync_c0_status(CPUMIPSState *env, CPUMIPSState *cpu, int tc);
+void cpu_mips_store_status(CPUMIPSState *env, target_ulong val);
+void cpu_mips_store_cause(CPUMIPSState *env, target_ulong val);
+
 extern const VMStateDescription vmstate_mips_cpu;
 
 #endif /* !CONFIG_USER_ONLY */
@@ -395,8 +400,4 @@ static inline void compute_hflags(CPUMIPSState *env)
 }
 }
 
-void sync_c0_status(CPUMIPSState *env, CPUMIPSState *cpu, int tc);
-void cpu_mips_store_status(CPUMIPSState *env, target_ulong val);
-void cpu_mips_store_cause(CPUMIPSState *env, target_ulong val);
-
 #endif
diff --git a/target/mips/cpu.c b/target/mips/cpu.c
index 38328ba0927..aa42f1e5647 100644
--- a/target/mips/cpu.c
+++ b/target/mips/cpu.c
@@ -42,109 +42,6 @@ const char * const regnames[32] = {
 "t8", "t9", "k0", "k1", "gp", "sp", "s8", "ra",
 };
 
-#if !defined(CONFIG_USER_ONLY)
-
-/* Called for updates to CP0_Status.  */
-void sync_c0_status(CPUMIPSState *env, CPUMIPSState *cpu, int tc)
-{
-int32_t tcstatus, *tcst;
-uint32_t v = cpu->CP0_Status;
-uint32_t cu, mx, asid, ksu;
-uint32_t mask = ((1 << CP0TCSt_TCU3)
-   | (1 << CP0TCSt_TCU2)
-   | (1 << CP0TCSt_TCU1)
-   | (1 << CP0TCSt_TCU0)
-   | (1 << CP0TCSt_TMX)
-   | (3 << CP0TCSt_TKSU)
-   | (0xff << CP0TCSt_TASID));
-
-cu = (v >> CP0St_CU0) & 0xf;
-mx = (v >> CP0St_MX) & 0x1;
-ksu = (v >> CP0St_KSU) & 0x3;
-asid = env->CP0_EntryHi & env->CP0_EntryHi_ASID_mask;
-
-tcstatus = cu << CP0TCSt_TCU0;
-tcstatus |= mx << CP0TCSt_TMX;
-tcstatus |= ksu << CP0TCSt_TKSU;
-tcstatus |= asid;
-
-if (tc == cpu->current_tc) {
-tcst = &cpu->active_tc.CP0_TCStatus;
-} else {
-tcst = &cpu->tcs[tc].CP0_TCStatus;
-}
-
-*tcst &= ~mask;
-*tcst |= tcstatus;
-compute_hflags(cpu);
-}
-
-void cpu_mips_store_status(CPUMIPSState *env, target_ulong val)
-{
-uint32_t mask = env->CP0_Status_rw_bitmask;
-target_ulong old = env->CP0_Status;
-
-if (env->insn_flags & ISA_MIPS_R6) {
-bool has_supervisor = extract32(mask, CP0St_KSU, 2) == 0x3;
-#if defined(TARGET_MIPS64)
-uint32_t ksux = (1 << CP0St_KX) & val;
-ksux |= (ksux >> 1) & val; /* KX = 0 forces SX to be 0 */
-ksux |= (ksux >> 1) & val; /* SX = 0 forces UX to be 0 */
-val = (val & ~(7 << CP0St_UX)) | ksux;
-#endif
-if (has_supervisor && extract32(val, CP0St_KSU, 2) == 0x3) {
-mask &= ~(3 << CP0St_KSU);
-}
-mask &= ~(((1 << CP0St_SR) | (1 << CP0St_NMI)) & val);
-}
-
-env->CP0_Status = (old & ~mask) | (val & mask);
-#if defined(TARGET_MIPS64)
-if ((env->CP0_Status ^ old) & (old & (7 << CP0St_UX))) {
-/* Access to at least one of the 64-bit segments has been disabled */
-tlb_flush(env_cpu(env));
-}
-#endif
-if (ase_mt_available(env)) {
-sync_c0_status(env, env, env->current_tc);
-} else {
-compute_hflags(env);
-}
-}
-
-void cpu_mips_store_cause(CPUMIPSState *env, target_ulong val)
-{
-uint32_t mask = 0x00C00300;
-uint32_t old = env->CP0_Cause;
-int i;
-
-if (env->insn_flags & ISA_MIPS_R2) {
-mask |= 1 << CP0Ca_DC;
-}
-if (env->insn_flags & ISA_MIPS_R6) {
-mask &= ~((1 << CP0Ca_WP) & val);
-}
-
-env->CP0_Cause = (env->CP0_Cause & ~mask) | (val & mask);
-
-if ((old ^ env->CP0_Cause) & (1 << CP0Ca_DC)) {
-if (env->CP0_Cause & (1 << CP0Ca_DC)) {
-cpu_mips_stop_count(env);
-} else {
-cpu_mips_start_count(env);
-}
-}
-
-/* Set/reset software interrupts */
-for (i = 0 ; i < 2 ; i++) {
-if ((old ^ env->CP0_Cause) & (1 << (CP0Ca_IP + i))) {
-cpu_mips_soft_irq(env, i, env->CP0_Cause & (1 << (CP0Ca_IP + i)));
-}
-}
-}
-
-#endif /* !CONFIG_USER_ONLY */
-
 static void fpu_dump_state(CPUMIPSState *env, FILE * f, int flags)
 {
 int i;
diff --git a/target/mips/sysemu/cp0.

[PATCH 19/26] target/mips: Move helper_cache() to tcg/sysemu/special_helper.c

[Philippe Mathieu-Daudé]

Move helper_cache() to tcg/sysemu/special_helper.c.

The CACHE opcode is privileged and is not accessible in user
emulation. However we get a link failure when restricting the
symbol to sysemu. For now, add a stub to satisfy linking, which
abort if ever called.

Signed-off-by: Philippe Mathieu-Daudé 
---
 target/mips/op_helper.c | 35 -
 target/mips/tcg/sysemu/special_helper.c | 33 +++
 target/mips/tcg/user/stubs.c| 29 
 target/mips/tcg/user/meson.build|  1 +
 4 files changed, 63 insertions(+), 35 deletions(-)
 create mode 100644 target/mips/tcg/user/stubs.c

diff --git a/target/mips/op_helper.c b/target/mips/op_helper.c
index 3903545831f..659c4d15668 100644
--- a/target/mips/op_helper.c
+++ b/target/mips/op_helper.c
@@ -789,38 +789,3 @@ void mips_cpu_do_transaction_failed(CPUState *cs, hwaddr 
physaddr,
 }
 }
 #endif /* !CONFIG_USER_ONLY */
-
-void helper_cache(CPUMIPSState *env, target_ulong addr, uint32_t op)
-{
-#ifndef CONFIG_USER_ONLY
-static const char *const type_name[] = {
-"Primary Instruction",
-"Primary Data or Unified Primary",
-"Tertiary",
-"Secondary"
-};
-uint32_t cache_type = extract32(op, 0, 2);
-uint32_t cache_operation = extract32(op, 2, 3);
-target_ulong index = addr & 0x1fff;
-
-switch (cache_operation) {
-case 0b010: /* Index Store Tag */
-memory_region_dispatch_write(env->itc_tag, index, env->CP0_TagLo,
- MO_64, MEMTXATTRS_UNSPECIFIED);
-break;
-case 0b001: /* Index Load Tag */
-memory_region_dispatch_read(env->itc_tag, index, &env->CP0_TagLo,
-MO_64, MEMTXATTRS_UNSPECIFIED);
-break;
-case 0b000: /* Index Invalidate */
-case 0b100: /* Hit Invalidate */
-case 0b110: /* Hit Writeback */
-/* no-op */
-break;
-default:
-qemu_log_mask(LOG_UNIMP, "cache operation:%u (type: %s cache)\n",
-  cache_operation, type_name[cache_type]);
-break;
-}
-#endif
-}
diff --git a/target/mips/tcg/sysemu/special_helper.c 
b/target/mips/tcg/sysemu/special_helper.c
index f2cf7252484..ae8d0d03638 100644
--- a/target/mips/tcg/sysemu/special_helper.c
+++ b/target/mips/tcg/sysemu/special_helper.c
@@ -148,3 +148,36 @@ void helper_deret(CPUMIPSState *env)
 
 debug_post_eret(env);
 }
+
+void helper_cache(CPUMIPSState *env, target_ulong addr, uint32_t op)
+{
+static const char *const type_name[] = {
+"Primary Instruction",
+"Primary Data or Unified Primary",
+"Tertiary",
+"Secondary"
+};
+uint32_t cache_type = extract32(op, 0, 2);
+uint32_t cache_operation = extract32(op, 2, 3);
+target_ulong index = addr & 0x1fff;
+
+switch (cache_operation) {
+case 0b010: /* Index Store Tag */
+memory_region_dispatch_write(env->itc_tag, index, env->CP0_TagLo,
+ MO_64, MEMTXATTRS_UNSPECIFIED);
+break;
+case 0b001: /* Index Load Tag */
+memory_region_dispatch_read(env->itc_tag, index, &env->CP0_TagLo,
+MO_64, MEMTXATTRS_UNSPECIFIED);
+break;
+case 0b000: /* Index Invalidate */
+case 0b100: /* Hit Invalidate */
+case 0b110: /* Hit Writeback */
+/* no-op */
+break;
+default:
+qemu_log_mask(LOG_UNIMP, "cache operation:%u (type: %s cache)\n",
+  cache_operation, type_name[cache_type]);
+break;
+}
+}
diff --git a/target/mips/tcg/user/stubs.c b/target/mips/tcg/user/stubs.c
new file mode 100644
index 000..adb2f8e301b
--- /dev/null
+++ b/target/mips/tcg/user/stubs.c
@@ -0,0 +1,29 @@
+/*
+ *  MIPS emulation helpers for qemu.
+ *
+ *  Copyright (c) 2004-2005 Jocelyn Mayer
+ *
+ * This library is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU Lesser General Public
+ * License as published by the Free Software Foundation; either
+ * version 2.1 of the License, or (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
+ * Lesser General Public License for more details.
+ *
+ * You should have received a copy of the GNU Lesser General Public
+ * License along with this library; if not, see .
+ *
+ */
+
+#include "qemu/osdep.h"
+#include "cpu.h"
+#include "internal.h"
+#include "exec/helper-proto.h"
+
+void helper_cache(CPUMIPSState *env, target_ulong addr, uint32_t op)
+{
+g_assert_not_reached();
+}
diff --git a/target/mips/tcg/user/meson.build b/target/mips/tcg/user/meson.build
index 2fe2062a73b..5f34783bdf2 100644
--- a/target/mips/tcg/user/meson.build
+++ b/target/mips/tcg/user/meson.build
@@ 

[PATCH 25/26] hw/mips: Restrict non-virtualized machines to TCG

[Philippe Mathieu-Daudé]

Only the malta and loongson3-virt machines support KVM.

Restrict the other machines to TCG:

 - mipssim
 - magnum
 - pica61
 - fuloong2e
 - boston

Signed-off-by: Philippe Mathieu-Daudé 
---
 hw/mips/meson.build | 11 +++
 1 file changed, 7 insertions(+), 4 deletions(-)

diff --git a/hw/mips/meson.build b/hw/mips/meson.build
index 1195716dc73..dd0101ad4d8 100644
--- a/hw/mips/meson.build
+++ b/hw/mips/meson.build
@@ -1,12 +1,15 @@
 mips_ss = ss.source_set()
 mips_ss.add(files('bootloader.c', 'mips_int.c'))
 mips_ss.add(when: 'CONFIG_FW_CFG_MIPS', if_true: files('fw_cfg.c'))
-mips_ss.add(when: 'CONFIG_FULOONG', if_true: files('fuloong2e.c'))
 mips_ss.add(when: 'CONFIG_LOONGSON3V', if_true: files('loongson3_bootp.c', 
'loongson3_virt.c'))
-mips_ss.add(when: 'CONFIG_JAZZ', if_true: files('jazz.c'))
 mips_ss.add(when: 'CONFIG_MALTA', if_true: files('gt64xxx_pci.c', 'malta.c'))
-mips_ss.add(when: 'CONFIG_MIPSSIM', if_true: files('mipssim.c'))
-mips_ss.add(when: 'CONFIG_MIPS_BOSTON', if_true: [files('boston.c'), fdt])
 mips_ss.add(when: 'CONFIG_MIPS_CPS', if_true: files('cps.c'))
 
+if 'CONFIG_TCG' in config_all
+mips_ss.add(when: 'CONFIG_JAZZ', if_true: files('jazz.c'))
+mips_ss.add(when: 'CONFIG_MIPSSIM', if_true: files('mipssim.c'))
+mips_ss.add(when: 'CONFIG_FULOONG', if_true: files('fuloong2e.c'))
+mips_ss.add(when: 'CONFIG_MIPS_BOSTON', if_true: [files('boston.c'), fdt])
+endif
+
 hw_arch += {'mips': mips_ss}
-- 
2.26.3

[PATCH 24/26] target/mips: Move TCG source files under tcg/ sub directory

[Philippe Mathieu-Daudé]

To ease maintenance, move all TCG specific files under the tcg/
sub-directory. Adapt the Meson machinery.

The following prototypes:
- mips_tcg_init()
- mips_cpu_do_unaligned_access()
- mips_cpu_do_transaction_failed()
can now be restricted to the "tcg-internal.h" header.

Signed-off-by: Philippe Mathieu-Daudé 
---
 target/mips/internal.h   | 11 ---
 target/mips/tcg/tcg-internal.h   | 11 +++
 target/mips/{ => tcg}/msa_helper.h.inc   |  0
 target/mips/{ => tcg}/mips32r6.decode|  0
 target/mips/{ => tcg}/mips64r6.decode|  0
 target/mips/{ => tcg}/msa32.decode   |  0
 target/mips/{ => tcg}/msa64.decode   |  0
 target/mips/{ => tcg}/tx79.decode|  0
 target/mips/{ => tcg}/dsp_helper.c   |  0
 target/mips/{ => tcg}/exception.c|  0
 target/mips/{ => tcg}/fpu_helper.c   |  0
 target/mips/{ => tcg}/ldst_helper.c  |  0
 target/mips/{ => tcg}/lmmi_helper.c  |  0
 target/mips/{ => tcg}/msa_helper.c   |  0
 target/mips/{ => tcg}/msa_translate.c|  0
 target/mips/{ => tcg}/mxu_translate.c|  0
 target/mips/{ => tcg}/op_helper.c|  0
 target/mips/{ => tcg}/rel6_translate.c   |  0
 target/mips/{ => tcg}/translate.c|  0
 target/mips/{ => tcg}/translate_addr_const.c |  0
 target/mips/{ => tcg}/tx79_translate.c   |  0
 target/mips/{ => tcg}/txx9_translate.c   |  0
 target/mips/meson.build  | 31 
 target/mips/tcg/meson.build  | 29 ++
 24 files changed, 40 insertions(+), 42 deletions(-)
 rename target/mips/{ => tcg}/msa_helper.h.inc (100%)
 rename target/mips/{ => tcg}/mips32r6.decode (100%)
 rename target/mips/{ => tcg}/mips64r6.decode (100%)
 rename target/mips/{ => tcg}/msa32.decode (100%)
 rename target/mips/{ => tcg}/msa64.decode (100%)
 rename target/mips/{ => tcg}/tx79.decode (100%)
 rename target/mips/{ => tcg}/dsp_helper.c (100%)
 rename target/mips/{ => tcg}/exception.c (100%)
 rename target/mips/{ => tcg}/fpu_helper.c (100%)
 rename target/mips/{ => tcg}/ldst_helper.c (100%)
 rename target/mips/{ => tcg}/lmmi_helper.c (100%)
 rename target/mips/{ => tcg}/msa_helper.c (100%)
 rename target/mips/{ => tcg}/msa_translate.c (100%)
 rename target/mips/{ => tcg}/mxu_translate.c (100%)
 rename target/mips/{ => tcg}/op_helper.c (100%)
 rename target/mips/{ => tcg}/rel6_translate.c (100%)
 rename target/mips/{ => tcg}/translate.c (100%)
 rename target/mips/{ => tcg}/translate_addr_const.c (100%)
 rename target/mips/{ => tcg}/tx79_translate.c (100%)
 rename target/mips/{ => tcg}/txx9_translate.c (100%)

diff --git a/target/mips/internal.h b/target/mips/internal.h
index 57eec83384a..0228f37b78c 100644
--- a/target/mips/internal.h
+++ b/target/mips/internal.h
@@ -82,9 +82,6 @@ extern const int mips_defs_number;
 
 int mips_cpu_gdb_read_register(CPUState *cpu, GByteArray *buf, int reg);
 int mips_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg);
-void mips_cpu_do_unaligned_access(CPUState *cpu, vaddr addr,
-  MMUAccessType access_type,
-  int mmu_idx, uintptr_t retaddr);
 
 #define USEG_LIMIT  ((target_ulong)(int32_t)0x7FFFUL)
 #define KSEG0_BASE  ((target_ulong)(int32_t)0x8000UL)
@@ -151,12 +148,6 @@ struct CPUMIPSTLBContext {
 } mmu;
 };
 
-void mips_cpu_do_transaction_failed(CPUState *cs, hwaddr physaddr,
-vaddr addr, unsigned size,
-MMUAccessType access_type,
-int mmu_idx, MemTxAttrs attrs,
-MemTxResult response, uintptr_t retaddr);
-
 void sync_c0_status(CPUMIPSState *env, CPUMIPSState *cpu, int tc);
 void cpu_mips_store_status(CPUMIPSState *env, target_ulong val);
 void cpu_mips_store_cause(CPUMIPSState *env, target_ulong val);
@@ -209,8 +200,6 @@ static inline bool 
cpu_mips_hw_interrupts_pending(CPUMIPSState *env)
 return r;
 }
 
-void mips_tcg_init(void);
-
 void msa_reset(CPUMIPSState *env);
 
 /* cp0_timer.c */
diff --git a/target/mips/tcg/tcg-internal.h b/target/mips/tcg/tcg-internal.h
index 70f0d5da436..ae9b35ff706 100644
--- a/target/mips/tcg/tcg-internal.h
+++ b/target/mips/tcg/tcg-internal.h
@@ -11,15 +11,21 @@
 #define MIPS_TCG_INTERNAL_H
 
 #include "tcg/tcg.h"
+#include "exec/memattrs.h"
 #include "hw/core/cpu.h"
 #include "cpu.h"
 
+void mips_tcg_init(void);
+
 void mips_cpu_synchronize_from_tb(CPUState *cs, const TranslationBlock *tb);
 void mips_cpu_do_interrupt(CPUState *cpu);
 bool mips_cpu_exec_interrupt(CPUState *cpu, int int_req);
 bool mips_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
MMUAccessType access_type, int mmu_idx,
bool probe, uintptr_t retaddr);
+void mips_cpu_do_unaligned_access(CPUState *cpu, vaddr addr,
+  MM

[PATCH 21/26] target/mips: Move exception management code to exception.c

[Philippe Mathieu-Daudé]

Signed-off-by: Philippe Mathieu-Daudé 
---
 target/mips/internal.h |  13 ---
 target/mips/tcg/tcg-internal.h |  14 +++
 target/mips/cpu.c  | 113 --
 target/mips/exception.c| 169 +
 target/mips/op_helper.c|  37 
 target/mips/meson.build|   1 +
 6 files changed, 184 insertions(+), 163 deletions(-)
 create mode 100644 target/mips/exception.c

diff --git a/target/mips/internal.h b/target/mips/internal.h
index b3f945f6cad..1e085b0625c 100644
--- a/target/mips/internal.h
+++ b/target/mips/internal.h
@@ -80,7 +80,6 @@ extern const char * const fregnames[32];
 extern const struct mips_def_t mips_defs[];
 extern const int mips_defs_number;
 
-bool mips_cpu_exec_interrupt(CPUState *cpu, int int_req);
 int mips_cpu_gdb_read_register(CPUState *cpu, GByteArray *buf, int reg);
 int mips_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg);
 void mips_cpu_do_unaligned_access(CPUState *cpu, vaddr addr,
@@ -400,16 +399,4 @@ void sync_c0_status(CPUMIPSState *env, CPUMIPSState *cpu, 
int tc);
 void cpu_mips_store_status(CPUMIPSState *env, target_ulong val);
 void cpu_mips_store_cause(CPUMIPSState *env, target_ulong val);
 
-const char *mips_exception_name(int32_t exception);
-
-void QEMU_NORETURN do_raise_exception_err(CPUMIPSState *env, uint32_t 
exception,
-  int error_code, uintptr_t pc);
-
-static inline void QEMU_NORETURN do_raise_exception(CPUMIPSState *env,
-uint32_t exception,
-uintptr_t pc)
-{
-do_raise_exception_err(env, exception, 0, pc);
-}
-
 #endif
diff --git a/target/mips/tcg/tcg-internal.h b/target/mips/tcg/tcg-internal.h
index e507dd1630f..70f0d5da436 100644
--- a/target/mips/tcg/tcg-internal.h
+++ b/target/mips/tcg/tcg-internal.h
@@ -14,11 +14,25 @@
 #include "hw/core/cpu.h"
 #include "cpu.h"
 
+void mips_cpu_synchronize_from_tb(CPUState *cs, const TranslationBlock *tb);
 void mips_cpu_do_interrupt(CPUState *cpu);
+bool mips_cpu_exec_interrupt(CPUState *cpu, int int_req);
 bool mips_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
MMUAccessType access_type, int mmu_idx,
bool probe, uintptr_t retaddr);
 
+const char *mips_exception_name(int32_t exception);
+
+void QEMU_NORETURN do_raise_exception_err(CPUMIPSState *env, uint32_t 
exception,
+  int error_code, uintptr_t pc);
+
+static inline void QEMU_NORETURN do_raise_exception(CPUMIPSState *env,
+uint32_t exception,
+uintptr_t pc)
+{
+do_raise_exception_err(env, exception, 0, pc);
+}
+
 #if !defined(CONFIG_USER_ONLY)
 
 void mmu_init(CPUMIPSState *env, const mips_def_t *def);
diff --git a/target/mips/cpu.c b/target/mips/cpu.c
index e756d75667f..38328ba0927 100644
--- a/target/mips/cpu.c
+++ b/target/mips/cpu.c
@@ -222,112 +222,12 @@ static void mips_cpu_dump_state(CPUState *cs, FILE *f, 
int flags)
 }
 }
 
-static const char * const excp_names[EXCP_LAST + 1] = {
-[EXCP_RESET] = "reset",
-[EXCP_SRESET] = "soft reset",
-[EXCP_DSS] = "debug single step",
-[EXCP_DINT] = "debug interrupt",
-[EXCP_NMI] = "non-maskable interrupt",
-[EXCP_MCHECK] = "machine check",
-[EXCP_EXT_INTERRUPT] = "interrupt",
-[EXCP_DFWATCH] = "deferred watchpoint",
-[EXCP_DIB] = "debug instruction breakpoint",
-[EXCP_IWATCH] = "instruction fetch watchpoint",
-[EXCP_AdEL] = "address error load",
-[EXCP_AdES] = "address error store",
-[EXCP_TLBF] = "TLB refill",
-[EXCP_IBE] = "instruction bus error",
-[EXCP_DBp] = "debug breakpoint",
-[EXCP_SYSCALL] = "syscall",
-[EXCP_BREAK] = "break",
-[EXCP_CpU] = "coprocessor unusable",
-[EXCP_RI] = "reserved instruction",
-[EXCP_OVERFLOW] = "arithmetic overflow",
-[EXCP_TRAP] = "trap",
-[EXCP_FPE] = "floating point",
-[EXCP_DDBS] = "debug data break store",
-[EXCP_DWATCH] = "data watchpoint",
-[EXCP_LTLBL] = "TLB modify",
-[EXCP_TLBL] = "TLB load",
-[EXCP_TLBS] = "TLB store",
-[EXCP_DBE] = "data bus error",
-[EXCP_DDBL] = "debug data break load",
-[EXCP_THREAD] = "thread",
-[EXCP_MDMX] = "MDMX",
-[EXCP_C2E] = "precise coprocessor 2",
-[EXCP_CACHE] = "cache error",
-[EXCP_TLBXI] = "TLB execute-inhibit",
-[EXCP_TLBRI] = "TLB read-inhibit",
-[EXCP_MSADIS] = "MSA disabled",
-[EXCP_MSAFPE] = "MSA floating point",
-};
-
-const char *mips_exception_name(int32_t exception)
-{
-if (exception < 0 || exception > EXCP_LAST) {
-return "unknown";
-}
-return excp_names[exception];
-}
-
 void cpu_set_exception_base(int vp_index, target_ulong address)
 {
 MIPSCPU *vp = MIPS_CPU(qemu_get_cpu(vp_index));
 vp->env.exception_base = address;
 }
 
-

[PATCH 26/26] gitlab-ci: Add KVM mips64el cross-build jobs

[Philippe Mathieu-Daudé]

Add a new job to cross-build the mips64el target without
the TCG accelerator (IOW: only KVM accelerator enabled).

Only build the mips64el target which is known to work
and has users.

Signed-off-by: Philippe Mathieu-Daudé 
---
 .gitlab-ci.d/crossbuilds.yml | 8 
 1 file changed, 8 insertions(+)

diff --git a/.gitlab-ci.d/crossbuilds.yml b/.gitlab-ci.d/crossbuilds.yml
index 2d95784ed51..e44e4b49a25 100644
--- a/.gitlab-ci.d/crossbuilds.yml
+++ b/.gitlab-ci.d/crossbuilds.yml
@@ -176,6 +176,14 @@ cross-s390x-kvm-only:
 IMAGE: debian-s390x-cross
 ACCEL_CONFIGURE_OPTS: --disable-tcg
 
+cross-mips64el-kvm-only:
+  extends: .cross_accel_build_job
+  needs:
+job: mips64el-debian-cross-container
+  variables:
+IMAGE: debian-mips64el-cross
+ACCEL_CONFIGURE_OPTS: --disable-tcg --target-list=mips64el-softmmu
+
 cross-win32-system:
   extends: .cross_system_build_job
   needs:
-- 
2.26.3

Re: [PATCH 00/26] target/mips: Re-org to allow KVM-only builds

[no-reply]

Patchew URL: https://patchew.org/QEMU/20210418163134.1133100-1-f4...@amsat.org/



Hi,

This series seems to have some coding style problems. See output below for
more information:

Type: series
Message-id: 20210418163134.1133100-1-f4...@amsat.org
Subject: [PATCH 00/26] target/mips: Re-org to allow KVM-only builds

=== TEST SCRIPT BEGIN ===
#!/bin/bash
git rev-parse base > /dev/null || exit 0
git config --local diff.renamelimit 0
git config --local diff.renames True
git config --local diff.algorithm histogram
./scripts/checkpatch.pl --mailback base..
=== TEST SCRIPT END ===

Updating 3c8cf5a9c21ff8782164d1def7f44bd888713384
From https://github.com/patchew-project/qemu
 - [tag update]  patchew/20210417194205.17057-1-peter.mayd...@linaro.org -> 
patchew/20210417194205.17057-1-peter.mayd...@linaro.org
 * [new tag] patchew/20210418163134.1133100-1-f4...@amsat.org -> 
patchew/20210418163134.1133100-1-f4...@amsat.org
Switched to a new branch 'test'
ec4a066 gitlab-ci: Add KVM mips64el cross-build jobs
0f39b27 hw/mips: Restrict non-virtualized machines to TCG
d91a8b3 target/mips: Move TCG source files under tcg/ sub directory
c83fb11 target/mips: Move helper.h -> tcg/helper.h.inc
c6e95b9 target/mips: Move CP0 helpers to sysemu/cp0.c
2d3b5d6 target/mips: Move exception management code to exception.c
78d355a target/mips: Move TLB management helpers to tcg/sysemu/tlb_helper.c
51e44c9 target/mips: Move helper_cache() to tcg/sysemu/special_helper.c
db846de target/mips: Move Special opcodes to tcg/sysemu/special_helper.c
7d440db target/mips: Restrict CPUMIPSTLBContext::map_address() handlers scope
6d61110 target/mips: Move tlb_helper.c to tcg/sysemu/
8f68aad target/mips: Restrict mmu_init() to TCG
7f51b6e target/mips: Move sysemu TCG-specific code to tcg/sysemu/ subfolder
4a8000c target/mips: Move code related to physical addressing to sysemu/phys.c
17eb078 target/mips: Move sysemu specific files under sysemu/ subfolder
2557ee2 target/mips: Move cpu_signal_handler definition around
2945a42 target/mips: Add simple user-mode mips_cpu_tlb_fill()
5dc00af target/mips: Add simple user-mode mips_cpu_do_interrupt()
1dee23e target/mips: Introduce tcg-internal.h for TCG specific declarations
d553454 meson: Introduce meson_user_arch source set for arch-specific user-mode
061bc56 target/mips: Extract load/store helpers to ldst_helper.c
55fbc48 target/mips: Restrict mips_cpu_dump_state() to cpu.c
1b28dda target/mips: Make CPU/FPU regnames[] arrays global
c920bad target/mips: Move msa_reset() to new source file
5af6fa7 target/mips: Move IEEE rounding mode array to new source file
990b30d target/mips: Simplify meson TCG rules

=== OUTPUT BEGIN ===
1/26 Checking commit 990b30d220a6 (target/mips: Simplify meson TCG rules)
2/26 Checking commit 5af6fa7b1717 (target/mips: Move IEEE rounding mode array 
to new source file)
Use of uninitialized value $acpi_testexpected in string eq at 
./scripts/checkpatch.pl line 1529.
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#30: 
new file mode 100644

total: 0 errors, 1 warnings, 39 lines checked

Patch 2/26 has style problems, please review.  If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
3/26 Checking commit c920bad76ffc (target/mips: Move msa_reset() to new source 
file)
Use of uninitialized value $acpi_testexpected in string eq at 
./scripts/checkpatch.pl line 1529.
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#36: 
new file mode 100644

total: 0 errors, 1 warnings, 70 lines checked

Patch 3/26 has style problems, please review.  If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
4/26 Checking commit 1b28ddabf976 (target/mips: Make CPU/FPU regnames[] arrays 
global)
5/26 Checking commit 55fbc48fe4bd (target/mips: Restrict mips_cpu_dump_state() 
to cpu.c)
6/26 Checking commit 061bc56c2038 (target/mips: Extract load/store helpers to 
ldst_helper.c)
Use of uninitialized value $acpi_testexpected in string eq at 
./scripts/checkpatch.pl line 1529.
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#17: 
new file mode 100644

total: 0 errors, 1 warnings, 591 lines checked

Patch 6/26 has style problems, please review.  If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
7/26 Checking commit d55345471b37 (meson: Introduce meson_user_arch source set 
for arch-specific user-mode)
8/26 Checking commit 1dee23e2dc56 (target/mips: Introduce tcg-internal.h for 
TCG specific declarations)
Use of uninitialized value $acpi_testexpected in string eq at 
./scripts/checkpatch.pl line 1529.
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#53: 
new file mode 100644

total: 0 errors, 1 warnings, 45 lines checked

Patch 8/26 has style problems, please review.  If any of these errors
are false positives report them to the maintainer, see
CHECK

[PATCH v2] hw/mips/jazz: Remove confusing ifdef'ry

[Philippe Mathieu-Daudé]

The jazz machine is not used under user emulation and
does not support KVM. Simplify the ifdef'ry.

Signed-off-by: Philippe Mathieu-Daudé 
Reviewed-by: Richard Henderson 
Reviewed-by: Claudio Fontana 
Message-Id: <20210226132723.3969650-3-f4...@amsat.org>
---
v2: Rebased.

Based-on: <20210418163134.1133100-1-f4...@amsat.org>
---
 hw/mips/jazz.c | 4 
 1 file changed, 4 deletions(-)

diff --git a/hw/mips/jazz.c b/hw/mips/jazz.c
index 1a0888a0fd5..29d32ef516f 100644
--- a/hw/mips/jazz.c
+++ b/hw/mips/jazz.c
@@ -120,7 +120,6 @@ static const MemoryRegionOps dma_dummy_ops = {
 #define MAGNUM_BIOS_SIZE   
\
 (BIOS_SIZE < MAGNUM_BIOS_SIZE_MAX ? BIOS_SIZE : MAGNUM_BIOS_SIZE_MAX)
 
-#if defined(CONFIG_TCG) && !defined(CONFIG_USER_ONLY)
 static void (*real_do_transaction_failed)(CPUState *cpu, hwaddr physaddr,
   vaddr addr, unsigned size,
   MMUAccessType access_type,
@@ -142,7 +141,6 @@ static void mips_jazz_do_transaction_failed(CPUState *cs, 
hwaddr physaddr,
 (*real_do_transaction_failed)(cs, physaddr, addr, size, access_type,
   mmu_idx, attrs, response, retaddr);
 }
-#endif /* CONFIG_TCG && !CONFIG_USER_ONLY */
 
 static void mips_jazz_init(MachineState *machine,
enum jazz_model_e jazz_model)
@@ -211,10 +209,8 @@ static void mips_jazz_init(MachineState *machine,
  * memory region that catches all memory accesses, as we do on Malta.
  */
 cc = CPU_GET_CLASS(cpu);
-#if defined(CONFIG_TCG) && !defined(CONFIG_USER_ONLY)
 real_do_transaction_failed = cc->tcg_ops->do_transaction_failed;
 cc->tcg_ops->do_transaction_failed = mips_jazz_do_transaction_failed;
-#endif /* CONFIG_TCG && !CONFIG_USER_ONLY */
 
 /* allocate RAM */
 memory_region_add_subregion(address_space, 0, machine->ram);
-- 
2.26.3

Re: [PATCH v2] hw/mips/jazz: Remove confusing ifdef'ry

[Richard Henderson]

On 4/18/21 9:51 AM, Philippe Mathieu-Daudé wrote:

The jazz machine is not used under user emulation and
does not support KVM. Simplify the ifdef'ry.

Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: Richard Henderson
Reviewed-by: Claudio Fontana
Message-Id:<20210226132723.3969650-3-f4...@amsat.org>
---
v2: Rebased.

Based-on:<20210418163134.1133100-1-f4...@amsat.org>
---
  hw/mips/jazz.c | 4 
  1 file changed, 4 deletions(-)


Were you going to apply this one before my cleanup to completely remove this 
hook manipulation?


https://patchew.org/QEMU/20210227232519.222663-1-richard.hender...@linaro.org/20210227232519.222663-2-richard.hender...@linaro.org/


r~

Re: [PATCH 01/26] target/mips: Simplify meson TCG rules

[Richard Henderson]

On 4/18/21 9:31 AM, Philippe Mathieu-Daudé wrote:

We already have the mips_tcg_ss source set for TCG-specific files,
use it for mxu_translate.c and tx79_translate.c to simplify a bit.

Signed-off-by: Philippe Mathieu-Daudé
---
  target/mips/meson.build | 5 ++---
  1 file changed, 2 insertions(+), 3 deletions(-)


Reviewed-by: Richard Henderson 

r~

Re: [PATCH 02/26] target/mips: Move IEEE rounding mode array to new source file

[Richard Henderson]

On 4/18/21 9:31 AM, Philippe Mathieu-Daudé wrote:

restore_msa_fp_status() is declared inlined in fpu_helper.h,
and uses the ieee_rm[] array. Therefore any code calling
restore_msa_fp_status() must have access to this ieee_rm[] array.

kvm_mips_get_fpu_registers(), which is in target/mips/kvm.c,
calls restore_msa_fp_status.

Except this tiny array, the rest of fpu_helper.c is only useful
for the TCG accelerator.

To be able to restrict fpu_helper.c to TCG, we need to move the
ieee_rm[] array to a new source file.

Signed-off-by: Philippe Mathieu-Daudé
---
  target/mips/fpu.c| 18 ++
  target/mips/fpu_helper.c |  8 
  target/mips/meson.build  |  1 +
  3 files changed, 19 insertions(+), 8 deletions(-)
  create mode 100644 target/mips/fpu.c


Reviewed-by: Richard Henderson 

r~

Re: [PATCH 03/26] target/mips: Move msa_reset() to new source file

[Richard Henderson]

On 4/18/21 9:31 AM, Philippe Mathieu-Daudé wrote:

mips_cpu_reset() is used by all accelerators, and calls
msa_reset(), which is defined in msa_helper.c.

Beside msa_reset(), the rest of msa_helper.c is only useful
to the TCG accelerator. To be able to restrict this helper
file to TCG, we need to move msa_reset() out of it.

Signed-off-by: Philippe Mathieu-Daudé
---
  target/mips/msa.c| 60 
  target/mips/msa_helper.c | 36 
  target/mips/meson.build  |  1 +
  3 files changed, 61 insertions(+), 36 deletions(-)
  create mode 100644 target/mips/msa.c


Reviewed-by: Richard Henderson 

Re: [PATCH 04/26] target/mips: Make CPU/FPU regnames[] arrays global

[Richard Henderson]

On 4/18/21 9:31 AM, Philippe Mathieu-Daudé wrote:

+const char * const regnames[32] = {
+"r0", "at", "v0", "v1", "a0", "a1", "a2", "a3",
+"t0", "t1", "t2", "t3", "t4", "t5", "t6", "t7",
+"s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7",
+"t8", "t9", "k0", "k1", "gp", "sp", "s8", "ra",
+};
+
  #if !defined(CONFIG_USER_ONLY)
  
  /* Called for updates to CP0_Status.  */

diff --git a/target/mips/fpu.c b/target/mips/fpu.c
index 39a2f7fd22e..1447dba3fa3 100644
--- a/target/mips/fpu.c
+++ b/target/mips/fpu.c
@@ -16,3 +16,10 @@ const FloatRoundMode ieee_rm[4] = {
  float_round_up,
  float_round_down
  };
+
+const char * const fregnames[32] = {
+"f0",  "f1",  "f2",  "f3",  "f4",  "f5",  "f6",  "f7",
+"f8",  "f9",  "f10", "f11", "f12", "f13", "f14", "f15",
+"f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23",
+"f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31",
+};


Code motion, so,
Reviewed-by: Richard Henderson 

but I'll note that you can save space and pie runtime relocations by using

const char {f,}regnames[32][4]

since all entries are no more than 4 bytes including nul terminator.


r~

Re: [PATCH 05/26] target/mips: Restrict mips_cpu_dump_state() to cpu.c

[Richard Henderson]

On 4/18/21 9:31 AM, Philippe Mathieu-Daudé wrote:

As mips_cpu_dump_state() is only used once to initialize the
CPUClass::dump_state handler, we can move it to cpu.c to keep
it symbol local.
Beside, this handler is used by all accelerators, while the
translate.c file targets TCG.

Signed-off-by: Philippe Mathieu-Daudé 
---
  target/mips/internal.h  |  1 -
  target/mips/cpu.c   | 77 +
  target/mips/translate.c | 77 -
  3 files changed, 77 insertions(+), 78 deletions(-)

diff --git a/target/mips/internal.h b/target/mips/internal.h
index a8644f754a6..1c5674935aa 100644
--- a/target/mips/internal.h
+++ b/target/mips/internal.h
@@ -79,7 +79,6 @@ extern const int mips_defs_number;
  
  void mips_cpu_do_interrupt(CPUState *cpu);

  bool mips_cpu_exec_interrupt(CPUState *cpu, int int_req);
-void mips_cpu_dump_state(CPUState *cpu, FILE *f, int flags);
  hwaddr mips_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr);
  int mips_cpu_gdb_read_register(CPUState *cpu, GByteArray *buf, int reg);
  int mips_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg);
diff --git a/target/mips/cpu.c b/target/mips/cpu.c
index f354d18aec4..ac38a3262ca 100644
--- a/target/mips/cpu.c
+++ b/target/mips/cpu.c
@@ -145,6 +145,83 @@ void cpu_mips_store_cause(CPUMIPSState *env, target_ulong 
val)
  
  #endif /* !CONFIG_USER_ONLY */
  
+static void fpu_dump_state(CPUMIPSState *env, FILE * f, int flags)

+{
+int i;
+int is_fpu64 = !!(env->hflags & MIPS_HFLAG_F64);
+
+#define printfpr(fp)\
+do {\
+if (is_fpu64)   \
+qemu_fprintf(f, "w:%08x d:%016" PRIx64  \
+ " fd:%13g fs:%13g psu: %13g\n",\
+ (fp)->w[FP_ENDIAN_IDX], (fp)->d,   \
+ (double)(fp)->fd,  \
+ (double)(fp)->fs[FP_ENDIAN_IDX],   \
+ (double)(fp)->fs[!FP_ENDIAN_IDX]); \
+else {  \
+fpr_t tmp;  \
+tmp.w[FP_ENDIAN_IDX] = (fp)->w[FP_ENDIAN_IDX];  \
+tmp.w[!FP_ENDIAN_IDX] = ((fp) + 1)->w[FP_ENDIAN_IDX];   \
+qemu_fprintf(f, "w:%08x d:%016" PRIx64  \
+ " fd:%13g fs:%13g psu:%13g\n", \
+ tmp.w[FP_ENDIAN_IDX], tmp.d,   \
+ (double)tmp.fd,\
+ (double)tmp.fs[FP_ENDIAN_IDX], \
+ (double)tmp.fs[!FP_ENDIAN_IDX]);   \
+}   \
+} while (0)
+


Code motion, so,
Reviewed-by: Richard Henderson 



+
+qemu_fprintf(f,
+ "CP1 FCR0 0x%08x  FCR31 0x%08x  SR.FR %d  fp_status 0x%02x\n",
+ env->active_fpu.fcr0, env->active_fpu.fcr31, is_fpu64,
+ get_float_exception_flags(&env->active_fpu.fp_status));
+for (i = 0; i < 32; (is_fpu64) ? i++ : (i += 2)) {
+qemu_fprintf(f, "%3s: ", fregnames[i]);
+printfpr(&env->active_fpu.fpr[i]);


... but since this macro has exacly one use, can we just inline it here?  Or 
turn it into a proper function?



r~

Re: [PATCH 06/26] target/mips: Extract load/store helpers to ldst_helper.c

[Richard Henderson]

On 4/18/21 9:31 AM, Philippe Mathieu-Daudé wrote:

+static inline hwaddr do_translate_address(CPUMIPSState *env,
+  target_ulong address,
+  MMUAccessType access_type,
+  uintptr_t retaddr)
+{
+hwaddr paddr;
+CPUState *cs = env_cpu(env);
+
+paddr = cpu_mips_translate_address(env, address, access_type);
+
+if (paddr == -1LL) {
+cpu_loop_exit_restore(cs, retaddr);
+} else {
+return paddr;
+}
+}


Code motion, so,
Reviewed-by: Richard Henderson 

but I think that it's a mistake for cpu_mips_translate_address to split the 
raise_mmu_exception from the cpu_loop_exit_restore.  If you make the changes to 
env to indicate the exception, you *must* then go back to the main loop.


There seems to be exactly one caller, this one, so it should be trivial to 
change, which the lets do_translate_address vanish entirely.



r~

Re: [PATCH 07/26] meson: Introduce meson_user_arch source set for arch-specific user-mode

[Richard Henderson]

On 4/18/21 9:31 AM, Philippe Mathieu-Daudé wrote:

Similarly to the 'target_softmmu_arch' source set which allows
to restrict target-specific sources to system emulation, add
the equivalent 'meson_user_arch' set for user emulation.


You didn't call it meson_user_arch in the end.  Last minute change?
Otherwise,
Reviewed-by: Richard Henderson 


r~



Signed-off-by: Philippe Mathieu-Daudé 
---
Cc: Paolo Bonzini 
---
  meson.build | 6 ++
  1 file changed, 6 insertions(+)

diff --git a/meson.build b/meson.build
index d8bb1ec5aa9..1ffdc9e6c4e 100644
--- a/meson.build
+++ b/meson.build
@@ -1751,6 +1751,7 @@
  hw_arch = {}
  target_arch = {}
  target_softmmu_arch = {}
+target_user_arch = {}
  
  ###

  # Trace files #
@@ -2168,6 +2169,11 @@
  abi = config_target['TARGET_ABI_DIR']
  target_type='user'
  qemu_target_name = 'qemu-' + target_name
+if arch in target_user_arch
+  t = target_user_arch[arch].apply(config_target, strict: false)
+  arch_srcs += t.sources()
+  arch_deps += t.dependencies()
+endif
  if 'CONFIG_LINUX_USER' in config_target
base_dir = 'linux-user'
target_inc += include_directories('linux-user/host/' / 
config_host['ARCH'])

Re: [PATCH 11/26] target/mips: Move cpu_signal_handler definition around

[Richard Henderson]

On 4/18/21 9:31 AM, Philippe Mathieu-Daudé wrote:

We have 2 blocks guarded with #ifdef for sysemu, which
are simply separated by the cpu_signal_handler definition.

To simplify the following commits which involve various
changes in internal.h, first join the sysemu-guarded blocks.

Signed-off-by: Philippe Mathieu-Daudé
---
  target/mips/internal.h | 9 -
  1 file changed, 4 insertions(+), 5 deletions(-)


Reviewed-by: Richard Henderson 

r~

Re: [PATCH 08/26] target/mips: Introduce tcg-internal.h for TCG specific declarations

[Richard Henderson]

On 4/18/21 9:31 AM, Philippe Mathieu-Daudé wrote:

We will gradually move TCG-specific declarations to a new local
header: "tcg-internal.h". To keep review simple, first add this
header with 2 TCG prototypes, which we are going to move in the
next 2 commits.

Signed-off-by: Philippe Mathieu-Daudé
---
  target/mips/internal.h |  7 +++
  target/mips/tcg/tcg-internal.h | 20 
  2 files changed, 23 insertions(+), 4 deletions(-)
  create mode 100644 target/mips/tcg/tcg-internal.h


Reviewed-by: Richard Henderson 

r~

Re: [PATCH 12/26] target/mips: Move sysemu specific files under sysemu/ subfolder

[Richard Henderson]

On 4/18/21 9:31 AM, Philippe Mathieu-Daudé wrote:

Move sysemu-specific files under the new sysemu/ subfolder
and adapt the Meson machinery.

Signed-off-by: Philippe Mathieu-Daudé
---
  target/mips/{ => sysemu}/addr.c  |  0
  target/mips/{ => sysemu}/cp0_timer.c |  0
  target/mips/{ => sysemu}/machine.c   |  0
  target/mips/meson.build  | 12 ++--
  target/mips/sysemu/meson.build   |  5 +
  5 files changed, 11 insertions(+), 6 deletions(-)
  rename target/mips/{ => sysemu}/addr.c (100%)
  rename target/mips/{ => sysemu}/cp0_timer.c (100%)
  rename target/mips/{ => sysemu}/machine.c (100%)
  create mode 100644 target/mips/sysemu/meson.build


Reviewed-by: Richard Henderson 

r~

Re: [PATCH 13/26] target/mips: Move code related to physical addressing to sysemu/phys.c

[Richard Henderson]

On 4/18/21 9:31 AM, Philippe Mathieu-Daudé wrote:

Declare get_physical_address() with local scope and move it along
with mips_cpu_get_phys_page_debug() to sysemu/phys.c new file.


You used physaddr.c in the end.  Otherwise,
Reviewed-by: Richard Henderson 


r~



Signed-off-by: Philippe Mathieu-Daudé
---
  target/mips/internal.h |  25 +++-
  target/mips/sysemu/physaddr.c  | 257 +
  target/mips/tlb_helper.c   | 254 
  target/mips/sysemu/meson.build |   1 +
  4 files changed, 282 insertions(+), 255 deletions(-)
  create mode 100644 target/mips/sysemu/physaddr.c

Re: [PATCH 14/26] target/mips: Move sysemu TCG-specific code to tcg/sysemu/ subfolder

[Richard Henderson]

On 4/18/21 9:31 AM, Philippe Mathieu-Daudé wrote:

Declare cpu_mips_get_random() and update_pagemask() on local scope,


What is "local scope"?  Anyway, I don't see what this has to do with the rest 
of the code movement.



r~


and move cp0_helper.c and mips-semi.c to the new tcg/sysemu/ folder,
adapting the Meson machinery.

Move the opcode definitions to tcg/sysemu_helper.h.inc.

Signed-off-by: Philippe Mathieu-Daudé 
---
  target/mips/helper.h  | 166 +
  target/mips/internal.h|   4 -
  target/mips/tcg/tcg-internal.h|   9 ++
  target/mips/tcg/sysemu_helper.h.inc   | 168 ++
  target/mips/{ => tcg/sysemu}/cp0_helper.c |   0
  target/mips/{ => tcg/sysemu}/mips-semi.c  |   0
  target/mips/meson.build   |   5 -
  target/mips/tcg/meson.build   |   3 +
  target/mips/tcg/sysemu/meson.build|   4 +
  9 files changed, 188 insertions(+), 171 deletions(-)
  create mode 100644 target/mips/tcg/sysemu_helper.h.inc
  rename target/mips/{ => tcg/sysemu}/cp0_helper.c (100%)
  rename target/mips/{ => tcg/sysemu}/mips-semi.c (100%)
  create mode 100644 target/mips/tcg/sysemu/meson.build

diff --git a/target/mips/helper.h b/target/mips/helper.h
index 709494445dd..bc308e5db13 100644
--- a/target/mips/helper.h
+++ b/target/mips/helper.h
@@ -2,10 +2,6 @@ DEF_HELPER_3(raise_exception_err, noreturn, env, i32, int)
  DEF_HELPER_2(raise_exception, noreturn, env, i32)
  DEF_HELPER_1(raise_exception_debug, noreturn, env)
  
-#ifndef CONFIG_USER_ONLY

-DEF_HELPER_1(do_semihosting, void, env)
-#endif
-
  #ifdef TARGET_MIPS64
  DEF_HELPER_4(sdl, void, env, tl, tl, int)
  DEF_HELPER_4(sdr, void, env, tl, tl, int)
@@ -42,164 +38,6 @@ DEF_HELPER_FLAGS_1(dbitswap, TCG_CALL_NO_RWG_SE, tl, tl)
  
  DEF_HELPER_FLAGS_4(rotx, TCG_CALL_NO_RWG_SE, tl, tl, i32, i32, i32)
  
-#ifndef CONFIG_USER_ONLY

-/* CP0 helpers */
-DEF_HELPER_1(mfc0_mvpcontrol, tl, env)
-DEF_HELPER_1(mfc0_mvpconf0, tl, env)
-DEF_HELPER_1(mfc0_mvpconf1, tl, env)
-DEF_HELPER_1(mftc0_vpecontrol, tl, env)
-DEF_HELPER_1(mftc0_vpeconf0, tl, env)
-DEF_HELPER_1(mfc0_random, tl, env)
-DEF_HELPER_1(mfc0_tcstatus, tl, env)
-DEF_HELPER_1(mftc0_tcstatus, tl, env)
-DEF_HELPER_1(mfc0_tcbind, tl, env)
-DEF_HELPER_1(mftc0_tcbind, tl, env)
-DEF_HELPER_1(mfc0_tcrestart, tl, env)
-DEF_HELPER_1(mftc0_tcrestart, tl, env)
-DEF_HELPER_1(mfc0_tchalt, tl, env)
-DEF_HELPER_1(mftc0_tchalt, tl, env)
-DEF_HELPER_1(mfc0_tccontext, tl, env)
-DEF_HELPER_1(mftc0_tccontext, tl, env)
-DEF_HELPER_1(mfc0_tcschedule, tl, env)
-DEF_HELPER_1(mftc0_tcschedule, tl, env)
-DEF_HELPER_1(mfc0_tcschefback, tl, env)
-DEF_HELPER_1(mftc0_tcschefback, tl, env)
-DEF_HELPER_1(mfc0_count, tl, env)
-DEF_HELPER_1(mfc0_saar, tl, env)
-DEF_HELPER_1(mfhc0_saar, tl, env)
-DEF_HELPER_1(mftc0_entryhi, tl, env)
-DEF_HELPER_1(mftc0_status, tl, env)
-DEF_HELPER_1(mftc0_cause, tl, env)
-DEF_HELPER_1(mftc0_epc, tl, env)
-DEF_HELPER_1(mftc0_ebase, tl, env)
-DEF_HELPER_2(mftc0_configx, tl, env, tl)
-DEF_HELPER_1(mfc0_lladdr, tl, env)
-DEF_HELPER_1(mfc0_maar, tl, env)
-DEF_HELPER_1(mfhc0_maar, tl, env)
-DEF_HELPER_2(mfc0_watchlo, tl, env, i32)
-DEF_HELPER_2(mfc0_watchhi, tl, env, i32)
-DEF_HELPER_2(mfhc0_watchhi, tl, env, i32)
-DEF_HELPER_1(mfc0_debug, tl, env)
-DEF_HELPER_1(mftc0_debug, tl, env)
-#ifdef TARGET_MIPS64
-DEF_HELPER_1(dmfc0_tcrestart, tl, env)
-DEF_HELPER_1(dmfc0_tchalt, tl, env)
-DEF_HELPER_1(dmfc0_tccontext, tl, env)
-DEF_HELPER_1(dmfc0_tcschedule, tl, env)
-DEF_HELPER_1(dmfc0_tcschefback, tl, env)
-DEF_HELPER_1(dmfc0_lladdr, tl, env)
-DEF_HELPER_1(dmfc0_maar, tl, env)
-DEF_HELPER_2(dmfc0_watchlo, tl, env, i32)
-DEF_HELPER_2(dmfc0_watchhi, tl, env, i32)
-DEF_HELPER_1(dmfc0_saar, tl, env)
-#endif /* TARGET_MIPS64 */
-
-DEF_HELPER_2(mtc0_index, void, env, tl)
-DEF_HELPER_2(mtc0_mvpcontrol, void, env, tl)
-DEF_HELPER_2(mtc0_vpecontrol, void, env, tl)
-DEF_HELPER_2(mttc0_vpecontrol, void, env, tl)
-DEF_HELPER_2(mtc0_vpeconf0, void, env, tl)
-DEF_HELPER_2(mttc0_vpeconf0, void, env, tl)
-DEF_HELPER_2(mtc0_vpeconf1, void, env, tl)
-DEF_HELPER_2(mtc0_yqmask, void, env, tl)
-DEF_HELPER_2(mtc0_vpeopt, void, env, tl)
-DEF_HELPER_2(mtc0_entrylo0, void, env, tl)
-DEF_HELPER_2(mtc0_tcstatus, void, env, tl)
-DEF_HELPER_2(mttc0_tcstatus, void, env, tl)
-DEF_HELPER_2(mtc0_tcbind, void, env, tl)
-DEF_HELPER_2(mttc0_tcbind, void, env, tl)
-DEF_HELPER_2(mtc0_tcrestart, void, env, tl)
-DEF_HELPER_2(mttc0_tcrestart, void, env, tl)
-DEF_HELPER_2(mtc0_tchalt, void, env, tl)
-DEF_HELPER_2(mttc0_tchalt, void, env, tl)
-DEF_HELPER_2(mtc0_tccontext, void, env, tl)
-DEF_HELPER_2(mttc0_tccontext, void, env, tl)
-DEF_HELPER_2(mtc0_tcschedule, void, env, tl)
-DEF_HELPER_2(mttc0_tcschedule, void, env, tl)
-DEF_HELPER_2(mtc0_tcschefback, void, env, tl)
-DEF_HELPER_2(mttc0_tcschefback, void, env, tl)
-DEF_HELPER_2(mtc0_entrylo1, void, env, tl)
-DEF_HELPER_2(mtc0_context, void, env, tl)
-DEF_HELPER_2(mtc0_memorymapid, void, env, tl)
-

Re: [PATCH 15/26] target/mips: Restrict mmu_init() to TCG

[Richard Henderson]

On 4/18/21 9:31 AM, Philippe Mathieu-Daudé wrote:

mmu_init() is only required by TCG accelerator.
Restrict its declaration and call to TCG.

Signed-off-by: Philippe Mathieu-Daudé
---
  target/mips/internal.h | 3 ---
  target/mips/tcg/tcg-internal.h | 2 ++
  target/mips/cpu.c  | 2 +-
  3 files changed, 3 insertions(+), 4 deletions(-)


Reviewed-by: Richard Henderson 

r~

Re: [PATCH 16/26] target/mips: Move tlb_helper.c to tcg/sysemu/

[Richard Henderson]

On 4/18/21 9:31 AM, Philippe Mathieu-Daudé wrote:

Move tlb_helper.c to the tcg/sysemu/ subdir, along with
the following 3 declarations to tcg-internal.h:
- cpu_mips_tlb_flush()
- cpu_mips_translate_address()
- r4k_invalidate_tlb()

Simplify tlb_helper.c #ifdef'ry because files in tcg/sysemu/
are only build when sysemu mode is configured.

Signed-off-by: Philippe Mathieu-Daudé
---
  target/mips/internal.h| 5 -
  target/mips/tcg/tcg-internal.h| 5 +
  target/mips/{ => tcg/sysemu}/tlb_helper.c | 3 ---
  target/mips/meson.build   | 1 -
  target/mips/tcg/sysemu/meson.build| 1 +
  5 files changed, 6 insertions(+), 9 deletions(-)
  rename target/mips/{ => tcg/sysemu}/tlb_helper.c (99%)


Reviewed-by: Richard Henderson 

r~

Re: [PATCH 17/26] target/mips: Restrict CPUMIPSTLBContext::map_address() handlers scope

[Richard Henderson]

On 4/18/21 9:31 AM, Philippe Mathieu-Daudé wrote:

The 3 map_address() handlers are local to tlb_helper.c,
no need to have their prototype declared publically.

Signed-off-by: Philippe Mathieu-Daudé
---
  target/mips/internal.h  |  6 --
  target/mips/tcg/sysemu/tlb_helper.c | 13 +++--
  2 files changed, 7 insertions(+), 12 deletions(-)


Reviewed-by: Richard Henderson 

r~

Re: [PATCH 18/26] target/mips: Move Special opcodes to tcg/sysemu/special_helper.c

[Richard Henderson]

On 4/18/21 9:31 AM, Philippe Mathieu-Daudé wrote:

Move the Special opcodes helpers to tcg/sysemu/special_helper.c.

Since mips_io_recompile_replay_branch() is set as
CPUClass::io_recompile_replay_branch handler in cpu.c,
we need to declare its prototype in "tcg-internal.h".

Signed-off-by: Philippe Mathieu-Daudé 


Reviewed-by: Richard Henderson 


-static void set_pc(CPUMIPSState *env, target_ulong error_pc)
-{
-env->active_tc.PC = error_pc & ~(target_ulong)1;
-if (error_pc & 1) {
-env->hflags |= MIPS_HFLAG_M16;
-} else {
-env->hflags &= ~(MIPS_HFLAG_M16);
-}
-}


I'll note that this is identical to mips_cpu_set_pc, bar CPUState vs 
CPUMIPSState.


r~

Re: [PATCH v2] hw/mips/jazz: Remove confusing ifdef'ry

[Philippe Mathieu-Daudé]

On 4/18/21 8:48 PM, Richard Henderson wrote:
> On 4/18/21 9:51 AM, Philippe Mathieu-Daudé wrote:
>> The jazz machine is not used under user emulation and
>> does not support KVM. Simplify the ifdef'ry.
>>
>> Signed-off-by: Philippe Mathieu-Daudé
>> Reviewed-by: Richard Henderson
>> Reviewed-by: Claudio Fontana
>> Message-Id:<20210226132723.3969650-3-f4...@amsat.org>
>> ---
>> v2: Rebased.
>>
>> Based-on:<20210418163134.1133100-1-f4...@amsat.org>
>> ---
>>   hw/mips/jazz.c | 4 
>>   1 file changed, 4 deletions(-)
> 
> Were you going to apply this one before my cleanup to completely remove
> this hook manipulation?
> 
> https://patchew.org/QEMU/20210227232519.222663-1-richard.hender...@linaro.org/20210227232519.222663-2-richard.hender...@linaro.org/

Doh I completely forgot your patch =)

Let's forget about mine then!

Regards,

Phil.

Re: [PATCH 19/26] target/mips: Move helper_cache() to tcg/sysemu/special_helper.c

[Richard Henderson]

On 4/18/21 9:31 AM, Philippe Mathieu-Daudé wrote:

Move helper_cache() to tcg/sysemu/special_helper.c.

The CACHE opcode is privileged and is not accessible in user
emulation. However we get a link failure when restricting the
symbol to sysemu. For now, add a stub to satisfy linking, which
abort if ever called.

Signed-off-by: Philippe Mathieu-Daudé
---
  target/mips/op_helper.c | 35 -
  target/mips/tcg/sysemu/special_helper.c | 33 +++
  target/mips/tcg/user/stubs.c| 29 
  target/mips/tcg/user/meson.build|  1 +
  4 files changed, 63 insertions(+), 35 deletions(-)
  create mode 100644 target/mips/tcg/user/stubs.c


You could add a different stub to translate.c instead.  See

https://lists.gnu.org/archive/html/qemu-devel/2021-02/msg08595.html


r~

Re: [PATCH 20/26] target/mips: Move TLB management helpers to tcg/sysemu/tlb_helper.c

[Richard Henderson]

On 4/18/21 9:31 AM, Philippe Mathieu-Daudé wrote:

Move TLB management helpers to tcg/sysemu/tlb_helper.c.

Signed-off-by: Philippe Mathieu-Daudé
---
4 checkpatch errors:

   ERROR: space prohibited after that '&' (ctx:WxW)
   #414: FILE: target/mips/tcg/sysemu/tlb_helper.c:71:
   +tlb->XI0 = (env->CP0_EntryLo0 >> CP0EnLo_XI) & 1;
 ^

   ERROR: space prohibited after that '&' (ctx:WxW)
   #415: FILE: target/mips/tcg/sysemu/tlb_helper.c:72:
   +tlb->RI0 = (env->CP0_EntryLo0 >> CP0EnLo_RI) & 1;
 ^

   ERROR: space prohibited after that '&' (ctx:WxW)
   #420: FILE: target/mips/tcg/sysemu/tlb_helper.c:77:
   +tlb->XI1 = (env->CP0_EntryLo1 >> CP0EnLo_XI) & 1;
 ^

   ERROR: space prohibited after that '&' (ctx:WxW)
   #421: FILE: target/mips/tcg/sysemu/tlb_helper.c:78:
   +tlb->RI1 = (env->CP0_EntryLo1 >> CP0EnLo_RI) & 1;
 ^


Wow, that's amazingly bogus.  I'm amazed that no one has re-written checkpatch 
in e.g. sparse...


Reviewed-by: Richard Henderson 

r~

Re: Resetting non-qdev children in a 3-phase reset device

[Philippe Mathieu-Daudé]

+Markus

On 4/9/21 8:13 PM, Peter Maydell wrote:
> I wanted to convert the hw/misc/mps2-scc.c device from old-style
> to 3-phase reset as a prerequisite for another change to the device,
> but I ran into a problem because currently it has some TYPE_DEVICE
> QOM child objects, the LEDs. Because TYPE_DEVICE don't live in the
> qbus hierarchy, the device resets them manually in its DeviceClass::reset
> method:
> 
> for (i = 0; i < ARRAY_SIZE(s->led); i++) {
> device_cold_reset(DEVICE(s->led[i]));
> }
> 
> This makes converting to 3-phase reset awkward. The obvious "natural"
> approach would be to say "in this device's phase X, invoke phase X
> for these objects", but we have no API for that. (The functions which
> would do it, resettable_phase_enter() etc, are static inside resettable.c.)
> 
> Ignoring the phasing and trying to just call device_cold_reset() in
> the 'enter' phase results in an assertion failure, because we trip
> the assert(!enter_phase_in_progress) in resettable_assert_reset(),
> which doesn't expect us to be triggering a reset inside a reset.
> 
> Ideally one would want to be able to add the LEDs to the list of
> things which are children of this object for purposes of reset
> (so they are iterated as part of the resettable_child_foreach()
> logic and their phases are automatically invoked at the right point).
> But for a subclass of DeviceState that's device_reset_child_foreach()
> and it only iterates any qbus children of this device.
> 
> Any clever ideas?

Not very clever... We could kludge it by calling device_legacy_reset()
instead of device_cold_reset() in mps2_fpgaio_reset()... But that
mean we are going backward with the API.


OK, back to read your previous explanations... and the threads around.
https://www.mail-archive.com/qemu-devel@nongnu.org/msg723312.html
https://www.mail-archive.com/qemu-devel@nongnu.org/msg738242.html

"Note that [qdev/qbus hierarchy] is an entirely separate thing
from the QOM hierarchy of parent-and-child object relationships."

Hmm OK. I guess I'm confused seeing parts are overlapping when they
aren't. So setting the QOM parent relationship helps in having a
correct QOM path and the object is displayed nicely in the qom-tree,
but doesn't bring anything on the qdev side.

So back to qdev.

- TYPE_DEVICE (aka 'qdev') is abstract.
  It inherits TYPE_OBJECT.
  It can provide a bus (aka qbus) to plug things.
  It implements TYPE_RESETTABLE_INTERFACE.

- TYPE_SYS_BUS_DEVICE is also abstract.
  It inherits from TYPE_DEVICE, setting qbus=TYPE_SYSTEM_BUS

(
To confuse more, there is some undocumented API called
'device_listener' in qdev which instead uses sysbus:
void device_listener_register(DeviceListener *listener);
void device_listener_unregister(DeviceListener *listener);
)

Making MachineState inherit TYPE_DEVICE and re-implement the
TYPE_RESETTABLE_INTERFACE doesn't seem going in the right
direction...
If TYPE_MACHINE were qdev, its qbus could be a ResetBus. Again
it feels wrong (over engineering).

> Maybe some mechanism for marking "these things which are my
> QOM children I want to be reset when I am reset (so make them> reset children 
> of me and don't reset them as part of the
> qbus-tree-walking)" would be useful. I do think that in a
> lot of cases we want to be doing something closer to "reset
> along the QOM tree".

Eh here you mention QOM again... Shouldn't it be qdev?

I know the LED is just an example of a broader problem.
I indeed took care to add the QOM parent relation:

(qemu) info qom-tree
/machine (mps2-an385-machine)
  /fpgaio (mps2-fpgaio)
/mps2-fpgaio[0] (memory-region)
/userled0 (led)
  /unnamed-gpio-in[0] (irq)
/userled1 (led)
  /unnamed-gpio-in[0] (irq)
  /scc (mps2-scc)
/mps2-scc[0] (memory-region)
/scc-led0 (led)
  /unnamed-gpio-in[0] (irq)
/scc-led1 (led)
  /unnamed-gpio-in[0] (irq)
...

So looking at this qom-tree, the reset tree seems to me
more natural than the sysbus one, but IIRC not many models
set this QOM relationship.
QOM objects aren't enforced to have a relation with a parent,
as opposed as recent changes from Markus to always have a qdev
on a qbus). But even without parent they end in the /unattached
container below /machine, so if the reset were there, the
machine could still iterate over the /unattached children.

> I really do need to spend some time working
> out what the right thing with reset is and how we might get
> from where we are now to there...

Well, finally this QOM-tree reset is appealing.

Sorry if I haven't been very helpful :S Still processing the
problem in background...

Regards,

Phil.

Re: [PATCH 19/26] target/mips: Move helper_cache() to tcg/sysemu/special_helper.c

[Philippe Mathieu-Daudé]

On 4/18/21 9:52 PM, Richard Henderson wrote:
> On 4/18/21 9:31 AM, Philippe Mathieu-Daudé wrote:
>> Move helper_cache() to tcg/sysemu/special_helper.c.
>>
>> The CACHE opcode is privileged and is not accessible in user
>> emulation. However we get a link failure when restricting the
>> symbol to sysemu. For now, add a stub to satisfy linking, which
>> abort if ever called.
>>
>> Signed-off-by: Philippe Mathieu-Daudé
>> ---
>>   target/mips/op_helper.c | 35 -
>>   target/mips/tcg/sysemu/special_helper.c | 33 +++
>>   target/mips/tcg/user/stubs.c    | 29 
>>   target/mips/tcg/user/meson.build    |  1 +
>>   4 files changed, 63 insertions(+), 35 deletions(-)
>>   create mode 100644 target/mips/tcg/user/stubs.c
> 
> You could add a different stub to translate.c instead.  See
> 
> https://lists.gnu.org/archive/html/qemu-devel/2021-02/msg08595.html

Great!

I think STUB_HELPER() belong to include/exec/helper-*.h.

Thanks,

Phil.

Re: [PATCH 21/26] target/mips: Move exception management code to exception.c

[Richard Henderson]

On 4/18/21 9:31 AM, Philippe Mathieu-Daudé wrote:

Signed-off-by: Philippe Mathieu-Daudé
---
  target/mips/internal.h |  13 ---
  target/mips/tcg/tcg-internal.h |  14 +++
  target/mips/cpu.c  | 113 --
  target/mips/exception.c| 169 +
  target/mips/op_helper.c|  37 
  target/mips/meson.build|   1 +
  6 files changed, 184 insertions(+), 163 deletions(-)
  create mode 100644 target/mips/exception.c


Reviewed-by: Richard Henderson 

r~

Re: [PATCH 22/26] target/mips: Move CP0 helpers to sysemu/cp0.c

[Richard Henderson]

On 4/18/21 9:31 AM, Philippe Mathieu-Daudé wrote:

Opcodes accessing Coprocessor 0 are privileged.
Move the CP0 helpers to sysemu/ and simplify the #ifdef'ry.

Signed-off-by: Philippe Mathieu-Daudé
---
  target/mips/internal.h |   9 +--
  target/mips/cpu.c  | 103 ---
  target/mips/sysemu/cp0.c   | 123 +
  target/mips/sysemu/meson.build |   1 +
  4 files changed, 129 insertions(+), 107 deletions(-)
  create mode 100644 target/mips/sysemu/cp0.c


Reviewed-by: Richard Henderson 

r~

Re: [PATCH 23/26] target/mips: Move helper.h -> tcg/helper.h.inc

[Richard Henderson]

On 4/18/21 9:31 AM, Philippe Mathieu-Daudé wrote:

TCG frontend "exec/helper-head.h" expects each target to declare
its helpers in 'target/$TARGET/helper.h'. To ease maintenance we
rather to have all TCG specific files under our tcg/ sub directory.

Move the current 'helper.h' there, and add a one-line 'helper.h'
which re-include it.

Signed-off-by: Philippe Mathieu-Daudé
---
  target/mips/helper.h | 614 +--
  target/mips/tcg/helper.h.inc | 613 ++
  2 files changed, 614 insertions(+), 613 deletions(-)
  create mode 100644 target/mips/tcg/helper.h.inc


Eh.  Ok, I guess.

If we renamed the file tcg-helper.h{,.inc?} globally, would you still want it 
moved into your tcg/ subdirectory?



r~

Re: [PATCH 24/26] target/mips: Move TCG source files under tcg/ sub directory

[Richard Henderson]

On 4/18/21 9:31 AM, Philippe Mathieu-Daudé wrote:

To ease maintenance, move all TCG specific files under the tcg/
sub-directory. Adapt the Meson machinery.

The following prototypes:
- mips_tcg_init()
- mips_cpu_do_unaligned_access()
- mips_cpu_do_transaction_failed()
can now be restricted to the "tcg-internal.h" header.

Signed-off-by: Philippe Mathieu-Daudé
---


Reviewed-by: Richard Henderson 

r~

Re: [PATCH 26/26] gitlab-ci: Add KVM mips64el cross-build jobs

[Richard Henderson]

On 4/18/21 9:31 AM, Philippe Mathieu-Daudé wrote:

Add a new job to cross-build the mips64el target without
the TCG accelerator (IOW: only KVM accelerator enabled).

Only build the mips64el target which is known to work
and has users.

Signed-off-by: Philippe Mathieu-Daudé
---
  .gitlab-ci.d/crossbuilds.yml | 8 
  1 file changed, 8 insertions(+)


Reviewed-by: Richard Henderson 

r~

Re: [PATCH 25/26] hw/mips: Restrict non-virtualized machines to TCG

[Richard Henderson]

On 4/18/21 9:31 AM, Philippe Mathieu-Daudé wrote:

Only the malta and loongson3-virt machines support KVM.

Restrict the other machines to TCG:

  - mipssim
  - magnum
  - pica61
  - fuloong2e
  - boston

Signed-off-by: Philippe Mathieu-Daudé
---
  hw/mips/meson.build | 11 +++
  1 file changed, 7 insertions(+), 4 deletions(-)


Reviewed-by: Richard Henderson 

r~

Re: [PATCH 09/26] target/mips: Add simple user-mode mips_cpu_do_interrupt()

[Richard Henderson]

On 4/18/21 9:31 AM, Philippe Mathieu-Daudé wrote:

  target/mips/tcg/user/helper.c| 28 


Since only this and the next helper go in here, perhaps continue to call it 
tlb_helper.c?  Otherwise,


Reviewed-by: Richard Henderson 

r~

Re: [PATCH 10/26] target/mips: Add simple user-mode mips_cpu_tlb_fill()

[Richard Henderson]

On 4/18/21 9:31 AM, Philippe Mathieu-Daudé wrote:

tlb_helper.c's #ifdef'ry hides a quite simple user-mode
implementation of mips_cpu_tlb_fill().

Copy the user-mode implementation (without #ifdef'ry) to
tcg/user/helper.c and simplify tlb_helper.c's #ifdef'ry.

This will allow us to restrict tlb_helper.c to sysemu.

Signed-off-by: Philippe Mathieu-Daudé
---
  target/mips/tcg/user/helper.c | 36 +++
  target/mips/tlb_helper.c  | 10 --
  2 files changed, 36 insertions(+), 10 deletions(-)


Reviewed-by: Richard Henderson 

r~

Re: [PATCH v4 01/12] tcg: expose TCGCond manipulation routines

[Richard Henderson]

On 4/15/21 9:34 AM, Alessandro Di Federico wrote:

From: Alessandro Di Federico

This commit moves into a separate file routines used to manipulate
TCGCond. These will be employed by the idef-parser.

Signed-off-by: Alessandro Di Federico
Signed-off-by: Paolo Montesel
---
  include/tcg/tcg-cond.h | 101 +
  include/tcg/tcg.h  |  70 +---
  2 files changed, 102 insertions(+), 69 deletions(-)
  create mode 100644 include/tcg/tcg-cond.h


Reviewed-by: Richard Henderson 

r~

Re: [PATCH v4 02/12] target/hexagon: update MAINTAINERS for idef-parser

[Richard Henderson]

On 4/15/21 9:34 AM, Alessandro Di Federico wrote:

From: Alessandro Di Federico

Signed-off-by: Alessandro Di Federico
---
  MAINTAINERS | 8 
  1 file changed, 8 insertions(+)


Reviewed-by: Richard Henderson 

r~

Re: [PATCH v4 04/12] target/hexagon: make slot number an unsigned

[Richard Henderson]

On 4/15/21 9:34 AM, Alessandro Di Federico wrote:

From: Paolo Montesel

Signed-off-by: Alessandro Di Federico
Signed-off-by: Paolo Montesel
---
  target/hexagon/genptr.c | 6 --
  target/hexagon/macros.h | 2 +-
  2 files changed, 5 insertions(+), 3 deletions(-)


Acked-by: Richard Henderson 

r~

Re: [PATCH v4 05/12] target/hexagon: make helper functions non-static

[Richard Henderson]

On 4/15/21 9:34 AM, Alessandro Di Federico wrote:

From: Paolo Montesel

Make certain helper functions non-static, making them available outside
genptr.c. These functions are required by code generated by the
idef-parser.

Signed-off-by: Alessandro Di Federico
Signed-off-by: Paolo Montesel
---
  target/hexagon/genptr.c | 7 ---
  target/hexagon/genptr.h | 6 ++
  2 files changed, 10 insertions(+), 3 deletions(-)


Reviewed-by: Richard Henderson 

r~

Re: [PATCH 23/26] target/mips: Move helper.h -> tcg/helper.h.inc

[Philippe Mathieu-Daudé]

On 4/18/21 10:34 PM, Richard Henderson wrote:
> On 4/18/21 9:31 AM, Philippe Mathieu-Daudé wrote:
>> TCG frontend "exec/helper-head.h" expects each target to declare
>> its helpers in 'target/$TARGET/helper.h'. To ease maintenance we
>> rather to have all TCG specific files under our tcg/ sub directory.
>>
>> Move the current 'helper.h' there, and add a one-line 'helper.h'
>> which re-include it.
>>
>> Signed-off-by: Philippe Mathieu-Daudé
>> ---
>>   target/mips/helper.h | 614 +--
>>   target/mips/tcg/helper.h.inc | 613 ++
>>   2 files changed, 614 insertions(+), 613 deletions(-)
>>   create mode 100644 target/mips/tcg/helper.h.inc
> 
> Eh.  Ok, I guess.
> 
> If we renamed the file tcg-helper.h{,.inc?} globally, would you still
> want it moved into your tcg/ subdirectory?

Not really... I wanted to have anything TCG related under tcg/,
but I can't find any good reason for it (I was thinking about
finer MAINTAINERS granularity, but this doesn't bring much).

I'll drop this patch, no need to change the other targets.

Thanks for the reviews!

Phil.

Re: [PATCH v4 06/12] target/hexagon: introduce new helper functions

[Richard Henderson]

On 4/15/21 9:34 AM, Alessandro Di Federico wrote:

+void gen_store32(TCGv vaddr, TCGv src, tcg_target_long width, unsigned slot)
+{
+tcg_gen_mov_tl(hex_store_addr[slot], vaddr);
+tcg_gen_movi_tl(hex_store_width[slot], width);
+tcg_gen_mov_tl(hex_store_val32[slot], src);
+}
+
+void gen_store1(TCGv_env cpu_env, TCGv vaddr, TCGv src, DisasContext *ctx,
+unsigned slot)
+{
+gen_store32(vaddr, src, 1, slot);
+ctx->store_width[slot] = 1;
+}


Why is store_width here and not in gen_store32?
Do you really need so many helpers here, as opposed to making use of MemOp?


+void gen_sat_i32_ext(TCGv ovfl, TCGv dest, TCGv source, int width)
+{
+gen_sat_i32(dest, source, width);
+TCGv zero = tcg_const_i32(0);
+TCGv one = tcg_const_i32(1);
+tcg_gen_movcond_i32(TCG_COND_NE, ovfl, source, dest, one, zero);


(source != dest ? 1 : 0) -> (source != dest).

Therefore, tcg_gen_setcond_i32.

Or did you intend

ovfl = (source != dest ? 1 : ovfl)?

which is probably still better as

  tcg_gen_setcond_tl(TCG_COND_NE, tmp, source,dest);
  tcg_gen_or_tl(ovfl, ovfl, tmp);


+void gen_fbrev(TCGv result, TCGv src)
+{
+TCGv lo = tcg_temp_new();
+TCGv tmp1 = tcg_temp_new();
+TCGv tmp2 = tcg_temp_new();
+
+/* Bit reversal of low 16 bits */
+tcg_gen_extract_tl(lo, src, 0, 16);
+tcg_gen_andi_tl(tmp1, lo, 0x);
+tcg_gen_shri_tl(tmp1, tmp1, 1);
+tcg_gen_andi_tl(tmp2, lo, 0x);
+tcg_gen_shli_tl(tmp2, tmp2, 1);
+tcg_gen_or_tl(lo, tmp1, tmp2);
+tcg_gen_andi_tl(tmp1, lo, 0x);
+tcg_gen_shri_tl(tmp1, tmp1, 2);
+tcg_gen_andi_tl(tmp2, lo, 0x);
+tcg_gen_shli_tl(tmp2, tmp2, 2);
+tcg_gen_or_tl(lo, tmp1, tmp2);
+tcg_gen_andi_tl(tmp1, lo, 0xf0f0);
+tcg_gen_shri_tl(tmp1, tmp1, 4);
+tcg_gen_andi_tl(tmp2, lo, 0x0f0f);
+tcg_gen_shli_tl(tmp2, tmp2, 4);
+tcg_gen_or_tl(lo, tmp1, tmp2);
+tcg_gen_bswap16_tl(lo, lo);
+
+/* Final tweaks */
+tcg_gen_deposit_tl(result, src, lo, 0, 16);
+tcg_gen_or_tl(result, result, lo);
+
+tcg_temp_free(lo);
+tcg_temp_free(tmp1);
+tcg_temp_free(tmp2);
+}


Coordinate with Taylor.
https://lists.gnu.org/archive/html/qemu-devel/2021-03/msg10007.html


r~

Re: [PATCH v4 07/12] target/hexagon: expose next PC in DisasContext

[Richard Henderson]

On 4/15/21 9:34 AM, Alessandro Di Federico wrote:

From: Paolo Montesel

Signed-off-by: Alessandro Di Federico
Signed-off-by: Paolo Montesel
---
  target/hexagon/translate.c | 3 ++-
  target/hexagon/translate.h | 1 +
  2 files changed, 3 insertions(+), 1 deletion(-)


Reviewed-by: Richard Henderson 

r~

Re: [PATCH v4 08/12] target/hexagon: prepare input for the idef-parser

[Richard Henderson]

On 4/15/21 9:34 AM, Alessandro Di Federico wrote:

+++ b/target/hexagon/idef-parser/prepare
@@ -0,0 +1,24 @@
+#!/bin/bash
+
+#
+# Copyright(c) 2019-2021 rev.ng Srls. All Rights Reserved.
+#
+# This library is free software; you can redistribute it and/or
+# modify it under the terms of the GNU Lesser General Public
+# License as published by the Free Software Foundation; either
+# version 2 of the License, or (at your option) any later version.
+#
+# This library is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
+# Lesser General Public License for more details.
+#
+# You should have received a copy of the GNU Lesser General Public
+# License along with this library; if not, see .
+#
+
+set -e
+set -o pipefail
+
+# Run the preprocessor and drop comments
+cpp "$@" | grep -v '^#'


Any reason not to handle '#' lines in the parser?


r~

[Bug 1921061] Re: Corsair iCUE Install Fails, qemu VM Reboots

[Russell Morris]

Hi,

Slight update - as I decided to passthru my NIC as well => driver
install there also causes a VM (Windows 10) reboot. Seems all driver
installs fail?

Running on the latest master, QEMU emulator version 5.2.93 (v6.0.0-rc3).

Thanks!

-- 
You received this bug notification because you are a member of qemu-
devel-ml, which is subscribed to QEMU.
https://bugs.launchpad.net/bugs/1921061

Title:
  Corsair iCUE Install Fails, qemu VM Reboots

Status in QEMU:
  New

Bug description:
  Hi,

  I had this working before, but in the latest version of QEMU (built
  from master), when I try to install Corsair iCUE, and it gets to the
  driver install point => my Windows 10 VM just reboots! I would be
  happy to capture logs, but ... what logs exist for an uncontrolled
  reboot? Thinking they are lost in the reboot :-(.

  Thanks!

To manage notifications about this bug go to:
https://bugs.launchpad.net/qemu/+bug/1921061/+subscriptions

Re: [PATCH 14/26] target/mips: Move sysemu TCG-specific code to tcg/sysemu/ subfolder

[Philippe Mathieu-Daudé]

On 4/18/21 9:35 PM, Richard Henderson wrote:
> On 4/18/21 9:31 AM, Philippe Mathieu-Daudé wrote:
>> Declare cpu_mips_get_random() and update_pagemask() on local scope,
> 
> What is "local scope"?  Anyway, I don't see what this has to do with the
> rest of the code movement.

I guess I meant 'TCG'. I'll split.

Re: [PATCH 06/26] target/mips: Extract load/store helpers to ldst_helper.c

[Philippe Mathieu-Daudé]

On 4/18/21 9:08 PM, Richard Henderson wrote:
> On 4/18/21 9:31 AM, Philippe Mathieu-Daudé wrote:
>> +static inline hwaddr do_translate_address(CPUMIPSState *env,
>> +  target_ulong address,
>> +  MMUAccessType access_type,
>> +  uintptr_t retaddr)
>> +{
>> +    hwaddr paddr;
>> +    CPUState *cs = env_cpu(env);
>> +
>> +    paddr = cpu_mips_translate_address(env, address, access_type);
>> +
>> +    if (paddr == -1LL) {
>> +    cpu_loop_exit_restore(cs, retaddr);
>> +    } else {
>> +    return paddr;
>> +    }
>> +}
> 
> Code motion, so,
> Reviewed-by: Richard Henderson 
> 
> but I think that it's a mistake for cpu_mips_translate_address to split
> the raise_mmu_exception from the cpu_loop_exit_restore.  If you make the
> changes to env to indicate the exception, you *must* then go back to the
> main loop.
> 
> There seems to be exactly one caller, this one, so it should be trivial
> to change, which the lets do_translate_address vanish entirely.

I'm taking note of this comment and will try to address it later.

[PATCH v2 05/29] target/mips: Optimize CPU/FPU regnames[] arrays

[Philippe Mathieu-Daudé]

Since all entries are no more than 4 bytes (including nul
terminator), can save space and pie runtime relocations by
declaring regnames[] as array of 4 const char.

Suggested-by: Richard Henderson 
Signed-off-by: Philippe Mathieu-Daudé 
---
 target/mips/internal.h | 4 ++--
 target/mips/cpu.c  | 2 +-
 target/mips/fpu.c  | 2 +-
 3 files changed, 4 insertions(+), 4 deletions(-)

diff --git a/target/mips/internal.h b/target/mips/internal.h
index a8644f754a6..37f54a8b3fc 100644
--- a/target/mips/internal.h
+++ b/target/mips/internal.h
@@ -71,8 +71,8 @@ struct mips_def_t {
 int32_t SAARP;
 };
 
-extern const char * const regnames[32];
-extern const char * const fregnames[32];
+extern const char regnames[32][4];
+extern const char fregnames[32][4];
 
 extern const struct mips_def_t mips_defs[];
 extern const int mips_defs_number;
diff --git a/target/mips/cpu.c b/target/mips/cpu.c
index f354d18aec4..ed9552ebeb7 100644
--- a/target/mips/cpu.c
+++ b/target/mips/cpu.c
@@ -35,7 +35,7 @@
 #include "qapi/qapi-commands-machine-target.h"
 #include "fpu_helper.h"
 
-const char * const regnames[32] = {
+const char regnames[32][4] = {
 "r0", "at", "v0", "v1", "a0", "a1", "a2", "a3",
 "t0", "t1", "t2", "t3", "t4", "t5", "t6", "t7",
 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7",
diff --git a/target/mips/fpu.c b/target/mips/fpu.c
index 1447dba3fa3..c7c487c1f9f 100644
--- a/target/mips/fpu.c
+++ b/target/mips/fpu.c
@@ -17,7 +17,7 @@ const FloatRoundMode ieee_rm[4] = {
 float_round_down
 };
 
-const char * const fregnames[32] = {
+const char fregnames[32][4] = {
 "f0",  "f1",  "f2",  "f3",  "f4",  "f5",  "f6",  "f7",
 "f8",  "f9",  "f10", "f11", "f12", "f13", "f14", "f15",
 "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23",
-- 
2.26.3

[PATCH v2 00/29] target/mips: Re-org to allow KVM-only builds

[Philippe Mathieu-Daudé]

TL;DR:

This series restrict TCG-specific objects by moving them to
the tcg/ subdir. Code is moved around to satisfy 3 cases:
{ generic sysemu / tcg sysemu / tcg user}.

Since v1:
- Addressed Richard review comments
- Added Richard R-b tag

Missing review: 5, 7, 8, 17, 18, 23

Hi,

This series move the MIPS TCG files under target/mips/tcg/.
tcg/ is split into {sysemu and user}, and code common to
both user/sysemu is left under tcg/ root.

Non-user code is moved to sysemu/ (common to TCG and KVM).

- Patches 1 & 10 are Meson generic
- Patches 2 to 9 move generic symbols around to satisfly KVM linking
- Patch 11 introduces tcg-internal.h where we'll move TCG specific
  prototypes from the current big internal.h
- Patches 12-27 move code by topic (first user, then sysemu, then tcg)
- Patch 28 restrict TCG specific machines to TCG (to actually
  only build malta/loongson3-virt machines when restricted to KVM)
- Patch 29 finally add a CI job with "KVM-only" config:
  https://gitlab.com/philmd/qemu/-/jobs/1189874868 (12min 5sec)

Diffstat is not that bad, and many #ifdef'ry removed.

Please review,

Phil.

Based-on: <20210413081008.3409459-1-f4...@amsat.org>
  "exec: Remove accel/tcg/ from include paths"

Philippe Mathieu-Daudé (29):
  target/mips: Simplify meson TCG rules
  target/mips: Move IEEE rounding mode array to new source file
  target/mips: Move msa_reset() to new source file
  target/mips: Make CPU/FPU regnames[] arrays global
  target/mips: Optimize CPU/FPU regnames[] arrays
  target/mips: Restrict mips_cpu_dump_state() to cpu.c
  target/mips: Turn printfpr() macro into a proper function
  target/mips: Declare mips_cpu_set_error_pc() inlined in "internal.h"
  target/mips: Extract load/store helpers to ldst_helper.c
  meson: Introduce meson_user_arch source set for arch-specific
user-mode
  target/mips: Introduce tcg-internal.h for TCG specific declarations
  target/mips: Add simple user-mode mips_cpu_do_interrupt()
  target/mips: Add simple user-mode mips_cpu_tlb_fill()
  target/mips: Move cpu_signal_handler definition around
  target/mips: Move sysemu specific files under sysemu/ subfolder
  target/mips: Move physical addressing code to sysemu/physaddr.c
  target/mips: Restrict cpu_mips_get_random() / update_pagemask() to TCG
  target/mips: Move sysemu TCG-specific code to tcg/sysemu/ subfolder
  target/mips: Restrict mmu_init() to TCG
  target/mips: Move tlb_helper.c to tcg/sysemu/
  target/mips: Restrict CPUMIPSTLBContext::map_address() handlers scope
  target/mips: Move Special opcodes to tcg/sysemu/special_helper.c
  target/mips: Move helper_cache() to tcg/sysemu/special_helper.c
  target/mips: Move TLB management helpers to tcg/sysemu/tlb_helper.c
  target/mips: Move exception management code to exception.c
  target/mips: Move CP0 helpers to sysemu/cp0.c
  target/mips: Move TCG source files under tcg/ sub directory
  hw/mips: Restrict non-virtualized machines to TCG
  gitlab-ci: Add KVM mips64el cross-build jobs

 meson.build  |6 +
 target/mips/helper.h |  183 +--
 target/mips/internal.h   |  106 +-
 target/mips/tcg/tcg-internal.h   |   64 +
 target/mips/{ => tcg}/msa_helper.h.inc   |0
 target/mips/tcg/sysemu_helper.h.inc  |  185 +++
 target/mips/{ => tcg}/mips32r6.decode|0
 target/mips/{ => tcg}/mips64r6.decode|0
 target/mips/{ => tcg}/msa32.decode   |0
 target/mips/{ => tcg}/msa64.decode   |0
 target/mips/{ => tcg}/tx79.decode|0
 target/mips/cpu.c|  311 ++---
 target/mips/fpu.c|   25 +
 target/mips/msa.c|   60 +
 target/mips/op_helper.c  | 1210 --
 target/mips/{ => sysemu}/addr.c  |0
 target/mips/sysemu/cp0.c |  123 ++
 target/mips/{ => sysemu}/cp0_timer.c |0
 target/mips/{ => sysemu}/machine.c   |0
 target/mips/sysemu/physaddr.c|  257 
 target/mips/{ => tcg}/dsp_helper.c   |0
 target/mips/tcg/exception.c  |  169 +++
 target/mips/{ => tcg}/fpu_helper.c   |8 -
 target/mips/tcg/ldst_helper.c|  304 +
 target/mips/{ => tcg}/lmmi_helper.c  |0
 target/mips/{ => tcg}/msa_helper.c   |   36 -
 target/mips/{ => tcg}/msa_translate.c|0
 target/mips/{ => tcg}/mxu_translate.c|0
 target/mips/tcg/op_helper.c  |  421 ++
 target/mips/{ => tcg}/rel6_translate.c   |0
 target/mips/{ => tcg/sysemu}/cp0_helper.c|0
 target/mips/{ => tcg/sysemu}/mips-semi.c |0
 target/mips/tcg/sysemu/special_helper.c  |  173 +++
 target/mips/{ => tcg/sysemu}/tlb_helper.c|  612 +
 target/mips/{ => tcg}/translate.c|  104 +-
 target/mips/{ => tcg}/translate_addr_const.c |0
 target/mi

[PATCH v2 07/29] target/mips: Turn printfpr() macro into a proper function

[Philippe Mathieu-Daudé]

Turn printfpr() macro into a proper function: fpu_dump_fpr().

Suggested-by: Richard Henderson 
Signed-off-by: Philippe Mathieu-Daudé 
---
 target/mips/cpu.c | 48 ++-
 1 file changed, 22 insertions(+), 26 deletions(-)

diff --git a/target/mips/cpu.c b/target/mips/cpu.c
index 232f701b836..90ae232c8b8 100644
--- a/target/mips/cpu.c
+++ b/target/mips/cpu.c
@@ -145,44 +145,40 @@ void cpu_mips_store_cause(CPUMIPSState *env, target_ulong 
val)
 
 #endif /* !CONFIG_USER_ONLY */
 
+static void fpu_dump_fpr(fpr_t *fpr, FILE *f, bool is_fpu64)
+{
+if (is_fpu64) {
+qemu_fprintf(f, "w:%08x d:%016" PRIx64 " fd:%13g fs:%13g psu: %13g\n",
+ fpr->w[FP_ENDIAN_IDX], fpr->d,
+ (double)fpr->fd,
+ (double)fpr->fs[FP_ENDIAN_IDX],
+ (double)fpr->fs[!FP_ENDIAN_IDX]);
+} else {
+fpr_t tmp;
+
+tmp.w[FP_ENDIAN_IDX] = fpr->w[FP_ENDIAN_IDX];
+tmp.w[!FP_ENDIAN_IDX] = (fpr + 1)->w[FP_ENDIAN_IDX];
+qemu_fprintf(f, "w:%08x d:%016" PRIx64 " fd:%13g fs:%13g psu:%13g\n",
+ tmp.w[FP_ENDIAN_IDX], tmp.d,
+ (double)tmp.fd,
+ (double)tmp.fs[FP_ENDIAN_IDX],
+ (double)tmp.fs[!FP_ENDIAN_IDX]);
+}
+}
+
 static void fpu_dump_state(CPUMIPSState *env, FILE *f, int flags)
 {
 int i;
 int is_fpu64 = !!(env->hflags & MIPS_HFLAG_F64);
 
-#define printfpr(fp)\
-do {\
-if (is_fpu64)   \
-qemu_fprintf(f, "w:%08x d:%016" PRIx64  \
- " fd:%13g fs:%13g psu: %13g\n",\
- (fp)->w[FP_ENDIAN_IDX], (fp)->d,   \
- (double)(fp)->fd,  \
- (double)(fp)->fs[FP_ENDIAN_IDX],   \
- (double)(fp)->fs[!FP_ENDIAN_IDX]); \
-else {  \
-fpr_t tmp;  \
-tmp.w[FP_ENDIAN_IDX] = (fp)->w[FP_ENDIAN_IDX];  \
-tmp.w[!FP_ENDIAN_IDX] = ((fp) + 1)->w[FP_ENDIAN_IDX];   \
-qemu_fprintf(f, "w:%08x d:%016" PRIx64  \
- " fd:%13g fs:%13g psu:%13g\n", \
- tmp.w[FP_ENDIAN_IDX], tmp.d,   \
- (double)tmp.fd,\
- (double)tmp.fs[FP_ENDIAN_IDX], \
- (double)tmp.fs[!FP_ENDIAN_IDX]);   \
-}   \
-} while (0)
-
-
 qemu_fprintf(f,
  "CP1 FCR0 0x%08x  FCR31 0x%08x  SR.FR %d  fp_status 0x%02x\n",
  env->active_fpu.fcr0, env->active_fpu.fcr31, is_fpu64,
  get_float_exception_flags(&env->active_fpu.fp_status));
 for (i = 0; i < 32; (is_fpu64) ? i++ : (i += 2)) {
 qemu_fprintf(f, "%3s: ", fregnames[i]);
-printfpr(&env->active_fpu.fpr[i]);
+fpu_dump_fpr(&env->active_fpu.fpr[i], f, is_fpu64);
 }
-
-#undef printfpr
 }
 
 static void mips_cpu_dump_state(CPUState *cs, FILE *f, int flags)
-- 
2.26.3

[PATCH v2 01/29] target/mips: Simplify meson TCG rules

[Philippe Mathieu-Daudé]

We already have the mips_tcg_ss source set for TCG-specific files,
use it for mxu_translate.c and tx79_translate.c to simplify a bit.

Reviewed-by: Richard Henderson 
Signed-off-by: Philippe Mathieu-Daudé 
---
 target/mips/meson.build | 5 ++---
 1 file changed, 2 insertions(+), 3 deletions(-)

diff --git a/target/mips/meson.build b/target/mips/meson.build
index 3b131c4a7f6..3733d1200f7 100644
--- a/target/mips/meson.build
+++ b/target/mips/meson.build
@@ -26,10 +26,9 @@
   'translate_addr_const.c',
   'txx9_translate.c',
 ))
-mips_ss.add(when: ['CONFIG_TCG', 'TARGET_MIPS64'], if_true: files(
+mips_tcg_ss.add(when: 'TARGET_MIPS64', if_true: files(
   'tx79_translate.c',
-))
-mips_tcg_ss.add(when: 'TARGET_MIPS64', if_false: files(
+), if_false: files(
   'mxu_translate.c',
 ))
 
-- 
2.26.3

[PATCH v2 04/29] target/mips: Make CPU/FPU regnames[] arrays global

[Philippe Mathieu-Daudé]

The CPU/FPU regnames[] arrays is used in mips_tcg_init() and
mips_cpu_dump_state(), which while being in translate.c is
not specific to TCG.

To be able to move mips_cpu_dump_state() to cpu.c, which is
compiled for all accelerator, we need to make the regnames[]
arrays global to target/mips/ by declaring them in "internal.h".

Reviewed-by: Richard Henderson 
Signed-off-by: Philippe Mathieu-Daudé 
---
 target/mips/internal.h  |  3 +++
 target/mips/cpu.c   |  7 +++
 target/mips/fpu.c   |  7 +++
 target/mips/translate.c | 14 --
 4 files changed, 17 insertions(+), 14 deletions(-)

diff --git a/target/mips/internal.h b/target/mips/internal.h
index 99264b8bf6a..a8644f754a6 100644
--- a/target/mips/internal.h
+++ b/target/mips/internal.h
@@ -71,6 +71,9 @@ struct mips_def_t {
 int32_t SAARP;
 };
 
+extern const char * const regnames[32];
+extern const char * const fregnames[32];
+
 extern const struct mips_def_t mips_defs[];
 extern const int mips_defs_number;
 
diff --git a/target/mips/cpu.c b/target/mips/cpu.c
index dce1e166bde..f354d18aec4 100644
--- a/target/mips/cpu.c
+++ b/target/mips/cpu.c
@@ -35,6 +35,13 @@
 #include "qapi/qapi-commands-machine-target.h"
 #include "fpu_helper.h"
 
+const char * const regnames[32] = {
+"r0", "at", "v0", "v1", "a0", "a1", "a2", "a3",
+"t0", "t1", "t2", "t3", "t4", "t5", "t6", "t7",
+"s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7",
+"t8", "t9", "k0", "k1", "gp", "sp", "s8", "ra",
+};
+
 #if !defined(CONFIG_USER_ONLY)
 
 /* Called for updates to CP0_Status.  */
diff --git a/target/mips/fpu.c b/target/mips/fpu.c
index 39a2f7fd22e..1447dba3fa3 100644
--- a/target/mips/fpu.c
+++ b/target/mips/fpu.c
@@ -16,3 +16,10 @@ const FloatRoundMode ieee_rm[4] = {
 float_round_up,
 float_round_down
 };
+
+const char * const fregnames[32] = {
+"f0",  "f1",  "f2",  "f3",  "f4",  "f5",  "f6",  "f7",
+"f8",  "f9",  "f10", "f11", "f12", "f13", "f14", "f15",
+"f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23",
+"f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31",
+};
diff --git a/target/mips/translate.c b/target/mips/translate.c
index 71fa5ec1973..f99d4d4016d 100644
--- a/target/mips/translate.c
+++ b/target/mips/translate.c
@@ -1267,13 +1267,6 @@ TCGv_i64 fpu_f64[32];
 #define DISAS_STOP   DISAS_TARGET_0
 #define DISAS_EXIT   DISAS_TARGET_1
 
-static const char * const regnames[] = {
-"r0", "at", "v0", "v1", "a0", "a1", "a2", "a3",
-"t0", "t1", "t2", "t3", "t4", "t5", "t6", "t7",
-"s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7",
-"t8", "t9", "k0", "k1", "gp", "sp", "s8", "ra",
-};
-
 static const char * const regnames_HI[] = {
 "HI0", "HI1", "HI2", "HI3",
 };
@@ -1282,13 +1275,6 @@ static const char * const regnames_LO[] = {
 "LO0", "LO1", "LO2", "LO3",
 };
 
-static const char * const fregnames[] = {
-"f0",  "f1",  "f2",  "f3",  "f4",  "f5",  "f6",  "f7",
-"f8",  "f9",  "f10", "f11", "f12", "f13", "f14", "f15",
-"f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23",
-"f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31",
-};
-
 /* General purpose registers moves. */
 void gen_load_gpr(TCGv t, int reg)
 {
-- 
2.26.3

[PATCH v2 08/29] target/mips: Declare mips_cpu_set_error_pc() inlined in "internal.h"

[Philippe Mathieu-Daudé]

Rename set_pc() as mips_cpu_set_error_pc(), declare it inlined
and use it in cpu.c and op_helper.c.

Reported-by: Richard Henderson 
Signed-off-by: Philippe Mathieu-Daudé 
---
 target/mips/internal.h  | 11 +++
 target/mips/cpu.c   |  8 +---
 target/mips/op_helper.c | 16 +++-
 3 files changed, 15 insertions(+), 20 deletions(-)

diff --git a/target/mips/internal.h b/target/mips/internal.h
index 57072a941e7..81671d567d0 100644
--- a/target/mips/internal.h
+++ b/target/mips/internal.h
@@ -219,6 +219,17 @@ bool mips_cpu_tlb_fill(CPUState *cs, vaddr address, int 
size,
 /* op_helper.c */
 void update_pagemask(CPUMIPSState *env, target_ulong arg1, int32_t *pagemask);
 
+static inline void mips_cpu_set_error_pc(CPUMIPSState *env,
+ target_ulong error_pc)
+{
+env->active_tc.PC = error_pc & ~(target_ulong)1;
+if (error_pc & 1) {
+env->hflags |= MIPS_HFLAG_M16;
+} else {
+env->hflags &= ~(MIPS_HFLAG_M16);
+}
+}
+
 static inline void restore_pamask(CPUMIPSState *env)
 {
 if (env->hflags & MIPS_HFLAG_ELPA) {
diff --git a/target/mips/cpu.c b/target/mips/cpu.c
index 90ae232c8b8..fcbf95c85b9 100644
--- a/target/mips/cpu.c
+++ b/target/mips/cpu.c
@@ -327,14 +327,8 @@ void QEMU_NORETURN do_raise_exception_err(CPUMIPSState 
*env,
 static void mips_cpu_set_pc(CPUState *cs, vaddr value)
 {
 MIPSCPU *cpu = MIPS_CPU(cs);
-CPUMIPSState *env = &cpu->env;
 
-env->active_tc.PC = value & ~(target_ulong)1;
-if (value & 1) {
-env->hflags |= MIPS_HFLAG_M16;
-} else {
-env->hflags &= ~(MIPS_HFLAG_M16);
-}
+mips_cpu_set_error_pc(&cpu->env, value);
 }
 
 #ifdef CONFIG_TCG
diff --git a/target/mips/op_helper.c b/target/mips/op_helper.c
index b80e8f75401..f7da8c83aee 100644
--- a/target/mips/op_helper.c
+++ b/target/mips/op_helper.c
@@ -993,24 +993,14 @@ static void debug_post_eret(CPUMIPSState *env)
 }
 }
 
-static void set_pc(CPUMIPSState *env, target_ulong error_pc)
-{
-env->active_tc.PC = error_pc & ~(target_ulong)1;
-if (error_pc & 1) {
-env->hflags |= MIPS_HFLAG_M16;
-} else {
-env->hflags &= ~(MIPS_HFLAG_M16);
-}
-}
-
 static inline void exception_return(CPUMIPSState *env)
 {
 debug_pre_eret(env);
 if (env->CP0_Status & (1 << CP0St_ERL)) {
-set_pc(env, env->CP0_ErrorEPC);
+mips_cpu_set_error_pc(env, env->CP0_ErrorEPC);
 env->CP0_Status &= ~(1 << CP0St_ERL);
 } else {
-set_pc(env, env->CP0_EPC);
+mips_cpu_set_error_pc(env, env->CP0_EPC);
 env->CP0_Status &= ~(1 << CP0St_EXL);
 }
 compute_hflags(env);
@@ -1036,7 +1026,7 @@ void helper_deret(CPUMIPSState *env)
 env->hflags &= ~MIPS_HFLAG_DM;
 compute_hflags(env);
 
-set_pc(env, env->CP0_DEPC);
+mips_cpu_set_error_pc(env, env->CP0_DEPC);
 
 debug_post_eret(env);
 }
-- 
2.26.3

[PATCH v2 12/29] target/mips: Add simple user-mode mips_cpu_do_interrupt()

[Philippe Mathieu-Daudé]

The #ifdef'ry hides that the user-mode implementation of
mips_cpu_do_interrupt() simply sets exception_index = EXCP_NONE.

Add this simple implementation to tcg/user/tlb_helper.c, and
the corresponding Meson machinery to build this file when user
emulation is configured.

Reviewed-by: Richard Henderson 
Signed-off-by: Philippe Mathieu-Daudé 
---
v2: Renamed helper.c -> tlb_helper.c (rth)
---
 target/mips/tcg/user/tlb_helper.c | 28 
 target/mips/tlb_helper.c  |  5 -
 target/mips/meson.build   |  5 +
 target/mips/tcg/meson.build   |  3 +++
 target/mips/tcg/user/meson.build  |  3 +++
 5 files changed, 39 insertions(+), 5 deletions(-)
 create mode 100644 target/mips/tcg/user/tlb_helper.c
 create mode 100644 target/mips/tcg/meson.build
 create mode 100644 target/mips/tcg/user/meson.build

diff --git a/target/mips/tcg/user/tlb_helper.c 
b/target/mips/tcg/user/tlb_helper.c
new file mode 100644
index 000..453b9e9b930
--- /dev/null
+++ b/target/mips/tcg/user/tlb_helper.c
@@ -0,0 +1,28 @@
+/*
+ * MIPS TLB (Translation lookaside buffer) helpers.
+ *
+ *  Copyright (c) 2004-2005 Jocelyn Mayer
+ *
+ * This library is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU Lesser General Public
+ * License as published by the Free Software Foundation; either
+ * version 2.1 of the License, or (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
+ * Lesser General Public License for more details.
+ *
+ * You should have received a copy of the GNU Lesser General Public
+ * License along with this library; if not, see .
+ */
+#include "qemu/osdep.h"
+
+#include "cpu.h"
+#include "exec/exec-all.h"
+#include "internal.h"
+
+void mips_cpu_do_interrupt(CPUState *cs)
+{
+cs->exception_index = EXCP_NONE;
+}
diff --git a/target/mips/tlb_helper.c b/target/mips/tlb_helper.c
index 8d3ea497803..46e9555c9ab 100644
--- a/target/mips/tlb_helper.c
+++ b/target/mips/tlb_helper.c
@@ -964,11 +964,8 @@ static inline void set_badinstr_registers(CPUMIPSState 
*env)
 }
 }
 
-#endif /* !CONFIG_USER_ONLY */
-
 void mips_cpu_do_interrupt(CPUState *cs)
 {
-#if !defined(CONFIG_USER_ONLY)
 MIPSCPU *cpu = MIPS_CPU(cs);
 CPUMIPSState *env = &cpu->env;
 bool update_badinstr = 0;
@@ -1271,11 +1268,9 @@ void mips_cpu_do_interrupt(CPUState *cs)
  env->CP0_Status, env->CP0_Cause, env->CP0_BadVAddr,
  env->CP0_DEPC);
 }
-#endif
 cs->exception_index = EXCP_NONE;
 }
 
-#if !defined(CONFIG_USER_ONLY)
 void r4k_invalidate_tlb(CPUMIPSState *env, int idx, int use_extra)
 {
 CPUState *cs = env_cpu(env);
diff --git a/target/mips/meson.build b/target/mips/meson.build
index 15c2f835c68..ca3cc62cf7a 100644
--- a/target/mips/meson.build
+++ b/target/mips/meson.build
@@ -6,6 +6,7 @@
   decodetree.process('tx79.decode', extra_args: '--static-decode=decode_tx79'),
 ]
 
+mips_user_ss = ss.source_set()
 mips_ss = ss.source_set()
 mips_ss.add(files(
   'cpu.c',
@@ -34,6 +35,9 @@
 ), if_false: files(
   'mxu_translate.c',
 ))
+if 'CONFIG_TCG' in config_all
+  subdir('tcg')
+endif
 
 mips_ss.add(when: 'CONFIG_KVM', if_true: files('kvm.c'))
 
@@ -52,3 +56,4 @@
 
 target_arch += {'mips': mips_ss}
 target_softmmu_arch += {'mips': mips_softmmu_ss}
+target_user_arch += {'mips': mips_user_ss}
diff --git a/target/mips/tcg/meson.build b/target/mips/tcg/meson.build
new file mode 100644
index 000..b74fa04303e
--- /dev/null
+++ b/target/mips/tcg/meson.build
@@ -0,0 +1,3 @@
+if have_user
+  subdir('user')
+endif
diff --git a/target/mips/tcg/user/meson.build b/target/mips/tcg/user/meson.build
new file mode 100644
index 000..79badcd3217
--- /dev/null
+++ b/target/mips/tcg/user/meson.build
@@ -0,0 +1,3 @@
+mips_user_ss.add(files(
+  'tlb_helper.c',
+))
-- 
2.26.3

[PATCH v2 02/29] target/mips: Move IEEE rounding mode array to new source file

[Philippe Mathieu-Daudé]

restore_msa_fp_status() is declared inlined in fpu_helper.h,
and uses the ieee_rm[] array. Therefore any code calling
restore_msa_fp_status() must have access to this ieee_rm[] array.

kvm_mips_get_fpu_registers(), which is in target/mips/kvm.c,
calls restore_msa_fp_status.

Except this tiny array, the rest of fpu_helper.c is only useful
for the TCG accelerator.

To be able to restrict fpu_helper.c to TCG, we need to move the
ieee_rm[] array to a new source file.

Reviewed-by: Richard Henderson 
Signed-off-by: Philippe Mathieu-Daudé 
---
 target/mips/fpu.c| 18 ++
 target/mips/fpu_helper.c |  8 
 target/mips/meson.build  |  1 +
 3 files changed, 19 insertions(+), 8 deletions(-)
 create mode 100644 target/mips/fpu.c

diff --git a/target/mips/fpu.c b/target/mips/fpu.c
new file mode 100644
index 000..39a2f7fd22e
--- /dev/null
+++ b/target/mips/fpu.c
@@ -0,0 +1,18 @@
+/*
+ * Helpers for emulation of FPU-related MIPS instructions.
+ *
+ *  Copyright (C) 2004-2005  Jocelyn Mayer
+ *
+ * SPDX-License-Identifier: LGPL-2.1-or-later
+ */
+#include "qemu/osdep.h"
+#include "fpu/softfloat-helpers.h"
+#include "fpu_helper.h"
+
+/* convert MIPS rounding mode in FCR31 to IEEE library */
+const FloatRoundMode ieee_rm[4] = {
+float_round_nearest_even,
+float_round_to_zero,
+float_round_up,
+float_round_down
+};
diff --git a/target/mips/fpu_helper.c b/target/mips/fpu_helper.c
index 6dd853259e2..8ce56ed7c81 100644
--- a/target/mips/fpu_helper.c
+++ b/target/mips/fpu_helper.c
@@ -38,14 +38,6 @@
 #define FP_TO_INT32_OVERFLOW 0x7fff
 #define FP_TO_INT64_OVERFLOW 0x7fffULL
 
-/* convert MIPS rounding mode in FCR31 to IEEE library */
-const FloatRoundMode ieee_rm[4] = {
-float_round_nearest_even,
-float_round_to_zero,
-float_round_up,
-float_round_down
-};
-
 target_ulong helper_cfc1(CPUMIPSState *env, uint32_t reg)
 {
 target_ulong arg1 = 0;
diff --git a/target/mips/meson.build b/target/mips/meson.build
index 3733d1200f7..5fcb211ca9a 100644
--- a/target/mips/meson.build
+++ b/target/mips/meson.build
@@ -9,6 +9,7 @@
 mips_ss = ss.source_set()
 mips_ss.add(files(
   'cpu.c',
+  'fpu.c',
   'gdbstub.c',
 ))
 mips_tcg_ss = ss.source_set()
-- 
2.26.3

[PATCH v2 11/29] target/mips: Introduce tcg-internal.h for TCG specific declarations

[Philippe Mathieu-Daudé]

We will gradually move TCG-specific declarations to a new local
header: "tcg-internal.h". To keep review simple, first add this
header with 2 TCG prototypes, which we are going to move in the
next 2 commits.

Reviewed-by: Richard Henderson 
Signed-off-by: Philippe Mathieu-Daudé 
---
 target/mips/internal.h |  7 +++
 target/mips/tcg/tcg-internal.h | 20 
 2 files changed, 23 insertions(+), 4 deletions(-)
 create mode 100644 target/mips/tcg/tcg-internal.h

diff --git a/target/mips/internal.h b/target/mips/internal.h
index 81671d567d0..284ef8d1e1a 100644
--- a/target/mips/internal.h
+++ b/target/mips/internal.h
@@ -9,6 +9,9 @@
 #define MIPS_INTERNAL_H
 
 #include "exec/memattrs.h"
+#ifdef CONFIG_TCG
+#include "tcg/tcg-internal.h"
+#endif
 
 /*
  * MMU types, the first four entries have the same layout as the
@@ -77,7 +80,6 @@ extern const char fregnames[32][4];
 extern const struct mips_def_t mips_defs[];
 extern const int mips_defs_number;
 
-void mips_cpu_do_interrupt(CPUState *cpu);
 bool mips_cpu_exec_interrupt(CPUState *cpu, int int_req);
 hwaddr mips_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr);
 int mips_cpu_gdb_read_register(CPUState *cpu, GByteArray *buf, int reg);
@@ -212,9 +214,6 @@ void cpu_mips_stop_count(CPUMIPSState *env);
 
 /* helper.c */
 void mmu_init(CPUMIPSState *env, const mips_def_t *def);
-bool mips_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
-   MMUAccessType access_type, int mmu_idx,
-   bool probe, uintptr_t retaddr);
 
 /* op_helper.c */
 void update_pagemask(CPUMIPSState *env, target_ulong arg1, int32_t *pagemask);
diff --git a/target/mips/tcg/tcg-internal.h b/target/mips/tcg/tcg-internal.h
new file mode 100644
index 000..24438667f47
--- /dev/null
+++ b/target/mips/tcg/tcg-internal.h
@@ -0,0 +1,20 @@
+/*
+ * MIPS internal definitions and helpers (TCG accelerator)
+ *
+ * SPDX-License-Identifier: GPL-2.0-or-later
+ *
+ * This work is licensed under the terms of the GNU GPL, version 2 or later.
+ * See the COPYING file in the top-level directory.
+ */
+
+#ifndef MIPS_TCG_INTERNAL_H
+#define MIPS_TCG_INTERNAL_H
+
+#include "hw/core/cpu.h"
+
+void mips_cpu_do_interrupt(CPUState *cpu);
+bool mips_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
+   MMUAccessType access_type, int mmu_idx,
+   bool probe, uintptr_t retaddr);
+
+#endif
-- 
2.26.3

[PATCH v2 09/29] target/mips: Extract load/store helpers to ldst_helper.c

[Philippe Mathieu-Daudé]

Reviewed-by: Richard Henderson 
Signed-off-by: Philippe Mathieu-Daudé 
---
 target/mips/ldst_helper.c | 304 ++
 target/mips/op_helper.c   | 274 --
 target/mips/meson.build   |   1 +
 3 files changed, 305 insertions(+), 274 deletions(-)
 create mode 100644 target/mips/ldst_helper.c

diff --git a/target/mips/ldst_helper.c b/target/mips/ldst_helper.c
new file mode 100644
index 000..3fbcc3509ab
--- /dev/null
+++ b/target/mips/ldst_helper.c
@@ -0,0 +1,304 @@
+/*
+ *  MIPS emulation load/store helpers for QEMU.
+ *
+ *  Copyright (c) 2004-2005 Jocelyn Mayer
+ *
+ * SPDX-License-Identifier: LGPL-2.1-or-later
+ *
+ * This library is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU Lesser General Public
+ * License as published by the Free Software Foundation; either
+ * version 2.1 of the License, or (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
+ * Lesser General Public License for more details.
+ *
+ * You should have received a copy of the GNU Lesser General Public
+ * License along with this library; if not, see .
+ *
+ */
+
+#include "qemu/osdep.h"
+#include "cpu.h"
+#include "exec/helper-proto.h"
+#include "exec/exec-all.h"
+#include "exec/memop.h"
+#include "internal.h"
+
+#ifndef CONFIG_USER_ONLY
+
+static inline hwaddr do_translate_address(CPUMIPSState *env,
+  target_ulong address,
+  MMUAccessType access_type,
+  uintptr_t retaddr)
+{
+hwaddr paddr;
+CPUState *cs = env_cpu(env);
+
+paddr = cpu_mips_translate_address(env, address, access_type);
+
+if (paddr == -1LL) {
+cpu_loop_exit_restore(cs, retaddr);
+} else {
+return paddr;
+}
+}
+
+#define HELPER_LD_ATOMIC(name, insn, almask, do_cast) \
+target_ulong helper_##name(CPUMIPSState *env, target_ulong arg, int mem_idx)  \
+{ \
+if (arg & almask) {   \
+if (!(env->hflags & MIPS_HFLAG_DM)) { \
+env->CP0_BadVAddr = arg;  \
+} \
+do_raise_exception(env, EXCP_AdEL, GETPC());  \
+} \
+env->CP0_LLAddr = do_translate_address(env, arg, MMU_DATA_LOAD, GETPC()); \
+env->lladdr = arg;\
+env->llval = do_cast cpu_##insn##_mmuidx_ra(env, arg, mem_idx, GETPC());  \
+return env->llval;\
+}
+HELPER_LD_ATOMIC(ll, ldl, 0x3, (target_long)(int32_t))
+#ifdef TARGET_MIPS64
+HELPER_LD_ATOMIC(lld, ldq, 0x7, (target_ulong))
+#endif
+#undef HELPER_LD_ATOMIC
+
+#endif /* !CONFIG_USER_ONLY */
+
+#ifdef TARGET_WORDS_BIGENDIAN
+#define GET_LMASK(v) ((v) & 3)
+#define GET_OFFSET(addr, offset) (addr + (offset))
+#else
+#define GET_LMASK(v) (((v) & 3) ^ 3)
+#define GET_OFFSET(addr, offset) (addr - (offset))
+#endif
+
+void helper_swl(CPUMIPSState *env, target_ulong arg1, target_ulong arg2,
+int mem_idx)
+{
+cpu_stb_mmuidx_ra(env, arg2, (uint8_t)(arg1 >> 24), mem_idx, GETPC());
+
+if (GET_LMASK(arg2) <= 2) {
+cpu_stb_mmuidx_ra(env, GET_OFFSET(arg2, 1), (uint8_t)(arg1 >> 16),
+  mem_idx, GETPC());
+}
+
+if (GET_LMASK(arg2) <= 1) {
+cpu_stb_mmuidx_ra(env, GET_OFFSET(arg2, 2), (uint8_t)(arg1 >> 8),
+  mem_idx, GETPC());
+}
+
+if (GET_LMASK(arg2) == 0) {
+cpu_stb_mmuidx_ra(env, GET_OFFSET(arg2, 3), (uint8_t)arg1,
+  mem_idx, GETPC());
+}
+}
+
+void helper_swr(CPUMIPSState *env, target_ulong arg1, target_ulong arg2,
+int mem_idx)
+{
+cpu_stb_mmuidx_ra(env, arg2, (uint8_t)arg1, mem_idx, GETPC());
+
+if (GET_LMASK(arg2) >= 1) {
+cpu_stb_mmuidx_ra(env, GET_OFFSET(arg2, -1), (uint8_t)(arg1 >> 8),
+  mem_idx, GETPC());
+}
+
+if (GET_LMASK(arg2) >= 2) {
+cpu_stb_mmuidx_ra(env, GET_OFFSET(arg2, -2), (uint8_t)(arg1 >> 16),
+  mem_idx, GETPC());
+}
+
+if (GET_LMASK(arg2) == 3) {
+cpu_stb_mmuidx_ra(env, GET_OFFSET(arg2, -3), (uint8_t)(arg1 >> 24),
+  mem_idx, GETPC());
+}
+}
+
+#if defined(TARGET_MIPS64)
+/*
+ * "half" load and stores.  We must do the memory access inline,
+ * or fault h

[PATCH v2 13/29] target/mips: Add simple user-mode mips_cpu_tlb_fill()

[Philippe Mathieu-Daudé]

tlb_helper.c's #ifdef'ry hides a quite simple user-mode
implementation of mips_cpu_tlb_fill().

Copy the user-mode implementation (without #ifdef'ry) to
tcg/user/helper.c and simplify tlb_helper.c's #ifdef'ry.

This will allow us to restrict tlb_helper.c to sysemu.

Reviewed-by: Richard Henderson 
Signed-off-by: Philippe Mathieu-Daudé 
---
 target/mips/tcg/user/tlb_helper.c | 36 +++
 target/mips/tlb_helper.c  | 10 -
 2 files changed, 36 insertions(+), 10 deletions(-)

diff --git a/target/mips/tcg/user/tlb_helper.c 
b/target/mips/tcg/user/tlb_helper.c
index 453b9e9b930..b835144b820 100644
--- a/target/mips/tcg/user/tlb_helper.c
+++ b/target/mips/tcg/user/tlb_helper.c
@@ -22,6 +22,42 @@
 #include "exec/exec-all.h"
 #include "internal.h"
 
+static void raise_mmu_exception(CPUMIPSState *env, target_ulong address,
+MMUAccessType access_type)
+{
+CPUState *cs = env_cpu(env);
+
+env->error_code = 0;
+if (access_type == MMU_INST_FETCH) {
+env->error_code |= EXCP_INST_NOTAVAIL;
+}
+
+/* Reference to kernel address from user mode or supervisor mode */
+/* Reference to supervisor address from user mode */
+if (access_type == MMU_DATA_STORE) {
+cs->exception_index = EXCP_AdES;
+} else {
+cs->exception_index = EXCP_AdEL;
+}
+
+/* Raise exception */
+if (!(env->hflags & MIPS_HFLAG_DM)) {
+env->CP0_BadVAddr = address;
+}
+}
+
+bool mips_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
+   MMUAccessType access_type, int mmu_idx,
+   bool probe, uintptr_t retaddr)
+{
+MIPSCPU *cpu = MIPS_CPU(cs);
+CPUMIPSState *env = &cpu->env;
+
+/* data access */
+raise_mmu_exception(env, address, access_type);
+do_raise_exception_err(env, cs->exception_index, env->error_code, retaddr);
+}
+
 void mips_cpu_do_interrupt(CPUState *cs)
 {
 cs->exception_index = EXCP_NONE;
diff --git a/target/mips/tlb_helper.c b/target/mips/tlb_helper.c
index 46e9555c9ab..bb4b503ff72 100644
--- a/target/mips/tlb_helper.c
+++ b/target/mips/tlb_helper.c
@@ -403,8 +403,6 @@ void cpu_mips_tlb_flush(CPUMIPSState *env)
 env->tlb->tlb_in_use = env->tlb->nb_tlb;
 }
 
-#endif /* !CONFIG_USER_ONLY */
-
 static void raise_mmu_exception(CPUMIPSState *env, target_ulong address,
 MMUAccessType access_type, int tlb_error)
 {
@@ -484,8 +482,6 @@ static void raise_mmu_exception(CPUMIPSState *env, 
target_ulong address,
 env->error_code = error_code;
 }
 
-#if !defined(CONFIG_USER_ONLY)
-
 hwaddr mips_cpu_get_phys_page_debug(CPUState *cs, vaddr addr)
 {
 MIPSCPU *cpu = MIPS_CPU(cs);
@@ -833,7 +829,6 @@ refill:
 return true;
 }
 #endif
-#endif /* !CONFIG_USER_ONLY */
 
 bool mips_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
MMUAccessType access_type, int mmu_idx,
@@ -841,14 +836,11 @@ bool mips_cpu_tlb_fill(CPUState *cs, vaddr address, int 
size,
 {
 MIPSCPU *cpu = MIPS_CPU(cs);
 CPUMIPSState *env = &cpu->env;
-#if !defined(CONFIG_USER_ONLY)
 hwaddr physical;
 int prot;
-#endif
 int ret = TLBRET_BADADDR;
 
 /* data access */
-#if !defined(CONFIG_USER_ONLY)
 /* XXX: put correct access by using cpu_restore_state() correctly */
 ret = get_physical_address(env, &physical, &prot, address,
access_type, mmu_idx);
@@ -896,13 +888,11 @@ bool mips_cpu_tlb_fill(CPUState *cs, vaddr address, int 
size,
 if (probe) {
 return false;
 }
-#endif
 
 raise_mmu_exception(env, address, access_type, ret);
 do_raise_exception_err(env, cs->exception_index, env->error_code, retaddr);
 }
 
-#ifndef CONFIG_USER_ONLY
 hwaddr cpu_mips_translate_address(CPUMIPSState *env, target_ulong address,
   MMUAccessType access_type)
 {
-- 
2.26.3

[PATCH v2 03/29] target/mips: Move msa_reset() to new source file

[Philippe Mathieu-Daudé]

mips_cpu_reset() is used by all accelerators, and calls
msa_reset(), which is defined in msa_helper.c.

Beside msa_reset(), the rest of msa_helper.c is only useful
to the TCG accelerator. To be able to restrict this helper
file to TCG, we need to move msa_reset() out of it.

Reviewed-by: Richard Henderson 
Signed-off-by: Philippe Mathieu-Daudé 
---
 target/mips/msa.c| 60 
 target/mips/msa_helper.c | 36 
 target/mips/meson.build  |  1 +
 3 files changed, 61 insertions(+), 36 deletions(-)
 create mode 100644 target/mips/msa.c

diff --git a/target/mips/msa.c b/target/mips/msa.c
new file mode 100644
index 000..61f1a9a5936
--- /dev/null
+++ b/target/mips/msa.c
@@ -0,0 +1,60 @@
+/*
+ * MIPS SIMD Architecture Module Instruction emulation helpers for QEMU.
+ *
+ * Copyright (c) 2014 Imagination Technologies
+ *
+ * This library is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU Lesser General Public
+ * License as published by the Free Software Foundation; either
+ * version 2.1 of the License, or (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
+ * Lesser General Public License for more details.
+ *
+ * You should have received a copy of the GNU Lesser General Public
+ * License along with this library; if not, see .
+ */
+
+#include "qemu/osdep.h"
+#include "cpu.h"
+#include "internal.h"
+#include "fpu/softfloat.h"
+#include "fpu_helper.h"
+
+void msa_reset(CPUMIPSState *env)
+{
+if (!ase_msa_available(env)) {
+return;
+}
+
+#ifdef CONFIG_USER_ONLY
+/* MSA access enabled */
+env->CP0_Config5 |= 1 << CP0C5_MSAEn;
+env->CP0_Status |= (1 << CP0St_CU1) | (1 << CP0St_FR);
+#endif
+
+/*
+ * MSA CSR:
+ * - non-signaling floating point exception mode off (NX bit is 0)
+ * - Cause, Enables, and Flags are all 0
+ * - round to nearest / ties to even (RM bits are 0)
+ */
+env->active_tc.msacsr = 0;
+
+restore_msa_fp_status(env);
+
+/* tininess detected after rounding.*/
+set_float_detect_tininess(float_tininess_after_rounding,
+  &env->active_tc.msa_fp_status);
+
+/* clear float_status exception flags */
+set_float_exception_flags(0, &env->active_tc.msa_fp_status);
+
+/* clear float_status nan mode */
+set_default_nan_mode(0, &env->active_tc.msa_fp_status);
+
+/* set proper signanling bit meaning ("1" means "quiet") */
+set_snan_bit_is_one(0, &env->active_tc.msa_fp_status);
+}
diff --git a/target/mips/msa_helper.c b/target/mips/msa_helper.c
index 4caefe29ad7..04af54f66d1 100644
--- a/target/mips/msa_helper.c
+++ b/target/mips/msa_helper.c
@@ -8595,39 +8595,3 @@ void helper_msa_st_d(CPUMIPSState *env, uint32_t wd,
 cpu_stq_data(env, addr + (1 << DF_DOUBLE), pwd->d[1]);
 #endif
 }
-
-void msa_reset(CPUMIPSState *env)
-{
-if (!ase_msa_available(env)) {
-return;
-}
-
-#ifdef CONFIG_USER_ONLY
-/* MSA access enabled */
-env->CP0_Config5 |= 1 << CP0C5_MSAEn;
-env->CP0_Status |= (1 << CP0St_CU1) | (1 << CP0St_FR);
-#endif
-
-/*
- * MSA CSR:
- * - non-signaling floating point exception mode off (NX bit is 0)
- * - Cause, Enables, and Flags are all 0
- * - round to nearest / ties to even (RM bits are 0)
- */
-env->active_tc.msacsr = 0;
-
-restore_msa_fp_status(env);
-
-/* tininess detected after rounding.*/
-set_float_detect_tininess(float_tininess_after_rounding,
-  &env->active_tc.msa_fp_status);
-
-/* clear float_status exception flags */
-set_float_exception_flags(0, &env->active_tc.msa_fp_status);
-
-/* clear float_status nan mode */
-set_default_nan_mode(0, &env->active_tc.msa_fp_status);
-
-/* set proper signanling bit meaning ("1" means "quiet") */
-set_snan_bit_is_one(0, &env->active_tc.msa_fp_status);
-}
diff --git a/target/mips/meson.build b/target/mips/meson.build
index 5fcb211ca9a..daf5f1d55bc 100644
--- a/target/mips/meson.build
+++ b/target/mips/meson.build
@@ -11,6 +11,7 @@
   'cpu.c',
   'fpu.c',
   'gdbstub.c',
+  'msa.c',
 ))
 mips_tcg_ss = ss.source_set()
 mips_tcg_ss.add(gen)
-- 
2.26.3

[PATCH v2 14/29] target/mips: Move cpu_signal_handler definition around

[Philippe Mathieu-Daudé]

We have 2 blocks guarded with #ifdef for sysemu, which
are simply separated by the cpu_signal_handler definition.

To simplify the following commits which involve various
changes in internal.h, first join the sysemu-guarded blocks.

Reviewed-by: Richard Henderson 
Signed-off-by: Philippe Mathieu-Daudé 
---
 target/mips/internal.h | 9 -
 1 file changed, 4 insertions(+), 5 deletions(-)

diff --git a/target/mips/internal.h b/target/mips/internal.h
index 284ef8d1e1a..8deb0703a34 100644
--- a/target/mips/internal.h
+++ b/target/mips/internal.h
@@ -151,14 +151,13 @@ void mips_cpu_do_transaction_failed(CPUState *cs, hwaddr 
physaddr,
 MemTxResult response, uintptr_t retaddr);
 hwaddr cpu_mips_translate_address(CPUMIPSState *env, target_ulong address,
   MMUAccessType access_type);
-#endif
+
+extern const VMStateDescription vmstate_mips_cpu;
+
+#endif /* !CONFIG_USER_ONLY */
 
 #define cpu_signal_handler cpu_mips_signal_handler
 
-#ifndef CONFIG_USER_ONLY
-extern const VMStateDescription vmstate_mips_cpu;
-#endif
-
 static inline bool cpu_mips_hw_interrupts_enabled(CPUMIPSState *env)
 {
 return (env->CP0_Status & (1 << CP0St_IE)) &&
-- 
2.26.3

[PATCH v2 16/29] target/mips: Move physical addressing code to sysemu/physaddr.c

[Philippe Mathieu-Daudé]

Declare get_physical_address() with local scope and move it along
with mips_cpu_get_phys_page_debug() to sysemu/physaddr.c new file.

Reviewed-by: Richard Henderson 
Signed-off-by: Philippe Mathieu-Daudé 
---
v2: phys.c -> physaddr.c in description (rth)
---
 target/mips/internal.h |  25 +++-
 target/mips/sysemu/physaddr.c  | 257 +
 target/mips/tlb_helper.c   | 254 
 target/mips/sysemu/meson.build |   1 +
 4 files changed, 282 insertions(+), 255 deletions(-)
 create mode 100644 target/mips/sysemu/physaddr.c

diff --git a/target/mips/internal.h b/target/mips/internal.h
index 8deb0703a34..8789ffb319f 100644
--- a/target/mips/internal.h
+++ b/target/mips/internal.h
@@ -81,15 +81,38 @@ extern const struct mips_def_t mips_defs[];
 extern const int mips_defs_number;
 
 bool mips_cpu_exec_interrupt(CPUState *cpu, int int_req);
-hwaddr mips_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr);
 int mips_cpu_gdb_read_register(CPUState *cpu, GByteArray *buf, int reg);
 int mips_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg);
 void mips_cpu_do_unaligned_access(CPUState *cpu, vaddr addr,
   MMUAccessType access_type,
   int mmu_idx, uintptr_t retaddr);
 
+#define USEG_LIMIT  ((target_ulong)(int32_t)0x7FFFUL)
+#define KSEG0_BASE  ((target_ulong)(int32_t)0x8000UL)
+#define KSEG1_BASE  ((target_ulong)(int32_t)0xA000UL)
+#define KSEG2_BASE  ((target_ulong)(int32_t)0xC000UL)
+#define KSEG3_BASE  ((target_ulong)(int32_t)0xE000UL)
+
+#define KVM_KSEG0_BASE  ((target_ulong)(int32_t)0x4000UL)
+#define KVM_KSEG2_BASE  ((target_ulong)(int32_t)0x6000UL)
+
 #if !defined(CONFIG_USER_ONLY)
 
+enum {
+TLBRET_XI = -6,
+TLBRET_RI = -5,
+TLBRET_DIRTY = -4,
+TLBRET_INVALID = -3,
+TLBRET_NOMATCH = -2,
+TLBRET_BADADDR = -1,
+TLBRET_MATCH = 0
+};
+
+int get_physical_address(CPUMIPSState *env, hwaddr *physical,
+ int *prot, target_ulong real_address,
+ MMUAccessType access_type, int mmu_idx);
+hwaddr mips_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr);
+
 typedef struct r4k_tlb_t r4k_tlb_t;
 struct r4k_tlb_t {
 target_ulong VPN;
diff --git a/target/mips/sysemu/physaddr.c b/target/mips/sysemu/physaddr.c
new file mode 100644
index 000..1918633aa1c
--- /dev/null
+++ b/target/mips/sysemu/physaddr.c
@@ -0,0 +1,257 @@
+/*
+ * MIPS TLB (Translation lookaside buffer) helpers.
+ *
+ *  Copyright (c) 2004-2005 Jocelyn Mayer
+ *
+ * This library is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU Lesser General Public
+ * License as published by the Free Software Foundation; either
+ * version 2.1 of the License, or (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
+ * Lesser General Public License for more details.
+ *
+ * You should have received a copy of the GNU Lesser General Public
+ * License along with this library; if not, see .
+ */
+#include "qemu/osdep.h"
+#include "cpu.h"
+#include "exec/exec-all.h"
+#include "../internal.h"
+
+static int is_seg_am_mapped(unsigned int am, bool eu, int mmu_idx)
+{
+/*
+ * Interpret access control mode and mmu_idx.
+ *   AdE? TLB?
+ *  AM  K S U E  K S U E
+ * UK0  0 1 1 0  0 - - 0
+ * MK1  0 1 1 0  1 - - !eu
+ * MSK   2  0 0 1 0  1 1 - !eu
+ * MUSK  3  0 0 0 0  1 1 1 !eu
+ * MUSUK 4  0 0 0 0  0 1 1 0
+ * USK   5  0 0 1 0  0 0 - 0
+ * - 6  - - - -  - - - -
+ * UUSK  7  0 0 0 0  0 0 0 0
+ */
+int32_t adetlb_mask;
+
+switch (mmu_idx) {
+case 3: /* ERL */
+/* If EU is set, always unmapped */
+if (eu) {
+return 0;
+}
+/* fall through */
+case MIPS_HFLAG_KM:
+/* Never AdE, TLB mapped if AM={1,2,3} */
+adetlb_mask = 0x7000;
+goto check_tlb;
+
+case MIPS_HFLAG_SM:
+/* AdE if AM={0,1}, TLB mapped if AM={2,3,4} */
+adetlb_mask = 0xc038;
+goto check_ade;
+
+case MIPS_HFLAG_UM:
+/* AdE if AM={0,1,2,5}, TLB mapped if AM={3,4} */
+adetlb_mask = 0xe418;
+/* fall through */
+check_ade:
+/* does this AM cause AdE in current execution mode */
+if ((adetlb_mask << am) < 0) {
+return TLBRET_BADADDR;
+}
+adetlb_mask <<= 8;
+/* fall through */
+check_tlb:
+/* is this AM mapped in current execution mode */
+return ((adetlb_mask << am) < 0);
+default:
+assert(0);
+return TLBRET_BADADDR;
+};
+}
+
+static int get_seg_physical_address(CPUMIPSState *env, hwaddr *ph

[PATCH v2 06/29] target/mips: Restrict mips_cpu_dump_state() to cpu.c

[Philippe Mathieu-Daudé]

As mips_cpu_dump_state() is only used once to initialize the
CPUClass::dump_state handler, we can move it to cpu.c to keep
it symbol local.
Beside, this handler is used by all accelerators, while the
translate.c file targets TCG.

Reviewed-by: Richard Henderson 
Signed-off-by: Philippe Mathieu-Daudé 
---
 target/mips/internal.h  |  1 -
 target/mips/cpu.c   | 77 +
 target/mips/translate.c | 77 -
 3 files changed, 77 insertions(+), 78 deletions(-)

diff --git a/target/mips/internal.h b/target/mips/internal.h
index 37f54a8b3fc..57072a941e7 100644
--- a/target/mips/internal.h
+++ b/target/mips/internal.h
@@ -79,7 +79,6 @@ extern const int mips_defs_number;
 
 void mips_cpu_do_interrupt(CPUState *cpu);
 bool mips_cpu_exec_interrupt(CPUState *cpu, int int_req);
-void mips_cpu_dump_state(CPUState *cpu, FILE *f, int flags);
 hwaddr mips_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr);
 int mips_cpu_gdb_read_register(CPUState *cpu, GByteArray *buf, int reg);
 int mips_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg);
diff --git a/target/mips/cpu.c b/target/mips/cpu.c
index ed9552ebeb7..232f701b836 100644
--- a/target/mips/cpu.c
+++ b/target/mips/cpu.c
@@ -145,6 +145,83 @@ void cpu_mips_store_cause(CPUMIPSState *env, target_ulong 
val)
 
 #endif /* !CONFIG_USER_ONLY */
 
+static void fpu_dump_state(CPUMIPSState *env, FILE *f, int flags)
+{
+int i;
+int is_fpu64 = !!(env->hflags & MIPS_HFLAG_F64);
+
+#define printfpr(fp)\
+do {\
+if (is_fpu64)   \
+qemu_fprintf(f, "w:%08x d:%016" PRIx64  \
+ " fd:%13g fs:%13g psu: %13g\n",\
+ (fp)->w[FP_ENDIAN_IDX], (fp)->d,   \
+ (double)(fp)->fd,  \
+ (double)(fp)->fs[FP_ENDIAN_IDX],   \
+ (double)(fp)->fs[!FP_ENDIAN_IDX]); \
+else {  \
+fpr_t tmp;  \
+tmp.w[FP_ENDIAN_IDX] = (fp)->w[FP_ENDIAN_IDX];  \
+tmp.w[!FP_ENDIAN_IDX] = ((fp) + 1)->w[FP_ENDIAN_IDX];   \
+qemu_fprintf(f, "w:%08x d:%016" PRIx64  \
+ " fd:%13g fs:%13g psu:%13g\n", \
+ tmp.w[FP_ENDIAN_IDX], tmp.d,   \
+ (double)tmp.fd,\
+ (double)tmp.fs[FP_ENDIAN_IDX], \
+ (double)tmp.fs[!FP_ENDIAN_IDX]);   \
+}   \
+} while (0)
+
+
+qemu_fprintf(f,
+ "CP1 FCR0 0x%08x  FCR31 0x%08x  SR.FR %d  fp_status 0x%02x\n",
+ env->active_fpu.fcr0, env->active_fpu.fcr31, is_fpu64,
+ get_float_exception_flags(&env->active_fpu.fp_status));
+for (i = 0; i < 32; (is_fpu64) ? i++ : (i += 2)) {
+qemu_fprintf(f, "%3s: ", fregnames[i]);
+printfpr(&env->active_fpu.fpr[i]);
+}
+
+#undef printfpr
+}
+
+static void mips_cpu_dump_state(CPUState *cs, FILE *f, int flags)
+{
+MIPSCPU *cpu = MIPS_CPU(cs);
+CPUMIPSState *env = &cpu->env;
+int i;
+
+qemu_fprintf(f, "pc=0x" TARGET_FMT_lx " HI=0x" TARGET_FMT_lx
+ " LO=0x" TARGET_FMT_lx " ds %04x "
+ TARGET_FMT_lx " " TARGET_FMT_ld "\n",
+ env->active_tc.PC, env->active_tc.HI[0], env->active_tc.LO[0],
+ env->hflags, env->btarget, env->bcond);
+for (i = 0; i < 32; i++) {
+if ((i & 3) == 0) {
+qemu_fprintf(f, "GPR%02d:", i);
+}
+qemu_fprintf(f, " %s " TARGET_FMT_lx,
+ regnames[i], env->active_tc.gpr[i]);
+if ((i & 3) == 3) {
+qemu_fprintf(f, "\n");
+}
+}
+
+qemu_fprintf(f, "CP0 Status  0x%08x Cause   0x%08x EPC0x"
+ TARGET_FMT_lx "\n",
+ env->CP0_Status, env->CP0_Cause, env->CP0_EPC);
+qemu_fprintf(f, "Config0 0x%08x Config1 0x%08x LLAddr 0x%016"
+ PRIx64 "\n",
+ env->CP0_Config0, env->CP0_Config1, env->CP0_LLAddr);
+qemu_fprintf(f, "Config2 0x%08x Config3 0x%08x\n",
+ env->CP0_Config2, env->CP0_Config3);
+qemu_fprintf(f, "Config4 0x%08x Config5 0x%08x\n",
+ env->CP0_Config4, env->CP0_Config5);
+if ((flags & CPU_DUMP_FPU) && (env->hflags & MIPS_HFLAG_FPU)) {
+fpu_dump_state(env, f, flags);
+}
+}
+
 static const char * const excp_names[EXCP_LAST + 1] = {
 

[PATCH v2 19/29] target/mips: Restrict mmu_init() to TCG

[Philippe Mathieu-Daudé]

mmu_init() is only required by TCG accelerator.
Restrict its declaration and call to TCG.

Reviewed-by: Richard Henderson 
Signed-off-by: Philippe Mathieu-Daudé 
---
 target/mips/internal.h | 3 ---
 target/mips/tcg/tcg-internal.h | 2 ++
 target/mips/cpu.c  | 2 +-
 3 files changed, 3 insertions(+), 4 deletions(-)

diff --git a/target/mips/internal.h b/target/mips/internal.h
index d7980ba9a94..548fd73c7cc 100644
--- a/target/mips/internal.h
+++ b/target/mips/internal.h
@@ -233,9 +233,6 @@ void cpu_mips_store_compare(CPUMIPSState *env, uint32_t 
value);
 void cpu_mips_start_count(CPUMIPSState *env);
 void cpu_mips_stop_count(CPUMIPSState *env);
 
-/* helper.c */
-void mmu_init(CPUMIPSState *env, const mips_def_t *def);
-
 static inline void mips_cpu_set_error_pc(CPUMIPSState *env,
  target_ulong error_pc)
 {
diff --git a/target/mips/tcg/tcg-internal.h b/target/mips/tcg/tcg-internal.h
index b65580af211..70655bab45c 100644
--- a/target/mips/tcg/tcg-internal.h
+++ b/target/mips/tcg/tcg-internal.h
@@ -20,6 +20,8 @@ bool mips_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
 
 #if !defined(CONFIG_USER_ONLY)
 
+void mmu_init(CPUMIPSState *env, const mips_def_t *def);
+
 void update_pagemask(CPUMIPSState *env, target_ulong arg1, int32_t *pagemask);
 
 uint32_t cpu_mips_get_random(CPUMIPSState *env);
diff --git a/target/mips/cpu.c b/target/mips/cpu.c
index fcbf95c85b9..acc149aa573 100644
--- a/target/mips/cpu.c
+++ b/target/mips/cpu.c
@@ -708,7 +708,7 @@ static void mips_cpu_realizefn(DeviceState *dev, Error 
**errp)
 
 env->exception_base = (int32_t)0xBFC0;
 
-#ifndef CONFIG_USER_ONLY
+#if defined(CONFIG_TCG) && !defined(CONFIG_USER_ONLY)
 mmu_init(env, env->cpu_model);
 #endif
 fpu_init(env, env->cpu_model);
-- 
2.26.3

[PATCH v2 10/29] meson: Introduce meson_user_arch source set for arch-specific user-mode

[Philippe Mathieu-Daudé]

Similarly to the 'target_softmmu_arch' source set which allows
to restrict target-specific sources to system emulation, add
the equivalent 'target_user_arch' set for user emulation.

Reviewed-by: Richard Henderson 
Signed-off-by: Philippe Mathieu-Daudé 
---
v2: meson_user_arch -> target_user_arch in description (rth)

Cc: Paolo Bonzini 
---
 meson.build | 6 ++
 1 file changed, 6 insertions(+)

diff --git a/meson.build b/meson.build
index d8bb1ec5aa9..1ffdc9e6c4e 100644
--- a/meson.build
+++ b/meson.build
@@ -1751,6 +1751,7 @@
 hw_arch = {}
 target_arch = {}
 target_softmmu_arch = {}
+target_user_arch = {}
 
 ###
 # Trace files #
@@ -2168,6 +2169,11 @@
 abi = config_target['TARGET_ABI_DIR']
 target_type='user'
 qemu_target_name = 'qemu-' + target_name
+if arch in target_user_arch
+  t = target_user_arch[arch].apply(config_target, strict: false)
+  arch_srcs += t.sources()
+  arch_deps += t.dependencies()
+endif
 if 'CONFIG_LINUX_USER' in config_target
   base_dir = 'linux-user'
   target_inc += include_directories('linux-user/host/' / 
config_host['ARCH'])
-- 
2.26.3

[PATCH v2 17/29] target/mips: Restrict cpu_mips_get_random() / update_pagemask() to TCG

[Philippe Mathieu-Daudé]

Signed-off-by: Philippe Mathieu-Daudé 
---
 target/mips/internal.h | 4 
 target/mips/tcg/tcg-internal.h | 9 +
 2 files changed, 9 insertions(+), 4 deletions(-)

diff --git a/target/mips/internal.h b/target/mips/internal.h
index 8789ffb319f..d7980ba9a94 100644
--- a/target/mips/internal.h
+++ b/target/mips/internal.h
@@ -165,7 +165,6 @@ void r4k_helper_tlbr(CPUMIPSState *env);
 void r4k_helper_tlbinv(CPUMIPSState *env);
 void r4k_helper_tlbinvf(CPUMIPSState *env);
 void r4k_invalidate_tlb(CPUMIPSState *env, int idx, int use_extra);
-uint32_t cpu_mips_get_random(CPUMIPSState *env);
 
 void mips_cpu_do_transaction_failed(CPUState *cs, hwaddr physaddr,
 vaddr addr, unsigned size,
@@ -237,9 +236,6 @@ void cpu_mips_stop_count(CPUMIPSState *env);
 /* helper.c */
 void mmu_init(CPUMIPSState *env, const mips_def_t *def);
 
-/* op_helper.c */
-void update_pagemask(CPUMIPSState *env, target_ulong arg1, int32_t *pagemask);
-
 static inline void mips_cpu_set_error_pc(CPUMIPSState *env,
  target_ulong error_pc)
 {
diff --git a/target/mips/tcg/tcg-internal.h b/target/mips/tcg/tcg-internal.h
index 24438667f47..b65580af211 100644
--- a/target/mips/tcg/tcg-internal.h
+++ b/target/mips/tcg/tcg-internal.h
@@ -11,10 +11,19 @@
 #define MIPS_TCG_INTERNAL_H
 
 #include "hw/core/cpu.h"
+#include "cpu.h"
 
 void mips_cpu_do_interrupt(CPUState *cpu);
 bool mips_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
MMUAccessType access_type, int mmu_idx,
bool probe, uintptr_t retaddr);
 
+#if !defined(CONFIG_USER_ONLY)
+
+void update_pagemask(CPUMIPSState *env, target_ulong arg1, int32_t *pagemask);
+
+uint32_t cpu_mips_get_random(CPUMIPSState *env);
+
+#endif /* !CONFIG_USER_ONLY */
+
 #endif
-- 
2.26.3

[PATCH v2 21/29] target/mips: Restrict CPUMIPSTLBContext::map_address() handlers scope

[Philippe Mathieu-Daudé]

The 3 map_address() handlers are local to tlb_helper.c,
no need to have their prototype declared publically.

Reviewed-by: Richard Henderson 
Signed-off-by: Philippe Mathieu-Daudé 
---
 target/mips/internal.h  |  6 --
 target/mips/tcg/sysemu/tlb_helper.c | 13 +++--
 2 files changed, 7 insertions(+), 12 deletions(-)

diff --git a/target/mips/internal.h b/target/mips/internal.h
index df419760df0..a59e2f9007d 100644
--- a/target/mips/internal.h
+++ b/target/mips/internal.h
@@ -152,12 +152,6 @@ struct CPUMIPSTLBContext {
 } mmu;
 };
 
-int no_mmu_map_address(CPUMIPSState *env, hwaddr *physical, int *prot,
-   target_ulong address, MMUAccessType access_type);
-int fixed_mmu_map_address(CPUMIPSState *env, hwaddr *physical, int *prot,
-  target_ulong address, MMUAccessType access_type);
-int r4k_map_address(CPUMIPSState *env, hwaddr *physical, int *prot,
-target_ulong address, MMUAccessType access_type);
 void r4k_helper_tlbwi(CPUMIPSState *env);
 void r4k_helper_tlbwr(CPUMIPSState *env);
 void r4k_helper_tlbp(CPUMIPSState *env);
diff --git a/target/mips/tcg/sysemu/tlb_helper.c 
b/target/mips/tcg/sysemu/tlb_helper.c
index 82cfb0a9135..cbb4ccf0dac 100644
--- a/target/mips/tcg/sysemu/tlb_helper.c
+++ b/target/mips/tcg/sysemu/tlb_helper.c
@@ -26,8 +26,8 @@
 #include "hw/mips/cpudevs.h"
 
 /* no MMU emulation */
-int no_mmu_map_address(CPUMIPSState *env, hwaddr *physical, int *prot,
-   target_ulong address, MMUAccessType access_type)
+static int no_mmu_map_address(CPUMIPSState *env, hwaddr *physical, int *prot,
+  target_ulong address, MMUAccessType access_type)
 {
 *physical = address;
 *prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC;
@@ -35,8 +35,9 @@ int no_mmu_map_address(CPUMIPSState *env, hwaddr *physical, 
int *prot,
 }
 
 /* fixed mapping MMU emulation */
-int fixed_mmu_map_address(CPUMIPSState *env, hwaddr *physical, int *prot,
-  target_ulong address, MMUAccessType access_type)
+static int fixed_mmu_map_address(CPUMIPSState *env, hwaddr *physical,
+ int *prot, target_ulong address,
+ MMUAccessType access_type)
 {
 if (address <= (int32_t)0x7FFFUL) {
 if (!(env->CP0_Status & (1 << CP0St_ERL))) {
@@ -55,8 +56,8 @@ int fixed_mmu_map_address(CPUMIPSState *env, hwaddr 
*physical, int *prot,
 }
 
 /* MIPS32/MIPS64 R4000-style MMU emulation */
-int r4k_map_address(CPUMIPSState *env, hwaddr *physical, int *prot,
-target_ulong address, MMUAccessType access_type)
+static int r4k_map_address(CPUMIPSState *env, hwaddr *physical, int *prot,
+   target_ulong address, MMUAccessType access_type)
 {
 uint16_t ASID = env->CP0_EntryHi & env->CP0_EntryHi_ASID_mask;
 uint32_t MMID = env->CP0_MemoryMapID;
-- 
2.26.3

[PATCH v2 15/29] target/mips: Move sysemu specific files under sysemu/ subfolder

[Philippe Mathieu-Daudé]

Move sysemu-specific files under the new sysemu/ subfolder
and adapt the Meson machinery.
Update the KVM MIPS entry in MAINTAINERS.

Reviewed-by: Richard Henderson 
Signed-off-by: Philippe Mathieu-Daudé 
---
v2: Update MAINTAINERS
---
 target/mips/{ => sysemu}/addr.c  |  0
 target/mips/{ => sysemu}/cp0_timer.c |  0
 target/mips/{ => sysemu}/machine.c   |  0
 MAINTAINERS  |  3 ++-
 target/mips/meson.build  | 12 ++--
 target/mips/sysemu/meson.build   |  5 +
 6 files changed, 13 insertions(+), 7 deletions(-)
 rename target/mips/{ => sysemu}/addr.c (100%)
 rename target/mips/{ => sysemu}/cp0_timer.c (100%)
 rename target/mips/{ => sysemu}/machine.c (100%)
 create mode 100644 target/mips/sysemu/meson.build

diff --git a/target/mips/addr.c b/target/mips/sysemu/addr.c
similarity index 100%
rename from target/mips/addr.c
rename to target/mips/sysemu/addr.c
diff --git a/target/mips/cp0_timer.c b/target/mips/sysemu/cp0_timer.c
similarity index 100%
rename from target/mips/cp0_timer.c
rename to target/mips/sysemu/cp0_timer.c
diff --git a/target/mips/machine.c b/target/mips/sysemu/machine.c
similarity index 100%
rename from target/mips/machine.c
rename to target/mips/sysemu/machine.c
diff --git a/MAINTAINERS b/MAINTAINERS
index 36055f14c59..0620326544e 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -404,7 +404,8 @@ F: target/arm/kvm.c
 MIPS KVM CPUs
 M: Huacai Chen 
 S: Odd Fixes
-F: target/mips/kvm.c
+F: target/mips/kvm*
+F: target/mips/sysemu/
 
 PPC KVM CPUs
 M: David Gibson 
diff --git a/target/mips/meson.build b/target/mips/meson.build
index ca3cc62cf7a..9a507937ece 100644
--- a/target/mips/meson.build
+++ b/target/mips/meson.build
@@ -7,6 +7,7 @@
 ]
 
 mips_user_ss = ss.source_set()
+mips_softmmu_ss = ss.source_set()
 mips_ss = ss.source_set()
 mips_ss.add(files(
   'cpu.c',
@@ -14,6 +15,11 @@
   'gdbstub.c',
   'msa.c',
 ))
+
+if have_system
+  subdir('sysemu')
+endif
+
 mips_tcg_ss = ss.source_set()
 mips_tcg_ss.add(gen)
 mips_tcg_ss.add(files(
@@ -41,12 +47,6 @@
 
 mips_ss.add(when: 'CONFIG_KVM', if_true: files('kvm.c'))
 
-mips_softmmu_ss = ss.source_set()
-mips_softmmu_ss.add(files(
-  'addr.c',
-  'cp0_timer.c',
-  'machine.c',
-))
 mips_softmmu_ss.add(when: 'CONFIG_TCG', if_true: files(
   'cp0_helper.c',
   'mips-semi.c',
diff --git a/target/mips/sysemu/meson.build b/target/mips/sysemu/meson.build
new file mode 100644
index 000..f2a1ff46081
--- /dev/null
+++ b/target/mips/sysemu/meson.build
@@ -0,0 +1,5 @@
+mips_softmmu_ss.add(files(
+  'addr.c',
+  'cp0_timer.c',
+  'machine.c',
+))
-- 
2.26.3