Re: [PATCH v4 01/12] accel/tcg: Add stub for cpu_loop_exit()
On 30/09/2020 00.43, Philippe Mathieu-Daudé wrote:
> Since the support of SYS_READC in commit 8de702cb67 the
> semihosting code is strongly depedent of the TCG accelerator
> via a call to cpu_loop_exit().
>
> Ideally we would only build semihosting support when TCG
> is available, but unfortunately this is not trivial because
> semihosting is used by many targets in different configurations.
> For now add a simple stub to avoid link failure when building
> with --disable-tcg:
>
> hw/semihosting/console.c:160: undefined reference to `cpu_loop_exit'
>
> Cc: Keith Packard
> Signed-off-by: Philippe Mathieu-Daudé
> ---
> accel/stubs/tcg-stub.c | 5 +
> 1 file changed, 5 insertions(+)
>
> diff --git a/accel/stubs/tcg-stub.c b/accel/stubs/tcg-stub.c
> index e4bbf997aa..1eec7fb90e 100644
> --- a/accel/stubs/tcg-stub.c
> +++ b/accel/stubs/tcg-stub.c
> @@ -29,3 +29,8 @@ void *probe_access(CPUArchState *env, target_ulong addr,
> int size,
> /* Handled by hardware accelerator. */
> g_assert_not_reached();
> }
> +
> +void cpu_loop_exit(CPUState *cpu)
> +{
> +g_assert_not_reached();
> +}
>
Reviewed-by: Thomas Huth
Re: [RFC PATCH v5 2/2] hw/riscv: sifive_u: Add backend drive support
On Wed, Sep 30, 2020 at 1:08 AM Alistair Francis wrote:
>
> On Mon, Sep 28, 2020 at 2:18 AM Green Wan wrote:
> >
> > Hi Alistair,
> >
> > Thanks for the review. See the reply inline below.
> >
> >
> > On Sat, Sep 26, 2020 at 5:52 AM Alistair Francis
> > wrote:
> > >
> > > On Tue, Sep 1, 2020 at 8:49 AM Green Wan wrote:
> > > >
> > > > Add '-drive' support to OTP device. Allow users to assign a raw file
> > > > as OTP image.
> > >
> > > Do you mind writing an example command line argument in the commit
> > > message?
> > >
> > > Also, do you have a test case for this? I would like to add it to my CI.
> > >
> >
> > Do you mean qtest? I run uboot and use uboot driver to test it and
> > didn't create a qemu test case.
>
> No, I just mean how are you running and testing this.
>
> So you are booting U-Boot, then how do you test it in U-Boot?
Correct, I just enabled the configuration for
./drivers/misc/sifive-otp.c in uboot for normal booting access to OTP.
And manually modify some failures write case to test write-once
feature.
>
> > Here is the command I use:
> >
> > $ qemu-system-riscv64 -M sifive_u -m 256M -nographic -bios none
> > -kernel ../opensbi/build/platform/sifive/fu540/firmware/fw_payload.elf
> > -d guest_errors -drive if=none,format=raw,file=otp.img
> >
> > I'll check how to create a test case but maybe not that soon in the next
> > patch.
> >
> > > >
> > > > Signed-off-by: Green Wan
> > > > ---
> > > > hw/riscv/sifive_u_otp.c | 50 +
> > > > include/hw/riscv/sifive_u_otp.h | 2 ++
> > > > 2 files changed, 52 insertions(+)
> > > >
> > > > diff --git a/hw/riscv/sifive_u_otp.c b/hw/riscv/sifive_u_otp.c
> > > > index b8369e9035..477c54c7b8 100644
> > > > --- a/hw/riscv/sifive_u_otp.c
> > > > +++ b/hw/riscv/sifive_u_otp.c
> > > > @@ -24,6 +24,8 @@
> > > > #include "qemu/log.h"
> > > > #include "qemu/module.h"
> > > > #include "hw/riscv/sifive_u_otp.h"
> > > > +#include "sysemu/blockdev.h"
> > > > +#include "sysemu/block-backend.h"
> > > >
> > > > #define WRITTEN_BIT_ON 0x1
> > > >
> > > > @@ -54,6 +56,16 @@ static uint64_t sifive_u_otp_read(void *opaque,
> > > > hwaddr addr, unsigned int size)
> > > > if ((s->pce & SIFIVE_U_OTP_PCE_EN) &&
> > > > (s->pdstb & SIFIVE_U_OTP_PDSTB_EN) &&
> > > > (s->ptrim & SIFIVE_U_OTP_PTRIM_EN)) {
> > > > +
> > > > +/* read from backend */
> > > > +if (s->blk) {
> > > > +int32_t buf;
> > > > +
> > > > +blk_pread(s->blk, s->pa * SIFIVE_U_OTP_FUSE_WORD, &buf,
> > > > + SIFIVE_U_OTP_FUSE_WORD);
> > > > +return buf;
> > > > +}
> > > > +
> > > > return s->fuse[s->pa & SIFIVE_U_OTP_PA_MASK];
> > > > } else {
> > > > return 0xff;
> > > > @@ -145,6 +157,12 @@ static void sifive_u_otp_write(void *opaque,
> > > > hwaddr addr,
> > > > /* write bit data */
> > > > SET_FUSEARRAY_BIT(s->fuse, s->pa, s->paio, s->pdin);
> > > >
> > > > +/* write to backend */
> > > > +if (s->blk) {
> > > > +blk_pwrite(s->blk, s->pa * SIFIVE_U_OTP_FUSE_WORD,
> > > > &val32,
> > > > + SIFIVE_U_OTP_FUSE_WORD, 0);
> > > > +}
> > > > +
> > > > /* update written bit */
> > > > SET_FUSEARRAY_BIT(s->fuse_wo, s->pa, s->paio,
> > > > WRITTEN_BIT_ON);
> > > > }
> > > > @@ -168,16 +186,48 @@ static const MemoryRegionOps sifive_u_otp_ops = {
> > > >
> > > > static Property sifive_u_otp_properties[] = {
> > > > DEFINE_PROP_UINT32("serial", SiFiveUOTPState, serial, 0),
> > > > +DEFINE_PROP_DRIVE("drive", SiFiveUOTPState, blk),
> > > > DEFINE_PROP_END_OF_LIST(),
> > > > };
> > > >
> > > > static void sifive_u_otp_realize(DeviceState *dev, Error **errp)
> > > > {
> > > > SiFiveUOTPState *s = SIFIVE_U_OTP(dev);
> > > > +DriveInfo *dinfo;
> > > >
> > > > memory_region_init_io(&s->mmio, OBJECT(dev), &sifive_u_otp_ops, s,
> > > >TYPE_SIFIVE_U_OTP, SIFIVE_U_OTP_REG_SIZE);
> > > > sysbus_init_mmio(SYS_BUS_DEVICE(dev), &s->mmio);
> > > > +
> > > > +dinfo = drive_get_next(IF_NONE);
> > > > +if (dinfo) {
> > > > +int ret;
> > > > +uint64_t perm;
> > > > +int filesize;
> > > > +BlockBackend *blk;
> > > > +
> > > > +blk = blk_by_legacy_dinfo(dinfo);
> > >
> > > I think this should be:
> > >
> > > blk = dinfo ? blk_by_legacy_dinfo(dinfo) : NULL;
> > >
> >
> > The previous code, "if (dinfo)", should check NULL already. But we can
> > add more checks for blk such as qdev_prop_set_drive_err().
>
> You are right, but I don't see a fallback if !dinfo
>
Not sure whether we need it. Originally, I also added '!dinfo' check
logic and turned out I found it can be handled like without "-drive"
case. It just does a fallback to use the fuse[] array in memory. For
Re: [PATCH] PoC: Rust binding for QAPI (qemu-ga only, for now)
Marc-André Lureau writes:
> Hi
>
> On Tue, Sep 29, 2020 at 3:01 PM Paolo Bonzini wrote:
[...]
>> Marc-André, we are totally in agreement about that! The problem is that
>> you have already decided what the solution looks like, and that's what
>> I'm not sure about because your solution also implies completely
>> revisiting the schema.
>>
>
> Did I? Which schema change are you (or I) implying? Versioning the
> interface? It's necessary at the client level, unless everything is
> dynamic, after introspection, which makes automated static bindings
> impractical.
I disagree with "necessary".
A client can use a specific version of QMP, and still talk to a server
with a different version, because we designed that capability into QMP.
You absolutely can create bindings for a specific version of QMP for the
client if you want. Just make sure the client as a whole obeys the
rules of the QMP game laid down in qmp-spec.txt and qapi-code-gen.txt.
>> I say there are many candidates (the ones I know are Protobuf and
>> Flexbuffers) for serialization and many candidates for transport (REST
>> and gRPC to begin with) in addition to the two {QMP,JSON} and
>> {DBus,DBus} tuples. We should at least look at how they do code
>> generation before deciding that JSON is bad and DBus is good.
>>
>
> Contrary to what you believe I am not focusing so much on DBus here :) It
> took about 200 loc to bind it, effortlessly (compared to sys<->rs
> conversion). All it does is to expose the same API we have in the generated
> C somehow (similar static types & functions - not all as a{sv} opaque
> dictionaries).
Two points.
1. Opaque dictionaries are far from the only way to do keyword arguments
in a language that lacks them.
2. The API we generate for C is not exactly wonderful.
Behold this beauty:
void qmp_block_commit(bool has_job_id, const char *job_id, const char
*device, bool has_base_node, const char *base_node, bool has_base, const char
*base, bool has_top_node, const char *top_node, bool has_top, const char *top,
bool has_backing_file, const char *backing_file, bool has_speed, int64_t speed,
bool has_on_error, BlockdevOnError on_error, bool has_filter_node_name, const
char *filter_node_name, bool has_auto_finalize, bool auto_finalize, bool
has_auto_dismiss, bool auto_dismiss, Error **errp);
It's gotten so bad we added a second way to do the C API:
void qmp_drive_backup(DriveBackup *arg, Error **errp);
Turns out
DriveBackup arg = {
... initialize the optionals you need ...
}
qmp_drive_backup(&arg, &err);
is a lot easier on the eyes than passing 29 positional arguments.
This could be viewed as a work-around for C's lack of positional
parameters.
Even more fun:
void qmp_blockdev_add(BlockdevOptions *arg, Error **errp);
BlockdevOptions is a tagged union.
This could be viewed as a work-around for C's lack of function
overloading.
> It's easy for QEMU to generate a good static binding for C, because the
> version always matches. For a client, you wouldn't be able to write a
> similar idiomatic API in C, Rust, Python or Go, unfortunately.
I disagree. You won't be able to write good bindings using just
positional parameters. Not even if you add restrictions on how we can
evolve QMP. And no, I do not consider the C bindings we create for QEMU
itself "good". They're the best we could do, and good enough.
When you do bindings for another language, do bindings for that
language, not C bindings in that language.
Regardless of bindings, the client as a whole should obey the rules of
the QMP game laid down in qmp-spec.txt and qapi-code-gen.txt. If these
rules have become counter-productive, then it's time to replace QMP
wholesale.
Do not attempt to force a square peg into a round hole. If we must have
square pegs, design a square hole, and retire the round hole.
> Iow, I am not trying to sell DBus, I would like to make it easier to bind
> QMP in general. (although I do believe that DBus is a better protocol than
> QMP for local IPC, yes. And gRPC is probably better for remoting)
>
>> I would rather make those problems solved at the server level, that
>> > doesn't require any change to QMP today, just a more careful
>> > consideration when making changes (and probably some tools to help
>> > enforce some stability).
>>
>> Problem is, "more careful consideration when making changes" is not a
>> small thing. And other RPCs have evolved in a completely different
>> space (REST APIs for web services) that have chosen the same tradeoffs
>> as QMP, so why should we not learn from them?
>>
>>
> I don't buy that generalization. A very recent protocol in this space, that
> aims to be a good low-level RPC on Linux (for containers, cloud etc) is
> varlink. (In many ways, we could compare it to QMP, but it lacks some
> important features, like events)
>
> varlink does non-optional members and versioning the same way I propose
> here, for what I could tell. Although they use JSON, and
Re: [PATCH v10 13/13] tests/acpi: add DSDT.hpbrroot DSDT table blob to test global i440fx hotplug
On Tue, Sep 29, 2020 at 06:03:00PM +0530, Ani Sinha wrote:
> On Tue, Sep 29, 2020 at 5:05 PM Michael S. Tsirkin wrote:
> >
> > On Tue, Sep 29, 2020 at 04:58:03PM +0530, Ani Sinha wrote:
> > > On Tue, Sep 29, 2020 at 4:45 PM Michael S. Tsirkin
> > > wrote:
> > > >
> > > > On Tue, Sep 29, 2020 at 04:35:50PM +0530, Ani Sinha wrote:
> > > > > On Tue, Sep 29, 2020 at 4:25 PM Michael S. Tsirkin
> > > > > wrote:
> > > > > >
> > > > > > On Tue, Sep 29, 2020 at 04:11:45PM +0530, Ani Sinha wrote:
> > > > > > > On Tue, Sep 29, 2020 at 4:07 PM Michael S. Tsirkin
> > > > > > > wrote:
> > > > > > > >
> > > > > > > > On Tue, Sep 29, 2020 at 04:02:07PM +0530, Ani Sinha wrote:
> > > > > > > > > On Tue, Sep 29, 2020 at 4:00 PM Ani Sinha
> > > > > > > > > wrote:
> > > > > > > > > >
> > > > > > > > > > In your pull request the following patch is completely
> > > > > > > > > > screwed up:
> > > > > > > > > >
> > > > > > > > > > commit cda2006eded0ed91974e1d9e7f9f288e65812a3e
> > > > > > > > > > Author: Ani Sinha
> > > > > > > > > > Date: Tue Sep 29 03:22:52 2020 -0400
> > > > > > > > > >
> > > > > > > > > > tests/acpi: update golden master DSDT binary table
> > > > > > > > > > blobs for q35
> > > > > > > > > >
> > > > > > > > > >
> > > > > > > > > > This is not my patch. It has all sorts of changes which
> > > > > > > > > > does not
> > > > > > > > > > belong there. Can you please check?
> > > > > > > > >
> > > > > > > > > See
> > > > > > > > > https://patchew.org/QEMU/20200929071948.281157-1-...@redhat.com/20200929071948.281157-46-...@redhat.com/
> > > > > > > >
> > > > > > > >
> > > > > > > > I had to regenerate the binary, yes. That's par for the course.
> > > > > > > > But it looks like I added disasssembled files. Will fix up and
> > > > > > > > drop,
> > > > > > > > thanks for noticing this.
> > > > > >
> > > > > > OK I pushed out a fixed variant. Pls take a look.
> > > > >
> > > > > OK I am not used to this workflow. How am I supposed to get it? Which
> > > > > tag?
> > > >
> > > > New for_upstream tag - I just sent in a pull request.
> > >
> > > Can you please point me to your tree?
> >
> >
> > git://git.kernel.org/pub/scm/virt/kvm/mst/qemu.git tags/for_upstream
>
> I have sent the updated patches based on your pull request tag. I just
> had to regenrated the blob for tests/data/acpi/pc/DSDT.hpbrroot.
>
> make && make check-qtest-x86_64 V=1 passes.
>
> The diff looks good.
>
> Can you please send a pull request with these two patches ASAP?
Thanks, I will queue them and merge in the next pull request.
> >
> >
> >
> > > >
> > > > >
> > > > > >
> > > > > > > I think DSDT.hbridge is wrong. The checksum looks weird:
> > > > > > >
> > > > > > >
> > > > > > > + * Length 0x0B89 (2953)
> > > > > > > * Revision 0x01 32-bit table (V1), no 64-bit
> > > > > > > math support
> > > > > > > - * Checksum 0x05
> > > > > >
> > > > > > What is weird about it?
> > > > > >
> > > > > > >
> > > > > > > This file should be introduced just by one patch. my patch.
> > > > > >
> > > > > > I just re-run rebuild-expected-aml, no changes.
> > > > > >
> > > > > > I have this:
> > > > > > commit 5e3a486211f02d9ecb18939ca21087515ec81883
> > > > > > Author: Ani Sinha
> > > > > > Date: Fri Sep 18 14:11:05 2020 +0530
> > > > > >
> > > > > > tests/acpi: unit test for
> > > > > > 'acpi-pci-hotplug-with-bridge-support' bridge flag
> > > > > >
> > > > > > This change adds a new unit test for the global flag
> > > > > > 'acpi-pci-hotplug-with-bridge-support' which is available for
> > > > > > cold plugged pci
> > > > > > bridges in i440fx. The flag can be used to turn off ACPI based
> > > > > > hotplug support
> > > > > > on all pci bridges.
> > > > > >
> > > > > >
> > > > > > Here is the full DSDT header, attached:
> > > > > >
> > > > > > /*
> > > > > > * Intel ACPI Component Architecture
> > > > > > * AML/ASL+ Disassembler version 20190509 (64-bit version)
> > > > > > * Copyright (c) 2000 - 2019 Intel Corporation
> > > > > > *
> > > > > > * Disassembling to symbolic ASL+ operators
> > > > > > *
> > > > > > * Disassembly of tests/data/acpi/pc/DSDT.hpbridge, Tue Sep 29
> > > > > > 06:51:03 2020
> > > > > > *
> > > > > > * Original Table Header:
> > > > > > * Signature"DSDT"
> > > > > > * Length 0x139D (5021)
> > > > > > * Revision 0x01 32-bit table (V1), no 64-bit math
> > > > > > support
> > > > > > * Checksum 0x05
> > > > > > * OEM ID "BOCHS "
> > > > > > * OEM Table ID "BXPCDSDT"
> > > > > > * OEM Revision 0x0001 (1)
> > > > > > * Compiler ID "BXPC"
> > > > > > * Compiler Version 0x0001 (1)
> > > > > > */
> > > > > > DefinitionBlock ("", "DSDT", 1, "BOCHS ", "BXPCDSDT", 0x0001)
> > > > > >
> > > > > > --
> > > > > > MST
> > > > > >
> > > >
> >
Re: [PATCH v10 13/13] tests/acpi: add DSDT.hpbrroot DSDT table blob to test global i440fx hotplug
On Wed, Sep 30, 2020 at 1:06 PM Michael S. Tsirkin wrote: > On Tue, Sep 29, 2020 at 06:03:00PM +0530, Ani Sinha wrote: > > > On Tue, Sep 29, 2020 at 5:05 PM Michael S. Tsirkin > wrote: > > > > > > > > On Tue, Sep 29, 2020 at 04:58:03PM +0530, Ani Sinha wrote: > > > > > On Tue, Sep 29, 2020 at 4:45 PM Michael S. Tsirkin > wrote: > > > > > > > > > > > > On Tue, Sep 29, 2020 at 04:35:50PM +0530, Ani Sinha wrote: > > > > > > > On Tue, Sep 29, 2020 at 4:25 PM Michael S. Tsirkin < > m...@redhat.com> wrote: > > > > > > > > > > > > > > > > On Tue, Sep 29, 2020 at 04:11:45PM +0530, Ani Sinha wrote: > > > > > > > > > On Tue, Sep 29, 2020 at 4:07 PM Michael S. Tsirkin < > m...@redhat.com> wrote: > > > > > > > > > > > > > > > > > > > > On Tue, Sep 29, 2020 at 04:02:07PM +0530, Ani Sinha wrote: > > > > > > > > > > > On Tue, Sep 29, 2020 at 4:00 PM Ani Sinha < > a...@anisinha.ca> wrote: > > > > > > > > > > > > > > > > > > > > > > > > In your pull request the following patch is completely > screwed up: > > > > > > > > > > > > > > > > > > > > > > > > commit cda2006eded0ed91974e1d9e7f9f288e65812a3e > > > > > > > > > > > > Author: Ani Sinha > > > > > > > > > > > > Date: Tue Sep 29 03:22:52 2020 -0400 > > > > > > > > > > > > > > > > > > > > > > > > tests/acpi: update golden master DSDT binary table > blobs for q35 > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > This is not my patch. It has all sorts of changes > which does not > > > > > > > > > > > > belong there. Can you please check? > > > > > > > > > > > > > > > > > > > > > > See > https://patchew.org/QEMU/20200929071948.281157-1-...@redhat.com/20200929071948.281157-46-...@redhat.com/ > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > I had to regenerate the binary, yes. That's par for the > course. > > > > > > > > > > But it looks like I added disasssembled files. Will fix up > and drop, > > > > > > > > > > thanks for noticing this. > > > > > > > > > > > > > > > > OK I pushed out a fixed variant. Pls take a look. > > > > > > > > > > > > > > OK I am not used to this workflow. How am I supposed to get it? > Which tag? > > > > > > > > > > > > New for_upstream tag - I just sent in a pull request. > > > > > > > > > > Can you please point me to your tree? > > > > > > > > > > > > git://git.kernel.org/pub/scm/virt/kvm/mst/qemu.git tags/for_upstream > > > > > > I have sent the updated patches based on your pull request tag. I just > > > had to regenrated the blob for tests/data/acpi/pc/DSDT.hpbrroot. > > > > > > make && make check-qtest-x86_64 V=1 passes. > > > > > > The diff looks good. > > > > > > Can you please send a pull request with these two patches ASAP? > > > > > > Thanks, I will queue them and merge in the next pull request. I'm willing to get down on my knees begging you to just do one another pull request for these two patches. Were so close with my entire work merged. Please let's not wait another week or so. > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > I think DSDT.hbridge is wrong. The checksum looks weird: > > > > > > > > > > > > > > > > > > > > > > > > > > > + * Length 0x0B89 (2953) > > > > > > > > > * Revision 0x01 32-bit table (V1), no > 64-bit math support > > > > > > > > > - * Checksum 0x05 > > > > > > > > > > > > > > > > What is weird about it? > > > > > > > > > > > > > > > > > > > > > > > > > > This file should be introduced just by one patch. my patch. > > > > > > > > > > > > > > > > I just re-run rebuild-expected-aml, no changes. > > > > > > > > > > > > > > > > I have this: > > > > > > > > commit 5e3a486211f02d9ecb18939ca21087515ec81883 > > > > > > > > Author: Ani Sinha > > > > > > > > Date: Fri Sep 18 14:11:05 2020 +0530 > > > > > > > > > > > > > > > > tests/acpi: unit test for > 'acpi-pci-hotplug-with-bridge-support' bridge flag > > > > > > > > > > > > > > > > This change adds a new unit test for the global flag > > > > > > > > 'acpi-pci-hotplug-with-bridge-support' which is available > for cold plugged pci > > > > > > > > bridges in i440fx. The flag can be used to turn off ACPI > based hotplug support > > > > > > > > on all pci bridges. > > > > > > > > > > > > > > > > > > > > > > > > Here is the full DSDT header, attached: > > > > > > > > > > > > > > > > /* > > > > > > > > * Intel ACPI Component Architecture > > > > > > > > * AML/ASL+ Disassembler version 20190509 (64-bit version) > > > > > > > > * Copyright (c) 2000 - 2019 Intel Corporation > > > > > > > > * > > > > > > > > * Disassembling to symbolic ASL+ operators > > > > > > > > * > > > > > > > > * Disassembly of tests/data/acpi/pc/DSDT.hpbridge, Tue Sep 29 > 06:51:03 2020 > > > > > > > > * > > > > > > > > * Original Table Header: > > > > > > > > * Signature"DSDT" > > > > > > > > * Length 0x139D (5021) > > > > > > > > * Revision 0x01 32-bit table (V1), no 64-bit > math support
Re: [PATCH 00/16] hw/mips: Set CPU frequency
On Mon, 28 Sep 2020 19:15:23 +0200 Philippe Mathieu-Daudé wrote: > All the MIPS cores emulated by QEMU provides the Coproc#0 > 'Count' register which can be used as a free running timer. > > Since it's introduction in 2005 this timer uses a fixed > frequency of 100 MHz (for a CPU freq of 200 MHz). > While this is not an issue with Linux guests, it makes > some firmwares behave incorrectly. > > The Clock API allow propagating clocks. It is particularly > useful when hardware dynamicly changes clock frequencies. > > To be able to model such MIPS hardware, we need to refactor > the MIPS hardware code to handle clocks. > > This series is organized as follow: > > - let all CPU have an input clock, > - MIPS CPU get an input clock > - when the clock is changed, CP0 timer is updated > - set correct CPU frequencies to all boards > - do not allow MIPS CPU without input clock is this clock an integral part of MIPS cpus or it's an external device? > I used a MIPSsim test suggested by Thomas. It is also included > as bonus at the end. > > Possible follow up: > - QOM'ify the GIC > - let the GIC handle dynamic clock changes > > Regards, > > Phil. > > Philippe Mathieu-Daudé (16): > hw/core/cpu: Let CPU object have a clock source > target/mips: Move cpu_mips_get_random() with CP0 helpers > target/mips/cp0_timer: Explicit unit in variable name > target/mips/cpu: Introduce mips_cpu_properties[] > target/mips/cpu: Set default CPU frequency to 200 MHz > target/mips: Keep CP0 counter in sync with the CPU frequency > hw/mips/r4k: Explicit CPU frequency is 200 MHz > hw/mips/fuloong2e: Set CPU frequency to 533 MHz > hw/mips/mipssim: Correct CPU frequency > hw/mips/jazz: Correct CPU frequencies > hw/mips/cps: Expose input clock and connect it to CPU cores > hw/mips/boston: Set CPU frequency to 1 GHz > hw/mips/malta: Set CPU frequency to 320 MHz > hw/mips/cps: Do not allow use without input clock > target/mips/cpu: Do not allow system-mode use without input clock > tests/acceptance: Test the MIPSsim machine > > include/hw/core/cpu.h| 5 +++ > include/hw/mips/cps.h| 2 + > target/mips/cpu.h| 9 > target/mips/internal.h | 2 +- > hw/core/cpu.c| 12 + > hw/mips/boston.c | 13 ++ > hw/mips/cps.c| 8 > hw/mips/fuloong2e.c | 8 +++- > hw/mips/jazz.c | 16 ++- > hw/mips/malta.c | 20 +++-- > hw/mips/mipssim.c| 12 - > hw/mips/r4k.c| 8 +++- > target/mips/cp0_helper.c | 25 +++ > target/mips/cp0_timer.c | 51 ++--- > target/mips/cpu.c| 43 +- > MAINTAINERS | 1 + > tests/acceptance/machine_mips_mipssim.py | 56 > 17 files changed, 244 insertions(+), 47 deletions(-) > create mode 100644 tests/acceptance/machine_mips_mipssim.py >
Re: [PATCH 01/16] hw/core/cpu: Let CPU object have a clock source
On Mon, 28 Sep 2020 19:15:24 +0200
Philippe Mathieu-Daudé wrote:
> Let CPUState have a clock source (named 'clk') and CPUClass
> have a clock_update() callback. The clock can be optionally
> set Using qdev_connect_clock_in() from the Clock API.
> If the clock changes, the optional clock_update() will be
> called.
the sole user of it is mips cpu, so question is why
you are making it part of generic CPUm instead of
MIPSCPUClass/MIPSCPU?
>
> Signed-off-by: Philippe Mathieu-Daudé
> ---
> include/hw/core/cpu.h | 5 +
> hw/core/cpu.c | 12
> 2 files changed, 17 insertions(+)
>
> diff --git a/include/hw/core/cpu.h b/include/hw/core/cpu.h
> index 6c34798c8b3..6989d90c193 100644
> --- a/include/hw/core/cpu.h
> +++ b/include/hw/core/cpu.h
> @@ -31,6 +31,7 @@
> #include "qemu/thread.h"
> #include "qemu/plugin.h"
> #include "qom/object.h"
> +#include "hw/clock.h"
>
> typedef int (*WriteCoreDumpFunction)(const void *buf, size_t size,
> void *opaque);
> @@ -155,6 +156,7 @@ struct TranslationBlock;
> * @disas_set_info: Setup architecture specific components of disassembly
> info
> * @adjust_watchpoint_address: Perform a target-specific adjustment to an
> * address before attempting to match it against watchpoints.
> + * @clock_update: Callback for input clock changes
> *
> * Represents a CPU family or model.
> */
> @@ -176,6 +178,7 @@ struct CPUClass {
>unsigned size, MMUAccessType access_type,
>int mmu_idx, MemTxAttrs attrs,
>MemTxResult response, uintptr_t retaddr);
> +void (*clock_update)(CPUState *cpu);
> bool (*virtio_is_big_endian)(CPUState *cpu);
> int (*memory_rw_debug)(CPUState *cpu, vaddr addr,
> uint8_t *buf, int len, bool is_write);
> @@ -316,6 +319,7 @@ struct qemu_work_item;
> * QOM parent.
> * @nr_cores: Number of cores within this CPU package.
> * @nr_threads: Number of threads within this CPU.
> + * @clock: this CPU source clock (an output clock of another device)
> * @running: #true if CPU is currently running (lockless).
> * @has_waiter: #true if a CPU is currently waiting for the cpu_exec_end;
> * valid under cpu_list_lock.
> @@ -400,6 +404,7 @@ struct CPUState {
> int num_ases;
> AddressSpace *as;
> MemoryRegion *memory;
> +Clock *clock;
>
> void *env_ptr; /* CPUArchState */
> IcountDecr *icount_decr_ptr;
> diff --git a/hw/core/cpu.c b/hw/core/cpu.c
> index c55c09f734c..37fcff3ec64 100644
> --- a/hw/core/cpu.c
> +++ b/hw/core/cpu.c
> @@ -30,6 +30,7 @@
> #include "qemu/qemu-print.h"
> #include "sysemu/tcg.h"
> #include "hw/boards.h"
> +#include "hw/qdev-clock.h"
> #include "hw/qdev-properties.h"
> #include "trace/trace-root.h"
> #include "qemu/plugin.h"
> @@ -247,6 +248,16 @@ void cpu_reset(CPUState *cpu)
> trace_guest_cpu_reset(cpu);
> }
>
> +static void cpu_clk_update(void *opaque)
> +{
> +CPUState *cpu = opaque;
> +CPUClass *cc = CPU_GET_CLASS(cpu);
> +
> +if (cc->clock_update) {
> +cc->clock_update(cpu);
> +}
> +}
> +
> static void cpu_common_reset(DeviceState *dev)
> {
> CPUState *cpu = CPU(dev);
> @@ -367,6 +378,7 @@ static void cpu_common_initfn(Object *obj)
> /* the default value is changed by qemu_init_vcpu() for softmmu */
> cpu->nr_cores = 1;
> cpu->nr_threads = 1;
> +cpu->clock = qdev_init_clock_in(DEVICE(obj), "clk", cpu_clk_update, cpu);
>
> qemu_mutex_init(&cpu->work_mutex);
> QSIMPLEQ_INIT(&cpu->work_list);
Re: [PATCH v10 13/13] tests/acpi: add DSDT.hpbrroot DSDT table blob to test global i440fx hotplug
On Wed, Sep 30, 2020 at 01:09:09PM +0530, Ani Sinha wrote: > > > On Wed, Sep 30, 2020 at 1:06 PM Michael S. Tsirkin wrote: > > On Tue, Sep 29, 2020 at 06:03:00PM +0530, Ani Sinha wrote: > > > On Tue, Sep 29, 2020 at 5:05 PM Michael S. Tsirkin > wrote: > > > > > > > > On Tue, Sep 29, 2020 at 04:58:03PM +0530, Ani Sinha wrote: > > > > > On Tue, Sep 29, 2020 at 4:45 PM Michael S. Tsirkin > wrote: > > > > > > > > > > > > On Tue, Sep 29, 2020 at 04:35:50PM +0530, Ani Sinha wrote: > > > > > > > On Tue, Sep 29, 2020 at 4:25 PM Michael S. Tsirkin < > m...@redhat.com> wrote: > > > > > > > > > > > > > > > > On Tue, Sep 29, 2020 at 04:11:45PM +0530, Ani Sinha wrote: > > > > > > > > > On Tue, Sep 29, 2020 at 4:07 PM Michael S. Tsirkin < > m...@redhat.com> wrote: > > > > > > > > > > > > > > > > > > > > On Tue, Sep 29, 2020 at 04:02:07PM +0530, Ani Sinha wrote: > > > > > > > > > > > On Tue, Sep 29, 2020 at 4:00 PM Ani Sinha < > a...@anisinha.ca> wrote: > > > > > > > > > > > > > > > > > > > > > > > > In your pull request the following patch is completely > screwed up: > > > > > > > > > > > > > > > > > > > > > > > > commit cda2006eded0ed91974e1d9e7f9f288e65812a3e > > > > > > > > > > > > Author: Ani Sinha > > > > > > > > > > > > Date:  Tue Sep 29 03:22:52 2020 -0400 > > > > > > > > > > > > > > > > > > > > > > > >   tests/acpi: update golden master DSDT binary > table > blobs for q35 > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > This is not my patch. It has all sorts of changes > which > does not > > > > > > > > > > > > belong there. Can you please check? > > > > > > > > > > > > > > > > > > > > > > See https://patchew.org/QEMU/ > 20200929071948.281157-1-...@redhat.com/ > 20200929071948.281157-46-...@redhat.com/ > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > I had to regenerate the binary, yes. That's par for the > course. > > > > > > > > > > But it looks like I added disasssembled files. Will fix up > and drop, > > > > > > > > > > thanks for noticing this. > > > > > > > > > > > > > > > > OK I pushed out a fixed variant. Pls take a look. > > > > > > > > > > > > > > OK I am not used to this workflow. How am I supposed to get it? > Which tag? > > > > > > > > > > > > New for_upstream tag - I just sent in a pull request. > > > > > > > > > > Can you please point me to your tree? > > > > > > > > > > > >  git://git.kernel.org/pub/scm/virt/kvm/mst/qemu.git > tags/for_upstream > > > > > > I have sent the updated patches based on your pull request tag. I just > > > had to regenrated the blob for tests/data/acpi/pc/DSDT.hpbrroot. > > > > > > make && make check-qtest-x86_64 V=1 passes. > > > > > > The diff looks good. > > > > > > Can you please send a pull request with these two patches ASAP? > > > > > > Thanks, I will queue them and merge in the next pull request. > > > I'm willing to get down on my knees begging you to just do one another pull > request for these two patches. Were so close with my entire work merged. > > Please let's not wait another week or so. OK it's not too much work but ... could you please add justification about why adding this one unit test is needed so urgently? That motivation would be quite helpful for the pull request. > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > I think DSDT.hbridge is wrong. The checksum looks weird: > > > > > > > > > > > > > > > > > > > > > > > > > > > + *   Length      0x0B89 (2953) > > > > > > > > >  *   Revision     0x01 32-bit table > (V1), no > 64-bit math support > > > > > > > > > - *   Checksum     0x05 > > > > > > > > > > > > > > > > What is weird about it? > > > > > > > > > > > > > > > > > > > > > > > > > > This file should be introduced just by one patch. my patch. > > > > > > > > > > > > > > > > I just re-run rebuild-expected-aml, no changes. > > > > > > > > > > > > > > > > I have this: > > > > > > > > commit 5e3a486211f02d9ecb18939ca21087515ec81883 > > > > > > > > Author: Ani Sinha > > > > > > > > Date:  Fri Sep 18 14:11:05 2020 +0530 > > > > > > > > > > > > > > > >   tests/acpi: unit test for > 'acpi-pci-hotplug-with-bridge-support' bridge flag > > > > > > > > > > > > > > > >   This change adds a new unit test for the global flag > > > > > > > >   'acpi-pci-hotplug-with-bridge-support' which is > available > for cold plugged pci > > > > > > > >   bridges in i440fx. The flag can be used to turn off
Re: [PATCH v10 13/13] tests/acpi: add DSDT.hpbrroot DSDT table blob to test global i440fx hotplug
On Wed, Sep 30, 2020 at 1:14 PM Michael S. Tsirkin wrote: > On Wed, Sep 30, 2020 at 01:09:09PM +0530, Ani Sinha wrote: > > > > > > > > > On Wed, Sep 30, 2020 at 1:06 PM Michael S. Tsirkin > wrote: > > > > > > On Tue, Sep 29, 2020 at 06:03:00PM +0530, Ani Sinha wrote: > > > > > > > On Tue, Sep 29, 2020 at 5:05 PM Michael S. Tsirkin > > > > wrote: > > > > > > > > > > > > > > > > On Tue, Sep 29, 2020 at 04:58:03PM +0530, Ani Sinha wrote: > > > > > > > > > On Tue, Sep 29, 2020 at 4:45 PM Michael S. Tsirkin < > m...@redhat.com> > > > wrote: > > > > > > > > > > > > > > > > > > > > On Tue, Sep 29, 2020 at 04:35:50PM +0530, Ani Sinha wrote: > > > > > > > > > > > On Tue, Sep 29, 2020 at 4:25 PM Michael S. Tsirkin < > > > m...@redhat.com> wrote: > > > > > > > > > > > > > > > > > > > > > > > > On Tue, Sep 29, 2020 at 04:11:45PM +0530, Ani Sinha > wrote: > > > > > > > > > > > > > On Tue, Sep 29, 2020 at 4:07 PM Michael S. Tsirkin < > > > m...@redhat.com> wrote: > > > > > > > > > > > > > > > > > > > > > > > > > > > > On Tue, Sep 29, 2020 at 04:02:07PM +0530, Ani Sinha > wrote: > > > > > > > > > > > > > > > On Tue, Sep 29, 2020 at 4:00 PM Ani Sinha < > > > a...@anisinha.ca> wrote: > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > In your pull request the following patch is > completely > > > screwed up: > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > commit cda2006eded0ed91974e1d9e7f9f288e65812a3e > > > > > > > > > > > > > > > > Author: Ani Sinha > > > > > > > > > > > > > > > > Date: Tue Sep 29 03:22:52 2020 -0400 > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > tests/acpi: update golden master DSDT binary > table > > > blobs for q35 > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > This is not my patch. It has all sorts of > changes which > > > does not > > > > > > > > > > > > > > > > belong there. Can you please check? > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > See https://patchew.org/QEMU/ > > > 20200929071948.281157-1-...@redhat.com/ > > > 20200929071948.281157-46-...@redhat.com/ > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > I had to regenerate the binary, yes. That's par for > the > > > course. > > > > > > > > > > > > > > But it looks like I added disasssembled files. Will > fix up > > > and drop, > > > > > > > > > > > > > > thanks for noticing this. > > > > > > > > > > > > > > > > > > > > > > > > OK I pushed out a fixed variant. Pls take a look. > > > > > > > > > > > > > > > > > > > > > > OK I am not used to this workflow. How am I supposed to > get it? > > > Which tag? > > > > > > > > > > > > > > > > > > > > New for_upstream tag - I just sent in a pull request. > > > > > > > > > > > > > > > > > > Can you please point me to your tree? > > > > > > > > > > > > > > > > > > > > > > > > git://git.kernel.org/pub/scm/virt/kvm/mst/qemu.git > tags/for_upstream > > > > > > > > > > > > > > I have sent the updated patches based on your pull request tag. I > just > > > > > > > had to regenrated the blob for tests/data/acpi/pc/DSDT.hpbrroot. > > > > > > > > > > > > > > make && make check-qtest-x86_64 V=1 passes. > > > > > > > > > > > > > > The diff looks good. > > > > > > > > > > > > > > Can you please send a pull request with these two patches ASAP? > > > > > > > > > > > > > > > > > > Thanks, I will queue them and merge in the next pull request. > > > > > > > > > I'm willing to get down on my knees begging you to just do one another > pull > > > request for these two patches. Were so close with my entire work merged. > > > > > > Please let's not wait another week or so. > > > > > > OK it's not too much work but ... could you please add justification > > about why adding this one unit test is needed so urgently? > > That motivation would be quite helpful for the pull request. A patch without unit test doesn't complete the patch work. A unit test makes sure that the change would not get broken by other changes that come in later. Typically all code changes are accompanied by unit test in the same patch. Hence since the main work has already been merged, the unit test should merge ASAP so that no breakage can happen in between. Plus this completes an entire series of work which I've been working for a while. I really would love to see it all merged cleanly and fully completed. > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > I think DSDT.hbridge is wrong. The checksum looks > weird: > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > >
Re: [PATCH] PoC: Rust binding for QAPI (qemu-ga only, for now)
Hi
On Wed, Sep 30, 2020 at 11:34 AM Markus Armbruster
wrote:
> Marc-André Lureau writes:
>
> > Hi
> >
> > On Tue, Sep 29, 2020 at 3:01 PM Paolo Bonzini
> wrote:
> [...]
> >> Marc-André, we are totally in agreement about that! The problem is that
> >> you have already decided what the solution looks like, and that's what
> >> I'm not sure about because your solution also implies completely
> >> revisiting the schema.
> >>
> >
> > Did I? Which schema change are you (or I) implying? Versioning the
> > interface? It's necessary at the client level, unless everything is
> > dynamic, after introspection, which makes automated static bindings
> > impractical.
>
> I disagree with "necessary".
>
> A client can use a specific version of QMP, and still talk to a server
> with a different version, because we designed that capability into QMP.
>
"A client can use a specific version of QMP" == versioning on the client
side
>
> You absolutely can create bindings for a specific version of QMP for the
> client if you want. Just make sure the client as a whole obeys the
> rules of the QMP game laid down in qmp-spec.txt and qapi-code-gen.txt.
>
> >> I say there are many candidates (the ones I know are Protobuf and
> >> Flexbuffers) for serialization and many candidates for transport (REST
> >> and gRPC to begin with) in addition to the two {QMP,JSON} and
> >> {DBus,DBus} tuples. We should at least look at how they do code
> >> generation before deciding that JSON is bad and DBus is good.
> >>
> >
> > Contrary to what you believe I am not focusing so much on DBus here :) It
> > took about 200 loc to bind it, effortlessly (compared to sys<->rs
> > conversion). All it does is to expose the same API we have in the
> generated
> > C somehow (similar static types & functions - not all as a{sv} opaque
> > dictionaries).
>
> Two points.
>
> 1. Opaque dictionaries are far from the only way to do keyword arguments
> in a language that lacks them.
>
Oh one can always be creative. The point is trying to stay idiomatic in the
target language.
>
> 2. The API we generate for C is not exactly wonderful.
>
> Behold this beauty:
>
> void qmp_block_commit(bool has_job_id, const char *job_id, const char
> *device, bool has_base_node, const char *base_node, bool has_base, const
> char *base, bool has_top_node, const char *top_node, bool has_top, const
> char *top, bool has_backing_file, const char *backing_file, bool has_speed,
> int64_t speed, bool has_on_error, BlockdevOnError on_error, bool
> has_filter_node_name, const char *filter_node_name, bool has_auto_finalize,
> bool auto_finalize, bool has_auto_dismiss, bool auto_dismiss, Error **errp);
>
> It's gotten so bad we added a second way to do the C API:
>
> void qmp_drive_backup(DriveBackup *arg, Error **errp);
>
> Turns out
>
> DriveBackup arg = {
> ... initialize the optionals you need ...
> }
> qmp_drive_backup(&arg, &err);
>
> is a lot easier on the eyes than passing 29 positional arguments.
>
>
So is writing the function arguments with indentation. Then I don't see
much difference between a long list of arguments in a struct and that
function. The main difference is that you make it easy to pass those
arguments down. But often, you want to pass a subset, you don't want to
pass the whole context as it may lead to bad design / bugs.
This could be viewed as a work-around for C's lack of positional
> parameters.
>
>
Or a badly designed QMP command.
Even more fun:
>
> void qmp_blockdev_add(BlockdevOptions *arg, Error **errp);
>
> BlockdevOptions is a tagged union.
>
> This could be viewed as a work-around for C's lack of function
> overloading.
>
>
Or a badly designed QMP command ?
> It's easy for QEMU to generate a good static binding for C, because the
> > version always matches. For a client, you wouldn't be able to write a
> > similar idiomatic API in C, Rust, Python or Go, unfortunately.
>
> I disagree. You won't be able to write good bindings using just
> positional parameters. Not even if you add restrictions on how we can
> evolve QMP. And no, I do not consider the C bindings we create for QEMU
> itself "good". They're the best we could do, and good enough.
>
>
Sure they could be better, they are still quite idiomatic for C.
When you do bindings for another language, do bindings for that
> language, not C bindings in that language.
>
>
Yes
Regardless of bindings, the client as a whole should obey the rules of
> the QMP game laid down in qmp-spec.txt and qapi-code-gen.txt. If these
> rules have become counter-productive, then it's time to replace QMP
> wholesale.
>
> Do not attempt to force a square peg into a round hole. If we must have
> square pegs, design a square hole, and retire the round hole.
>
>
Hmm? I am trying to make the hole a bit more regular...
> Iow, I am not trying to sell DBus, I would like to make it easier to bind
> > QMP in general. (although I do believe that DBus is a better protocol
> than
> > QMP for l
Re: [PATCH v4 00/12] Support disabling TCG on ARM (part 2)
On Wed, 30 Sep 2020 00:43:43 +0200
Philippe Mathieu-Daudé wrote:
> Cover from Samuel Ortiz from (part 1) [1]:
>
> This patchset allows for building and running ARM targets with TCG
> disabled. [...]
>
> The rationale behind this work comes from the NEMU project where we're
> trying to only support x86 and ARM 64-bit architectures, without
> including the TCG code base. We can only do so if we can build and run
> ARM binaries with TCG disabled.
I don't recall exact reason but TCG variant is used by bios-tables-test
to test arm/virt so it will probably break that
(it has something to do with how KVM uses CPU/GIC, which was making
ACPI tables not stable (i.e. depend on host), so comparison with master
tables was failing)
>
> v4 almost 2 years later... [2]:
> - Rebased on Meson
> - Addressed Richard review comments
> - Addressed Claudio review comments
>
> v3 almost 18 months later [3]:
> - Rebased
> - Addressed Thomas review comments
> - Added Travis-CI job to keep building --disable-tcg on ARM
>
> v2 [4]:
> - Addressed review comments from Richard and Thomas from v1 [1]
>
> Regards,
>
> Phil.
>
> [1]: https://lists.gnu.org/archive/html/qemu-devel/2018-11/msg02451.html
> [2]: https://www.mail-archive.com/qemu-devel@nongnu.org/msg689168.html
> [3]: https://www.mail-archive.com/qemu-devel@nongnu.org/msg641796.html
> [4]: https://lists.gnu.org/archive/html/qemu-devel/2019-08/msg05003.html
>
> Green CI:
> - https://cirrus-ci.com/build/4572961761918976
> - https://gitlab.com/philmd/qemu/-/pipelines/196047779
> - https://travis-ci.org/github/philmd/qemu/builds/731370972
>
> Based-on: <20200929125609.1088330-1-phi...@redhat.com>
> "hw/arm: Restrict APEI tables generation to the 'virt' machine"
> https://www.mail-archive.com/qemu-devel@nongnu.org/msg745792.html
>
> Philippe Mathieu-Daudé (10):
> accel/tcg: Add stub for cpu_loop_exit()
> meson: Allow optional target/${ARCH}/Kconfig
> target/arm: Select SEMIHOSTING if TCG is available
> target/arm: Restrict ARMv4 cpus to TCG accel
> target/arm: Restrict ARMv5 cpus to TCG accel
> target/arm: Restrict ARMv6 cpus to TCG accel
> target/arm: Restrict ARMv7 R-profile cpus to TCG accel
> target/arm: Restrict ARMv7 M-profile cpus to TCG accel
> target/arm: Reorder meson.build rules
> .travis.yml: Add a KVM-only Aarch64 job
>
> Samuel Ortiz (1):
> target/arm: Do not build TCG objects when TCG is off
>
> Thomas Huth (1):
> target/arm: Make m_helper.c optional via CONFIG_ARM_V7M
>
> default-configs/arm-softmmu.mak | 3 --
> meson.build | 8 +++-
> target/arm/cpu.h| 12 --
> accel/stubs/tcg-stub.c | 5 +++
> target/arm/cpu_tcg.c| 4 +-
> target/arm/helper.c | 7
> target/arm/m_helper-stub.c | 73 +
> .travis.yml | 35
> hw/arm/Kconfig | 32 +++
> target/arm/Kconfig | 4 ++
> target/arm/meson.build | 40 +++---
> 11 files changed, 184 insertions(+), 39 deletions(-)
> create mode 100644 target/arm/m_helper-stub.c
> create mode 100644 target/arm/Kconfig
>
Re: [PATCH v4 04/12] target/arm: Restrict ARMv4 cpus to TCG accel
On 9/30/20 12:43 AM, Philippe Mathieu-Daudé wrote: > KVM requires a cpu based on (at least) the ARMv7 architecture. > > Only enable the following ARMv4 CPUs when TCG is available: > > - StrongARM (SA1100/1110) > - OMAP1510 (TI925T) > > Signed-off-by: Philippe Mathieu-Daudé > --- > hw/arm/Kconfig | 6 ++ > 1 file changed, 6 insertions(+) > > diff --git a/hw/arm/Kconfig b/hw/arm/Kconfig > index 7d040827af..b546b20654 100644 > --- a/hw/arm/Kconfig > +++ b/hw/arm/Kconfig > @@ -1,3 +1,7 @@ > +config ARM_V4 > +bool > +select TCG This should be 'depends on TCG' because we can not *select* TCG, either we enabled it or not. The problem is the machines are already selected in default-configs/arm-softmmu.mak, so we can not build the current config without TCG. > + > config ARM_VIRT > bool > imply PCI_DEVICES > @@ -30,6 +34,7 @@ config ARM_VIRT > > config CHEETAH > bool > +select ARM_V4 > select OMAP > select TSC210X > > @@ -244,6 +249,7 @@ config COLLIE > > config SX1 > bool > +select ARM_V4 > select OMAP > > config VERSATILE >
Re: [PATCH v10 13/13] tests/acpi: add DSDT.hpbrroot DSDT table blob to test global i440fx hotplug
On Wed, Sep 30, 2020 at 01:17:53PM +0530, Ani Sinha wrote: > > > On Wed, Sep 30, 2020 at 1:14 PM Michael S. Tsirkin wrote: > > On Wed, Sep 30, 2020 at 01:09:09PM +0530, Ani Sinha wrote: > > > > > > > > > On Wed, Sep 30, 2020 at 1:06 PM Michael S. Tsirkin > wrote: > > > > > >   On Tue, Sep 29, 2020 at 06:03:00PM +0530, Ani Sinha wrote: > > > > > >   > On Tue, Sep 29, 2020 at 5:05 PM Michael S. Tsirkin > > > >   wrote: > > > > > >   > > > > > > > >   > > On Tue, Sep 29, 2020 at 04:58:03PM +0530, Ani Sinha wrote: > > > > > >   > > > On Tue, Sep 29, 2020 at 4:45 PM Michael S. Tsirkin < > m...@redhat.com> > > >   wrote: > > > > > >   > > > > > > > > > >   > > > > On Tue, Sep 29, 2020 at 04:35:50PM +0530, Ani Sinha > wrote: > > > > > >   > > > > > On Tue, Sep 29, 2020 at 4:25 PM Michael S. Tsirkin < > > >   m...@redhat.com> wrote: > > > > > >   > > > > > > > > > > > >   > > > > > > On Tue, Sep 29, 2020 at 04:11:45PM +0530, Ani Sinha > wrote: > > > > > >   > > > > > > > On Tue, Sep 29, 2020 at 4:07 PM Michael S. Tsirkin > < > > >   m...@redhat.com> wrote: > > > > > >   > > > > > > > > > > > > > >   > > > > > > > > On Tue, Sep 29, 2020 at 04:02:07PM +0530, Ani > Sinha > wrote: > > > > > >   > > > > > > > > > On Tue, Sep 29, 2020 at 4:00 PM Ani Sinha < > > >   a...@anisinha.ca> wrote: > > > > > >   > > > > > > > > > > > > > > > >   > > > > > > > > > > In your pull request the following patch is > completely > > >   screwed up: > > > > > >   > > > > > > > > > > > > > > > >   > > > > > > > > > > commit > cda2006eded0ed91974e1d9e7f9f288e65812a3e > > > > > >   > > > > > > > > > > Author: Ani Sinha > > > > > >   > > > > > > > > > > Date:  Tue Sep 29 03:22:52 2020 -0400 > > > > > >   > > > > > > > > > > > > > > > >   > > > > > > > > > >   tests/acpi: update golden master DSDT > binary > table > > >   blobs for q35 > > > > > >   > > > > > > > > > > > > > > > >   > > > > > > > > > > > > > > > >   > > > > > > > > > > This is not my patch. It has all sorts of > changes > which > > >   does not > > > > > >   > > > > > > > > > > belong there. Can you please check? > > > > > >   > > > > > > > > > > > > > > >   > > > > > > > > > See https://patchew.org/QEMU/ > > >   20200929071948.281157-1-...@redhat.com/ > > >   20200929071948.281157-46-...@redhat.com/ > > > > > >   > > > > > > > > > > > > > >   > > > > > > > > > > > > > >   > > > > > > > > I had to regenerate the binary, yes. That's par > for > the > > >   course. > > > > > >   > > > > > > > > But it looks like I added disasssembled files. > Will > fix up > > >   and drop, > > > > > >   > > > > > > > > thanks for noticing this. > > > > > >   > > > > > > > > > > > >   > > > > > > OK I pushed out a fixed variant. Pls take a look. > > > > > >   > > > > > > > > > > >   > > > > > OK I am not used to this workflow. How am I supposed > to get > it? > > >   Which tag? > > > > > >   > > > > > > > > > >   > > > > New for_upstream tag - I just sent in a pull request. > > > > > >   > > > > > > > > >   > > > Can you please point me to your tree? > > > > > >   > > > > > > > >   > > > > > > > >   > >  git://git.kernel.org/pub/scm/virt/kvm/mst/qemu.git tags/ > for_upstream > > > > > >   > > > > > > >   > I have sent the updated patches based on your pull request > tag. I > just > > > > > >   > had to regenrated the blob for > tests/data/acpi/pc/DSDT.hpbrroot. > > > > > >   > > > > > > >   > make && make check-qtest-x86_64 V=1 passes. > > > > > >   > > > > > > >   > The diff looks good. > > > > > >   > > > > > > >   > Can you please send a pull request with these two patches ASAP? > > > > > > > > > > > > > > > > > >   Thanks, I will queue them and merge in the next pull request. > > > > > > > > > I'm willing to get down on my knees begging you to just do one another > pull > > > request for these two patches. Were so close with my entire work merged. > > > > > > Please let's not wait another week or so. > > > > > >
Re: [PATCH v10 13/13] tests/acpi: add DSDT.hpbrroot DSDT table blob to test global i440fx hotplug
On Wed, Sep 30, 2020 at 1:34 PM Michael S. Tsirkin wrote: > > On Wed, Sep 30, 2020 at 01:17:53PM +0530, Ani Sinha wrote: > > > > > > On Wed, Sep 30, 2020 at 1:14 PM Michael S. Tsirkin wrote: > > > > On Wed, Sep 30, 2020 at 01:09:09PM +0530, Ani Sinha wrote: > > > > > > > > > > > > > > > On Wed, Sep 30, 2020 at 1:06 PM Michael S. Tsirkin > > wrote: > > > > > > > > > > On Tue, Sep 29, 2020 at 06:03:00PM +0530, Ani Sinha wrote: > > > > > > > > > > > On Tue, Sep 29, 2020 at 5:05 PM Michael S. Tsirkin > > > > > > > wrote: > > > > > > > > > > > > > > > > > > > > > > > > On Tue, Sep 29, 2020 at 04:58:03PM +0530, Ani Sinha wrote: > > > > > > > > > > > > > On Tue, Sep 29, 2020 at 4:45 PM Michael S. Tsirkin < > > m...@redhat.com> > > > > > wrote: > > > > > > > > > > > > > > > > > > > > > > > > > > > > On Tue, Sep 29, 2020 at 04:35:50PM +0530, Ani Sinha wrote: > > > > > > > > > > > > > > > On Tue, Sep 29, 2020 at 4:25 PM Michael S. Tsirkin < > > > > > m...@redhat.com> wrote: > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > On Tue, Sep 29, 2020 at 04:11:45PM +0530, Ani Sinha > > wrote: > > > > > > > > > > > > > > > > > On Tue, Sep 29, 2020 at 4:07 PM Michael S. Tsirkin < > > > > > m...@redhat.com> wrote: > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > On Tue, Sep 29, 2020 at 04:02:07PM +0530, Ani > > Sinha > > wrote: > > > > > > > > > > > > > > > > > > > On Tue, Sep 29, 2020 at 4:00 PM Ani Sinha < > > > > > a...@anisinha.ca> wrote: > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > In your pull request the following patch is > > completely > > > > > screwed up: > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > commit > > cda2006eded0ed91974e1d9e7f9f288e65812a3e > > > > > > > > > > > > > > > > > > > > Author: Ani Sinha > > > > > > > > > > > > > > > > > > > > Date: Tue Sep 29 03:22:52 2020 -0400 > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > tests/acpi: update golden master DSDT > > binary > > table > > > > > blobs for q35 > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > This is not my patch. It has all sorts of > > changes > > which > > > > > does not > > > > > > > > > > > > > > > > > > > > belong there. Can you please check? > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > See https://patchew.org/QEMU/ > > > > > 20200929071948.281157-1-...@redhat.com/ > > > > > 20200929071948.281157-46-...@redhat.com/ > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > I had to regenerate the binary, yes. That's par > > for > > the > > > > > course. > > > > > > > > > > > > > > > > > > But it looks like I added disasssembled files. > > Will > > fix up > > > > > and drop, > > > > > > > > > > > > > > > > > > thanks for noticing this. > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > OK I pushed out a fixed variant. Pls take a look. > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > OK I am not used to this workflow. How am I supposed to > > get > > it? > > > > > Which tag? > > > > > > > > > > > > > > > > > > > > > > > > > > > > New for_upstream tag - I just sent in a pull request. > > > > > > > > > > > > > > > > > > > > > > > > > > Can you please point me to your tree? > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > git://git.kernel.org/pub/scm/virt/kvm/mst/qemu.git tags/ > > for_upstream > > > > > > > > > > > > > > > > > > > > > > I have sent the updated patches based on your pull request tag. > > I > > just > > > > > > > > > > > had to regenrated the blob for tests/data/acpi/pc/DSDT.hpbrroot. > > > > > > > > > > > > > > > > > > > > > > make && make check-qtest-x86_64 V=1 passes. > > > > > > > > > > > > > > > > > > > > > > The diff looks good. > > > > > > > > > > > > > > > > > > > > > > Can you please send a pull request with these two patches ASAP? > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > Thanks, I will queue them and merge in the next pull request. > >
Re: Outline for VHOST_USER_PROTOCOL_F_VDPA
On Tue, Sep 29, 2020 at 07:38:24PM +0100, Stefan Hajnoczi wrote: > On Tue, Sep 29, 2020 at 06:04:34AM -0400, Michael S. Tsirkin wrote: > > On Tue, Sep 29, 2020 at 09:57:51AM +0100, Stefan Hajnoczi wrote: > > > On Tue, Sep 29, 2020 at 02:09:55AM -0400, Michael S. Tsirkin wrote: > > > > On Mon, Sep 28, 2020 at 10:25:37AM +0100, Stefan Hajnoczi wrote: > > > > > Why extend vhost-user with vDPA? > > > > > > > > > > Reusing VIRTIO emulation code for vhost-user backends > > > > > - > > > > > It is a common misconception that a vhost device is a VIRTIO device. > > > > > VIRTIO devices are defined in the VIRTIO specification and consist of > > > > > a > > > > > configuration space, virtqueues, and a device lifecycle that includes > > > > > feature negotiation. A vhost device is a subset of the corresponding > > > > > VIRTIO device. The exact subset depends on the device type, and some > > > > > vhost devices are closer to the full functionality of their > > > > > corresponding VIRTIO device than others. The most well-known example > > > > > is > > > > > that vhost-net devices have rx/tx virtqueues and but lack the > > > > > virtio-net > > > > > control virtqueue. Also, the configuration space and device lifecycle > > > > > are only partially available to vhost devices. > > > > > > > > > > This difference makes it impossible to use a VIRTIO device as a > > > > > vhost-user device and vice versa. There is an impedance mismatch and > > > > > missing functionality. That's a shame because existing VIRTIO device > > > > > emulation code is mature and duplicating it to provide vhost-user > > > > > backends creates additional work. > > > > > > > > > > > > The biggest issue facing vhost-user and absent in vdpa is > > > > backend disconnect handling. This is the reason control path > > > > is kept under QEMU control: we do not need any logic to > > > > restore control path data, and we can verify a new backend > > > > is consistent with old one. > > > > > > I don't think using vhost-user with vDPA changes that. The VMM still > > > needs to emulate a virtio-pci/ccw/mmio device that the guest interfaces > > > with. If the device backend goes offline it's possible to restore that > > > state upon reconnection. What have I missed? > > > > The need to maintain the state in a way that is robust > > against backend disconnects and can be restored. > > QEMU is only bypassed for virtqueue accesses. Everything else still > goes through the virtio-pci emulation in QEMU (VIRTIO configuration > space, status register). vDPA doesn't change this. > > Existing vhost-user messages can be kept if they are useful (e.g. > virtqueue state tracking). So I think the situation is no different than > with the existing vhost-user protocol. > > > > Regarding reconnection in general, it currently seems like a partially > > > solved problem in vhost-user. There is the "Inflight I/O tracking" > > > mechanism in the spec and some wording about reconnecting the socket, > > > but in practice I wouldn't expect all device types, VMMs, or device > > > backends to actually support reconnection. This is an area where a > > > uniform solution would be very welcome too. > > > > I'm not aware of big issues. What are they? > > I think "Inflight I/O tracking" can only be used when request processing > is idempotent? In other words, it can only be used when submitting the > same request multiple times is safe. Not inherently it just does not attempt to address this problem. Inflight tracking only tries to address issues on the guest side, that is, making sure the same buffer is used exactly once. > A silly example where this recovery mechanism cannot be used is if a > device has a persistent counter that is incremented by the request. The > guest can't be sure that the counter will be incremented exactly once. > > Another example: devices that support requests with compare-and-swap > semantics cannot use this mechanism. During recover the compare will > fail if the request was just completing when the backend crashed. > > Do I understand the limitations of this mechanism correctly? It doesn't > seem general and I doubt it can be applied to all existing device types. Device with any kind of atomicity guarantees will have to use some internal mechanism (e.g. log?) to ensure internal consistency, that is out of scope for tracking. > > > There was discussion about recovering state in muser. The original idea > > > was for the muser kernel module to host state that persists across > > > device backend restart. That way the device backend can go away > > > temporarily and resume without guest intervention. > > > > > > Then when the vfio-user discussion started the idea morphed into simply > > > keeping a tmpfs file for each device instance (no special muser.ko > > > support needed anymore). This allows the device backend to resume > > > without losing state. In prac
Re: [PATCH v5 03/14] hw/block/nvme: Introduce the Namespace Types definitions
On Sep 28 11:35, Dmitry Fomichev wrote:
> From: Niklas Cassel
>
> Define the structures and constants required to implement
> Namespace Types support.
>
> Signed-off-by: Niklas Cassel
> Signed-off-by: Dmitry Fomichev
> ---
> hw/block/nvme-ns.h | 2 ++
> hw/block/nvme.c | 2 +-
> include/block/nvme.h | 74 +++-
> 3 files changed, 63 insertions(+), 15 deletions(-)
>
> diff --git a/hw/block/nvme-ns.h b/hw/block/nvme-ns.h
> index 83734f4606..cca23bc0b3 100644
> --- a/hw/block/nvme-ns.h
> +++ b/hw/block/nvme-ns.h
> @@ -21,6 +21,8 @@
>
> typedef struct NvmeNamespaceParams {
> uint32_t nsid;
> +uint8_t csi;
> +QemuUUID uuid;
> } NvmeNamespaceParams;
The motivation behind the NvmeNamespaceParams was to only keep user
visible parameters in this struct.
Can we move csi/uuid to the NvmeNamespace struct?
signature.asc
Description: PGP signature
Re: [PATCH v5 05/14] hw/block/nvme: Add support for Namespace Types
On Sep 28 11:35, Dmitry Fomichev wrote: > From: Niklas Cassel > > Namespace Types introduce a new command set, "I/O Command Sets", > that allows the host to retrieve the command sets associated with > a namespace. Introduce support for the command set and enable > detection for the NVM Command Set. > > The new workflows for identify commands rely heavily on zero-filled > identify structs. E.g., certain CNS commands are defined to return > a zero-filled identify struct when an inactive namespace NSID > is supplied. > > Add a helper function in order to avoid code duplication when > reporting zero-filled identify structures. > > Signed-off-by: Niklas Cassel > Signed-off-by: Dmitry Fomichev > --- > hw/block/nvme-ns.c | 3 + > hw/block/nvme.c| 210 + > 2 files changed, 175 insertions(+), 38 deletions(-) > > diff --git a/hw/block/nvme-ns.c b/hw/block/nvme-ns.c > index bbd7879492..31b7f986c3 100644 > --- a/hw/block/nvme-ns.c > +++ b/hw/block/nvme-ns.c > @@ -40,6 +40,9 @@ static void nvme_ns_init(NvmeNamespace *ns) > > id_ns->nsze = cpu_to_le64(nvme_ns_nlbas(ns)); > > +ns->params.csi = NVME_CSI_NVM; > +qemu_uuid_generate(&ns->params.uuid); /* TODO make UUIDs persistent */ > + It is straight-forward to put this into a 'uuid' nvme-ns parameter using DEFINE_PROP_UUID. That will default to 'auto' which will generate an UUID for each invocation, but if the user requires it to be "persistent", it can be specified explicitly. If you choose to do this, please extract to separate patch. Or I can post it on top of nvme-next if you like. signature.asc Description: PGP signature
[Bug 1849644] Re: QEMU VNC websocket proxy requires non-standard 'binary' subprotocol
Trying to connect using novnc latest/stable:1.2.0 2020-07-31 (6) 18MB - as-is failing to connect Keeping VNC up and refreshing qemu. Updating to the new qemu from focal proposed (by now resolved the archive publishing issues we had before this morning). Get:67 http://archive.ubuntu.com/ubuntu focal-proposed/main amd64 qemu-utils amd64 1:4.2-3ubuntu6.7 [975 kB] Get:68 http://archive.ubuntu.com/ubuntu focal-proposed/main amd64 qemu-system-common amd64 1:4.2-3ubuntu6.7 [1056 kB] Get:69 http://archive.ubuntu.com/ubuntu focal-proposed/main amd64 qemu-block-extra amd64 1:4.2-3ubuntu6.7 [53.8 kB] Get:70 http://archive.ubuntu.com/ubuntu focal-proposed/main amd64 qemu-system-data all 1:4.2-3ubuntu6.7 [563 kB] Get:71 http://archive.ubuntu.com/ubuntu focal-proposed/main amd64 qemu-kvm amd64 1:4.2-3ubuntu6.7 [13.1 kB] Get:72 http://archive.ubuntu.com/ubuntu focal-proposed/main amd64 qemu-system-x86 amd64 1:4.2-3ubuntu6.7 [6720 kB] Get:73 http://archive.ubuntu.com/ubuntu focal-proposed/main amd64 qemu-system-gui amd64 1:4.2-3ubuntu6.7 [40.8 kB] Get:74 http://archive.ubuntu.com/ubuntu focal-proposed/main amd64 qemu-system-mips amd64 1:4.2-3ubuntu6.7 [12.9 MB] Now the same novnc1.2 can connect to it \o/ Setting verified ** Tags removed: verification-needed verification-needed-focal ** Tags added: verification-done verification-done-focal -- You received this bug notification because you are a member of qemu- devel-ml, which is subscribed to QEMU. https://bugs.launchpad.net/bugs/1849644 Title: QEMU VNC websocket proxy requires non-standard 'binary' subprotocol Status in QEMU: Fix Released Status in qemu package in Ubuntu: Fix Released Status in qemu source package in Focal: Fix Committed Bug description: [Impact] * The exact details of the protocol/subprotocal was slightly unclear between the projects. So qemu ended up insisting on "binary" being used but newer noVNC clients no more used it. * Qemu got fixed in 5.0 to be more tolerant and accept an empty sub- protocol as well. This SRU backports that fix to Focal. [Test Case] * Without the fix the following will "Failed to connect", but with the fix it will work. $ sudo apt install qemu-system-x86 # will only boot into a failing bootloader, but that is enough $ qemu-system-x86_64 -vnc :0,websocket # We need version 1.2 or later, so use the snap $ snap install novnc $ novnc --vnc localhost:5700 Connect browser to http://:6080/vnc.html Click "Connect" * Cross check with an older noVNC (e.g. the one in Focal) if the connectivity still works on those as well - Reminders when switching between the noVNC implementations - always refresh the browser with all clear ctrl+alt+f5 - start/stop the snapped one via snap.novnc.novncsvc.service [Regression Potential] * This is exclusive to the functionality of noVNC, so regressions would have to be expected in there. The tests try to exercise the basics, but e.g. Openstack would be a major product using [Other Info] * The noVNC in Focal itself does not yet have the offending change, but we want the qemu in focal to be connecteable from ~any type of client --- When running a machine using "-vnc" and the "websocket" option QEMU seems to require the subprotocol called 'binary'. This subprotocol does not exist in the WebSocket specification. In fact it has never existed in the spec, in one of the very early drafts of WebSockets it was briefly mentioned but it never made it to a final version. When the WebSocket server requires a non-standard subprotocol any WebSocket client that works correctly won't be able to connect. One example of such a client is noVNC, it tells the server that it doesn't want to use any subprotocol. QEMU's WebSocket proxy doesn't let noVNC connect. If noVNC is modified to ask for 'binary' it will work, this is, however, incorrect behavior. Looking at the code in "io/channel-websock.c" it seems it's quite hard-coded to binary: Look at line 58 and 433 here: https://git.qemu.org/?p=qemu.git;a=blob;f=io/channel-websock.c This code has to be made more dynamic, and shouldn't require binary. To manage notifications about this bug go to: https://bugs.launchpad.net/qemu/+bug/1849644/+subscriptions
Re: [PATCH] hw/rtc/m48t59: Simplify m48t59_init()
On 24/09/2020 16:00, Laurent Vivier wrote: > Le 24/09/2020 à 16:53, Philippe Mathieu-Daudé a écrit : >> On 9/16/20 4:50 AM, David Gibson wrote: >>> On Mon, Sep 14, 2020 at 12:24:25PM +0200, Philippe Mathieu-Daudé wrote: As the 'io_base' argument of m48t59_init() is unused (set to 0), remove it to simplify. To create a device on the ISA bus, m48t59_init_isa() is the preferred function to use. Signed-off-by: Philippe Mathieu-Daudé --- include/hw/rtc/m48t59.h | 2 +- hw/ppc/ppc405_boards.c | 2 +- hw/rtc/m48t59.c | 10 ++ hw/sparc/sun4m.c| 2 +- hw/sparc64/sun4u.c | 2 +- 5 files changed, 6 insertions(+), 12 deletions(-) >>> >>> ppc part >>> Acked-by: David Gibson >> >> Thanks! >> >> Can this go via qemu-trivial@? > > Yes, but more reviewers would help. Mark? Ooof sorry I missed this one. Let me take a quick look now... ATB, Mark.
Re: [PATCH] hw/rtc/m48t59: Simplify m48t59_init()
On 14/09/2020 11:24, Philippe Mathieu-Daudé wrote:
> As the 'io_base' argument of m48t59_init() is unused (set to 0),
> remove it to simplify.
> To create a device on the ISA bus, m48t59_init_isa() is the
> preferred function to use.
>
> Signed-off-by: Philippe Mathieu-Daudé
> ---
> include/hw/rtc/m48t59.h | 2 +-
> hw/ppc/ppc405_boards.c | 2 +-
> hw/rtc/m48t59.c | 10 ++
> hw/sparc/sun4m.c| 2 +-
> hw/sparc64/sun4u.c | 2 +-
> 5 files changed, 6 insertions(+), 12 deletions(-)
>
> diff --git a/include/hw/rtc/m48t59.h b/include/hw/rtc/m48t59.h
> index 04abedf3b2b..62297ee0db1 100644
> --- a/include/hw/rtc/m48t59.h
> +++ b/include/hw/rtc/m48t59.h
> @@ -50,7 +50,7 @@ struct NvramClass {
> Nvram *m48t59_init_isa(ISABus *bus, uint32_t io_base, uint16_t size,
> int base_year, int type);
> Nvram *m48t59_init(qemu_irq IRQ, hwaddr mem_base,
> - uint32_t io_base, uint16_t size, int base_year,
> + uint16_t size, int base_year,
> int type);
>
> #endif /* HW_M48T59_H */
> diff --git a/hw/ppc/ppc405_boards.c b/hw/ppc/ppc405_boards.c
> index 6198ec1035b..93ffee801a3 100644
> --- a/hw/ppc/ppc405_boards.c
> +++ b/hw/ppc/ppc405_boards.c
> @@ -227,7 +227,7 @@ static void ref405ep_init(MachineState *machine)
> /* Register FPGA */
> ref405ep_fpga_init(sysmem, 0xF030);
> /* Register NVRAM */
> -m48t59_init(NULL, 0xF000, 0, 8192, 1968, 8);
> +m48t59_init(NULL, 0xF000, 8192, 1968, 8);
> /* Load kernel */
> linux_boot = (kernel_filename != NULL);
> if (linux_boot) {
> diff --git a/hw/rtc/m48t59.c b/hw/rtc/m48t59.c
> index 6525206976b..2d6a095c4e4 100644
> --- a/hw/rtc/m48t59.c
> +++ b/hw/rtc/m48t59.c
> @@ -566,7 +566,7 @@ const MemoryRegionOps m48t59_io_ops = {
>
> /* Initialisation routine */
> Nvram *m48t59_init(qemu_irq IRQ, hwaddr mem_base,
> - uint32_t io_base, uint16_t size, int base_year,
> + uint16_t size, int base_year,
> int model)
> {
> DeviceState *dev;
> @@ -584,13 +584,7 @@ Nvram *m48t59_init(qemu_irq IRQ, hwaddr mem_base,
> s = SYS_BUS_DEVICE(dev);
> sysbus_realize_and_unref(s, &error_fatal);
> sysbus_connect_irq(s, 0, IRQ);
> -if (io_base != 0) {
> -memory_region_add_subregion(get_system_io(), io_base,
> -sysbus_mmio_get_region(s, 1));
> -}
> -if (mem_base != 0) {
> -sysbus_mmio_map(s, 0, mem_base);
> -}
> +sysbus_mmio_map(s, 0, mem_base);
>
> return NVRAM(s);
> }
> diff --git a/hw/sparc/sun4m.c b/hw/sparc/sun4m.c
> index 947b69d1597..56a0d38f274 100644
> --- a/hw/sparc/sun4m.c
> +++ b/hw/sparc/sun4m.c
> @@ -970,7 +970,7 @@ static void sun4m_hw_init(const struct sun4m_hwdef *hwdef,
> create_unimplemented_device("SUNW,sx", hwdef->sx_base, 0x2000);
> }
>
> -nvram = m48t59_init(slavio_irq[0], hwdef->nvram_base, 0, 0x2000, 1968,
> 8);
> +nvram = m48t59_init(slavio_irq[0], hwdef->nvram_base, 0x2000, 1968, 8);
>
> slavio_timer_init_all(hwdef->counter_base, slavio_irq[19],
> slavio_cpu_irq, smp_cpus);
>
> diff --git a/hw/sparc64/sun4u.c b/hw/sparc64/sun4u.c
> index b4aabfc076f..1cc57b030a7 100644
> --- a/hw/sparc64/sun4u.c
> +++ b/hw/sparc64/sun4u.c
> @@ -675,7 +675,7 @@ static void sun4uv_init(MemoryRegion *address_space_mem,
> pci_ide_create_devs(pci_dev);
>
> /* Map NVRAM into I/O (ebus) space */
> -nvram = m48t59_init(NULL, 0, 0, NVRAM_SIZE, 1968, 59);
> +nvram = m48t59_init(NULL, 0, NVRAM_SIZE, 1968, 59);
> s = SYS_BUS_DEVICE(nvram);
> memory_region_add_subregion(pci_address_space_io(ebus), 0x2000,
> sysbus_mmio_get_region(s, 0));
Looks good to me. In fact, if you're working in this area there are a couple of
other
quick wins here too:
- Remove m48t59_init() and replace with QOM/qdev properties
- Remove m48t59_init_isa() as this seems to be unused, along with the associated
complexity of handling the m48txx_isa_info[] array
Anyhow:
Reviewed-by: Mark Cave-Ayland
ATB,
Mark.
[PULL 0/2] acpi: unit test
The following changes since commit f142e4ede72853aaa7d306bc79b099caed45769b: tests/acpi: drop unnecessary files (2020-09-29 07:10:37 -0400) are available in the Git repository at: git://git.kernel.org/pub/scm/virt/kvm/mst/qemu.git tags/for_upstream for you to fetch changes up to 42803552319a5481e90e93382d74a7336dfab496: tests/acpi: add DSDT.hpbrroot DSDT table blob to test global i440fx hotplug (2020-09-30 04:10:51 -0400) acpi: unit test This just adds a unit test for previously merged functionality. A bit unusual, but we have a contribitor under a deadline, let's be nice and merge the unit test right away - does no harm. Hopefully this won't be a beginning of a trend ... Signed-off-by: Michael S. Tsirkin Ani Sinha (2): tests/acpi: unit test exercising global pci hotplug off for i440fx tests/acpi: add DSDT.hpbrroot DSDT table blob to test global i440fx hotplug tests/qtest/bios-tables-test.c | 17 + tests/data/acpi/pc/DSDT.hpbrroot | Bin 0 -> 3079 bytes 2 files changed, 17 insertions(+) create mode 100644 tests/data/acpi/pc/DSDT.hpbrroot
[PULL 1/2] tests/acpi: unit test exercising global pci hotplug off for i440fx
From: Ani Sinha
This change adds a unit test to exercise the case when hotplug is disabled
both for pci root bus and the pci bridges by passing the following two
switches to qemu:
-global PIIX4_PM.acpi-root-pci-hotplug=off
-global PIIX4_PM.acpi-pci-hotplug-with-bridge-support=off
bios-tables-test-allowed-diff.h documents the fact that a new DSDT acpi gold
master binary blob we need to be added to test this. We will do the actual
addition in the next patch in the series.
Signed-off-by: Ani Sinha
Reviewed-by: Igor Mammedov
Message-Id: <20200929123011.31836-2-...@anisinha.ca>
Reviewed-by: Michael S. Tsirkin
Signed-off-by: Michael S. Tsirkin
---
tests/qtest/bios-tables-test-allowed-diff.h | 1 +
tests/qtest/bios-tables-test.c | 17 +
2 files changed, 18 insertions(+)
diff --git a/tests/qtest/bios-tables-test-allowed-diff.h
b/tests/qtest/bios-tables-test-allowed-diff.h
index dfb8523c8b..dea61d94f1 100644
--- a/tests/qtest/bios-tables-test-allowed-diff.h
+++ b/tests/qtest/bios-tables-test-allowed-diff.h
@@ -1 +1,2 @@
/* List of comma-separated changed AML files to ignore */
+"tests/data/acpi/pc/DSDT.hpbrroot",
diff --git a/tests/qtest/bios-tables-test.c b/tests/qtest/bios-tables-test.c
index 3c09b844f9..b514b70b62 100644
--- a/tests/qtest/bios-tables-test.c
+++ b/tests/qtest/bios-tables-test.c
@@ -770,6 +770,21 @@ static void test_acpi_piix4_no_bridge_hotplug(void)
free_test_data(&data);
}
+static void test_acpi_piix4_no_acpi_pci_hotplug(void)
+{
+test_data data;
+
+memset(&data, 0, sizeof(data));
+data.machine = MACHINE_PC;
+data.variant = ".hpbrroot";
+data.required_struct_types = base_required_struct_types;
+data.required_struct_types_len = ARRAY_SIZE(base_required_struct_types);
+test_acpi_one("-global PIIX4_PM.acpi-root-pci-hotplug=off "
+ "-global PIIX4_PM.acpi-pci-hotplug-with-bridge-support=off "
+ "-device pci-bridge,chassis_nr=1", &data);
+free_test_data(&data);
+}
+
static void test_acpi_q35_tcg(void)
{
test_data data;
@@ -1192,6 +1207,8 @@ int main(int argc, char *argv[])
test_acpi_piix4_no_root_hotplug);
qtest_add_func("acpi/piix4/pci-hotplug/no_bridge_hotplug",
test_acpi_piix4_no_bridge_hotplug);
+qtest_add_func("acpi/piix4/pci-hotplug/off",
+ test_acpi_piix4_no_acpi_pci_hotplug);
qtest_add_func("acpi/q35", test_acpi_q35_tcg);
qtest_add_func("acpi/q35/bridge", test_acpi_q35_tcg_bridge);
qtest_add_func("acpi/q35/mmio64", test_acpi_q35_tcg_mmio64);
--
MST
[PULL 2/2] tests/acpi: add DSDT.hpbrroot DSDT table blob to test global i440fx hotplug
From: Ani Sinha
This change adds a new DSDT golden master table blob to test disabling
hotplug on both pci root bus and pci bridges. Also reverts the change
in file bios-tables-test-allowed-diff.h to make sure its now empty so that
future modifications to acpi tables can be caught.
The following is the disassembled diff between DSDT.hpbridge and DSDT.hpbrroot:
@@ -5,13 +5,13 @@
*
* Disassembling to symbolic ASL+ operators
*
- * Disassembly of tests/data/acpi/pc/DSDT.hpbridge, Tue Sep 29 17:51:04 2020
+ * Disassembly of tests/data/acpi/pc/DSDT.hpbrroot, Tue Sep 29 17:50:00 2020
*
* Original Table Header:
* Signature"DSDT"
- * Length 0x139D (5021)
+ * Length 0x0C07 (3079)
* Revision 0x01 32-bit table (V1), no 64-bit math support
- * Checksum 0x05
+ * Checksum 0xAD
* OEM ID "BOCHS "
* OEM Table ID "BXPCDSDT"
* OEM Revision 0x0001 (1)
@@ -247,38 +247,6 @@
}
}
-Scope (_SB.PCI0)
-{
-OperationRegion (PCST, SystemIO, 0xAE00, 0x08)
-Field (PCST, DWordAcc, NoLock, WriteAsZeros)
-{
-PCIU, 32,
-PCID, 32
-}
-
-OperationRegion (SEJ, SystemIO, 0xAE08, 0x04)
-Field (SEJ, DWordAcc, NoLock, WriteAsZeros)
-{
-B0EJ, 32
-}
-
-OperationRegion (BNMR, SystemIO, 0xAE10, 0x04)
-Field (BNMR, DWordAcc, NoLock, WriteAsZeros)
-{
-BNUM, 32
-}
-
-Mutex (BLCK, 0x00)
-Method (PCEJ, 2, NotSerialized)
-{
-Acquire (BLCK, 0x)
-BNUM = Arg0
-B0EJ = (One << Arg1)
-Release (BLCK)
-Return (Zero)
-}
-}
-
Scope (_SB)
{
Scope (PCI0)
@@ -737,12 +705,6 @@
Scope (_GPE)
{
Name (_HID, "ACPI0006" /* GPE Block Device */) // _HID: Hardware ID
-Method (_E01, 0, NotSerialized) // _Exx: Edge-Triggered GPE
-{
-Acquire (\_SB.PCI0.BLCK, 0x)
-\_SB.PCI0.PCNT ()
-Release (\_SB.PCI0.BLCK)
-}
}
Scope (\_SB.PCI0)
@@ -813,22 +775,6 @@
)
})
}
-
-Device (PHPR)
-{
-Name (_HID, "PNP0A06" /* Generic Container Device */) // _HID:
Hardware ID
-Name (_UID, "PCI Hotplug resources") // _UID: Unique ID
-Name (_STA, 0x0B) // _STA: Status
-Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings
-{
-IO (Decode16,
-0xAE00, // Range Minimum
-0xAE00, // Range Maximum
-0x01, // Alignment
-0x14, // Length
-)
-})
-}
}
Scope (\)
@@ -878,7 +824,6 @@
{
Scope (PCI0)
{
-Name (BSEL, Zero)
Device (S00)
{
Name (_ADR, Zero) // _ADR: Address
@@ -907,436 +852,6 @@
{
Name (_ADR, 0x0003) // _ADR: Address
}
-
-Device (S20)
-{
-Name (_SUN, 0x04) // _SUN: Slot User Number
-Name (_ADR, 0x0004) // _ADR: Address
-Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device
-{
-PCEJ (BSEL, _SUN)
-}
-}
-
-Device (S28)
-{
-Name (_SUN, 0x05) // _SUN: Slot User Number
-Name (_ADR, 0x0005) // _ADR: Address
-Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device
-{
-PCEJ (BSEL, _SUN)
-}
-}
-
-Device (S30)
-{
-Name (_SUN, 0x06) // _SUN: Slot User Number
-Name (_ADR, 0x0006) // _ADR: Address
-Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device
-{
-PCEJ (BSEL, _SUN)
-}
-}
-
-Device (S38)
-{
-Name (_SUN, 0x07) // _SUN: Slot User Number
-Name (_ADR, 0x0007) // _ADR: Address
-Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device
-{
-PCEJ (BSEL, _SUN)
-}
-}
-
-Device (S40)
-{
-Name (_SUN, 0x08) // _SUN: Slot User Number
-Name (_ADR, 0x0008) // _ADR: Address
-Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device
-{
-PCEJ (BSEL, _SUN)
-}
-}
-
-Device (S48)
-{
-Name (_SUN, 0x09) // _SUN: Slot User Number
-
Re: [PATCH v3 3/5] hw/arm/virt: Move kvm pmu setup to virt_cpu_post_init
Hi Drew,
On 9/16/20 11:26 AM, Andrew Jones wrote:
> Move the KVM PMU setup part of fdt_add_pmu_nodes() to
> virt_cpu_post_init(), which is a more appropriate location. Now
> fdt_add_pmu_nodes() is also named more appropriately, because it
> no longer does anything but fdt node creation.
>
> No functional change intended.
>
> Reviewed-by: Peter Maydell
> Signed-off-by: Andrew Jones
Reviewed-by: Eric Auger
Eric
> ---
> hw/arm/virt.c | 34 ++
> 1 file changed, 18 insertions(+), 16 deletions(-)
>
> diff --git a/hw/arm/virt.c b/hw/arm/virt.c
> index 2cba21fe3ad9..6797eb397a7a 100644
> --- a/hw/arm/virt.c
> +++ b/hw/arm/virt.c
> @@ -521,21 +521,12 @@ static void fdt_add_gic_node(VirtMachineState *vms)
>
> static void fdt_add_pmu_nodes(const VirtMachineState *vms)
> {
> -CPUState *cpu;
> -ARMCPU *armcpu;
> +ARMCPU *armcpu = ARM_CPU(first_cpu);
> uint32_t irqflags = GIC_FDT_IRQ_FLAGS_LEVEL_HI;
>
> -CPU_FOREACH(cpu) {
> -armcpu = ARM_CPU(cpu);
> -if (!arm_feature(&armcpu->env, ARM_FEATURE_PMU)) {
> -return;
> -}
> -if (kvm_enabled()) {
> -if (kvm_irqchip_in_kernel()) {
> -kvm_arm_pmu_set_irq(cpu, PPI(VIRTUAL_PMU_IRQ));
> -}
> -kvm_arm_pmu_init(cpu);
> -}
> +if (!arm_feature(&armcpu->env, ARM_FEATURE_PMU)) {
> +assert(!object_property_get_bool(OBJECT(armcpu), "pmu", NULL));
> +return;
> }
>
> if (vms->gic_version == VIRT_GIC_VERSION_2) {
> @@ -544,7 +535,6 @@ static void fdt_add_pmu_nodes(const VirtMachineState *vms)
> (1 << vms->smp_cpus) - 1);
> }
>
> -armcpu = ARM_CPU(qemu_get_cpu(0));
> qemu_fdt_add_subnode(vms->fdt, "/pmu");
> if (arm_feature(&armcpu->env, ARM_FEATURE_V8)) {
> const char compat[] = "arm,armv8-pmuv3";
> @@ -1678,11 +1668,23 @@ static void finalize_gic_version(VirtMachineState
> *vms)
> */
> static void virt_cpu_post_init(VirtMachineState *vms)
> {
> -bool aarch64;
> +bool aarch64, pmu;
> +CPUState *cpu;
>
> aarch64 = object_property_get_bool(OBJECT(first_cpu), "aarch64", NULL);
> +pmu = object_property_get_bool(OBJECT(first_cpu), "pmu", NULL);
>
> -if (!kvm_enabled()) {
> +if (kvm_enabled()) {
> +CPU_FOREACH(cpu) {
> +if (pmu) {
> +assert(arm_feature(&ARM_CPU(cpu)->env, ARM_FEATURE_PMU));
> +if (kvm_irqchip_in_kernel()) {
> +kvm_arm_pmu_set_irq(cpu, PPI(VIRTUAL_PMU_IRQ));
> +}
> +kvm_arm_pmu_init(cpu);
> +}
> +}
> +} else {
> if (aarch64 && vms->highmem) {
> int requested_pa_size = 64 - clz64(vms->highest_gpa);
> int pamax = arm_pamax(ARM_CPU(first_cpu));
>
Re: [PATCH v3 4/5] DO NOT MERGE: HACK: Add steal time KVM cap to kvm.h
Hi Drew,
On 9/16/20 11:26 AM, Andrew Jones wrote:
> ---
> linux-headers/linux/kvm.h | 1 +
> 1 file changed, 1 insertion(+)
>
> diff --git a/linux-headers/linux/kvm.h b/linux-headers/linux/kvm.h
> index a28c3667370b..924672cca1f1 100644
> --- a/linux-headers/linux/kvm.h
> +++ b/linux-headers/linux/kvm.h
> @@ -1031,6 +1031,7 @@ struct kvm_ppc_resize_hpt {
> #define KVM_CAP_PPC_SECURE_GUEST 181
> #define KVM_CAP_HALT_POLL 182
> #define KVM_CAP_ASYNC_PF_INT 183
> +#define KVM_CAP_STEAL_TIME 187
>
> #ifdef KVM_CAP_IRQ_ROUTING
>
>
So [PULL v4 01/48] linux headers: sync to 5.9-rc4 missed this update.
Needs a scripts/update-linux-headers.sh run.
Thanks
Eric
Some comments on using qemu-storage-daemon
I understand that QSD is at an early stage of development and I'm sure you have plans to fix these things. Nevertheless here are my comments after trying to add an interop test with libnbd. (1) Documentation! (Or complete lack of it ...) I had to ask Kevin how to construct the command line because several things were not obvious. In particular the --blockdev parameters only make sense if you're already used to constructing blockdev parameters (and these are, separately, not well-documented). And you have to supply the parameters in a particular order on the command line, else it doesn't work. (2) There seems to be no --pid-file option, so there's no way of knowing when the server is ready to accept connections, except to start QSD and then "sleep for a bit". (3) Seems to be no support for either serving requests over stdin/stdout (qemu-nbd also lacks this, but it's common for other NBD servers); or for systemd socket activation (qemu-nbd supports this). (4) Some parameter names changed between 5.1 and upstream. I understand that you're still finalizing the command line, so this isn't a problem in itself, but others who try to use QSD will need to be aware of it. Rich. -- Richard Jones, Virtualization Group, Red Hat http://people.redhat.com/~rjones Read my programming and virtualization blog: http://rwmj.wordpress.com virt-df lists disk usage of guests without needing to install any software inside the virtual machine. Supports Linux and Windows. http://people.redhat.com/~rjones/virt-df/
Re: [PATCH 16/16] tests/acceptance: Test the MIPSsim machine
On Tue, Sep 29, 2020 at 10:38:30AM +0100, Alex Bennée wrote:
>
> Philippe Mathieu-Daudé writes:
>
> > +Alex/Daniel
> >
> > On 9/28/20 10:33 PM, Willian Rampazzo wrote:
> >> On Mon, Sep 28, 2020 at 2:31 PM Philippe Mathieu-Daudé
> >> wrote:
> >>>
> >>> Add a test for the mipssim machine, based on the recommended
> >>> test setup from Thomas Huth:
> >>> https://www.mail-archive.com/qemu-devel@nongnu.org/msg606846.html
> >>>
> >>> The test is quick and can be run as:
> >>>
> >>> $ avocado --show=console run -t machine:mipssim tests/acceptance/
> >>>(1/1)
> >>> tests/acceptance/machine_mips_mipssim.py:MipsSimMachine.test_mipssim_linux_console:
> >>> console: Linux version 3.6.11 (root@711bb8ba16a7) (gcc version 4.8.3
> >>> (Buildroot 2014.11) ) #2 Sun Sep 27 13:39:35 UTC 2020
> >>> console: Setting default memory size 0x0200
> >>> console: bootconsole [early0] enabled
> >>> console: CPU revision is: 00019300 (MIPS 24Kc)
> >>> console: FPU revision is: 00739300
> >>> ...
> >>> console: CPU frequency 12.00 MHz
> >>> console: Calibrating delay loop... 950.27 BogoMIPS (lpj=4751360)
> >>> ...
> >>> console: MIPSNet Ethernet driver. Version: 2007-11-17. (c)2005 MIPS
> >>> Technologies, Inc.
> >>> ...
> >>> console: Welcome to Buildroot
> >>> console: buildroot login: root
> >>> console: # root
> >>> console: -sh: root: not found
> >>> console: # ping -c 3 10.0.2.2
> >>> console: PING 10.0.2.2 (10.0.2.2): 56 data bytes
> >>> console: 64 bytes from 10.0.2.2: seq=0 ttl=255 time=48.231 ms
> >>> console: 64 bytes from 10.0.2.2: seq=1 ttl=255 time=9.407 ms
> >>> console: 64 bytes from 10.0.2.2: seq=2 ttl=255 time=2.298 ms
> >>> console: --- 10.0.2.2 ping statistics ---
> >>> console: 3 packets transmitted, 3 packets received, 0% packet loss
> >>> PASS (7.99 s)
> >>>
> >>> Signed-off-by: Philippe Mathieu-Daudé
> >>> ---
> >>> Cc: Thomas Huth
> >>> ---
> >>> MAINTAINERS | 1 +
> >>> tests/acceptance/machine_mips_mipssim.py | 56
> >>> 2 files changed, 57 insertions(+)
> >>> create mode 100644 tests/acceptance/machine_mips_mipssim.py
> >>>
> >>> diff --git a/MAINTAINERS b/MAINTAINERS
> >>> index 5eed1e692b4..17d8a012b0e 100644
> >>> --- a/MAINTAINERS
> >>> +++ b/MAINTAINERS
> >>> @@ -240,6 +240,7 @@ F: include/hw/misc/mips_*
> >>> F: include/hw/timer/mips_gictimer.h
> >>> F: tests/acceptance/linux_ssh_mips_malta.py
> >>> F: tests/acceptance/machine_mips_malta.py
> >>> +F: tests/acceptance/machine_mips_mipssim.py
> >>> F: tests/tcg/mips/
> >>> K: ^Subject:.*(?i)mips
> >>>
> >>> diff --git a/tests/acceptance/machine_mips_mipssim.py
> >>> b/tests/acceptance/machine_mips_mipssim.py
> >>> new file mode 100644
> >>> index 000..b2749917b08
> >>> --- /dev/null
> >>> +++ b/tests/acceptance/machine_mips_mipssim.py
> >>> @@ -0,0 +1,56 @@
> >>> +# Functional tests for the MIPS simulator (MIPSsim machine)
> >>> +#
> >>> +# Copyright (c) 2020 Philippe Mathieu-Daudé
> >>> +#
> >>> +# This work is licensed under the terms of the GNU GPL, version 2 or
> >>> later.
> >>> +# See the COPYING file in the top-level directory.
> >>> +#
> >>> +# SPDX-License-Identifier: GPL-2.0-or-later
> >>> +
> >>> +import os
> >>> +import logging
> >>> +import time
> >>> +
> >>> +from avocado import skipUnless
> >>> +from avocado_qemu import Test
> >>> +from avocado_qemu import exec_command_and_wait_for_pattern
> >>> +from avocado_qemu import interrupt_interactive_console_until_pattern
> >>> +from avocado_qemu import wait_for_console_pattern
> >>> +
> >>> +class MipsSimMachine(Test):
> >>> +
> >>> +timeout = 30
> >>> +KERNEL_COMMON_COMMAND_LINE = 'printk.time=0 '
> >>> +
> >>> +@skipUnless(os.getenv('AVOCADO_ALLOW_UNTRUSTED_CODE'), 'untrusted
> >>> code')
> >>> +def test_mipssim_linux_console(self):
> >>> +"""
> >>> +Boots the Linux kernel and checks that the console is operational
> >>> +:avocado: tags=arch:mipsel
> >>> +:avocado: tags=machine:mipssim
> >>> +:avocado: tags=device:mipsnet
> >>> +"""
> >>> +kernel_url = ('https://github.com/philmd/qemu-testing-blob/raw/'
> >>> + '32ea5764e1de8fffa0d59366c44822cd06d7c8e0/'
> >>> + 'mips/mipssim/mipsel/vmlinux')
> >>
> >> So, are you willing to maintain some images on your GitHub to avoid
> >> the image changes when they are not found?
> >
> > No, I am not willing to do that.
> >
> > But I see it pointless to have everyone (including CI) to spend 1h
> > building this image, when the sources and build recipe is available,
> > making the built image reproducible.
>
> I agree we don't want to build from scratch each time. However as we
> move from relying on third parties (which outside of the major distros
> has proved very flaky) we are getting to the point of managing our GPL
> liabilities.
I'm wondering what the 1 hour time to build the images is
spent on, and w
Re: [PATCH v4 04/46] qapi: modify docstrings to be sphinx-compatible
John Snow writes: > I did not say "sphinx beautiful", just "sphinx compatible". They will > not throw errors when parsed and interpreted as ReST. "Bang on the keyboard until Sphinx doesn't throw errors anymore" might be good enough for a certain kind of mathematician, but a constructive solution needs a bit more direction. Is there a specification to follow? Other useful resources? > > Signed-off-by: John Snow > --- > scripts/qapi/gen.py| 6 -- > scripts/qapi/parser.py | 9 + > 2 files changed, 9 insertions(+), 6 deletions(-) > > diff --git a/scripts/qapi/gen.py b/scripts/qapi/gen.py > index ca66c82b5b8..fc19b2aeb9b 100644 > --- a/scripts/qapi/gen.py > +++ b/scripts/qapi/gen.py > @@ -154,9 +154,11 @@ def _bottom(self): > > @contextmanager > def ifcontext(ifcond, *args): > -"""A 'with' statement context manager to wrap with start_if()/end_if() > +""" > +A 'with' statement context manager that wraps with `start_if` and > `end_if`. Sadly, the fact that start_if() and end_if() are functions isn't immediately obvious anymore. I've seen :func:`start_if` elsewhere. Is this something we should or want to use? > > -*args: any number of QAPIGenCCode > +:param ifcond: List of conditionals > +:param args: any number of `QAPIGenCCode`. > > Example:: > > diff --git a/scripts/qapi/parser.py b/scripts/qapi/parser.py > index 9d1a3e2eea9..02983979965 100644 > --- a/scripts/qapi/parser.py > +++ b/scripts/qapi/parser.py > @@ -381,10 +381,11 @@ def append(self, line): > > The way that the line is dealt with depends on which part of > the documentation we're parsing right now: > -* The body section: ._append_line is ._append_body_line > -* An argument section: ._append_line is ._append_args_line > -* A features section: ._append_line is ._append_features_line > -* An additional section: ._append_line is ._append_various_line > + > + * The body section: ._append_line is ._append_body_line > + * An argument section: ._append_line is ._append_args_line > + * A features section: ._append_line is ._append_features_line > + * An additional section: ._append_line is ._append_various_line > """ > line = line[1:] > if not line: I understand why you insert a blank line (reST wants blank lines around lists), I don't understand why you indent. Can you explain?
Re: Some comments on using qemu-storage-daemon
On Wed, Sep 30, 2020 at 09:40:59AM +0100, Richard W.M. Jones wrote: > I understand that QSD is at an early stage of development and I'm sure > you have plans to fix these things. Nevertheless here are my comments > after trying to add an interop test with libnbd. > > (1) Documentation! (Or complete lack of it ...) I had to ask Kevin > how to construct the command line because several things were not > obvious. In particular the --blockdev parameters only make sense if > you're already used to constructing blockdev parameters (and these > are, separately, not well-documented). And you have to supply the > parameters in a particular order on the command line, else it doesn't > work. > > (2) There seems to be no --pid-file option, so there's no way of > knowing when the server is ready to accept connections, except to > start QSD and then "sleep for a bit". It supports QMP via the normal chardev framework, so you can pre-create a UNIX listener socket and pass in the pre-opened FD. The parent just sends the QMP handshake, and waits until it gets EOF (exited during startup) or gets the QMP response (successfully running). > > (3) Seems to be no support for either serving requests over > stdin/stdout (qemu-nbd also lacks this, but it's common for other NBD > servers); or for systemd socket activation (qemu-nbd supports this). > > (4) Some parameter names changed between 5.1 and upstream. I > understand that you're still finalizing the command line, so this > isn't a problem in itself, but others who try to use QSD will need to > be aware of it. Regards, Daniel -- |: https://berrange.com -o-https://www.flickr.com/photos/dberrange :| |: https://libvirt.org -o-https://fstop138.berrange.com :| |: https://entangle-photo.org-o-https://www.instagram.com/dberrange :|
Re: [PATCH v2 3/4] block: move block exports to libblockdev
On Tue, Sep 29, 2020 at 12:36:10PM -0500, Eric Blake wrote: > On 9/29/20 7:55 AM, Stefan Hajnoczi wrote: > > Block exports are used by softmmu, qemu-storage-daemon, and qemu-nbd. > > They are not used by other programs and are not otherwise needed in > > libblock. > > > > Undo the recent move of blockdev-nbd.c from blockdev_ss into block_ss. > > Since bdrv_close_all() (libblock) calls blk_exp_close_all() > > (libblockdev) a stub function is required.. > > > > Make qemu-ndb.c use signal handling utility functions instead of > > duplicating the code. This helps because os-posix.c is in libblockdev > > and it depends on a qemu_system_killed() symbol that qemu-nbd.c lacks. > > Once we use the signal handling utility functions we also end up > > providing the necessary symbol. > > Hmm. I just stumbled on a long-standing bug in qemu-nbd - it installs a > SIGTERM handler, but not a SIGINT or SIGHUP handler. This matters in > the following sequence: > > qemu-nbd -f qcow2 -B bitmap image # Ctrl-C > qemu-nbd -f qcow2 -B bitmap image > > because the first instance dies with SIGINT but there is no handler > installed, qemu-nbd does not release the bitmap from being marked > in-use, and the second instance then fails with: > > qemu-nbd: Bitmap 'b0' is inconsistent and cannot be used > > And to my surprise, while I was trying to find the root cause to fixing > the bug I just found, I noticed that your patch happens to fix that... > > > +++ b/qemu-nbd.c > > > @@ -581,20 +586,12 @@ int main(int argc, char **argv) > > const char *pid_file_name = NULL; > > BlockExportOptions *export_opts; > > > > +os_setup_early_signal_handling(); > > + > > #if HAVE_NBD_DEVICE > > -/* The client thread uses SIGTERM to interrupt the server. A signal > > - * handler ensures that "qemu-nbd -v -c" exits with a nice status code. > > - */ > > -struct sigaction sa_sigterm; > > -memset(&sa_sigterm, 0, sizeof(sa_sigterm)); > > -sa_sigterm.sa_handler = termsig_handler; > > -sigaction(SIGTERM, &sa_sigterm, NULL); > > +os_setup_signal_handling(); > > ...by installing a SIGINT handler. > > Is HAVE_NBD_DEVICE really the best gate for this code, or is it really > whether we are compiling for mingw? At any rate, you may want to add a > link to https://bugzilla.redhat.com/show_bug.cgi?id=1883608 in the > commit message, and/or separate the bug fix out into a separate commit. Thanks for letting me know about the bug report. The link can be added to the commit description when merging (or if I resend). Stefan signature.asc Description: PGP signature
Re: [PATCH v3 5/5] hw/arm/virt: Implement kvm-steal-time
Hi Drew,
On 9/16/20 11:26 AM, Andrew Jones wrote:
> We add the kvm-steal-time CPU property and implement it for machvirt.
> A tiny bit of refactoring was also done to allow pmu and pvtime to
> use the same vcpu device helper functions.
This needs a rebase. Besides this still looks good to me
Reviewed-by: Eric Auger
Thanks
Eric
>
> Signed-off-by: Andrew Jones
> ---
> docs/system/arm/cpu-features.rst | 11 ++
> hw/arm/virt.c| 43 +++--
> include/hw/arm/virt.h| 5 +++
> target/arm/cpu.c | 8
> target/arm/cpu.h | 4 ++
> target/arm/kvm.c | 16
> target/arm/kvm64.c | 64 +---
> target/arm/kvm_arm.h | 43 +
> target/arm/monitor.c | 2 +-
> tests/qtest/arm-cpu-features.c | 25 +++--
> 10 files changed, 208 insertions(+), 13 deletions(-)
>
> diff --git a/docs/system/arm/cpu-features.rst
> b/docs/system/arm/cpu-features.rst
> index 2d5c06cd016b..35196a6b759d 100644
> --- a/docs/system/arm/cpu-features.rst
> +++ b/docs/system/arm/cpu-features.rst
> @@ -200,6 +200,17 @@ the list of KVM VCPU features and their descriptions.
> adjustment, also restoring the legacy (pre-5.0)
> behavior.
>
> + kvm-steal-time Since v5.2, kvm-steal-time is enabled by
> + default when KVM is enabled, the feature is
> + supported, and the guest is 64-bit.
> +
> + When kvm-steal-time is enabled a 64-bit guest
> + can account for time its CPUs were not running
> + due to the host not scheduling the corresponding
> + VCPU threads. The accounting statistics may
> + influence the guest scheduler behavior and/or be
> + exposed to the guest userspace.
> +
> SVE CPU Properties
> ==
>
> diff --git a/hw/arm/virt.c b/hw/arm/virt.c
> index 6797eb397a7a..12efc2f095cb 100644
> --- a/hw/arm/virt.c
> +++ b/hw/arm/virt.c
> @@ -151,6 +151,7 @@ static const MemMapEntry base_memmap[] = {
> [VIRT_PCDIMM_ACPI] ={ 0x0907, MEMORY_HOTPLUG_IO_LEN },
> [VIRT_ACPI_GED] = { 0x0908, ACPI_GED_EVT_SEL_LEN },
> [VIRT_NVDIMM_ACPI] ={ 0x0909, NVDIMM_ACPI_IO_LEN},
> +[VIRT_PVTIME] = { 0x090a, 0x0001 },
> [VIRT_MMIO] = { 0x0a00, 0x0200 },
> /* ...repeating for a total of NUM_VIRTIO_TRANSPORTS, each of that size
> */
> [VIRT_PLATFORM_BUS] = { 0x0c00, 0x0200 },
> @@ -1666,15 +1667,39 @@ static void finalize_gic_version(VirtMachineState
> *vms)
> * virt_cpu_post_init() must be called after the CPUs have
> * been realized and the GIC has been created.
> */
> -static void virt_cpu_post_init(VirtMachineState *vms)
> +static void virt_cpu_post_init(VirtMachineState *vms, int max_cpus,
> + MemoryRegion *sysmem)
> {
> -bool aarch64, pmu;
> +bool aarch64, pmu, steal_time;
> CPUState *cpu;
>
> aarch64 = object_property_get_bool(OBJECT(first_cpu), "aarch64", NULL);
> pmu = object_property_get_bool(OBJECT(first_cpu), "pmu", NULL);
> +steal_time = object_property_get_bool(OBJECT(first_cpu),
> + "kvm-steal-time", NULL);
>
> if (kvm_enabled()) {
> +hwaddr pvtime_reg_base = vms->memmap[VIRT_PVTIME].base;
> +hwaddr pvtime_reg_size = vms->memmap[VIRT_PVTIME].size;
> +
> +if (steal_time) {
> +MemoryRegion *pvtime = g_new(MemoryRegion, 1);
> +hwaddr pvtime_size = max_cpus * PVTIME_SIZE_PER_CPU;
> +
> +/* The memory region size must be a multiple of host page size.
> */
> +pvtime_size = REAL_HOST_PAGE_ALIGN(pvtime_size);
> +
> +if (pvtime_size > pvtime_reg_size) {
> +error_report("pvtime requires a %ld byte memory region for "
> + "%d CPUs, but only %ld has been reserved",
> + pvtime_size, max_cpus, pvtime_reg_size);
> +exit(1);
> +}
> +
> +memory_region_init_ram(pvtime, NULL, "pvtime", pvtime_size,
> NULL);
> +memory_region_add_subregion(sysmem, pvtime_reg_base, pvtime);
> +}
> +
> CPU_FOREACH(cpu) {
> if (pmu) {
> assert(arm_feature(&ARM_CPU(cpu)->env, ARM_FEATURE_PMU));
> @@ -1683,6 +1708,10 @@ static void virt_cpu_post_init(VirtMachineState *vms)
> }
> kvm_arm_pmu_init(cpu);
> }
> +if (steal_time) {
> +kvm_arm_pvtime_init(cpu, pvtime_reg_base +
> + cpu->cpu_index *
> PVTIME_SI
Re: Some comments on using qemu-storage-daemon
On Wed, Sep 30, 2020 at 09:49:00AM +0100, Daniel P. Berrangé wrote: > On Wed, Sep 30, 2020 at 09:40:59AM +0100, Richard W.M. Jones wrote: > > I understand that QSD is at an early stage of development and I'm sure > > you have plans to fix these things. Nevertheless here are my comments > > after trying to add an interop test with libnbd. > > > > (1) Documentation! (Or complete lack of it ...) I had to ask Kevin > > how to construct the command line because several things were not > > obvious. In particular the --blockdev parameters only make sense if > > you're already used to constructing blockdev parameters (and these > > are, separately, not well-documented). And you have to supply the > > parameters in a particular order on the command line, else it doesn't > > work. > > > > (2) There seems to be no --pid-file option, so there's no way of > > knowing when the server is ready to accept connections, except to > > start QSD and then "sleep for a bit". > > It supports QMP via the normal chardev framework, so you can pre-create > a UNIX listener socket and pass in the pre-opened FD. The parent just > sends the QMP handshake, and waits until it gets EOF (exited during > startup) or gets the QMP response (successfully running). This is all fine when run from libvirt (and I do understand that QSD is all about that, not necessarily a standalone general purpose server), but also that's a massive hassle for anyone else trying to use QSD. I'm not confident I could correctly formulate the set of QMP commands that would be needed to make this work, even with the documentation and full source code. Also this moves the problem to "when is the chardev socket ready", especially when not using chardev over stdio. Rich. -- Richard Jones, Virtualization Group, Red Hat http://people.redhat.com/~rjones Read my programming and virtualization blog: http://rwmj.wordpress.com virt-top is 'top' for virtual machines. Tiny program with many powerful monitoring features, net stats, disk stats, logging, etc. http://people.redhat.com/~rjones/virt-top
Re: [PATCH] PoC: Rust binding for QAPI (qemu-ga only, for now)
Hi On Tue, Sep 29, 2020 at 10:23 PM Paolo Bonzini wrote: > On 29/09/20 19:55, Marc-André Lureau wrote: > > My understanding of what you propose is: > > - ForeignConvert::with_foreign > > - FromForeign::from_foreign (with implied into_native) > > And: > > - ForeignConvert::as_foreign (with the BorrowedPointer/stash-like) > > - ToForeign::to_foreign + ForeignConvert::as_foreign_mut (which seems > > wrongly designed in your proposal and unnecessary for now) > > Might well be, but how is it wrong? (I'd like to improve). > Why BorrowedMutPointer provides both *const P and *mut P ? The *const P conversion seems overlapping with BorrowedPointer. Anyway, the &mut T -> *mut P conversion seems fairly rare to me and error-prone. You usually give up ownership if you let the foreign function tweak the P. In any case, we don't need such conversion for QAPI, for now. > > I don't have your head, so I find it hard to remember & work with. It> > uses all possible prefixes: with_, from_, as_, as_mut, to_, and into_. > > That just blows my mind, sorry :) > > Ahah I don't have your head either! The idea anyway is to reuse > prefixes that are common in Rust code: > > * with_: a constructor that uses something to build a type (think > Vec::with_capacity) and therefore takes ownership > ForeignConvert::with_foreign (const *P -> T) doesn't take ownership. The Rust reference for this kind of conversion is CStr::from_ptr. > * as_: a cheap conversion to something, it's cheap because it reuses the > lifetime (and therefore takes no ownership). Think Option::as_ref. > as_ shouldn't create any object, and is thus unsuitable for a general rs<->sys conversion function (any). * from_/to_: a copying and possibly expensive conversion (that you have > to write the code for). Because it's copying, it doesn't consume the > argument (for from_) or self (for to_). > > and that's what glib-rs uses (and CStr). > * into_: a conversion that consumes the receiver > > That's not used by glib afaik, but we should be able to introduce it for "mut *P -> T", it's not incompatible with FromPtrFull::from_full. In general, I like the fact that the conversion traits are associated to T, and not to P (which can remain a bare pointer, without much associated methods). It may well be over the top. > > > Then, I don't understand why ForeignConvert should hold both the "const > > *P -> T" and "&T -> const *P" conversions. Except the common types, > > what's the relation between the two? > > Maybe I'm wrong, but why would you need just one? > No I mean they could be on different traits. One could be implemented without the other. Or else I don't understand why the other conversion functions would not be in that trait too. > > Finally, I thought you introduced some differences with the stash > > design, but in fact I can see that ForeignConvert::Storage works just > > the way as ToPtr::Storage. So composition should be similar. Only your > > example code is more repetitive as it doesn't indirectly refer to the > > trait Storage the same way as glib-rs does (via ::Storage). > > Yes, that's the main difference. I removed Storage because I didn't > want to force any trait on BorrowedPointer's second type argument. It > seemed like a generic concept to me. > To the cost of some duplication. I like the coupling between the traits better. If you need a similar tuple/struct elsewhere, it's easy to make your own. The Storage type can quickly become quite complicated with QAPI, I would rather avoid having to repeat it, it would create hideous compiler errors too. > The other difference is that Stash is a tuple while BorrowedPointer is a > struct and has methods to access it. Stash seems very ugly to use. > Yes I agree. Not sure why they made it a bare tuple, laziness perhaps :). -- Marc-André Lureau
Re: [PATCH v2 2/2] util/vfio-helpers: Rework the IOVA allocator to avoid IOVA reserved regions
On Tue, Sep 29, 2020 at 09:44:48PM +0200, Auger Eric wrote:
> Hi Stefan,
>
> On 9/29/20 5:59 PM, Stefan Hajnoczi wrote:
> > On Tue, Sep 29, 2020 at 10:55:50AM +0200, Eric Auger wrote:
> >> diff --git a/util/vfio-helpers.c b/util/vfio-helpers.c
> >> index ba0ee6e21c..71145970f3 100644
> >> --- a/util/vfio-helpers.c
> >> +++ b/util/vfio-helpers.c
> >> @@ -667,6 +667,50 @@ static bool qemu_vfio_verify_mappings(QEMUVFIOState
> >> *s)
> >> return true;
> >> }
> >>
> >> +static int
> >> +qemu_vfio_find_fixed_iova(QEMUVFIOState *s, size_t size, uint64_t *iova)
> >> +{
> >> +int i;
> >> +
> >> +for (i = 0; i < s->nb_iova_ranges; i++) {
> >> +if (s->usable_iova_ranges[i].end < s->low_water_mark) {
> >> +continue;
> >> +}
> >> +s->low_water_mark =
> >> +MAX(s->low_water_mark, s->usable_iova_ranges[i].start);
> >> +
> >> +if (s->usable_iova_ranges[i].end - s->low_water_mark + 1 >= size
> >> ||
> >> +s->usable_iova_ranges[i].end - s->low_water_mark + 1 == 0) {
> >
> > I don't understand the == 0 case. It seems like we are allocating an
> > IOVA beyond usable_iova_ranges[i].end?>
> It is meant to handle the case were low_water_mark = 0 and
> s->usable_iova_ranges[0].end = ULLONG_MAX (I know it cannot exist at the
> moment but may happen in the future) where we get an overflow. Given the
> if (s->usable_iova_ranges[i].end < s->low_water_mark) {
> continue;
> }
> I think this prevents us from allocating beyond
> usable_iova_ranges[i].end or do I miss something?
Yes, you are right. Here are the constraints:
e >= l
j = max(l, s)
e - j + 1 < s
e - j + 1 == 0
Assume l >= s so we can replace j with l:
e >= l
e - l + 1 < s
e - l + 1 == 0
The case I'm worried about is when the iova range cannot fit s bytes.
The last condition is only true when e = l - 1, but this violates the
first condition e >= l.
So the problem scenario cannot occur.
Reviewed-by: Stefan Hajnoczi
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Re: [PATCH v2 0/2] NVMe passthrough: Take into account host IOVA reserved regions
On Tue, Sep 29, 2020 at 10:55:48AM +0200, Eric Auger wrote: > The current IOVA allocator allocates within the [0x1, 1ULL << 39] > window, without paying attention to the host IOVA reserved regions. > This prevents NVMe passthtrough from working on ARM as the fixed > IOVAs rapidly grow up to the MSI reserved region [0x800, 0x810] > causing some VFIO MAP DMA failures. This series collects the usable > IOVA regions using VFIO GET_INFO (this requires the host to support > VFIO_IOMMU_TYPE1_INFO_CAP_IOVA_RANGE) and rework the fixed and > temporary IOVA allocators to avoid those latter. > > For the time being we do not change the arbitrary min/max IOVAs. > In theory they could be dynamically determined but the kernel > currently fails to expose some HW limitations described in the ACPI > tables (such as PCI root complex Device Memory Address Size Limit). > See kernel thread related to "[RFC 0/3] iommu: Reserved regions for > IOVAs beyond dma_mask and iommu aperture" for more details: > https://lkml.org/lkml/2020/9/28/1102 > > Best Regards > > Eric > > This series can be found at: > https://github.com/eauger/qemu/tree/nvme_resv_v2 > > This was tested on ARM only. > > History: > v1 -> v2: > - remove "util/vfio-helpers: Dynamically compute the min/max IOVA" to > relax the kernel dependency > - Fix cabapbility enumeration loop > - set s->usable_iova_ranges=NULL to avoid double free > - handle possible u64 wrap > > Eric Auger (2): > util/vfio-helpers: Collect IOVA reserved regions > util/vfio-helpers: Rework the IOVA allocator to avoid IOVA reserved > regions > > util/vfio-helpers.c | 129 +--- > 1 file changed, 123 insertions(+), 6 deletions(-) > > -- > 2.21.3 > Thanks, applied to my block tree: https://github.com/stefanha/qemu/commits/block Stefan signature.asc Description: PGP signature
Re: [PATCH v7 06/13] qmp: Call monitor_set_cur() only in qmp_dispatch()
Kevin Wolf writes:
> Am 28.09.2020 um 13:42 hat Markus Armbruster geschrieben:
>> Kevin Wolf writes:
>>
>> > Am 14.09.2020 um 17:10 hat Markus Armbruster geschrieben:
>> >> Kevin Wolf writes:
>> >>
>> >> > The correct way to set the current monitor for a coroutine handler will
>> >> > be different than for a blocking handler, so monitor_set_cur() needs to
>> >> > be called in qmp_dispatch().
>> >> >
>> >> > Signed-off-by: Kevin Wolf
>> >> > ---
>> >> > include/qapi/qmp/dispatch.h | 3 ++-
>> >> > monitor/qmp.c | 8 +---
>> >> > qapi/qmp-dispatch.c | 8 +++-
>> >> > qga/main.c | 2 +-
>> >> > stubs/monitor-core.c| 5 +
>> >> > tests/test-qmp-cmds.c | 6 +++---
>> >> > 6 files changed, 19 insertions(+), 13 deletions(-)
>> >> >
>> >> > diff --git a/include/qapi/qmp/dispatch.h b/include/qapi/qmp/dispatch.h
>> >> > index 5a9cf82472..0c2f467028 100644
>> >> > --- a/include/qapi/qmp/dispatch.h
>> >> > +++ b/include/qapi/qmp/dispatch.h
>> >> > @@ -14,6 +14,7 @@
>> >> > #ifndef QAPI_QMP_DISPATCH_H
>> >> > #define QAPI_QMP_DISPATCH_H
>> >> >
>> >> > +#include "monitor/monitor.h"
>> >> > #include "qemu/queue.h"
>> >> >
>> >> > typedef void (QmpCommandFunc)(QDict *, QObject **, Error **);
>> >> > @@ -49,7 +50,7 @@ const char *qmp_command_name(const QmpCommand *cmd);
>> >> > bool qmp_has_success_response(const QmpCommand *cmd);
>> >> > QDict *qmp_error_response(Error *err);
>> >> > QDict *qmp_dispatch(const QmpCommandList *cmds, QObject *request,
>> >> > -bool allow_oob);
>> >> > +bool allow_oob, Monitor *cur_mon);
>> >> > bool qmp_is_oob(const QDict *dict);
>> >> >
>> >> > typedef void (*qmp_cmd_callback_fn)(const QmpCommand *cmd, void
>> >> > *opaque);
>> >> > diff --git a/monitor/qmp.c b/monitor/qmp.c
>> >> > index 8469970c69..922fdb5541 100644
>> >> > --- a/monitor/qmp.c
>> >> > +++ b/monitor/qmp.c
>> >> > @@ -135,16 +135,10 @@ static void monitor_qmp_respond(MonitorQMP *mon,
>> >> > QDict *rsp)
>> >> >
>> >> > static void monitor_qmp_dispatch(MonitorQMP *mon, QObject *req)
>> >> > {
>> >> > -Monitor *old_mon;
>> >> > QDict *rsp;
>> >> > QDict *error;
>> >> >
>> >> > -old_mon = monitor_set_cur(&mon->common);
>> >> > -assert(old_mon == NULL);
>> >> > -
>> >> > -rsp = qmp_dispatch(mon->commands, req, qmp_oob_enabled(mon));
>> >> > -
>> >> > -monitor_set_cur(NULL);
>> >> > +rsp = qmp_dispatch(mon->commands, req, qmp_oob_enabled(mon),
>> >> > &mon->common);
>> >>
>> >> Long line. Happy to wrap it in my tree. A few more in PATCH 08-11.
>> >
>> > It's 79 characters. Should be fine even with your local deviation from
>> > the coding style to require less than that for comments?
>>
>> Let me rephrase my remark.
>>
>> For me,
>>
>> rsp = qmp_dispatch(mon->commands, req, qmp_oob_enabled(mon),
>>&mon->common);
>>
>> is significantly easier to read than
>>
>> rsp = qmp_dispatch(mon->commands, req, qmp_oob_enabled(mon),
>> &mon->common);
>
> I guess this is highly subjective. I find wrapped lines harder to read.
> For answering subjective questions like this, we generally use the
> coding style document.
>
> Anyway, I guess following an idiosyncratic coding style that is
> different from every other subsystem in QEMU is possible (if
> inconvenient) if I know what it is.
The applicable coding style document is PEP 8.
> My problem is more that I don't know what the exact rules are. Can they
> only be figured out experimentally by submitting patches and seeing
> whether you like them or not?
PEP 8:
A style guide is about consistency. Consistency with this style
guide is important. Consistency within a project is more important.
Consistency within one module or function is the most important.
In other words, you should make a reasonable effort to blend in.
>> Would you mind me wrapping this line in my tree?
>
> I have no say in this subsystem and I take it that you want all code to
> look as if you had written it yourself, so do as you wish.
I'm refusing the bait.
> But I understand that I'll have to respin anyway, so if you could
> explain what you're after, I might be able to apply the rules for the
> next version of the series.
First, PEP 8 again:
Limit all lines to a maximum of 79 characters.
For flowing long blocks of text with fewer structural restrictions
(docstrings or comments), the line length should be limited to 72
characters.
Second, an argument we two had on this list, during review of a prior
version of this patch series, talking about C:
Legibility. Humans tend to have trouble following long lines with
their eyes (I sure do). Typographic manuals suggest to limit
columns to roughly 60 characters for exactly that reason[*].
Code is special. It's typically indented, and long identifiers push
it further to the right, function arguments in particu
Re: [PATCH v10 13/13] tests/acpi: add DSDT.hpbrroot DSDT table blob to test global i440fx hotplug
On Wed, Sep 30, 2020 at 1:37 PM Ani Sinha wrote: > On Wed, Sep 30, 2020 at 1:34 PM Michael S. Tsirkin wrote: > > > > > > On Wed, Sep 30, 2020 at 01:17:53PM +0530, Ani Sinha wrote: > > > > > > > > > > > > On Wed, Sep 30, 2020 at 1:14 PM Michael S. Tsirkin > wrote: > > > > > > > > On Wed, Sep 30, 2020 at 01:09:09PM +0530, Ani Sinha wrote: > > > > > > > > > > > > > > > > > > > > > > > > > > > On Wed, Sep 30, 2020 at 1:06 PM Michael S. Tsirkin < > m...@redhat.com> > > > > wrote: > > > > > > > > > > > > > > > > > > On Tue, Sep 29, 2020 at 06:03:00PM +0530, Ani Sinha wrote: > > > > > > > > > > > > > > > > > > > On Tue, Sep 29, 2020 at 5:05 PM Michael S. Tsirkin < > m...@redhat.com> > > > > > > > > > wrote: > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > On Tue, Sep 29, 2020 at 04:58:03PM +0530, Ani Sinha > wrote: > > > > > > > > > > > > > > > > > > > > > On Tue, Sep 29, 2020 at 4:45 PM Michael S. Tsirkin < > > > > m...@redhat.com> > > > > > > > > > wrote: > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > On Tue, Sep 29, 2020 at 04:35:50PM +0530, Ani Sinha > wrote: > > > > > > > > > > > > > > > > > > > > > > > On Tue, Sep 29, 2020 at 4:25 PM Michael S. Tsirkin > < > > > > > > > > > m...@redhat.com> wrote: > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > On Tue, Sep 29, 2020 at 04:11:45PM +0530, Ani > Sinha > > > > wrote: > > > > > > > > > > > > > > > > > > > > > > > > > On Tue, Sep 29, 2020 at 4:07 PM Michael S. > Tsirkin < > > > > > > > > > m...@redhat.com> wrote: > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > On Tue, Sep 29, 2020 at 04:02:07PM +0530, > Ani Sinha > > > > wrote: > > > > > > > > > > > > > > > > > > > > > > > > > > > On Tue, Sep 29, 2020 at 4:00 PM Ani Sinha < > > > > > > > > > a...@anisinha.ca> wrote: > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > In your pull request the following patch > is > > > > completely > > > > > > > > > screwed up: > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > commit > cda2006eded0ed91974e1d9e7f9f288e65812a3e > > > > > > > > > > > > > > > > > > > > > > > > > > > > Author: Ani Sinha > > > > > > > > > > > > > > > > > > > > > > > > > > > > Date: Tue Sep 29 03:22:52 2020 -0400 > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > tests/acpi: update golden master > DSDT binary > > > > table > > > > > > > > > blobs for q35 > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > This is not my patch. It has all sorts > of changes > > > > which > > > > > > > > > does not > > > > > > > > > > > > > > > > > > > > > > > > > > > > belong there. Can you please check? > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > See https://patchew.org/QEMU/ > > > > > > > > > 20200929071948.281157-1-...@redhat.com/ > > > > > > > > > 20200929071948.281157-46-...@redhat.com/ > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > I had to regenerate the binary, yes. That's > par for > > > > the > > > > > > > > > course. > > > > > > > > > > > > > > > > > > > > > > > > > > But it looks like I added disasssembled > files. Will > > > > fix up > > > > > > > > > and drop, > > > > > > > > > > > > > > > > > > > > > > > > > > thanks for noticing this. > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > OK I pushed out a fixed variant. Pls take a look. > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > OK I am not used to this workflow. How am I > supposed to get > > > > it? > > > > > > > > > Which tag? > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > New for_upstream tag - I just sent in a pull request. > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > Can you please point me to your
Re: [PATCH v2 11/13] block/export: convert vhost-user-blk server to block export API
On Wed, Sep 30, 2020 at 07:28:58AM +0200, Markus Armbruster wrote:
> Stefan Hajnoczi writes:
>
> > Use the new QAPI block exports API instead of defining our own QOM
> > objects.
> >
> > This is a large change because the lifecycle of VuBlockDev needs to
> > follow BlockExportDriver. QOM properties are replaced by QAPI options
> > objects.
> >
> > VuBlockDev is renamed VuBlkExport and contains a BlockExport field.
> > Several fields can be dropped since BlockExport already has equivalents.
> >
> > The file names and meson build integration will be adjusted in a future
> > patch. libvhost-user should probably be built as a static library that
> > is linked into QEMU instead of as a .c file that results in duplicate
> > compilation.
> >
> > The new command-line syntax is:
> >
> > $ qemu-storage-daemon \
> > --blockdev file,node-name=drive0,filename=test.img \
> > --export
> > vhost-user-blk,node-name=drive0,id=export0,unix-socket=/tmp/vhost-user-blk.sock
> >
> > Note that unix-socket is optional because we may wish to accept chardevs
> > too in the future.
> >
> > Signed-off-by: Stefan Hajnoczi
> > ---
> > v2:
> > * Replace str unix-socket with SocketAddress addr to match NBD and
> >support file descriptor passing
> > * Make addr mandatory [Markus]
> > * Update vhost-user-blk-test.c to use --export syntax
> > ---
> > qapi/block-export.json | 21 +-
> > block/export/vhost-user-blk-server.h | 23 +-
> > block/export/export.c| 8 +-
> > block/export/vhost-user-blk-server.c | 452 +++
> > tests/qtest/vhost-user-blk-test.c| 2 +-
> > util/vhost-user-server.c | 10 +-
> > block/export/meson.build | 1 +
> > block/meson.build| 1 -
> > 8 files changed, 158 insertions(+), 360 deletions(-)
> >
> > diff --git a/qapi/block-export.json b/qapi/block-export.json
> > index ace0d66e17..2e44625bb1 100644
> > --- a/qapi/block-export.json
> > +++ b/qapi/block-export.json
> > @@ -84,6 +84,21 @@
> >'data': { '*name': 'str', '*description': 'str',
> > '*bitmap': 'str' } }
> >
> > +##
> > +# @BlockExportOptionsVhostUserBlk:
> > +#
> > +# A vhost-user-blk block export.
> > +#
> > +# @addr: The vhost-user socket on which to listen. Both 'unix' and 'fd'
> > +#SocketAddress types are supported. Passed fds must be UNIX domain
> > +#sockets.
>
> "addr.type must be 'unix' or 'fd'" is not visible in introspection.
> Awkward. Practical problem only if other addresses ever become
> available here. Is that possible?
addr.type=fd itself has the same problem, because it is a file
descriptor without type information. Therefore the QMP client cannot
introspect which types of file descriptors can be passed.
Two ideas:
1. Introduce per-address family fd types (SocketAddrFdTcpInet,
SocketAddrFdTcpInet6, SocketAddrFdUnix, etc) to express specific
address families in the QAPI schema.
Then use per-command unions to express the address families supported
by specific commands. For example,
BlockExportOptionsVhostUserBlkSocketAddr would only allow
SocketAddrUnix and SocketAddrFdUnix. That way new address families
can be supported in the future and introspection reports.
2. Use a side-channel (query-features, I think we discussed something
like this a while back) to report features that cannot be
introspected.
I think the added complexity for achieving full introspection is not
worth it. It becomes harder to define new QAPI commands, increases the
chance of errors, and is more tedious to program for clients/servers.
Accepting any SocketAddr seems reasonable to me since vhost-user
requires an address family that has file descriptor passing. Very few
address families support this feature and we don't expect to add new
ones often.
Stefan
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Description: PGP signature
[RFC PATCH v2 1/8] block-backend: introduce I/O rehandle info
The I/O hang feature is realized based on a rehandle mechanism.
Each block backend will have a list to store hanging block AIOs,
and a timer to regularly resend these aios. In order to issue
the AIOs again, each block AIOs also need to store its coroutine entry.
Signed-off-by: Jiahui Cen
Signed-off-by: Ying Fang
---
block/block-backend.c | 19 +++
1 file changed, 19 insertions(+)
diff --git a/block/block-backend.c b/block/block-backend.c
index ce78d30794..b8367d82cc 100644
--- a/block/block-backend.c
+++ b/block/block-backend.c
@@ -35,6 +35,18 @@
static AioContext *blk_aiocb_get_aio_context(BlockAIOCB *acb);
+/* block backend rehandle timer interval 5s */
+#define BLOCK_BACKEND_REHANDLE_TIMER_INTERVAL 5000
+
+typedef struct BlockBackendRehandleInfo {
+bool enable;
+QEMUTimer *ts;
+unsigned timer_interval_ms;
+
+unsigned int in_flight;
+QTAILQ_HEAD(, BlkAioEmAIOCB) re_aios;
+} BlockBackendRehandleInfo;
+
typedef struct BlockBackendAioNotifier {
void (*attached_aio_context)(AioContext *new_context, void *opaque);
void (*detach_aio_context)(void *opaque);
@@ -95,6 +107,8 @@ struct BlockBackend {
* Accessed with atomic ops.
*/
unsigned int in_flight;
+
+BlockBackendRehandleInfo reinfo;
};
typedef struct BlockBackendAIOCB {
@@ -350,6 +364,7 @@ BlockBackend *blk_new(AioContext *ctx, uint64_t perm,
uint64_t shared_perm)
qemu_co_queue_init(&blk->queued_requests);
notifier_list_init(&blk->remove_bs_notifiers);
notifier_list_init(&blk->insert_bs_notifiers);
+
QLIST_INIT(&blk->aio_notifiers);
QTAILQ_INSERT_TAIL(&block_backends, blk, link);
@@ -1392,6 +1407,10 @@ typedef struct BlkAioEmAIOCB {
BlkRwCo rwco;
int bytes;
bool has_returned;
+
+/* for rehandle */
+CoroutineEntry *co_entry;
+QTAILQ_ENTRY(BlkAioEmAIOCB) list;
} BlkAioEmAIOCB;
static AioContext *blk_aio_em_aiocb_get_aio_context(BlockAIOCB *acb_)
--
2.28.0
[RFC PATCH v2 0/8] block-backend: Introduce I/O hang
A VM in the cloud environment may use a virutal disk as the backend storage, and there are usually filesystems on the virtual block device. When backend storage is temporarily down, any I/O issued to the virtual block device will cause an error. For example, an error occurred in ext4 filesystem would make the filesystem readonly. However a cloud backend storage can be soon recovered. For example, an IP-SAN may be down due to network failure and will be online soon after network is recovered. The error in the filesystem may not be recovered unless a device reattach or system restart. So an I/O rehandle is in need to implement a self-healing mechanism. This patch series propose a feature called I/O hang. It can rehandle AIOs with EIO error without sending error back to guest. From guest's perspective of view it is just like an IO is hanging and not returned. Guest can get back running smoothly when I/O is recovred with this feature enabled. v1->v2: * Rebase to fix compile problems. * Fix incorrect remove of rehandle list. * Provide rehandle pause interface. Jiahui Cen (8): block-backend: introduce I/O rehandle info block-backend: rehandle block aios when EIO block-backend: add I/O hang timeout block-backend: add I/O rehandle pause/unpause block-backend: enable I/O hang when timeout is set virtio-blk: pause I/O hang when resetting qemu-option: add I/O hang timeout option qapi: add I/O hang and I/O hang timeout qapi event block/block-backend.c | 300 + blockdev.c | 11 ++ hw/block/virtio-blk.c | 8 + include/sysemu/block-backend.h | 5 + qapi/block-core.json | 26 +++ 5 files changed, 350 insertions(+) -- 2.28.0
[RFC PATCH v2 6/8] virtio-blk: pause I/O hang when resetting
When resetting virtio-blk, we have to drain all AIOs but do not care about the
results. So it is necessary to disable I/O hang before resetting virtio-blk,
and enable it after resetting.
Signed-off-by: Jiahui Cen
Signed-off-by: Ying Fang
---
hw/block/virtio-blk.c | 8
1 file changed, 8 insertions(+)
diff --git a/hw/block/virtio-blk.c b/hw/block/virtio-blk.c
index bac2d6fa2b..f96e4ac274 100644
--- a/hw/block/virtio-blk.c
+++ b/hw/block/virtio-blk.c
@@ -899,6 +899,10 @@ static void virtio_blk_reset(VirtIODevice *vdev)
AioContext *ctx;
VirtIOBlockReq *req;
+if (blk_iohang_is_enabled(s->blk)) {
+blk_rehandle_pause(s->blk);
+}
+
ctx = blk_get_aio_context(s->blk);
aio_context_acquire(ctx);
blk_drain(s->blk);
@@ -916,6 +920,10 @@ static void virtio_blk_reset(VirtIODevice *vdev)
assert(!s->dataplane_started);
blk_set_enable_write_cache(s->blk, s->original_wce);
+
+if (blk_iohang_is_enabled(s->blk)) {
+blk_rehandle_unpause(s->blk);
+}
}
/* coalesce internal state, copy to pci i/o region 0
--
2.28.0
Re: [PATCH 16/16] tests/acceptance: Test the MIPSsim machine
Daniel P. Berrangé writes:
> On Tue, Sep 29, 2020 at 10:38:30AM +0100, Alex Bennée wrote:
>>
>> Philippe Mathieu-Daudé writes:
>>
>> > +Alex/Daniel
>> >
>> > On 9/28/20 10:33 PM, Willian Rampazzo wrote:
>> >> On Mon, Sep 28, 2020 at 2:31 PM Philippe Mathieu-Daudé
>> >> wrote:
>> >>>
>> >>> Add a test for the mipssim machine, based on the recommended
>> >>> test setup from Thomas Huth:
>> >>> https://www.mail-archive.com/qemu-devel@nongnu.org/msg606846.html
>> >>>
>> >>> The test is quick and can be run as:
>> >>>
>> >>> $ avocado --show=console run -t machine:mipssim tests/acceptance/
>> >>>(1/1)
>> >>> tests/acceptance/machine_mips_mipssim.py:MipsSimMachine.test_mipssim_linux_console:
>> >>> console: Linux version 3.6.11 (root@711bb8ba16a7) (gcc version 4.8.3
>> >>> (Buildroot 2014.11) ) #2 Sun Sep 27 13:39:35 UTC 2020
>> >>> console: Setting default memory size 0x0200
>> >>> console: bootconsole [early0] enabled
>> >>> console: CPU revision is: 00019300 (MIPS 24Kc)
>> >>> console: FPU revision is: 00739300
>> >>> ...
>> >>> console: CPU frequency 12.00 MHz
>> >>> console: Calibrating delay loop... 950.27 BogoMIPS (lpj=4751360)
>> >>> ...
>> >>> console: MIPSNet Ethernet driver. Version: 2007-11-17. (c)2005 MIPS
>> >>> Technologies, Inc.
>> >>> ...
>> >>> console: Welcome to Buildroot
>> >>> console: buildroot login: root
>> >>> console: # root
>> >>> console: -sh: root: not found
>> >>> console: # ping -c 3 10.0.2.2
>> >>> console: PING 10.0.2.2 (10.0.2.2): 56 data bytes
>> >>> console: 64 bytes from 10.0.2.2: seq=0 ttl=255 time=48.231 ms
>> >>> console: 64 bytes from 10.0.2.2: seq=1 ttl=255 time=9.407 ms
>> >>> console: 64 bytes from 10.0.2.2: seq=2 ttl=255 time=2.298 ms
>> >>> console: --- 10.0.2.2 ping statistics ---
>> >>> console: 3 packets transmitted, 3 packets received, 0% packet loss
>> >>> PASS (7.99 s)
>> >>>
>> >>> Signed-off-by: Philippe Mathieu-Daudé
>> >>> ---
>> >>> Cc: Thomas Huth
>> >>> ---
>> >>> MAINTAINERS | 1 +
>> >>> tests/acceptance/machine_mips_mipssim.py | 56
>> >>> 2 files changed, 57 insertions(+)
>> >>> create mode 100644 tests/acceptance/machine_mips_mipssim.py
>> >>>
>> >>> diff --git a/MAINTAINERS b/MAINTAINERS
>> >>> index 5eed1e692b4..17d8a012b0e 100644
>> >>> --- a/MAINTAINERS
>> >>> +++ b/MAINTAINERS
>> >>> @@ -240,6 +240,7 @@ F: include/hw/misc/mips_*
>> >>> F: include/hw/timer/mips_gictimer.h
>> >>> F: tests/acceptance/linux_ssh_mips_malta.py
>> >>> F: tests/acceptance/machine_mips_malta.py
>> >>> +F: tests/acceptance/machine_mips_mipssim.py
>> >>> F: tests/tcg/mips/
>> >>> K: ^Subject:.*(?i)mips
>> >>>
>> >>> diff --git a/tests/acceptance/machine_mips_mipssim.py
>> >>> b/tests/acceptance/machine_mips_mipssim.py
>> >>> new file mode 100644
>> >>> index 000..b2749917b08
>> >>> --- /dev/null
>> >>> +++ b/tests/acceptance/machine_mips_mipssim.py
>> >>> @@ -0,0 +1,56 @@
>> >>> +# Functional tests for the MIPS simulator (MIPSsim machine)
>> >>> +#
>> >>> +# Copyright (c) 2020 Philippe Mathieu-Daudé
>> >>> +#
>> >>> +# This work is licensed under the terms of the GNU GPL, version 2 or
>> >>> later.
>> >>> +# See the COPYING file in the top-level directory.
>> >>> +#
>> >>> +# SPDX-License-Identifier: GPL-2.0-or-later
>> >>> +
>> >>> +import os
>> >>> +import logging
>> >>> +import time
>> >>> +
>> >>> +from avocado import skipUnless
>> >>> +from avocado_qemu import Test
>> >>> +from avocado_qemu import exec_command_and_wait_for_pattern
>> >>> +from avocado_qemu import interrupt_interactive_console_until_pattern
>> >>> +from avocado_qemu import wait_for_console_pattern
>> >>> +
>> >>> +class MipsSimMachine(Test):
>> >>> +
>> >>> +timeout = 30
>> >>> +KERNEL_COMMON_COMMAND_LINE = 'printk.time=0 '
>> >>> +
>> >>> +@skipUnless(os.getenv('AVOCADO_ALLOW_UNTRUSTED_CODE'), 'untrusted
>> >>> code')
>> >>> +def test_mipssim_linux_console(self):
>> >>> +"""
>> >>> +Boots the Linux kernel and checks that the console is
>> >>> operational
>> >>> +:avocado: tags=arch:mipsel
>> >>> +:avocado: tags=machine:mipssim
>> >>> +:avocado: tags=device:mipsnet
>> >>> +"""
>> >>> +kernel_url = ('https://github.com/philmd/qemu-testing-blob/raw/'
>> >>> + '32ea5764e1de8fffa0d59366c44822cd06d7c8e0/'
>> >>> + 'mips/mipssim/mipsel/vmlinux')
>> >>
>> >> So, are you willing to maintain some images on your GitHub to avoid
>> >> the image changes when they are not found?
>> >
>> > No, I am not willing to do that.
>> >
>> > But I see it pointless to have everyone (including CI) to spend 1h
>> > building this image, when the sources and build recipe is available,
>> > making the built image reproducible.
>>
>> I agree we don't want to build from scratch each time. However as we
>> move from relying on third parties (which outside of the major distros
[RFC PATCH v2 2/8] block-backend: rehandle block aios when EIO
When a backend device temporarily does not response, like a network disk down
due to some network faults, any IO to the coresponding virtual block device
in VM would return I/O error. If the hypervisor returns the error to VM, the
filesystem on this block device may not work as usual. And in many situations,
the returned error is often an EIO.
To avoid this unavailablity, we can store the failed AIOs, and resend them
later. If the error is temporary, the retries can succeed and the AIOs can
be successfully completed.
Signed-off-by: Jiahui Cen
Signed-off-by: Ying Fang
---
block/block-backend.c | 89 +++
1 file changed, 89 insertions(+)
diff --git a/block/block-backend.c b/block/block-backend.c
index b8367d82cc..8050669d23 100644
--- a/block/block-backend.c
+++ b/block/block-backend.c
@@ -365,6 +365,12 @@ BlockBackend *blk_new(AioContext *ctx, uint64_t perm,
uint64_t shared_perm)
notifier_list_init(&blk->remove_bs_notifiers);
notifier_list_init(&blk->insert_bs_notifiers);
+/* for rehandle */
+blk->reinfo.enable = false;
+blk->reinfo.ts = NULL;
+qatomic_set(&blk->reinfo.in_flight, 0);
+QTAILQ_INIT(&blk->reinfo.re_aios);
+
QLIST_INIT(&blk->aio_notifiers);
QTAILQ_INSERT_TAIL(&block_backends, blk, link);
@@ -1425,8 +1431,16 @@ static const AIOCBInfo blk_aio_em_aiocb_info = {
.get_aio_context= blk_aio_em_aiocb_get_aio_context,
};
+static void blk_rehandle_timer_cb(void *opaque);
+static void blk_rehandle_aio_complete(BlkAioEmAIOCB *acb);
+
static void blk_aio_complete(BlkAioEmAIOCB *acb)
{
+if (acb->rwco.blk->reinfo.enable) {
+blk_rehandle_aio_complete(acb);
+return;
+}
+
if (acb->has_returned) {
acb->common.cb(acb->common.opaque, acb->rwco.ret);
blk_dec_in_flight(acb->rwco.blk);
@@ -1459,6 +1473,7 @@ static BlockAIOCB *blk_aio_prwv(BlockBackend *blk,
int64_t offset, int bytes,
.ret= NOT_DONE,
};
acb->bytes = bytes;
+acb->co_entry = co_entry;
acb->has_returned = false;
co = qemu_coroutine_create(co_entry, acb);
@@ -2054,6 +2069,20 @@ static int blk_do_set_aio_context(BlockBackend *blk,
AioContext *new_context,
throttle_group_attach_aio_context(tgm, new_context);
bdrv_drained_end(bs);
}
+
+if (blk->reinfo.enable) {
+if (blk->reinfo.ts) {
+timer_del(blk->reinfo.ts);
+timer_free(blk->reinfo.ts);
+}
+blk->reinfo.ts = aio_timer_new(new_context, QEMU_CLOCK_REALTIME,
+ SCALE_MS, blk_rehandle_timer_cb,
+ blk);
+if (qatomic_read(&blk->reinfo.in_flight)) {
+timer_mod(blk->reinfo.ts,
+ qemu_clock_get_ms(QEMU_CLOCK_REALTIME));
+}
+}
}
blk->ctx = new_context;
@@ -2406,6 +2435,66 @@ static void blk_root_drained_end(BdrvChild *child, int
*drained_end_counter)
}
}
+static void blk_rehandle_insert_aiocb(BlockBackend *blk, BlkAioEmAIOCB *acb)
+{
+assert(blk->reinfo.enable);
+
+qatomic_inc(&blk->reinfo.in_flight);
+QTAILQ_INSERT_TAIL(&blk->reinfo.re_aios, acb, list);
+timer_mod(blk->reinfo.ts, qemu_clock_get_ms(QEMU_CLOCK_REALTIME) +
+ blk->reinfo.timer_interval_ms);
+}
+
+static void blk_rehandle_remove_aiocb(BlockBackend *blk, BlkAioEmAIOCB *acb)
+{
+QTAILQ_REMOVE(&blk->reinfo.re_aios, acb, list);
+qatomic_dec(&blk->reinfo.in_flight);
+}
+
+static void blk_rehandle_timer_cb(void *opaque)
+{
+BlockBackend *blk = opaque;
+BlockBackendRehandleInfo *reinfo = &blk->reinfo;
+BlkAioEmAIOCB *acb, *tmp;
+Coroutine *co;
+
+aio_context_acquire(blk_get_aio_context(blk));
+QTAILQ_FOREACH_SAFE(acb, &reinfo->re_aios, list, tmp) {
+if (acb->rwco.ret == NOT_DONE) {
+continue;
+}
+
+blk_inc_in_flight(acb->rwco.blk);
+acb->rwco.ret = NOT_DONE;
+acb->has_returned = false;
+blk_rehandle_remove_aiocb(acb->rwco.blk, acb);
+
+co = qemu_coroutine_create(acb->co_entry, acb);
+qemu_coroutine_enter(co);
+
+acb->has_returned = true;
+if (acb->rwco.ret != NOT_DONE) {
+replay_bh_schedule_oneshot_event(blk_get_aio_context(blk),
+ blk_aio_complete_bh, acb);
+}
+}
+aio_context_release(blk_get_aio_context(blk));
+}
+
+static void blk_rehandle_aio_complete(BlkAioEmAIOCB *acb)
+{
+if (acb->has_returned) {
+blk_dec_in_flight(acb->rwco.blk);
+if (acb->rwco.ret == -EIO) {
+blk_rehandle_insert_aiocb(acb->rwco.blk, acb);
+return;
+}
+
+acb->common.cb(acb->common.opaque, acb->rwco.ret);
+qemu_aio_unref(acb);
+}
+}
+
void blk_register_buf(BlockBackend *blk, void *host, size_t size)
{
bd
[RFC PATCH v2 8/8] qapi: add I/O hang and I/O hang timeout qapi event
Sometimes hypervisor management tools like libvirt may need to monitor
I/O hang events. Let's report I/O hang and I/O hang timeout event via qapi.
Signed-off-by: Jiahui Cen
Signed-off-by: Ying Fang
---
block/block-backend.c | 3 +++
qapi/block-core.json | 26 ++
2 files changed, 29 insertions(+)
diff --git a/block/block-backend.c b/block/block-backend.c
index c812b3a9c7..42337ceb04 100644
--- a/block/block-backend.c
+++ b/block/block-backend.c
@@ -2556,6 +2556,7 @@ static bool blk_iohang_handle(BlockBackend *blk, int
new_status)
/* Case when I/O Hang is recovered */
blk->is_iohang_timeout = false;
blk->iohang_time = 0;
+qapi_event_send_block_io_hang(false);
}
break;
case BLOCK_IO_HANG_STATUS_HANG:
@@ -2563,12 +2564,14 @@ static bool blk_iohang_handle(BlockBackend *blk, int
new_status)
/* Case when I/O hang is first triggered */
blk->iohang_time = qemu_clock_get_ms(QEMU_CLOCK_REALTIME) / 1000;
need_rehandle = true;
+qapi_event_send_block_io_hang(true);
} else {
if (!blk->is_iohang_timeout) {
now = qemu_clock_get_ms(QEMU_CLOCK_REALTIME) / 1000;
if (now >= (blk->iohang_time + blk->iohang_timeout)) {
/* Case when I/O hang is timeout */
blk->is_iohang_timeout = true;
+qapi_event_send_block_io_hang_timeout(true);
} else {
/* Case when I/O hang is continued */
need_rehandle = true;
diff --git a/qapi/block-core.json b/qapi/block-core.json
index 3c16f1e11d..7bdf75c6d7 100644
--- a/qapi/block-core.json
+++ b/qapi/block-core.json
@@ -5535,3 +5535,29 @@
{ 'command': 'blockdev-snapshot-delete-internal-sync',
'data': { 'device': 'str', '*id': 'str', '*name': 'str'},
'returns': 'SnapshotInfo' }
+
+##
+# @BLOCK_IO_HANG:
+#
+# Emitted when device I/O hang trigger event begin or end
+#
+# @set: true if I/O hang begin; false if I/O hang end.
+#
+# Since: 5.2
+#
+##
+{ 'event': 'BLOCK_IO_HANG',
+ 'data': { 'set': 'bool' }}
+
+##
+# @BLOCK_IO_HANG_TIMEOUT:
+#
+# Emitted when device I/O hang timeout event set or clear
+#
+# @set: true if set; false if clear.
+#
+# Since: 5.2
+#
+##
+{ 'event': 'BLOCK_IO_HANG_TIMEOUT',
+ 'data': { 'set': 'bool' }}
--
2.28.0
[RFC PATCH v2 4/8] block-backend: add I/O rehandle pause/unpause
Sometimes there is no need to rehandle AIOs although I/O hang is enabled. For
example, when deleting a block backend, we have to wait AIO completed by calling
blk_drain(), but not care about the results. So a pause interface of I/O hang
is helpful to bypass the rehandle mechanism.
Signed-off-by: Jiahui Cen
Signed-off-by: Ying Fang
---
block/block-backend.c | 60 +++---
include/sysemu/block-backend.h | 2 ++
2 files changed, 58 insertions(+), 4 deletions(-)
diff --git a/block/block-backend.c b/block/block-backend.c
index 90fcc678b5..c16d95a2c9 100644
--- a/block/block-backend.c
+++ b/block/block-backend.c
@@ -37,6 +37,9 @@ static AioContext *blk_aiocb_get_aio_context(BlockAIOCB *acb);
/* block backend rehandle timer interval 5s */
#define BLOCK_BACKEND_REHANDLE_TIMER_INTERVAL 5000
+#define BLOCK_BACKEND_REHANDLE_NORMAL 1
+#define BLOCK_BACKEND_REHANDLE_DRAIN_REQUESTED 2
+#define BLOCK_BACKEND_REHANDLE_DRAINED 3
enum BlockIOHangStatus {
BLOCK_IO_HANG_STATUS_NORMAL = 0,
@@ -50,6 +53,8 @@ typedef struct BlockBackendRehandleInfo {
unsigned int in_flight;
QTAILQ_HEAD(, BlkAioEmAIOCB) re_aios;
+
+int status;
} BlockBackendRehandleInfo;
typedef struct BlockBackendAioNotifier {
@@ -2461,6 +2466,51 @@ static void blk_rehandle_remove_aiocb(BlockBackend *blk,
BlkAioEmAIOCB *acb)
qatomic_dec(&blk->reinfo.in_flight);
}
+static void blk_rehandle_drain(BlockBackend *blk)
+{
+if (blk_bs(blk)) {
+bdrv_drained_begin(blk_bs(blk));
+BDRV_POLL_WHILE(blk_bs(blk), qatomic_read(&blk->reinfo.in_flight) > 0);
+bdrv_drained_end(blk_bs(blk));
+}
+}
+
+static bool blk_rehandle_is_paused(BlockBackend *blk)
+{
+return blk->reinfo.status == BLOCK_BACKEND_REHANDLE_DRAIN_REQUESTED ||
+ blk->reinfo.status == BLOCK_BACKEND_REHANDLE_DRAINED;
+}
+
+void blk_rehandle_pause(BlockBackend *blk)
+{
+BlockBackendRehandleInfo *reinfo = &blk->reinfo;
+
+aio_context_acquire(blk_get_aio_context(blk));
+if (!reinfo->enable || reinfo->status == BLOCK_BACKEND_REHANDLE_DRAINED) {
+aio_context_release(blk_get_aio_context(blk));
+return;
+}
+
+reinfo->status = BLOCK_BACKEND_REHANDLE_DRAIN_REQUESTED;
+blk_rehandle_drain(blk);
+reinfo->status = BLOCK_BACKEND_REHANDLE_DRAINED;
+aio_context_release(blk_get_aio_context(blk));
+}
+
+void blk_rehandle_unpause(BlockBackend *blk)
+{
+BlockBackendRehandleInfo *reinfo = &blk->reinfo;
+
+aio_context_acquire(blk_get_aio_context(blk));
+if (!reinfo->enable || reinfo->status == BLOCK_BACKEND_REHANDLE_NORMAL) {
+aio_context_release(blk_get_aio_context(blk));
+return;
+}
+
+reinfo->status = BLOCK_BACKEND_REHANDLE_NORMAL;
+aio_context_release(blk_get_aio_context(blk));
+}
+
static void blk_rehandle_timer_cb(void *opaque)
{
BlockBackend *blk = opaque;
@@ -2560,10 +2610,12 @@ static void blk_rehandle_aio_complete(BlkAioEmAIOCB
*acb)
if (acb->has_returned) {
blk_dec_in_flight(acb->rwco.blk);
-need_rehandle = blk_rehandle_aio(acb, &has_timeout);
-if (need_rehandle) {
-blk_rehandle_insert_aiocb(acb->rwco.blk, acb);
-return;
+if (!blk_rehandle_is_paused(acb->rwco.blk)) {
+need_rehandle = blk_rehandle_aio(acb, &has_timeout);
+if (need_rehandle) {
+blk_rehandle_insert_aiocb(acb->rwco.blk, acb);
+return;
+}
}
acb->common.cb(acb->common.opaque, acb->rwco.ret);
diff --git a/include/sysemu/block-backend.h b/include/sysemu/block-backend.h
index bfebe3a960..391a047444 100644
--- a/include/sysemu/block-backend.h
+++ b/include/sysemu/block-backend.h
@@ -268,6 +268,8 @@ const BdrvChild *blk_root(BlockBackend *blk);
int blk_make_empty(BlockBackend *blk, Error **errp);
+void blk_rehandle_pause(BlockBackend *blk);
+void blk_rehandle_unpause(BlockBackend *blk);
void blk_iohang_init(BlockBackend *blk, int64_t iohang_timeout);
#endif
--
2.28.0
[RFC PATCH v2 3/8] block-backend: add I/O hang timeout
Not all errors would be fixed, so it is better to add a rehandle timeout
for I/O hang.
Signed-off-by: Jiahui Cen
Signed-off-by: Ying Fang
---
block/block-backend.c | 99 +-
include/sysemu/block-backend.h | 2 +
2 files changed, 100 insertions(+), 1 deletion(-)
diff --git a/block/block-backend.c b/block/block-backend.c
index 8050669d23..90fcc678b5 100644
--- a/block/block-backend.c
+++ b/block/block-backend.c
@@ -38,6 +38,11 @@ static AioContext *blk_aiocb_get_aio_context(BlockAIOCB
*acb);
/* block backend rehandle timer interval 5s */
#define BLOCK_BACKEND_REHANDLE_TIMER_INTERVAL 5000
+enum BlockIOHangStatus {
+BLOCK_IO_HANG_STATUS_NORMAL = 0,
+BLOCK_IO_HANG_STATUS_HANG,
+};
+
typedef struct BlockBackendRehandleInfo {
bool enable;
QEMUTimer *ts;
@@ -109,6 +114,11 @@ struct BlockBackend {
unsigned int in_flight;
BlockBackendRehandleInfo reinfo;
+
+int64_t iohang_timeout; /* The I/O hang timeout value in sec. */
+int64_t iohang_time;/* The I/O hang start time */
+bool is_iohang_timeout;
+int iohang_status;
};
typedef struct BlockBackendAIOCB {
@@ -2481,20 +2491,107 @@ static void blk_rehandle_timer_cb(void *opaque)
aio_context_release(blk_get_aio_context(blk));
}
+static bool blk_iohang_handle(BlockBackend *blk, int new_status)
+{
+int64_t now;
+int old_status = blk->iohang_status;
+bool need_rehandle = false;
+
+switch (new_status) {
+case BLOCK_IO_HANG_STATUS_NORMAL:
+if (old_status == BLOCK_IO_HANG_STATUS_HANG) {
+/* Case when I/O Hang is recovered */
+blk->is_iohang_timeout = false;
+blk->iohang_time = 0;
+}
+break;
+case BLOCK_IO_HANG_STATUS_HANG:
+if (old_status != BLOCK_IO_HANG_STATUS_HANG) {
+/* Case when I/O hang is first triggered */
+blk->iohang_time = qemu_clock_get_ms(QEMU_CLOCK_REALTIME) / 1000;
+need_rehandle = true;
+} else {
+if (!blk->is_iohang_timeout) {
+now = qemu_clock_get_ms(QEMU_CLOCK_REALTIME) / 1000;
+if (now >= (blk->iohang_time + blk->iohang_timeout)) {
+/* Case when I/O hang is timeout */
+blk->is_iohang_timeout = true;
+} else {
+/* Case when I/O hang is continued */
+need_rehandle = true;
+}
+}
+}
+break;
+default:
+break;
+}
+
+blk->iohang_status = new_status;
+return need_rehandle;
+}
+
+static bool blk_rehandle_aio(BlkAioEmAIOCB *acb, bool *has_timeout)
+{
+bool need_rehandle = false;
+
+/* Rehandle aio which returns EIO before hang timeout */
+if (acb->rwco.ret == -EIO) {
+if (acb->rwco.blk->is_iohang_timeout) {
+/* I/O hang has timeout and not recovered */
+*has_timeout = true;
+} else {
+need_rehandle = blk_iohang_handle(acb->rwco.blk,
+ BLOCK_IO_HANG_STATUS_HANG);
+/* I/O hang timeout first trigger */
+if (acb->rwco.blk->is_iohang_timeout) {
+*has_timeout = true;
+}
+}
+}
+
+return need_rehandle;
+}
+
static void blk_rehandle_aio_complete(BlkAioEmAIOCB *acb)
{
+bool has_timeout = false;
+bool need_rehandle = false;
+
if (acb->has_returned) {
blk_dec_in_flight(acb->rwco.blk);
-if (acb->rwco.ret == -EIO) {
+need_rehandle = blk_rehandle_aio(acb, &has_timeout);
+if (need_rehandle) {
blk_rehandle_insert_aiocb(acb->rwco.blk, acb);
return;
}
acb->common.cb(acb->common.opaque, acb->rwco.ret);
+
+/* I/O hang return to normal status */
+if (!has_timeout) {
+blk_iohang_handle(acb->rwco.blk, BLOCK_IO_HANG_STATUS_NORMAL);
+}
+
qemu_aio_unref(acb);
}
}
+void blk_iohang_init(BlockBackend *blk, int64_t iohang_timeout)
+{
+if (!blk) {
+return;
+}
+
+blk->is_iohang_timeout = false;
+blk->iohang_time = 0;
+blk->iohang_timeout = 0;
+blk->iohang_status = BLOCK_IO_HANG_STATUS_NORMAL;
+if (iohang_timeout > 0) {
+blk->iohang_timeout = iohang_timeout;
+}
+}
+
void blk_register_buf(BlockBackend *blk, void *host, size_t size)
{
bdrv_register_buf(blk_bs(blk), host, size);
diff --git a/include/sysemu/block-backend.h b/include/sysemu/block-backend.h
index 8203d7f6f9..bfebe3a960 100644
--- a/include/sysemu/block-backend.h
+++ b/include/sysemu/block-backend.h
@@ -268,4 +268,6 @@ const BdrvChild *blk_root(BlockBackend *blk);
int blk_make_empty(BlockBackend *blk, Error **errp);
+void blk_iohang_init(BlockBackend *blk, int64_t iohang_timeout);
+
#endif
--
2.28.0
[RFC PATCH v2 5/8] block-backend: enable I/O hang when timeout is set
Setting a non-zero timeout of I/O hang indicates I/O hang is enabled for the
block backend. And when the block backend is going to be deleted, we should
disable I/O hang.
Signed-off-by: Jiahui Cen
Signed-off-by: Ying Fang
---
block/block-backend.c | 40 ++
include/sysemu/block-backend.h | 1 +
2 files changed, 41 insertions(+)
diff --git a/block/block-backend.c b/block/block-backend.c
index c16d95a2c9..c812b3a9c7 100644
--- a/block/block-backend.c
+++ b/block/block-backend.c
@@ -34,6 +34,7 @@
#define NOT_DONE 0x7fff /* used while emulated sync operation in progress
*/
static AioContext *blk_aiocb_get_aio_context(BlockAIOCB *acb);
+static void blk_rehandle_disable(BlockBackend *blk);
/* block backend rehandle timer interval 5s */
#define BLOCK_BACKEND_REHANDLE_TIMER_INTERVAL 5000
@@ -476,6 +477,8 @@ static void blk_delete(BlockBackend *blk)
assert(!blk->refcnt);
assert(!blk->name);
assert(!blk->dev);
+assert(qatomic_read(&blk->reinfo.in_flight) == 0);
+blk_rehandle_disable(blk);
if (blk->public.throttle_group_member.throttle_state) {
blk_io_limits_disable(blk);
}
@@ -2629,6 +2632,42 @@ static void blk_rehandle_aio_complete(BlkAioEmAIOCB *acb)
}
}
+static void blk_rehandle_enable(BlockBackend *blk)
+{
+BlockBackendRehandleInfo *reinfo = &blk->reinfo;
+
+aio_context_acquire(blk_get_aio_context(blk));
+if (reinfo->enable) {
+aio_context_release(blk_get_aio_context(blk));
+return;
+}
+
+reinfo->ts = aio_timer_new(blk_get_aio_context(blk), QEMU_CLOCK_REALTIME,
+ SCALE_MS, blk_rehandle_timer_cb, blk);
+reinfo->timer_interval_ms = BLOCK_BACKEND_REHANDLE_TIMER_INTERVAL;
+reinfo->status = BLOCK_BACKEND_REHANDLE_NORMAL;
+reinfo->enable = true;
+aio_context_release(blk_get_aio_context(blk));
+}
+
+static void blk_rehandle_disable(BlockBackend *blk)
+{
+if (!blk->reinfo.enable) {
+return;
+}
+
+blk_rehandle_pause(blk);
+timer_del(blk->reinfo.ts);
+timer_free(blk->reinfo.ts);
+blk->reinfo.ts = NULL;
+blk->reinfo.enable = false;
+}
+
+bool blk_iohang_is_enabled(BlockBackend *blk)
+{
+return blk->iohang_timeout != 0;
+}
+
void blk_iohang_init(BlockBackend *blk, int64_t iohang_timeout)
{
if (!blk) {
@@ -2641,6 +2680,7 @@ void blk_iohang_init(BlockBackend *blk, int64_t
iohang_timeout)
blk->iohang_status = BLOCK_IO_HANG_STATUS_NORMAL;
if (iohang_timeout > 0) {
blk->iohang_timeout = iohang_timeout;
+blk_rehandle_enable(blk);
}
}
diff --git a/include/sysemu/block-backend.h b/include/sysemu/block-backend.h
index 391a047444..851b90b99b 100644
--- a/include/sysemu/block-backend.h
+++ b/include/sysemu/block-backend.h
@@ -270,6 +270,7 @@ int blk_make_empty(BlockBackend *blk, Error **errp);
void blk_rehandle_pause(BlockBackend *blk);
void blk_rehandle_unpause(BlockBackend *blk);
+bool blk_iohang_is_enabled(BlockBackend *blk);
void blk_iohang_init(BlockBackend *blk, int64_t iohang_timeout);
#endif
--
2.28.0
[PATCH RFC 01/14] cris/: fix some comment spelling errors
I found that there are many spelling errors in the comments of qemu/target/cris.
I used spellcheck to check the spelling errors and found some errors in the
folder.
Signed-off-by: zhaolichang
---
target/cris/helper.c| 6 +++---
target/cris/op_helper.c | 2 +-
target/cris/translate.c | 14 +++---
3 files changed, 11 insertions(+), 11 deletions(-)
diff --git a/target/cris/helper.c b/target/cris/helper.c
index b5159b8..50419e7 100644
--- a/target/cris/helper.c
+++ b/target/cris/helper.c
@@ -141,7 +141,7 @@ void crisv10_cpu_do_interrupt(CPUState *cs)
assert(!(env->pregs[PR_CCS] & PFIX_FLAG));
switch (cs->exception_index) {
case EXCP_BREAK:
-/* These exceptions are genereated by the core itself.
+/* These exceptions are generated by the core itself.
ERP should point to the insn following the brk. */
ex_vec = env->trap_vector;
env->pregs[PRV10_BRP] = env->pc;
@@ -197,7 +197,7 @@ void cris_cpu_do_interrupt(CPUState *cs)
switch (cs->exception_index) {
case EXCP_BREAK:
-/* These exceptions are genereated by the core itself.
+/* These exceptions are generated by the core itself.
ERP should point to the insn following the brk. */
ex_vec = env->trap_vector;
env->pregs[PR_ERP] = env->pc;
@@ -256,7 +256,7 @@ void cris_cpu_do_interrupt(CPUState *cs)
undefined. */
env->pc = cpu_ldl_code(env, env->pregs[PR_EBP] + ex_vec * 4);
-/* Clear the excption_index to avoid spurios hw_aborts for recursive
+/* Clear the excption_index to avoid spurious hw_aborts for recursive
bus faults. */
cs->exception_index = -1;
diff --git a/target/cris/op_helper.c b/target/cris/op_helper.c
index 6b1e7ae..3c4aacc 100644
--- a/target/cris/op_helper.c
+++ b/target/cris/op_helper.c
@@ -231,7 +231,7 @@ static inline uint32_t
evaluate_flags_writeback(CPUCRISState *env,
{
unsigned int x, z, mask;
-/* Extended arithmetics, leave the z flag alone. */
+/* Extended arithmetic, leave the z flag alone. */
x = env->cc_x;
mask = env->cc_mask | X_FLAG;
if (x) {
diff --git a/target/cris/translate.c b/target/cris/translate.c
index c312e6f..16b0ef8 100644
--- a/target/cris/translate.c
+++ b/target/cris/translate.c
@@ -348,7 +348,7 @@ static void t_gen_cris_mstep(TCGv d, TCGv a, TCGv b, TCGv
ccs)
tcg_temp_free(t);
}
-/* Extended arithmetics on CRIS. */
+/* Extended arithmetic on CRIS. */
static inline void t_gen_add_flag(TCGv d, int flag)
{
TCGv c;
@@ -725,7 +725,7 @@ static void cris_alu_op_exec(DisasContext *dc, int op,
switch (op) {
case CC_OP_ADD:
tcg_gen_add_tl(dst, a, b);
-/* Extended arithmetics. */
+/* Extended arithmetic. */
t_gen_addx_carry(dc, dst);
break;
case CC_OP_ADDC:
@@ -738,7 +738,7 @@ static void cris_alu_op_exec(DisasContext *dc, int op,
break;
case CC_OP_SUB:
tcg_gen_sub_tl(dst, a, b);
-/* Extended arithmetics. */
+/* Extended arithmetic. */
t_gen_subx_carry(dc, dst);
break;
case CC_OP_MOVE:
@@ -764,7 +764,7 @@ static void cris_alu_op_exec(DisasContext *dc, int op,
break;
case CC_OP_NEG:
tcg_gen_neg_tl(dst, b);
-/* Extended arithmetics. */
+/* Extended arithmetic. */
t_gen_subx_carry(dc, dst);
break;
case CC_OP_LZ:
@@ -787,7 +787,7 @@ static void cris_alu_op_exec(DisasContext *dc, int op,
break;
case CC_OP_CMP:
tcg_gen_sub_tl(dst, a, b);
-/* Extended arithmetics. */
+/* Extended arithmetic. */
t_gen_subx_carry(dc, dst);
break;
default:
@@ -3053,12 +3053,12 @@ static unsigned int crisv32_decoder(CPUCRISState *env,
DisasContext *dc)
* On QEMU care needs to be taken when a branch+delayslot sequence is broken
* and the branch and delayslot don't share pages.
*
- * The TB contaning the branch insn will set up env->btarget and evaluate
+ * The TB containing the branch insn will set up env->btarget and evaluate
* env->btaken. When the translation loop exits we will note that the branch
* sequence is broken and let env->dslot be the size of the branch insn (those
* vary in length).
*
- * The TB contaning the delayslot will have the PC of its real insn (i.e no lsb
+ * The TB containing the delayslot will have the PC of its real insn (i.e no
lsb
* set). It will also expect to have env->dslot setup with the size of the
* delay slot so that env->pc - env->dslot point to the branch insn. This TB
* will execute the dslot and take the branch, either to btarget or just one
--
2.26.2.windows.1
[PATCH RFC 02/14] ppc/: fix some comment spelling errors
I found that there are many spelling errors in the comments of qemu/target/ppc.
I used spellcheck to check the spelling errors and found some errors in the
folder.
Signed-off-by: zhaolichang
---
target/ppc/cpu.h| 6 +++---
target/ppc/excp_helper.c| 6 +++---
target/ppc/fpu_helper.c | 2 +-
target/ppc/internal.h | 2 +-
target/ppc/kvm.c| 2 +-
target/ppc/machine.c| 2 +-
target/ppc/mmu-hash64.c | 2 +-
target/ppc/mmu_helper.c | 4 ++--
target/ppc/translate_init.c.inc | 2 +-
9 files changed, 14 insertions(+), 14 deletions(-)
diff --git a/target/ppc/cpu.h b/target/ppc/cpu.h
index 766e9c5..ba5ebb1 100644
--- a/target/ppc/cpu.h
+++ b/target/ppc/cpu.h
@@ -615,7 +615,7 @@ enum {
#define FPSCR_VXCVI 8 /* Floating-point invalid operation exception (int) */
#define FPSCR_VE 7 /* Floating-point invalid operation exception enable */
#define FPSCR_OE 6 /* Floating-point overflow exception enable */
-#define FPSCR_UE 5 /* Floating-point undeflow exception enable */
+#define FPSCR_UE 5 /* Floating-point underflow exception enable
*/
#define FPSCR_ZE 4 /* Floating-point zero divide exception enable */
#define FPSCR_XE 3 /* Floating-point inexact exception enable */
#define FPSCR_NI 2 /* Floating-point non-IEEE mode */
@@ -2331,13 +2331,13 @@ enum {
/* Internal hardware exception sources */
PPC_INTERRUPT_DECR, /* Decrementer exception*/
PPC_INTERRUPT_HDECR, /* Hypervisor decrementer exception */
-PPC_INTERRUPT_PIT,/* Programmable inteval timer interrupt */
+PPC_INTERRUPT_PIT,/* Programmable interval timer interrupt */
PPC_INTERRUPT_FIT,/* Fixed interval timer interrupt */
PPC_INTERRUPT_WDT,/* Watchdog timer interrupt */
PPC_INTERRUPT_CDOORBELL, /* Critical doorbell interrupt */
PPC_INTERRUPT_DOORBELL, /* Doorbell interrupt */
PPC_INTERRUPT_PERFM, /* Performance monitor interrupt*/
-PPC_INTERRUPT_HMI,/* Hypervisor Maintainance interrupt*/
+PPC_INTERRUPT_HMI,/* Hypervisor Maintenance interrupt*/
PPC_INTERRUPT_HDOORBELL, /* Hypervisor Doorbell interrupt*/
PPC_INTERRUPT_HVIRT, /* Hypervisor virtualization interrupt */
};
diff --git a/target/ppc/excp_helper.c b/target/ppc/excp_helper.c
index a988ba1..d7411bc 100644
--- a/target/ppc/excp_helper.c
+++ b/target/ppc/excp_helper.c
@@ -231,7 +231,7 @@ static inline void powerpc_excp(PowerPCCPU *cpu, int
excp_model, int excp)
}
/*
- * Exception targetting modifiers
+ * Exception targeting modifiers
*
* LPES0 is supported on POWER7/8/9
* LPES1 is not supported (old iSeries mode)
@@ -1015,7 +1015,7 @@ static void ppc_hw_interrupt(CPUPPCState *env)
* This means we will incorrectly execute past the power management
* instruction instead of triggering a reset.
*
- * It generally means a discrepancy between the wakup conditions in the
+ * It generally means a discrepancy between the wakeup conditions in
the
* processor has_work implementation and the logic in this function.
*/
cpu_abort(env_cpu(env),
@@ -1191,7 +1191,7 @@ void helper_rfi(CPUPPCState *env)
void helper_rfid(CPUPPCState *env)
{
/*
- * The architeture defines a number of rules for which bits can
+ * The architecture defines a number of rules for which bits can
* change but in practice, we handle this in hreg_store_msr()
* which will be called by do_rfi(), so there is no need to filter
* here
diff --git a/target/ppc/fpu_helper.c b/target/ppc/fpu_helper.c
index ae43b08..9b8c8b7 100644
--- a/target/ppc/fpu_helper.c
+++ b/target/ppc/fpu_helper.c
@@ -1804,7 +1804,7 @@ uint32_t helper_efdcmpeq(CPUPPCState *env, uint64_t op1,
uint64_t op2)
/*
- * VSX_ADD_SUB - VSX floating point add/subract
+ * VSX_ADD_SUB - VSX floating point add/subtract
* name - instruction mnemonic
* op- operation (add or sub)
* nels - number of elements (1, 2 or 4)
diff --git a/target/ppc/internal.h b/target/ppc/internal.h
index 15d655b..b4df127 100644
--- a/target/ppc/internal.h
+++ b/target/ppc/internal.h
@@ -1,5 +1,5 @@
/*
- * PowerPC interal definitions for qemu.
+ * PowerPC internal definitions for qemu.
*
* This library is free software; you can redistribute it and/or
* modify it under the terms of the GNU Lesser General Public
diff --git a/target/ppc/kvm.c b/target/ppc/kvm.c
index d85ba8f..e85ef2e 100644
--- a/target/ppc/kvm.c
+++ b/target/ppc/kvm.c
@@ -487,7 +487,7 @@ int kvm_arch_init_vcpu(CPUState *cs)
/*
* KVM-HV has transactional memory on POWER8 also without
[RFC PATCH v2 7/8] qemu-option: add I/O hang timeout option
I/O hang timeout should be different under different situations. So it is
better to provide an option for user to determine I/O hang timeout for
each block device.
Signed-off-by: Jiahui Cen
Signed-off-by: Ying Fang
---
blockdev.c | 11 +++
1 file changed, 11 insertions(+)
diff --git a/blockdev.c b/blockdev.c
index bebd3ba1c3..127a7ea894 100644
--- a/blockdev.c
+++ b/blockdev.c
@@ -500,6 +500,7 @@ static BlockBackend *blockdev_init(const char *file, QDict
*bs_opts,
BlockdevDetectZeroesOptions detect_zeroes =
BLOCKDEV_DETECT_ZEROES_OPTIONS_OFF;
const char *throttling_group = NULL;
+int64_t iohang_timeout = 0;
/* Check common options by copying from bs_opts to opts, all other options
* stay in bs_opts for processing by bdrv_open(). */
@@ -622,6 +623,12 @@ static BlockBackend *blockdev_init(const char *file, QDict
*bs_opts,
bs->detect_zeroes = detect_zeroes;
+/* init timeout value for I/O Hang */
+iohang_timeout = qemu_opt_get_number(opts, "iohang-timeout", 0);
+if (iohang_timeout > 0) {
+blk_iohang_init(blk, iohang_timeout);
+}
+
block_acct_setup(blk_get_stats(blk), account_invalid, account_failed);
if (!parse_stats_intervals(blk_get_stats(blk), interval_list, errp)) {
@@ -3786,6 +3793,10 @@ QemuOptsList qemu_common_drive_opts = {
.type = QEMU_OPT_BOOL,
.help = "whether to account for failed I/O operations "
"in the statistics",
+},{
+.name = "iohang-timeout",
+.type = QEMU_OPT_NUMBER,
+.help = "timeout value for I/O Hang",
},
{ /* end of list */ }
},
--
2.28.0
[PATCH RFC 00/14] fix some comment spelling errors
I found that there are many spelling errors in the comments of qemu/target/. I used spellcheck to check the spelling errors and found some errors in the folder. The checkpatch.pl file in the Linux kernel can check spelling errors in patches. I'm trying to add this function to the checkpatch.pl in qemu, so that no similar spelling errors will occur in the feture. It's not done yet and I will commit the patch when it's done. Signed-off-by: zhaolichang zhaolichang (14): cris/: fix some comment spelling errors ppc/: fix some comment spelling errors riscv/: fix some comment spelling errors rx/: fix some comment spelling errors tricore/: fix some comment spelling errors mips/: fix some comment spelling errors s390x/: fix some comment spelling errors m68k/: fix some comment spelling errors sh4/: fix some comment spelling errors i386/: fix some comment spelling errors avr/: fix some comment spelling errors arm/: fix some comment spelling errors alpha/: fix some comment spelling errors target/: fix some comment spelling errors target/alpha/cpu.h | 4 ++-- target/alpha/translate.c | 2 +- target/arm/cpu.h | 2 +- target/arm/helper.c | 4 ++-- target/arm/m_helper.c| 2 +- target/arm/translate-a64.c | 4 ++-- target/arm/translate-sve.c | 2 +- target/avr/helper.c | 6 +++--- target/cris/helper.c | 6 +++--- target/cris/op_helper.c | 2 +- target/cris/translate.c | 14 +++--- target/i386/cpu.c| 4 ++-- target/i386/hax-interface.h | 4 ++-- target/i386/hax-windows.c| 2 +- target/i386/kvm.c| 2 +- target/i386/machine.c| 6 +++--- target/i386/translate.c | 8 target/i386/whpx-all.c | 2 +- target/m68k/translate.c | 16 target/mips/internal.h | 2 +- target/mips/translate.c | 10 +- target/mips/translate_init.c.inc | 2 +- target/openrisc/cpu.h| 2 +- target/ppc/cpu.h | 6 +++--- target/ppc/excp_helper.c | 6 +++--- target/ppc/fpu_helper.c | 2 +- target/ppc/internal.h| 2 +- target/ppc/kvm.c | 2 +- target/ppc/machine.c | 2 +- target/ppc/mmu-hash64.c | 2 +- target/ppc/mmu_helper.c | 4 ++-- target/ppc/translate_init.c.inc | 2 +- target/riscv/cpu.c | 2 +- target/riscv/cpu_bits.h | 2 +- target/riscv/csr.c | 6 +++--- target/riscv/vector_helper.c | 2 +- target/rx/op_helper.c| 2 +- target/rx/translate.c| 2 +- target/s390x/cpu_models.h| 4 ++-- target/s390x/excp_helper.c | 2 +- target/s390x/fpu_helper.c| 2 +- target/s390x/insn-data.def | 2 +- target/s390x/ioinst.c| 2 +- target/s390x/misc_helper.c | 2 +- target/s390x/translate.c | 4 ++-- target/s390x/translate_vx.c.inc | 2 +- target/sh4/cpu.h | 2 +- target/sh4/op_helper.c | 2 +- target/sh4/translate.c | 2 +- target/sparc/asi.h | 2 +- target/tricore/csfr.def | 2 +- target/tricore/translate.c | 2 +- target/unicore32/translate.c | 2 +- 53 files changed, 93 insertions(+), 93 deletions(-) -- 2.26.2.windows.1
[PATCH RFC 03/14] riscv/: fix some comment spelling errors
I found that there are many spelling errors in the comments of
qemu/target/riscv.
I used spellcheck to check the spelling errors and found some errors in the
folder.
Signed-off-by: zhaolichang
---
target/riscv/cpu.c | 2 +-
target/riscv/cpu_bits.h | 2 +-
target/riscv/csr.c | 6 +++---
target/riscv/vector_helper.c | 2 +-
4 files changed, 6 insertions(+), 6 deletions(-)
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index 0bbfd7f..f40a0b2 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -472,7 +472,7 @@ static void riscv_cpu_realize(DeviceState *dev, Error
**errp)
return;
}
} else {
-qemu_log("vector verison is not specified, "
+qemu_log("vector version is not specified, "
"use the default value v0.7.1\n");
}
set_vext_version(env, vext_version);
diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h
index bd36062..6e11555 100644
--- a/target/riscv/cpu_bits.h
+++ b/target/riscv/cpu_bits.h
@@ -536,7 +536,7 @@
/* Leaf page shift amount */
#define PGSHIFT 12
-/* Default Reset Vector adress */
+/* Default Reset Vector address */
#define DEFAULT_RSTVEC 0x1000
/* Exception causes */
diff --git a/target/riscv/csr.c b/target/riscv/csr.c
index 26ae347..559db11 100644
--- a/target/riscv/csr.c
+++ b/target/riscv/csr.c
@@ -624,7 +624,7 @@ static int write_mcounteren(CPURISCVState *env, int csrno,
target_ulong val)
return 0;
}
-/* This regiser is replaced with CSR_MCOUNTINHIBIT in 1.11.0 */
+/* This register is replaced with CSR_MCOUNTINHIBIT in 1.11.0 */
static int read_mscounteren(CPURISCVState *env, int csrno, target_ulong *val)
{
if (env->priv_ver < PRIV_VERSION_1_11_0) {
@@ -634,7 +634,7 @@ static int read_mscounteren(CPURISCVState *env, int csrno,
target_ulong *val)
return 0;
}
-/* This regiser is replaced with CSR_MCOUNTINHIBIT in 1.11.0 */
+/* This register is replaced with CSR_MCOUNTINHIBIT in 1.11.0 */
static int write_mscounteren(CPURISCVState *env, int csrno, target_ulong val)
{
if (env->priv_ver < PRIV_VERSION_1_11_0) {
@@ -1278,7 +1278,7 @@ int riscv_csrrw(CPURISCVState *env, int csrno,
target_ulong *ret_value,
!riscv_cpu_virt_enabled(env)) {
/*
* We are in S mode without virtualisation, therefore we are in HS
Mode.
- * Add 1 to the effective privledge level to allow us to access the
+ * Add 1 to the effective privilege level to allow us to access the
* Hypervisor CSRs.
*/
effective_priv++;
diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c
index a156573..fa89a6e 100644
--- a/target/riscv/vector_helper.c
+++ b/target/riscv/vector_helper.c
@@ -709,7 +709,7 @@ typedef void vext_amo_noatomic_fn(void *vs3, target_ulong
addr,
uint32_t wd, uint32_t idx, CPURISCVState
*env,
uintptr_t retaddr);
-/* no atomic opreation for vector atomic insructions */
+/* no atomic operation for vector atomic insructions */
#define DO_SWAP(N, M) (M)
#define DO_AND(N, M) (N & M)
#define DO_XOR(N, M) (N ^ M)
--
2.26.2.windows.1
[PATCH RFC 04/14] rx/: fix some comment spelling errors
I found that there are many spelling errors in the comments of qemu/target/rx.
I used spellcheck to check the spelling errors and found some errors in the
folder.
Signed-off-by: zhaolichang
---
target/rx/op_helper.c | 2 +-
target/rx/translate.c | 2 +-
2 files changed, 2 insertions(+), 2 deletions(-)
diff --git a/target/rx/op_helper.c b/target/rx/op_helper.c
index f89d294..59389f4 100644
--- a/target/rx/op_helper.c
+++ b/target/rx/op_helper.c
@@ -318,7 +318,7 @@ void helper_swhile(CPURXState *env, uint32_t sz)
env->psw_c = (tmp <= env->regs[2]);
}
-/* accumlator operations */
+/* accumulator operations */
void helper_rmpa(CPURXState *env, uint32_t sz)
{
uint64_t result_l, prev;
diff --git a/target/rx/translate.c b/target/rx/translate.c
index 482278e..9ea941c 100644
--- a/target/rx/translate.c
+++ b/target/rx/translate.c
@@ -1089,7 +1089,7 @@ static void rx_sub(TCGv ret, TCGv arg1, TCGv arg2)
tcg_gen_xor_i32(temp, arg1, arg2);
tcg_gen_and_i32(cpu_psw_o, cpu_psw_o, temp);
tcg_temp_free_i32(temp);
-/* CMP not requred return */
+/* CMP not required return */
if (ret) {
tcg_gen_mov_i32(ret, cpu_psw_s);
}
--
2.26.2.windows.1
[PATCH RFC 12/14] arm/: fix some comment spelling errors
I found that there are many spelling errors in the comments of qemu/target/arm.
I used spellcheck to check the spelling errors and found some errors in the
folder.
Signed-off-by: zhaolichang
---
target/arm/cpu.h | 2 +-
target/arm/helper.c| 4 ++--
target/arm/m_helper.c | 2 +-
target/arm/translate-a64.c | 4 ++--
target/arm/translate-sve.c | 2 +-
5 files changed, 7 insertions(+), 7 deletions(-)
diff --git a/target/arm/cpu.h b/target/arm/cpu.h
index 6036f61..996308b 100644
--- a/target/arm/cpu.h
+++ b/target/arm/cpu.h
@@ -2067,7 +2067,7 @@ static inline bool arm_el_is_aa64(CPUARMState *env, int
el)
return aa64;
}
-/* Function for determing whether guest cp register reads and writes should
+/* Function for determining whether guest cp register reads and writes should
* access the secure or non-secure bank of a cp register. When EL3 is
* operating in AArch32 state, the NS-bit determines whether the secure
* instance of a cp register should be used. When EL3 is AArch64 (or if
diff --git a/target/arm/helper.c b/target/arm/helper.c
index 88bd9dd..9292e16 100644
--- a/target/arm/helper.c
+++ b/target/arm/helper.c
@@ -1867,7 +1867,7 @@ static void pmevtyper_rawwrite(CPUARMState *env, const
ARMCPRegInfo *ri,
* pmevtyper_rawwrite is called between a pair of pmu_op_start and
* pmu_op_finish calls when loading saved state for a migration. Because
* we're potentially updating the type of event here, the value written to
- * c14_pmevcntr_delta by the preceeding pmu_op_start call may be for a
+ * c14_pmevcntr_delta by the preceding pmu_op_start call may be for a
* different counter type. Therefore, we need to set this value to the
* current count for the counter type we're writing so that pmu_op_finish
* has the correct count for its calculation.
@@ -12214,7 +12214,7 @@ bool get_phys_addr(CPUARMState *env, target_ulong
address,
} else {
memattr = 0x44; /* Normal, NC, No */
}
-cacheattrs->shareability = 2; /* outer sharable */
+cacheattrs->shareability = 2; /* outer shareable */
} else {
memattr = 0x00; /* Device, nGnRnE */
}
diff --git a/target/arm/m_helper.c b/target/arm/m_helper.c
index 0364542..1e8080d 100644
--- a/target/arm/m_helper.c
+++ b/target/arm/m_helper.c
@@ -158,7 +158,7 @@ uint32_t HELPER(v7m_tt)(CPUARMState *env, uint32_t addr,
uint32_t op)
* R: 0 because unpriv and A flag not set
* SRVALID: 0 because NS
* MRVALID: 0 because unpriv and A flag not set
- * SREGION: 0 becaus SRVALID is 0
+ * SREGION: 0 because SRVALID is 0
* MREGION: 0 because MRVALID is 0
*/
return 0;
diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
index 7188808..5451f02 100644
--- a/target/arm/translate-a64.c
+++ b/target/arm/translate-a64.c
@@ -160,7 +160,7 @@ void gen_a64_set_pc_im(uint64_t val)
* + for EL2 and EL3 there is only one TBI bit, and if it is set
*then the address is zero-extended, clearing bits [63:56]
* + for EL0 and EL1, TBI0 controls addresses with bit 55 == 0
- *and TBI1 controls addressses with bit 55 == 1.
+ *and TBI1 controls addresses with bit 55 == 1.
*If the appropriate TBI bit is set for the address then
*the address is sign-extended from bit 55 into bits [63:56]
*
@@ -1964,7 +1964,7 @@ static void handle_sys(DisasContext *s, uint32_t insn,
bool isread,
}
if (!isread && !(ri->type & ARM_CP_SUPPRESS_TB_END)) {
/*
- * A write to any coprocessor regiser that ends a TB
+ * A write to any coprocessor register that ends a TB
* must rebuild the hflags for the next TB.
*/
TCGv_i32 tcg_el = tcg_const_i32(s->current_el);
diff --git a/target/arm/translate-sve.c b/target/arm/translate-sve.c
index e4cd6b6..4e8a1c7 100644
--- a/target/arm/translate-sve.c
+++ b/target/arm/translate-sve.c
@@ -1528,7 +1528,7 @@ static bool trans_PNEXT(DisasContext *s, arg_rr_esz *a)
/* Perform an inline saturating addition of a 32-bit value within
* a 64-bit register. The second operand is known to be positive,
- * which halves the comparisions we must perform to bound the result.
+ * which halves the comparisons we must perform to bound the result.
*/
static void do_sat_addsub_32(TCGv_i64 reg, TCGv_i64 val, bool u, bool d)
{
--
2.26.2.windows.1
[PATCH RFC 05/14] tricore/: fix some comment spelling errors
I found that there are many spelling errors in the comments of
qemu/target/tricore.
I used spellcheck to check the spelling errors and found some errors in the
folder.
Signed-off-by: zhaolichang
---
target/s390x/ioinst.c | 2 +-
target/tricore/csfr.def| 2 +-
target/tricore/translate.c | 2 +-
3 files changed, 3 insertions(+), 3 deletions(-)
diff --git a/target/s390x/ioinst.c b/target/s390x/ioinst.c
index a412926..c576d85 100644
--- a/target/s390x/ioinst.c
+++ b/target/s390x/ioinst.c
@@ -279,7 +279,7 @@ void ioinst_handle_stsch(S390CPU *cpu, uint64_t reg1,
uint32_t ipb,
/*
* As operand exceptions have a lower priority than access exceptions,
* we check whether the memory area is writeable (injecting the
- * access execption if it is not) first.
+ * access exception if it is not) first.
*/
if (!s390_cpu_virt_mem_check_write(cpu, addr, ar, sizeof(schib))) {
s390_program_interrupt(env, PGM_OPERAND, ra);
diff --git a/target/tricore/csfr.def b/target/tricore/csfr.def
index ff004cb..cdfaf1d 100644
--- a/target/tricore/csfr.def
+++ b/target/tricore/csfr.def
@@ -1,4 +1,4 @@
-/* A(ll) access permited
+/* A(ll) access permitted
R(ead only) access
E(nd init protected) access
diff --git a/target/tricore/translate.c b/target/tricore/translate.c
index 7752630..c9c420d 100644
--- a/target/tricore/translate.c
+++ b/target/tricore/translate.c
@@ -397,7 +397,7 @@ static inline void gen_mfcr(DisasContext *ctx, TCGv ret,
int32_t offset)
#undef E
#define R(ADDRESS, REG, FEATURE) /* don't gen writes to read-only reg,
-since no execption occurs */
+since no exception occurs */
#define A(ADDRESS, REG, FEATURE) R(ADDRESS, REG, FEATURE)\
case ADDRESS:\
if (has_feature(ctx, FEATURE)) { \
--
2.26.2.windows.1
[PATCH RFC 07/14] s390x/: fix some comment spelling errors
I found that there are many spelling errors in the comments of
qemu/target/s390x.
I used spellcheck to check the spelling errors and found some errors in the
folder.
Signed-off-by: zhaolichang
---
target/s390x/cpu_models.h | 4 ++--
target/s390x/excp_helper.c | 2 +-
target/s390x/fpu_helper.c | 2 +-
target/s390x/insn-data.def | 2 +-
target/s390x/misc_helper.c | 2 +-
target/s390x/translate.c| 4 ++--
target/s390x/translate_vx.c.inc | 2 +-
7 files changed, 9 insertions(+), 9 deletions(-)
diff --git a/target/s390x/cpu_models.h b/target/s390x/cpu_models.h
index 74d1f87..15c0f0d 100644
--- a/target/s390x/cpu_models.h
+++ b/target/s390x/cpu_models.h
@@ -24,13 +24,13 @@ struct S390CPUDef {
uint8_t gen;/* hw generation identification */
uint16_t type; /* cpu type identification */
uint8_t ec_ga; /* EC GA version (on which also the BC is based) */
-uint8_t mha_pow;/* Maximum Host Adress Power, mha = 2^pow-1 */
+uint8_t mha_pow;/* Maximum Host Address Power, mha = 2^pow-1 */
uint32_t hmfai; /* hypervisor-managed facilities */
/* base/min features, must never be changed between QEMU versions */
S390FeatBitmap base_feat;
/* used to init base_feat from generated data */
S390FeatInit base_init;
-/* deafault features, QEMU version specific */
+/* default features, QEMU version specific */
S390FeatBitmap default_feat;
/* used to init default_feat from generated data */
S390FeatInit default_init;
diff --git a/target/s390x/excp_helper.c b/target/s390x/excp_helper.c
index 3b58d10..9644a67 100644
--- a/target/s390x/excp_helper.c
+++ b/target/s390x/excp_helper.c
@@ -538,7 +538,7 @@ try_deliver:
/* don't trigger a cpu_loop_exit(), use an interrupt instead */
cpu_interrupt(CPU(cpu), CPU_INTERRUPT_HALT);
} else if (cs->halted) {
-/* unhalt if we had a WAIT PSW somehwere in our injection chain */
+/* unhalt if we had a WAIT PSW somewhere in our injection chain */
s390_cpu_unhalt(cpu);
}
}
diff --git a/target/s390x/fpu_helper.c b/target/s390x/fpu_helper.c
index f155bc0..3e609b7 100644
--- a/target/s390x/fpu_helper.c
+++ b/target/s390x/fpu_helper.c
@@ -89,7 +89,7 @@ static void handle_exceptions(CPUS390XState *env, bool XxC,
uintptr_t retaddr)
/*
* invalid/divbyzero cannot coexist with other conditions.
* overflow/underflow however can coexist with inexact, we have to
- * handle it separatly.
+ * handle it separately.
*/
if (s390_exc & ~S390_IEEE_MASK_INEXACT) {
if (s390_exc & ~S390_IEEE_MASK_INEXACT & env->fpc >> 24) {
diff --git a/target/s390x/insn-data.def b/target/s390x/insn-data.def
index d79ae9e..1631948 100644
--- a/target/s390x/insn-data.def
+++ b/target/s390x/insn-data.def
@@ -523,7 +523,7 @@
/* LOAD LOGICAL HALFWORD RELATIVE LONG */
C(0xc402, LLHRL, RIL_b, GIE, 0, ri2, new, r1_32, ld16u, 0)
C(0xc406, LLGHRL, RIL_b, GIE, 0, ri2, r1, 0, ld16u, 0)
-/* LOAD LOGICAL IMMEDATE */
+/* LOAD LOGICAL IMMEDIATE */
D(0xc00e, LLIHF, RIL_a, EI, 0, i2_32u_shl, 0, r1, mov2, 0, 32)
D(0xc00f, LLILF, RIL_a, EI, 0, i2_32u_shl, 0, r1, mov2, 0, 0)
D(0xa50c, LLIHH, RI_a, Z, 0, i2_16u_shl, 0, r1, mov2, 0, 48)
diff --git a/target/s390x/misc_helper.c b/target/s390x/misc_helper.c
index 58dbc02..929e509 100644
--- a/target/s390x/misc_helper.c
+++ b/target/s390x/misc_helper.c
@@ -312,7 +312,7 @@ uint32_t HELPER(stsi)(CPUS390XState *env, uint64_t a0,
uint64_t r0, uint64_t r1)
/* same as machine type number in STORE CPU ID, but in EBCDIC */
snprintf(type, ARRAY_SIZE(type), "%X", cpu->model->def->type);
ebcdic_put(sysib.sysib_111.type, type, 4);
-/* model number (not stored in STORE CPU ID for z/Architecure) */
+/* model number (not stored in STORE CPU ID for z/Architecture) */
ebcdic_put(sysib.sysib_111.model, "QEMU", 16);
ebcdic_put(sysib.sysib_111.sequence, "QEMU", 16);
ebcdic_put(sysib.sysib_111.plant, "QEMU", 4);
diff --git a/target/s390x/translate.c b/target/s390x/translate.c
index a777343..58ad6c8 100644
--- a/target/s390x/translate.c
+++ b/target/s390x/translate.c
@@ -433,7 +433,7 @@ static void gen_program_exception(DisasContext *s, int code)
{
TCGv_i32 tmp;
-/* Remember what pgm exeption this was. */
+/* Remember what pgm exception this was. */
tmp = tcg_const_i32(code);
tcg_gen_st_i32(tmp, cpu_env, offsetof(CPUS390XState, int_pgm_code));
tcg_temp_free_i32(tmp);
@@ -489,7 +489,7 @@ static TCGv_i64 get_address(DisasContext *s, int x2, int
b2, int d2)
/*
* Note that d2 is limited to 20 bits, signed. If we crop negative
- * displacements early we create larger immedate addends.
+ * displacements early we create larger immediate addends.
*/
if (b2 && x2) {
[PATCH RFC 08/14] m68k/: fix some comment spelling errors
I found that there are many spelling errors in the comments of qemu/target/m68k. I used spellcheck to check the spelling errors and found some errors in the folder. Signed-off-by: zhaolichang --- target/m68k/translate.c | 16 1 file changed, 8 insertions(+), 8 deletions(-) diff --git a/target/m68k/translate.c b/target/m68k/translate.c index 3fc67aa..133a404 100644 --- a/target/m68k/translate.c +++ b/target/m68k/translate.c @@ -438,7 +438,7 @@ static TCGv gen_addr_index(DisasContext *s, uint16_t ext, TCGv tmp) } /* - * Handle a base + index + displacement effective addresss. + * Handle a base + index + displacement effective address. * A NULL_QREG base means pc-relative. */ static TCGv gen_lea_indexed(CPUM68KState *env, DisasContext *s, TCGv base) @@ -1696,7 +1696,7 @@ static void bcd_add(TCGv dest, TCGv src) /* * t1 = (src + 0x066) + dest + X - *= result with some possible exceding 0x6 + *= result with some possible exceeding 0x6 */ t0 = tcg_const_i32(0x066); @@ -1706,7 +1706,7 @@ static void bcd_add(TCGv dest, TCGv src) tcg_gen_add_i32(t1, t0, dest); tcg_gen_add_i32(t1, t1, QREG_CC_X); -/* we will remove exceding 0x6 where there is no carry */ +/* we will remove exceeding 0x6 where there is no carry */ /* * t0 = (src + 0x0066) ^ dest @@ -1736,7 +1736,7 @@ static void bcd_add(TCGv dest, TCGv src) tcg_temp_free(t0); /* - * remove the exceding 0x6 + * remove the exceeding 0x6 * for digits that have not generated a carry */ @@ -2638,7 +2638,7 @@ DISAS_INSN(negx) gen_flush_flags(s); /* compute old Z */ /* - * Perform substract with borrow. + * Perform subtract with borrow. * (X, N) = -(src + X); */ @@ -2653,7 +2653,7 @@ DISAS_INSN(negx) /* * Compute signed-overflow for negation. The normal formula for * subtraction is (res ^ src) & (src ^ dest), but with dest==0 - * this simplies to res & src. + * this simplifies to res & src. */ tcg_gen_and_i32(QREG_CC_V, QREG_CC_N, src); @@ -3159,7 +3159,7 @@ static inline void gen_subx(DisasContext *s, TCGv src, TCGv dest, int opsize) gen_flush_flags(s); /* compute old Z */ /* - * Perform substract with borrow. + * Perform subtract with borrow. * (X, N) = dest - (src + X); */ @@ -3169,7 +3169,7 @@ static inline void gen_subx(DisasContext *s, TCGv src, TCGv dest, int opsize) gen_ext(QREG_CC_N, QREG_CC_N, opsize, 1); tcg_gen_andi_i32(QREG_CC_X, QREG_CC_X, 1); -/* Compute signed-overflow for substract. */ +/* Compute signed-overflow for subtract. */ tcg_gen_xor_i32(QREG_CC_V, QREG_CC_N, dest); tcg_gen_xor_i32(tmp, dest, src); -- 2.26.2.windows.1
[PATCH RFC 06/14] mips/: fix some comment spelling errors
I found that there are many spelling errors in the comments of qemu/target/mips.
I used spellcheck to check the spelling errors and found some errors in the
folder.
Signed-off-by: zhaolichang
---
target/mips/internal.h | 2 +-
target/mips/translate.c | 10 +-
target/mips/translate_init.c.inc | 2 +-
3 files changed, 7 insertions(+), 7 deletions(-)
diff --git a/target/mips/internal.h b/target/mips/internal.h
index 7f159a9..b811f54 100644
--- a/target/mips/internal.h
+++ b/target/mips/internal.h
@@ -188,7 +188,7 @@ static inline bool
cpu_mips_hw_interrupts_pending(CPUMIPSState *env)
/*
* A MIPS configured with a vectorizing external interrupt controller
* will feed a vector into the Cause pending lines. The core treats
- * the status lines as a vector level, not as indiviual masks.
+ * the status lines as a vector level, not as individual masks.
*/
r = pending > status;
} else {
diff --git a/target/mips/translate.c b/target/mips/translate.c
index 398edf7..b4d0090 100644
--- a/target/mips/translate.c
+++ b/target/mips/translate.c
@@ -3718,7 +3718,7 @@ static void gen_st_cond(DisasContext *ctx, int rt, int
base, int offset,
t0 = tcg_temp_new();
addr = tcg_temp_new();
-/* compare the address against that of the preceeding LL */
+/* compare the address against that of the preceding LL */
gen_base_offset_addr(ctx, addr, base, offset);
tcg_gen_brcond_tl(TCG_COND_EQ, addr, cpu_lladdr, l1);
tcg_temp_free(addr);
@@ -25597,7 +25597,7 @@ static void gen_mxu_D16MAX_D16MIN(DisasContext *ctx)
}
/* return resulting half-words to its original position */
tcg_gen_shri_i32(t0, t0, 16);
-/* finaly update the destination */
+/* finally update the destination */
tcg_gen_or_i32(mxu_gpr[XRa - 1], mxu_gpr[XRa - 1], t0);
tcg_temp_free(t1);
@@ -25633,7 +25633,7 @@ static void gen_mxu_D16MAX_D16MIN(DisasContext *ctx)
}
/* return resulting half-words to its original position */
tcg_gen_shri_i32(t0, t0, 16);
-/* finaly update the destination */
+/* finally update the destination */
tcg_gen_or_i32(mxu_gpr[XRa - 1], mxu_gpr[XRa - 1], t0);
tcg_temp_free(t1);
@@ -25702,7 +25702,7 @@ static void gen_mxu_Q8MAX_Q8MIN(DisasContext *ctx)
}
/* return resulting byte to its original position */
tcg_gen_shri_i32(t0, t0, 8 * (3 - i));
-/* finaly update the destination */
+/* finally update the destination */
tcg_gen_or_i32(mxu_gpr[XRa - 1], mxu_gpr[XRa - 1], t0);
}
@@ -25742,7 +25742,7 @@ static void gen_mxu_Q8MAX_Q8MIN(DisasContext *ctx)
}
/* return resulting byte to its original position */
tcg_gen_shri_i32(t0, t0, 8 * (3 - i));
-/* finaly update the destination */
+/* finally update the destination */
tcg_gen_or_i32(mxu_gpr[XRa - 1], mxu_gpr[XRa - 1], t0);
}
diff --git a/target/mips/translate_init.c.inc b/target/mips/translate_init.c.inc
index 637cacc..c735b2b 100644
--- a/target/mips/translate_init.c.inc
+++ b/target/mips/translate_init.c.inc
@@ -995,7 +995,7 @@ static void mvp_init (CPUMIPSState *env, const mips_def_t
*def)
/* MVPConf1 implemented, TLB sharable, no gating storage support,
programmable cache partitioning implemented, number of allocatable
- and sharable TLB entries, MVP has allocatable TCs, 2 VPEs
+ and shareable TLB entries, MVP has allocatable TCs, 2 VPEs
implemented, 5 TCs implemented. */
env->mvp->CP0_MVPConf0 = (1U << CP0MVPC0_M) | (1 << CP0MVPC0_TLBS) |
(0 << CP0MVPC0_GS) | (1 << CP0MVPC0_PCP) |
--
2.26.2.windows.1
[PATCH RFC 09/14] sh4/: fix some comment spelling errors
I found that there are many spelling errors in the comments of qemu/target/sh4.
I used spellcheck to check the spelling errors and found some errors in the
folder.
Signed-off-by: zhaolichang
---
target/sh4/cpu.h | 2 +-
target/sh4/op_helper.c | 2 +-
target/sh4/translate.c | 2 +-
3 files changed, 3 insertions(+), 3 deletions(-)
diff --git a/target/sh4/cpu.h b/target/sh4/cpu.h
index dbe58c7..91fa949 100644
--- a/target/sh4/cpu.h
+++ b/target/sh4/cpu.h
@@ -160,7 +160,7 @@ typedef struct CPUSH4State {
uint32_t pteh; /* page table entry high register */
uint32_t ptel; /* page table entry low register */
uint32_t ptea; /* page table entry assistance register */
-uint32_t ttb; /* tranlation table base register */
+uint32_t ttb; /* translation table base register */
uint32_t tea; /* TLB exception address register */
uint32_t tra; /* TRAPA exception register */
uint32_t expevt; /* exception event register */
diff --git a/target/sh4/op_helper.c b/target/sh4/op_helper.c
index 14c3db0..9de4152 100644
--- a/target/sh4/op_helper.c
+++ b/target/sh4/op_helper.c
@@ -400,7 +400,7 @@ float32 helper_fsrra_FT(CPUSH4State *env, float32 t0)
t0 = float32_div(float32_one, t0, &env->fp_status);
/* Since this is supposed to be an approximation, an imprecision
exception is required. One supposes this also follows the usual
- IEEE rule that other exceptions take precidence. */
+ IEEE rule that other exceptions take precedence. */
if (get_float_exception_flags(&env->fp_status) == 0) {
set_float_exception_flags(float_flag_inexact, &env->fp_status);
}
diff --git a/target/sh4/translate.c b/target/sh4/translate.c
index 60c863d..c57218e 100644
--- a/target/sh4/translate.c
+++ b/target/sh4/translate.c
@@ -1959,7 +1959,7 @@ static void decode_gusa(DisasContext *ctx, CPUSH4State
*env)
NEXT_INSN;
switch (ctx->opcode & 0xf00f) {
case 0x6003: /* mov Rm,Rn */
-/* Here we want to recognize ld_dst being saved for later consumtion,
+/* Here we want to recognize ld_dst being saved for later consumption,
or for another input register being copied so that ld_dst need not
be clobbered during the operation. */
op_dst = B11_8;
--
2.26.2.windows.1
[PATCH RFC 10/14] i386/: fix some comment spelling errors
I found that there are many spelling errors in the comments of qemu/target/i386.
I used spellcheck to check the spelling errors and found some errors in the
folder.
Signed-off-by: zhaolichang
---
target/i386/cpu.c | 4 ++--
target/i386/hax-interface.h | 4 ++--
target/i386/hax-windows.c | 2 +-
target/i386/kvm.c | 2 +-
target/i386/machine.c | 6 +++---
target/i386/translate.c | 8
target/i386/whpx-all.c | 2 +-
7 files changed, 14 insertions(+), 14 deletions(-)
diff --git a/target/i386/cpu.c b/target/i386/cpu.c
index 3ffd877..23851e5 100644
--- a/target/i386/cpu.c
+++ b/target/i386/cpu.c
@@ -4677,7 +4677,7 @@ static const char *x86_cpu_feature_name(FeatureWord w,
int bitnr)
return name;
}
-/* Compatibily hack to maintain legacy +-feat semantic,
+/* Compatibility hack to maintain legacy +-feat semantic,
* where +-feat overwrites any feature set by
* feat=on|feat even if the later is parsed after +-feat
* (i.e. "-x2apic,x2apic=on" will result in x2apic disabled)
@@ -6896,7 +6896,7 @@ static void x86_cpu_get_crash_info_qom(Object *obj,
Visitor *v,
GuestPanicInformation *panic_info;
if (!cs->crash_occurred) {
-error_setg(errp, "No crash occured");
+error_setg(errp, "No crash occurred");
return;
}
diff --git a/target/i386/hax-interface.h b/target/i386/hax-interface.h
index 537ae08..edef4fd 100644
--- a/target/i386/hax-interface.h
+++ b/target/i386/hax-interface.h
@@ -238,7 +238,7 @@ enum exit_status {
HAX_EXIT_UNKNOWN_VMEXIT,
/* HALT from guest */
HAX_EXIT_HLT,
-/* Reboot request, like because of tripple fault in guest */
+/* Reboot request, like because of triple fault in guest */
HAX_EXIT_STATECHANGE,
/* the vcpu is now only paused when destroy, so simply return to hax */
HAX_EXIT_PAUSED,
@@ -295,7 +295,7 @@ struct hax_qemu_version {
uint32_t min_version;
} __attribute__ ((__packed__));
-/* The mac specfic interface to qemu, mostly is ioctl related */
+/* The mac specific interface to qemu, mostly is ioctl related */
struct hax_tunnel_info {
uint64_t va;
uint64_t io_va;
diff --git a/target/i386/hax-windows.c b/target/i386/hax-windows.c
index 863c2bc..881089b 100644
--- a/target/i386/hax-windows.c
+++ b/target/i386/hax-windows.c
@@ -174,7 +174,7 @@ int hax_mod_version(struct hax_state *hax, struct
hax_module_version *version)
if (!ret) {
err = GetLastError();
if (err == ERROR_INSUFFICIENT_BUFFER || err == ERROR_MORE_DATA) {
-fprintf(stderr, "hax module verion is too long to hold.\n");
+fprintf(stderr, "hax module version is too long to hold.\n");
}
fprintf(stderr, "Failed to get Hax module version:%lu\n", err);
return -EFAULT;
diff --git a/target/i386/kvm.c b/target/i386/kvm.c
index 9efb07e..fbdbb49 100644
--- a/target/i386/kvm.c
+++ b/target/i386/kvm.c
@@ -1179,7 +1179,7 @@ static int hv_cpuid_check_and_set(CPUState *cs, struct
kvm_cpuid2 *cpuid,
/*
* Fill in Hyper-V CPUIDs. Returns the number of entries filled in cpuid_ent in
* case of success, errno < 0 in case of failure and 0 when no Hyper-V
- * extentions are enabled.
+ * extensions are enabled.
*/
static int hyperv_handle_properties(CPUState *cs,
struct kvm_cpuid_entry2 *cpuid_ent)
diff --git a/target/i386/machine.c b/target/i386/machine.c
index b1acf7d..90e6139 100644
--- a/target/i386/machine.c
+++ b/target/i386/machine.c
@@ -264,12 +264,12 @@ static int cpu_pre_save(void *opaque)
* hypervisor, its exception payload (CR2/DR6 on #PF/#DB)
* should not be set yet in the respective vCPU register.
* Thus, in case an exception is pending, it is
- * important to save the exception payload seperately.
+ * important to save the exception payload separately.
*
* Therefore, if an exception is not in a pending state
* or vCPU is not in guest-mode, it is not important to
* distinguish between a pending and injected exception
- * and we don't need to store seperately the exception payload.
+ * and we don't need to store separately the exception payload.
*
* In order to preserve better backwards-compatible migration,
* convert a pending exception to an injected exception in
@@ -1138,7 +1138,7 @@ static int nested_state_post_load(void *opaque, int
version_id)
return -EINVAL;
}
if (nested_state->size > max_nested_state_len) {
-error_report("Recieved unsupported nested state size: "
+error_report("Received unsupported nested state size: "
"nested_state->size=%d, max=%d",
nested_state->size, max_nested_state_len);
return -EINVAL;
diff --git a/target/i386/translate.c b/target/i386/translate.c
index caea6f5..5cdfe0e 100644
--- a/target/i386/translate.c
+++ b/target/i386/translate.c
@@ -893,7 +893,7 @@ static CCPrepare gen_pre
[PATCH RFC 11/14] avr/: fix some comment spelling errors
I found that there are many spelling errors in the comments of qemu/target/avr.
I used spellcheck to check the spelling errors and found some errors in the
folder.
Signed-off-by: zhaolichang
---
target/avr/helper.c | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/target/avr/helper.c b/target/avr/helper.c
index d96d143..9f325bc 100644
--- a/target/avr/helper.c
+++ b/target/avr/helper.c
@@ -97,7 +97,7 @@ int avr_cpu_memory_rw_debug(CPUState *cs, vaddr addr, uint8_t
*buf,
hwaddr avr_cpu_get_phys_page_debug(CPUState *cs, vaddr addr)
{
-return addr; /* I assume 1:1 address correspondance */
+return addr; /* I assume 1:1 address correspondence */
}
bool avr_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
@@ -298,7 +298,7 @@ void helper_outb(CPUAVRState *env, uint32_t port, uint32_t
data)
}
/*
- * this function implements LD instruction when there is a posibility to read
+ * this function implements LD instruction when there is a possibility to read
* from a CPU register
*/
target_ulong helper_fullrd(CPUAVRState *env, uint32_t addr)
@@ -322,7 +322,7 @@ target_ulong helper_fullrd(CPUAVRState *env, uint32_t addr)
}
/*
- * this function implements ST instruction when there is a posibility to write
+ * this function implements ST instruction when there is a possibility to
write
* into a CPU register
*/
void helper_fullwr(CPUAVRState *env, uint32_t data, uint32_t addr)
--
2.26.2.windows.1
[PATCH RFC 13/14] alpha/: fix some comment spelling errors
I found that there are many spelling errors in the comments of
qemu/target/alpha.
I used spellcheck to check the spelling errors and found some errors in the
folder.
Signed-off-by: zhaolichang
---
target/alpha/cpu.h | 4 ++--
target/alpha/translate.c | 2 +-
2 files changed, 3 insertions(+), 3 deletions(-)
diff --git a/target/alpha/cpu.h b/target/alpha/cpu.h
index be29bdd..8a6d477 100644
--- a/target/alpha/cpu.h
+++ b/target/alpha/cpu.h
@@ -190,7 +190,7 @@ enum {
That said, we're only emulating Unix PALcode, and not attempting VMS,
so we don't need to implement Executive and Supervisor. QEMU's own
- PALcode cheats and usees the KSEG mapping for its code+data rather than
+ PALcode cheats and uses the KSEG mapping for its code+data rather than
physical addresses. */
#define MMU_KERNEL_IDX 0
@@ -370,7 +370,7 @@ enum {
The Unix PALcode only uses bit 4. */
#define PS_USER_MODE 8u
-/* CPUAlphaState->flags constants. These are layed out so that we
+/* CPUAlphaState->flags constants. These are laid out so that we
can set or reset the pieces individually by assigning to the byte,
or manipulated as a whole. */
diff --git a/target/alpha/translate.c b/target/alpha/translate.c
index 8870284..6aef9ec 100644
--- a/target/alpha/translate.c
+++ b/target/alpha/translate.c
@@ -2939,7 +2939,7 @@ static void alpha_tr_init_disas_context(DisasContextBase
*dcbase, CPUState *cpu)
the first fp insn of the TB. Alternately we could define a proper
default for every TB (e.g. QUAL_RM_N or QUAL_RM_D) and make sure
to reset the FP_STATUS to that default at the end of any TB that
- changes the default. We could even (gasp) dynamiclly figure out
+ changes the default. We could even (gasp) dynamically figure out
what default would be most efficient given the running program. */
ctx->tb_rm = -1;
/* Similarly for flush-to-zero. */
--
2.26.2.windows.1
[PATCH RFC 14/14] target/: fix some comment spelling errors
I found that there are many spelling errors in the comments of qemu/target.
I used spellcheck to check the spelling errors and found some errors in the
folder.
Signed-off-by: zhaolichang
---
target/openrisc/cpu.h| 2 +-
target/sparc/asi.h | 2 +-
target/unicore32/translate.c | 2 +-
3 files changed, 3 insertions(+), 3 deletions(-)
diff --git a/target/openrisc/cpu.h b/target/openrisc/cpu.h
index bd42faf..8ca8605 100644
--- a/target/openrisc/cpu.h
+++ b/target/openrisc/cpu.h
@@ -291,7 +291,7 @@ typedef struct CPUOpenRISCState {
int is_counting;
uint32_t picmr; /* Interrupt mask register */
-uint32_t picsr; /* Interrupt contrl register*/
+uint32_t picsr; /* Interrupt control register*/
#endif
void *irq[32]; /* Interrupt irq input */
} CPUOpenRISCState;
diff --git a/target/sparc/asi.h b/target/sparc/asi.h
index bb58735..4e9f1d5 100644
--- a/target/sparc/asi.h
+++ b/target/sparc/asi.h
@@ -231,7 +231,7 @@
#define ASI_INTR_ID0x63 /* (CMT) Interrupt ID register */
#define ASI_CORE_ID0x63 /* (CMT) LP ID register*/
#define ASI_CESR_ID0x63 /* (CMT) CESR ID register */
-#define ASI_IC_INSTR 0x66 /* Insn cache instrucion ram diag */
+#define ASI_IC_INSTR 0x66 /* Insn cache instruction ram diag */
#define ASI_IC_TAG 0x67 /* Insn cache tag/valid ram diag */
#define ASI_IC_STAG0x68 /* (III) Insn cache snoop tag ram */
#define ASI_IC_PRE_DECODE 0x6e /* Insn cache pre-decode ram diag */
diff --git a/target/unicore32/translate.c b/target/unicore32/translate.c
index d4b06df..2e91b05 100644
--- a/target/unicore32/translate.c
+++ b/target/unicore32/translate.c
@@ -119,7 +119,7 @@ static void load_reg_var(DisasContext *s, TCGv var, int reg)
{
if (reg == 31) {
uint32_t addr;
-/* normaly, since we updated PC */
+/* normally, since we updated PC */
addr = (long)s->pc;
tcg_gen_movi_i32(var, addr);
} else {
--
2.26.2.windows.1
[PATCH v3 1/3] target-i386: seperate MCIP & MCE_MASK error reason
Previously we can only get a simple string "Triple fault" in qemu
log. Add detailed message for the two reasons to describe why qemu
has to reset the guest.
Signed-off-by: zhenwei pi
---
target/i386/helper.c | 25 ++---
1 file changed, 18 insertions(+), 7 deletions(-)
diff --git a/target/i386/helper.c b/target/i386/helper.c
index 70be53e2c3..17e1684ff9 100644
--- a/target/i386/helper.c
+++ b/target/i386/helper.c
@@ -857,6 +857,8 @@ static void do_inject_x86_mce(CPUState *cs, run_on_cpu_data
data)
X86CPU *cpu = X86_CPU(cs);
CPUX86State *cenv = &cpu->env;
uint64_t *banks = cenv->mce_banks + 4 * params->bank;
+g_autofree char *msg = NULL;
+bool need_reset = false;
cpu_synchronize_state(cs);
@@ -894,16 +896,25 @@ static void do_inject_x86_mce(CPUState *cs,
run_on_cpu_data data)
return;
}
-if ((cenv->mcg_status & MCG_STATUS_MCIP) ||
-!(cenv->cr[4] & CR4_MCE_MASK)) {
-monitor_printf(params->mon,
- "CPU %d: Previous MCE still in progress, raising"
- " triple fault\n",
- cs->cpu_index);
-qemu_log_mask(CPU_LOG_RESET, "Triple fault\n");
+if (cenv->mcg_status & MCG_STATUS_MCIP) {
+need_reset = true;
+msg = g_strdup_printf("CPU %d: Previous MCE still in progress, "
+ "raising triple fault", cs->cpu_index);
+}
+
+if (!(cenv->cr[4] & CR4_MCE_MASK)) {
+need_reset = true;
+msg = g_strdup_printf("CPU %d: MCE capability is not enabled, "
+ "raising triple fault", cs->cpu_index);
+}
+
+if (need_reset) {
+monitor_printf(params->mon, "%s", msg);
+qemu_log_mask(CPU_LOG_RESET, "%s\n", msg);
qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST_RESET);
return;
}
+
if (banks[1] & MCI_STATUS_VAL) {
params->status |= MCI_STATUS_OVER;
}
--
2.11.0
[PATCH v3 2/3] qapi/run-state.json: introduce memory failure event
Introduce memory failure events for hyperviso/guest . Then uplayer
could know when/why/what happened during hitting a hardware memory
failure.
Suggested by Peter Maydell, rename events name&description to make
them architecture-neutral; and suggested by Paolo, add more info to
distinguish a mce is AR/AO, previous mce is still processing in
guest or not.
Signed-off-by: zhenwei pi
---
qapi/run-state.json | 85 +
1 file changed, 85 insertions(+)
diff --git a/qapi/run-state.json b/qapi/run-state.json
index 7cc9f96a5b..d795dc21fc 100644
--- a/qapi/run-state.json
+++ b/qapi/run-state.json
@@ -475,3 +475,88 @@
'psw-mask': 'uint64',
'psw-addr': 'uint64',
'reason': 'S390CrashReason' } }
+
+##
+# @MEMORY_FAILURE:
+#
+# Emitted when a memory failure occurs on host side.
+#
+# @recipient: recipient is defined as @MemoryFailureRecipient.
+#
+# @action: action that has been taken. action is defined as
@MemoryFailureAction.
+#
+# @flags: flags for MemoryFailureAction. action is defined as
@MemoryFailureFlags.
+#
+# Since: 5.2
+#
+# Example:
+#
+# <- { "event": "MEMORY_FAILURE",
+# "data": { "action": "guest-mce" } }
+#
+##
+{ 'event': 'MEMORY_FAILURE',
+ 'data': { 'recipient': 'MemoryFailureRecipient',
+'action': 'MemoryFailureAction',
+'flags': 'MemoryFailureFlags'} }
+
+##
+# @MemoryFailureRecipient:
+#
+# Hardware memory failure occurs, handled by recipient.
+#
+# @hypervisor: memory failure at QEMU process address space.
+# (none guest memory, but used by QEMU itself).
+#
+# @guest: memory failure at guest memory,
+#
+# Since: 5.2
+#
+##
+{ 'enum': 'MemoryFailureRecipient',
+ 'data': [ 'hypervisor',
+'guest' ] }
+
+
+##
+# @MemoryFailureAction:
+#
+# Hardware memory failure occurs, action by QEMU.
+#
+# @ignore: action optional memory failure which could be ignored.
+#
+# @inject: memory failure at guest memory, and guest enables MCE handling
+# mechanism, QEMU injects MCE to guest successfully.
+#
+# @fatal: action required memory failure occurs. If recipient is hypervior,
QEMU
+# hits a fatal error and exits later. And if recipient is guest, QEMU
+# tries to inject MCE to guest, but guest is not ready to handle MCE
+# (typical cases: guest has no MCE mechanism, or guest disables MCE,
+# or during previous MCE still in processing, an AR MCE occurs). QEMU
+# has to raise a fault and shutdown/reset. Also see detailed info in
+# QEMU log.
+#
+# Since: 5.2
+#
+##
+{ 'enum': 'MemoryFailureAction',
+ 'data': [ 'ignore',
+'inject',
+'fatal' ] }
+
+##
+# @MemoryFailureFlags:
+#
+# Structure of flags for each memory failure event.
+#
+# @action-required: describe a MCE event as AR/AO.
+#
+# @recursive: previous MCE in processing in guest, another AO MCE
+# occurs, set recursive as true.
+#
+# Since: 5.2
+#
+##
+{ 'struct': 'MemoryFailureFlags',
+ 'data': { 'action-required': 'bool',
+'recursive': 'bool'} }
--
2.11.0
[PATCH v3 0/3] add MEMORY_FAILURE event
v2->v3: Use g_strdup_printf instead of snprintf. Declear memory failure event as 3 parts: 'recipient', 'action', 'flags'. Wrapper function emit_guest_memory_failure&emit_hypervisor_memory_failure. v1->v2: Suggested by Peter Maydell, rename events to make them architecture-neutral: 'PC-RAM' -> 'guest-memory' 'guest-triple-fault' -> 'guest-mce-fatal' Suggested by Paolo, add more fields in event: 'action-required': boolean type to distinguish a guest-mce is AR/AO. 'recursive': boolean type. set true if: previous MCE in processing in guest, another AO MCE occurs. v1: Although QEMU could catch signal BUS to handle hardware memory corrupted event, sadly, QEMU just prints a little log and try to fix it silently. In these patches, introduce a 'MEMORY_FAILURE' event with 4 detailed actions of QEMU, then uplayer could know what situaction QEMU hit and did. And further step we can do: if a host server hits a 'hypervisor-ignore' or 'guest-mce', scheduler could migrate VM to another host; if hitting 'hypervisor-stop' or 'guest-triple-fault', scheduler could select other healthy servers to launch VM. Zhenwei Pi (3): target-i386: seperate MCIP & MCE_MASK error reason qapi/run-state.json: introduce memory failure event target-i386: post memory failure event to uplayer qapi/run-state.json | 85 target/i386/helper.c | 47 ++--- target/i386/kvm.c| 13 +++- 3 files changed, 134 insertions(+), 11 deletions(-) -- 2.11.0
Re: [PATCH] hw/arm/aspeed: Map the UART5 device unconditionally
On 9/30/20 7:29 AM, Andrew Jeffery wrote: > > > On Fri, 18 Sep 2020, at 02:33, Cédric Le Goater wrote: >> On 9/17/20 6:57 PM, Philippe Mathieu-Daudé wrote: >>> On 9/16/20 7:51 AM, Cédric Le Goater wrote: On 9/15/20 7:23 PM, Philippe Mathieu-Daudé wrote: > ping? It's reviewed : http://patchwork.ozlabs.org/project/qemu-devel/patch/20200905212415.760452-1-f4...@amsat.org/ >>> >>> Yes I know :) This is part of my routine to check if a >>> patch hasn't been confirmed to be queued 1 week after the >>> last review, to ping the maintainer (because some >>> automatically flush patches older than 1month in their >>> mailbox). >> >> ooh. That's brutal. >> I will send a PR when I have more patches. >>> >>> Ah OK. I didn't know you would keep merging the Aspeed >>> patches. Since this was a single patch, I thought it would >>> go via the usual qemu-arm queue from Peter. >> >> sure. It could also. Fine with me. I have only three for the >> moment. >> >>> No rush, I just wanted to be sure the patch was not lost. >>> Also, once a patch is queued, I understand it is the >>> maintainer responsibility to keep rebasing the patch >>> queued. >> >> yes. I know. I have been taking care of Andrew's ADC patches >> since 2017 ... cough cough :) > > Agh! Does that mean "I will work on it !" ? :) C.
[PATCH v3 3/3] target-i386: post memory failure event to uplayer
Post memory failure event to uplayer to handle hardware memory
corrupted event. Rather than simple QEMU log, QEMU could report more
effective message to uplayer. For example, guest crashes by MCE,
selecting another host server is a better choice.
Signed-off-by: zhenwei pi
---
target/i386/helper.c | 24
target/i386/kvm.c| 13 -
2 files changed, 32 insertions(+), 5 deletions(-)
diff --git a/target/i386/helper.c b/target/i386/helper.c
index 17e1684ff9..2a184c4835 100644
--- a/target/i386/helper.c
+++ b/target/i386/helper.c
@@ -18,6 +18,7 @@
*/
#include "qemu/osdep.h"
+#include "qapi/qapi-events-run-state.h"
#include "cpu.h"
#include "exec/exec-all.h"
#include "qemu/qemu-print.h"
@@ -851,6 +852,15 @@ typedef struct MCEInjectionParams {
int flags;
} MCEInjectionParams;
+static void emit_guest_memory_failure(MemoryFailureAction action, bool ar,
+ bool recursive)
+{
+MemoryFailureFlags mff = {.action_required = ar, .recursive = recursive};
+
+qapi_event_send_memory_failure(MEMORY_FAILURE_RECIPIENT_GUEST, action,
+ &mff);
+}
+
static void do_inject_x86_mce(CPUState *cs, run_on_cpu_data data)
{
MCEInjectionParams *params = data.host_ptr;
@@ -859,16 +869,18 @@ static void do_inject_x86_mce(CPUState *cs,
run_on_cpu_data data)
uint64_t *banks = cenv->mce_banks + 4 * params->bank;
g_autofree char *msg = NULL;
bool need_reset = false;
+bool recursive;
+bool ar = !!(params->status & MCI_STATUS_AR);
cpu_synchronize_state(cs);
+recursive = !!(cenv->mcg_status & MCG_STATUS_MCIP);
/*
* If there is an MCE exception being processed, ignore this SRAO MCE
* unless unconditional injection was requested.
*/
-if (!(params->flags & MCE_INJECT_UNCOND_AO)
-&& !(params->status & MCI_STATUS_AR)
-&& (cenv->mcg_status & MCG_STATUS_MCIP)) {
+if (!(params->flags & MCE_INJECT_UNCOND_AO) && !ar && recursive) {
+emit_guest_memory_failure(MEMORY_FAILURE_ACTION_IGNORE, ar, recursive);
return;
}
@@ -896,7 +908,7 @@ static void do_inject_x86_mce(CPUState *cs, run_on_cpu_data
data)
return;
}
-if (cenv->mcg_status & MCG_STATUS_MCIP) {
+if (recursive) {
need_reset = true;
msg = g_strdup_printf("CPU %d: Previous MCE still in progress, "
"raising triple fault", cs->cpu_index);
@@ -909,6 +921,8 @@ static void do_inject_x86_mce(CPUState *cs, run_on_cpu_data
data)
}
if (need_reset) {
+emit_guest_memory_failure(MEMORY_FAILURE_ACTION_FATAL, ar,
+ recursive);
monitor_printf(params->mon, "%s", msg);
qemu_log_mask(CPU_LOG_RESET, "%s\n", msg);
qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST_RESET);
@@ -934,6 +948,8 @@ static void do_inject_x86_mce(CPUState *cs, run_on_cpu_data
data)
} else {
banks[1] |= MCI_STATUS_OVER;
}
+
+emit_guest_memory_failure(MEMORY_FAILURE_ACTION_INJECT, ar, recursive);
}
void cpu_x86_inject_mce(Monitor *mon, X86CPU *cpu, int bank,
diff --git a/target/i386/kvm.c b/target/i386/kvm.c
index 9efb07e7c8..923749f5d8 100644
--- a/target/i386/kvm.c
+++ b/target/i386/kvm.c
@@ -13,6 +13,7 @@
*/
#include "qemu/osdep.h"
+#include "qapi/qapi-events-run-state.h"
#include "qapi/error.h"
#include
#include
@@ -575,8 +576,17 @@ static void kvm_mce_inject(X86CPU *cpu, hwaddr paddr, int
code)
(MCM_ADDR_PHYS << 6) | 0xc, flags);
}
+static void emit_hypervisor_memory_failure(MemoryFailureAction action, bool ar)
+{
+MemoryFailureFlags mff = {.action_required = ar, .recursive = false};
+
+qapi_event_send_memory_failure(MEMORY_FAILURE_RECIPIENT_HYPERVISOR, action,
+ &mff);
+}
+
static void hardware_memory_error(void *host_addr)
{
+emit_hypervisor_memory_failure(MEMORY_FAILURE_ACTION_FATAL, true);
error_report("QEMU got Hardware memory error at addr %p", host_addr);
exit(1);
}
@@ -631,7 +641,8 @@ void kvm_arch_on_sigbus_vcpu(CPUState *c, int code, void
*addr)
hardware_memory_error(addr);
}
-/* Hope we are lucky for AO MCE */
+/* Hope we are lucky for AO MCE, just notify a event */
+emit_hypervisor_memory_failure(MEMORY_FAILURE_ACTION_IGNORE, false);
}
static void kvm_reset_exception(CPUX86State *env)
--
2.11.0
[PULL 01/17] util/vfio-helpers: Pass page protections to qemu_vfio_pci_map_bar()
From: Philippe Mathieu-Daudé
Pages are currently mapped READ/WRITE. To be able to use different
protections, add a new argument to qemu_vfio_pci_map_bar().
Signed-off-by: Philippe Mathieu-Daudé
Signed-off-by: Stefan Hajnoczi
Message-Id: <20200922083821.578519-2-phi...@redhat.com>
---
include/qemu/vfio-helpers.h | 2 +-
block/nvme.c| 3 ++-
util/vfio-helpers.c | 4 ++--
3 files changed, 5 insertions(+), 4 deletions(-)
diff --git a/include/qemu/vfio-helpers.h b/include/qemu/vfio-helpers.h
index 1f057c2b9e..4491c8e1a6 100644
--- a/include/qemu/vfio-helpers.h
+++ b/include/qemu/vfio-helpers.h
@@ -22,7 +22,7 @@ int qemu_vfio_dma_map(QEMUVFIOState *s, void *host, size_t
size,
int qemu_vfio_dma_reset_temporary(QEMUVFIOState *s);
void qemu_vfio_dma_unmap(QEMUVFIOState *s, void *host);
void *qemu_vfio_pci_map_bar(QEMUVFIOState *s, int index,
-uint64_t offset, uint64_t size,
+uint64_t offset, uint64_t size, int prot,
Error **errp);
void qemu_vfio_pci_unmap_bar(QEMUVFIOState *s, int index, void *bar,
uint64_t offset, uint64_t size);
diff --git a/block/nvme.c b/block/nvme.c
index f4f27b6da7..5a4dc6a722 100644
--- a/block/nvme.c
+++ b/block/nvme.c
@@ -712,7 +712,8 @@ static int nvme_init(BlockDriverState *bs, const char
*device, int namespace,
goto out;
}
-s->regs = qemu_vfio_pci_map_bar(s->vfio, 0, 0, NVME_BAR_SIZE, errp);
+s->regs = qemu_vfio_pci_map_bar(s->vfio, 0, 0, NVME_BAR_SIZE,
+PROT_READ | PROT_WRITE, errp);
if (!s->regs) {
ret = -EINVAL;
goto out;
diff --git a/util/vfio-helpers.c b/util/vfio-helpers.c
index 583bdfb36f..9ac307e3d4 100644
--- a/util/vfio-helpers.c
+++ b/util/vfio-helpers.c
@@ -146,13 +146,13 @@ static int qemu_vfio_pci_init_bar(QEMUVFIOState *s, int
index, Error **errp)
* Map a PCI bar area.
*/
void *qemu_vfio_pci_map_bar(QEMUVFIOState *s, int index,
-uint64_t offset, uint64_t size,
+uint64_t offset, uint64_t size, int prot,
Error **errp)
{
void *p;
assert_bar_index_valid(s, index);
p = mmap(NULL, MIN(size, s->bar_region_info[index].size - offset),
- PROT_READ | PROT_WRITE, MAP_SHARED,
+ prot, MAP_SHARED,
s->device, s->bar_region_info[index].offset + offset);
if (p == MAP_FAILED) {
error_setg_errno(errp, errno, "Failed to map BAR region");
--
2.26.2
[PULL 00/17] Block patches
The following changes since commit b150cb8f67bf491a49a1cb1c7da151eeacbdbcc9: Merge remote-tracking branch 'remotes/mst/tags/for_upstream' into staging (2020-09-29 13:18:54 +0100) are available in the Git repository at: https://gitlab.com/stefanha/qemu.git tags/block-pull-request for you to fetch changes up to bc47831ff28d6f5830c9c8d74220131dc54c5253: util/vfio-helpers: Rework the IOVA allocator to avoid IOVA reserved regions (2020-09-30 10:23:05 +0100) Pull request Note I have switched from GitHub to GitLab. Eric Auger (2): util/vfio-helpers: Collect IOVA reserved regions util/vfio-helpers: Rework the IOVA allocator to avoid IOVA reserved regions Philippe Mathieu-Daudé (6): util/vfio-helpers: Pass page protections to qemu_vfio_pci_map_bar() block/nvme: Map doorbells pages write-only block/nvme: Reduce I/O registers scope block/nvme: Drop NVMeRegs structure, directly use NvmeBar block/nvme: Use register definitions from 'block/nvme.h' block/nvme: Replace magic value by SCALE_MS definition Stefano Garzarella (1): docs: add 'io_uring' option to 'aio' param in qemu-options.hx Vladimir Sementsov-Ogievskiy (8): block: return error-code from bdrv_invalidate_cache block/io: refactor coroutine wrappers block: declare some coroutine functions in block/coroutines.h scripts: add block-coroutine-wrapper.py block: generate coroutine-wrapper code block: drop bdrv_prwv block/io: refactor save/load vmstate include/block/block.h: drop non-ascii quotation mark block/block-gen.h | 49 block/coroutines.h | 65 + include/block/block.h | 36 ++- include/qemu/vfio-helpers.h| 2 +- block.c| 97 +-- block/io.c | 339 - block/nvme.c | 73 +++--- tests/test-bdrv-drain.c| 2 +- util/vfio-helpers.c| 133 +- block/meson.build | 8 + docs/devel/block-coroutine-wrapper.rst | 54 docs/devel/index.rst | 1 + qemu-options.hx| 10 +- scripts/block-coroutine-wrapper.py | 188 ++ 14 files changed, 629 insertions(+), 428 deletions(-) create mode 100644 block/block-gen.h create mode 100644 block/coroutines.h create mode 100644 docs/devel/block-coroutine-wrapper.rst create mode 100644 scripts/block-coroutine-wrapper.py -- 2.26.2
Re: [PATCH 16/16] tests/acceptance: Test the MIPSsim machine
On 9/30/20 11:49 AM, Alex Bennée wrote:
>
> Daniel P. Berrangé writes:
>
>> On Tue, Sep 29, 2020 at 10:38:30AM +0100, Alex Bennée wrote:
>>>
>>> Philippe Mathieu-Daudé writes:
>>>
+Alex/Daniel
On 9/28/20 10:33 PM, Willian Rampazzo wrote:
> On Mon, Sep 28, 2020 at 2:31 PM Philippe Mathieu-Daudé
> wrote:
>>
>> Add a test for the mipssim machine, based on the recommended
>> test setup from Thomas Huth:
>> https://www.mail-archive.com/qemu-devel@nongnu.org/msg606846.html
>>
>> The test is quick and can be run as:
>>
>> $ avocado --show=console run -t machine:mipssim tests/acceptance/
>>(1/1)
>> tests/acceptance/machine_mips_mipssim.py:MipsSimMachine.test_mipssim_linux_console:
>> console: Linux version 3.6.11 (root@711bb8ba16a7) (gcc version 4.8.3
>> (Buildroot 2014.11) ) #2 Sun Sep 27 13:39:35 UTC 2020
>> console: Setting default memory size 0x0200
>> console: bootconsole [early0] enabled
>> console: CPU revision is: 00019300 (MIPS 24Kc)
>> console: FPU revision is: 00739300
>> ...
>> console: CPU frequency 12.00 MHz
>> console: Calibrating delay loop... 950.27 BogoMIPS (lpj=4751360)
>> ...
>> console: MIPSNet Ethernet driver. Version: 2007-11-17. (c)2005 MIPS
>> Technologies, Inc.
>> ...
>> console: Welcome to Buildroot
>> console: buildroot login: root
>> console: # root
>> console: -sh: root: not found
>> console: # ping -c 3 10.0.2.2
>> console: PING 10.0.2.2 (10.0.2.2): 56 data bytes
>> console: 64 bytes from 10.0.2.2: seq=0 ttl=255 time=48.231 ms
>> console: 64 bytes from 10.0.2.2: seq=1 ttl=255 time=9.407 ms
>> console: 64 bytes from 10.0.2.2: seq=2 ttl=255 time=2.298 ms
>> console: --- 10.0.2.2 ping statistics ---
>> console: 3 packets transmitted, 3 packets received, 0% packet loss
>> PASS (7.99 s)
>>
>> Signed-off-by: Philippe Mathieu-Daudé
>> ---
>> Cc: Thomas Huth
>> ---
>> MAINTAINERS | 1 +
>> tests/acceptance/machine_mips_mipssim.py | 56
>> 2 files changed, 57 insertions(+)
>> create mode 100644 tests/acceptance/machine_mips_mipssim.py
>>
>> diff --git a/MAINTAINERS b/MAINTAINERS
>> index 5eed1e692b4..17d8a012b0e 100644
>> --- a/MAINTAINERS
>> +++ b/MAINTAINERS
>> @@ -240,6 +240,7 @@ F: include/hw/misc/mips_*
>> F: include/hw/timer/mips_gictimer.h
>> F: tests/acceptance/linux_ssh_mips_malta.py
>> F: tests/acceptance/machine_mips_malta.py
>> +F: tests/acceptance/machine_mips_mipssim.py
>> F: tests/tcg/mips/
>> K: ^Subject:.*(?i)mips
>>
>> diff --git a/tests/acceptance/machine_mips_mipssim.py
>> b/tests/acceptance/machine_mips_mipssim.py
>> new file mode 100644
>> index 000..b2749917b08
>> --- /dev/null
>> +++ b/tests/acceptance/machine_mips_mipssim.py
>> @@ -0,0 +1,56 @@
>> +# Functional tests for the MIPS simulator (MIPSsim machine)
>> +#
>> +# Copyright (c) 2020 Philippe Mathieu-Daudé
>> +#
>> +# This work is licensed under the terms of the GNU GPL, version 2 or
>> later.
>> +# See the COPYING file in the top-level directory.
>> +#
>> +# SPDX-License-Identifier: GPL-2.0-or-later
>> +
>> +import os
>> +import logging
>> +import time
>> +
>> +from avocado import skipUnless
>> +from avocado_qemu import Test
>> +from avocado_qemu import exec_command_and_wait_for_pattern
>> +from avocado_qemu import interrupt_interactive_console_until_pattern
>> +from avocado_qemu import wait_for_console_pattern
>> +
>> +class MipsSimMachine(Test):
>> +
>> +timeout = 30
>> +KERNEL_COMMON_COMMAND_LINE = 'printk.time=0 '
>> +
>> +@skipUnless(os.getenv('AVOCADO_ALLOW_UNTRUSTED_CODE'), 'untrusted
>> code')
>> +def test_mipssim_linux_console(self):
>> +"""
>> +Boots the Linux kernel and checks that the console is
>> operational
>> +:avocado: tags=arch:mipsel
>> +:avocado: tags=machine:mipssim
>> +:avocado: tags=device:mipsnet
>> +"""
>> +kernel_url = ('https://github.com/philmd/qemu-testing-blob/raw/'
>> + '32ea5764e1de8fffa0d59366c44822cd06d7c8e0/'
>> + 'mips/mipssim/mipsel/vmlinux')
>
> So, are you willing to maintain some images on your GitHub to avoid
> the image changes when they are not found?
No, I am not willing to do that.
But I see it pointless to have everyone (including CI) to spend 1h
building this image, when the sources and build recipe is available,
making the built image reproducible.
>>>
>>> I agree we don't want to build from scratch each time. However as we
>>> move from relying on th
[PULL 04/17] block/nvme: Drop NVMeRegs structure, directly use NvmeBar
From: Philippe Mathieu-Daudé
NVMeRegs only contains NvmeBar. Simplify the code by using NvmeBar
directly.
This triggers a checkpatch.pl error:
ERROR: Use of volatile is usually wrong, please add a comment
#30: FILE: block/nvme.c:691:
+volatile NvmeBar *regs;
This is a false positive as in our case we are using I/O registers,
so the 'volatile' use is justified.
Signed-off-by: Philippe Mathieu-Daudé
Signed-off-by: Stefan Hajnoczi
Message-Id: <20200922083821.578519-5-phi...@redhat.com>
---
block/nvme.c | 23 +--
1 file changed, 9 insertions(+), 14 deletions(-)
diff --git a/block/nvme.c b/block/nvme.c
index e517c7539f..bd82990b66 100644
--- a/block/nvme.c
+++ b/block/nvme.c
@@ -81,11 +81,6 @@ typedef struct {
QEMUBH *completion_bh;
} NVMeQueuePair;
-/* Memory mapped registers */
-typedef volatile struct {
-NvmeBar ctrl;
-} NVMeRegs;
-
#define INDEX_ADMIN 0
#define INDEX_IO(n) (1 + n)
@@ -694,7 +689,7 @@ static int nvme_init(BlockDriverState *bs, const char
*device, int namespace,
uint64_t timeout_ms;
uint64_t deadline, now;
Error *local_err = NULL;
-NVMeRegs *regs;
+volatile NvmeBar *regs = NULL;
qemu_co_mutex_init(&s->dma_map_lock);
qemu_co_queue_init(&s->dma_flush_queue);
@@ -722,7 +717,7 @@ static int nvme_init(BlockDriverState *bs, const char
*device, int namespace,
/* Perform initialize sequence as described in NVMe spec "7.6.1
* Initialization". */
-cap = le64_to_cpu(regs->ctrl.cap);
+cap = le64_to_cpu(regs->cap);
if (!(cap & (1ULL << 37))) {
error_setg(errp, "Device doesn't support NVMe command set");
ret = -EINVAL;
@@ -735,10 +730,10 @@ static int nvme_init(BlockDriverState *bs, const char
*device, int namespace,
timeout_ms = MIN(500 * ((cap >> 24) & 0xFF), 3);
/* Reset device to get a clean state. */
-regs->ctrl.cc = cpu_to_le32(le32_to_cpu(regs->ctrl.cc) & 0xFE);
+regs->cc = cpu_to_le32(le32_to_cpu(regs->cc) & 0xFE);
/* Wait for CSTS.RDY = 0. */
deadline = qemu_clock_get_ns(QEMU_CLOCK_REALTIME) + timeout_ms * SCALE_MS;
-while (le32_to_cpu(regs->ctrl.csts) & 0x1) {
+while (le32_to_cpu(regs->csts) & 0x1) {
if (qemu_clock_get_ns(QEMU_CLOCK_REALTIME) > deadline) {
error_setg(errp, "Timeout while waiting for device to reset (%"
PRId64 " ms)",
@@ -766,18 +761,18 @@ static int nvme_init(BlockDriverState *bs, const char
*device, int namespace,
}
s->nr_queues = 1;
QEMU_BUILD_BUG_ON(NVME_QUEUE_SIZE & 0xF000);
-regs->ctrl.aqa = cpu_to_le32((NVME_QUEUE_SIZE << 16) | NVME_QUEUE_SIZE);
-regs->ctrl.asq = cpu_to_le64(s->queues[INDEX_ADMIN]->sq.iova);
-regs->ctrl.acq = cpu_to_le64(s->queues[INDEX_ADMIN]->cq.iova);
+regs->aqa = cpu_to_le32((NVME_QUEUE_SIZE << 16) | NVME_QUEUE_SIZE);
+regs->asq = cpu_to_le64(s->queues[INDEX_ADMIN]->sq.iova);
+regs->acq = cpu_to_le64(s->queues[INDEX_ADMIN]->cq.iova);
/* After setting up all control registers we can enable device now. */
-regs->ctrl.cc = cpu_to_le32((ctz32(NVME_CQ_ENTRY_BYTES) << 20) |
+regs->cc = cpu_to_le32((ctz32(NVME_CQ_ENTRY_BYTES) << 20) |
(ctz32(NVME_SQ_ENTRY_BYTES) << 16) |
0x1);
/* Wait for CSTS.RDY = 1. */
now = qemu_clock_get_ns(QEMU_CLOCK_REALTIME);
deadline = now + timeout_ms * 100;
-while (!(le32_to_cpu(regs->ctrl.csts) & 0x1)) {
+while (!(le32_to_cpu(regs->csts) & 0x1)) {
if (qemu_clock_get_ns(QEMU_CLOCK_REALTIME) > deadline) {
error_setg(errp, "Timeout while waiting for device to start (%"
PRId64 " ms)",
--
2.26.2
Re: [PATCH 00/16] hw/mips: Set CPU frequency
On 9/30/20 9:40 AM, Igor Mammedov wrote: > On Mon, 28 Sep 2020 19:15:23 +0200 > Philippe Mathieu-Daudé wrote: > >> All the MIPS cores emulated by QEMU provides the Coproc#0 >> 'Count' register which can be used as a free running timer. >> >> Since it's introduction in 2005 this timer uses a fixed >> frequency of 100 MHz (for a CPU freq of 200 MHz). >> While this is not an issue with Linux guests, it makes >> some firmwares behave incorrectly. >> >> The Clock API allow propagating clocks. It is particularly >> useful when hardware dynamicly changes clock frequencies. >> >> To be able to model such MIPS hardware, we need to refactor >> the MIPS hardware code to handle clocks. >> >> This series is organized as follow: >> >> - let all CPU have an input clock, >> - MIPS CPU get an input clock >> - when the clock is changed, CP0 timer is updated >> - set correct CPU frequencies to all boards >> - do not allow MIPS CPU without input clock > > is this clock an integral part of MIPS cpus or it's an external device? CPU cores are clocked via an external clock. This clock can be on the board (from a crystal oscillator to complex PLL) or on-chip for some system-on-chip. In all the (current) QEMU MIPS machines it is external although. Regards, Phil.
[PULL 02/17] block/nvme: Map doorbells pages write-only
From: Philippe Mathieu-Daudé
Per the datasheet sections 3.1.13/3.1.14:
"The host should not read the doorbell registers."
As we don't need read access, map the doorbells with write-only
permission. We keep a reference to this mapped address in the
BDRVNVMeState structure.
Signed-off-by: Philippe Mathieu-Daudé
Signed-off-by: Stefan Hajnoczi
Message-Id: <20200922083821.578519-3-phi...@redhat.com>
---
block/nvme.c | 29 +++--
1 file changed, 19 insertions(+), 10 deletions(-)
diff --git a/block/nvme.c b/block/nvme.c
index 5a4dc6a722..3c834da8fe 100644
--- a/block/nvme.c
+++ b/block/nvme.c
@@ -31,7 +31,7 @@
#define NVME_SQ_ENTRY_BYTES 64
#define NVME_CQ_ENTRY_BYTES 16
#define NVME_QUEUE_SIZE 128
-#define NVME_BAR_SIZE 8192
+#define NVME_DOORBELL_SIZE 4096
/*
* We have to leave one slot empty as that is the full queue case where
@@ -84,10 +84,6 @@ typedef struct {
/* Memory mapped registers */
typedef volatile struct {
NvmeBar ctrl;
-struct {
-uint32_t sq_tail;
-uint32_t cq_head;
-} doorbells[];
} NVMeRegs;
#define INDEX_ADMIN 0
@@ -103,6 +99,11 @@ struct BDRVNVMeState {
AioContext *aio_context;
QEMUVFIOState *vfio;
NVMeRegs *regs;
+/* Memory mapped registers */
+volatile struct {
+uint32_t sq_tail;
+uint32_t cq_head;
+} *doorbells;
/* The submission/completion queue pairs.
* [0]: admin queue.
* [1..]: io queues.
@@ -247,14 +248,14 @@ static NVMeQueuePair
*nvme_create_queue_pair(BDRVNVMeState *s,
error_propagate(errp, local_err);
goto fail;
}
-q->sq.doorbell = &s->regs->doorbells[idx * s->doorbell_scale].sq_tail;
+q->sq.doorbell = &s->doorbells[idx * s->doorbell_scale].sq_tail;
nvme_init_queue(s, &q->cq, size, NVME_CQ_ENTRY_BYTES, &local_err);
if (local_err) {
error_propagate(errp, local_err);
goto fail;
}
-q->cq.doorbell = &s->regs->doorbells[idx * s->doorbell_scale].cq_head;
+q->cq.doorbell = &s->doorbells[idx * s->doorbell_scale].cq_head;
return q;
fail:
@@ -712,13 +713,12 @@ static int nvme_init(BlockDriverState *bs, const char
*device, int namespace,
goto out;
}
-s->regs = qemu_vfio_pci_map_bar(s->vfio, 0, 0, NVME_BAR_SIZE,
+s->regs = qemu_vfio_pci_map_bar(s->vfio, 0, 0, sizeof(NvmeBar),
PROT_READ | PROT_WRITE, errp);
if (!s->regs) {
ret = -EINVAL;
goto out;
}
-
/* Perform initialize sequence as described in NVMe spec "7.6.1
* Initialization". */
@@ -748,6 +748,13 @@ static int nvme_init(BlockDriverState *bs, const char
*device, int namespace,
}
}
+s->doorbells = qemu_vfio_pci_map_bar(s->vfio, 0, sizeof(NvmeBar),
+ NVME_DOORBELL_SIZE, PROT_WRITE, errp);
+if (!s->doorbells) {
+ret = -EINVAL;
+goto out;
+}
+
/* Set up admin queue. */
s->queues = g_new(NVMeQueuePair *, 1);
s->queues[INDEX_ADMIN] = nvme_create_queue_pair(s, aio_context, 0,
@@ -873,7 +880,9 @@ static void nvme_close(BlockDriverState *bs)
&s->irq_notifier[MSIX_SHARED_IRQ_IDX],
false, NULL, NULL);
event_notifier_cleanup(&s->irq_notifier[MSIX_SHARED_IRQ_IDX]);
-qemu_vfio_pci_unmap_bar(s->vfio, 0, (void *)s->regs, 0, NVME_BAR_SIZE);
+qemu_vfio_pci_unmap_bar(s->vfio, 0, (void *)s->doorbells,
+sizeof(NvmeBar), NVME_DOORBELL_SIZE);
+qemu_vfio_pci_unmap_bar(s->vfio, 0, (void *)s->regs, 0, sizeof(NvmeBar));
qemu_vfio_close(s->vfio);
g_free(s->device);
--
2.26.2
[PULL 06/17] block/nvme: Replace magic value by SCALE_MS definition
From: Philippe Mathieu-Daudé
Use self-explicit SCALE_MS definition instead of magic value
(missed in similar commit e4f310fe7f5).
Signed-off-by: Philippe Mathieu-Daudé
Signed-off-by: Stefan Hajnoczi
Message-Id: <20200922083821.578519-7-phi...@redhat.com>
---
block/nvme.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/block/nvme.c b/block/nvme.c
index 959569d262..b48f6f2588 100644
--- a/block/nvme.c
+++ b/block/nvme.c
@@ -772,7 +772,7 @@ static int nvme_init(BlockDriverState *bs, const char
*device, int namespace,
CC_EN_MASK);
/* Wait for CSTS.RDY = 1. */
now = qemu_clock_get_ns(QEMU_CLOCK_REALTIME);
-deadline = now + timeout_ms * 100;
+deadline = now + timeout_ms * SCALE_MS;
while (!NVME_CSTS_RDY(le32_to_cpu(regs->csts))) {
if (qemu_clock_get_ns(QEMU_CLOCK_REALTIME) > deadline) {
error_setg(errp, "Timeout while waiting for device to start (%"
--
2.26.2
[PULL 10/17] scripts: add block-coroutine-wrapper.py
From: Vladimir Sementsov-Ogievskiy
We have a very frequent pattern of creating a coroutine from a function
with several arguments:
- create a structure to pack parameters
- create _entry function to call original function taking parameters
from struct
- do different magic to handle completion: set ret to NOT_DONE or
EINPROGRESS or use separate bool field
- fill the struct and create coroutine from _entry function with this
struct as a parameter
- do coroutine enter and BDRV_POLL_WHILE loop
Let's reduce code duplication by generating coroutine wrappers.
This patch adds scripts/block-coroutine-wrapper.py together with some
friends, which will generate functions with declared prototypes marked
by the 'generated_co_wrapper' specifier.
The usage of new code generation is as follows:
1. define the coroutine function somewhere
int coroutine_fn bdrv_co_NAME(...) {...}
2. declare in some header file
int generated_co_wrapper bdrv_NAME(...);
with same list of parameters (generated_co_wrapper is
defined in "include/block/block.h").
3. Make sure the block_gen_c declaration in block/meson.build
mentions the file with your marker function.
Still, no function is now marked, this work is for the following
commit.
Signed-off-by: Vladimir Sementsov-Ogievskiy
Reviewed-by: Eric Blake
Message-Id: <20200924185414.28642-5-vsement...@virtuozzo.com>
[Added encoding='utf-8' to open() calls as requested by Vladimir. Fixed
typo and grammar issues pointed out by Eric Blake.
--Stefan]
Signed-off-by: Stefan Hajnoczi
---
block/block-gen.h | 49 +++
include/block/block.h | 10 ++
block/meson.build | 8 ++
docs/devel/block-coroutine-wrapper.rst | 54 +++
docs/devel/index.rst | 1 +
scripts/block-coroutine-wrapper.py | 188 +
6 files changed, 310 insertions(+)
create mode 100644 block/block-gen.h
create mode 100644 docs/devel/block-coroutine-wrapper.rst
create mode 100644 scripts/block-coroutine-wrapper.py
diff --git a/block/block-gen.h b/block/block-gen.h
new file mode 100644
index 00..f80cf4897d
--- /dev/null
+++ b/block/block-gen.h
@@ -0,0 +1,49 @@
+/*
+ * Block coroutine wrapping core, used by auto-generated block/block-gen.c
+ *
+ * Copyright (c) 2003 Fabrice Bellard
+ * Copyright (c) 2020 Virtuozzo International GmbH
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to
deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ */
+
+#ifndef BLOCK_BLOCK_GEN_H
+#define BLOCK_BLOCK_GEN_H
+
+#include "block/block_int.h"
+
+/* Base structure for argument packing structures */
+typedef struct BdrvPollCo {
+BlockDriverState *bs;
+bool in_progress;
+int ret;
+Coroutine *co; /* Keep pointer here for debugging */
+} BdrvPollCo;
+
+static inline int bdrv_poll_co(BdrvPollCo *s)
+{
+assert(!qemu_in_coroutine());
+
+bdrv_coroutine_enter(s->bs, s->co);
+BDRV_POLL_WHILE(s->bs, s->in_progress);
+
+return s->ret;
+}
+
+#endif /* BLOCK_BLOCK_GEN_H */
diff --git a/include/block/block.h b/include/block/block.h
index 81d591dd4c..0f0ddc51b4 100644
--- a/include/block/block.h
+++ b/include/block/block.h
@@ -10,6 +10,16 @@
#include "block/blockjob.h"
#include "qemu/hbitmap.h"
+/*
+ * generated_co_wrapper
+ *
+ * Function specifier, which does nothing but mark functions to be
+ * generated by scripts/block-coroutine-wrapper.py
+ *
+ * Read more in docs/devel/block-coroutine-wrapper.rst
+ */
+#define generated_co_wrapper
+
/* block.c */
typedef struct BlockDriver BlockDriver;
typedef struct BdrvChild BdrvChild;
diff --git a/block/meson.build b/block/meson.build
index a3e56b7cd1..88ad73583a 100644
--- a/block/meson.build
+++ b/block/meson.build
@@ -107,6 +107,14 @@ module_block_h = custom_target('module_block.h',
command: [module_block_py, '@OUTPUT0@', modsrc])
block_ss.add(module_block_h)
+wrapper_py = find
[PULL 03/17] block/nvme: Reduce I/O registers scope
From: Philippe Mathieu-Daudé
We only access the I/O register in nvme_init().
Remove the reference in BDRVNVMeState and reduce its scope.
Signed-off-by: Philippe Mathieu-Daudé
Signed-off-by: Stefan Hajnoczi
Message-Id: <20200922083821.578519-4-phi...@redhat.com>
---
block/nvme.c | 29 -
1 file changed, 16 insertions(+), 13 deletions(-)
diff --git a/block/nvme.c b/block/nvme.c
index 3c834da8fe..e517c7539f 100644
--- a/block/nvme.c
+++ b/block/nvme.c
@@ -98,7 +98,6 @@ enum {
struct BDRVNVMeState {
AioContext *aio_context;
QEMUVFIOState *vfio;
-NVMeRegs *regs;
/* Memory mapped registers */
volatile struct {
uint32_t sq_tail;
@@ -695,6 +694,7 @@ static int nvme_init(BlockDriverState *bs, const char
*device, int namespace,
uint64_t timeout_ms;
uint64_t deadline, now;
Error *local_err = NULL;
+NVMeRegs *regs;
qemu_co_mutex_init(&s->dma_map_lock);
qemu_co_queue_init(&s->dma_flush_queue);
@@ -713,16 +713,16 @@ static int nvme_init(BlockDriverState *bs, const char
*device, int namespace,
goto out;
}
-s->regs = qemu_vfio_pci_map_bar(s->vfio, 0, 0, sizeof(NvmeBar),
-PROT_READ | PROT_WRITE, errp);
-if (!s->regs) {
+regs = qemu_vfio_pci_map_bar(s->vfio, 0, 0, sizeof(NvmeBar),
+ PROT_READ | PROT_WRITE, errp);
+if (!regs) {
ret = -EINVAL;
goto out;
}
/* Perform initialize sequence as described in NVMe spec "7.6.1
* Initialization". */
-cap = le64_to_cpu(s->regs->ctrl.cap);
+cap = le64_to_cpu(regs->ctrl.cap);
if (!(cap & (1ULL << 37))) {
error_setg(errp, "Device doesn't support NVMe command set");
ret = -EINVAL;
@@ -735,10 +735,10 @@ static int nvme_init(BlockDriverState *bs, const char
*device, int namespace,
timeout_ms = MIN(500 * ((cap >> 24) & 0xFF), 3);
/* Reset device to get a clean state. */
-s->regs->ctrl.cc = cpu_to_le32(le32_to_cpu(s->regs->ctrl.cc) & 0xFE);
+regs->ctrl.cc = cpu_to_le32(le32_to_cpu(regs->ctrl.cc) & 0xFE);
/* Wait for CSTS.RDY = 0. */
deadline = qemu_clock_get_ns(QEMU_CLOCK_REALTIME) + timeout_ms * SCALE_MS;
-while (le32_to_cpu(s->regs->ctrl.csts) & 0x1) {
+while (le32_to_cpu(regs->ctrl.csts) & 0x1) {
if (qemu_clock_get_ns(QEMU_CLOCK_REALTIME) > deadline) {
error_setg(errp, "Timeout while waiting for device to reset (%"
PRId64 " ms)",
@@ -766,18 +766,18 @@ static int nvme_init(BlockDriverState *bs, const char
*device, int namespace,
}
s->nr_queues = 1;
QEMU_BUILD_BUG_ON(NVME_QUEUE_SIZE & 0xF000);
-s->regs->ctrl.aqa = cpu_to_le32((NVME_QUEUE_SIZE << 16) | NVME_QUEUE_SIZE);
-s->regs->ctrl.asq = cpu_to_le64(s->queues[INDEX_ADMIN]->sq.iova);
-s->regs->ctrl.acq = cpu_to_le64(s->queues[INDEX_ADMIN]->cq.iova);
+regs->ctrl.aqa = cpu_to_le32((NVME_QUEUE_SIZE << 16) | NVME_QUEUE_SIZE);
+regs->ctrl.asq = cpu_to_le64(s->queues[INDEX_ADMIN]->sq.iova);
+regs->ctrl.acq = cpu_to_le64(s->queues[INDEX_ADMIN]->cq.iova);
/* After setting up all control registers we can enable device now. */
-s->regs->ctrl.cc = cpu_to_le32((ctz32(NVME_CQ_ENTRY_BYTES) << 20) |
+regs->ctrl.cc = cpu_to_le32((ctz32(NVME_CQ_ENTRY_BYTES) << 20) |
(ctz32(NVME_SQ_ENTRY_BYTES) << 16) |
0x1);
/* Wait for CSTS.RDY = 1. */
now = qemu_clock_get_ns(QEMU_CLOCK_REALTIME);
deadline = now + timeout_ms * 100;
-while (!(le32_to_cpu(s->regs->ctrl.csts) & 0x1)) {
+while (!(le32_to_cpu(regs->ctrl.csts) & 0x1)) {
if (qemu_clock_get_ns(QEMU_CLOCK_REALTIME) > deadline) {
error_setg(errp, "Timeout while waiting for device to start (%"
PRId64 " ms)",
@@ -808,6 +808,10 @@ static int nvme_init(BlockDriverState *bs, const char
*device, int namespace,
ret = -EIO;
}
out:
+if (regs) {
+qemu_vfio_pci_unmap_bar(s->vfio, 0, (void *)regs, 0, sizeof(NvmeBar));
+}
+
/* Cleaning up is done in nvme_file_open() upon error. */
return ret;
}
@@ -882,7 +886,6 @@ static void nvme_close(BlockDriverState *bs)
event_notifier_cleanup(&s->irq_notifier[MSIX_SHARED_IRQ_IDX]);
qemu_vfio_pci_unmap_bar(s->vfio, 0, (void *)s->doorbells,
sizeof(NvmeBar), NVME_DOORBELL_SIZE);
-qemu_vfio_pci_unmap_bar(s->vfio, 0, (void *)s->regs, 0, sizeof(NvmeBar));
qemu_vfio_close(s->vfio);
g_free(s->device);
--
2.26.2
[PULL 05/17] block/nvme: Use register definitions from 'block/nvme.h'
From: Philippe Mathieu-Daudé
Use the NVMe register definitions from "block/nvme.h" which
ease a bit reviewing the code while matching the datasheet.
Signed-off-by: Philippe Mathieu-Daudé
Signed-off-by: Stefan Hajnoczi
Message-Id: <20200922083821.578519-6-phi...@redhat.com>
---
block/nvme.c | 21 +++--
1 file changed, 11 insertions(+), 10 deletions(-)
diff --git a/block/nvme.c b/block/nvme.c
index bd82990b66..959569d262 100644
--- a/block/nvme.c
+++ b/block/nvme.c
@@ -718,22 +718,22 @@ static int nvme_init(BlockDriverState *bs, const char
*device, int namespace,
* Initialization". */
cap = le64_to_cpu(regs->cap);
-if (!(cap & (1ULL << 37))) {
+if (!NVME_CAP_CSS(cap)) {
error_setg(errp, "Device doesn't support NVMe command set");
ret = -EINVAL;
goto out;
}
-s->page_size = MAX(4096, 1 << (12 + ((cap >> 48) & 0xF)));
-s->doorbell_scale = (4 << (((cap >> 32) & 0xF))) / sizeof(uint32_t);
+s->page_size = MAX(4096, 1 << NVME_CAP_MPSMIN(cap));
+s->doorbell_scale = (4 << NVME_CAP_DSTRD(cap)) / sizeof(uint32_t);
bs->bl.opt_mem_alignment = s->page_size;
-timeout_ms = MIN(500 * ((cap >> 24) & 0xFF), 3);
+timeout_ms = MIN(500 * NVME_CAP_TO(cap), 3);
/* Reset device to get a clean state. */
regs->cc = cpu_to_le32(le32_to_cpu(regs->cc) & 0xFE);
/* Wait for CSTS.RDY = 0. */
deadline = qemu_clock_get_ns(QEMU_CLOCK_REALTIME) + timeout_ms * SCALE_MS;
-while (le32_to_cpu(regs->csts) & 0x1) {
+while (NVME_CSTS_RDY(le32_to_cpu(regs->csts))) {
if (qemu_clock_get_ns(QEMU_CLOCK_REALTIME) > deadline) {
error_setg(errp, "Timeout while waiting for device to reset (%"
PRId64 " ms)",
@@ -761,18 +761,19 @@ static int nvme_init(BlockDriverState *bs, const char
*device, int namespace,
}
s->nr_queues = 1;
QEMU_BUILD_BUG_ON(NVME_QUEUE_SIZE & 0xF000);
-regs->aqa = cpu_to_le32((NVME_QUEUE_SIZE << 16) | NVME_QUEUE_SIZE);
+regs->aqa = cpu_to_le32((NVME_QUEUE_SIZE << AQA_ACQS_SHIFT) |
+(NVME_QUEUE_SIZE << AQA_ASQS_SHIFT));
regs->asq = cpu_to_le64(s->queues[INDEX_ADMIN]->sq.iova);
regs->acq = cpu_to_le64(s->queues[INDEX_ADMIN]->cq.iova);
/* After setting up all control registers we can enable device now. */
-regs->cc = cpu_to_le32((ctz32(NVME_CQ_ENTRY_BYTES) << 20) |
- (ctz32(NVME_SQ_ENTRY_BYTES) << 16) |
- 0x1);
+regs->cc = cpu_to_le32((ctz32(NVME_CQ_ENTRY_BYTES) << CC_IOCQES_SHIFT) |
+ (ctz32(NVME_SQ_ENTRY_BYTES) << CC_IOSQES_SHIFT) |
+ CC_EN_MASK);
/* Wait for CSTS.RDY = 1. */
now = qemu_clock_get_ns(QEMU_CLOCK_REALTIME);
deadline = now + timeout_ms * 100;
-while (!(le32_to_cpu(regs->csts) & 0x1)) {
+while (!NVME_CSTS_RDY(le32_to_cpu(regs->csts))) {
if (qemu_clock_get_ns(QEMU_CLOCK_REALTIME) > deadline) {
error_setg(errp, "Timeout while waiting for device to start (%"
PRId64 " ms)",
--
2.26.2
[PULL 17/17] util/vfio-helpers: Rework the IOVA allocator to avoid IOVA reserved regions
From: Eric Auger
Introduce the qemu_vfio_find_fixed/temp_iova helpers which
respectively allocate IOVAs from the bottom/top parts of the
usable IOVA range, without picking within host IOVA reserved
windows. The allocation remains basic: if the size is too big
for the remaining of the current usable IOVA range, we jump
to the next one, leaving a hole in the address map.
Signed-off-by: Eric Auger
Message-id: 20200929085550.30926-3-eric.au...@redhat.com
Signed-off-by: Stefan Hajnoczi
---
util/vfio-helpers.c | 57 +
1 file changed, 53 insertions(+), 4 deletions(-)
diff --git a/util/vfio-helpers.c b/util/vfio-helpers.c
index fe9ca9ce38..c469beb061 100644
--- a/util/vfio-helpers.c
+++ b/util/vfio-helpers.c
@@ -667,6 +667,50 @@ static bool qemu_vfio_verify_mappings(QEMUVFIOState *s)
return true;
}
+static int
+qemu_vfio_find_fixed_iova(QEMUVFIOState *s, size_t size, uint64_t *iova)
+{
+int i;
+
+for (i = 0; i < s->nb_iova_ranges; i++) {
+if (s->usable_iova_ranges[i].end < s->low_water_mark) {
+continue;
+}
+s->low_water_mark =
+MAX(s->low_water_mark, s->usable_iova_ranges[i].start);
+
+if (s->usable_iova_ranges[i].end - s->low_water_mark + 1 >= size ||
+s->usable_iova_ranges[i].end - s->low_water_mark + 1 == 0) {
+*iova = s->low_water_mark;
+s->low_water_mark += size;
+return 0;
+}
+}
+return -ENOMEM;
+}
+
+static int
+qemu_vfio_find_temp_iova(QEMUVFIOState *s, size_t size, uint64_t *iova)
+{
+int i;
+
+for (i = s->nb_iova_ranges - 1; i >= 0; i--) {
+if (s->usable_iova_ranges[i].start > s->high_water_mark) {
+continue;
+}
+s->high_water_mark =
+MIN(s->high_water_mark, s->usable_iova_ranges[i].end + 1);
+
+if (s->high_water_mark - s->usable_iova_ranges[i].start + 1 >= size ||
+s->high_water_mark - s->usable_iova_ranges[i].start + 1 == 0) {
+*iova = s->high_water_mark - size;
+s->high_water_mark = *iova;
+return 0;
+}
+}
+return -ENOMEM;
+}
+
/* Map [host, host + size) area into a contiguous IOVA address space, and store
* the result in @iova if not NULL. The caller need to make sure the area is
* aligned to page size, and mustn't overlap with existing mapping areas (split
@@ -693,7 +737,11 @@ int qemu_vfio_dma_map(QEMUVFIOState *s, void *host, size_t
size,
goto out;
}
if (!temporary) {
-iova0 = s->low_water_mark;
+if (qemu_vfio_find_fixed_iova(s, size, &iova0)) {
+ret = -ENOMEM;
+goto out;
+}
+
mapping = qemu_vfio_add_mapping(s, host, size, index + 1, iova0);
if (!mapping) {
ret = -ENOMEM;
@@ -705,15 +753,16 @@ int qemu_vfio_dma_map(QEMUVFIOState *s, void *host,
size_t size,
qemu_vfio_undo_mapping(s, mapping, NULL);
goto out;
}
-s->low_water_mark += size;
qemu_vfio_dump_mappings(s);
} else {
-iova0 = s->high_water_mark - size;
+if (qemu_vfio_find_temp_iova(s, size, &iova0)) {
+ret = -ENOMEM;
+goto out;
+}
ret = qemu_vfio_do_mapping(s, host, size, iova0);
if (ret) {
goto out;
}
-s->high_water_mark -= size;
}
}
if (iova) {
--
2.26.2
[PULL 15/17] docs: add 'io_uring' option to 'aio' param in qemu-options.hx
From: Stefano Garzarella
When we added io_uring AIO engine, we forgot to update qemu-options.hx,
so qemu(1) man page and qemu help were outdated.
Signed-off-by: Stefano Garzarella
Signed-off-by: Stefan Hajnoczi
Reviewed-by: Julia Suvorova
Reviewed-by: Pankaj Gupta
Message-Id: <20200924151511.131471-1-sgarz...@redhat.com>
---
qemu-options.hx | 10 ++
1 file changed, 6 insertions(+), 4 deletions(-)
diff --git a/qemu-options.hx b/qemu-options.hx
index 3564c2303f..1da52a269c 100644
--- a/qemu-options.hx
+++ b/qemu-options.hx
@@ -1053,7 +1053,8 @@ SRST
The path to the image file in the local filesystem
``aio``
-Specifies the AIO backend (threads/native, default: threads)
+Specifies the AIO backend (threads/native/io_uring,
+default: threads)
``locking``
Specifies whether the image file is protected with Linux OFD
@@ -1175,7 +1176,8 @@ DEF("drive", HAS_ARG, QEMU_OPTION_drive,
"-drive [file=file][,if=type][,bus=n][,unit=m][,media=d][,index=i]\n"
"
[,cache=writethrough|writeback|none|directsync|unsafe][,format=f]\n"
" [,snapshot=on|off][,rerror=ignore|stop|report]\n"
-"
[,werror=ignore|stop|report|enospc][,id=name][,aio=threads|native]\n"
+" [,werror=ignore|stop|report|enospc][,id=name]\n"
+" [,aio=threads|native|io_uring]\n"
" [,readonly=on|off][,copy-on-read=on|off]\n"
" [,discard=ignore|unmap][,detect-zeroes=on|off|unmap]\n"
" [[,bps=b]|[[,bps_rd=r][,bps_wr=w]]]\n"
@@ -1247,8 +1249,8 @@ SRST
The default mode is ``cache=writeback``.
``aio=aio``
-aio is "threads", or "native" and selects between pthread based
-disk I/O and native Linux AIO.
+aio is "threads", "native", or "io_uring" and selects between pthread
+based disk I/O, native Linux AIO, or Linux io_uring API.
``format=format``
Specify which disk format will be used rather than detecting the
--
2.26.2
[PULL 09/17] block: declare some coroutine functions in block/coroutines.h
From: Vladimir Sementsov-Ogievskiy
We are going to keep coroutine-wrappers code (structure-packing
parameters, BDRV_POLL wrapper functions) in separate auto-generated
files. So, we'll need a header with declaration of original _co_
functions, for those which are static now. As well, we'll need
declarations for wrapper functions. Do these declarations now, as a
preparation step.
Signed-off-by: Vladimir Sementsov-Ogievskiy
Signed-off-by: Stefan Hajnoczi
Reviewed-by: Eric Blake
Reviewed-by: Philippe Mathieu-Daudé
Reviewed-by: Stefan Hajnoczi
Message-Id: <20200924185414.28642-4-vsement...@virtuozzo.com>
---
block/coroutines.h | 67 ++
block.c| 8 +++---
block/io.c | 34 +++
3 files changed, 88 insertions(+), 21 deletions(-)
create mode 100644 block/coroutines.h
diff --git a/block/coroutines.h b/block/coroutines.h
new file mode 100644
index 00..9ce1730a09
--- /dev/null
+++ b/block/coroutines.h
@@ -0,0 +1,67 @@
+/*
+ * Block layer I/O functions
+ *
+ * Copyright (c) 2003 Fabrice Bellard
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to
deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ */
+
+#ifndef BLOCK_COROUTINES_INT_H
+#define BLOCK_COROUTINES_INT_H
+
+#include "block/block_int.h"
+
+int coroutine_fn bdrv_co_check(BlockDriverState *bs,
+ BdrvCheckResult *res, BdrvCheckMode fix);
+int coroutine_fn bdrv_co_invalidate_cache(BlockDriverState *bs, Error **errp);
+
+int coroutine_fn
+bdrv_co_prwv(BdrvChild *child, int64_t offset, QEMUIOVector *qiov,
+ bool is_write, BdrvRequestFlags flags);
+int
+bdrv_prwv(BdrvChild *child, int64_t offset, QEMUIOVector *qiov,
+ bool is_write, BdrvRequestFlags flags);
+
+int coroutine_fn
+bdrv_co_common_block_status_above(BlockDriverState *bs,
+ BlockDriverState *base,
+ bool want_zero,
+ int64_t offset,
+ int64_t bytes,
+ int64_t *pnum,
+ int64_t *map,
+ BlockDriverState **file);
+int
+bdrv_common_block_status_above(BlockDriverState *bs,
+ BlockDriverState *base,
+ bool want_zero,
+ int64_t offset,
+ int64_t bytes,
+ int64_t *pnum,
+ int64_t *map,
+ BlockDriverState **file);
+
+int coroutine_fn
+bdrv_co_rw_vmstate(BlockDriverState *bs, QEMUIOVector *qiov, int64_t pos,
+ bool is_read);
+int
+bdrv_rw_vmstate(BlockDriverState *bs, QEMUIOVector *qiov, int64_t pos,
+bool is_read);
+
+#endif /* BLOCK_COROUTINES_INT_H */
diff --git a/block.c b/block.c
index 4829c8ac47..517a425340 100644
--- a/block.c
+++ b/block.c
@@ -48,6 +48,7 @@
#include "qemu/timer.h"
#include "qemu/cutils.h"
#include "qemu/id.h"
+#include "block/coroutines.h"
#ifdef CONFIG_BSD
#include
@@ -4676,8 +4677,8 @@ static void bdrv_delete(BlockDriverState *bs)
* free of errors) or -errno when an internal error occurred. The results of
the
* check are stored in res.
*/
-static int coroutine_fn bdrv_co_check(BlockDriverState *bs,
- BdrvCheckResult *res, BdrvCheckMode fix)
+int coroutine_fn bdrv_co_check(BlockDriverState *bs,
+ BdrvCheckResult *res, BdrvCheckMode fix)
{
if (bs->drv == NULL) {
return -ENOMEDIUM;
@@ -5781,8 +5782,7 @@ void bdrv_init_with_whitelist(void)
bdrv_init();
}
-static int coroutine_fn bdrv_co_invalidate_cache(BlockDriverState *bs,
- Error **errp)
+int coroutine_fn bdrv_co_invalidate_cache(BlockDriverState *bs, Error **errp)
{
BdrvChild *child, *parent;
[PULL 07/17] block: return error-code from bdrv_invalidate_cache
From: Vladimir Sementsov-Ogievskiy
This is the only coroutine wrapper from block.c and block/io.c which
doesn't return a value, so let's convert it to the common behavior, to
simplify moving to generated coroutine wrappers in a further commit.
Also, bdrv_invalidate_cache is a void function, returning error only
through **errp parameter, which is considered to be bad practice, as
it forces callers to define and propagate local_err variable, so
conversion is good anyway.
This patch leaves the conversion of .bdrv_co_invalidate_cache() driver
callbacks and bdrv_invalidate_cache_all() for another day.
Signed-off-by: Vladimir Sementsov-Ogievskiy
Signed-off-by: Stefan Hajnoczi
Reviewed-by: Eric Blake
Reviewed-by: Philippe Mathieu-Daudé
Reviewed-by: Stefan Hajnoczi
Message-Id: <20200924185414.28642-2-vsement...@virtuozzo.com>
---
include/block/block.h | 2 +-
block.c | 32 ++--
2 files changed, 19 insertions(+), 15 deletions(-)
diff --git a/include/block/block.h b/include/block/block.h
index 981ab5b314..81d591dd4c 100644
--- a/include/block/block.h
+++ b/include/block/block.h
@@ -460,7 +460,7 @@ void bdrv_aio_cancel_async(BlockAIOCB *acb);
int bdrv_co_ioctl(BlockDriverState *bs, int req, void *buf);
/* Invalidate any cached metadata used by image formats */
-void bdrv_invalidate_cache(BlockDriverState *bs, Error **errp);
+int bdrv_invalidate_cache(BlockDriverState *bs, Error **errp);
void bdrv_invalidate_cache_all(Error **errp);
int bdrv_inactivate_all(void);
diff --git a/block.c b/block.c
index f72a2e26e8..4829c8ac47 100644
--- a/block.c
+++ b/block.c
@@ -5781,8 +5781,8 @@ void bdrv_init_with_whitelist(void)
bdrv_init();
}
-static void coroutine_fn bdrv_co_invalidate_cache(BlockDriverState *bs,
- Error **errp)
+static int coroutine_fn bdrv_co_invalidate_cache(BlockDriverState *bs,
+ Error **errp)
{
BdrvChild *child, *parent;
uint64_t perm, shared_perm;
@@ -5791,14 +5791,14 @@ static void coroutine_fn
bdrv_co_invalidate_cache(BlockDriverState *bs,
BdrvDirtyBitmap *bm;
if (!bs->drv) {
-return;
+return -ENOMEDIUM;
}
QLIST_FOREACH(child, &bs->children, next) {
bdrv_co_invalidate_cache(child->bs, &local_err);
if (local_err) {
error_propagate(errp, local_err);
-return;
+return -EINVAL;
}
}
@@ -5821,7 +5821,7 @@ static void coroutine_fn
bdrv_co_invalidate_cache(BlockDriverState *bs,
ret = bdrv_check_perm(bs, NULL, perm, shared_perm, NULL, NULL, errp);
if (ret < 0) {
bs->open_flags |= BDRV_O_INACTIVE;
-return;
+return ret;
}
bdrv_set_perm(bs, perm, shared_perm);
@@ -5830,7 +5830,7 @@ static void coroutine_fn
bdrv_co_invalidate_cache(BlockDriverState *bs,
if (local_err) {
bs->open_flags |= BDRV_O_INACTIVE;
error_propagate(errp, local_err);
-return;
+return -EINVAL;
}
}
@@ -5842,7 +5842,7 @@ static void coroutine_fn
bdrv_co_invalidate_cache(BlockDriverState *bs,
if (ret < 0) {
bs->open_flags |= BDRV_O_INACTIVE;
error_setg_errno(errp, -ret, "Could not refresh total sector
count");
-return;
+return ret;
}
}
@@ -5852,27 +5852,30 @@ static void coroutine_fn
bdrv_co_invalidate_cache(BlockDriverState *bs,
if (local_err) {
bs->open_flags |= BDRV_O_INACTIVE;
error_propagate(errp, local_err);
-return;
+return -EINVAL;
}
}
}
+
+return 0;
}
typedef struct InvalidateCacheCo {
BlockDriverState *bs;
Error **errp;
bool done;
+int ret;
} InvalidateCacheCo;
static void coroutine_fn bdrv_invalidate_cache_co_entry(void *opaque)
{
InvalidateCacheCo *ico = opaque;
-bdrv_co_invalidate_cache(ico->bs, ico->errp);
+ico->ret = bdrv_co_invalidate_cache(ico->bs, ico->errp);
ico->done = true;
aio_wait_kick();
}
-void bdrv_invalidate_cache(BlockDriverState *bs, Error **errp)
+int bdrv_invalidate_cache(BlockDriverState *bs, Error **errp)
{
Coroutine *co;
InvalidateCacheCo ico = {
@@ -5889,22 +5892,23 @@ void bdrv_invalidate_cache(BlockDriverState *bs, Error
**errp)
bdrv_coroutine_enter(bs, co);
BDRV_POLL_WHILE(bs, !ico.done);
}
+
+return ico.ret;
}
void bdrv_invalidate_cache_all(Error **errp)
{
BlockDriverState *bs;
-Error *local_err = NULL;
BdrvNextIterator it;
for (bs = bdrv_first(&it); bs; bs = bdrv_next(&it)) {
AioContext *aio_context = bdrv_get_aio_context(bs);
+int ret;
aio_context_acquire(aio_context);
-bdrv_invalidate_cache(bs, &local_err);
+
[PULL 08/17] block/io: refactor coroutine wrappers
From: Vladimir Sementsov-Ogievskiy
Most of our coroutine wrappers already follow this convention:
We have 'coroutine_fn bdrv_co_()' as
the core function, and a wrapper 'bdrv_()' which does parameter packing and calls bdrv_run_co().
The only outsiders are the bdrv_prwv_co and
bdrv_common_block_status_above wrappers. Let's refactor them to behave
as the others, it simplifies further conversion of coroutine wrappers.
This patch adds an indirection layer, but it will be compensated by
a further commit, which will drop bdrv_co_prwv together with the
is_write logic, to keep the read and write paths separate.
Signed-off-by: Vladimir Sementsov-Ogievskiy
Signed-off-by: Stefan Hajnoczi
Reviewed-by: Eric Blake
Reviewed-by: Philippe Mathieu-Daudé
Reviewed-by: Stefan Hajnoczi
Message-Id: <20200924185414.28642-3-vsement...@virtuozzo.com>
---
block/io.c | 60 +-
1 file changed, 32 insertions(+), 28 deletions(-)
diff --git a/block/io.c b/block/io.c
index 11df1889f1..b4f6ab0ab1 100644
--- a/block/io.c
+++ b/block/io.c
@@ -933,27 +933,31 @@ typedef struct RwCo {
BdrvRequestFlags flags;
} RwCo;
+static int coroutine_fn bdrv_co_prwv(BdrvChild *child, int64_t offset,
+ QEMUIOVector *qiov, bool is_write,
+ BdrvRequestFlags flags)
+{
+if (is_write) {
+return bdrv_co_pwritev(child, offset, qiov->size, qiov, flags);
+} else {
+return bdrv_co_preadv(child, offset, qiov->size, qiov, flags);
+}
+}
+
static int coroutine_fn bdrv_rw_co_entry(void *opaque)
{
RwCo *rwco = opaque;
-if (!rwco->is_write) {
-return bdrv_co_preadv(rwco->child, rwco->offset,
- rwco->qiov->size, rwco->qiov,
- rwco->flags);
-} else {
-return bdrv_co_pwritev(rwco->child, rwco->offset,
- rwco->qiov->size, rwco->qiov,
- rwco->flags);
-}
+return bdrv_co_prwv(rwco->child, rwco->offset, rwco->qiov,
+rwco->is_write, rwco->flags);
}
/*
* Process a vectored synchronous request using coroutines
*/
-static int bdrv_prwv_co(BdrvChild *child, int64_t offset,
-QEMUIOVector *qiov, bool is_write,
-BdrvRequestFlags flags)
+static int bdrv_prwv(BdrvChild *child, int64_t offset,
+ QEMUIOVector *qiov, bool is_write,
+ BdrvRequestFlags flags)
{
RwCo rwco = {
.child = child,
@@ -971,8 +975,7 @@ int bdrv_pwrite_zeroes(BdrvChild *child, int64_t offset,
{
QEMUIOVector qiov = QEMU_IOVEC_INIT_BUF(qiov, NULL, bytes);
-return bdrv_prwv_co(child, offset, &qiov, true,
-BDRV_REQ_ZERO_WRITE | flags);
+return bdrv_prwv(child, offset, &qiov, true, BDRV_REQ_ZERO_WRITE | flags);
}
/*
@@ -1021,7 +1024,7 @@ int bdrv_preadv(BdrvChild *child, int64_t offset,
QEMUIOVector *qiov)
{
int ret;
-ret = bdrv_prwv_co(child, offset, qiov, false, 0);
+ret = bdrv_prwv(child, offset, qiov, false, 0);
if (ret < 0) {
return ret;
}
@@ -1045,7 +1048,7 @@ int bdrv_pwritev(BdrvChild *child, int64_t offset,
QEMUIOVector *qiov)
{
int ret;
-ret = bdrv_prwv_co(child, offset, qiov, true, 0);
+ret = bdrv_prwv(child, offset, qiov, true, 0);
if (ret < 0) {
return ret;
}
@@ -2449,14 +2452,15 @@ early_out:
return ret;
}
-static int coroutine_fn bdrv_co_block_status_above(BlockDriverState *bs,
- BlockDriverState *base,
- bool want_zero,
- int64_t offset,
- int64_t bytes,
- int64_t *pnum,
- int64_t *map,
- BlockDriverState **file)
+static int coroutine_fn
+bdrv_co_common_block_status_above(BlockDriverState *bs,
+ BlockDriverState *base,
+ bool want_zero,
+ int64_t offset,
+ int64_t bytes,
+ int64_t *pnum,
+ int64_t *map,
+ BlockDriverState **file)
{
BlockDriverState *p;
int ret = 0;
@@ -2494,10 +2498,10 @@ static int coroutine_fn
bdrv_block_status_above_co_entry(void *opaque)
{
BdrvCoBlockStatusData *data = opaque;
-return bdrv_co_block_status_above(data->bs, data->base,
- data->want_zero,
- data->offset, data->bytes,
- data->pnum, data->map, data->fi
Re: [PATCH] pci: check bus pointer before dereference
+-- On Wed, 30 Sep 2020, Igor Mammedov wrote --+ | 'dest' is offset into MemoryRegion, so far I don't see how it could break | into QEMU stack. Do you have a simple reproducer? Please see: -> https://ruhr-uni-bochum.sciebo.de/s/NNWP2GfwzYKeKwE?path=%2Flsi_nullptr1 Thank you. -- Prasad J Pandit / Red Hat Product Security Team 8685 545E B54C 486B C6EB 271E E285 8B5A F050 DE8D
[PULL 13/17] block/io: refactor save/load vmstate
From: Vladimir Sementsov-Ogievskiy
Like for read/write in a previous commit, drop extra indirection layer,
generate directly bdrv_readv_vmstate() and bdrv_writev_vmstate().
Signed-off-by: Vladimir Sementsov-Ogievskiy
Signed-off-by: Stefan Hajnoczi
Reviewed-by: Eric Blake
Reviewed-by: Stefan Hajnoczi
Message-Id: <20200924185414.28642-8-vsement...@virtuozzo.com>
---
block/coroutines.h| 10 +++
include/block/block.h | 6 ++--
block/io.c| 70 ++-
3 files changed, 44 insertions(+), 42 deletions(-)
diff --git a/block/coroutines.h b/block/coroutines.h
index 6c63a819c9..f69179f5ef 100644
--- a/block/coroutines.h
+++ b/block/coroutines.h
@@ -57,11 +57,9 @@ bdrv_common_block_status_above(BlockDriverState *bs,
int64_t *map,
BlockDriverState **file);
-int coroutine_fn
-bdrv_co_rw_vmstate(BlockDriverState *bs, QEMUIOVector *qiov, int64_t pos,
- bool is_read);
-int generated_co_wrapper
-bdrv_rw_vmstate(BlockDriverState *bs, QEMUIOVector *qiov, int64_t pos,
-bool is_read);
+int coroutine_fn bdrv_co_readv_vmstate(BlockDriverState *bs,
+ QEMUIOVector *qiov, int64_t pos);
+int coroutine_fn bdrv_co_writev_vmstate(BlockDriverState *bs,
+QEMUIOVector *qiov, int64_t pos);
#endif /* BLOCK_COROUTINES_INT_H */
diff --git a/include/block/block.h b/include/block/block.h
index eef4cceaf0..8b87df69a1 100644
--- a/include/block/block.h
+++ b/include/block/block.h
@@ -572,8 +572,10 @@ int path_has_protocol(const char *path);
int path_is_absolute(const char *path);
char *path_combine(const char *base_path, const char *filename);
-int bdrv_readv_vmstate(BlockDriverState *bs, QEMUIOVector *qiov, int64_t pos);
-int bdrv_writev_vmstate(BlockDriverState *bs, QEMUIOVector *qiov, int64_t pos);
+int generated_co_wrapper
+bdrv_readv_vmstate(BlockDriverState *bs, QEMUIOVector *qiov, int64_t pos);
+int generated_co_wrapper
+bdrv_writev_vmstate(BlockDriverState *bs, QEMUIOVector *qiov, int64_t pos);
int bdrv_save_vmstate(BlockDriverState *bs, const uint8_t *buf,
int64_t pos, int size);
diff --git a/block/io.c b/block/io.c
index c3dc1db036..54f0968aee 100644
--- a/block/io.c
+++ b/block/io.c
@@ -2475,28 +2475,50 @@ int bdrv_is_allocated_above(BlockDriverState *top,
}
int coroutine_fn
-bdrv_co_rw_vmstate(BlockDriverState *bs, QEMUIOVector *qiov, int64_t pos,
- bool is_read)
+bdrv_co_readv_vmstate(BlockDriverState *bs, QEMUIOVector *qiov, int64_t pos)
{
BlockDriver *drv = bs->drv;
BlockDriverState *child_bs = bdrv_primary_bs(bs);
int ret = -ENOTSUP;
+if (!drv) {
+return -ENOMEDIUM;
+}
+
bdrv_inc_in_flight(bs);
+if (drv->bdrv_load_vmstate) {
+ret = drv->bdrv_load_vmstate(bs, qiov, pos);
+} else if (child_bs) {
+ret = bdrv_co_readv_vmstate(child_bs, qiov, pos);
+}
+
+bdrv_dec_in_flight(bs);
+
+return ret;
+}
+
+int coroutine_fn
+bdrv_co_writev_vmstate(BlockDriverState *bs, QEMUIOVector *qiov, int64_t pos)
+{
+BlockDriver *drv = bs->drv;
+BlockDriverState *child_bs = bdrv_primary_bs(bs);
+int ret = -ENOTSUP;
+
if (!drv) {
-ret = -ENOMEDIUM;
-} else if (drv->bdrv_load_vmstate) {
-if (is_read) {
-ret = drv->bdrv_load_vmstate(bs, qiov, pos);
-} else {
-ret = drv->bdrv_save_vmstate(bs, qiov, pos);
-}
+return -ENOMEDIUM;
+}
+
+bdrv_inc_in_flight(bs);
+
+if (drv->bdrv_save_vmstate) {
+ret = drv->bdrv_save_vmstate(bs, qiov, pos);
} else if (child_bs) {
-ret = bdrv_co_rw_vmstate(child_bs, qiov, pos, is_read);
+ret = bdrv_co_writev_vmstate(child_bs, qiov, pos);
}
bdrv_dec_in_flight(bs);
+
return ret;
}
@@ -2504,38 +2526,18 @@ int bdrv_save_vmstate(BlockDriverState *bs, const
uint8_t *buf,
int64_t pos, int size)
{
QEMUIOVector qiov = QEMU_IOVEC_INIT_BUF(qiov, buf, size);
-int ret;
+int ret = bdrv_writev_vmstate(bs, &qiov, pos);
-ret = bdrv_writev_vmstate(bs, &qiov, pos);
-if (ret < 0) {
-return ret;
-}
-
-return size;
-}
-
-int bdrv_writev_vmstate(BlockDriverState *bs, QEMUIOVector *qiov, int64_t pos)
-{
-return bdrv_rw_vmstate(bs, qiov, pos, false);
+return ret < 0 ? ret : size;
}
int bdrv_load_vmstate(BlockDriverState *bs, uint8_t *buf,
int64_t pos, int size)
{
QEMUIOVector qiov = QEMU_IOVEC_INIT_BUF(qiov, buf, size);
-int ret;
+int ret = bdrv_readv_vmstate(bs, &qiov, pos);
-ret = bdrv_readv_vmstate(bs, &qiov, pos);
-if (ret < 0) {
-return ret;
-}
-
-return size;
-}
-
-int bdrv_readv_vmstate(BlockDriverState *bs, QEMUIOVector *qiov, int64_t pos)
-{
-return bdrv_rw_vmstate(bs, qiov, pos, true);
+return r
[PULL 11/17] block: generate coroutine-wrapper code
From: Vladimir Sementsov-Ogievskiy
Use code generation implemented in previous commit to generated
coroutine wrappers in block.c and block/io.c
Signed-off-by: Vladimir Sementsov-Ogievskiy
Signed-off-by: Stefan Hajnoczi
Reviewed-by: Eric Blake
Reviewed-by: Stefan Hajnoczi
Message-Id: <20200924185414.28642-6-vsement...@virtuozzo.com>
---
block/coroutines.h| 6 +-
include/block/block.h | 16 ++--
block.c | 73 ---
block/io.c| 212 --
4 files changed, 13 insertions(+), 294 deletions(-)
diff --git a/block/coroutines.h b/block/coroutines.h
index 9ce1730a09..c62b3a2697 100644
--- a/block/coroutines.h
+++ b/block/coroutines.h
@@ -34,7 +34,7 @@ int coroutine_fn bdrv_co_invalidate_cache(BlockDriverState
*bs, Error **errp);
int coroutine_fn
bdrv_co_prwv(BdrvChild *child, int64_t offset, QEMUIOVector *qiov,
bool is_write, BdrvRequestFlags flags);
-int
+int generated_co_wrapper
bdrv_prwv(BdrvChild *child, int64_t offset, QEMUIOVector *qiov,
bool is_write, BdrvRequestFlags flags);
@@ -47,7 +47,7 @@ bdrv_co_common_block_status_above(BlockDriverState *bs,
int64_t *pnum,
int64_t *map,
BlockDriverState **file);
-int
+int generated_co_wrapper
bdrv_common_block_status_above(BlockDriverState *bs,
BlockDriverState *base,
bool want_zero,
@@ -60,7 +60,7 @@ bdrv_common_block_status_above(BlockDriverState *bs,
int coroutine_fn
bdrv_co_rw_vmstate(BlockDriverState *bs, QEMUIOVector *qiov, int64_t pos,
bool is_read);
-int
+int generated_co_wrapper
bdrv_rw_vmstate(BlockDriverState *bs, QEMUIOVector *qiov, int64_t pos,
bool is_read);
diff --git a/include/block/block.h b/include/block/block.h
index 0f0ddc51b4..f2d85f2cf1 100644
--- a/include/block/block.h
+++ b/include/block/block.h
@@ -403,8 +403,9 @@ void bdrv_refresh_filename(BlockDriverState *bs);
int coroutine_fn bdrv_co_truncate(BdrvChild *child, int64_t offset, bool exact,
PreallocMode prealloc, BdrvRequestFlags
flags,
Error **errp);
-int bdrv_truncate(BdrvChild *child, int64_t offset, bool exact,
- PreallocMode prealloc, BdrvRequestFlags flags, Error **errp);
+int generated_co_wrapper
+bdrv_truncate(BdrvChild *child, int64_t offset, bool exact,
+ PreallocMode prealloc, BdrvRequestFlags flags, Error **errp);
int64_t bdrv_nb_sectors(BlockDriverState *bs);
int64_t bdrv_getlength(BlockDriverState *bs);
@@ -446,7 +447,8 @@ typedef enum {
BDRV_FIX_ERRORS = 2,
} BdrvCheckMode;
-int bdrv_check(BlockDriverState *bs, BdrvCheckResult *res, BdrvCheckMode fix);
+int generated_co_wrapper bdrv_check(BlockDriverState *bs, BdrvCheckResult *res,
+BdrvCheckMode fix);
/* The units of offset and total_work_size may be chosen arbitrarily by the
* block driver; total_work_size may change during the course of the amendment
@@ -470,12 +472,13 @@ void bdrv_aio_cancel_async(BlockAIOCB *acb);
int bdrv_co_ioctl(BlockDriverState *bs, int req, void *buf);
/* Invalidate any cached metadata used by image formats */
-int bdrv_invalidate_cache(BlockDriverState *bs, Error **errp);
+int generated_co_wrapper bdrv_invalidate_cache(BlockDriverState *bs,
+ Error **errp);
void bdrv_invalidate_cache_all(Error **errp);
int bdrv_inactivate_all(void);
/* Ensure contents are flushed to disk. */
-int bdrv_flush(BlockDriverState *bs);
+int generated_co_wrapper bdrv_flush(BlockDriverState *bs);
int coroutine_fn bdrv_co_flush(BlockDriverState *bs);
int bdrv_flush_all(void);
void bdrv_close_all(void);
@@ -490,7 +493,8 @@ void bdrv_drain_all(void);
AIO_WAIT_WHILE(bdrv_get_aio_context(bs_), \
cond); })
-int bdrv_pdiscard(BdrvChild *child, int64_t offset, int64_t bytes);
+int generated_co_wrapper bdrv_pdiscard(BdrvChild *child, int64_t offset,
+ int64_t bytes);
int bdrv_co_pdiscard(BdrvChild *child, int64_t offset, int64_t bytes);
int bdrv_has_zero_init_1(BlockDriverState *bs);
int bdrv_has_zero_init(BlockDriverState *bs);
diff --git a/block.c b/block.c
index 517a425340..429864e204 100644
--- a/block.c
+++ b/block.c
@@ -4691,43 +4691,6 @@ int coroutine_fn bdrv_co_check(BlockDriverState *bs,
return bs->drv->bdrv_co_check(bs, res, fix);
}
-typedef struct CheckCo {
-BlockDriverState *bs;
-BdrvCheckResult *res;
-BdrvCheckMode fix;
-int ret;
-} CheckCo;
-
-static void coroutine_fn bdrv_check_co_entry(void *opaque)
-{
-CheckCo *cco = opaque;
-cco->ret = bdrv_co_check(cco->bs, cco->res, cco->fix);
-aio_wait_kick();
-}
-
-int bdrv_check(BlockDriverState *bs,
- BdrvCheck
Re: [PATCH RFC 14/14] target/: fix some comment spelling errors
On 9/30/20 11:53 AM, zhaolichang wrote:
> I found that there are many spelling errors in the comments of qemu/target.
> I used spellcheck to check the spelling errors and found some errors in the
> folder.
>
> Signed-off-by: zhaolichang
Reviewed-by: Philippe Mathieu-Daudé
> ---
> target/openrisc/cpu.h| 2 +-
> target/sparc/asi.h | 2 +-
> target/unicore32/translate.c | 2 +-
> 3 files changed, 3 insertions(+), 3 deletions(-)
>
> diff --git a/target/openrisc/cpu.h b/target/openrisc/cpu.h
> index bd42faf..8ca8605 100644
> --- a/target/openrisc/cpu.h
> +++ b/target/openrisc/cpu.h
> @@ -291,7 +291,7 @@ typedef struct CPUOpenRISCState {
> int is_counting;
>
> uint32_t picmr; /* Interrupt mask register */
> -uint32_t picsr; /* Interrupt contrl register*/
> +uint32_t picsr; /* Interrupt control register*/
> #endif
> void *irq[32]; /* Interrupt irq input */
> } CPUOpenRISCState;
> diff --git a/target/sparc/asi.h b/target/sparc/asi.h
> index bb58735..4e9f1d5 100644
> --- a/target/sparc/asi.h
> +++ b/target/sparc/asi.h
> @@ -231,7 +231,7 @@
> #define ASI_INTR_ID 0x63 /* (CMT) Interrupt ID register */
> #define ASI_CORE_ID 0x63 /* (CMT) LP ID register*/
> #define ASI_CESR_ID 0x63 /* (CMT) CESR ID register */
> -#define ASI_IC_INSTR 0x66 /* Insn cache instrucion ram diag */
> +#define ASI_IC_INSTR 0x66 /* Insn cache instruction ram diag */
> #define ASI_IC_TAG 0x67 /* Insn cache tag/valid ram diag */
> #define ASI_IC_STAG 0x68 /* (III) Insn cache snoop tag ram */
> #define ASI_IC_PRE_DECODE0x6e /* Insn cache pre-decode ram diag */
> diff --git a/target/unicore32/translate.c b/target/unicore32/translate.c
> index d4b06df..2e91b05 100644
> --- a/target/unicore32/translate.c
> +++ b/target/unicore32/translate.c
> @@ -119,7 +119,7 @@ static void load_reg_var(DisasContext *s, TCGv var, int
> reg)
> {
> if (reg == 31) {
> uint32_t addr;
> -/* normaly, since we updated PC */
> +/* normally, since we updated PC */
> addr = (long)s->pc;
> tcg_gen_movi_i32(var, addr);
> } else {
>
[PULL 12/17] block: drop bdrv_prwv
From: Vladimir Sementsov-Ogievskiy
Now that we are not maintaining boilerplate code for coroutine
wrappers, there is no more sense in keeping the extra indirection layer
of bdrv_prwv(). Let's drop it and instead generate pure bdrv_preadv()
and bdrv_pwritev().
Currently, bdrv_pwritev() and bdrv_preadv() are returning bytes on
success, auto generated functions will instead return zero, as their
_co_ prototype. Still, it's simple to make the conversion safe: the
only external user of bdrv_pwritev() is test-bdrv-drain, and it is
comfortable enough with bdrv_co_pwritev() instead. So prototypes are
moved to local block/coroutines.h. Next, the only internal use is
bdrv_pread() and bdrv_pwrite(), which are modified to return bytes on
success.
Of course, it would be great to convert bdrv_pread() and bdrv_pwrite()
to return 0 on success. But this requires audit (and probably
conversion) of all their users, let's leave it for another day
refactoring.
Signed-off-by: Vladimir Sementsov-Ogievskiy
Signed-off-by: Stefan Hajnoczi
Reviewed-by: Eric Blake
Reviewed-by: Philippe Mathieu-Daudé
Reviewed-by: Stefan Hajnoczi
Message-Id: <20200924185414.28642-7-vsement...@virtuozzo.com>
---
block/coroutines.h | 10 -
include/block/block.h | 2 --
block/io.c | 49 -
tests/test-bdrv-drain.c | 2 +-
4 files changed, 15 insertions(+), 48 deletions(-)
diff --git a/block/coroutines.h b/block/coroutines.h
index c62b3a2697..6c63a819c9 100644
--- a/block/coroutines.h
+++ b/block/coroutines.h
@@ -31,12 +31,12 @@ int coroutine_fn bdrv_co_check(BlockDriverState *bs,
BdrvCheckResult *res, BdrvCheckMode fix);
int coroutine_fn bdrv_co_invalidate_cache(BlockDriverState *bs, Error **errp);
-int coroutine_fn
-bdrv_co_prwv(BdrvChild *child, int64_t offset, QEMUIOVector *qiov,
- bool is_write, BdrvRequestFlags flags);
int generated_co_wrapper
-bdrv_prwv(BdrvChild *child, int64_t offset, QEMUIOVector *qiov,
- bool is_write, BdrvRequestFlags flags);
+bdrv_preadv(BdrvChild *child, int64_t offset, unsigned int bytes,
+QEMUIOVector *qiov, BdrvRequestFlags flags);
+int generated_co_wrapper
+bdrv_pwritev(BdrvChild *child, int64_t offset, unsigned int bytes,
+ QEMUIOVector *qiov, BdrvRequestFlags flags);
int coroutine_fn
bdrv_co_common_block_status_above(BlockDriverState *bs,
diff --git a/include/block/block.h b/include/block/block.h
index f2d85f2cf1..eef4cceaf0 100644
--- a/include/block/block.h
+++ b/include/block/block.h
@@ -383,9 +383,7 @@ int bdrv_pwrite_zeroes(BdrvChild *child, int64_t offset,
int bytes, BdrvRequestFlags flags);
int bdrv_make_zero(BdrvChild *child, BdrvRequestFlags flags);
int bdrv_pread(BdrvChild *child, int64_t offset, void *buf, int bytes);
-int bdrv_preadv(BdrvChild *child, int64_t offset, QEMUIOVector *qiov);
int bdrv_pwrite(BdrvChild *child, int64_t offset, const void *buf, int bytes);
-int bdrv_pwritev(BdrvChild *child, int64_t offset, QEMUIOVector *qiov);
int bdrv_pwrite_sync(BdrvChild *child, int64_t offset,
const void *buf, int count);
/*
diff --git a/block/io.c b/block/io.c
index 2891303a8d..c3dc1db036 100644
--- a/block/io.c
+++ b/block/io.c
@@ -890,23 +890,11 @@ static int bdrv_check_byte_request(BlockDriverState *bs,
int64_t offset,
return 0;
}
-int coroutine_fn bdrv_co_prwv(BdrvChild *child, int64_t offset,
- QEMUIOVector *qiov, bool is_write,
- BdrvRequestFlags flags)
-{
-if (is_write) {
-return bdrv_co_pwritev(child, offset, qiov->size, qiov, flags);
-} else {
-return bdrv_co_preadv(child, offset, qiov->size, qiov, flags);
-}
-}
-
int bdrv_pwrite_zeroes(BdrvChild *child, int64_t offset,
int bytes, BdrvRequestFlags flags)
{
-QEMUIOVector qiov = QEMU_IOVEC_INIT_BUF(qiov, NULL, bytes);
-
-return bdrv_prwv(child, offset, &qiov, true, BDRV_REQ_ZERO_WRITE | flags);
+return bdrv_pwritev(child, offset, bytes, NULL,
+BDRV_REQ_ZERO_WRITE | flags);
}
/*
@@ -950,41 +938,19 @@ int bdrv_make_zero(BdrvChild *child, BdrvRequestFlags
flags)
}
}
-/* return < 0 if error. See bdrv_pwrite() for the return codes */
-int bdrv_preadv(BdrvChild *child, int64_t offset, QEMUIOVector *qiov)
-{
-int ret;
-
-ret = bdrv_prwv(child, offset, qiov, false, 0);
-if (ret < 0) {
-return ret;
-}
-
-return qiov->size;
-}
-
/* See bdrv_pwrite() for the return codes */
int bdrv_pread(BdrvChild *child, int64_t offset, void *buf, int bytes)
{
+int ret;
QEMUIOVector qiov = QEMU_IOVEC_INIT_BUF(qiov, buf, bytes);
if (bytes < 0) {
return -EINVAL;
}
-return bdrv_preadv(child, offset, &qiov);
-}
+ret = bdrv_preadv(child, offset, bytes, &qiov, 0);
-int bdrv_pwritev(BdrvChild *child, int64_t offset, QEMUIOVector *qio
Re: [PATCH RFC 04/14] rx/: fix some comment spelling errors
On 9/30/20 11:53 AM, zhaolichang wrote:
> I found that there are many spelling errors in the comments of qemu/target/rx.
> I used spellcheck to check the spelling errors and found some errors in the
> folder.
>
> Signed-off-by: zhaolichang
Reviewed-by: Philippe Mathieu-Daudé
> ---
> target/rx/op_helper.c | 2 +-
> target/rx/translate.c | 2 +-
> 2 files changed, 2 insertions(+), 2 deletions(-)
>
> diff --git a/target/rx/op_helper.c b/target/rx/op_helper.c
> index f89d294..59389f4 100644
> --- a/target/rx/op_helper.c
> +++ b/target/rx/op_helper.c
> @@ -318,7 +318,7 @@ void helper_swhile(CPURXState *env, uint32_t sz)
> env->psw_c = (tmp <= env->regs[2]);
> }
>
> -/* accumlator operations */
> +/* accumulator operations */
> void helper_rmpa(CPURXState *env, uint32_t sz)
> {
> uint64_t result_l, prev;
> diff --git a/target/rx/translate.c b/target/rx/translate.c
> index 482278e..9ea941c 100644
> --- a/target/rx/translate.c
> +++ b/target/rx/translate.c
> @@ -1089,7 +1089,7 @@ static void rx_sub(TCGv ret, TCGv arg1, TCGv arg2)
> tcg_gen_xor_i32(temp, arg1, arg2);
> tcg_gen_and_i32(cpu_psw_o, cpu_psw_o, temp);
> tcg_temp_free_i32(temp);
> -/* CMP not requred return */
> +/* CMP not required return */
> if (ret) {
> tcg_gen_mov_i32(ret, cpu_psw_s);
> }
>
[PULL 16/17] util/vfio-helpers: Collect IOVA reserved regions
From: Eric Auger
The IOVA allocator currently ignores host reserved regions.
As a result some chosen IOVAs may collide with some of them,
resulting in VFIO MAP_DMA errors later on. This happens on ARM
where the MSI reserved window quickly is encountered:
[0x800, 0x810]. since 5.4 kernel, VFIO returns the usable
IOVA regions. So let's enumerate them in the prospect to avoid
them, later on.
Signed-off-by: Eric Auger
Message-id: 20200929085550.30926-2-eric.au...@redhat.com
Signed-off-by: Stefan Hajnoczi
---
util/vfio-helpers.c | 72 +++--
1 file changed, 70 insertions(+), 2 deletions(-)
diff --git a/util/vfio-helpers.c b/util/vfio-helpers.c
index 9ac307e3d4..fe9ca9ce38 100644
--- a/util/vfio-helpers.c
+++ b/util/vfio-helpers.c
@@ -40,6 +40,11 @@ typedef struct {
uint64_t iova;
} IOVAMapping;
+struct IOVARange {
+uint64_t start;
+uint64_t end;
+};
+
struct QEMUVFIOState {
QemuMutex lock;
@@ -49,6 +54,8 @@ struct QEMUVFIOState {
int device;
RAMBlockNotifier ram_notifier;
struct vfio_region_info config_region_info, bar_region_info[6];
+struct IOVARange *usable_iova_ranges;
+uint8_t nb_iova_ranges;
/* These fields are protected by @lock */
/* VFIO's IO virtual address space is managed by splitting into a few
@@ -236,6 +243,35 @@ static int qemu_vfio_pci_write_config(QEMUVFIOState *s,
void *buf, int size, int
return ret == size ? 0 : -errno;
}
+static void collect_usable_iova_ranges(QEMUVFIOState *s, void *buf)
+{
+struct vfio_iommu_type1_info *info = (struct vfio_iommu_type1_info *)buf;
+struct vfio_info_cap_header *cap = (void *)buf + info->cap_offset;
+struct vfio_iommu_type1_info_cap_iova_range *cap_iova_range;
+int i;
+
+while (cap->id != VFIO_IOMMU_TYPE1_INFO_CAP_IOVA_RANGE) {
+if (!cap->next) {
+return;
+}
+cap = (struct vfio_info_cap_header *)(buf + cap->next);
+}
+
+cap_iova_range = (struct vfio_iommu_type1_info_cap_iova_range *)cap;
+
+s->nb_iova_ranges = cap_iova_range->nr_iovas;
+if (s->nb_iova_ranges > 1) {
+s->usable_iova_ranges =
+g_realloc(s->usable_iova_ranges,
+ s->nb_iova_ranges * sizeof(struct IOVARange));
+}
+
+for (i = 0; i < s->nb_iova_ranges; i++) {
+s->usable_iova_ranges[i].start = cap_iova_range->iova_ranges[i].start;
+s->usable_iova_ranges[i].end = cap_iova_range->iova_ranges[i].end;
+}
+}
+
static int qemu_vfio_init_pci(QEMUVFIOState *s, const char *device,
Error **errp)
{
@@ -243,10 +279,13 @@ static int qemu_vfio_init_pci(QEMUVFIOState *s, const
char *device,
int i;
uint16_t pci_cmd;
struct vfio_group_status group_status = { .argsz = sizeof(group_status) };
-struct vfio_iommu_type1_info iommu_info = { .argsz = sizeof(iommu_info) };
+struct vfio_iommu_type1_info *iommu_info = NULL;
+size_t iommu_info_size = sizeof(*iommu_info);
struct vfio_device_info device_info = { .argsz = sizeof(device_info) };
char *group_file = NULL;
+s->usable_iova_ranges = NULL;
+
/* Create a new container */
s->container = open("/dev/vfio/vfio", O_RDWR);
@@ -310,13 +349,35 @@ static int qemu_vfio_init_pci(QEMUVFIOState *s, const
char *device,
goto fail;
}
+iommu_info = g_malloc0(iommu_info_size);
+iommu_info->argsz = iommu_info_size;
+
/* Get additional IOMMU info */
-if (ioctl(s->container, VFIO_IOMMU_GET_INFO, &iommu_info)) {
+if (ioctl(s->container, VFIO_IOMMU_GET_INFO, iommu_info)) {
error_setg_errno(errp, errno, "Failed to get IOMMU info");
ret = -errno;
goto fail;
}
+/*
+ * if the kernel does not report usable IOVA regions, choose
+ * the legacy [QEMU_VFIO_IOVA_MIN, QEMU_VFIO_IOVA_MAX -1] region
+ */
+s->nb_iova_ranges = 1;
+s->usable_iova_ranges = g_new0(struct IOVARange, 1);
+s->usable_iova_ranges[0].start = QEMU_VFIO_IOVA_MIN;
+s->usable_iova_ranges[0].end = QEMU_VFIO_IOVA_MAX - 1;
+
+if (iommu_info->argsz > iommu_info_size) {
+iommu_info_size = iommu_info->argsz;
+iommu_info = g_realloc(iommu_info, iommu_info_size);
+if (ioctl(s->container, VFIO_IOMMU_GET_INFO, iommu_info)) {
+ret = -errno;
+goto fail;
+}
+collect_usable_iova_ranges(s, iommu_info);
+}
+
s->device = ioctl(s->group, VFIO_GROUP_GET_DEVICE_FD, device);
if (s->device < 0) {
@@ -365,8 +426,13 @@ static int qemu_vfio_init_pci(QEMUVFIOState *s, const char
*device,
if (ret) {
goto fail;
}
+g_free(iommu_info);
return 0;
fail:
+g_free(s->usable_iova_ranges);
+s->usable_iova_ranges = NULL;
+s->nb_iova_ranges = 0;
+g_free(iommu_info);
close(s->group);
fail_container:
close(s->container);
@@ -716,6 +782,8 @@ void qemu_vfio_close(QEMUVFIOState *s)
qemu_
Re: [PATCH RFC 06/14] mips/: fix some comment spelling errors
On Wed, Sep 30, 2020 at 12:23 PM Philippe Mathieu-Daudé wrote: > > On 9/30/20 11:53 AM, zhaolichang wrote: > > I found that there are many spelling errors in the comments of > > qemu/target/mips. > > I used spellcheck to check the spelling errors and found some errors in the > > folder. > > > > Signed-off-by: zhaolichang > > --- > > target/mips/internal.h | 2 +- > > target/mips/translate.c | 10 +- > > target/mips/translate_init.c.inc | 2 +- > > 3 files changed, 7 insertions(+), 7 deletions(-) > > Acked-by: Philippe Mathieu-Daudé Err: Reviewed-by: Philippe Mathieu-Daudé
[PULL 14/17] include/block/block.h: drop non-ascii quotation mark
From: Vladimir Sementsov-Ogievskiy
This is the only non-ascii character in the file and it doesn't really
needed here. Let's use normal "'" symbol for consistency with the rest
11 occurrences of "'" in the file.
Signed-off-by: Vladimir Sementsov-Ogievskiy
Reviewed-by: Eric Blake
Signed-off-by: Stefan Hajnoczi
---
include/block/block.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/include/block/block.h b/include/block/block.h
index 8b87df69a1..ce2ac39299 100644
--- a/include/block/block.h
+++ b/include/block/block.h
@@ -304,7 +304,7 @@ enum BdrvChildRoleBits {
BDRV_CHILD_FILTERED = (1 << 2),
/*
- * Child from which to read all data that isn’t allocated in the
+ * Child from which to read all data that isn't allocated in the
* parent (i.e., the backing child); such data is copied to the
* parent through COW (and optionally COR).
* This field is mutually exclusive with DATA, METADATA, and
--
2.26.2
Re: [PATCH 01/16] hw/core/cpu: Let CPU object have a clock source
+arm/ppc/riscv folks
On 9/30/20 9:43 AM, Igor Mammedov wrote:
> On Mon, 28 Sep 2020 19:15:24 +0200
> Philippe Mathieu-Daudé wrote:
>
>> Let CPUState have a clock source (named 'clk') and CPUClass
>> have a clock_update() callback. The clock can be optionally
>> set Using qdev_connect_clock_in() from the Clock API.
>> If the clock changes, the optional clock_update() will be
>> called.
>
> the sole user of it is mips cpu, so question is why
> you are making it part of generic CPUm instead of
> MIPSCPUClass/MIPSCPU?
This is a feature of the CPU, regardless its architecture.
I expect the other archs to start using it soon.
>
>>
>> Signed-off-by: Philippe Mathieu-Daudé
>> ---
>> include/hw/core/cpu.h | 5 +
>> hw/core/cpu.c | 12
>> 2 files changed, 17 insertions(+)
>>
>> diff --git a/include/hw/core/cpu.h b/include/hw/core/cpu.h
>> index 6c34798c8b3..6989d90c193 100644
>> --- a/include/hw/core/cpu.h
>> +++ b/include/hw/core/cpu.h
>> @@ -31,6 +31,7 @@
>> #include "qemu/thread.h"
>> #include "qemu/plugin.h"
>> #include "qom/object.h"
>> +#include "hw/clock.h"
>>
>> typedef int (*WriteCoreDumpFunction)(const void *buf, size_t size,
>> void *opaque);
>> @@ -155,6 +156,7 @@ struct TranslationBlock;
>> * @disas_set_info: Setup architecture specific components of disassembly
>> info
>> * @adjust_watchpoint_address: Perform a target-specific adjustment to an
>> * address before attempting to match it against watchpoints.
>> + * @clock_update: Callback for input clock changes
>> *
>> * Represents a CPU family or model.
>> */
>> @@ -176,6 +178,7 @@ struct CPUClass {
>>unsigned size, MMUAccessType access_type,
>>int mmu_idx, MemTxAttrs attrs,
>>MemTxResult response, uintptr_t retaddr);
>> +void (*clock_update)(CPUState *cpu);
>> bool (*virtio_is_big_endian)(CPUState *cpu);
>> int (*memory_rw_debug)(CPUState *cpu, vaddr addr,
>> uint8_t *buf, int len, bool is_write);
>> @@ -316,6 +319,7 @@ struct qemu_work_item;
>> * QOM parent.
>> * @nr_cores: Number of cores within this CPU package.
>> * @nr_threads: Number of threads within this CPU.
>> + * @clock: this CPU source clock (an output clock of another device)
>> * @running: #true if CPU is currently running (lockless).
>> * @has_waiter: #true if a CPU is currently waiting for the cpu_exec_end;
>> * valid under cpu_list_lock.
>> @@ -400,6 +404,7 @@ struct CPUState {
>> int num_ases;
>> AddressSpace *as;
>> MemoryRegion *memory;
>> +Clock *clock;
>>
>> void *env_ptr; /* CPUArchState */
>> IcountDecr *icount_decr_ptr;
>> diff --git a/hw/core/cpu.c b/hw/core/cpu.c
>> index c55c09f734c..37fcff3ec64 100644
>> --- a/hw/core/cpu.c
>> +++ b/hw/core/cpu.c
>> @@ -30,6 +30,7 @@
>> #include "qemu/qemu-print.h"
>> #include "sysemu/tcg.h"
>> #include "hw/boards.h"
>> +#include "hw/qdev-clock.h"
>> #include "hw/qdev-properties.h"
>> #include "trace/trace-root.h"
>> #include "qemu/plugin.h"
>> @@ -247,6 +248,16 @@ void cpu_reset(CPUState *cpu)
>> trace_guest_cpu_reset(cpu);
>> }
>>
>> +static void cpu_clk_update(void *opaque)
>> +{
>> +CPUState *cpu = opaque;
>> +CPUClass *cc = CPU_GET_CLASS(cpu);
>> +
>> +if (cc->clock_update) {
>> +cc->clock_update(cpu);
>> +}
>> +}
>> +
>> static void cpu_common_reset(DeviceState *dev)
>> {
>> CPUState *cpu = CPU(dev);
>> @@ -367,6 +378,7 @@ static void cpu_common_initfn(Object *obj)
>> /* the default value is changed by qemu_init_vcpu() for softmmu */
>> cpu->nr_cores = 1;
>> cpu->nr_threads = 1;
>> +cpu->clock = qdev_init_clock_in(DEVICE(obj), "clk", cpu_clk_update,
>> cpu);
>>
>> qemu_mutex_init(&cpu->work_mutex);
>> QSIMPLEQ_INIT(&cpu->work_list);
>
Re: [PULL 00/29] QAPI patches patches for 2020-09-29
On Tue, 29 Sep 2020 at 21:19, Markus Armbruster wrote: > > The following changes since commit b150cb8f67bf491a49a1cb1c7da151eeacbdbcc9: > > Merge remote-tracking branch 'remotes/mst/tags/for_upstream' into staging > (2020-09-29 13:18:54 +0100) > > are available in the Git repository at: > > git://repo.or.cz/qemu/armbru.git tags/pull-qapi-2020-09-29 > > for you to fetch changes up to 7cd77fb02b9a2117a56fed172f09a1820fcd6b0b: > > Remove texinfo dependency from docker and CI configs (2020-09-29 17:55:39 > +0200) > > > QAPI patches patches for 2020-09-29 Applied, thanks. Please update the changelog at https://wiki.qemu.org/ChangeLog/5.2 for any user-visible changes. -- PMM
use of 'apt' in scripting in our dockerfiles provokes warnings
While processing a recent pullreq which updated the dockerfile
dependencies and thus provoked a rebuild, I noticed that we
use the 'apt' command in ways that provoke a warning:
#7 0.789 WARNING: apt does not have a stable CLI interface. Use with
caution in scripts.
The apt(8) manpage says:
SCRIPT USAGE AND DIFFERENCES FROM OTHER APT TOOLS
The apt(8) commandline is designed as an end-user tool and it may
change behavior between versions. While it tries not to break backward
compatibility this is not guaranteed either if a change seems
beneficial for interactive use.
All features of apt(8) are available in dedicated APT tools like apt-
get(8) and apt-cache(8) as well. apt(8) just changes the default value
of some options (see apt.conf(5) and specifically the Binary scope). So
you should prefer using these commands (potentially with some
additional options enabled) in your scripts as they keep backward
compatibility as much as possible.
That suggests that we should probably be using apt-get instead
of apt in our dockerfiles...
Also, any idea what this error is about?
#4 importing cache manifest from registry.gitlab.com/qemu-project/qemu/qemu...
#4 digest:
sha256:815fb44b573ac7520d148d9b2510c00f31846ca6fa55127d322bc8db3c5d0ec0
#4 name: "importing cache manifest from
registry.gitlab.com/qemu-project/qemu/qemu/debian-alpha-cross:latest"
#4 started: 2020-09-29 22:57:54.371490684 + UTC
#4completed: 2020-09-29 22:57:55.064468936 + UTC
#4 duration: 692.978252ms
#4error: "invalid build cache from
{MediaType:application/vnd.docker.distribution.manifest.v2+json
Digest:sha256:a1e8a5830bb19b7cddda64872c5d71a0337d4b98bed30fd7684d20467adcd289
Size:1161 URLs:[] Annotations:map[] Platform:}"
It didn't seemt to have an adverse effect...
thanks
-- PMM
Re: [PATCH] hw/rtc/m48t59: Simplify m48t59_init()
On 9/30/20 10:35 AM, Mark Cave-Ayland wrote:
> On 14/09/2020 11:24, Philippe Mathieu-Daudé wrote:
>
>> As the 'io_base' argument of m48t59_init() is unused (set to 0),
>> remove it to simplify.
>> To create a device on the ISA bus, m48t59_init_isa() is the
>> preferred function to use.
>>
>> Signed-off-by: Philippe Mathieu-Daudé
>> ---
>> include/hw/rtc/m48t59.h | 2 +-
>> hw/ppc/ppc405_boards.c | 2 +-
>> hw/rtc/m48t59.c | 10 ++
>> hw/sparc/sun4m.c| 2 +-
>> hw/sparc64/sun4u.c | 2 +-
>> 5 files changed, 6 insertions(+), 12 deletions(-)
>>
>> diff --git a/include/hw/rtc/m48t59.h b/include/hw/rtc/m48t59.h
>> index 04abedf3b2b..62297ee0db1 100644
>> --- a/include/hw/rtc/m48t59.h
>> +++ b/include/hw/rtc/m48t59.h
>> @@ -50,7 +50,7 @@ struct NvramClass {
>> Nvram *m48t59_init_isa(ISABus *bus, uint32_t io_base, uint16_t size,
>> int base_year, int type);
>> Nvram *m48t59_init(qemu_irq IRQ, hwaddr mem_base,
>> - uint32_t io_base, uint16_t size, int base_year,
>> + uint16_t size, int base_year,
>> int type);
>>
>> #endif /* HW_M48T59_H */
>> diff --git a/hw/ppc/ppc405_boards.c b/hw/ppc/ppc405_boards.c
>> index 6198ec1035b..93ffee801a3 100644
>> --- a/hw/ppc/ppc405_boards.c
>> +++ b/hw/ppc/ppc405_boards.c
>> @@ -227,7 +227,7 @@ static void ref405ep_init(MachineState *machine)
>> /* Register FPGA */
>> ref405ep_fpga_init(sysmem, 0xF030);
>> /* Register NVRAM */
>> -m48t59_init(NULL, 0xF000, 0, 8192, 1968, 8);
>> +m48t59_init(NULL, 0xF000, 8192, 1968, 8);
>> /* Load kernel */
>> linux_boot = (kernel_filename != NULL);
>> if (linux_boot) {
>> diff --git a/hw/rtc/m48t59.c b/hw/rtc/m48t59.c
>> index 6525206976b..2d6a095c4e4 100644
>> --- a/hw/rtc/m48t59.c
>> +++ b/hw/rtc/m48t59.c
>> @@ -566,7 +566,7 @@ const MemoryRegionOps m48t59_io_ops = {
>>
>> /* Initialisation routine */
>> Nvram *m48t59_init(qemu_irq IRQ, hwaddr mem_base,
>> - uint32_t io_base, uint16_t size, int base_year,
>> + uint16_t size, int base_year,
>> int model)
>> {
>> DeviceState *dev;
>> @@ -584,13 +584,7 @@ Nvram *m48t59_init(qemu_irq IRQ, hwaddr mem_base,
>> s = SYS_BUS_DEVICE(dev);
>> sysbus_realize_and_unref(s, &error_fatal);
>> sysbus_connect_irq(s, 0, IRQ);
>> -if (io_base != 0) {
>> -memory_region_add_subregion(get_system_io(), io_base,
>> -sysbus_mmio_get_region(s, 1));
>> -}
>> -if (mem_base != 0) {
>> -sysbus_mmio_map(s, 0, mem_base);
>> -}
>> +sysbus_mmio_map(s, 0, mem_base);
>>
>> return NVRAM(s);
>> }
>> diff --git a/hw/sparc/sun4m.c b/hw/sparc/sun4m.c
>> index 947b69d1597..56a0d38f274 100644
>> --- a/hw/sparc/sun4m.c
>> +++ b/hw/sparc/sun4m.c
>> @@ -970,7 +970,7 @@ static void sun4m_hw_init(const struct sun4m_hwdef
>> *hwdef,
>> create_unimplemented_device("SUNW,sx", hwdef->sx_base, 0x2000);
>> }
>>
>> -nvram = m48t59_init(slavio_irq[0], hwdef->nvram_base, 0, 0x2000, 1968,
>> 8);
>> +nvram = m48t59_init(slavio_irq[0], hwdef->nvram_base, 0x2000, 1968, 8);
>>
>> slavio_timer_init_all(hwdef->counter_base, slavio_irq[19],
>> slavio_cpu_irq, smp_cpus);
>>
>> diff --git a/hw/sparc64/sun4u.c b/hw/sparc64/sun4u.c
>> index b4aabfc076f..1cc57b030a7 100644
>> --- a/hw/sparc64/sun4u.c
>> +++ b/hw/sparc64/sun4u.c
>> @@ -675,7 +675,7 @@ static void sun4uv_init(MemoryRegion *address_space_mem,
>> pci_ide_create_devs(pci_dev);
>>
>> /* Map NVRAM into I/O (ebus) space */
>> -nvram = m48t59_init(NULL, 0, 0, NVRAM_SIZE, 1968, 59);
>> +nvram = m48t59_init(NULL, 0, NVRAM_SIZE, 1968, 59);
>> s = SYS_BUS_DEVICE(nvram);
>> memory_region_add_subregion(pci_address_space_io(ebus), 0x2000,
>> sysbus_mmio_get_region(s, 0));
>
> Looks good to me. In fact, if you're working in this area there are a couple
> of other
> quick wins here too:
>
> - Remove m48t59_init() and replace with QOM/qdev properties
>
> - Remove m48t59_init_isa() as this seems to be unused, along with the
> associated
> complexity of handling the m48txx_isa_info[] array
OK.
>
> Anyhow:
>
> Reviewed-by: Mark Cave-Ayland
Thanks!
>
>
> ATB,
>
> Mark.
>
Re: [PATCH RFC 00/14] fix some comment spelling errors
On 9/30/20 11:53 AM, zhaolichang wrote: > I found that there are many spelling errors in the comments of qemu/target/. > I used spellcheck to check the spelling errors and found some errors in the > folder. > > The checkpatch.pl file in the Linux kernel can check spelling errors in > patches. > I'm trying to add this function to the checkpatch.pl in qemu, > so that no similar spelling errors will occur in the feture. > It's not done yet and I will commit the patch when it's done. > > Signed-off-by: zhaolichang BTW your git-config is still messy, maybe you missed my previous comment: https://www.mail-archive.com/qemu-devel@nongnu.org/msg741642.html
Re: [PATCH v4 00/12] Support disabling TCG on ARM (part 2)
On 9/30/20 9:58 AM, Igor Mammedov wrote:
> On Wed, 30 Sep 2020 00:43:43 +0200
> Philippe Mathieu-Daudé wrote:
>
>> Cover from Samuel Ortiz from (part 1) [1]:
>>
>> This patchset allows for building and running ARM targets with TCG
>> disabled. [...]
>>
>> The rationale behind this work comes from the NEMU project where we're
>> trying to only support x86 and ARM 64-bit architectures, without
>> including the TCG code base. We can only do so if we can build and run
>> ARM binaries with TCG disabled.
>
> I don't recall exact reason but TCG variant is used by bios-tables-test
> to test arm/virt so it will probably break that
> (it has something to do with how KVM uses CPU/GIC, which was making
> ACPI tables not stable (i.e. depend on host), so comparison with master
> tables was failing)
Not a problem, we can restrict bios-tables-test to TCG.
I don't expect the KVM-only build being able to run many
of our current tests, as most of them expect TCG.
I'll have a look at restricting the TCG-dependent tests
after this series get accepted.
>
>>
>> v4 almost 2 years later... [2]:
>> - Rebased on Meson
>> - Addressed Richard review comments
>> - Addressed Claudio review comments
>>
>> v3 almost 18 months later [3]:
>> - Rebased
>> - Addressed Thomas review comments
>> - Added Travis-CI job to keep building --disable-tcg on ARM
>>
>> v2 [4]:
>> - Addressed review comments from Richard and Thomas from v1 [1]
>>
>> Regards,
>>
>> Phil.
>>
>> [1]: https://lists.gnu.org/archive/html/qemu-devel/2018-11/msg02451.html
>> [2]: https://www.mail-archive.com/qemu-devel@nongnu.org/msg689168.html
>> [3]: https://www.mail-archive.com/qemu-devel@nongnu.org/msg641796.html
>> [4]: https://lists.gnu.org/archive/html/qemu-devel/2019-08/msg05003.html
>>
>> Green CI:
>> - https://cirrus-ci.com/build/4572961761918976
>> - https://gitlab.com/philmd/qemu/-/pipelines/196047779
>> - https://travis-ci.org/github/philmd/qemu/builds/731370972
>>
>> Based-on: <20200929125609.1088330-1-phi...@redhat.com>
>> "hw/arm: Restrict APEI tables generation to the 'virt' machine"
>> https://www.mail-archive.com/qemu-devel@nongnu.org/msg745792.html
>>
>> Philippe Mathieu-Daudé (10):
>> accel/tcg: Add stub for cpu_loop_exit()
>> meson: Allow optional target/${ARCH}/Kconfig
>> target/arm: Select SEMIHOSTING if TCG is available
>> target/arm: Restrict ARMv4 cpus to TCG accel
>> target/arm: Restrict ARMv5 cpus to TCG accel
>> target/arm: Restrict ARMv6 cpus to TCG accel
>> target/arm: Restrict ARMv7 R-profile cpus to TCG accel
>> target/arm: Restrict ARMv7 M-profile cpus to TCG accel
>> target/arm: Reorder meson.build rules
>> .travis.yml: Add a KVM-only Aarch64 job
>>
>> Samuel Ortiz (1):
>> target/arm: Do not build TCG objects when TCG is off
>>
>> Thomas Huth (1):
>> target/arm: Make m_helper.c optional via CONFIG_ARM_V7M
>>
>> default-configs/arm-softmmu.mak | 3 --
>> meson.build | 8 +++-
>> target/arm/cpu.h| 12 --
>> accel/stubs/tcg-stub.c | 5 +++
>> target/arm/cpu_tcg.c| 4 +-
>> target/arm/helper.c | 7
>> target/arm/m_helper-stub.c | 73 +
>> .travis.yml | 35
>> hw/arm/Kconfig | 32 +++
>> target/arm/Kconfig | 4 ++
>> target/arm/meson.build | 40 +++---
>> 11 files changed, 184 insertions(+), 39 deletions(-)
>> create mode 100644 target/arm/m_helper-stub.c
>> create mode 100644 target/arm/Kconfig
>>
>
Re: [PATCH RFC 09/14] sh4/: fix some comment spelling errors
On 9/30/20 11:53 AM, zhaolichang wrote: > I found that there are many spelling errors in the comments of > qemu/target/sh4. > I used spellcheck to check the spelling errors and found some errors in the > folder. > > Signed-off-by: zhaolichang > --- > target/sh4/cpu.h | 2 +- > target/sh4/op_helper.c | 2 +- > target/sh4/translate.c | 2 +- > 3 files changed, 3 insertions(+), 3 deletions(-) Reviewed-by: Philippe Mathieu-Daudé
Re: [PATCH RFC 11/14] avr/: fix some comment spelling errors
On 9/30/20 11:53 AM, zhaolichang wrote: > I found that there are many spelling errors in the comments of > qemu/target/avr. > I used spellcheck to check the spelling errors and found some errors in the > folder. > > Signed-off-by: zhaolichang > --- > target/avr/helper.c | 6 +++--- > 1 file changed, 3 insertions(+), 3 deletions(-) Reviewed-by: Philippe Mathieu-Daudé
