I found that there are many spelling errors in the comments of
qemu/target/riscv.
I used spellcheck to check the spelling errors and found some errors in the
folder.
Signed-off-by: zhaolichang <zhaolich...@huawei.com>
---
target/riscv/cpu.c | 2 +-
target/riscv/cpu_bits.h | 2 +-
target/riscv/csr.c | 6 +++---
target/riscv/vector_helper.c | 2 +-
4 files changed, 6 insertions(+), 6 deletions(-)
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index 0bbfd7f..f40a0b2 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -472,7 +472,7 @@ static void riscv_cpu_realize(DeviceState *dev, Error
**errp)
return;
}
} else {
- qemu_log("vector verison is not specified, "
+ qemu_log("vector version is not specified, "
"use the default value v0.7.1\n");
}
set_vext_version(env, vext_version);
diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h
index bd36062..6e11555 100644
--- a/target/riscv/cpu_bits.h
+++ b/target/riscv/cpu_bits.h
@@ -536,7 +536,7 @@
/* Leaf page shift amount */
#define PGSHIFT 12
-/* Default Reset Vector adress */
+/* Default Reset Vector address */
#define DEFAULT_RSTVEC 0x1000
/* Exception causes */
diff --git a/target/riscv/csr.c b/target/riscv/csr.c
index 26ae347..559db11 100644
--- a/target/riscv/csr.c
+++ b/target/riscv/csr.c
@@ -624,7 +624,7 @@ static int write_mcounteren(CPURISCVState *env, int csrno,
target_ulong val)
return 0;
}
-/* This regiser is replaced with CSR_MCOUNTINHIBIT in 1.11.0 */
+/* This register is replaced with CSR_MCOUNTINHIBIT in 1.11.0 */
static int read_mscounteren(CPURISCVState *env, int csrno, target_ulong *val)
{
if (env->priv_ver < PRIV_VERSION_1_11_0) {
@@ -634,7 +634,7 @@ static int read_mscounteren(CPURISCVState *env, int csrno,
target_ulong *val)
return 0;
}
-/* This regiser is replaced with CSR_MCOUNTINHIBIT in 1.11.0 */
+/* This register is replaced with CSR_MCOUNTINHIBIT in 1.11.0 */
static int write_mscounteren(CPURISCVState *env, int csrno, target_ulong val)
{
if (env->priv_ver < PRIV_VERSION_1_11_0) {
@@ -1278,7 +1278,7 @@ int riscv_csrrw(CPURISCVState *env, int csrno,
target_ulong *ret_value,
!riscv_cpu_virt_enabled(env)) {
/*
* We are in S mode without virtualisation, therefore we are in HS
Mode.
- * Add 1 to the effective privledge level to allow us to access the
+ * Add 1 to the effective privilege level to allow us to access the
* Hypervisor CSRs.
*/
effective_priv++;
diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c
index a156573..fa89a6e 100644
--- a/target/riscv/vector_helper.c
+++ b/target/riscv/vector_helper.c
@@ -709,7 +709,7 @@ typedef void vext_amo_noatomic_fn(void *vs3, target_ulong
addr,
uint32_t wd, uint32_t idx, CPURISCVState
*env,
uintptr_t retaddr);
-/* no atomic opreation for vector atomic insructions */
+/* no atomic operation for vector atomic insructions */
#define DO_SWAP(N, M) (M)
#define DO_AND(N, M) (N & M)
#define DO_XOR(N, M) (N ^ M)
--
2.26.2.windows.1
