Re: [PATCH v8 4/7] scripts: add block-coroutine-wrapper.py

[Vladimir Sementsov-Ogievskiy]

24.09.2020 03:00, Eric Blake wrote:

On 9/15/20 3:02 PM, Vladimir Sementsov-Ogievskiy wrote:

15.09.2020 19:44, Vladimir Sementsov-Ogievskiy wrote:

We have a very frequent pattern of creating coroutine from function
with several arguments:

   - create structure to pack parameters
   - create _entry function to call original function taking parameters
 from struct
   - do different magic to handle completion: set ret to NOT_DONE or
 EINPROGRESS or use separate bool field
   - fill the struct and create coroutine from _entry function and this
 struct as a parameter
   - do coroutine enter and BDRV_POLL_WHILE loop

Let's reduce code duplication by generating coroutine wrappers.

This patch adds scripts/block-coroutine-wrapper.py together with some
friends, which will generate functions with declared prototypes marked
by 'generated_co_wrapper' specifier.





 4. add header with generated_co_wrapper declaration into
    COROUTINE_HEADERS list in Makefile


This phrase is out-of-date.  I also see 4 steps here,...



Still, no function is now marked, this work is for the following
commit.

Signed-off-by: Vladimir Sementsov-Ogievskiy
---
  docs/devel/block-coroutine-wrapper.rst |  54 +++
  block/block-gen.h  |  49 +++
  include/block/block.h  |  10 ++
  block/meson.build  |   8 ++
  scripts/block-coroutine-wrapper.py | 187 +
  5 files changed, 308 insertions(+)
  create mode 100644 docs/devel/block-coroutine-wrapper.rst
  create mode 100644 block/block-gen.h
  create mode 100755 scripts/block-coroutine-wrapper.py



Also needed:

diff --git a/docs/devel/index.rst b/docs/devel/index.rst
index 04773ce076..cb0abe1e69 100644
--- a/docs/devel/index.rst
+++ b/docs/devel/index.rst
@@ -31,3 +31,4 @@ Contents:
 reset
 s390-dasd-ipl
 clocks
+   block-coroutine-wrapper


I've squashed that in.


+++ b/docs/devel/block-coroutine-wrapper.rst
@@ -0,0 +1,54 @@
+===
+block-coroutine-wrapper
+===
+
+A lot of functions in QEMJ block layer (see ``block/*``) can by called


QEMU

s/by called only/only be called/


+only in coroutine context. Such functions are normally marked by


by the


+coroutine_fn specifier. Still, sometimes we need to call them from
+non-coroutine context, for this we need to start a coroutine, run the



s/context,/context;/


+needed function from it and wait for coroutine finish in


in a


+BDRV_POLL_WHILE() loop. To run a coroutine we need a function with one
+void* argument. So for each coroutine_fn function, which needs


needs a


+non-coroutine interface, we should define a structure to pack the
+parameters, define a separate function to unpack the parameters and
+call the original function and finally define a new interface function
+with same list of arguments as original one, which will pack the
+parameters into a struct, create a coroutine, run it and wait in
+BDRV_POLL_WHILE() loop. It's boring to create such wrappers by hand, so
+we have a script to generate them.

+Usage
+=
+
+Assume we have defined ``coroutine_fn`` function
+``bdrv_co_foo()`` and need a non-coroutine interface for it,
+called ``bdrv_foo()``. In this case the script can help. To
+trigger the generation:
+
+1. You need ``bdrv_foo`` declaration somewhere (for example in
+   ``block/coroutines.h`` with ``generated_co_wrapper`` mark,
+   like this:


Missing a closing ).


+
+.. code-block:: c
+
+    int generated_co_wrapper bdrv_foor();


s/foor/foo/


+
+2. You need to feed this declaration to block-coroutine-wrapper script.


to the block-


+   For this, add .h (or .c) file with the declaration to
+   ``input: files(...)`` list of ``block_gen_c`` target declaration in
+   ``block/meson.build``
+
+You are done. On build, coroutine wrappers will be generated in


s/On/During the/


+``/block/block-gen.c``.


...but 2 in the .rst.  Presumably, the .rst steps belong in the commit message 
as well.


+++ b/block/block-gen.h



+++ b/include/block/block.h
@@ -10,6 +10,16 @@
 #include "block/blockjob.h"
 #include "qemu/hbitmap.h"

+/*
+ * generated_co_wrapper
+ *
+ * Function specifier, which does nothing but marking functions to be


s/marking/mark/


+ * generated by scripts/block-coroutine-wrapper.py
+ *
+ * Read more in docs/devel/block-coroutine-wrapper.rst
+ */
+#define generated_co_wrapper
+
 /* block.c */
 typedef struct BlockDriver BlockDriver;
 typedef struct BdrvChild BdrvChild;
diff --git a/block/meson.build b/block/meson.build
index a3e56b7cd1..88ad73583a 100644
--- a/block/meson.build
+++ b/block/meson.build
@@ -107,6 +107,14 @@ module_block_h = custom_target('module_block.h',
    command: [module_block_py, '@OUTPUT0@', modsrc])
 block_ss.add(module_block_h)

+wrapper_py = find_program('../scripts/block-coroutine-wrapper.py')
+block_gen_c = custom_target('block-gen.c',
+    output: 'block-gen.c',
+   

[RFC PATCH v3 0/7] Use ACPI PCI hot-plug for Q35

[Julia Suvorova]

The patch set consists of two parts:
patches 1-4: introduce new feature
 'acpi-pci-hotplug-with-bridge-support' on Q35
patches 5-7: make the feature default along with changes in ACPI tables

This way maintainers can decide which way to choose without breaking
the patch set.

With the feature disabled Q35 falls back to the native hot-plug.

Pros
* no racy behavior during boot (see 110c477c2ed)
* eject is possible - according to PCIe spec, attention button
  press should lead to power off, and then the adapter should be
  removed manually. As there is no power down state exists in QEMU,
  we cannot distinguish between an eject and a power down
  request.
* no delay during deleting - after the actual power off software
  must wait at least 1 second before indicating about it. This case
  is quite important for users, it even has its own bug:
  https://bugzilla.redhat.com/show_bug.cgi?id=1594168
* no timer-based behavior - in addition to the previous example,
  the attention button has a 5-second waiting period, during which
  the operation can be canceled with a second press. While this
  looks fine for manual button control, automation will result in
  the need to queue or drop events, and the software receiving
  events in all sort of unspecified combinations of attention/power
  indicator states, which is racy and uppredictable.
* fixes:
* https://bugzilla.redhat.com/show_bug.cgi?id=1752465
* https://bugzilla.redhat.com/show_bug.cgi?id=1690256

Cons:
* lose per-port control over hot-plug (can be resolved)
* no access to possible features presented in slot capabilities
  (this is only surprise removal AFAIK)

v3:
* drop change of _OSC to allow SHPC on hotplugged bridges
* use 'acpi-root-pci-hotplug'
* add migration states [Igor]
* minor style changes

v2:
* new ioport range for acpiphp [Gerd]
* drop find_pci_host() [Igor]
* explain magic numbers in _OSC [Igor]
* drop build_q35_pci_hotplug() wrapper [Igor]

Julia Suvorova (7):
  hw/acpi/pcihp: Enhance acpi_pcihp_disable_root_bus() to support Q35
  hw/i386/acpi-build: Add ACPI PCI hot-plug methods to Q35
  hw/pci/pcie: Do not initialize slot capability if acpihp is used
  hw/acpi/ich9: Enable ACPI PCI hot-plug
  bios-tables-test: Allow changes in DSDT ACPI tables
  hw/acpi/ich9: Set ACPI PCI hot-plug as default
  bios-tables-test: Update golden binaries

 hw/i386/acpi-build.h  |   7 
 include/hw/acpi/ich9.h|   5 +++
 include/hw/acpi/pcihp.h   |   3 +-
 hw/acpi/ich9.c|  67 ++
 hw/acpi/pcihp.c   |  16 ---
 hw/acpi/piix4.c   |   4 +-
 hw/i386/acpi-build.c  |  31 --
 hw/i386/pc.c  |   1 +
 hw/pci/pcie.c |  16 +++
 tests/data/acpi/q35/DSDT  | Bin 7678 -> 7950 bytes
 tests/data/acpi/q35/DSDT.acpihmat | Bin 9002 -> 9274 bytes
 tests/data/acpi/q35/DSDT.bridge   | Bin 7695 -> 9865 bytes
 tests/data/acpi/q35/DSDT.cphp | Bin 8141 -> 8413 bytes
 tests/data/acpi/q35/DSDT.dimmpxm  | Bin 9331 -> 9603 bytes
 tests/data/acpi/q35/DSDT.ipmibt   | Bin 7753 -> 8025 bytes
 tests/data/acpi/q35/DSDT.memhp| Bin 9037 -> 9309 bytes
 tests/data/acpi/q35/DSDT.mmio64   | Bin 8808 -> 9080 bytes
 tests/data/acpi/q35/DSDT.numamem  | Bin 7684 -> 7956 bytes
 tests/data/acpi/q35/DSDT.tis  | Bin 8283 -> 8555 bytes
 19 files changed, 129 insertions(+), 21 deletions(-)

-- 
2.25.4

[RFC PATCH v3 5/7] bios-tables-test: Allow changes in DSDT ACPI tables

[Julia Suvorova]

All DSDT Q35 tables will be modified because ACPI hot-plug is enabled
by default.

Signed-off-by: Julia Suvorova 
---
 tests/qtest/bios-tables-test-allowed-diff.h | 10 ++
 1 file changed, 10 insertions(+)

diff --git a/tests/qtest/bios-tables-test-allowed-diff.h 
b/tests/qtest/bios-tables-test-allowed-diff.h
index dfb8523c8b..84f56b14db 100644
--- a/tests/qtest/bios-tables-test-allowed-diff.h
+++ b/tests/qtest/bios-tables-test-allowed-diff.h
@@ -1 +1,11 @@
 /* List of comma-separated changed AML files to ignore */
+"tests/data/acpi/q35/DSDT",
+"tests/data/acpi/q35/DSDT.tis",
+"tests/data/acpi/q35/DSDT.bridge",
+"tests/data/acpi/q35/DSDT.mmio64",
+"tests/data/acpi/q35/DSDT.ipmibt",
+"tests/data/acpi/q35/DSDT.cphp",
+"tests/data/acpi/q35/DSDT.memhp",
+"tests/data/acpi/q35/DSDT.acpihmat",
+"tests/data/acpi/q35/DSDT.numamem",
+"tests/data/acpi/q35/DSDT.dimmpxm",
-- 
2.25.4

[RFC PATCH v3 1/7] hw/acpi/pcihp: Enhance acpi_pcihp_disable_root_bus() to support Q35

[Julia Suvorova]

PCI Express does not allow hot-plug on pcie.0. Check for Q35 in
acpi_pcihp_disable_root_bus() to be able to forbid hot-plug using the
'acpi-root-pci-hotplug' flag.

Signed-off-by: Julia Suvorova 
---
 hw/acpi/pcihp.c | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/hw/acpi/pcihp.c b/hw/acpi/pcihp.c
index 39b1f74442..ff23104aea 100644
--- a/hw/acpi/pcihp.c
+++ b/hw/acpi/pcihp.c
@@ -107,13 +107,14 @@ static void acpi_set_pci_info(void)
 static void acpi_pcihp_disable_root_bus(void)
 {
 static bool root_hp_disabled;
+Object *host = acpi_get_i386_pci_host();
 PCIBus *bus;
 
 if (root_hp_disabled) {
 return;
 }
 
-bus = find_i440fx();
+bus = PCI_HOST_BRIDGE(host)->bus;
 if (bus) {
 /* setting the hotplug handler to NULL makes the bus non-hotpluggable 
*/
 qbus_set_hotplug_handler(BUS(bus), NULL);
-- 
2.25.4

[RFC PATCH v3 2/7] hw/i386/acpi-build: Add ACPI PCI hot-plug methods to Q35

[Julia Suvorova]

Implement notifications and gpe to support q35 ACPI PCI hot-plug.
Use 0xcc4 - 0xcd7 range for 'acpi-pci-hotplug' io ports.

Signed-off-by: Julia Suvorova 
---
 hw/i386/acpi-build.h|  4 
 include/hw/acpi/ich9.h  |  2 ++
 include/hw/acpi/pcihp.h |  3 ++-
 hw/acpi/pcihp.c |  8 
 hw/acpi/piix4.c |  4 +++-
 hw/i386/acpi-build.c| 27 ---
 6 files changed, 31 insertions(+), 17 deletions(-)

diff --git a/hw/i386/acpi-build.h b/hw/i386/acpi-build.h
index 74df5fc612..487ec7710f 100644
--- a/hw/i386/acpi-build.h
+++ b/hw/i386/acpi-build.h
@@ -5,6 +5,10 @@
 
 extern const struct AcpiGenericAddress x86_nvdimm_acpi_dsmio;
 
+/* PCI Hot-plug registers bases. See docs/spec/acpi_pci_hotplug.txt */
+#define ACPI_PCIHP_SEJ_BASE 0x8
+#define ACPI_PCIHP_BNMR_BASE 0x10
+
 void acpi_setup(void);
 
 #endif
diff --git a/include/hw/acpi/ich9.h b/include/hw/acpi/ich9.h
index 28a53181cb..4d19571ed7 100644
--- a/include/hw/acpi/ich9.h
+++ b/include/hw/acpi/ich9.h
@@ -28,6 +28,8 @@
 #include "hw/acpi/acpi_dev_interface.h"
 #include "hw/acpi/tco.h"
 
+#define ACPI_PCIHP_ADDR_ICH9 0x0cc4
+
 typedef struct ICH9LPCPMRegs {
 /*
  * In ich9 spec says that pm1_cnt register is 32bit width and
diff --git a/include/hw/acpi/pcihp.h b/include/hw/acpi/pcihp.h
index 02f4665767..ce49fb03b9 100644
--- a/include/hw/acpi/pcihp.h
+++ b/include/hw/acpi/pcihp.h
@@ -54,7 +54,8 @@ typedef struct AcpiPciHpState {
 } AcpiPciHpState;
 
 void acpi_pcihp_init(Object *owner, AcpiPciHpState *, PCIBus *root,
- MemoryRegion *address_space_io, bool bridges_enabled);
+ MemoryRegion *address_space_io, bool bridges_enabled,
+ uint16_t io_base);
 
 void acpi_pcihp_device_pre_plug_cb(HotplugHandler *hotplug_dev,
DeviceState *dev, Error **errp);
diff --git a/hw/acpi/pcihp.c b/hw/acpi/pcihp.c
index ff23104aea..bb457bc279 100644
--- a/hw/acpi/pcihp.c
+++ b/hw/acpi/pcihp.c
@@ -38,7 +38,6 @@
 #include "qom/qom-qobject.h"
 #include "trace.h"
 
-#define ACPI_PCIHP_ADDR 0xae00
 #define ACPI_PCIHP_SIZE 0x0014
 #define PCI_UP_BASE 0x
 #define PCI_DOWN_BASE 0x0004
@@ -381,12 +380,13 @@ static const MemoryRegionOps acpi_pcihp_io_ops = {
 };
 
 void acpi_pcihp_init(Object *owner, AcpiPciHpState *s, PCIBus *root_bus,
- MemoryRegion *address_space_io, bool bridges_enabled)
+ MemoryRegion *address_space_io, bool bridges_enabled,
+ uint16_t io_base)
 {
 s->io_len = ACPI_PCIHP_SIZE;
-s->io_base = ACPI_PCIHP_ADDR;
+s->io_base = io_base;
 
-s->root= root_bus;
+s->root = root_bus;
 s->legacy_piix = !bridges_enabled;
 
 memory_region_init_io(&s->io, owner, &acpi_pcihp_io_ops, s,
diff --git a/hw/acpi/piix4.c b/hw/acpi/piix4.c
index 832f8fba82..a505ab5bcf 100644
--- a/hw/acpi/piix4.c
+++ b/hw/acpi/piix4.c
@@ -50,6 +50,8 @@
 #define GPE_BASE 0xafe0
 #define GPE_LEN 4
 
+#define ACPI_PCIHP_ADDR_PIIX4 0xae00
+
 struct pci_status {
 uint32_t up; /* deprecated, maintained for migration compatibility */
 uint32_t down;
@@ -597,7 +599,7 @@ static void piix4_acpi_system_hot_add_init(MemoryRegion 
*parent,
 memory_region_add_subregion(parent, GPE_BASE, &s->io_gpe);
 
 acpi_pcihp_init(OBJECT(s), &s->acpi_pci_hotplug, bus, parent,
-s->use_acpi_hotplug_bridge);
+s->use_acpi_hotplug_bridge, ACPI_PCIHP_ADDR_PIIX4);
 
 s->cpu_hotplug_legacy = true;
 object_property_add_bool(OBJECT(s), "cpu-hotplug-legacy",
diff --git a/hw/i386/acpi-build.c b/hw/i386/acpi-build.c
index 0e0535d2e3..cf503b16af 100644
--- a/hw/i386/acpi-build.c
+++ b/hw/i386/acpi-build.c
@@ -201,10 +201,6 @@ static void acpi_get_pm_info(MachineState *machine, 
AcpiPmInfo *pm)
 /* w2k requires FADT(rev1) or it won't boot, keep PC compatible */
 pm->fadt.rev = 1;
 pm->cpu_hp_io_base = PIIX4_CPU_HOTPLUG_IO_BASE;
-pm->pcihp_io_base =
-object_property_get_uint(obj, ACPI_PCIHP_IO_BASE_PROP, NULL);
-pm->pcihp_io_len =
-object_property_get_uint(obj, ACPI_PCIHP_IO_LEN_PROP, NULL);
 }
 if (lpc) {
 struct AcpiGenericAddress r = { .space_id = AML_AS_SYSTEM_IO,
@@ -214,6 +210,10 @@ static void acpi_get_pm_info(MachineState *machine, 
AcpiPmInfo *pm)
 pm->fadt.flags |= 1 << ACPI_FADT_F_RESET_REG_SUP;
 pm->cpu_hp_io_base = ICH9_CPU_HOTPLUG_IO_BASE;
 }
+pm->pcihp_io_base =
+object_property_get_uint(obj, ACPI_PCIHP_IO_BASE_PROP, NULL);
+pm->pcihp_io_len =
+object_property_get_uint(obj, ACPI_PCIHP_IO_LEN_PROP, NULL);
 
 /* The above need not be conditional on machine type because the reset port
  * happens to be the same on PIIX (pc) and ICH9 (q35). */
@@ -472,7 +472,7 @@ static void build_append_pci_bus_devices(Aml *parent_scope, 
PCIBus *bus,
 QLIST_FOREACH(sec, &bus->child, sibling) {
 int32_t devfn =

[RFC PATCH v3 4/7] hw/acpi/ich9: Enable ACPI PCI hot-plug

[Julia Suvorova]

Add acpi_pcihp to ich9_pm as part of
'acpi-pci-hotplug-with-bridge-support' option. Set default to false.

Signed-off-by: Julia Suvorova 
---
 hw/i386/acpi-build.h   |  1 +
 include/hw/acpi/ich9.h |  3 ++
 hw/acpi/ich9.c | 67 ++
 hw/acpi/pcihp.c|  5 +++-
 hw/i386/acpi-build.c   |  2 +-
 5 files changed, 76 insertions(+), 2 deletions(-)

diff --git a/hw/i386/acpi-build.h b/hw/i386/acpi-build.h
index 4c5bfb3d0b..39f143830a 100644
--- a/hw/i386/acpi-build.h
+++ b/hw/i386/acpi-build.h
@@ -10,6 +10,7 @@ extern const struct AcpiGenericAddress x86_nvdimm_acpi_dsmio;
 #define ACPI_PCIHP_BNMR_BASE 0x10
 
 void acpi_setup(void);
+Object *acpi_get_i386_pci_host(void);
 
 Object *object_resolve_type_unambiguous(const char *typename);
 
diff --git a/include/hw/acpi/ich9.h b/include/hw/acpi/ich9.h
index 4d19571ed7..833e62fefe 100644
--- a/include/hw/acpi/ich9.h
+++ b/include/hw/acpi/ich9.h
@@ -24,6 +24,7 @@
 #include "hw/acpi/acpi.h"
 #include "hw/acpi/cpu_hotplug.h"
 #include "hw/acpi/cpu.h"
+#include "hw/acpi/pcihp.h"
 #include "hw/acpi/memory_hotplug.h"
 #include "hw/acpi/acpi_dev_interface.h"
 #include "hw/acpi/tco.h"
@@ -55,6 +56,8 @@ typedef struct ICH9LPCPMRegs {
 AcpiCpuHotplug gpe_cpu;
 CPUHotplugState cpuhp_state;
 
+bool use_acpi_hotplug_bridge;
+AcpiPciHpState acpi_pci_hotplug;
 MemHotplugState acpi_memory_hotplug;
 
 uint8_t disable_s3;
diff --git a/hw/acpi/ich9.c b/hw/acpi/ich9.c
index 6a19070cec..987f23e388 100644
--- a/hw/acpi/ich9.c
+++ b/hw/acpi/ich9.c
@@ -218,6 +218,26 @@ static const VMStateDescription vmstate_cpuhp_state = {
 }
 };
 
+static bool vmstate_test_use_pcihp(void *opaque)
+{
+ICH9LPCPMRegs *s = opaque;
+
+return s->use_acpi_hotplug_bridge;
+}
+
+static const VMStateDescription vmstate_pcihp_state = {
+.name = "ich9_pm/pcihp",
+.version_id = 1,
+.minimum_version_id = 1,
+.needed = vmstate_test_use_pcihp,
+.fields  = (VMStateField[]) {
+VMSTATE_PCI_HOTPLUG(acpi_pci_hotplug,
+ICH9LPCPMRegs,
+NULL),
+VMSTATE_END_OF_LIST()
+}
+};
+
 const VMStateDescription vmstate_ich9_pm = {
 .name = "ich9_pm",
 .version_id = 1,
@@ -239,6 +259,7 @@ const VMStateDescription vmstate_ich9_pm = {
 &vmstate_memhp_state,
 &vmstate_tco_io_state,
 &vmstate_cpuhp_state,
+&vmstate_pcihp_state,
 NULL
 }
 };
@@ -260,6 +281,7 @@ static void pm_reset(void *opaque)
 }
 pm->smi_en_wmask = ~0;
 
+acpi_pcihp_reset(&pm->acpi_pci_hotplug, true);
 acpi_update_sci(&pm->acpi_regs, pm->irq);
 }
 
@@ -298,6 +320,18 @@ void ich9_pm_init(PCIDevice *lpc_pci, ICH9LPCPMRegs *pm,
 pm->enable_tco = true;
 acpi_pm_tco_init(&pm->tco_regs, &pm->io);
 
+if (pm->use_acpi_hotplug_bridge) {
+acpi_pcihp_init(OBJECT(lpc_pci),
+&pm->acpi_pci_hotplug,
+pci_get_bus(lpc_pci),
+pci_address_space_io(lpc_pci),
+true,
+ACPI_PCIHP_ADDR_ICH9);
+
+qbus_set_hotplug_handler(BUS(pci_get_bus(lpc_pci)),
+ OBJECT(lpc_pci));
+}
+
 pm->irq = sci_irq;
 qemu_register_reset(pm_reset, pm);
 pm->powerdown_notifier.notify = pm_powerdown_req;
@@ -369,6 +403,20 @@ static void ich9_pm_set_enable_tco(Object *obj, bool 
value, Error **errp)
 s->pm.enable_tco = value;
 }
 
+static bool ich9_pm_get_acpi_pci_hotplug(Object *obj, Error **errp)
+{
+ICH9LPCState *s = ICH9_LPC_DEVICE(obj);
+
+return s->pm.use_acpi_hotplug_bridge;
+}
+
+static void ich9_pm_set_acpi_pci_hotplug(Object *obj, bool value,
+   Error **errp)
+{
+ICH9LPCState *s = ICH9_LPC_DEVICE(obj);
+
+s->pm.use_acpi_hotplug_bridge = value;
+}
 void ich9_pm_add_properties(Object *obj, ICH9LPCPMRegs *pm)
 {
 static const uint32_t gpe0_len = ICH9_PMIO_GPE0_LEN;
@@ -377,6 +425,7 @@ void ich9_pm_add_properties(Object *obj, ICH9LPCPMRegs *pm)
 pm->disable_s3 = 0;
 pm->disable_s4 = 0;
 pm->s4_val = 2;
+pm->use_acpi_hotplug_bridge = false;
 
 object_property_add_uint32_ptr(obj, ACPI_PM_PROP_PM_IO_BASE,
&pm->pm_io_base, OBJ_PROP_FLAG_READ);
@@ -400,6 +449,9 @@ void ich9_pm_add_properties(Object *obj, ICH9LPCPMRegs *pm)
 object_property_add_bool(obj, ACPI_PM_PROP_TCO_ENABLED,
  ich9_pm_get_enable_tco,
  ich9_pm_set_enable_tco);
+object_property_add_bool(obj, "acpi-pci-hotplug-with-bridge-support",
+ ich9_pm_get_acpi_pci_hotplug,
+ ich9_pm_set_acpi_pci_hotplug);
 }
 
 void ich9_pm_device_pre_plug_cb(HotplugHandler *hotplug_dev, DeviceState *dev,
@@ -407,6 +459,11 @@ void ich9_pm_device_pre_plug_cb(HotplugHandler 
*hotplug_dev, DeviceState *dev,
 

[RFC PATCH v3 6/7] hw/acpi/ich9: Set ACPI PCI hot-plug as default

[Julia Suvorova]

Signed-off-by: Julia Suvorova 
---
 hw/acpi/ich9.c | 2 +-
 hw/i386/pc.c   | 1 +
 2 files changed, 2 insertions(+), 1 deletion(-)

diff --git a/hw/acpi/ich9.c b/hw/acpi/ich9.c
index 987f23e388..c67c20de4e 100644
--- a/hw/acpi/ich9.c
+++ b/hw/acpi/ich9.c
@@ -425,7 +425,7 @@ void ich9_pm_add_properties(Object *obj, ICH9LPCPMRegs *pm)
 pm->disable_s3 = 0;
 pm->disable_s4 = 0;
 pm->s4_val = 2;
-pm->use_acpi_hotplug_bridge = false;
+pm->use_acpi_hotplug_bridge = true;
 
 object_property_add_uint32_ptr(obj, ACPI_PM_PROP_PM_IO_BASE,
&pm->pm_io_base, OBJ_PROP_FLAG_READ);
diff --git a/hw/i386/pc.c b/hw/i386/pc.c
index b55369357e..5de4475570 100644
--- a/hw/i386/pc.c
+++ b/hw/i386/pc.c
@@ -101,6 +101,7 @@ GlobalProperty pc_compat_5_1[] = {};
 const size_t pc_compat_5_1_len = G_N_ELEMENTS(pc_compat_5_1);
 
 GlobalProperty pc_compat_5_0[] = {
+{ "ICH9-LPC", "acpi-pci-hotplug-with-bridge-support", "off" },
 };
 const size_t pc_compat_5_0_len = G_N_ELEMENTS(pc_compat_5_0);
 
-- 
2.25.4

[RFC PATCH v3 3/7] hw/pci/pcie: Do not initialize slot capability if acpihp is used

[Julia Suvorova]

Instead of changing the hot-plug type in _OSC register, do not
initialize the slot capability or set the 'Slot Implemented' flag.
This way guest will choose ACPI hot-plug if it is preferred and leave
the option to use SHPC with pcie-pci-bridge.

Signed-off-by: Julia Suvorova 
---
 hw/i386/acpi-build.h |  2 ++
 hw/i386/acpi-build.c |  2 +-
 hw/pci/pcie.c| 16 
 3 files changed, 19 insertions(+), 1 deletion(-)

diff --git a/hw/i386/acpi-build.h b/hw/i386/acpi-build.h
index 487ec7710f..4c5bfb3d0b 100644
--- a/hw/i386/acpi-build.h
+++ b/hw/i386/acpi-build.h
@@ -11,4 +11,6 @@ extern const struct AcpiGenericAddress x86_nvdimm_acpi_dsmio;
 
 void acpi_setup(void);
 
+Object *object_resolve_type_unambiguous(const char *typename);
+
 #endif
diff --git a/hw/i386/acpi-build.c b/hw/i386/acpi-build.c
index cf503b16af..b7811a8912 100644
--- a/hw/i386/acpi-build.c
+++ b/hw/i386/acpi-build.c
@@ -174,7 +174,7 @@ static void init_common_fadt_data(MachineState *ms, Object 
*o,
 *data = fadt;
 }
 
-static Object *object_resolve_type_unambiguous(const char *typename)
+Object *object_resolve_type_unambiguous(const char *typename)
 {
 bool ambig;
 Object *o = object_resolve_path_type("", typename, &ambig);
diff --git a/hw/pci/pcie.c b/hw/pci/pcie.c
index 5b48bae0f6..c1a082e8b9 100644
--- a/hw/pci/pcie.c
+++ b/hw/pci/pcie.c
@@ -27,6 +27,8 @@
 #include "hw/pci/pci_bus.h"
 #include "hw/pci/pcie_regs.h"
 #include "hw/pci/pcie_port.h"
+#include "hw/i386/ich9.h"
+#include "hw/i386/acpi-build.h"
 #include "qemu/range.h"
 
 //#define DEBUG_PCIE
@@ -515,12 +517,26 @@ void pcie_cap_slot_unplug_request_cb(HotplugHandler 
*hotplug_dev,
 pcie_cap_slot_push_attention_button(hotplug_pdev);
 }
 
+static bool acpi_pcihp_enabled(void)
+{
+Object *lpc = object_resolve_type_unambiguous(TYPE_ICH9_LPC_DEVICE);
+
+return lpc &&
+   object_property_get_bool(lpc, 
"acpi-pci-hotplug-with-bridge-support",
+NULL);
+
+}
+
 /* pci express slot for pci express root/downstream port
PCI express capability slot registers */
 void pcie_cap_slot_init(PCIDevice *dev, PCIESlot *s)
 {
 uint32_t pos = dev->exp.exp_cap;
 
+if (acpi_pcihp_enabled()) {
+return;
+}
+
 pci_word_test_and_set_mask(dev->config + pos + PCI_EXP_FLAGS,
PCI_EXP_FLAGS_SLOT);
 
-- 
2.25.4

[RFC PATCH v3 7/7] bios-tables-test: Update golden binaries

[Julia Suvorova]

Add ACPI hot-plug registers to DSDT Q35 tables.
Changes in the tables:

+Scope (_SB.PCI0)
+{
+OperationRegion (PCST, SystemIO, 0x0CC4, 0x08)
+Field (PCST, DWordAcc, NoLock, WriteAsZeros)
+{
+PCIU,   32,
+PCID,   32
+}
+
+OperationRegion (SEJ, SystemIO, 0x0CCC, 0x04)
+Field (SEJ, DWordAcc, NoLock, WriteAsZeros)
+{
+B0EJ,   32
+}
+
+OperationRegion (BNMR, SystemIO, 0x0CD4, 0x04)
+Field (BNMR, DWordAcc, NoLock, WriteAsZeros)
+{
+BNUM,   32
+}
+
+Mutex (BLCK, 0x00)
+Method (PCEJ, 2, NotSerialized)
+{
+Acquire (BLCK, 0x)
+BNUM = Arg0
+B0EJ = (One << Arg1)
+Release (BLCK)
+Return (Zero)
+}
+}
+
...

 Scope (_GPE)
 {
 Name (_HID, "ACPI0006" /* GPE Block Device */)  // _HID: Hardware ID
+Method (_E01, 0, NotSerialized)  // _Exx: Edge-Triggered GPE, 
xx=0x00-0xFF
+{
+Acquire (\_SB.PCI0.BLCK, 0x)
+\_SB.PCI0.PCNT ()
+Release (\_SB.PCI0.BLCK)
+}
 }
...

+
+Device (PHPR)
+{
+Name (_HID, "PNP0A06" /* Generic Container Device */)  // _HID: 
Hardware ID
+Name (_UID, "PCI Hotplug resources")  // _UID: Unique ID
+Name (_STA, 0x0B)  // _STA: Status
+Name (_CRS, ResourceTemplate ()  // _CRS: Current Resource Settings
+{
+IO (Decode16,
+0x0CC4, // Range Minimum
+0x0CC4, // Range Maximum
+0x01,   // Alignment
+0x14,   // Length
+)
+})
+}
 }

And if there is a port in configuration:

 Device (S10)
 {
 Name (_ADR, 0x0002)  // _ADR: Address
+Name (BSEL, Zero)
+Device (S00)
+{
+Name (_SUN, Zero)  // _SUN: Slot User Number
+Name (_ADR, Zero)  // _ADR: Address
+Method (_EJ0, 1, NotSerialized)  // _EJx: Eject Device, 
x=0-9
+{
+PCEJ (BSEL, _SUN)
+}
+}
+
...

+
+Method (DVNT, 2, NotSerialized)
+{
+If ((Arg0 & One))
+{
+Notify (S00, Arg1)
+}
+
+If ((Arg0 & 0x02))
+{
+Notify (S08, Arg1)
+}
+
...

Signed-off-by: Julia Suvorova 
---
 tests/qtest/bios-tables-test-allowed-diff.h |  10 --
 tests/data/acpi/q35/DSDT| Bin 7678 -> 7950 bytes
 tests/data/acpi/q35/DSDT.acpihmat   | Bin 9002 -> 9274 bytes
 tests/data/acpi/q35/DSDT.bridge | Bin 7695 -> 9865 bytes
 tests/data/acpi/q35/DSDT.cphp   | Bin 8141 -> 8413 bytes
 tests/data/acpi/q35/DSDT.dimmpxm| Bin 9331 -> 9603 bytes
 tests/data/acpi/q35/DSDT.ipmibt | Bin 7753 -> 8025 bytes
 tests/data/acpi/q35/DSDT.memhp  | Bin 9037 -> 9309 bytes
 tests/data/acpi/q35/DSDT.mmio64 | Bin 8808 -> 9080 bytes
 tests/data/acpi/q35/DSDT.numamem| Bin 7684 -> 7956 bytes
 tests/data/acpi/q35/DSDT.tis| Bin 8283 -> 8555 bytes
 11 files changed, 10 deletions(-)

diff --git a/tests/qtest/bios-tables-test-allowed-diff.h 
b/tests/qtest/bios-tables-test-allowed-diff.h
index 84f56b14db..dfb8523c8b 100644
--- a/tests/qtest/bios-tables-test-allowed-diff.h
+++ b/tests/qtest/bios-tables-test-allowed-diff.h
@@ -1,11 +1 @@
 /* List of comma-separated changed AML files to ignore */
-"tests/data/acpi/q35/DSDT",
-"tests/data/acpi/q35/DSDT.tis",
-"tests/data/acpi/q35/DSDT.bridge",
-"tests/data/acpi/q35/DSDT.mmio64",
-"tests/data/acpi/q35/DSDT.ipmibt",
-"tests/data/acpi/q35/DSDT.cphp",
-"tests/data/acpi/q35/DSDT.memhp",
-"tests/data/acpi/q35/DSDT.acpihmat",
-"tests/data/acpi/q35/DSDT.numamem",
-"tests/data/acpi/q35/DSDT.dimmpxm",
diff --git a/tests/data/acpi/q35/DSDT b/tests/data/acpi/q35/DSDT
index 
bba8884073a27427b88ac0d733c9c87330a59366..56e5b111f3239ea0af2cfb6dea962e3cd837da80
 100644
GIT binary patch
delta 329
zcmexo-Dk(;66_MfC(ppZ*twDGAXB}72ZvsKuv2`1v!_9HLx6K|2qX6q9xjgPMgb7V
z87LmA03=)#q8ox;z2X_U&+u@uL^pDSIL=N6u3kV1CqLgHM(!&R2@uEG$uHDbA)3+2
z$Jv`fL^Z(K)r%=w8N~blzaRr7Sy0KC$>3zb>FO1&4iaCo`4m&6WRO2gynBEvN4$rp
z3$LSdfTw|hff<8{WxT6_Aw#rsj6O5Wtq`-21OlA>LZa1?1VAbTd_^}~$?!9JMK^h|
z1b74lK}-(t3ovj58q5(N3bY64I|YyYl7gJlbcLeS;{4L0R

delta 57
zcmeCP`)AGN66_N4PnLm!am_}qgG`%4m?I>`MdIB9Tsh)BJY9GlodY}#3=GT|1RMo7
N|C8ZooE#~)6#(|i5Rd=>

diff --git a/tests/data/acpi/q35/DSDT.acpihmat 
b/tests/data/acpi/q35/DSDT.acpihmat
index 
9cac92418b5fcc2767dc74603d599642b59623fe..aff5e7d14fdb5b1a332dcc1866d33bff5247

Re: [PATCH v8 4/7] scripts: add block-coroutine-wrapper.py

[Vladimir Sementsov-Ogievskiy]

24.09.2020 03:18, Eric Blake wrote:

On 9/15/20 11:44 AM, Vladimir Sementsov-Ogievskiy wrote:

We have a very frequent pattern of creating coroutine from function
with several arguments:




+++ b/scripts/block-coroutine-wrapper.py
@@ -0,0 +1,187 @@
+#!/usr/bin/env python3
+"""Generate coroutine wrappers for block subsystem.


Looking at the generated file after patch 5 is applied,...



+
+def gen_header():
+    copyright = re.sub('^.*Copyright', 'Copyright', __doc__, flags=re.DOTALL)
+    copyright = re.sub('^(?=.)', ' * ', copyright.strip(), flags=re.MULTILINE)
+    copyright = re.sub('^$', ' *', copyright, flags=re.MULTILINE)
+    return f"""\


This generated comment...



+
+
+def gen_wrappers_file(input_code: str) -> str:
+    res = gen_header()


...is getting inserted into the generated file...


+    for func in func_decl_iter(input_code):
+    res += '\n\n\n'
+    res += gen_wrapper(func)
+
+    return prettify(res)  # prettify to wrap long lines
+
+
+if __name__ == '__main__':
+    if len(sys.argv) < 3:
+    exit(f'Usage: {sys.argv[0]} OUT_FILE.c IN_FILE.[ch]...')
+
+    with open(sys.argv[1], 'w') as f_out:
+    for fname in sys.argv[2:]:
+    with open(fname) as f_in:
+    f_out.write(gen_wrappers_file(f_in.read()))


multiple times.  You'll want to hoist the call to gen_header outside the loop 
over fname in sys.argv[2:].



Right, thanks for fixing. I missed it when rebasing on meson system (and move 
to calling gen_wrappers_file() several times). Hmm, gen_wrappers_file() is now 
a bit misleading name, it would better be just gen_wrappers()

--
Best regards,
Vladimir

Re: [PATCH v8 4/7] scripts: add block-coroutine-wrapper.py

[Vladimir Sementsov-Ogievskiy]

24.09.2020 04:20, Eric Blake wrote:

On 9/23/20 7:00 PM, Eric Blake wrote:



Tested-by: Eric Blake 

There's enough grammar fixes, and the fact that John is working on python 
cleanups, to make me wonder if we need a v9, or if I should just stage it where 
it is with any other cleanups as followups.  But I'm liking the reduced 
maintenance burden once it is in, and don't want to drag it out to the point 
that it needs more rebasing as other things land first.



Here's what I've squashed in and temporarily pushed to my tree if you want to 
double-check my rebase work:
https://repo.or.cz/qemu/ericb.git/shortlog/refs/heads/master

diff --git a/docs/devel/block-coroutine-wrapper.rst 
b/docs/devel/block-coroutine-wrapper.rst
index f7050bbc8fa6..d09fff2cc539 100644
--- a/docs/devel/block-coroutine-wrapper.rst
+++ b/docs/devel/block-coroutine-wrapper.rst
@@ -2,43 +2,43 @@
  block-coroutine-wrapper
  ===

-A lot of functions in QEMJ block layer (see ``block/*``) can by called
-only in coroutine context. Such functions are normally marked by
+A lot of functions in QEMU block layer (see ``block/*``) can only be
+called in coroutine context. Such functions are normally marked by the
  coroutine_fn specifier. Still, sometimes we need to call them from
-non-coroutine context, for this we need to start a coroutine, run the
+non-coroutine context; for this we need to start a coroutine, run the
  needed function from it and wait for coroutine finish in
  BDRV_POLL_WHILE() loop. To run a coroutine we need a function with one
-void* argument. So for each coroutine_fn function, which needs
+void* argument. So for each coroutine_fn function which needs a
  non-coroutine interface, we should define a structure to pack the
  parameters, define a separate function to unpack the parameters and
  call the original function and finally define a new interface function
  with same list of arguments as original one, which will pack the
  parameters into a struct, create a coroutine, run it and wait in
-BDRV_POLL_WHILE() loop. It's boring to create such wrappers by hand, so
-we have a script to generate them.
+BDRV_POLL_WHILE() loop. It's boring to create such wrappers by hand,
+so we have a script to generate them.

  Usage
  =

-Assume we have defined ``coroutine_fn`` function
+Assume we have defined the ``coroutine_fn`` function
  ``bdrv_co_foo()`` and need a non-coroutine interface for it,
  called ``bdrv_foo()``. In this case the script can help. To
  trigger the generation:

-1. You need ``bdrv_foo`` declaration somewhere (for example in
-   ``block/coroutines.h`` with ``generated_co_wrapper`` mark,
+1. You need ``bdrv_foo`` declaration somewhere (for example, in
+   ``block/coroutines.h``) with the ``generated_co_wrapper`` mark,
     like this:

  .. code-block:: c

-    int generated_co_wrapper bdrv_foor();
+    int generated_co_wrapper bdrv_foo();

  2. You need to feed this declaration to block-coroutine-wrapper script.
-   For this, add .h (or .c) file with the declaration to
+   For this, add the .h (or .c) file with the declaration to the
     ``input: files(...)`` list of ``block_gen_c`` target declaration in
     ``block/meson.build``

-You are done. On build, coroutine wrappers will be generated in
+You are done. During the build, coroutine wrappers will be generated in
  ``/block/block-gen.c``.

  Links
diff --git a/docs/devel/index.rst b/docs/devel/index.rst
index 04773ce076b3..cb0abe1e6988 100644
--- a/docs/devel/index.rst
+++ b/docs/devel/index.rst
@@ -31,3 +31,4 @@ Contents:
     reset
     s390-dasd-ipl
     clocks
+   block-coroutine-wrapper
diff --git a/scripts/block-coroutine-wrapper.py 
b/scripts/block-coroutine-wrapper.py
index d859c07a5f55..8c0a08d9b020 100755
--- a/scripts/block-coroutine-wrapper.py
+++ b/scripts/block-coroutine-wrapper.py
@@ -2,7 +2,7 @@
  """Generate coroutine wrappers for block subsystem.

  The program parses one or several concatenated c files from stdin,
-searches for functions with 'generated_co_wrapper' specifier
+searches for functions with the 'generated_co_wrapper' specifier
  and generates corresponding wrappers on stdout.

  Usage: block-coroutine-wrapper.py generated-file.c FILE.[ch]...
@@ -39,7 +39,7 @@ def prettify(code: str) -> str:
  'BraceWrapping': {'AfterFunction': True},
  'BreakBeforeBraces': 'Custom',
  'SortIncludes': False,
-    'MaxEmptyLinesToKeep': 2
+    'MaxEmptyLinesToKeep': 2,
  })
  p = subprocess.run(['clang-format', f'-style={style}'], check=True,
     encoding='utf-8', input=code,
@@ -168,7 +168,7 @@ int {func.name}({ func.gen_list('{decl}') })


  def gen_wrappers_file(input_code: str) -> str:
-    res = gen_header()
+    res = ''
  for func in func_decl_iter(input_code):
  res += '\n\n\n'
  res += gen_wrapper(func)
@@ -181,6 +181,7 @@ if __name__ == '__main__':
  exit(f'Usage: {sys.argv[0]} OUT_FILE.c IN_FIL

Re: [PATCH v6 00/11] x86: fix cpu hotplug with secure boot

[Igor Mammedov]

On Wed, 23 Sep 2020 18:44:50 +0200
Laszlo Ersek  wrote:

> On 09/23/20 11:46, Igor Mammedov wrote:
> > v6:
> >   - [9/10] Add comment explaining why while_ctx2 restarts from the last 
> > processed CPU.
> >   - rebase on top of current master, due to non trivial conflict
> > caused by microvm series, which moved/renamed pc_cpu_pre_plug()  
> 
> So, I went back to my local branch where I had applied your v5, *plus*
> the comment fixup ("[PATCH v5 9/10] fixup! x68: acpi: trigger SMI before
> sending hotplug Notify event to OSPM") on top. I rebased that branch to
> its *same* base commit, only squashing the comment fixup into patch#9.
> 
> Then I applied your v6 series on top of current master, using a
> different (new) local branch.
> 
> Then I ran git-range-diff on these two local branches.
> 
> In patches 6, 7, 8, and 9, you've picked up my feedback tags from the v5
> review session; that's good, there was nothing else to do.
> 
> There is a trivial difference in patch 2 -- trivial to review, that is;
> I'm not saying that it's so trivial that git-rebase should have coped
> with it automatically on your end. Here's the git-range-diff output:
> 
> >  2:  e606a75432a8 !  2:  94702d2e3125 x86: cpuhp: prevent guest crash on 
> > CPU hotplug when broadcast SMI is in use
> > @@ -12,7 +12,7 @@
> >  Signed-off-by: Igor Mammedov 
> >  Reviewed-by: Laszlo Ersek 
> >  Tested-by: Laszlo Ersek 
> > -Message-Id: <20200907112348.530921-3-imamm...@redhat.com>
> > +Message-Id: <20200923094650.1301166-3-imamm...@redhat.com>
> >
> >  diff --git a/hw/acpi/ich9.c b/hw/acpi/ich9.c
> >  --- a/hw/acpi/ich9.c
> > @@ -40,17 +40,17 @@
> >
> >   void ich9_pm_device_plug_cb(HotplugHandler *hotplug_dev, DeviceState 
> > *dev,
> >
> > -diff --git a/hw/i386/pc.c b/hw/i386/pc.c
> >  a/hw/i386/pc.c
> > -+++ b/hw/i386/pc.c
> > +diff --git a/hw/i386/x86.c b/hw/i386/x86.c
> > +--- a/hw/i386/x86.c
> >  b/hw/i386/x86.c
> >  @@
> >   return;
> >   }
> >
> > -+if (pcms->acpi_dev) {
> > ++if (x86ms->acpi_dev) {
> >  +Error *local_err = NULL;
> >  +
> > -+hotplug_handler_pre_plug(HOTPLUG_HANDLER(pcms->acpi_dev), dev,
> > ++hotplug_handler_pre_plug(HOTPLUG_HANDLER(x86ms->acpi_dev), 
> > dev,
> >  + &local_err);
> >  +if (local_err) {
> >  +error_propagate(errp, local_err);  
> 
> Meaning that, in v6, you had to refer to "x86ms", rather than to "pcms",
> and that the code had to be introduced in a different file / function.
> 
> The need for that originates from 0cca1a918b85 ("x86: move cpu hotplug
> from pc to x86", 2020-09-17).
I should have added this commit to change log to spare you
trouble figuring out what exactly has changed.

> 
> It looks innocent enough, but I should still retest patch#2. I'll report
> back under that patch in this series.
> 
> Thanks
> Laszlo

Re: [PATCH v3 2/3] hw/smbios: report error if table size is too large

[Laszlo Ersek]

On 09/23/20 15:38, Daniel P. Berrangé wrote:
> The SMBIOS 2.1 entry point uses a uint16 data type for reporting the
> total length of the tables. If the user passes -smbios configuration to
> QEMU that causes the table size to exceed this limit then various bad
> behaviours result, including
> 
>  - firmware hangs in an infinite loop
>  - firmware triggers a KVM crash on bad memory access
>  - firmware silently discards user's SMBIOS data replacing it with
>a generic data set.
> 
> Limiting the size to 0x in QEMU avoids triggering most of these
> problems. There is a remaining bug in SeaBIOS which tries to prepend its
> own data for table 0, and does not check whether there is sufficient
> space before attempting this.
> 
> Reviewed-by: Igor Mammedov 
> Reviewed-by: Philippe Mathieu-Daudé 
> Signed-off-by: Daniel P. Berrangé 
> ---
>  hw/smbios/smbios.c | 14 ++
>  1 file changed, 14 insertions(+)
> 
> diff --git a/hw/smbios/smbios.c b/hw/smbios/smbios.c
> index d993448087..8b30906e50 100644
> --- a/hw/smbios/smbios.c
> +++ b/hw/smbios/smbios.c
> @@ -365,6 +365,13 @@ static void smbios_register_config(void)
>  
>  opts_init(smbios_register_config);
>  
> +/*
> + * The SMBIOS 2.1 "structure table length" field in the
> + * entry point uses a 16-bit integer, so we're limited
> + * in total table size
> + */
> +#define SMBIOS_21_MAX_TABLES_LEN 0x
> +
>  static void smbios_validate_table(MachineState *ms)
>  {
>  uint32_t expect_t4_count = smbios_legacy ?
> @@ -375,6 +382,13 @@ static void smbios_validate_table(MachineState *ms)
>   expect_t4_count, smbios_type4_count);
>  exit(1);
>  }
> +
> +if (smbios_ep_type == SMBIOS_ENTRY_POINT_21 &&
> +smbios_tables_len > SMBIOS_21_MAX_TABLES_LEN) {
> +error_report("SMBIOS 2.1 table length %zu exceeds %d",
> + smbios_tables_len, SMBIOS_21_MAX_TABLES_LEN);
> +exit(1);
> +}
>  }
>  
>  
> 

Tested-by: Laszlo Ersek 

Re: [PATCH 1/3] virtio-net: Set mac address to hardware if the peer is vdpa

[Jason Wang]

On 2020/9/22 上午11:01, Cindy Lu wrote:

On Tue, Sep 22, 2020 at 9:55 AM Jason Wang  wrote:


On 2020/9/17 下午11:58, Cindy Lu wrote:

If the peer's type is vdpa,set the mac address to NIC in 
virtio_net_device_realize,
Also sometime vdpa get an all 0 macaddress from the hardware, this will cause 
the traffic down
So we add the check for this part.
if we get an 0 mac address we will use the default mac address instead

Signed-off-by: Cindy Lu 
---
   hw/net/virtio-net.c | 12 +++-
   1 file changed, 11 insertions(+), 1 deletion(-)

diff --git a/hw/net/virtio-net.c b/hw/net/virtio-net.c
index cb0d27084c..7db9da1482 100644
--- a/hw/net/virtio-net.c
+++ b/hw/net/virtio-net.c
@@ -126,6 +126,7 @@ static void virtio_net_get_config(VirtIODevice *vdev, 
uint8_t *config)
   VirtIONet *n = VIRTIO_NET(vdev);
   struct virtio_net_config netcfg;
   NetClientState *nc = qemu_get_queue(n->nic);
+static const MACAddr zero = { .a = { 0, 0, 0, 0, 0, 0 } };

   int ret = 0;
   memset(&netcfg, 0 , sizeof(struct virtio_net_config));
@@ -151,7 +152,11 @@ static void virtio_net_get_config(VirtIODevice *vdev, 
uint8_t *config)
   ret = vhost_net_get_config(get_vhost_net(nc->peer), (uint8_t 
*)&netcfg,
  n->config_size);
   if (ret != -1) {
-memcpy(config, &netcfg, n->config_size);
+if (memcmp(&netcfg.mac, &zero, sizeof(zero)) != 0) {
+memcpy(config, &netcfg, n->config_size);
+} else {
+error_report("Get an all zero mac address from hardware");


This is probably a hint that MAC is not properly provisioned.

So I guess we can leave this as is, or simply warn until the management
interface is finalized.


Hi Jason, For sure this is NIC card's problem, They cannot provide an
correct MAC address,
But if we continue use this 0 mac address will cause this traffic
down, maybe will cost a lot of effort in debugging
So I think maybe Just an warn is not enough, We can use the default
mac address  and let the traffic working



Yes, and it's done by the following code.

But the question is there's no much value for the error here consider 
you've already had a solution.


Thanks



+}
   }
   }
   }
@@ -3399,6 +3404,11 @@ static void virtio_net_device_realize(DeviceState *dev, 
Error **errp)
   nc = qemu_get_queue(n->nic);
   nc->rxfilter_notify_enabled = 1;

+   if (nc->peer && nc->peer->info->type == NET_CLIENT_DRIVER_VHOST_VDPA) {
+struct virtio_net_config netcfg = {};
+memcpy(&netcfg.mac, &n->nic_conf.macaddr, ETH_ALEN);
+virtio_net_set_config(vdev, (uint8_t *)&netcfg);


Won't this overwrite all other fields in the netcfg? I think we should
only touch mac part.

Thanks



Sure, will fix this

+}
   QTAILQ_INIT(&n->rsc_chains);
   n->qdev = dev;

Re: [PATCH v3 1/3] hw/smbios: support loading OEM strings values from a file

[Laszlo Ersek]

On 09/23/20 15:38, Daniel P. Berrangé wrote:
> Some applications want to pass quite large values for the OEM strings
> entries. Rather than having huge strings on the command line, it would
> be better to load them from a file, as supported with -fw_cfg.
> 
> This introduces the "path" parameter allowing for:
> 
>   $ echo -n "thisthing" > mydata.txt
>   $ qemu-system-x86_64 \
> -smbios type=11,value=something \
> -smbios type=11,path=mydata.txt \
> -smbios type=11,value=somemore \
> ...other args...
> 
> Now in the guest
> 
> $ dmidecode -t 11
> Getting SMBIOS data from sysfs.
> SMBIOS 2.8 present.
> 
> Handle 0x0E00, DMI type 11, 5 bytes
> OEM Strings
>   String 1: something
>   String 2: thisthing
>   String 3: somemore
> 
> Reviewed-by: Philippe Mathieu-Daudé 
> Signed-off-by: Daniel P. Berrangé 
> ---
>  hw/smbios/smbios.c | 71 +-
>  1 file changed, 58 insertions(+), 13 deletions(-)
> 
> diff --git a/hw/smbios/smbios.c b/hw/smbios/smbios.c
> index 7cc950b41c..d993448087 100644
> --- a/hw/smbios/smbios.c
> +++ b/hw/smbios/smbios.c
> @@ -110,7 +110,7 @@ static struct {
>  
>  static struct {
>  size_t nvalues;
> -const char **values;
> +char **values;
>  } type11;
>  
>  static struct {
> @@ -314,6 +314,11 @@ static const QemuOptDesc qemu_smbios_type11_opts[] = {
>  .type = QEMU_OPT_STRING,
>  .help = "OEM string data",
>  },
> +{
> +.name = "path",
> +.type = QEMU_OPT_STRING,
> +.help = "OEM string data from file",
> +},
>  };
>  
>  static const QemuOptDesc qemu_smbios_type17_opts[] = {
> @@ -641,6 +646,8 @@ static void smbios_build_type_11_table(void)
>  
>  for (i = 0; i < type11.nvalues; i++) {
>  SMBIOS_TABLE_SET_STR_LIST(11, type11.values[i]);
> +g_free(type11.values[i]);
> +type11.values[i] = NULL;
>  }
>  
>  SMBIOS_BUILD_TABLE_POST;
> @@ -940,9 +947,8 @@ static void save_opt(const char **dest, QemuOpts *opts, 
> const char *name)
>  
>  
>  struct opt_list {
> -const char *name;
>  size_t *ndest;
> -const char ***dest;
> +char ***dest;
>  };
>  
>  static int save_opt_one(void *opaque,
> @@ -951,23 +957,60 @@ static int save_opt_one(void *opaque,
>  {
>  struct opt_list *opt = opaque;
>  
> -if (!g_str_equal(name, opt->name)) {
> -return 0;
> +if (g_str_equal(name, "path")) {
> +g_autoptr(GByteArray) data = g_byte_array_new();
> +g_autofree char *buf = g_new(char, 4096);
> +ssize_t ret;
> +int fd = qemu_open(value, O_RDONLY, errp);
> +if (fd < 0) {
> +return -1;
> +}
> +
> +while (1) {
> +ret = read(fd, buf, 4096);
> +if (ret == 0) {
> +break;
> +}
> +if (ret < 0) {
> +error_setg(errp, "Unable to read from %s: %s",
> +   value, strerror(errno));
> +return -1;
> +}
> +if (memchr(buf, '\0', ret)) {
> +error_setg(errp, "NUL in OEM strings value in %s", value);
> +return -1;
> +}
> +g_byte_array_append(data, (guint8 *)buf, ret);
> +}
> +
> +close(fd);
> +
> +*opt->dest = g_renew(char *, *opt->dest, (*opt->ndest) + 1);
> +(*opt->dest)[*opt->ndest] = (char *)g_byte_array_free(data,  FALSE);
> +(*opt->ndest)++;
> +data = NULL;
> +   } else if (g_str_equal(name, "value")) {
> +*opt->dest = g_renew(char *, *opt->dest, (*opt->ndest) + 1);
> +(*opt->dest)[*opt->ndest] = g_strdup(value);
> +(*opt->ndest)++;
> +} else if (!g_str_equal(name, "type")) {
> +error_setg(errp, "Unexpected option %s", name);
> +return -1;
>  }
>  
> -*opt->dest = g_renew(const char *, *opt->dest, (*opt->ndest) + 1);
> -(*opt->dest)[*opt->ndest] = value;
> -(*opt->ndest)++;
>  return 0;
>  }
>  
> -static void save_opt_list(size_t *ndest, const char ***dest,
> -  QemuOpts *opts, const char *name)
> +static bool save_opt_list(size_t *ndest, char ***dest, QemuOpts *opts,
> +  Error **errp)
>  {
>  struct opt_list opt = {
> -name, ndest, dest,
> +ndest, dest,
>  };
> -qemu_opt_foreach(opts, save_opt_one, &opt, NULL);
> +if (!qemu_opt_foreach(opts, save_opt_one, &opt, errp)) {
> +return false;
> +}
> +return true;
>  }
>  
>  void smbios_entry_add(QemuOpts *opts, Error **errp)
> @@ -1149,7 +1192,9 @@ void smbios_entry_add(QemuOpts *opts, Error **errp)
>  if (!qemu_opts_validate(opts, qemu_smbios_type11_opts, errp)) {
>  return;
>  }
> -save_opt_list(&type11.nvalues, &type11.values, opts, "value");
> +if (!save_opt_list(&type11.nvalues, &type11.values, opts, errp)) 
> {
> +return;
> +  

Re: [PATCH v8 7/7] block/io: refactor save/load vmstate

[Vladimir Sementsov-Ogievskiy]

23.09.2020 23:10, Eric Blake wrote:

On 9/15/20 11:44 AM, Vladimir Sementsov-Ogievskiy wrote:

Like for read/write in a previous commit, drop extra indirection layer,
generate directly bdrv_readv_vmstate() and bdrv_writev_vmstate().

Signed-off-by: Vladimir Sementsov-Ogievskiy 
Reviewed-by: Eric Blake 
---
  block/coroutines.h    | 10 +++
  include/block/block.h |  6 ++--
  block/io.c    | 67 ++-
  3 files changed, 42 insertions(+), 41 deletions(-)

diff --git a/block/coroutines.h b/block/coroutines.h



  int coroutine_fn
-bdrv_co_rw_vmstate(BlockDriverState *bs, QEMUIOVector *qiov, int64_t pos,
-   bool is_read)
+bdrv_co_readv_vmstate(BlockDriverState *bs, QEMUIOVector *qiov, int64_t pos)
  {
  BlockDriver *drv = bs->drv;
  int ret = -ENOTSUP;
+    if (!drv) {
+    return -ENOMEDIUM;
+    }
+
  bdrv_inc_in_flight(bs);
-    if (!drv) {
-    ret = -ENOMEDIUM;
-    } else if (drv->bdrv_load_vmstate) {
-    if (is_read) {
-    ret = drv->bdrv_load_vmstate(bs, qiov, pos);
-    } else {
-    ret = drv->bdrv_save_vmstate(bs, qiov, pos);
-    }
+    if (drv->bdrv_load_vmstate) {
+    ret = drv->bdrv_load_vmstate(bs, qiov, pos);


This one makes sense;


  } else if (bs->file) {
-    ret = bdrv_co_rw_vmstate(bs->file->bs, qiov, pos, is_read);
+    ret = bdrv_co_readv_vmstate(bs->file->bs, qiov, pos);
  }
  bdrv_dec_in_flight(bs);
+
  return ret;
  }
-int bdrv_save_vmstate(BlockDriverState *bs, const uint8_t *buf,
-  int64_t pos, int size)
+int coroutine_fn
+bdrv_co_writev_vmstate(BlockDriverState *bs, QEMUIOVector *qiov, int64_t pos)
  {
-    QEMUIOVector qiov = QEMU_IOVEC_INIT_BUF(qiov, buf, size);
-    int ret;
+    BlockDriver *drv = bs->drv;
+    int ret = -ENOTSUP;
-    ret = bdrv_writev_vmstate(bs, &qiov, pos);
-    if (ret < 0) {
-    return ret;
+    if (!drv) {
+    return -ENOMEDIUM;
  }
-    return size;
-}
+    bdrv_inc_in_flight(bs);
-int bdrv_writev_vmstate(BlockDriverState *bs, QEMUIOVector *qiov, int64_t pos)
-{
-    return bdrv_rw_vmstate(bs, qiov, pos, false);
+    if (drv->bdrv_load_vmstate) {
+    ret = drv->bdrv_save_vmstate(bs, qiov, pos);


but this one looks awkward. It represents the pre-patch logic, but it would be 
nicer to check for bdrv_save_vmstate.  With that tweak, my R-b still stands.


Agree.



I had an interesting time applying this patch due to merge conflicts with the 
new bdrv_primary_bs() changes that landed in the meantime.



Thanks a lot!

To clarify: did you finally staged the series to send a pull request? Or Stefan 
should do it? Should I make a v9?

--
Best regards,
Vladimir

Re: [PATCH v2 00/11] microvm: add pcie support

[Michael S. Tsirkin]

On Thu, Sep 24, 2020 at 08:27:23AM +0200, Gerd Hoffmann wrote:
> v2:
>  - move aml generator to gpex and have arm virt + microvm share it.
>  - add 64bit window.
>  - add testcase.

Reviewed-by: Michael S. Tsirkin 

which tree is this for? Yours?


> Gerd Hoffmann (11):
>   move MemMapEntry
>   acpi: add acpi_dsdt_add_gpex
>   arm: use acpi_dsdt_add_gpex
>   microvm: add irq table
>   microvm: add pcie support
>   microvm/pcie: add 64bit mmio window
>   tests/acpi: allow updates for expected data files
>   tests/acpi: factor out common microvm test setup
>   tests/acpi: add microvm pcie test
>   acpi/gpex: no reason to use a method for _CRS
>   tests/acpi: update expected data files
> 
>  include/exec/hwaddr.h |   5 +
>  include/hw/arm/virt.h |   5 -
>  include/hw/i386/microvm.h |  32 ++
>  include/hw/pci-host/gpex.h|  11 ++
>  hw/arm/sbsa-ref.c |   5 -
>  hw/arm/virt-acpi-build.c  | 175 ++---
>  hw/i386/acpi-microvm.c|  12 ++
>  hw/i386/microvm.c |  91 +++
>  hw/pci-host/gpex-acpi.c   | 177 ++
>  tests/qtest/bios-tables-test.c|  27 -
>  hw/i386/Kconfig   |   1 +
>  hw/pci-host/meson.build   |   1 +
>  tests/data/acpi/microvm/DSDT.pcie | Bin 0 -> 3023 bytes
>  tests/data/acpi/virt/DSDT | Bin 5200 -> 5196 bytes
>  tests/data/acpi/virt/DSDT.memhp   | Bin 6561 -> 6557 bytes
>  tests/data/acpi/virt/DSDT.numamem | Bin 5200 -> 5196 bytes
>  16 files changed, 361 insertions(+), 181 deletions(-)
>  create mode 100644 hw/pci-host/gpex-acpi.c
>  create mode 100644 tests/data/acpi/microvm/DSDT.pcie
> 
> -- 
> 2.27.0
> 

Re: [PATCH] PoC: Rust binding for QAPI (qemu-ga only, for now)

[Markus Armbruster]

Marc-André Lureau  writes:

[...]
> What does this freedom really gives us in exchange? We don't want to commit
> to a stable API? It's not rocket science, everybody else does it with
> interface version numbers. What makes QEMU/QMP so different?

It's not rocket science, and we're so used to it that we don't even
notice anymore how awful it is.

When you compile to native code, exact interface match is required for
efficiency.

This used to be pretty much a non-issue: when you compile and link
statically, the only interface remaining at run time is system calls.

Dynamic linking threw us into DLL hell.  Yes, we figured out how to
version symbols, when to bump sonames, and how prepare for and make
binary compatible interface changes.  It's still awful.  People deploy
in containers just to get out of this awful game.  But remember: there's
a *reason*, namely efficiency.

Once you go beyond a single process, you need interprocess
communication.  We use procedure calls for intraprocess communication,
so remote procedure calls are an obvious solution for interprocess
communication.

Where many RPC systems have gone wrong, in my opinion, is bringing along
the awfulness of exact interface matches, with much less of a reason,
but even more awfulness: you now get to also wrestle with multiple
versions of servers fighting over ports and such.

Yes, containers, I know.  They help a lot with keeping such messes under
control.  But some messes are necessary, while others are not.

I respectfully disagree with the notion that "everybody else does it
with interface version numbers".  There's a ton of IPC protocols out
there that do not require exact interface matches.

[...]

Re: [PATCH 1/8] softfloat: Use mulu64 for mul64To128

[David Hildenbrand]

On 24.09.20 03:24, Richard Henderson wrote:
> Via host-utils.h, we use a host widening multiply for
> 64-bit hosts, and a common subroutine for 32-bit hosts.
> 
> Signed-off-by: Richard Henderson 
> ---
>  include/fpu/softfloat-macros.h | 24 
>  1 file changed, 4 insertions(+), 20 deletions(-)
> 
> diff --git a/include/fpu/softfloat-macros.h b/include/fpu/softfloat-macros.h
> index a35ec2893a..57845f8af0 100644
> --- a/include/fpu/softfloat-macros.h
> +++ b/include/fpu/softfloat-macros.h
> @@ -83,6 +83,7 @@ this code that are retained.
>  #define FPU_SOFTFLOAT_MACROS_H
>  
>  #include "fpu/softfloat-types.h"
> +#include "qemu/host-utils.h"
>  
>  
> /*
>  | Shifts `a' right by the number of bits given in `count'.  If any nonzero
> @@ -515,27 +516,10 @@ static inline void
>  | `z0Ptr' and `z1Ptr'.
>  
> **/
>  
> -static inline void mul64To128( uint64_t a, uint64_t b, uint64_t *z0Ptr, 
> uint64_t *z1Ptr )
> +static inline void
> +mul64To128(uint64_t a, uint64_t b, uint64_t *z0Ptr, uint64_t *z1Ptr)
>  {
> -uint32_t aHigh, aLow, bHigh, bLow;
> -uint64_t z0, zMiddleA, zMiddleB, z1;
> -
> -aLow = a;
> -aHigh = a>>32;
> -bLow = b;
> -bHigh = b>>32;
> -z1 = ( (uint64_t) aLow ) * bLow;
> -zMiddleA = ( (uint64_t) aLow ) * bHigh;
> -zMiddleB = ( (uint64_t) aHigh ) * bLow;
> -z0 = ( (uint64_t) aHigh ) * bHigh;
> -zMiddleA += zMiddleB;
> -z0 += ( ( (uint64_t) ( zMiddleA < zMiddleB ) )<<32 ) + ( zMiddleA>>32 );
> -zMiddleA <<= 32;
> -z1 += zMiddleA;
> -z0 += ( z1 < zMiddleA );
> -*z1Ptr = z1;
> -*z0Ptr = z0;
> -
> +mulu64(z1Ptr, z0Ptr, a, b);
>  }
>  
>  
> /*
> 

Reviewed-by: David Hildenbrand 

-- 
Thanks,

David / dhildenb

Re: [RFC PATCH v3 3/7] hw/pci/pcie: Do not initialize slot capability if acpihp is used

[Michael S. Tsirkin]

On Thu, Sep 24, 2020 at 09:00:09AM +0200, Julia Suvorova wrote:
> Instead of changing the hot-plug type in _OSC register, do not
> initialize the slot capability or set the 'Slot Implemented' flag.
> This way guest will choose ACPI hot-plug if it is preferred and leave
> the option to use SHPC with pcie-pci-bridge.
> 
> Signed-off-by: Julia Suvorova 
> ---
>  hw/i386/acpi-build.h |  2 ++
>  hw/i386/acpi-build.c |  2 +-
>  hw/pci/pcie.c| 16 
>  3 files changed, 19 insertions(+), 1 deletion(-)
> 
> diff --git a/hw/i386/acpi-build.h b/hw/i386/acpi-build.h
> index 487ec7710f..4c5bfb3d0b 100644
> --- a/hw/i386/acpi-build.h
> +++ b/hw/i386/acpi-build.h
> @@ -11,4 +11,6 @@ extern const struct AcpiGenericAddress 
> x86_nvdimm_acpi_dsmio;
>  
>  void acpi_setup(void);
>  
> +Object *object_resolve_type_unambiguous(const char *typename);
> +
>  #endif
> diff --git a/hw/i386/acpi-build.c b/hw/i386/acpi-build.c
> index cf503b16af..b7811a8912 100644
> --- a/hw/i386/acpi-build.c
> +++ b/hw/i386/acpi-build.c
> @@ -174,7 +174,7 @@ static void init_common_fadt_data(MachineState *ms, 
> Object *o,
>  *data = fadt;
>  }
>  
> -static Object *object_resolve_type_unambiguous(const char *typename)
> +Object *object_resolve_type_unambiguous(const char *typename)
>  {
>  bool ambig;
>  Object *o = object_resolve_path_type("", typename, &ambig);
> diff --git a/hw/pci/pcie.c b/hw/pci/pcie.c
> index 5b48bae0f6..c1a082e8b9 100644
> --- a/hw/pci/pcie.c
> +++ b/hw/pci/pcie.c
> @@ -27,6 +27,8 @@
>  #include "hw/pci/pci_bus.h"
>  #include "hw/pci/pcie_regs.h"
>  #include "hw/pci/pcie_port.h"
> +#include "hw/i386/ich9.h"
> +#include "hw/i386/acpi-build.h"
>  #include "qemu/range.h"
>  
>  //#define DEBUG_PCIE


Not really happy with pcie.c getting an i386 dependency.



> @@ -515,12 +517,26 @@ void pcie_cap_slot_unplug_request_cb(HotplugHandler 
> *hotplug_dev,
>  pcie_cap_slot_push_attention_button(hotplug_pdev);
>  }
>  
> +static bool acpi_pcihp_enabled(void)
> +{
> +Object *lpc = object_resolve_type_unambiguous(TYPE_ICH9_LPC_DEVICE);
> +
> +return lpc &&
> +   object_property_get_bool(lpc, 
> "acpi-pci-hotplug-with-bridge-support",
> +NULL);
> +
> +}
> +

Why not just check the property unconditionally?


>  /* pci express slot for pci express root/downstream port
> PCI express capability slot registers */
>  void pcie_cap_slot_init(PCIDevice *dev, PCIESlot *s)
>  {
>  uint32_t pos = dev->exp.exp_cap;
>  
> +if (acpi_pcihp_enabled()) {
> +return;
> +}
> +

I think I would rather not teach pcie about acpi. How about we
change the polarity, name the property
"pci-native-hotplug" or whatever makes sense.

>  pci_word_test_and_set_mask(dev->config + pos + PCI_EXP_FLAGS,
> PCI_EXP_FLAGS_SLOT);
>  
> -- 
> 2.25.4

[PATCH V11 1/8] linux-headers: Update MIPS KVM type defintition

[Huacai Chen]

Update MIPS KVM type defintition from Linux 5.9-rc6.

Signed-off-by: Huacai Chen 
---
 linux-headers/linux/kvm.h | 5 +++--
 1 file changed, 3 insertions(+), 2 deletions(-)

diff --git a/linux-headers/linux/kvm.h b/linux-headers/linux/kvm.h
index a28c366737..36a480fd77 100644
--- a/linux-headers/linux/kvm.h
+++ b/linux-headers/linux/kvm.h
@@ -789,9 +789,10 @@ struct kvm_ppc_resize_hpt {
 #define KVM_VM_PPC_HV 1
 #define KVM_VM_PPC_PR 2
 
-/* on MIPS, 0 forces trap & emulate, 1 forces VZ ASE */
-#define KVM_VM_MIPS_TE 0
+/* on MIPS, 0 indicates auto, 1 forces VZ ASE, 2 forces trap & emulate */
+#define KVM_VM_MIPS_AUTO   0
 #define KVM_VM_MIPS_VZ 1
+#define KVM_VM_MIPS_TE 2
 
 #define KVM_S390_SIE_PAGE_OFFSET 1
 
-- 
2.17.2

Re: [PATCH 2/8] softfloat: Use int128.h for some operations

[David Hildenbrand]

On 24.09.20 03:24, Richard Henderson wrote:
> Use our Int128, which wraps the compiler's __int128_t,
> instead of open-coding left shifts and arithmetic.
> We'd need to extend Int128 to have unsigned operations
> to replace more than these three.
> 
> Signed-off-by: Richard Henderson 
> ---
>  include/fpu/softfloat-macros.h | 39 +-
>  1 file changed, 20 insertions(+), 19 deletions(-)
> 
> diff --git a/include/fpu/softfloat-macros.h b/include/fpu/softfloat-macros.h
> index 57845f8af0..95d88d05b8 100644
> --- a/include/fpu/softfloat-macros.h
> +++ b/include/fpu/softfloat-macros.h
> @@ -84,6 +84,7 @@ this code that are retained.
>  
>  #include "fpu/softfloat-types.h"
>  #include "qemu/host-utils.h"
> +#include "qemu/int128.h"
>  
>  
> /*
>  | Shifts `a' right by the number of bits given in `count'.  If any nonzero
> @@ -352,13 +353,11 @@ static inline void shortShift128Left(uint64_t a0, 
> uint64_t a1, int count,
>  static inline void shift128Left(uint64_t a0, uint64_t a1, int count,
>  uint64_t *z0Ptr, uint64_t *z1Ptr)
>  {
> -if (count < 64) {
> -*z1Ptr = a1 << count;
> -*z0Ptr = count == 0 ? a0 : (a0 << count) | (a1 >> (-count & 63));
> -} else {
> -*z1Ptr = 0;
> -*z0Ptr = a1 << (count - 64);
> -}
> +Int128 a = int128_make128(a1, a0);
> +Int128 z = int128_lshift(a, count);
> +
> +*z0Ptr = int128_gethi(z);
> +*z1Ptr = int128_getlo(z);
>  }
>  
>  
> /*
> @@ -405,15 +404,15 @@ static inline void
>  
> **/
>  
>  static inline void
> - add128(
> - uint64_t a0, uint64_t a1, uint64_t b0, uint64_t b1, uint64_t *z0Ptr, 
> uint64_t *z1Ptr )
> +add128(uint64_t a0, uint64_t a1, uint64_t b0, uint64_t b1,
> +   uint64_t *z0Ptr, uint64_t *z1Ptr)
>  {
> -uint64_t z1;
> -
> -z1 = a1 + b1;
> -*z1Ptr = z1;
> -*z0Ptr = a0 + b0 + ( z1 < a1 );
> +Int128 a = int128_make128(a1, a0);
> +Int128 b = int128_make128(b1, b0);
> +Int128 z = int128_add(a, b);
>  
> +*z0Ptr = int128_gethi(z);
> +*z1Ptr = int128_getlo(z);
>  }
>  
>  
> /*
> @@ -463,13 +462,15 @@ static inline void
>  
> **/
>  
>  static inline void
> - sub128(
> - uint64_t a0, uint64_t a1, uint64_t b0, uint64_t b1, uint64_t *z0Ptr, 
> uint64_t *z1Ptr )
> +sub128(uint64_t a0, uint64_t a1, uint64_t b0, uint64_t b1,
> +   uint64_t *z0Ptr, uint64_t *z1Ptr)
>  {
> +Int128 a = int128_make128(a1, a0);
> +Int128 b = int128_make128(b1, b0);
> +Int128 z = int128_sub(a, b);
>  
> -*z1Ptr = a1 - b1;
> -*z0Ptr = a0 - b0 - ( a1 < b1 );
> -
> +*z0Ptr = int128_gethi(z);
> +*z1Ptr = int128_getlo(z);
>  }
>  
>  
> /*
> 

Reviewed-by: David Hildenbrand 

-- 
Thanks,

David / dhildenb

[PATCH V11 0/8] mips: Add Loongson-3 machine support

[Huacai Chen]

Loongson-3 CPU family include Loongson-3A R1/R2/R3/R4 and Loongson-3B
R1/R2. Loongson-3A R1 is the oldest and its ISA is the smallest, while
Loongson-3A R4 is the newest and its ISA is almost the superset of all
others. To reduce complexity, in QEMU we just define two CPU types:

1, "Loongson-3A1000" CPU which is corresponding to Loongson-3A R1. It is
   suitable for TCG because Loongson-3A R1 has fewest ASE.
2, "Loongson-3A4000" CPU which is corresponding to Loongson-3A R4. It is
   suitable for KVM because Loongson-3A R4 has the VZ ASE.

Loongson-3 lacks English documents. I've tried to translated them with
translate.google.com, and the machine translated documents (together
with their original Chinese versions) are available here.

Loongson-3A R1 (Loongson-3A1000)
User Manual Part 1:
http://ftp.godson.ac.cn/lemote/3A1000_p1.pdf
http://ftp.godson.ac.cn/lemote/Loongson3A1000_processor_user_manual_P1.pdf 
(Chinese Version)
User Manual Part 2:
http://ftp.godson.ac.cn/lemote/3A1000_p2.pdf
http://ftp.godson.ac.cn/lemote/Loongson3A1000_processor_user_manual_P2.pdf 
(Chinese Version)

Loongson-3A R2 (Loongson-3A2000)
User Manual Part 1:
http://ftp.godson.ac.cn/lemote/3A2000_p1.pdf
http://ftp.godson.ac.cn/lemote/Loongson3A2000_user1.pdf (Chinese Version)
User Manual Part 2:
http://ftp.godson.ac.cn/lemote/3A2000_p2.pdf
http://ftp.godson.ac.cn/lemote/Loongson3A2000_user2.pdf (Chinese Version)

Loongson-3A R3 (Loongson-3A3000)
User Manual Part 1:
http://ftp.godson.ac.cn/lemote/3A3000_p1.pdf
http://ftp.godson.ac.cn/lemote/Loongson3A3000_3B3000usermanual1.pdf (Chinese 
Version)
User Manual Part 2:
http://ftp.godson.ac.cn/lemote/3A3000_p2.pdf
http://ftp.godson.ac.cn/lemote/Loongson3A3000_3B3000usermanual2.pdf (Chinese 
Version)

Loongson-3A R4 (Loongson-3A4000)
User Manual Part 1:
http://ftp.godson.ac.cn/lemote/3A4000_p1.pdf
http://ftp.godson.ac.cn/lemote/3A4000user.pdf (Chinese Version)
User Manual Part 2:
I'm sorry that it is unavailable now.

And human-translated documents (W.I.P) are available here now:
https://github.com/loongson-community/docs/tree/master/English-translation-of-Loongson-manual

Both KVM and TCG are available now!

We now already have a full functional Linux kernel (based on Linux-5.4.x
LTS, the kvm host side and guest side have both been upstream for Linux-
5.9, but Linux-5.9 has not been released yet) here:

https://github.com/chenhuacai/linux

Of course the upstream kernel is also usable (though it is "unstable"
now):

https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git

How to use QEMU/Loongson-3?
1, Download kernel source from the above URL;
2, Build a kernel with arch/mips/configs/loongson3_{def,hpc}config;
3, Boot a Loongson-3A4000 host with this kernel (for KVM mode);
4, Build QEMU-master with this patchset;
5, modprobe kvm (only necessary for KVM mode);
6, Use QEMU with TCG:
   qemu-system-mips64el -M loongson3-virt,accel=tcg -cpu Loongson-3A1000 
-kernel  -append ...
   Use QEMU with KVM:
   qemu-system-mips64el -M loongson3-virt,accel=kvm -cpu Loongson-3A4000 
-kernel  -append ...

   The "-cpu" parameter is optional here and QEMU will use the correct type for 
TCG/KVM automatically.

V1 -> V2:
1, Add a cover letter;
2, Improve CPU definitions;
3, Remove LS7A-related things (Use GPEX instead);
4, Add a description of how to run QEMU/Loongson-3.

V2 -> V3:
1, Fix all possible checkpatch.pl errors and warnings.

V3 -> V4:
1, Sync code with upstream;
2, Remove merged patches;
3, Fix build failure without CONFIG_KVM;
4, Add Reviewed-by: Aleksandar Markovic .

V4 -> V5:
1, Improve coding style;
2, Remove merged patches;
3, Rename machine name from "loongson3" to "loongson3-virt";
4, Rework the "loongson3-virt" machine to drop any ISA things;
5, Rework "hw/mips: Implement the kvm_type() hook in MachineClass";
6, Add Jiaxun Yang as a reviewer of Loongson-3.

V5 -> V6:
1, Fix license preamble;
2, Improve commit messages;
3, Add hw/intc/loongson_liointc.c to MAINTAINERS;
4, Fix all possible checkpatch.pl errors and warnings.

V7 and V8 have only one patch (machine definition) with some minor improvements.

V8 -> V9:
1, Update KVM type definition from kernel;
2, Fix PageMask with variable page size for TCG;
3, Add TCG support (add Loongson-EXT instructions).

V9 -> V10:
1, Split fw_cfg to a separate patch;
2, Split boot parameters definition to a local header;
3, Update MIPS machine documentation;
4, Many other improvements suggested by Philippe Mathieu-Daudé.

V10 -> V11:
1, Fix some typos;
2, Add Reviewed-by: Philippe Mathieu-Daudé .

Huacai Chen and Jiaxun Yang (8):
 linux-headers: Update MIPS KVM type defintition
 target/mips: Fix PageMask with variable page size
 target/mips: Add loongson-ext lswc2 group of instructions (Part 1)
 target/mips: Add loongson-ext lswc2 group of instructions (Part 2)
 target/mips: Add loongson-ext lsdc2 group of instructions
 hw/mips: Implement fw_cfg_arch_key_name()
 hw/mips: Add Loongson-3 machine support
 docs/system: Update MIPS machin

[PATCH V11 2/8] target/mips: Fix PageMask with variable page size

[Huacai Chen]

From: Jiaxun Yang 

Our current code assumed the target page size is always 4k
when handling PageMask and VPN2, however, variable page size
was just added to mips target and that's no longer true.

Fixes: ee3863b9d414 ("target/mips: Support variable page size")
Signed-off-by: Huacai Chen 
Signed-off-by: Jiaxun Yang 
---
 target/mips/cp0_helper.c | 36 +---
 target/mips/cpu.h|  1 +
 2 files changed, 30 insertions(+), 7 deletions(-)

diff --git a/target/mips/cp0_helper.c b/target/mips/cp0_helper.c
index de64add038..62bcb9707e 100644
--- a/target/mips/cp0_helper.c
+++ b/target/mips/cp0_helper.c
@@ -867,13 +867,35 @@ void helper_mtc0_memorymapid(CPUMIPSState *env, 
target_ulong arg1)
 
 void update_pagemask(CPUMIPSState *env, target_ulong arg1, int32_t *pagemask)
 {
-uint64_t mask = arg1 >> (TARGET_PAGE_BITS + 1);
-if (!(env->insn_flags & ISA_MIPS32R6) || (arg1 == ~0) ||
-(mask == 0x || mask == 0x0003 || mask == 0x000F ||
- mask == 0x003F || mask == 0x00FF || mask == 0x03FF ||
- mask == 0x0FFF || mask == 0x3FFF || mask == 0x)) {
-env->CP0_PageMask = arg1 & (0x1FFF & (TARGET_PAGE_MASK << 1));
+unsigned long mask;
+int maskbits;
+
+if (env->insn_flags & ISA_MIPS32R6) {
+return;
+}
+/* Don't care MASKX as we don't support 1KB page */
+mask = extract32((uint32_t)arg1, CP0PM_MASK, 16);
+maskbits = find_first_zero_bit(&mask, 32);
+
+/* Ensure no more set bit after first zero */
+if (mask >> maskbits) {
+goto invalid;
+}
+/* We don't support VTLB entry smaller than target page */
+if ((maskbits + 12) < TARGET_PAGE_BITS) {
+goto invalid;
 }
+env->CP0_PageMask = mask << CP0PM_MASK;
+
+return;
+
+invalid:
+/*
+ * When invalid, ensure the value is bigger than or equal to
+ * the minimal but smaller than or equal to the maxium.
+ */
+maskbits = MIN(16, MAX(maskbits, TARGET_PAGE_BITS - 12));
+env->CP0_PageMask = ((1 << (16 + 1)) - 1) << CP0PM_MASK;
 }
 
 void helper_mtc0_pagemask(CPUMIPSState *env, target_ulong arg1)
@@ -1104,7 +1126,7 @@ void helper_mthc0_saar(CPUMIPSState *env, target_ulong 
arg1)
 void helper_mtc0_entryhi(CPUMIPSState *env, target_ulong arg1)
 {
 target_ulong old, val, mask;
-mask = (TARGET_PAGE_MASK << 1) | env->CP0_EntryHi_ASID_mask;
+mask = ~((1 << 14) - 1) | env->CP0_EntryHi_ASID_mask;
 if (((env->CP0_Config4 >> CP0C4_IE) & 0x3) >= 2) {
 mask |= 1 << CP0EnHi_EHINV;
 }
diff --git a/target/mips/cpu.h b/target/mips/cpu.h
index 7cf7f5239f..9c8bb23807 100644
--- a/target/mips/cpu.h
+++ b/target/mips/cpu.h
@@ -618,6 +618,7 @@ struct CPUMIPSState {
  * CP0 Register 5
  */
 int32_t CP0_PageMask;
+#define CP0PM_MASK 13
 int32_t CP0_PageGrain_rw_bitmask;
 int32_t CP0_PageGrain;
 #define CP0PG_RIE 31
-- 
2.17.2

Re: [PATCH 3/8] softfloat: Tidy a * b + inf return

[David Hildenbrand]

On 24.09.20 03:24, Richard Henderson wrote:
> No reason to set values in 'a', when we already
> have float_class_inf in 'c', and can flip that sign.
> 
> Signed-off-by: Richard Henderson 
> ---
>  fpu/softfloat.c | 5 ++---
>  1 file changed, 2 insertions(+), 3 deletions(-)
> 
> diff --git a/fpu/softfloat.c b/fpu/softfloat.c
> index 67cfa0fd82..9db55d2b11 100644
> --- a/fpu/softfloat.c
> +++ b/fpu/softfloat.c
> @@ -1380,9 +1380,8 @@ static FloatParts muladd_floats(FloatParts a, 
> FloatParts b, FloatParts c,
>  s->float_exception_flags |= float_flag_invalid;
>  return parts_default_nan(s);
>  } else {
> -a.cls = float_class_inf;
> -a.sign = c.sign ^ sign_flip;
> -return a;
> +c.sign ^= sign_flip;
> +return c;
>  }
>  }
>  
> 

Reviewed-by: David Hildenbrand 

-- 
Thanks,

David / dhildenb

[PATCH V11 3/8] target/mips: Add loongson-ext lswc2 group of instructions (Part 1)

[Huacai Chen]

From: Jiaxun Yang 

LWC2 & SWC2 have been rewritten by Loongson EXT vendor ASE
as "load/store quad word" and "shifted load/store" groups of
instructions.

This patch add implementation of these instructions:
gslq: load 16 bytes to GPR
gssq: store 16 bytes from GPR
gslqc1: load 16 bytes to FPR
gssqc1: store 16 bytes from FPR

Details of Loongson-EXT is here:
https://github.com/FlyGoat/loongson-insn/blob/master/loongson-ext.md

Signed-off-by: Huacai Chen 
Signed-off-by: Jiaxun Yang 
---
 target/mips/translate.c | 87 +
 1 file changed, 87 insertions(+)

diff --git a/target/mips/translate.c b/target/mips/translate.c
index 398edf7289..cb0adde310 100644
--- a/target/mips/translate.c
+++ b/target/mips/translate.c
@@ -460,6 +460,17 @@ enum {
 R6_OPC_SCD = 0x27 | OPC_SPECIAL3,
 };
 
+/* Loongson EXT load/store quad word opcodes */
+#define MASK_LOONGSON_GSLSQ(op)   (MASK_OP_MAJOR(op) | (op & 0x8020))
+enum {
+OPC_GSLQ= 0x0020 | OPC_LWC2,
+OPC_GSLQC1  = 0x8020 | OPC_LWC2,
+OPC_GSSHFL  = OPC_LWC2,
+OPC_GSSQ= 0x0020 | OPC_SWC2,
+OPC_GSSQC1  = 0x8020 | OPC_SWC2,
+OPC_GSSHFS  = OPC_SWC2,
+};
+
 /* BSHFL opcodes */
 #define MASK_BSHFL(op)  (MASK_SPECIAL3(op) | (op & (0x1F << 6)))
 
@@ -5910,6 +5921,80 @@ no_rd:
 tcg_temp_free_i64(t1);
 }
 
+static void gen_loongson_lswc2(DisasContext *ctx, int rt,
+int rs, int rd)
+{
+TCGv t0, t1, t2;
+TCGv_i32 fp0;
+#if defined(TARGET_MIPS64)
+int lsq_rt1 = ctx->opcode & 0x1f;
+int lsq_offset = ((int)((ctx->opcode >> 6) & 0x1ff) << 23) >> 19;
+#endif
+int shf_offset = (int8_t)(ctx->opcode >> 6);
+
+t0 = tcg_temp_new();
+
+switch (MASK_LOONGSON_GSLSQ(ctx->opcode)) {
+#if defined(TARGET_MIPS64)
+case OPC_GSLQ:
+t1 = tcg_temp_new();
+gen_base_offset_addr(ctx, t0, rs, lsq_offset);
+tcg_gen_qemu_ld_tl(t1, t0, ctx->mem_idx, MO_TEQ |
+ctx->default_tcg_memop_mask);
+gen_base_offset_addr(ctx, t0, rs, lsq_offset + 8);
+tcg_gen_qemu_ld_tl(t0, t0, ctx->mem_idx, MO_TEQ |
+ctx->default_tcg_memop_mask);
+gen_store_gpr(t1, rt);
+gen_store_gpr(t0, lsq_rt1);
+tcg_temp_free(t1);
+break;
+case OPC_GSLQC1:
+check_cp1_enabled(ctx);
+t1 = tcg_temp_new();
+gen_base_offset_addr(ctx, t0, rs, lsq_offset);
+tcg_gen_qemu_ld_tl(t1, t0, ctx->mem_idx, MO_TEQ |
+ctx->default_tcg_memop_mask);
+gen_base_offset_addr(ctx, t0, rs, lsq_offset + 8);
+tcg_gen_qemu_ld_tl(t0, t0, ctx->mem_idx, MO_TEQ |
+ctx->default_tcg_memop_mask);
+gen_store_fpr64(ctx, t1, rt);
+gen_store_fpr64(ctx, t0, lsq_rt1);
+tcg_temp_free(t1);
+break;
+case OPC_GSSQ:
+t1 = tcg_temp_new();
+gen_base_offset_addr(ctx, t0, rs, lsq_offset);
+gen_load_gpr(t1, rt);
+tcg_gen_qemu_st_tl(t1, t0, ctx->mem_idx, MO_TEQ |
+ctx->default_tcg_memop_mask);
+gen_base_offset_addr(ctx, t0, rs, lsq_offset + 8);
+gen_load_gpr(t1, lsq_rt1);
+tcg_gen_qemu_st_tl(t1, t0, ctx->mem_idx, MO_TEQ |
+ctx->default_tcg_memop_mask);
+tcg_temp_free(t1);
+break;
+case OPC_GSSQC1:
+check_cp1_enabled(ctx);
+t1 = tcg_temp_new();
+gen_base_offset_addr(ctx, t0, rs, lsq_offset);
+gen_load_fpr64(ctx, t1, rt);
+tcg_gen_qemu_st_tl(t1, t0, ctx->mem_idx, MO_TEQ |
+ctx->default_tcg_memop_mask);
+gen_base_offset_addr(ctx, t0, rs, lsq_offset + 8);
+gen_load_fpr64(ctx, t1, lsq_rt1);
+tcg_gen_qemu_st_tl(t1, t0, ctx->mem_idx, MO_TEQ |
+ctx->default_tcg_memop_mask);
+tcg_temp_free(t1);
+break;
+#endif
+default:
+MIPS_INVAL("loongson_gslsq");
+generate_exception_end(ctx, EXCP_RI);
+break;
+}
+tcg_temp_free(t0);
+}
+
 /* Traps */
 static void gen_trap(DisasContext *ctx, uint32_t opc,
  int rs, int rt, int16_t imm)
@@ -30774,6 +30859,8 @@ static void decode_opc(CPUMIPSState *env, DisasContext 
*ctx)
 /* OPC_BC, OPC_BALC */
 gen_compute_compact_branch(ctx, op, 0, 0,
sextract32(ctx->opcode << 2, 0, 28));
+} else if (ctx->insn_flags & ASE_LEXT) {
+gen_loongson_lswc2(ctx, rt, rs, rd);
 } else {
 /* OPC_LWC2, OPC_SWC2 */
 /* COP2: Not implemented. */
-- 
2.17.2

[PATCH V11 6/8] hw/mips: Implement fw_cfg_arch_key_name()

[Huacai Chen]

Implement fw_cfg_arch_key_name(), which returns the name of a
mips-specific key.

Reviewed-by: Philippe Mathieu-Daudé 
Signed-off-by: Huacai Chen 
Co-developed-by: Jiaxun Yang 
---
 hw/mips/fw_cfg.c| 35 +++
 hw/mips/fw_cfg.h| 19 +++
 hw/mips/meson.build |  2 +-
 3 files changed, 55 insertions(+), 1 deletion(-)
 create mode 100644 hw/mips/fw_cfg.c
 create mode 100644 hw/mips/fw_cfg.h

diff --git a/hw/mips/fw_cfg.c b/hw/mips/fw_cfg.c
new file mode 100644
index 00..67c4a74f4b
--- /dev/null
+++ b/hw/mips/fw_cfg.c
@@ -0,0 +1,35 @@
+/*
+ * QEMU fw_cfg helpers (MIPS specific)
+ *
+ * Copyright (c) 2020 Lemote, Inc.
+ *
+ * Author:
+ *   Huacai Chen (che...@lemote.com)
+ *
+ * SPDX-License-Identifier: GPL-2.0-or-later
+ *
+ * This work is licensed under the terms of the GNU GPL, version 2 or later.
+ * See the COPYING file in the top-level directory.
+ */
+
+#include "qemu/osdep.h"
+#include "hw/mips/fw_cfg.h"
+#include "hw/nvram/fw_cfg.h"
+
+const char *fw_cfg_arch_key_name(uint16_t key)
+{
+static const struct {
+uint16_t key;
+const char *name;
+} fw_cfg_arch_wellknown_keys[] = {
+{FW_CFG_MACHINE_VERSION, "machine_version"},
+{FW_CFG_CPU_FREQ, "cpu_frequency"},
+};
+
+for (size_t i = 0; i < ARRAY_SIZE(fw_cfg_arch_wellknown_keys); i++) {
+if (fw_cfg_arch_wellknown_keys[i].key == key) {
+return fw_cfg_arch_wellknown_keys[i].name;
+}
+}
+return NULL;
+}
diff --git a/hw/mips/fw_cfg.h b/hw/mips/fw_cfg.h
new file mode 100644
index 00..e317d5b9a3
--- /dev/null
+++ b/hw/mips/fw_cfg.h
@@ -0,0 +1,19 @@
+/*
+ * QEMU fw_cfg helpers (MIPS specific)
+ *
+ * Copyright (c) 2020 Huacai Chen
+ *
+ * SPDX-License-Identifier: MIT
+ */
+
+#ifndef HW_MIPS_FW_CFG_H
+#define HW_MIPS_FW_CFG_H
+
+#include "hw/boards.h"
+#include "hw/nvram/fw_cfg.h"
+
+/* Data for BIOS to identify machine */
+#define FW_CFG_MACHINE_VERSION  (FW_CFG_ARCH_LOCAL + 0)
+#define FW_CFG_CPU_FREQ (FW_CFG_ARCH_LOCAL + 1)
+
+#endif
diff --git a/hw/mips/meson.build b/hw/mips/meson.build
index 46294b7382..c98391ce99 100644
--- a/hw/mips/meson.build
+++ b/hw/mips/meson.build
@@ -1,5 +1,5 @@
 mips_ss = ss.source_set()
-mips_ss.add(files('addr.c', 'mips_int.c'))
+mips_ss.add(files('addr.c', 'mips_int.c', 'fw_cfg.c'))
 mips_ss.add(when: 'CONFIG_FULOONG', if_true: files('fuloong2e.c'))
 mips_ss.add(when: 'CONFIG_JAZZ', if_true: files('jazz.c'))
 mips_ss.add(when: 'CONFIG_MALTA', if_true: files('gt64xxx_pci.c', 'malta.c'))
-- 
2.17.2

[PATCH V11 4/8] target/mips: Add loongson-ext lswc2 group of instructions (Part 2)

[Huacai Chen]

From: Jiaxun Yang 

LWC2 & SWC2 have been rewritten by Loongson EXT vendor ASE
as "load/store quad word" and "shifted load/store" groups of
instructions.

This patch add implementation of these instructions:
gslwlc1: similar to lwl but RT is FPR instead of GPR
gslwrc1: similar to lwr but RT is FPR instead of GPR
gsldlc1: similar to ldl but RT is FPR instead of GPR
gsldrc1: similar to ldr but RT is FPR instead of GPR
gsswlc1: similar to swl but RT is FPR instead of GPR
gsswrc1: similar to swr but RT is FPR instead of GPR
gssdlc1: similar to sdl but RT is FPR instead of GPR
gssdrc1: similar to sdr but RT is FPR instead of GPR

Details of Loongson-EXT is here:
https://github.com/FlyGoat/loongson-insn/blob/master/loongson-ext.md

Signed-off-by: Huacai Chen 
Signed-off-by: Jiaxun Yang 
---
 target/mips/translate.c | 177 
 1 file changed, 177 insertions(+)

diff --git a/target/mips/translate.c b/target/mips/translate.c
index cb0adde310..916b57f293 100644
--- a/target/mips/translate.c
+++ b/target/mips/translate.c
@@ -471,6 +471,19 @@ enum {
 OPC_GSSHFS  = OPC_SWC2,
 };
 
+/* Loongson EXT shifted load/store opcodes */
+#define MASK_LOONGSON_GSSHFLS(op) (MASK_OP_MAJOR(op) | (op & 0xc03f))
+enum {
+OPC_GSLWLC1 = 0x4 | OPC_GSSHFL,
+OPC_GSLWRC1 = 0x5 | OPC_GSSHFL,
+OPC_GSLDLC1 = 0x6 | OPC_GSSHFL,
+OPC_GSLDRC1 = 0x7 | OPC_GSSHFL,
+OPC_GSSWLC1 = 0x4 | OPC_GSSHFS,
+OPC_GSSWRC1 = 0x5 | OPC_GSSHFS,
+OPC_GSSDLC1 = 0x6 | OPC_GSSHFS,
+OPC_GSSDRC1 = 0x7 | OPC_GSSHFS,
+};
+
 /* BSHFL opcodes */
 #define MASK_BSHFL(op)  (MASK_SPECIAL3(op) | (op & (0x1F << 6)))
 
@@ -5987,6 +6000,170 @@ static void gen_loongson_lswc2(DisasContext *ctx, int 
rt,
 tcg_temp_free(t1);
 break;
 #endif
+case OPC_GSSHFL:
+switch (MASK_LOONGSON_GSSHFLS(ctx->opcode)) {
+case OPC_GSLWLC1:
+check_cp1_enabled(ctx);
+gen_base_offset_addr(ctx, t0, rs, shf_offset);
+t1 = tcg_temp_new();
+tcg_gen_qemu_ld_tl(t1, t0, ctx->mem_idx, MO_UB);
+tcg_gen_andi_tl(t1, t0, 3);
+#ifndef TARGET_WORDS_BIGENDIAN
+tcg_gen_xori_tl(t1, t1, 3);
+#endif
+tcg_gen_shli_tl(t1, t1, 3);
+tcg_gen_andi_tl(t0, t0, ~3);
+tcg_gen_qemu_ld_tl(t0, t0, ctx->mem_idx, MO_TEUL);
+tcg_gen_shl_tl(t0, t0, t1);
+t2 = tcg_const_tl(-1);
+tcg_gen_shl_tl(t2, t2, t1);
+fp0 = tcg_temp_new_i32();
+gen_load_fpr32(ctx, fp0, rt);
+tcg_gen_ext_i32_tl(t1, fp0);
+tcg_gen_andc_tl(t1, t1, t2);
+tcg_temp_free(t2);
+tcg_gen_or_tl(t0, t0, t1);
+tcg_temp_free(t1);
+#if defined(TARGET_MIPS64)
+tcg_gen_extrl_i64_i32(fp0, t0);
+#else
+tcg_gen_ext32s_tl(fp0, t0);
+#endif
+gen_store_fpr32(ctx, fp0, rt);
+tcg_temp_free_i32(fp0);
+break;
+case OPC_GSLWRC1:
+check_cp1_enabled(ctx);
+gen_base_offset_addr(ctx, t0, rs, shf_offset);
+t1 = tcg_temp_new();
+tcg_gen_qemu_ld_tl(t1, t0, ctx->mem_idx, MO_UB);
+tcg_gen_andi_tl(t1, t0, 3);
+#ifdef TARGET_WORDS_BIGENDIAN
+tcg_gen_xori_tl(t1, t1, 3);
+#endif
+tcg_gen_shli_tl(t1, t1, 3);
+tcg_gen_andi_tl(t0, t0, ~3);
+tcg_gen_qemu_ld_tl(t0, t0, ctx->mem_idx, MO_TEUL);
+tcg_gen_shr_tl(t0, t0, t1);
+tcg_gen_xori_tl(t1, t1, 31);
+t2 = tcg_const_tl(0xfffeull);
+tcg_gen_shl_tl(t2, t2, t1);
+fp0 = tcg_temp_new_i32();
+gen_load_fpr32(ctx, fp0, rt);
+tcg_gen_ext_i32_tl(t1, fp0);
+tcg_gen_and_tl(t1, t1, t2);
+tcg_temp_free(t2);
+tcg_gen_or_tl(t0, t0, t1);
+tcg_temp_free(t1);
+#if defined(TARGET_MIPS64)
+tcg_gen_extrl_i64_i32(fp0, t0);
+#else
+tcg_gen_ext32s_tl(fp0, t0);
+#endif
+gen_store_fpr32(ctx, fp0, rt);
+tcg_temp_free_i32(fp0);
+break;
+#if defined(TARGET_MIPS64)
+case OPC_GSLDLC1:
+check_cp1_enabled(ctx);
+gen_base_offset_addr(ctx, t0, rs, shf_offset);
+t1 = tcg_temp_new();
+tcg_gen_qemu_ld_tl(t1, t0, ctx->mem_idx, MO_UB);
+tcg_gen_andi_tl(t1, t0, 7);
+#ifndef TARGET_WORDS_BIGENDIAN
+tcg_gen_xori_tl(t1, t1, 7);
+#endif
+tcg_gen_shli_tl(t1, t1, 3);
+tcg_gen_andi_tl(t0, t0, ~7);
+tcg_gen_qemu_ld_tl(t0, t0, ctx->mem_idx, MO_TEQ);
+tcg_gen_shl_tl(t0, t0, t1);
+t2 = tcg_const_tl(-1);
+tcg_gen_shl_tl(t2, t2, t1);
+gen_load_fpr64(ctx, t1, rt);
+tcg_gen_andc_tl(t1, t1, t2);
+tcg_temp_free(t2);
+tcg_gen_or_tl(t0, t0, t1);
+tcg_temp_free(t1);
+

[PATCH V11 5/8] target/mips: Add loongson-ext lsdc2 group of instructions

[Huacai Chen]

From: Jiaxun Yang 

LDC2/SDC2 opcodes have been rewritten as "load & store with offset"
group of instructions by loongson-ext ASE.

This patch add implementation of these instructions:
gslbx: load 1 bytes to GPR
gslhx: load 2 bytes to GPR
gslwx: load 4 bytes to GPR
gsldx: load 8 bytes to GPR
gslwxc1: load 4 bytes to FPR
gsldxc1: load 8 bytes to FPR
gssbx: store 1 bytes from GPR
gsshx: store 2 bytes from GPR
gsswx: store 4 bytes from GPR
gssdx: store 8 bytes from GPR
gsswxc1: store 4 bytes from FPR
gssdxc1: store 8 bytes from FPR

Details of Loongson-EXT is here:
https://github.com/FlyGoat/loongson-insn/blob/master/loongson-ext.md

Signed-off-by: Huacai Chen 
Signed-off-by: Jiaxun Yang 
---
 target/mips/translate.c | 179 
 1 file changed, 179 insertions(+)

diff --git a/target/mips/translate.c b/target/mips/translate.c
index 916b57f293..4d42cfceaf 100644
--- a/target/mips/translate.c
+++ b/target/mips/translate.c
@@ -484,6 +484,24 @@ enum {
 OPC_GSSDRC1 = 0x7 | OPC_GSSHFS,
 };
 
+/* Loongson EXT LDC2/SDC2 opcodes */
+#define MASK_LOONGSON_LSDC2(op)   (MASK_OP_MAJOR(op) | (op & 0x7))
+
+enum {
+OPC_GSLBX  = 0x0 | OPC_LDC2,
+OPC_GSLHX  = 0x1 | OPC_LDC2,
+OPC_GSLWX  = 0x2 | OPC_LDC2,
+OPC_GSLDX  = 0x3 | OPC_LDC2,
+OPC_GSLWXC1= 0x6 | OPC_LDC2,
+OPC_GSLDXC1= 0x7 | OPC_LDC2,
+OPC_GSSBX  = 0x0 | OPC_SDC2,
+OPC_GSSHX  = 0x1 | OPC_SDC2,
+OPC_GSSWX  = 0x2 | OPC_SDC2,
+OPC_GSSDX  = 0x3 | OPC_SDC2,
+OPC_GSSWXC1= 0x6 | OPC_SDC2,
+OPC_GSSDXC1= 0x7 | OPC_SDC2,
+};
+
 /* BSHFL opcodes */
 #define MASK_BSHFL(op)  (MASK_SPECIAL3(op) | (op & (0x1F << 6)))
 
@@ -6172,6 +6190,165 @@ static void gen_loongson_lswc2(DisasContext *ctx, int 
rt,
 tcg_temp_free(t0);
 }
 
+/* Loongson EXT LDC2/SDC2 */
+static void gen_loongson_lsdc2(DisasContext *ctx, int rt,
+int rs, int rd)
+{
+int offset = (int8_t)(ctx->opcode >> 3);
+uint32_t opc = MASK_LOONGSON_LSDC2(ctx->opcode);
+TCGv t0, t1;
+TCGv_i32 fp0;
+
+/* Pre-conditions */
+switch (opc) {
+case OPC_GSLBX:
+case OPC_GSLHX:
+case OPC_GSLWX:
+case OPC_GSLDX:
+/* prefetch, implement as NOP */
+if (rt == 0) {
+return;
+}
+break;
+case OPC_GSSBX:
+case OPC_GSSHX:
+case OPC_GSSWX:
+case OPC_GSSDX:
+break;
+case OPC_GSLWXC1:
+#if defined(TARGET_MIPS64)
+case OPC_GSLDXC1:
+#endif
+check_cp1_enabled(ctx);
+/* prefetch, implement as NOP */
+if (rt == 0) {
+return;
+}
+break;
+case OPC_GSSWXC1:
+#if defined(TARGET_MIPS64)
+case OPC_GSSDXC1:
+#endif
+check_cp1_enabled(ctx);
+break;
+default:
+MIPS_INVAL("loongson_lsdc2");
+generate_exception_end(ctx, EXCP_RI);
+return;
+break;
+}
+
+t0 = tcg_temp_new();
+
+gen_base_offset_addr(ctx, t0, rs, offset);
+gen_op_addr_add(ctx, t0, cpu_gpr[rd], t0);
+
+switch (opc) {
+case OPC_GSLBX:
+tcg_gen_qemu_ld_tl(t0, t0, ctx->mem_idx, MO_SB);
+gen_store_gpr(t0, rt);
+break;
+case OPC_GSLHX:
+tcg_gen_qemu_ld_tl(t0, t0, ctx->mem_idx, MO_TESW |
+ctx->default_tcg_memop_mask);
+gen_store_gpr(t0, rt);
+break;
+case OPC_GSLWX:
+gen_base_offset_addr(ctx, t0, rs, offset);
+if (rd) {
+gen_op_addr_add(ctx, t0, cpu_gpr[rd], t0);
+}
+tcg_gen_qemu_ld_tl(t0, t0, ctx->mem_idx, MO_TESL |
+ctx->default_tcg_memop_mask);
+gen_store_gpr(t0, rt);
+break;
+#if defined(TARGET_MIPS64)
+case OPC_GSLDX:
+gen_base_offset_addr(ctx, t0, rs, offset);
+if (rd) {
+gen_op_addr_add(ctx, t0, cpu_gpr[rd], t0);
+}
+tcg_gen_qemu_ld_tl(t0, t0, ctx->mem_idx, MO_TEQ |
+ctx->default_tcg_memop_mask);
+gen_store_gpr(t0, rt);
+break;
+#endif
+case OPC_GSLWXC1:
+check_cp1_enabled(ctx);
+gen_base_offset_addr(ctx, t0, rs, offset);
+if (rd) {
+gen_op_addr_add(ctx, t0, cpu_gpr[rd], t0);
+}
+fp0 = tcg_temp_new_i32();
+tcg_gen_qemu_ld_i32(fp0, t0, ctx->mem_idx, MO_TESL |
+ctx->default_tcg_memop_mask);
+gen_store_fpr32(ctx, fp0, rt);
+tcg_temp_free_i32(fp0);
+break;
+#if defined(TARGET_MIPS64)
+case OPC_GSLDXC1:
+check_cp1_enabled(ctx);
+gen_base_offset_addr(ctx, t0, rs, offset);
+if (rd) {
+gen_op_addr_add(ctx, t0, cpu_gpr[rd], t0);
+}
+tcg_gen_qemu_ld_tl(t0, t0, ctx->mem_idx, MO_TEQ |
+ctx->default_tcg_memop_mask);
+gen_store_fpr64(ctx, t0, rt);
+break;
+#endif
+case OPC_GSSBX:
+t1 = tcg_temp

Re: [RFC PATCH v3 4/7] hw/acpi/ich9: Enable ACPI PCI hot-plug

[Michael S. Tsirkin]

On Thu, Sep 24, 2020 at 09:00:10AM +0200, Julia Suvorova wrote:
> Add acpi_pcihp to ich9_pm as part of
> 'acpi-pci-hotplug-with-bridge-support' option. Set default to false.
> 
> Signed-off-by: Julia Suvorova 
> ---
>  hw/i386/acpi-build.h   |  1 +
>  include/hw/acpi/ich9.h |  3 ++
>  hw/acpi/ich9.c | 67 ++
>  hw/acpi/pcihp.c|  5 +++-
>  hw/i386/acpi-build.c   |  2 +-
>  5 files changed, 76 insertions(+), 2 deletions(-)
> 
> diff --git a/hw/i386/acpi-build.h b/hw/i386/acpi-build.h
> index 4c5bfb3d0b..39f143830a 100644
> --- a/hw/i386/acpi-build.h
> +++ b/hw/i386/acpi-build.h
> @@ -10,6 +10,7 @@ extern const struct AcpiGenericAddress 
> x86_nvdimm_acpi_dsmio;
>  #define ACPI_PCIHP_BNMR_BASE 0x10
>  
>  void acpi_setup(void);
> +Object *acpi_get_i386_pci_host(void);
>  
>  Object *object_resolve_type_unambiguous(const char *typename);
>  
> diff --git a/include/hw/acpi/ich9.h b/include/hw/acpi/ich9.h
> index 4d19571ed7..833e62fefe 100644
> --- a/include/hw/acpi/ich9.h
> +++ b/include/hw/acpi/ich9.h
> @@ -24,6 +24,7 @@
>  #include "hw/acpi/acpi.h"
>  #include "hw/acpi/cpu_hotplug.h"
>  #include "hw/acpi/cpu.h"
> +#include "hw/acpi/pcihp.h"
>  #include "hw/acpi/memory_hotplug.h"
>  #include "hw/acpi/acpi_dev_interface.h"
>  #include "hw/acpi/tco.h"
> @@ -55,6 +56,8 @@ typedef struct ICH9LPCPMRegs {
>  AcpiCpuHotplug gpe_cpu;
>  CPUHotplugState cpuhp_state;
>  
> +bool use_acpi_hotplug_bridge;
> +AcpiPciHpState acpi_pci_hotplug;
>  MemHotplugState acpi_memory_hotplug;
>  
>  uint8_t disable_s3;
> diff --git a/hw/acpi/ich9.c b/hw/acpi/ich9.c
> index 6a19070cec..987f23e388 100644
> --- a/hw/acpi/ich9.c
> +++ b/hw/acpi/ich9.c
> @@ -218,6 +218,26 @@ static const VMStateDescription vmstate_cpuhp_state = {
>  }
>  };
>  
> +static bool vmstate_test_use_pcihp(void *opaque)
> +{
> +ICH9LPCPMRegs *s = opaque;
> +
> +return s->use_acpi_hotplug_bridge;
> +}
> +
> +static const VMStateDescription vmstate_pcihp_state = {
> +.name = "ich9_pm/pcihp",
> +.version_id = 1,
> +.minimum_version_id = 1,
> +.needed = vmstate_test_use_pcihp,
> +.fields  = (VMStateField[]) {
> +VMSTATE_PCI_HOTPLUG(acpi_pci_hotplug,
> +ICH9LPCPMRegs,
> +NULL),
> +VMSTATE_END_OF_LIST()
> +}
> +};
> +
>  const VMStateDescription vmstate_ich9_pm = {
>  .name = "ich9_pm",
>  .version_id = 1,
> @@ -239,6 +259,7 @@ const VMStateDescription vmstate_ich9_pm = {
>  &vmstate_memhp_state,
>  &vmstate_tco_io_state,
>  &vmstate_cpuhp_state,
> +&vmstate_pcihp_state,
>  NULL
>  }
>  };
> @@ -260,6 +281,7 @@ static void pm_reset(void *opaque)
>  }
>  pm->smi_en_wmask = ~0;
>  
> +acpi_pcihp_reset(&pm->acpi_pci_hotplug, true);
>  acpi_update_sci(&pm->acpi_regs, pm->irq);
>  }
>  
> @@ -298,6 +320,18 @@ void ich9_pm_init(PCIDevice *lpc_pci, ICH9LPCPMRegs *pm,
>  pm->enable_tco = true;
>  acpi_pm_tco_init(&pm->tco_regs, &pm->io);
>  
> +if (pm->use_acpi_hotplug_bridge) {
> +acpi_pcihp_init(OBJECT(lpc_pci),
> +&pm->acpi_pci_hotplug,
> +pci_get_bus(lpc_pci),
> +pci_address_space_io(lpc_pci),
> +true,
> +ACPI_PCIHP_ADDR_ICH9);
> +
> +qbus_set_hotplug_handler(BUS(pci_get_bus(lpc_pci)),
> + OBJECT(lpc_pci));
> +}
> +
>  pm->irq = sci_irq;
>  qemu_register_reset(pm_reset, pm);
>  pm->powerdown_notifier.notify = pm_powerdown_req;
> @@ -369,6 +403,20 @@ static void ich9_pm_set_enable_tco(Object *obj, bool 
> value, Error **errp)
>  s->pm.enable_tco = value;
>  }
>  
> +static bool ich9_pm_get_acpi_pci_hotplug(Object *obj, Error **errp)
> +{
> +ICH9LPCState *s = ICH9_LPC_DEVICE(obj);
> +
> +return s->pm.use_acpi_hotplug_bridge;
> +}
> +
> +static void ich9_pm_set_acpi_pci_hotplug(Object *obj, bool value,
> +   Error **errp)
> +{
> +ICH9LPCState *s = ICH9_LPC_DEVICE(obj);
> +
> +s->pm.use_acpi_hotplug_bridge = value;
> +}
>  void ich9_pm_add_properties(Object *obj, ICH9LPCPMRegs *pm)
>  {
>  static const uint32_t gpe0_len = ICH9_PMIO_GPE0_LEN;
> @@ -377,6 +425,7 @@ void ich9_pm_add_properties(Object *obj, ICH9LPCPMRegs 
> *pm)
>  pm->disable_s3 = 0;
>  pm->disable_s4 = 0;
>  pm->s4_val = 2;
> +pm->use_acpi_hotplug_bridge = false;
>  
>  object_property_add_uint32_ptr(obj, ACPI_PM_PROP_PM_IO_BASE,
> &pm->pm_io_base, OBJ_PROP_FLAG_READ);
> @@ -400,6 +449,9 @@ void ich9_pm_add_properties(Object *obj, ICH9LPCPMRegs 
> *pm)
>  object_property_add_bool(obj, ACPI_PM_PROP_TCO_ENABLED,
>   ich9_pm_get_enable_tco,
>   ich9_pm_set_enable_tco);
> +object_proper

Re: [PATCH 4/8] softfloat: Add float_cmask and constants

[David Hildenbrand]

On 24.09.20 03:24, Richard Henderson wrote:
> Testing more than one class at a time is better done with masks.
> This reduces the static branch count.
> 
> Signed-off-by: Richard Henderson 
> ---
>  fpu/softfloat.c | 31 ---
>  1 file changed, 24 insertions(+), 7 deletions(-)
> 
> diff --git a/fpu/softfloat.c b/fpu/softfloat.c
> index 9db55d2b11..3e625c47cd 100644
> --- a/fpu/softfloat.c
> +++ b/fpu/softfloat.c
> @@ -469,6 +469,20 @@ typedef enum __attribute__ ((__packed__)) {
>  float_class_snan,
>  } FloatClass;
>  
> +#define float_cmask(bit)  (1u << (bit))
> +
> +enum {
> +float_cmask_zero= float_cmask(float_class_zero),
> +float_cmask_normal  = float_cmask(float_class_normal),
> +float_cmask_inf = float_cmask(float_class_inf),
> +float_cmask_qnan= float_cmask(float_class_qnan),
> +float_cmask_snan= float_cmask(float_class_snan),
> +
> +float_cmask_infzero = float_cmask_zero | float_cmask_inf,
> +float_cmask_anynan  = float_cmask_qnan | float_cmask_snan,
> +};
> +
> +
>  /* Simple helpers for checking if, or what kind of, NaN we have */
>  static inline __attribute__((unused)) bool is_nan(FloatClass c)
>  {
> @@ -1335,24 +1349,27 @@ bfloat16 QEMU_FLATTEN bfloat16_mul(bfloat16 a, 
> bfloat16 b, float_status *status)
>  static FloatParts muladd_floats(FloatParts a, FloatParts b, FloatParts c,
>  int flags, float_status *s)
>  {
> -bool inf_zero = ((1 << a.cls) | (1 << b.cls)) ==
> -((1 << float_class_inf) | (1 << float_class_zero));
> -bool p_sign;
> +bool inf_zero, p_sign;
>  bool sign_flip = flags & float_muladd_negate_result;
>  FloatClass p_class;
>  uint64_t hi, lo;
>  int p_exp;
> +int ab_mask, abc_mask;
> +
> +ab_mask = float_cmask(a.cls) | float_cmask(b.cls);
> +abc_mask = float_cmask(c.cls) | ab_mask;
> +inf_zero = ab_mask == float_cmask_infzero;
>  
>  /* It is implementation-defined whether the cases of (0,inf,qnan)
>   * and (inf,0,qnan) raise InvalidOperation or not (and what QNaN
>   * they return if they do), so we have to hand this information
>   * off to the target-specific pick-a-NaN routine.
>   */
> -if (is_nan(a.cls) || is_nan(b.cls) || is_nan(c.cls)) {
> +if (unlikely(abc_mask & float_cmask_anynan)) {
>  return pick_nan_muladd(a, b, c, inf_zero, s);
>  }
>  
> -if (inf_zero) {
> +if (unlikely(inf_zero)) {
>  s->float_exception_flags |= float_flag_invalid;
>  return parts_default_nan(s);
>  }
> @@ -1367,9 +1384,9 @@ static FloatParts muladd_floats(FloatParts a, 
> FloatParts b, FloatParts c,
>  p_sign ^= 1;
>  }
>  
> -if (a.cls == float_class_inf || b.cls == float_class_inf) {
> +if (ab_mask & float_cmask_inf) {
>  p_class = float_class_inf;
> -} else if (a.cls == float_class_zero || b.cls == float_class_zero) {
> +} else if (ab_mask & float_cmask_zero) {
>  p_class = float_class_zero;
>  } else {
>  p_class = float_class_normal;
> 

Reviewed-by: David Hildenbrand 

-- 
Thanks,

David / dhildenb

[PATCH V11 7/8] hw/mips: Add Loongson-3 machine support

[Huacai Chen]

Add Loongson-3 based machine support, it use liointc as the interrupt
controler and use GPEX as the pci controller. Currently it can work with
both TCG and KVM.

As the machine model is not based on any exiting physical hardware, the
name of the machine is "loongson3-virt". It may be superseded in future
by a real machine model. If this happens, then a regular deprecation
procedure shall occur for "loongson3-virt" machine.

We now already have a full functional Linux kernel (based on Linux-5.4.x
LTS, the kvm host side and guest side have both been upstream for Linux-
5.9, but Linux-5.9 has not been released yet) here:

https://github.com/chenhuacai/linux

Of course the upstream kernel is also usable (though it is "unstable"
now):

https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git

How to use QEMU/Loongson-3?
1, Download kernel source from the above URL;
2, Build a kernel with arch/mips/configs/loongson3_defconfig;
3, Boot a Loongson-3A4000 host with this kernel (for KVM mode);
4, Build QEMU-master with this patchset;
5, modprobe kvm (only necessary for KVM mode);
6, Use QEMU with TCG:
   qemu-system-mips64el -M loongson3-virt,accel=tcg -cpu Loongson-3A1000 
-kernel  -append ...
   Use QEMU with KVM:
   qemu-system-mips64el -M loongson3-virt,accel=kvm -cpu Loongson-3A4000 
-kernel  -append ...

   The "-cpu" parameter is optional here and QEMU will use the correct type for 
TCG/KVM automatically.

Signed-off-by: Huacai Chen 
Co-developed-by: Jiaxun Yang 
---
 default-configs/mips64el-softmmu.mak |   1 +
 hw/mips/Kconfig  |  11 +
 hw/mips/loongson3_virt.c | 775 +++
 hw/mips/loongson_bootp.h | 187 +++
 hw/mips/meson.build  |   1 +
 5 files changed, 975 insertions(+)
 create mode 100644 hw/mips/loongson3_virt.c
 create mode 100644 hw/mips/loongson_bootp.h

diff --git a/default-configs/mips64el-softmmu.mak 
b/default-configs/mips64el-softmmu.mak
index 9f8a3ef156..26c660a05c 100644
--- a/default-configs/mips64el-softmmu.mak
+++ b/default-configs/mips64el-softmmu.mak
@@ -3,6 +3,7 @@
 include mips-softmmu-common.mak
 CONFIG_IDE_VIA=y
 CONFIG_FULOONG=y
+CONFIG_LOONGSON3V=y
 CONFIG_ATI_VGA=y
 CONFIG_RTL8139_PCI=y
 CONFIG_JAZZ=y
diff --git a/hw/mips/Kconfig b/hw/mips/Kconfig
index 67d39c56a4..cc5609b08c 100644
--- a/hw/mips/Kconfig
+++ b/hw/mips/Kconfig
@@ -45,6 +45,18 @@ config FULOONG
 bool
 select PCI_BONITO
 
+config LOONGSON3V
+bool
+select PCKBD
+select SERIAL
+select GOLDFISH_RTC
+select LOONGSON_LIOINTC
+select PCI_DEVICES
+select PCI_EXPRESS_GENERIC_BRIDGE
+select VIRTIO_VGA
+select QXL if SPICE
+select MSI_NONBROKEN
+
 config MIPS_CPS
 bool
 select PTIMER
diff --git a/hw/mips/loongson3_virt.c b/hw/mips/loongson3_virt.c
new file mode 100644
index 00..f9f454b47c
--- /dev/null
+++ b/hw/mips/loongson3_virt.c
@@ -0,0 +1,775 @@
+/*
+ * Generic Loongson-3 Platform support
+ *
+ * Copyright (c) 2017-2020 Huacai Chen (che...@lemote.com)
+ * Copyright (c) 2017-2020 Jiaxun Yang 
+ *
+ * This program is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation, either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program. If not, see .
+ */
+
+/*
+ * Generic virtualized PC Platform based on Loongson-3 CPU (MIPS64R2 with
+ * extensions, 800~2000MHz)
+ */
+
+#include "qemu/osdep.h"
+#include "qemu-common.h"
+#include "qemu/units.h"
+#include "qemu/cutils.h"
+#include "qapi/error.h"
+#include "cpu.h"
+#include "elf.h"
+#include "kvm_mips.h"
+#include "hw/boards.h"
+#include "hw/char/serial.h"
+#include "hw/mips/mips.h"
+#include "hw/mips/cpudevs.h"
+#include "hw/mips/fw_cfg.h"
+#include "hw/mips/loongson_bootp.h"
+#include "hw/misc/unimp.h"
+#include "hw/intc/i8259.h"
+#include "hw/loader.h"
+#include "hw/isa/superio.h"
+#include "hw/pci/msi.h"
+#include "hw/pci/pci.h"
+#include "hw/pci/pci_host.h"
+#include "hw/pci-host/gpex.h"
+#include "hw/rtc/mc146818rtc.h"
+#include "hw/usb.h"
+#include "net/net.h"
+#include "exec/address-spaces.h"
+#include "sysemu/kvm.h"
+#include "sysemu/qtest.h"
+#include "sysemu/reset.h"
+#include "sysemu/runstate.h"
+#include "qemu/log.h"
+#include "qemu/error-report.h"
+
+#define PM_CNTL_MODE  0x10
+
+/* Overall MMIO & Memory layout */
+enum {
+VIRT_LOWMEM,
+VIRT_PM,
+VIRT_FW_CFG,
+VIRT_RTC,
+VIRT_PCIE_PIO,
+VIRT_PCIE_ECAM,
+VIRT_BIOS_ROM,
+VIRT_UART,
+VIRT_LIOINTC,
+VIRT_PCIE_MMI

[PATCH V11 8/8] docs/system: Update MIPS machine documentation

[Huacai Chen]

Add Loongson-3A CPU models and Loongson-3 based machine description.

Signed-off-by: Huacai Chen 
---
 docs/system/cpu-models-mips.rst.inc | 10 --
 docs/system/target-mips.rst | 10 ++
 2 files changed, 18 insertions(+), 2 deletions(-)

diff --git a/docs/system/cpu-models-mips.rst.inc 
b/docs/system/cpu-models-mips.rst.inc
index 499b5b6fed..02cc4bb884 100644
--- a/docs/system/cpu-models-mips.rst.inc
+++ b/docs/system/cpu-models-mips.rst.inc
@@ -48,11 +48,17 @@ across all desired hosts.
 ``I6400``
 MIPS64 Processor (Release 6, 2014)
 
+``Loongson-2E``
+MIPS64 Processor (Loongson 2, 2006)
+
 ``Loongson-2F``
 MIPS64 Processor (Loongson 2, 2008)
 
-``Loongson-2E``
-MIPS64 Processor (Loongson 2, 2006)
+``Loongson-3A1000``
+MIPS64 Processor (Loongson 3, 2010)
+
+``Loongson-3A4000``
+MIPS64 Processor (Loongson 3, 2018)
 
 ``mips64dspr2``
 MIPS64 Processor (Release 2, 2006)
diff --git a/docs/system/target-mips.rst b/docs/system/target-mips.rst
index cd2a931edf..1f86ccb697 100644
--- a/docs/system/target-mips.rst
+++ b/docs/system/target-mips.rst
@@ -84,6 +84,16 @@ The Fuloong 2E emulation supports:
 
 -  RTL8139D as a network card chipset
 
+The Loongson-3 virtual platform emulation supports:
+
+-  Loongson 3A CPU
+
+-  LIOINTC as interrupt controller
+
+-  GPEX and virtio as variable devices
+
+-  Both KVM and TCG supported
+
 The mipssim pseudo board emulation provides an environment similar to
 what the proprietary MIPS emulator uses for running Linux. It supports:
 
-- 
2.17.2

Re: [PATCH 1/6] spapr: add spapr_machine_using_legacy_numa() helper

[Greg Kurz]

On Wed, 23 Sep 2020 16:34:53 -0300
Daniel Henrique Barboza  wrote:

> The changes to come to NUMA support are all guest visible. In
> theory we could just create a new 5_1 class option flag to
> avoid the changes to cascade to 5.1 and under. The reality is that
> these changes are only relevant if the machine has more than one
> NUMA node. There is no need to change guest behavior that has
> been around for years needlesly.
> 
> This new helper will be used by the next patches to determine
> whether we should retain the (soon to be) legacy NUMA behavior
> in the pSeries machine. The new behavior will only be exposed
> if:
> 
> - machine is pseries-5.2 and newer;
> - more than one NUMA node is declared in NUMA state.
> 
> Reviewed-by: David Gibson 
> Signed-off-by: Daniel Henrique Barboza 
> ---

Reviewed-by: Greg Kurz 

>  hw/ppc/spapr.c | 12 
>  include/hw/ppc/spapr.h |  2 ++
>  2 files changed, 14 insertions(+)
> 
> diff --git a/hw/ppc/spapr.c b/hw/ppc/spapr.c
> index e813c7cfb9..c5d8910a74 100644
> --- a/hw/ppc/spapr.c
> +++ b/hw/ppc/spapr.c
> @@ -294,6 +294,15 @@ static hwaddr spapr_node0_size(MachineState *machine)
>  return machine->ram_size;
>  }
>  
> +bool spapr_machine_using_legacy_numa(SpaprMachineState *spapr)
> +{
> +MachineState *machine = MACHINE(spapr);
> +SpaprMachineClass *smc = SPAPR_MACHINE_GET_CLASS(machine);
> +
> +return smc->pre_5_2_numa_associativity ||
> +   machine->numa_state->num_nodes <= 1;
> +}
> +
>  static void add_str(GString *s, const gchar *s1)
>  {
>  g_string_append_len(s, s1, strlen(s1) + 1);
> @@ -4522,8 +4531,11 @@ DEFINE_SPAPR_MACHINE(5_2, "5.2", true);
>   */
>  static void spapr_machine_5_1_class_options(MachineClass *mc)
>  {
> +SpaprMachineClass *smc = SPAPR_MACHINE_CLASS(mc);
> +
>  spapr_machine_5_2_class_options(mc);
>  compat_props_add(mc->compat_props, hw_compat_5_1, hw_compat_5_1_len);
> +smc->pre_5_2_numa_associativity = true;
>  }
>  
>  DEFINE_SPAPR_MACHINE(5_1, "5.1", false);
> diff --git a/include/hw/ppc/spapr.h b/include/hw/ppc/spapr.h
> index 114e819969..d1aae03b97 100644
> --- a/include/hw/ppc/spapr.h
> +++ b/include/hw/ppc/spapr.h
> @@ -143,6 +143,7 @@ struct SpaprMachineClass {
>  bool smp_threads_vsmt; /* set VSMT to smp_threads by default */
>  hwaddr rma_limit;  /* clamp the RMA to this size */
>  bool pre_5_1_assoc_refpoints;
> +bool pre_5_2_numa_associativity;
>  
>  void (*phb_placement)(SpaprMachineState *spapr, uint32_t index,
>uint64_t *buid, hwaddr *pio, 
> @@ -860,6 +861,7 @@ int spapr_max_server_number(SpaprMachineState *spapr);
>  void spapr_store_hpte(PowerPCCPU *cpu, hwaddr ptex,
>uint64_t pte0, uint64_t pte1);
>  void spapr_mce_req_event(PowerPCCPU *cpu, bool recovered);
> +bool spapr_machine_using_legacy_numa(SpaprMachineState *spapr);
>  
>  /* DRC callbacks. */
>  void spapr_core_release(DeviceState *dev);

Re: [PATCH 5/8] softfloat: Inline pick_nan_muladd into its caller

[David Hildenbrand]

On 24.09.20 03:24, Richard Henderson wrote:
> Because of FloatParts, there will only ever be one caller.
> Inlining allows us to re-use abc_mask for the snan test.
> 
> Signed-off-by: Richard Henderson 
> ---
>  fpu/softfloat.c | 75 +++--
>  1 file changed, 35 insertions(+), 40 deletions(-)
> 
> diff --git a/fpu/softfloat.c b/fpu/softfloat.c
> index 3e625c47cd..e038434a07 100644
> --- a/fpu/softfloat.c
> +++ b/fpu/softfloat.c
> @@ -929,45 +929,6 @@ static FloatParts pick_nan(FloatParts a, FloatParts b, 
> float_status *s)
>  return a;
>  }
>  
> -static FloatParts pick_nan_muladd(FloatParts a, FloatParts b, FloatParts c,
> -  bool inf_zero, float_status *s)
> -{
> -int which;
> -
> -if (is_snan(a.cls) || is_snan(b.cls) || is_snan(c.cls)) {
> -s->float_exception_flags |= float_flag_invalid;
> -}
> -
> -which = pickNaNMulAdd(a.cls, b.cls, c.cls, inf_zero, s);
> -
> -if (s->default_nan_mode) {
> -/* Note that this check is after pickNaNMulAdd so that function
> - * has an opportunity to set the Invalid flag.
> - */
> -which = 3;
> -}
> -
> -switch (which) {
> -case 0:
> -break;
> -case 1:
> -a = b;
> -break;
> -case 2:
> -a = c;
> -break;
> -case 3:
> -return parts_default_nan(s);
> -default:
> -g_assert_not_reached();
> -}
> -
> -if (is_snan(a.cls)) {
> -return parts_silence_nan(a, s);
> -}
> -return a;
> -}
> -
>  /*
>   * Returns the result of adding or subtracting the values of the
>   * floating-point values `a' and `b'. The operation is performed
> @@ -1366,7 +1327,41 @@ static FloatParts muladd_floats(FloatParts a, 
> FloatParts b, FloatParts c,
>   * off to the target-specific pick-a-NaN routine.
>   */
>  if (unlikely(abc_mask & float_cmask_anynan)) {
> -return pick_nan_muladd(a, b, c, inf_zero, s);
> +int which;
> +
> +if (unlikely(abc_mask & float_cmask_snan)) {
> +float_raise(float_flag_invalid, s);
> +}
> +
> +which = pickNaNMulAdd(a.cls, b.cls, c.cls, inf_zero, s);
> +
> +if (s->default_nan_mode) {
> +/*
> + * Note that this check is after pickNaNMulAdd so that function
> + * has an opportunity to set the Invalid flag for inf_zero.
> + */
> +which = 3;
> +}
> +
> +switch (which) {
> +case 0:
> +break;
> +case 1:
> +a = b;
> +break;
> +case 2:
> +a = c;
> +break;
> +case 3:
> +return parts_default_nan(s);
> +default:
> +g_assert_not_reached();
> +}
> +
> +if (is_snan(a.cls)) {
> +return parts_silence_nan(a, s);
> +}
> +return a;
>  }
>  
>  if (unlikely(inf_zero)) {
> 

Not sure if that increases readability of muladd_floats() ... sometimes
there is good reason to factor out stuff into subfunctions to improve
readability.

But the change itself looks good to me

Reviewed-by: David Hildenbrand 

-- 
Thanks,

David / dhildenb

Re: [PATCH v9 14/20] multi-process: PCI BAR read/write handling for proxy & remote endpoints

[Stefan Hajnoczi]

On Thu, Aug 27, 2020 at 11:12:25AM -0700, elena.ufimts...@oracle.com wrote:
> +static void process_bar_read(QIOChannel *ioc, MPQemuMsg *msg, Error **errp)
> +{
> +BarAccessMsg *bar_access = &msg->data.bar_access;
> +MPQemuMsg ret = { 0 };
> +MPQemuRequest req = { 0 };
> +AddressSpace *as;
> +MemTxResult res;
> +uint64_t val = 0;
> +Error *local_err = NULL;
> +
> +as = bar_access->memory ? &address_space_memory : &address_space_io;

Doesn't need to be changed yet but eventually this should directly
access BAR MemoryRegions instead of using global
address_space_memory/address_space_io. Then bar_access->addr can be
relative to the start of the BAR.

Isolating the device from global address spaces makes it possible to
support multiple devices running in the same device emulation process.

> diff --git a/hw/pci/proxy.c b/hw/pci/proxy.c
> index 23aab44d8e..d332c63bf3 100644
> --- a/hw/pci/proxy.c
> +++ b/hw/pci/proxy.c
> @@ -61,7 +61,7 @@ static int config_op_send(PCIProxyDev *pdev, uint32_t addr, 
> uint32_t *val,
>int l, unsigned int op)
>  {
>  MPQemuMsg msg = { 0 };
> -long ret = -EINVAL;
> +uint64_t ret = -EINVAL;
>  Error *local_err = NULL;
>  
>  msg.cmd = op;
> @@ -72,7 +72,7 @@ static int config_op_send(PCIProxyDev *pdev, uint32_t addr, 
> uint32_t *val,
>  
>  ret = mpqemu_msg_send_and_await_reply(&msg, pdev, &local_err);
>  if (local_err) {
> -error_report("Failed to exchange PCI_CONFIG message with remote");
> +error_report_err(local_err);
>  }
>  if (op == PCI_CONFIG_READ) {
>  *val = (uint32_t)ret;

Unrelated fixes. Please squash them into the PCI_CONFIG_READ patch.

Reviewed-by: Stefan Hajnoczi 


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Description: PGP signature

Re: [PATCH V11 0/8] mips: Add Loongson-3 machine support

[no-reply]

Patchew URL: 
https://patchew.org/QEMU/1600932956-11642-1-git-send-email-che...@lemote.com/



Hi,

This series seems to have some coding style problems. See output below for
more information:

Type: series
Message-id: 1600932956-11642-1-git-send-email-che...@lemote.com
Subject: [PATCH V11 0/8] mips: Add Loongson-3 machine support

=== TEST SCRIPT BEGIN ===
#!/bin/bash
git rev-parse base > /dev/null || exit 0
git config --local diff.renamelimit 0
git config --local diff.renames True
git config --local diff.algorithm histogram
./scripts/checkpatch.pl --mailback base..
=== TEST SCRIPT END ===

From https://github.com/patchew-project/qemu
 * [new tag] 
patchew/1600932956-11642-1-git-send-email-che...@lemote.com -> 
patchew/1600932956-11642-1-git-send-email-che...@lemote.com
Switched to a new branch 'test'
cf89714 docs/system: Update MIPS machine documentation
cabf51a hw/mips: Add Loongson-3 machine support
fd67757 hw/mips: Implement fw_cfg_arch_key_name()
dca18c2 target/mips: Add loongson-ext lsdc2 group of instructions
d6d9a34 target/mips: Add loongson-ext lswc2 group of instructions (Part 2)
7832191 target/mips: Add loongson-ext lswc2 group of instructions (Part 1)
40a536a target/mips: Fix PageMask with variable page size
5fe85fa linux-headers: Update MIPS KVM type defintition

=== OUTPUT BEGIN ===
1/8 Checking commit 5fe85fa02e96 (linux-headers: Update MIPS KVM type 
defintition)
2/8 Checking commit 40a536afdaaf (target/mips: Fix PageMask with variable page 
size)
3/8 Checking commit 7832191c4d37 (target/mips: Add loongson-ext lswc2 group of 
instructions (Part 1))
4/8 Checking commit d6d9a344b00a (target/mips: Add loongson-ext lswc2 group of 
instructions (Part 2))
5/8 Checking commit dca18c2e9cbe (target/mips: Add loongson-ext lsdc2 group of 
instructions)
6/8 Checking commit fd67757d7016 (hw/mips: Implement fw_cfg_arch_key_name())
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#16: 
new file mode 100644

total: 0 errors, 1 warnings, 60 lines checked

Patch 6/8 has style problems, please review.  If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
7/8 Checking commit cabf51ae1224 (hw/mips: Add Loongson-3 machine support)
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#80: 
new file mode 100644

WARNING: line over 80 characters
#226: FILE: hw/mips/loongson3_virt.c:142:
+static void loongson3_pm_write(void *opaque, hwaddr addr, uint64_t val, 
unsigned size)

ERROR: return is not a function, parentheses are not required
#288: FILE: hw/mips/loongson3_virt.c:204:
+return (freq * 2);

WARNING: line over 80 characters
#394: FILE: hw/mips/loongson3_virt.c:310:
+lp->boarddev_table_offset = (uintptr_t)board_devices_info(p) - 
(uintptr_t)lp;

WARNING: line over 80 characters
#510: FILE: hw/mips/loongson3_virt.c:426:
+fw_cfg_add_i16(fw_cfg, FW_CFG_MAX_CPUS, 
(uint16_t)current_machine->smp.max_cpus);

WARNING: line over 80 characters
#558: FILE: hw/mips/loongson3_virt.c:474:
+sprintf(highmemenv, "%ld", (unsigned long)(loaderparams.ram_size / MiB) - 
256);

WARNING: line over 80 characters
#644: FILE: hw/mips/loongson3_virt.c:560:
+static inline void loongson3_virt_devices_init(MachineState *machine, 
DeviceState *pic)

WARNING: line over 80 characters
#675: FILE: hw/mips/loongson3_virt.c:591:
+ get_system_io(), 0, 
virt_memmap[VIRT_PCIE_PIO].size);

WARNING: line over 80 characters
#781: FILE: hw/mips/loongson3_virt.c:697:
+/* Allocate RAM/BIOS, 0x~0x1000 is alias of 
0x8000~0x9000 */

total: 1 errors, 8 warnings, 994 lines checked

Patch 7/8 has style problems, please review.  If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.

8/8 Checking commit cf897144bf96 (docs/system: Update MIPS machine 
documentation)
=== OUTPUT END ===

Test command exited with code: 1


The full log is available at
http://patchew.org/logs/1600932956-11642-1-git-send-email-che...@lemote.com/testing.checkpatch/?type=message.
---
Email generated automatically by Patchew [https://patchew.org/].
Please send your feedback to patchew-de...@redhat.com

Re: [PATCH] hw/pci/pci: Fix slot check for plugged devices

[Michael S. Tsirkin]

On Wed, Sep 23, 2020 at 05:57:19PM +0200, Julia Suvorova wrote:
> On Wed, Sep 23, 2020 at 5:03 PM Michael S. Tsirkin  wrote:
> >
> > On Wed, Sep 23, 2020 at 11:26:36AM +0200, Julia Suvorova wrote:
> > > If devfn is assigned automatically, 'else' clauses will never be
> > > executed. And if it does not matter for the reserved and available
> > > devfn, because we have already checked it, the check for function0
> > > needs to be done again.
> > >
> > > Signed-off-by: Julia Suvorova 
> >
> > This is just cosmetics right? I wouldn't describe this as
> > a "fix" then - "simplify" would be clearer.
> 
> No, this is a bug fix. For example, if you had a root port with a
> device on it already, and you do
> 'device_add new_device,bus=the_same_root_port', then it will miss the
> last 'if' and will be added to slot 1.

OK and I think that is the only example - if devfn is not supplied
and is auto-assigned. Can you add this to commit log pls?


> > > ---
> > >  hw/pci/pci.c | 5 +++--
> > >  1 file changed, 3 insertions(+), 2 deletions(-)
> > >
> > > diff --git a/hw/pci/pci.c b/hw/pci/pci.c
> > > index de0fae10ab..ae132b0b52 100644
> > > --- a/hw/pci/pci.c
> > > +++ b/hw/pci/pci.c
> > > @@ -1034,8 +1034,9 @@ static PCIDevice *do_pci_register_device(PCIDevice 
> > > *pci_dev,
> > > PCI_SLOT(devfn), PCI_FUNC(devfn), name,
> > > bus->devices[devfn]->name);
> > >  return NULL;
> > > -} else if (dev->hotplugged &&
> > > -   pci_get_function_0(pci_dev)) {
> > > +};
> > > +
> > > +if (dev->hotplugged && pci_get_function_0(pci_dev)) {
> > >  error_setg(errp, "PCI: slot %d function 0 already ocuppied by 
> > > %s,"
> > > " new func %s cannot be exposed to guest.",
> > > PCI_SLOT(pci_get_function_0(pci_dev)->devfn),
> > > --
> > > 2.25.4
> >

Re: [PATCH 6/8] softfloat: Implement float128_muladd

[David Hildenbrand]

[...]

>  
> /*
>  | Packs the sign `zSign', the exponent `zExp', and the significand formed
>  | by the concatenation of `zSig0' and `zSig1' into a quadruple-precision
> @@ -7205,6 +7253,312 @@ float128 float128_mul(float128 a, float128 b, 
> float_status *status)
>  
>  }
>  

I do wonder if a type for Int256 would make sense - instead of manually
passing these arrays.

> +static void shortShift256Left(uint64_t p[4], unsigned count)
> +{
> +int negcount = -count & 63;

That's the same as "64 - count", right? (which I find easier to get)

> +
> +if (count == 0) {
> +return;
> +}
> +g_assert(count < 64);
> +p[0] = (p[0] << count) | (p[1] >> negcount);
> +p[1] = (p[1] << count) | (p[2] >> negcount);
> +p[2] = (p[2] << count) | (p[3] >> negcount);
> +p[3] = (p[3] << count);
> +}
> +
> +static void shift256RightJamming(uint64_t p[4], int count)
> +{
> +uint64_t in = 0;
> +
> +g_assert(count >= 0);
> +
> +count = MIN(count, 256);
> +for (; count >= 64; count -= 64) {
> +in |= p[3];
> +p[3] = p[2];
> +p[2] = p[1];
> +p[1] = p[0];
> +p[0] = 0;
> +}
> +
> +if (count) {
> +int negcount = -count & 63;

dito

> +
> +in |= p[3] << negcount;
> +p[3] = (p[2] << negcount) | (p[3] >> count);
> +p[2] = (p[1] << negcount) | (p[2] >> count);
> +p[1] = (p[0] << negcount) | (p[1] >> count);
> +p[0] = p[0] >> count;
> +}
> +p[3] |= (in != 0);

Took ma a bit longer to understand, but now I know why the function name
has "Jamming" in it :)

[...]

> +
> +float128 float128_muladd(float128 a_f, float128 b_f, float128 c_f,
> + int flags, float_status *status)
> +{
> +bool inf_zero, p_sign, sign_flip;
> +uint64_t p_frac[4];
> +FloatParts128 a, b, c;
> +int p_exp, exp_diff, shift, ab_mask, abc_mask;
> +FloatClass p_cls;
> +
> +float128_unpack(&a, a_f, status);
> +float128_unpack(&b, b_f, status);
> +float128_unpack(&c, c_f, status);
> +
> +ab_mask = float_cmask(a.cls) | float_cmask(b.cls);
> +abc_mask = float_cmask(c.cls) | ab_mask;
> +inf_zero = ab_mask == float_cmask_infzero;
> +
> +/* If any input is a NaN, select the required result. */
> +if (unlikely(abc_mask & float_cmask_anynan)) {
> +if (unlikely(abc_mask & float_cmask_snan)) {
> +float_raise(float_flag_invalid, status);
> +}
> +
> +int which = pickNaNMulAdd(a.cls, b.cls, c.cls, inf_zero, status);
> +if (status->default_nan_mode) {
> +which = 3;
> +}
> +switch (which) {
> +case 0:
> +break;
> +case 1:
> +a_f = b_f;
> +a.cls = b.cls;
> +break;
> +case 2:
> +a_f = c_f;
> +a.cls = c.cls;
> +break;
> +case 3:
> +return float128_default_nan(status);
> +}
> +if (is_snan(a.cls)) {
> +return float128_silence_nan(a_f, status);
> +}
> +return a_f;
> +}
> +
> +/* After dealing with input NaNs, look for Inf * Zero. */
> +if (unlikely(inf_zero)) {
> +float_raise(float_flag_invalid, status);
> +return float128_default_nan(status);
> +}
> +
> +p_sign = a.sign ^ b.sign;
> +
> +if (flags & float_muladd_negate_c) {
> +c.sign ^= 1;
> +}
> +if (flags & float_muladd_negate_product) {
> +p_sign ^= 1;
> +}
> +sign_flip = (flags & float_muladd_negate_result);
> +
> +if (ab_mask & float_cmask_inf) {
> +p_cls = float_class_inf;
> +} else if (ab_mask & float_cmask_zero) {
> +p_cls = float_class_zero;
> +} else {
> +p_cls = float_class_normal;
> +}
> +
> +if (c.cls == float_class_inf) {
> +if (p_cls == float_class_inf && p_sign != c.sign) {
> +/* +Inf + -Inf = NaN */
> +float_raise(float_flag_invalid, status);
> +return float128_default_nan(status);
> +}
> +/* Inf + Inf = Inf of the proper sign; reuse the return below. */
> +p_cls = float_class_inf;
> +p_sign = c.sign;
> +}
> +
> +if (p_cls == float_class_inf) {
> +return packFloat128(p_sign ^ sign_flip, 0x7fff, 0, 0);
> +}
> +
> +if (p_cls == float_class_zero) {
> +if (c.cls == float_class_zero) {
> +if (p_sign != c.sign) {
> +p_sign = status->float_rounding_mode == float_round_down;
> +}
> +return packFloat128(p_sign ^ sign_flip, 0, 0, 0);
> +}
> +
> +if (flags & float_muladd_halve_result) {
> +c.exp -= 1;
> +}
> +return roundAndPackFloat128(c.sign ^ sign_flip,
> +c.exp + 0x3fff - 1,
> +c.frac0, c.frac1, 0, status);
> + 

Re: [PATCH 0/8] softfloat: Implement float128_muladd

[David Hildenbrand]

On 24.09.20 03:24, Richard Henderson wrote:
> Plus assorted cleanups, passes tests/fp/fp-test.
> I will eventually fill in ppc and s390x assembly bits.
> 

Thanks for looking into this! Would have taken me ages to come up with
that :)


-- 
Thanks,

David / dhildenb

Re: [PATCH 2/6] spapr_numa: forbid asymmetrical NUMA setups

[Greg Kurz]

On Wed, 23 Sep 2020 16:34:54 -0300
Daniel Henrique Barboza  wrote:

> The pSeries machine does not support asymmetrical NUMA
> configurations. This doesn't make much of a different
> since we're not using user input for pSeries NUMA setup,
> but this will change in the next patches.
> 
> To avoid breaking existing setups, gate this change by
> checking for legacy NUMA support.
> 
> Signed-off-by: Daniel Henrique Barboza 
> ---
>  hw/ppc/spapr_numa.c | 34 ++
>  1 file changed, 34 insertions(+)
> 
> diff --git a/hw/ppc/spapr_numa.c b/hw/ppc/spapr_numa.c
> index 64fe567f5d..36aaa273ee 100644
> --- a/hw/ppc/spapr_numa.c
> +++ b/hw/ppc/spapr_numa.c
> @@ -19,6 +19,24 @@
>  /* Moved from hw/ppc/spapr_pci_nvlink2.c */
>  #define SPAPR_GPU_NUMA_ID   (cpu_to_be32(1))
>  
> +static bool spapr_numa_is_symmetrical(MachineState *ms)
> +{
> +int src, dst;
> +int nb_numa_nodes = ms->numa_state->num_nodes;
> +NodeInfo *numa_info = ms->numa_state->nodes;
> +
> +for (src = 0; src < nb_numa_nodes; src++) {
> +for (dst = src; dst < nb_numa_nodes; dst++) {
> +if (numa_info[src].distance[dst] !=
> +numa_info[dst].distance[src]) {
> +return false;
> +}
> +}
> +}
> +
> +return true;
> +}
> +
>  void spapr_numa_associativity_init(SpaprMachineState *spapr,
> MachineState *machine)
>  {
> @@ -61,6 +79,22 @@ void spapr_numa_associativity_init(SpaprMachineState 
> *spapr,
>  
>  spapr->numa_assoc_array[i][MAX_DISTANCE_REF_POINTS] = cpu_to_be32(i);
>  }
> +
> +/*
> + * Legacy NUMA guests (pseries-5.1 and order, or guests with only

s/order/older

> + * 1 NUMA node) will not benefit from anything we're going to do
> + * after this point.
> + */
> +if (spapr_machine_using_legacy_numa(spapr)) {
> +return;
> +}
> +
> +if (!spapr_numa_is_symmetrical(machine)) {
> +error_report("Asymmetrical NUMA topologies aren't supported "
> + "in the pSeries machine");
> +exit(1);

Even if the code base is still heavily populated with exit(1), it seems
that exit(EXIT_FAILURE) is preferred.

Anyway,

Reviewed-by: Greg Kurz 

> +}
> +
>  }
>  
>  void spapr_numa_write_associativity_dt(SpaprMachineState *spapr, void *fdt,

Re: [PATCH 3/6] spapr_numa: translate regular NUMA distance to PAPR distance

[Greg Kurz]

On Wed, 23 Sep 2020 16:34:55 -0300
Daniel Henrique Barboza  wrote:

> QEMU allows the user to set NUMA distances in the command line.
> For ACPI architectures like x86, this means that user input is
> used to populate the SLIT table, and the guest perceives the
> distances as the user chooses to.
> 
> PPC64 does not work that way. In the PAPR concept of NUMA,
> associativity relations between the NUMA nodes are provided by
> the device tree, and the guest kernel is free to calculate the
> distances as it sees fit. Given how ACPI architectures works,
> this puts the pSeries machine in a strange spot - users expect
> to define NUMA distances like in the ACPI case, but QEMU does
> not have control over it. To give pSeries users a similar
> experience, we'll need to bring kernel specifics to QEMU
> to approximate the NUMA distances.
> 
> The pSeries kernel works with the NUMA distance range 10,
> 20, 40, 80 and 160. The code starts at 10 (local distance) and
> searches for a match in the first NUMA level between the
> resources. If there is no match, the distance is doubled and
> then it proceeds to try to match in the next NUMA level. Rinse
> and repeat for MAX_DISTANCE_REF_POINTS levels.
> 
> This patch introduces a spapr_numa_PAPRify_distances() helper

Funky naming but meaningful and funny, for me at least :)

> that translates the user distances to kernel distance, which
> we're going to use to determine the associativity domains for
> the NUMA nodes.
> 
> Signed-off-by: Daniel Henrique Barboza 
> ---
>  hw/ppc/spapr_numa.c | 44 
>  1 file changed, 44 insertions(+)
> 
> diff --git a/hw/ppc/spapr_numa.c b/hw/ppc/spapr_numa.c
> index 36aaa273ee..180800b2f3 100644
> --- a/hw/ppc/spapr_numa.c
> +++ b/hw/ppc/spapr_numa.c
> @@ -37,6 +37,49 @@ static bool spapr_numa_is_symmetrical(MachineState *ms)
>  return true;
>  }
>  
> +/*
> + * This function will translate the user distances into
> + * what the kernel understand as possible values: 10
> + * (local distance), 20, 40, 80 and 160. Current heuristic
> + * is:
> + *
> + *  - distances between 11 and 30 -> rounded to 20
> + *  - distances between 31 and 60 -> rounded to 40
> + *  - distances between 61 and 120 -> rounded to 80
> + *  - everything above 120 -> 160

It isn't clear what happens when the distances are exactly
30, 60 or 120...

> + *
> + * This step can also be done in the same time as the NUMA
> + * associativity domains calculation, at the cost of extra
> + * complexity. We chose to keep it simpler.
> + *
> + * Note: this will overwrite the distance values in
> + * ms->numa_state->nodes.
> + */
> +static void spapr_numa_PAPRify_distances(MachineState *ms)
> +{
> +int src, dst;
> +int nb_numa_nodes = ms->numa_state->num_nodes;
> +NodeInfo *numa_info = ms->numa_state->nodes;
> +
> +for (src = 0; src < nb_numa_nodes; src++) {
> +for (dst = src; dst < nb_numa_nodes; dst++) {
> +uint8_t distance = numa_info[src].distance[dst];
> +uint8_t rounded_distance = 160;
> +
> +if (distance > 11 && distance < 30) {
> +rounded_distance = 20;
> +} else if (distance > 31 && distance < 60) {
> +rounded_distance = 40;
> +} else if (distance > 61 && distance < 120) {
> +rounded_distance = 80;
> +}

... and this code doesn't convert them to PAPR-friendly values
actually. I guess < should be turned into <= .

> +
> +numa_info[src].distance[dst] = rounded_distance;
> +numa_info[dst].distance[src] = rounded_distance;
> +}
> +}
> +}
> +
>  void spapr_numa_associativity_init(SpaprMachineState *spapr,
> MachineState *machine)
>  {
> @@ -95,6 +138,7 @@ void spapr_numa_associativity_init(SpaprMachineState 
> *spapr,
>  exit(1);
>  }
>  
> +spapr_numa_PAPRify_distances(machine);
>  }
>  
>  void spapr_numa_write_associativity_dt(SpaprMachineState *spapr, void *fdt,

Re: [PATCH v4] introduce vfio-user protocol specification

[Stefan Hajnoczi]

On Tue, Sep 15, 2020 at 07:29:17AM -0700, Thanos Makatos wrote:
> This patch introduces the vfio-user protocol specification (formerly
> known as VFIO-over-socket), which is designed to allow devices to be
> emulated outside QEMU, in a separate process. vfio-user reuses the
> existing VFIO defines, structs and concepts.
> 
> It has been earlier discussed as an RFC in:
> "RFC: use VFIO over a UNIX domain socket to implement device offloading"
> 
> Signed-off-by: John G Johnson 
> Signed-off-by: Thanos Makatos 

The approach looks promising. It's hard to know what changes will be
required when this is implemented, so let's not worry about getting
every detail of the spec right.

Now that there is a spec to start from, the next step is patches
implementing --device vfio-user-pci,chardev= in
hw/vfio-user/pci.c (mirroring hw/vfio/).

It should be accompanied by a test in tests/. PCI-level testing APIS for
BARs, configuration space, interrupts, etc are available in
tests/qtest/libqos/pci.h. The test case needs to include a vfio-user
device backend interact with QEMU's vfio-user-pci implementation.

I think this spec can be merged in docs/devel/ now and marked as
"subject to change (not a stable public interface)".

After the details have been proven and any necessary changes have been
made the spec can be promoted to docs/interop/ as a stable public
interface. This gives the freedom to make changes discovered when
figuring out issues like disconnect/reconnect, live migration, etc that
can be hard to get right without a working implementation.

Does this approach sound good?

Also please let us know who is working on what so additional people can
get involved in areas that need work!

Stefan


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Re: [RFC PATCH v3 3/7] hw/pci/pcie: Do not initialize slot capability if acpihp is used

[Julia Suvorova]

On Thu, Sep 24, 2020 at 9:36 AM Michael S. Tsirkin  wrote:
>
> On Thu, Sep 24, 2020 at 09:00:09AM +0200, Julia Suvorova wrote:
> > Instead of changing the hot-plug type in _OSC register, do not
> > initialize the slot capability or set the 'Slot Implemented' flag.
> > This way guest will choose ACPI hot-plug if it is preferred and leave
> > the option to use SHPC with pcie-pci-bridge.
> >
> > Signed-off-by: Julia Suvorova 
> > ---
> >  hw/i386/acpi-build.h |  2 ++
> >  hw/i386/acpi-build.c |  2 +-
> >  hw/pci/pcie.c| 16 
> >  3 files changed, 19 insertions(+), 1 deletion(-)
> >
> > diff --git a/hw/i386/acpi-build.h b/hw/i386/acpi-build.h
> > index 487ec7710f..4c5bfb3d0b 100644
> > --- a/hw/i386/acpi-build.h
> > +++ b/hw/i386/acpi-build.h
> > @@ -11,4 +11,6 @@ extern const struct AcpiGenericAddress 
> > x86_nvdimm_acpi_dsmio;
> >
> >  void acpi_setup(void);
> >
> > +Object *object_resolve_type_unambiguous(const char *typename);
> > +
> >  #endif
> > diff --git a/hw/i386/acpi-build.c b/hw/i386/acpi-build.c
> > index cf503b16af..b7811a8912 100644
> > --- a/hw/i386/acpi-build.c
> > +++ b/hw/i386/acpi-build.c
> > @@ -174,7 +174,7 @@ static void init_common_fadt_data(MachineState *ms, 
> > Object *o,
> >  *data = fadt;
> >  }
> >
> > -static Object *object_resolve_type_unambiguous(const char *typename)
> > +Object *object_resolve_type_unambiguous(const char *typename)
> >  {
> >  bool ambig;
> >  Object *o = object_resolve_path_type("", typename, &ambig);
> > diff --git a/hw/pci/pcie.c b/hw/pci/pcie.c
> > index 5b48bae0f6..c1a082e8b9 100644
> > --- a/hw/pci/pcie.c
> > +++ b/hw/pci/pcie.c
> > @@ -27,6 +27,8 @@
> >  #include "hw/pci/pci_bus.h"
> >  #include "hw/pci/pcie_regs.h"
> >  #include "hw/pci/pcie_port.h"
> > +#include "hw/i386/ich9.h"
> > +#include "hw/i386/acpi-build.h"
> >  #include "qemu/range.h"
> >
> >  //#define DEBUG_PCIE
>
>
> Not really happy with pcie.c getting an i386 dependency.
>
>
>
> > @@ -515,12 +517,26 @@ void pcie_cap_slot_unplug_request_cb(HotplugHandler 
> > *hotplug_dev,
> >  pcie_cap_slot_push_attention_button(hotplug_pdev);
> >  }
> >
> > +static bool acpi_pcihp_enabled(void)
> > +{
> > +Object *lpc = object_resolve_type_unambiguous(TYPE_ICH9_LPC_DEVICE);
> > +
> > +return lpc &&
> > +   object_property_get_bool(lpc, 
> > "acpi-pci-hotplug-with-bridge-support",
> > +NULL);
> > +
> > +}
> > +
>
> Why not just check the property unconditionally?

Ok.

> >  /* pci express slot for pci express root/downstream port
> > PCI express capability slot registers */
> >  void pcie_cap_slot_init(PCIDevice *dev, PCIESlot *s)
> >  {
> >  uint32_t pos = dev->exp.exp_cap;
> >
> > +if (acpi_pcihp_enabled()) {
> > +return;
> > +}
> > +
>
> I think I would rather not teach pcie about acpi. How about we
> change the polarity, name the property
> "pci-native-hotplug" or whatever makes sense.

I'd prefer not to change the property name since the common code in
hw/i386/acpi-build.c depends on it, but I can add a new one if it
makes any sense.

> >  pci_word_test_and_set_mask(dev->config + pos + PCI_EXP_FLAGS,
> > PCI_EXP_FLAGS_SLOT);
> >
> > --
> > 2.25.4
>

Re: [PATCH v8 1/7] block: return error-code from bdrv_invalidate_cache

[Philippe Mathieu-Daudé]

On 9/15/20 6:44 PM, Vladimir Sementsov-Ogievskiy wrote:
> This is the only coroutine wrapper from block.c and block/io.c which
> doesn't return a value, so let's convert it to the common behavior, to
> simplify moving to generated coroutine wrappers in a further commit.
> 
> Also, bdrv_invalidate_cache is a void function, returning error only
> through **errp parameter, which is considered to be bad practice, as
> it forces callers to define and propagate local_err variable, so
> conversion is good anyway.
> 
> This patch leaves the conversion of .bdrv_co_invalidate_cache() driver
> callbacks and bdrv_invalidate_cache_all() for another day.
> 
> Signed-off-by: Vladimir Sementsov-Ogievskiy 
> Reviewed-by: Eric Blake 
> ---
>  include/block/block.h |  2 +-
>  block.c   | 32 ++--
>  2 files changed, 19 insertions(+), 15 deletions(-)

Reviewed-by: Philippe Mathieu-Daudé 

Re: [PATCH v9 15/20] multi-process: Synchronize remote memory

[Stefan Hajnoczi]

On Thu, Aug 27, 2020 at 11:12:26AM -0700, elena.ufimts...@oracle.com wrote:
> From: Jagannathan Raman 
> 
> Add memory-listener object which is used to keep the view of the RAM
> in sync between QEMU and remote process.
> A MemoryListener is registered for system-memory AddressSpace. The
> listener sends SYNC_SYSMEM message to the remote process when memory
> listener commits the changes to memory, the remote process receives
> the message and processes it in the handler for SYNC_SYSMEM message.
> 
> Signed-off-by: Jagannathan Raman 
> Signed-off-by: John G Johnson 
> Signed-off-by: Elena Ufimtseva 
> ---
>  MAINTAINERS  |   2 +
>  hw/i386/remote-msg.c |   4 +
>  hw/pci/memory-sync.c | 210 +++
>  hw/pci/meson.build   |   2 +
>  hw/pci/proxy.c   |   6 +
>  include/hw/pci/memory-sync.h |  27 +
>  include/hw/pci/proxy.h   |   3 +
>  7 files changed, 254 insertions(+)
>  create mode 100644 hw/pci/memory-sync.c
>  create mode 100644 include/hw/pci/memory-sync.h

Reviewed-by: Stefan Hajnoczi 


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Re: [PATCH v8 2/7] block/io: refactor coroutine wrappers

[Philippe Mathieu-Daudé]

On 9/15/20 6:44 PM, Vladimir Sementsov-Ogievskiy wrote:
> Most of our coroutine wrappers already follow this convention:
> 
> We have 'coroutine_fn bdrv_co_()' as
> the core function, and a wrapper 'bdrv_( list>)' which does parameters packing and call bdrv_run_co().
> 
> The only outsiders are the bdrv_prwv_co and
> bdrv_common_block_status_above wrappers. Let's refactor them to behave
> as the others, it simplifies further conversion of coroutine wrappers.
> 
> This patch adds indirection layer, but it will be compensated by
> further commit, which will drop bdrv_co_prwv together with is_write
> logic, to keep read and write path separate.
> 
> Signed-off-by: Vladimir Sementsov-Ogievskiy 
> Reviewed-by: Eric Blake 
> ---
>  block/io.c | 60 +-
>  1 file changed, 32 insertions(+), 28 deletions(-)

Reviewed-by: Philippe Mathieu-Daudé 

Re: [PATCH v9 16/20] multi-process: create IOHUB object to handle irq

[Stefan Hajnoczi]

On Thu, Aug 27, 2020 at 11:12:27AM -0700, elena.ufimts...@oracle.com wrote:
> From: Jagannathan Raman 
> 
> IOHUB object is added to manage PCI IRQs. It uses KVM_IRQFD
> ioctl to create irqfd to injecting PCI interrupts to the guest.
> IOHUB object forwards the irqfd to the remote process. Remote process
> uses this fd to directly send interrupts to the guest, bypassing QEMU.
> 
> Signed-off-by: John G Johnson 
> Signed-off-by: Jagannathan Raman 
> Signed-off-by: Elena Ufimtseva 
> ---
>  MAINTAINERS|   2 +
>  hw/i386/meson.build|   1 +
>  hw/i386/remote-iohub.c | 123 +
>  hw/i386/remote-msg.c   |   4 ++
>  hw/i386/remote.c   |  10 +++
>  hw/pci/proxy.c |  58 
>  include/hw/i386/remote-iohub.h |  42 +++
>  include/hw/i386/remote.h   |   3 +
>  include/hw/pci/pci_ids.h   |   3 +
>  include/hw/pci/proxy.h |   5 ++
>  include/io/mpqemu-link.h   |   1 +
>  io/mpqemu-link.c   |   5 ++
>  12 files changed, 257 insertions(+)
>  create mode 100644 hw/i386/remote-iohub.c
>  create mode 100644 include/hw/i386/remote-iohub.h

Reviewed-by: Stefan Hajnoczi 


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Re: [PATCH v8 6/7] block: drop bdrv_prwv

[Philippe Mathieu-Daudé]

On 9/15/20 6:44 PM, Vladimir Sementsov-Ogievskiy wrote:
> Now that we are not maintaining boilerplate code for coroutine
> wrappers, there is no more sense in keeping the extra indirection layer
> of bdrv_prwv().  Let's drop it and instead generate pure bdrv_preadv()
> and bdrv_pwritev().
> 
> Currently, bdrv_pwritev() and bdrv_preadv() are returning bytes on
> success, auto generated functions will instead return zero, as their
> _co_ prototype. Still, it's simple to make the conversion safe: the
> only external user of bdrv_pwritev() is test-bdrv-drain, and it is
> comfortable enough with bdrv_co_pwritev() instead. So prototypes are
> moved to local block/coroutines.h. Next, the only internal use is
> bdrv_pread() and bdrv_pwrite(), which are modified to return bytes on
> success.
> 
> Of course, it would be great to convert bdrv_pread() and bdrv_pwrite()
> to return 0 on success. But this requires audit (and probably
> conversion) of all their users, let's leave it for another day
> refactoring.
> 
> Signed-off-by: Vladimir Sementsov-Ogievskiy 
> Reviewed-by: Eric Blake 
> ---
>  block/coroutines.h  | 10 -
>  include/block/block.h   |  2 --
>  block/io.c  | 49 -
>  tests/test-bdrv-drain.c |  2 +-
>  4 files changed, 15 insertions(+), 48 deletions(-)

Reviewed-by: Philippe Mathieu-Daudé 

Re: [PATCH v9 17/20] multi-process: Retrieve PCI info from remote process

[Stefan Hajnoczi]

On Thu, Aug 27, 2020 at 11:12:28AM -0700, elena.ufimts...@oracle.com wrote:
> From: Jagannathan Raman 
> 
> Retrieve PCI configuration info about the remote device and
> configure the Proxy PCI object based on the returned information
> 
> Signed-off-by: Elena Ufimtseva 
> Signed-off-by: John G Johnson 
> Signed-off-by: Jagannathan Raman 
> ---
>  hw/pci/proxy.c | 85 ++
>  1 file changed, 85 insertions(+)

Reviewed-by: Stefan Hajnoczi 


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Re: [PATCH v9 19/20] multi-process: add the concept description to docs/devel/qemu-multiprocess

[Stefan Hajnoczi]

On Thu, Aug 27, 2020 at 11:12:30AM -0700, elena.ufimts...@oracle.com wrote:
> From: John G Johnson 
> 
> Signed-off-by: John G Johnson 
> Signed-off-by: Elena Ufimtseva 
> Signed-off-by: Jagannathan Raman 
> ---
>  MAINTAINERS  |   1 +
>  docs/devel/index.rst |   1 +
>  docs/devel/multi-process.rst | 966 +++
>  3 files changed, 968 insertions(+)
>  create mode 100644 docs/devel/multi-process.rst

Reviewed-by: Stefan Hajnoczi 


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Re: [PATCH v9 18/20] multi-process: perform device reset in the remote process

[Stefan Hajnoczi]

On Thu, Aug 27, 2020 at 11:12:29AM -0700, elena.ufimts...@oracle.com wrote:
> From: Elena Ufimtseva 
> 
> Perform device reset in the remote process when QEMU performs
> device reset. This is required to reset the internal state
> (like registers, etc...) of emulated devices
> 
> Signed-off-by: Elena Ufimtseva 
> Signed-off-by: John G Johnson 
> Signed-off-by: Jagannathan Raman 
> ---
>  hw/i386/remote-msg.c | 25 +
>  hw/pci/proxy.c   | 20 
>  include/io/mpqemu-link.h |  1 +
>  3 files changed, 46 insertions(+)

Reviewed-by: Stefan Hajnoczi 


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Re: [PATCH v8 3/7] block: declare some coroutine functions in block/coroutines.h

[Philippe Mathieu-Daudé]

On 9/15/20 6:44 PM, Vladimir Sementsov-Ogievskiy wrote:
> We are going to keep coroutine-wrappers code (structure-packing
> parameters, BDRV_POLL wrapper functions) in separate auto-generated
> files. So, we'll need a header with declaration of original _co_
> functions, for those which are static now. As well, we'll need
> declarations for wrapper functions. Do these declarations now, as a
> preparation step.
> 
> Signed-off-by: Vladimir Sementsov-Ogievskiy 
> Reviewed-by: Eric Blake 
> ---
>  block/coroutines.h | 67 ++
>  block.c|  8 +++---
>  block/io.c | 34 +++
>  3 files changed, 88 insertions(+), 21 deletions(-)
>  create mode 100644 block/coroutines.h
> 
> diff --git a/block/coroutines.h b/block/coroutines.h
> new file mode 100644
> index 00..9ce1730a09
> --- /dev/null
> +++ b/block/coroutines.h
> @@ -0,0 +1,67 @@

Maybe also add:

   /* SPDX-License-Identifier: MIT */

> +/*
> + * Block layer I/O functions
> + *
> + * Copyright (c) 2003 Fabrice Bellard
> + *
> + * Permission is hereby granted, free of charge, to any person obtaining a 
> copy
> + * of this software and associated documentation files (the "Software"), to 
> deal
> + * in the Software without restriction, including without limitation the 
> rights
> + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
> + * copies of the Software, and to permit persons to whom the Software is
> + * furnished to do so, subject to the following conditions:
> + *
> + * The above copyright notice and this permission notice shall be included in
> + * all copies or substantial portions of the Software.
> + *
> + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
> + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
> + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
> + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
> + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 
> FROM,
> + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
> + * THE SOFTWARE.
> + */
> +
> +#ifndef BLOCK_COROUTINES_INT_H
> +#define BLOCK_COROUTINES_INT_H
> +
> +#include "block/block_int.h"
> +
> +int coroutine_fn bdrv_co_check(BlockDriverState *bs,
> +   BdrvCheckResult *res, BdrvCheckMode fix);
> +int coroutine_fn bdrv_co_invalidate_cache(BlockDriverState *bs, Error 
> **errp);
> +
> +int coroutine_fn
> +bdrv_co_prwv(BdrvChild *child, int64_t offset, QEMUIOVector *qiov,
> + bool is_write, BdrvRequestFlags flags);
> +int
> +bdrv_prwv(BdrvChild *child, int64_t offset, QEMUIOVector *qiov,
> +  bool is_write, BdrvRequestFlags flags);
> +
> +int coroutine_fn
> +bdrv_co_common_block_status_above(BlockDriverState *bs,
> +  BlockDriverState *base,
> +  bool want_zero,
> +  int64_t offset,
> +  int64_t bytes,
> +  int64_t *pnum,
> +  int64_t *map,
> +  BlockDriverState **file);
> +int
> +bdrv_common_block_status_above(BlockDriverState *bs,
> +   BlockDriverState *base,
> +   bool want_zero,
> +   int64_t offset,
> +   int64_t bytes,
> +   int64_t *pnum,
> +   int64_t *map,
> +   BlockDriverState **file);
> +

Prototypes documentation welcomed, but this is rather scarce
in the block APIs, so:

Reviewed-by: Philippe Mathieu-Daudé 

> +int coroutine_fn
> +bdrv_co_rw_vmstate(BlockDriverState *bs, QEMUIOVector *qiov, int64_t pos,
> +   bool is_read);
> +int
> +bdrv_rw_vmstate(BlockDriverState *bs, QEMUIOVector *qiov, int64_t pos,
> +bool is_read);
> +
> +#endif /* BLOCK_COROUTINES_INT_H */

Re: [PATCH v9 20/20] multi-process: add configure and usage information

[Stefan Hajnoczi]

On Thu, Aug 27, 2020 at 11:12:31AM -0700, elena.ufimts...@oracle.com wrote:
> From: Elena Ufimtseva 
> 
> Signed-off-by: Elena Ufimtseva 
> Signed-off-by: Jagannathan Raman 
> Signed-off-by: John G Johnson 
> ---
>  MAINTAINERS|  2 ++
>  docs/multi-process.rst | 67 ++
>  scripts/mpqemu-launcher.py | 49 
>  3 files changed, 118 insertions(+)
>  create mode 100644 docs/multi-process.rst
>  create mode 100755 scripts/mpqemu-launcher.py

Reviewed-by: Stefan Hajnoczi 


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Re: [PATCH v9 00/20] Initial support for multi-process Qemu

[Stefan Hajnoczi]

On Thu, Aug 27, 2020 at 11:12:11AM -0700, elena.ufimts...@oracle.com wrote:
> The v9 has the following changes:
> - Communication channel. Qemu side uses blocking call to send
>   and receive the message from the remote and cannot progress
>   further until the remote side replies. Enhanced the
>   communication channel by dropping iothread lock before blocking
>   on Qemu end. Use the co-routines on the remote end to avoid
>   blocking QMP monitor;
> - removed the heartbeat functionality, it will be added later
>   in a full extent;
> - fixed leaked errors and similar fixes;
> - eliminated bytestream passing over the channel;
> - The build system had to be changed in order to accomodate the
>   latest changes in Qemu to use Kconfig/mason.

Thanks, I left comments but I'm happy with most patches now.

Stefan


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Re: [PATCH v10 11/12] migration/dirtyrate: Implement qmp_cal_dirty_rate()/qmp_get_dirty_rate() function

[Zheng Chuan]

On 2020/9/24 3:03, Dr. David Alan Gilbert wrote:
> * Eric Blake (ebl...@redhat.com) wrote:
>> On 9/16/20 1:22 AM, Chuan Zheng wrote:
>>> Implement qmp_cal_dirty_rate()/qmp_get_dirty_rate() function which could be 
>>> called
>>>
>>> Signed-off-by: Chuan Zheng 
>>> ---
>>
>>> +++ b/qapi/migration.json
>>> @@ -1737,3 +1737,53 @@
>>>   ##
>>>   { 'enum': 'DirtyRateStatus',
>>> 'data': [ 'unstarted', 'measuring', 'measured'] }
>>> +
>>> +##
>>> +# @DirtyRateInfo:
>>> +#
>>> +# Information about current dirty page rate of vm.
>>> +#
>>> +# @dirty-rate: @dirtyrate describing the dirty page rate of vm
>>> +#  in units of MB/s.
>>> +#  If this field return '-1', it means querying is not
>>> +#  start or not complete.
>>
>> Grammar:
>>
>> it means querying has not yet started or completed.
>>
>> Should this field instead be optional, and omitted for those cases?  In
>> which case, I'd suggest:
>>
>> ...in units of MB/s, present only when querying the rate has completed.
> 
Hi, Eric.
Thanks for your review.
Yeah, it could be optional.
and should it need keep start-time and calc-time when omit dirtyrate?
like:
{"return":{"status":"measuring","start-time":3718293,"calc-time":1},"id":"libvirt-15"}
or
{"return":{"status":"unstarted","start-time":3718293,"calc-time":1},"id":"libvirt-15"}

> I've already got it queued; I'll fix up the grammar; if someone wants to
> send a change to make it optional before this version freezes that's OK.
> 
> Dave
> 
>>
>>> +#
>>> +# @status: status containing dirtyrate query status includes
>>> +#  'unstarted' or 'measuring' or 'measured'
>>> +#
>>> +# @start-time: start time in units of second for calculation
>>> +#
>>> +# @calc-time: time in units of second for sample dirty pages
>>> +#
>>> +# Since: 5.2
>>> +#
>>> +##
>>> +{ 'struct': 'DirtyRateInfo',
>>> +  'data': {'dirty-rate': 'int64',
>>> +   'status': 'DirtyRateStatus',
>>> +   'start-time': 'int64',
>>> +   'calc-time': 'int64'} }
>>> +
>>> +##
>>> +# @calc-dirty-rate:
>>> +#
>>> +# start calculating dirty page rate for vm
>>> +#
>>> +# @calc-time: time in units of second for sample dirty pages
>>> +#
>>> +# Since: 5.2
>>> +#
>>> +# Example:
>>> +#   {"command": "calc-dirty-rate", "data": {"calc-time": 1} }
>>> +#
>>> +##
>>> +{ 'command': 'calc-dirty-rate', 'data': {'calc-time': 'int64'} }
>>> +
>>> +##
>>> +# @query-dirty-rate:
>>> +#
>>> +# query dirty page rate in units of MB/s for vm
>>> +#
>>> +# Since: 5.2
>>> +##
>>> +{ 'command': 'query-dirty-rate', 'returns': 'DirtyRateInfo' }
>>>
>>
>> -- 
>> Eric Blake, Principal Software Engineer
>> Red Hat, Inc.   +1-919-301-3226
>> Virtualization:  qemu.org | libvirt.org

Re: [PATCH v2 2/2] vhost-vdpa: add trace-events

[Laurent Vivier]

On 22/09/2020 04:09, Jason Wang wrote:
> 
> On 2020/9/21 下午9:04, Laurent Vivier wrote:
>> Add trace functionis in vhost-vdpa.c.
>>
>> All traces from this file can be enabled with '-trace vhost_vdpa*'.
>>
>> Acked-by: Stefan Hajnoczi 
>> Signed-off-by: Laurent Vivier 
>> ---
>>   hw/virtio/trace-events | 29 ++
>>   hw/virtio/vhost-vdpa.c | 86 +++---
>>   2 files changed, 110 insertions(+), 5 deletions(-)
>>
>> diff --git a/hw/virtio/trace-events b/hw/virtio/trace-events
>> index 845200bf109d..2b453f77a4e3 100644
>> --- a/hw/virtio/trace-events
>> +++ b/hw/virtio/trace-events
>> @@ -22,6 +22,35 @@ vhost_user_postcopy_waker(const char *rb, uint64_t
>> rb_offset) "%s + 0x%"PRIx64
>>   vhost_user_postcopy_waker_found(uint64_t client_addr) "0x%"PRIx64
>>   vhost_user_postcopy_waker_nomatch(const char *rb, uint64_t
>> rb_offset) "%s + 0x%"PRIx64
>>   +# vhost-vdpa.c
>> +vhost_vdpa_listener_region_add(void *vdpa, uint64_t iova, uint64_t
>> llend, void *vaddr, bool readonly) "vdpa: %p iova 0x%"PRIx64" llend
>> 0x%"PRIx64" vaddr: %p read-only: %d"
>> +vhost_vdpa_listener_region_del(void *vdpa, uint64_t iova, uint64_t
>> llend) "vdpa: %p iova 0x%"PRIx64" llend 0x%"PRIx64
>> +vhost_vdpa_add_status(void *dev, uint8_t status) "dev: %p status:
>> 0x%"PRIx8
>> +vhost_vdpa_init(void *dev, void *vdpa) "dev: %p vdpa: %p"
>> +vhost_vdpa_cleanup(void *dev, void *vdpa) "dev: %p vdpa: %p"
>> +vhost_vdpa_memslots_limit(void *dev, int ret) "dev: %p = 0x%x"
>> +vhost_vdpa_set_mem_table(void *dev, uint32_t nregions, uint32_t
>> padding) "dev: %p nregions: %"PRIu32" padding: 0x%"PRIx32
>> +vhost_vdpa_dump_regions(void *dev, int i, uint64_t guest_phys_addr,
>> uint64_t memory_size, uint64_t userspace_addr, uint64_t flags_padding)
>> "dev: %p %d: guest_phys_addr: 0x%"PRIx64" memory_size: 0x%"PRIx64"
>> userspace_addr: 0x%"PRIx64" flags_padding: 0x%"PRIx64
>> +vhost_vdpa_set_features(void *dev, uint64_t features) "dev: %p
>> features: 0x%"PRIx64
>> +vhost_vdpa_get_device_id(void *dev, uint32_t device_id) "dev: %p
>> device_id %"PRIu32
>> +vhost_vdpa_reset_device(void *dev, uint8_t status) "dev: %p status:
>> 0x%"PRIx8
>> +vhost_vdpa_get_vq_index(void *dev, int idx, int vq_idx) "dev: %p idx:
>> %d vq idx: %d"
>> +vhost_vdpa_set_vring_ready(void *dev) "dev: %p"
>> +vhost_vdpa_dump_config(void *dev, const char *line) "dev: %p %s"
>> +vhost_vdpa_set_config(void *dev, uint32_t offset, uint32_t size,
>> uint32_t flags) "dev: %p offset: %"PRIu32" size: %"PRIu32" flags:
>> 0x%"PRIx32
>> +vhost_vdpa_get_config(void *dev, void *config, uint32_t config_len)
>> "dev: %p config: %p config_len: %"PRIu32
>> +vhost_vdpa_dev_start(void *dev, bool started) "dev: %p started: %d"
>> +vhost_vdpa_set_log_base(void *dev, uint64_t base, unsigned long long
>> size, int refcnt, int fd, void *log) "dev: %p base: 0x%"PRIx64" size:
>> %llu refcnt: %d fd: %d log: %p"
>> +vhost_vdpa_set_vring_addr(void *dev, unsigned int index, unsigned int
>> flags, uint64_t desc_user_addr, uint64_t used_user_addr, uint64_t
>> avail_user_addr, uint64_t log_guest_addr) "dev: %p index: %u flags:
>> 0x%x desc_user_addr: 0x%"PRIx64" used_user_addr: 0x%"PRIx64"
>> avail_user_addr: 0x%"PRIx64" log_guest_addr: 0x%"PRIx64
>> +vhost_vdpa_set_vring_num(void *dev, unsigned int index, unsigned int
>> num) "dev: %p index: %u num: %u"
>> +vhost_vdpa_set_vring_base(void *dev, unsigned int index, unsigned int
>> num) "dev: %p index: %u num: %u"
>> +vhost_vdpa_get_vring_base(void *dev, unsigned int index, unsigned int
>> num) "dev: %p index: %u num: %u"
>> +vhost_vdpa_set_vring_kick(void *dev, unsigned int index, int fd)
>> "dev: %p index: %u fd: %d"
>> +vhost_vdpa_set_vring_call(void *dev, unsigned int index, int fd)
>> "dev: %p index: %u fd: %d"
> 
> 
> It's better to add set/get_vring_addr() and dma_map()/dma_unmap().

I'm adding dma_map()/dma_unmap().

set_vring_addr() is already in the list, and get_vring_addr() doesn't
exist. As I don't see the link with vhost_vdpa_set_vring_call() I would
keep it.

Did I miss something?

Thanks,
Laurent

Re: [PATCH v2 1/1] accel/tcg: Fix computing of is_write for mips

[Kele Huang]

Got it. Thank you very much!
I will resend the same v2 patch to v1 thread.

On Wed, 23 Sep 2020 at 19:08, Philippe Mathieu-Daudé 
wrote:

> Cc'ing the TCG MIPS maintainers, and also
> Cc'ing Richard who made a comment in v1.
>
> On 9/23/20 11:38 AM, Kele Huang wrote:
> > Detect mips store instructions in cpu_signal_handler for all MIPS
> > versions, and set is_write if encountering such store instructions.
> >
> > This fixed the error while dealing with self-modifed code for MIPS.
>
> Quoting Eric Blake:
>
> "It's better to post a v2 as a new top-level thread rather
> than buried in-reply-to the v1 thread; among other things,
> burying a reply can cause automated patch tooling to miss
> the updated series."
>
> >
> > Signed-off-by: Kele Huang 
> > Signed-off-by: Xu Zou 
> > ---
> >  accel/tcg/user-exec.c | 51 ++-
> >  1 file changed, 50 insertions(+), 1 deletion(-)
> >
> > diff --git a/accel/tcg/user-exec.c b/accel/tcg/user-exec.c
> > index bb039eb32d..18784516e5 100644
> > --- a/accel/tcg/user-exec.c
> > +++ b/accel/tcg/user-exec.c
> > @@ -710,11 +710,60 @@ int cpu_signal_handler(int host_signum, void
> *pinfo,
> >  greg_t pc = uc->uc_mcontext.pc;
> >  int is_write;
> >
> > -/* XXX: compute is_write */
> >  is_write = 0;
> > +
> > +/* Detect store by reading the instruction at the program counter.
> */
> > +uint32_t insn = *(uint32_t *)pc;
> > +switch(insn>>29) {
> > +case 0x5:
> > +switch((insn>>26) & 0x7) {
> > +case 0x0: /* SB */
> > +case 0x1: /* SH */
> > +case 0x2: /* SWL */
> > +case 0x3: /* SW */
> > +case 0x4: /* SDL */
> > +case 0x5: /* SDR */
> > +case 0x6: /* SWR */
> > +is_write = 1;
> > +}
> > +break;
> > +case 0x7:
> > +switch((insn>>26) & 0x7) {
> > +case 0x0: /* SC */
> > +case 0x1: /* SWC1 */
> > +case 0x4: /* SCD */
> > +case 0x5: /* SDC1 */
> > +case 0x7: /* SD */
> > +#if !defined(__mips_isa_rev) || __mips_isa_rev < 6
> > +case 0x2: /* SWC2 */
> > +case 0x6: /* SDC2 */
> > +#endif
> > +is_write = 1;
> > +}
> > +break;
> > +}
> > +
> > +/*
> > + * Required in all versions of MIPS64 since MIPS64r1. Not available
> > + * in MIPS32r1. Required by MIPS32r2 and subsequent versions of
> MIPS32.
> > + */
> > +switch ((insn >> 3) & 0x7) {
> > +case 0x1:
> > +switch (insn & 0x7) {
> > +case 0x0: /* SWXC1 */
> > +case 0x1: /* SDXC1 */
> > +is_write = 1;
> > +}
> > +break;
> > +}
> > +
> >  return handle_cpu_signal(pc, info, is_write, &uc->uc_sigmask);
> >  }
> >
> > +#elif defined(__misp16) || defined(__mips_micromips)
> > +
> > +#error "Unsupported encoding"
> > +
> >  #elif defined(__riscv)
> >
> >  int cpu_signal_handler(int host_signum, void *pinfo,
> >
>
>

Re: [RFC PATCH v3 0/7] Use ACPI PCI hot-plug for Q35

[no-reply]

Patchew URL: https://patchew.org/QEMU/20200924070013.165026-1-jus...@redhat.com/



Hi,

This series failed the docker-mingw@fedora build test. Please find the testing 
commands and
their output below. If you have Docker installed, you can probably reproduce it
locally.

=== TEST SCRIPT BEGIN ===
#! /bin/bash
export ARCH=x86_64
make docker-image-fedora V=1 NETWORK=1
time make docker-test-mingw@fedora J=14 NETWORK=1
=== TEST SCRIPT END ===

Host machine cpu: x86_64
Target machine cpu family: x86
Target machine cpu: x86_64
../src/meson.build:10: WARNING: Module unstable-keyval has no backwards or 
forwards compatibility and might not exist in future releases.
Program sh found: YES
Program python3 found: YES (/usr/bin/python3)
Configuring ninjatool using configuration
---
The manual pages are in docs.
/usr/lib/gcc/x86_64-w64-mingw32/9.2.1/../../../../x86_64-w64-mingw32/bin/ld: 
libcommon.fa.p/hw_pci_pcie.c.obj: in function `acpi_pcihp_enabled':
/tmp/qemu-test/build/../src/hw/pci/pcie.c:522: undefined reference to 
`object_resolve_type_unambiguous'
collect2: error: ld returned 1 exit status
make: *** [Makefile.ninja:1878: qemu-system-aarch64w.exe] Error 1
make: *** Waiting for unfinished jobs
/usr/lib/gcc/x86_64-w64-mingw32/9.2.1/../../../../x86_64-w64-mingw32/bin/ld: 
libcommon.fa.p/hw_pci_pcie.c.obj: in function `acpi_pcihp_enabled':
/tmp/qemu-test/build/../src/hw/pci/pcie.c:522: undefined reference to 
`object_resolve_type_unambiguous'
collect2: error: ld returned 1 exit status
make: *** [Makefile.ninja:1876: qemu-system-aarch64.exe] Error 1
Traceback (most recent call last):
  File "./tests/docker/docker.py", line 709, in 
sys.exit(main())
---
raise CalledProcessError(retcode, cmd)
subprocess.CalledProcessError: Command '['sudo', '-n', 'docker', 'run', '--rm', 
'--label', 'com.qemu.instance.uuid=342bc147a50847f886da9b01c0ca5ec9', '-u', 
'1003', '--security-opt', 'seccomp=unconfined', '-e', 'TARGET_LIST=', '-e', 
'EXTRA_CONFIGURE_OPTS=', '-e', 'V=', '-e', 'J=14', '-e', 'DEBUG=', '-e', 
'SHOW_ENV=', '-e', 'CCACHE_DIR=/var/tmp/ccache', '-v', 
'/home/patchew2/.cache/qemu-docker-ccache:/var/tmp/ccache:z', '-v', 
'/var/tmp/patchew-tester-tmp-vmsaoknh/src/docker-src.2020-09-24-04.53.10.30016:/var/tmp/qemu:z,ro',
 'qemu/fedora', '/var/tmp/qemu/run', 'test-mingw']' returned non-zero exit 
status 2.
filter=--filter=label=com.qemu.instance.uuid=342bc147a50847f886da9b01c0ca5ec9
make[1]: *** [docker-run] Error 1
make[1]: Leaving directory `/var/tmp/patchew-tester-tmp-vmsaoknh/src'
make: *** [docker-run-test-mingw@fedora] Error 2

real4m42.837s
user0m18.829s


The full log is available at
http://patchew.org/logs/20200924070013.165026-1-jus...@redhat.com/testing.docker-mingw@fedora/?type=message.
---
Email generated automatically by Patchew [https://patchew.org/].
Please send your feedback to patchew-de...@redhat.com

[PATCH 1/3] pc-bios/s390-ccw: fix off-by-one error

[Marc Hartmayer]

This error takes effect when the magic value "zIPL" is located at the
end of a block. For example if s2_cur_blk = 0x7fe18000 and the magic
value "zIPL" is located at 0x7fe18ffc - 0x7fe18fff.

Fixes: ba831b25262a ("s390-ccw: read stage2 boot loader data to find menu")
Reviewed-by: Collin Walling 
Signed-off-by: Marc Hartmayer 
---
 pc-bios/s390-ccw/bootmap.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/pc-bios/s390-ccw/bootmap.c b/pc-bios/s390-ccw/bootmap.c
index 97205674e59a..0d29dceaa3cc 100644
--- a/pc-bios/s390-ccw/bootmap.c
+++ b/pc-bios/s390-ccw/bootmap.c
@@ -163,7 +163,7 @@ static bool find_zipl_boot_menu_banner(int *offset)
 int i;
 
 /* Menu banner starts with "zIPL" */
-for (i = 0; i < virtio_get_block_size() - 4; i++) {
+for (i = 0; i < virtio_get_block_size() - 3; i++) {
 if (magic_match(s2_cur_blk + i, ZIPL_MAGIC_EBCDIC)) {
 *offset = i;
 return true;
-- 
2.25.4

[PATCH 2/3] pc-bios/s390-ccw: break loop if a null block number is reached

[Marc Hartmayer]

Break the loop if `cur_block_nr` is a null block number because this
means that the end of chunk is reached. In this case we will try to
boot the default entry.

Fixes: ba831b25262a ("s390-ccw: read stage2 boot loader data to find menu")
Reviewed-by: Collin Walling 
Signed-off-by: Marc Hartmayer 
---
 pc-bios/s390-ccw/bootmap.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/pc-bios/s390-ccw/bootmap.c b/pc-bios/s390-ccw/bootmap.c
index 0d29dceaa3cc..08f16c5595a3 100644
--- a/pc-bios/s390-ccw/bootmap.c
+++ b/pc-bios/s390-ccw/bootmap.c
@@ -192,7 +192,7 @@ static int eckd_get_boot_menu_index(block_number_t 
s1b_block_nr)
 for (i = 0; i < STAGE2_BLK_CNT_MAX; i++) {
 cur_block_nr = eckd_block_num(&s1b->seek[i].chs);
 
-if (!cur_block_nr) {
+if (!cur_block_nr || is_null_block_number(cur_block_nr)) {
 break;
 }
 
-- 
2.25.4

Re: [PATCH 1/1] accel/tcg: Fix computing is_write for mips

[Kele Huang]

Sorry for the late reply. We make a new version submit as below.

Subject: [PATCH v2 1/1] accel/tcg: Fix computing of is_write for mips

Detect mips store instructions in cpu_signal_handler for all MIPS
versions, and set is_write if encountering such store instructions.

This fixed the error while dealing with self-modified code for MIPS.

Signed-off-by: Kele Huang 
Signed-off-by: Xu Zou 
---
 accel/tcg/user-exec.c | 51 ++-
 1 file changed, 50 insertions(+), 1 deletion(-)

diff --git a/accel/tcg/user-exec.c b/accel/tcg/user-exec.c
index bb039eb32d..18784516e5 100644
--- a/accel/tcg/user-exec.c
+++ b/accel/tcg/user-exec.c
@@ -710,11 +710,60 @@ int cpu_signal_handler(int host_signum, void *pinfo,
 greg_t pc = uc->uc_mcontext.pc;
 int is_write;

-/* XXX: compute is_write */
 is_write = 0;
+
+/* Detect store by reading the instruction at the program counter. */
+uint32_t insn = *(uint32_t *)pc;
+switch(insn>>29) {
+case 0x5:
+switch((insn>>26) & 0x7) {
+case 0x0: /* SB */
+case 0x1: /* SH */
+case 0x2: /* SWL */
+case 0x3: /* SW */
+case 0x4: /* SDL */
+case 0x5: /* SDR */
+case 0x6: /* SWR */
+is_write = 1;
+}
+break;
+case 0x7:
+switch((insn>>26) & 0x7) {
+case 0x0: /* SC */
+case 0x1: /* SWC1 */
+case 0x4: /* SCD */
+case 0x5: /* SDC1 */
+case 0x7: /* SD */
+#if !defined(__mips_isa_rev) || __mips_isa_rev < 6
+case 0x2: /* SWC2 */
+case 0x6: /* SDC2 */
+#endif
+is_write = 1;
+}
+break;
+}
+
+/*
+ * Required in all versions of MIPS64 since MIPS64r1. Not available
+ * in MIPS32r1. Required by MIPS32r2 and subsequent versions of MIPS32.
+ */
+switch ((insn >> 3) & 0x7) {
+case 0x1:
+switch (insn & 0x7) {
+case 0x0: /* SWXC1 */
+case 0x1: /* SDXC1 */
+is_write = 1;
+}
+break;
+}
+
 return handle_cpu_signal(pc, info, is_write, &uc->uc_sigmask);
 }

+#elif defined(__misp16) || defined(__mips_micromips)
+
+#error "Unsupported encoding"
+
 #elif defined(__riscv)

 int cpu_signal_handler(int host_signum, void *pinfo,
-- 
2.17.1

On Fri, 11 Sep 2020 at 01:18, Richard Henderson <
richard.hender...@linaro.org> wrote:

> On 9/10/20 12:43 AM, Kele Huang wrote:
> > Detect mips store instructions SWXC1 and SDXC1 for MIPS64 since
> > MIPS64r1, and MIPS32 since MIPS32r2.
> >
> > Signed-off-by: Kele Huang 
> > ---
> >  accel/tcg/user-exec.c | 21 +
> >  1 file changed, 21 insertions(+)
> >
> > diff --git a/accel/tcg/user-exec.c b/accel/tcg/user-exec.c
> > index bb039eb32d..e69b4d8780 100644
> > --- a/accel/tcg/user-exec.c
> > +++ b/accel/tcg/user-exec.c
> > @@ -712,6 +712,27 @@ int cpu_signal_handler(int host_signum, void *pinfo,
> >
> >  /* XXX: compute is_write */
> >  is_write = 0;
> > +
> > +/*
> > + * Detect store instructions. Required in all versions of MIPS64
> > + * since MIPS64r1. Not available in MIPS32r1. Required by MIPS32r2
> > + * and subsequent versions of MIPS32.
> > + */
> > +switch ((insn >> 3) & 0x7) {
> > +case 0x1:
> > +switch (insn & 0x7) {
> > +case 0x0: /* SWXC1 */
> > +case 0x1: /* SDXC1 */
> > +is_write = 1;
> > +break;
> > +default:
> > +break;
> > +}
> > +break;
> > +default:
> > +break;
>
>
> You should detect all of the store instructions, not just the coprocessor
> ones.
>  Compare, for example, the Sparc version around line 485.
>
> Once done, you can also remove that /* XXX */ comment just above, which
> indicates that there is work that needs doing.
>
>
> r~
>

Re: [PATCH v4 0/6] *** Add Multifd support for TLS migration ***

[Dr. David Alan Gilbert]

* Chuan Zheng (zhengch...@huawei.com) wrote:
> v3 -> v4:
> still use MigrationState field and save hostname in 
> migration_tls_channel_connect
> remove MigrationState from MultiFDSendParams
>  
> v2 -> v3:
> rebase patches on master
> 
> v1 -> v2:
> fix memoryleak of MigrationState hostname
> add tls_hostname into MultiFDSendParams for handshake use
> fix function alignment
> squash Patch005 and Patch006
> add ioc into trace-events
> 
> TLS migration could easily reach bottleneck of cpu because of encryption
> and decryption in migration thread.
> In our test, the tls migration could only reach 300MB/s under bandwidth
> of 500MB/s.
> 
> Inspired by multifd, we add multifd support for tls migration to make fully
> use of given net bandwidth at the cost of multi-cpus and could reduce
> at most of 100% migration time with 4U16G test vm.
> 
> Evaluate migration time of migration vm.
> The VM specifications for migration are as follows:
> - VM use 4-K page;
> - the number of VCPU is 4;
> - the total memory is 16Gigabit;
> - use 'mempress' tool to pressurize VM(mempress 4096 100);
> - migration flag is 73755 (8219 + 65536 (TLS)) vs 204827 (8219 + 65536 (TLS) 
> + 131072(Multifd))
> 
> +++
> |  | TLS   |  MultiFD + TLS (2 
> channel)|
> t---
> | mempress 1024 120|   25.035s |   15.067s
>  |
> 
> | mempress 1024 200|   48.798s |   25.334s
>  |
> 

Queued.

> Chuan Zheng (6):
>   migration/tls: save hostname into MigrationState
>   migration/tls: extract migration_tls_client_create for common-use
>   migration/tls: add tls_hostname into MultiFDSendParams
>   migration/tls: extract cleanup function for common-use
>   migration/tls: add support for multifd tls-handshake
>   migration/tls: add trace points for multifd-tls
> 
>  migration/channel.c|   1 +
>  migration/migration.c  |   1 +
>  migration/migration.h  |   5 ++
>  migration/multifd.c| 124 
> +++--
>  migration/multifd.h|   2 +
>  migration/tls.c|  28 +++
>  migration/tls.h|   6 +++
>  migration/trace-events |   4 ++
>  8 files changed, 149 insertions(+), 22 deletions(-)
> 
> -- 
> 1.8.3.1
> 
> 
-- 
Dr. David Alan Gilbert / dgilb...@redhat.com / Manchester, UK

Re: [RFC PATCH v3 3/7] hw/pci/pcie: Do not initialize slot capability if acpihp is used

[Michael S. Tsirkin]

On Thu, Sep 24, 2020 at 10:23:13AM +0200, Julia Suvorova wrote:
> On Thu, Sep 24, 2020 at 9:36 AM Michael S. Tsirkin  wrote:
> >
> > On Thu, Sep 24, 2020 at 09:00:09AM +0200, Julia Suvorova wrote:
> > > Instead of changing the hot-plug type in _OSC register, do not
> > > initialize the slot capability or set the 'Slot Implemented' flag.
> > > This way guest will choose ACPI hot-plug if it is preferred and leave
> > > the option to use SHPC with pcie-pci-bridge.
> > >
> > > Signed-off-by: Julia Suvorova 
> > > ---
> > >  hw/i386/acpi-build.h |  2 ++
> > >  hw/i386/acpi-build.c |  2 +-
> > >  hw/pci/pcie.c| 16 
> > >  3 files changed, 19 insertions(+), 1 deletion(-)
> > >
> > > diff --git a/hw/i386/acpi-build.h b/hw/i386/acpi-build.h
> > > index 487ec7710f..4c5bfb3d0b 100644
> > > --- a/hw/i386/acpi-build.h
> > > +++ b/hw/i386/acpi-build.h
> > > @@ -11,4 +11,6 @@ extern const struct AcpiGenericAddress 
> > > x86_nvdimm_acpi_dsmio;
> > >
> > >  void acpi_setup(void);
> > >
> > > +Object *object_resolve_type_unambiguous(const char *typename);
> > > +
> > >  #endif
> > > diff --git a/hw/i386/acpi-build.c b/hw/i386/acpi-build.c
> > > index cf503b16af..b7811a8912 100644
> > > --- a/hw/i386/acpi-build.c
> > > +++ b/hw/i386/acpi-build.c
> > > @@ -174,7 +174,7 @@ static void init_common_fadt_data(MachineState *ms, 
> > > Object *o,
> > >  *data = fadt;
> > >  }
> > >
> > > -static Object *object_resolve_type_unambiguous(const char *typename)
> > > +Object *object_resolve_type_unambiguous(const char *typename)
> > >  {
> > >  bool ambig;
> > >  Object *o = object_resolve_path_type("", typename, &ambig);
> > > diff --git a/hw/pci/pcie.c b/hw/pci/pcie.c
> > > index 5b48bae0f6..c1a082e8b9 100644
> > > --- a/hw/pci/pcie.c
> > > +++ b/hw/pci/pcie.c
> > > @@ -27,6 +27,8 @@
> > >  #include "hw/pci/pci_bus.h"
> > >  #include "hw/pci/pcie_regs.h"
> > >  #include "hw/pci/pcie_port.h"
> > > +#include "hw/i386/ich9.h"
> > > +#include "hw/i386/acpi-build.h"
> > >  #include "qemu/range.h"
> > >
> > >  //#define DEBUG_PCIE
> >
> >
> > Not really happy with pcie.c getting an i386 dependency.
> >
> >
> >
> > > @@ -515,12 +517,26 @@ void pcie_cap_slot_unplug_request_cb(HotplugHandler 
> > > *hotplug_dev,
> > >  pcie_cap_slot_push_attention_button(hotplug_pdev);
> > >  }
> > >
> > > +static bool acpi_pcihp_enabled(void)
> > > +{
> > > +Object *lpc = object_resolve_type_unambiguous(TYPE_ICH9_LPC_DEVICE);
> > > +
> > > +return lpc &&
> > > +   object_property_get_bool(lpc, 
> > > "acpi-pci-hotplug-with-bridge-support",
> > > +NULL);
> > > +
> > > +}
> > > +
> >
> > Why not just check the property unconditionally?
> 
> Ok.
> 
> > >  /* pci express slot for pci express root/downstream port
> > > PCI express capability slot registers */
> > >  void pcie_cap_slot_init(PCIDevice *dev, PCIESlot *s)
> > >  {
> > >  uint32_t pos = dev->exp.exp_cap;
> > >
> > > +if (acpi_pcihp_enabled()) {
> > > +return;
> > > +}
> > > +
> >
> > I think I would rather not teach pcie about acpi. How about we
> > change the polarity, name the property
> > "pci-native-hotplug" or whatever makes sense.
> 
> I'd prefer not to change the property name since the common code in
> hw/i386/acpi-build.c depends on it, but I can add a new one if it
> makes any sense.

And maybe prefix with "x-" so we don't commit to it as an
external API.


> > >  pci_word_test_and_set_mask(dev->config + pos + PCI_EXP_FLAGS,
> > > PCI_EXP_FLAGS_SLOT);
> > >
> > > --
> > > 2.25.4
> >

[PATCH 0/3] pc-bios: s390x: fix corner cases in booting from ECKD

[Marc Hartmayer]

The first patch fixes the scan for the string "zIPL" (which is used to
detect the start of the boot menu banner) in
`find_zipl_boot_menu_banner`. The second patch fixes the bug of not
booting the default entry if no zipl boot menu data was found.

For everybody's convenience there is a branch:
https://gitlab.com/mhartmay/qemu/-/tree/bios_fixes

Marc Hartmayer (3):
  pc-bios/s390-ccw: fix off-by-one error
  pc-bios/s390-ccw: break loop if a null block number is reached
  pc-bios/s390-ccw: Update s390-ccw.img bios binary

 pc-bios/s390-ccw.img   | Bin 42608 -> 42608 bytes
 pc-bios/s390-ccw/bootmap.c |   4 ++--
 2 files changed, 2 insertions(+), 2 deletions(-)

-- 
2.25.4

Re: [RFC PATCH v3 0/7] Use ACPI PCI hot-plug for Q35

[no-reply]

Patchew URL: https://patchew.org/QEMU/20200924070013.165026-1-jus...@redhat.com/



Hi,

This series failed the docker-quick@centos7 build test. Please find the testing 
commands and
their output below. If you have Docker installed, you can probably reproduce it
locally.

=== TEST SCRIPT BEGIN ===
#!/bin/bash
make docker-image-centos7 V=1 NETWORK=1
time make docker-test-quick@centos7 SHOW_ENV=1 J=14 NETWORK=1
=== TEST SCRIPT END ===

C linker for the host machine: cc ld.bfd 2.27-43
Host machine cpu family: x86_64
Host machine cpu: x86_64
../src/meson.build:10: WARNING: Module unstable-keyval has no backwards or 
forwards compatibility and might not exist in future releases.
Program sh found: YES
Program python3 found: YES (/usr/bin/python3)
Configuring ninjatool using configuration
---
Linking target tests/test-replication
libcommon.fa.p/hw_pci_pcie.c.o: In function `acpi_pcihp_enabled':
/tmp/qemu-test/build/../src/hw/pci/pcie.c:522: undefined reference to 
`object_resolve_type_unambiguous'
collect2: error: ld returned 1 exit status
make: *** [qemu-system-aarch64] Error 1
make: *** Waiting for unfinished jobs
Traceback (most recent call last):
  File "./tests/docker/docker.py", line 709, in 
---
raise CalledProcessError(retcode, cmd)
subprocess.CalledProcessError: Command '['sudo', '-n', 'docker', 'run', '--rm', 
'--label', 'com.qemu.instance.uuid=38644690a9934226b7e7108ea4390530', '-u', 
'1003', '--security-opt', 'seccomp=unconfined', '-e', 'TARGET_LIST=', '-e', 
'EXTRA_CONFIGURE_OPTS=', '-e', 'V=', '-e', 'J=14', '-e', 'DEBUG=', '-e', 
'SHOW_ENV=1', '-e', 'CCACHE_DIR=/var/tmp/ccache', '-v', 
'/home/patchew2/.cache/qemu-docker-ccache:/var/tmp/ccache:z', '-v', 
'/var/tmp/patchew-tester-tmp-2jqqex0j/src/docker-src.2020-09-24-04.59.06.4662:/var/tmp/qemu:z,ro',
 'qemu/centos7', '/var/tmp/qemu/run', 'test-quick']' returned non-zero exit 
status 2.
filter=--filter=label=com.qemu.instance.uuid=38644690a9934226b7e7108ea4390530
make[1]: *** [docker-run] Error 1
make[1]: Leaving directory `/var/tmp/patchew-tester-tmp-2jqqex0j/src'
make: *** [docker-run-test-quick@centos7] Error 2

real4m43.237s
user0m20.603s


The full log is available at
http://patchew.org/logs/20200924070013.165026-1-jus...@redhat.com/testing.docker-quick@centos7/?type=message.
---
Email generated automatically by Patchew [https://patchew.org/].
Please send your feedback to patchew-de...@redhat.com

[PATCH 3/3] pc-bios/s390-ccw: Update s390-ccw.img bios binary

[Marc Hartmayer]

Contains the fixes "pc-bios/s390-ccw: fix off-by-one error" and
"pc-bios/s390-ccw: break loop if a null block number is reached".

Signed-off-by: Marc Hartmayer 
---
 pc-bios/s390-ccw.img | Bin 42608 -> 42608 bytes
 1 file changed, 0 insertions(+), 0 deletions(-)

diff --git a/pc-bios/s390-ccw.img b/pc-bios/s390-ccw.img
index 
3074686a8c7448d943aa62f810d88d3e92865ef3..d166774ece9e2a3cd1d89e02acfffb68b370a363
 100644
GIT binary patch
literal 42608
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zz?Q$^J%iG&5%1Vj5!MwrO90w^Wb_OXP!Ch5cK&6kHx#x
z{;y*WuHSg1~PU(
zL#sVhHf26PH*x)MIR7Z+voo1vX_TKD&iO2EbF(bR>Z-C;g_V$AMd-Sk-2@BefUKW|
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zQQNEv<_Gznmb+q

[PATCH v4] Add a comment in bios-tables-test.c to clarify the reason behind approach

[Ani Sinha]

A comment is added in bios-tables-test.c that explains the reasoning
behind the process of updating the ACPI table blobs when new tests are added
or old tests are modified or code is committed that affect tests. The
explanation would help future contributors follow the correct process when
making code changes that affect ACPI tables.

Signed-off-by: Ani Sinha 
Acked-by: Igor Mammedov 
---
 tests/qtest/bios-tables-test.c | 7 ++-
 1 file changed, 6 insertions(+), 1 deletion(-)

Changelog:
v2: cosmetic - commit log reworded.
v3: review feedback incorporared and actual comment in the code reworded.
v4: more updates as per Igor's suggestion. Dropped some comment lines. added
ack'd by line.

diff --git a/tests/qtest/bios-tables-test.c b/tests/qtest/bios-tables-test.c
index b514b70b62..34e2e1c55b 100644
--- a/tests/qtest/bios-tables-test.c
+++ b/tests/qtest/bios-tables-test.c
@@ -11,7 +11,7 @@
  */
 
 /*
- * How to add or update the tests:
+ * How to add or update the tests or commit changes that affect ACPI tables:
  * Contributor:
  * 1. add empty files for new tables, if any, under tests/data/acpi
  * 2. list any changed files in tests/qtest/bios-tables-test-allowed-diff.h
@@ -38,6 +38,11 @@
  *  $(SRC_PATH)/tests/data/acpi/rebuild-expected-aml.sh
  * 6. Now commit any changes to the expected binary, include diff from step 4
  *in commit log.
+ *Expected binary updates needs to be a separate patch from the code that
+ *introduces changes to ACPI tables. It lets maintainer to drop
+ *and regenerate binary updates in case of merge conflicts. Further, a code
+ *change is easily reviewable but a binary blob is not (without doing a
+ *diassemly).
  * 7. Before sending patches to the list (Contributor)
  *or before doing a pull request (Maintainer), make sure
  *tests/qtest/bios-tables-test-allowed-diff.h is empty - this will ensure
-- 
2.17.1

Re: [PATCH v2 2/2] vhost-vdpa: add trace-events

[Jason Wang]

On 2020/9/24 下午4:42, Laurent Vivier wrote:

On 22/09/2020 04:09, Jason Wang wrote:

On 2020/9/21 下午9:04, Laurent Vivier wrote:

Add trace functionis in vhost-vdpa.c.

All traces from this file can be enabled with '-trace vhost_vdpa*'.

Acked-by: Stefan Hajnoczi 
Signed-off-by: Laurent Vivier 
---
   hw/virtio/trace-events | 29 ++
   hw/virtio/vhost-vdpa.c | 86 +++---
   2 files changed, 110 insertions(+), 5 deletions(-)

diff --git a/hw/virtio/trace-events b/hw/virtio/trace-events
index 845200bf109d..2b453f77a4e3 100644
--- a/hw/virtio/trace-events
+++ b/hw/virtio/trace-events
@@ -22,6 +22,35 @@ vhost_user_postcopy_waker(const char *rb, uint64_t
rb_offset) "%s + 0x%"PRIx64
   vhost_user_postcopy_waker_found(uint64_t client_addr) "0x%"PRIx64
   vhost_user_postcopy_waker_nomatch(const char *rb, uint64_t
rb_offset) "%s + 0x%"PRIx64
   +# vhost-vdpa.c
+vhost_vdpa_listener_region_add(void *vdpa, uint64_t iova, uint64_t
llend, void *vaddr, bool readonly) "vdpa: %p iova 0x%"PRIx64" llend
0x%"PRIx64" vaddr: %p read-only: %d"
+vhost_vdpa_listener_region_del(void *vdpa, uint64_t iova, uint64_t
llend) "vdpa: %p iova 0x%"PRIx64" llend 0x%"PRIx64
+vhost_vdpa_add_status(void *dev, uint8_t status) "dev: %p status:
0x%"PRIx8
+vhost_vdpa_init(void *dev, void *vdpa) "dev: %p vdpa: %p"
+vhost_vdpa_cleanup(void *dev, void *vdpa) "dev: %p vdpa: %p"
+vhost_vdpa_memslots_limit(void *dev, int ret) "dev: %p = 0x%x"
+vhost_vdpa_set_mem_table(void *dev, uint32_t nregions, uint32_t
padding) "dev: %p nregions: %"PRIu32" padding: 0x%"PRIx32
+vhost_vdpa_dump_regions(void *dev, int i, uint64_t guest_phys_addr,
uint64_t memory_size, uint64_t userspace_addr, uint64_t flags_padding)
"dev: %p %d: guest_phys_addr: 0x%"PRIx64" memory_size: 0x%"PRIx64"
userspace_addr: 0x%"PRIx64" flags_padding: 0x%"PRIx64
+vhost_vdpa_set_features(void *dev, uint64_t features) "dev: %p
features: 0x%"PRIx64
+vhost_vdpa_get_device_id(void *dev, uint32_t device_id) "dev: %p
device_id %"PRIu32
+vhost_vdpa_reset_device(void *dev, uint8_t status) "dev: %p status:
0x%"PRIx8
+vhost_vdpa_get_vq_index(void *dev, int idx, int vq_idx) "dev: %p idx:
%d vq idx: %d"
+vhost_vdpa_set_vring_ready(void *dev) "dev: %p"
+vhost_vdpa_dump_config(void *dev, const char *line) "dev: %p %s"
+vhost_vdpa_set_config(void *dev, uint32_t offset, uint32_t size,
uint32_t flags) "dev: %p offset: %"PRIu32" size: %"PRIu32" flags:
0x%"PRIx32
+vhost_vdpa_get_config(void *dev, void *config, uint32_t config_len)
"dev: %p config: %p config_len: %"PRIu32
+vhost_vdpa_dev_start(void *dev, bool started) "dev: %p started: %d"
+vhost_vdpa_set_log_base(void *dev, uint64_t base, unsigned long long
size, int refcnt, int fd, void *log) "dev: %p base: 0x%"PRIx64" size:
%llu refcnt: %d fd: %d log: %p"
+vhost_vdpa_set_vring_addr(void *dev, unsigned int index, unsigned int
flags, uint64_t desc_user_addr, uint64_t used_user_addr, uint64_t
avail_user_addr, uint64_t log_guest_addr) "dev: %p index: %u flags:
0x%x desc_user_addr: 0x%"PRIx64" used_user_addr: 0x%"PRIx64"
avail_user_addr: 0x%"PRIx64" log_guest_addr: 0x%"PRIx64
+vhost_vdpa_set_vring_num(void *dev, unsigned int index, unsigned int
num) "dev: %p index: %u num: %u"
+vhost_vdpa_set_vring_base(void *dev, unsigned int index, unsigned int
num) "dev: %p index: %u num: %u"
+vhost_vdpa_get_vring_base(void *dev, unsigned int index, unsigned int
num) "dev: %p index: %u num: %u"
+vhost_vdpa_set_vring_kick(void *dev, unsigned int index, int fd)
"dev: %p index: %u fd: %d"
+vhost_vdpa_set_vring_call(void *dev, unsigned int index, int fd)
"dev: %p index: %u fd: %d"


It's better to add set/get_vring_addr() and dma_map()/dma_unmap().

I'm adding dma_map()/dma_unmap().

set_vring_addr() is already in the list, and get_vring_addr() doesn't
exist.



Your are right. We don't have get_vring_addr() actually.



As I don't see the link with vhost_vdpa_set_vring_call() I would
keep it.

Did I miss something?



Nope, there's no link.

Please keep that.

Thanks




Thanks,
Laurent

[PATCH] numa: hmat: require parent cache description before the next level one

[Igor Mammedov]

Spec[1] defines 0 - 3 level memory side cache, however QEMU
CLI allows to specify an intermediate cache level without
specifying previous level. Such option(s) silently ignored
when building HMAT table, which leads to incomplete cache
information.
Make sure that previous level exists and error out
if it hasn't been provided.

1) ACPI 6.2A 5.2.27.5 Memory Side Cache Information Structure

Fixes: https://bugzilla.redhat.com/show_bug.cgi?id=1842877
Signed-off-by: Igor Mammedov 
---
 hw/core/numa.c | 8 +++-
 1 file changed, 7 insertions(+), 1 deletion(-)

diff --git a/hw/core/numa.c b/hw/core/numa.c
index f9593ec716..8282e0b2e6 100644
--- a/hw/core/numa.c
+++ b/hw/core/numa.c
@@ -424,7 +424,13 @@ void parse_numa_hmat_cache(MachineState *ms, 
NumaHmatCacheOptions *node,
 }
 
 if ((node->level > 1) &&
-ms->numa_state->hmat_cache[node->node_id][node->level - 1] &&
+ms->numa_state->hmat_cache[node->node_id][node->level - 1] == NULL) {
+error_setg(errp, "Cache level=%" PRIu8 " shall be defined first",
+   node->level - 1);
+return;
+}
+
+if ((node->level > 1) &&
 (node->size <=
 ms->numa_state->hmat_cache[node->node_id][node->level - 1]->size)) 
{
 error_setg(errp, "Invalid size=%" PRIu64 ", the size of level=%" PRIu8
-- 
2.27.0

Re: [PATCH v2] monitor: Use LOCK_GUARD macros

[Dr. David Alan Gilbert]

* Dr. David Alan Gilbert (git) (dgilb...@redhat.com) wrote:
> From: "Dr. David Alan Gilbert" 
> 
> Use the lock guard macros in monitor/misc.c - saves
> a lot of unlocks in error paths, and the occasional goto.
> 
> Signed-off-by: Dr. David Alan Gilbert 

Queued

> --
> v2:
>   The file changed quite a bit since my original posting, so reworked.
> 
> ---
>  monitor/misc.c | 44 ++--
>  1 file changed, 14 insertions(+), 30 deletions(-)
> 
> diff --git a/monitor/misc.c b/monitor/misc.c
> index 0b1b9b196c..9df917f464 100644
> --- a/monitor/misc.c
> +++ b/monitor/misc.c
> @@ -141,13 +141,13 @@ char *qmp_human_monitor_command(const char 
> *command_line, bool has_cpu_index,
>  handle_hmp_command(&hmp, command_line);
>  cur_mon = old_mon;
>  
> -qemu_mutex_lock(&hmp.common.mon_lock);
> -if (qstring_get_length(hmp.common.outbuf) > 0) {
> -output = g_strdup(qstring_get_str(hmp.common.outbuf));
> -} else {
> -output = g_strdup("");
> +WITH_QEMU_LOCK_GUARD(&hmp.common.mon_lock) {
> +if (qstring_get_length(hmp.common.outbuf) > 0) {
> +output = g_strdup(qstring_get_str(hmp.common.outbuf));
> +} else {
> +output = g_strdup("");
> +}
>  }
> -qemu_mutex_unlock(&hmp.common.mon_lock);
>  
>  out:
>  monitor_data_destroy(&hmp.common);
> @@ -1248,7 +1248,7 @@ void qmp_getfd(const char *fdname, Error **errp)
>  return;
>  }
>  
> -qemu_mutex_lock(&cur_mon->mon_lock);
> +QEMU_LOCK_GUARD(&cur_mon->mon_lock);
>  QLIST_FOREACH(monfd, &cur_mon->fds, next) {
>  if (strcmp(monfd->name, fdname) != 0) {
>  continue;
> @@ -1256,7 +1256,6 @@ void qmp_getfd(const char *fdname, Error **errp)
>  
>  tmp_fd = monfd->fd;
>  monfd->fd = fd;
> -qemu_mutex_unlock(&cur_mon->mon_lock);
>  /* Make sure close() is outside critical section */
>  close(tmp_fd);
>  return;
> @@ -1267,7 +1266,6 @@ void qmp_getfd(const char *fdname, Error **errp)
>  monfd->fd = fd;
>  
>  QLIST_INSERT_HEAD(&cur_mon->fds, monfd, next);
> -qemu_mutex_unlock(&cur_mon->mon_lock);
>  }
>  
>  void qmp_closefd(const char *fdname, Error **errp)
> @@ -1299,7 +1297,7 @@ int monitor_get_fd(Monitor *mon, const char *fdname, 
> Error **errp)
>  {
>  mon_fd_t *monfd;
>  
> -qemu_mutex_lock(&mon->mon_lock);
> +QEMU_LOCK_GUARD(&mon->mon_lock);
>  QLIST_FOREACH(monfd, &mon->fds, next) {
>  int fd;
>  
> @@ -1313,12 +1311,10 @@ int monitor_get_fd(Monitor *mon, const char *fdname, 
> Error **errp)
>  QLIST_REMOVE(monfd, next);
>  g_free(monfd->name);
>  g_free(monfd);
> -qemu_mutex_unlock(&mon->mon_lock);
>  
>  return fd;
>  }
>  
> -qemu_mutex_unlock(&mon->mon_lock);
>  error_setg(errp, "File descriptor named '%s' has not been found", 
> fdname);
>  return -1;
>  }
> @@ -1350,11 +1346,10 @@ void monitor_fdsets_cleanup(void)
>  MonFdset *mon_fdset;
>  MonFdset *mon_fdset_next;
>  
> -qemu_mutex_lock(&mon_fdsets_lock);
> +QEMU_LOCK_GUARD(&mon_fdsets_lock);
>  QLIST_FOREACH_SAFE(mon_fdset, &mon_fdsets, next, mon_fdset_next) {
>  monitor_fdset_cleanup(mon_fdset);
>  }
> -qemu_mutex_unlock(&mon_fdsets_lock);
>  }
>  
>  AddfdInfo *qmp_add_fd(bool has_fdset_id, int64_t fdset_id, bool has_opaque,
> @@ -1389,7 +1384,7 @@ void qmp_remove_fd(int64_t fdset_id, bool has_fd, 
> int64_t fd, Error **errp)
>  MonFdsetFd *mon_fdset_fd;
>  char fd_str[60];
>  
> -qemu_mutex_lock(&mon_fdsets_lock);
> +QEMU_LOCK_GUARD(&mon_fdsets_lock);
>  QLIST_FOREACH(mon_fdset, &mon_fdsets, next) {
>  if (mon_fdset->id != fdset_id) {
>  continue;
> @@ -1409,12 +1404,10 @@ void qmp_remove_fd(int64_t fdset_id, bool has_fd, 
> int64_t fd, Error **errp)
>  goto error;
>  }
>  monitor_fdset_cleanup(mon_fdset);
> -qemu_mutex_unlock(&mon_fdsets_lock);
>  return;
>  }
>  
>  error:
> -qemu_mutex_unlock(&mon_fdsets_lock);
>  if (has_fd) {
>  snprintf(fd_str, sizeof(fd_str), "fdset-id:%" PRId64 ", fd:%" PRId64,
>   fdset_id, fd);
> @@ -1430,7 +1423,7 @@ FdsetInfoList *qmp_query_fdsets(Error **errp)
>  MonFdsetFd *mon_fdset_fd;
>  FdsetInfoList *fdset_list = NULL;
>  
> -qemu_mutex_lock(&mon_fdsets_lock);
> +QEMU_LOCK_GUARD(&mon_fdsets_lock);
>  QLIST_FOREACH(mon_fdset, &mon_fdsets, next) {
>  FdsetInfoList *fdset_info = g_malloc0(sizeof(*fdset_info));
>  FdsetFdInfoList *fdsetfd_list = NULL;
> @@ -1460,7 +1453,6 @@ FdsetInfoList *qmp_query_fdsets(Error **errp)
>  fdset_info->next = fdset_list;
>  fdset_list = fdset_info;
>  }
> -qemu_mutex_unlock(&mon_fdsets_lock);
>  
>  return fdset_list;
>  }
> @@ -1554,7 +1546,7 @@ int monitor_fdset_dup_fd_add(int64_t fdset_id, int 
> flags)
>  #else
>  M

Re: [RFC PATCH v3 0/7] Use ACPI PCI hot-plug for Q35

[Michael S. Tsirkin]

On Thu, Sep 24, 2020 at 09:00:06AM +0200, Julia Suvorova wrote:
> The patch set consists of two parts:
> patches 1-4: introduce new feature
>  'acpi-pci-hotplug-with-bridge-support' on Q35
> patches 5-7: make the feature default along with changes in ACPI tables
> 
> This way maintainers can decide which way to choose without breaking
> the patch set.
> 
> With the feature disabled Q35 falls back to the native hot-plug.
> 
> Pros
> * no racy behavior during boot (see 110c477c2ed)
> * eject is possible - according to PCIe spec, attention button
>   press should lead to power off, and then the adapter should be
>   removed manually. As there is no power down state exists in QEMU,
>   we cannot distinguish between an eject and a power down
>   request.
> * no delay during deleting - after the actual power off software
>   must wait at least 1 second before indicating about it. This case
>   is quite important for users, it even has its own bug:
>   https://bugzilla.redhat.com/show_bug.cgi?id=1594168
> * no timer-based behavior - in addition to the previous example,
>   the attention button has a 5-second waiting period, during which
>   the operation can be canceled with a second press. While this
>   looks fine for manual button control, automation will result in
>   the need to queue or drop events, and the software receiving
>   events in all sort of unspecified combinations of attention/power
>   indicator states, which is racy and uppredictable.
> * fixes:
> * https://bugzilla.redhat.com/show_bug.cgi?id=1752465
> * https://bugzilla.redhat.com/show_bug.cgi?id=1690256
> 
> Cons:
> * lose per-port control over hot-plug (can be resolved)
> * no access to possible features presented in slot capabilities
>   (this is only surprise removal AFAIK)

something I don't quite get is whether with this one can still add
new pcie bridges and then hotplug into these with native
hotplug.

the challenge to answering this with certainty is that right now qemu
does not allow hotplugging complex devices such as bridges at all,
we only have a hack for multifunction devices.
Maybe adding a bridge as function 1 on command line, then hotplugging another 
device as
function 0 will work to test this.



> v3:
> * drop change of _OSC to allow SHPC on hotplugged bridges
> * use 'acpi-root-pci-hotplug'
> * add migration states [Igor]
> * minor style changes
> 
> v2:
> * new ioport range for acpiphp [Gerd]
> * drop find_pci_host() [Igor]
> * explain magic numbers in _OSC [Igor]
> * drop build_q35_pci_hotplug() wrapper [Igor]
> 
> Julia Suvorova (7):
>   hw/acpi/pcihp: Enhance acpi_pcihp_disable_root_bus() to support Q35
>   hw/i386/acpi-build: Add ACPI PCI hot-plug methods to Q35
>   hw/pci/pcie: Do not initialize slot capability if acpihp is used
>   hw/acpi/ich9: Enable ACPI PCI hot-plug
>   bios-tables-test: Allow changes in DSDT ACPI tables
>   hw/acpi/ich9: Set ACPI PCI hot-plug as default
>   bios-tables-test: Update golden binaries
> 
>  hw/i386/acpi-build.h  |   7 
>  include/hw/acpi/ich9.h|   5 +++
>  include/hw/acpi/pcihp.h   |   3 +-
>  hw/acpi/ich9.c|  67 ++
>  hw/acpi/pcihp.c   |  16 ---
>  hw/acpi/piix4.c   |   4 +-
>  hw/i386/acpi-build.c  |  31 --
>  hw/i386/pc.c  |   1 +
>  hw/pci/pcie.c |  16 +++
>  tests/data/acpi/q35/DSDT  | Bin 7678 -> 7950 bytes
>  tests/data/acpi/q35/DSDT.acpihmat | Bin 9002 -> 9274 bytes
>  tests/data/acpi/q35/DSDT.bridge   | Bin 7695 -> 9865 bytes
>  tests/data/acpi/q35/DSDT.cphp | Bin 8141 -> 8413 bytes
>  tests/data/acpi/q35/DSDT.dimmpxm  | Bin 9331 -> 9603 bytes
>  tests/data/acpi/q35/DSDT.ipmibt   | Bin 7753 -> 8025 bytes
>  tests/data/acpi/q35/DSDT.memhp| Bin 9037 -> 9309 bytes
>  tests/data/acpi/q35/DSDT.mmio64   | Bin 8808 -> 9080 bytes
>  tests/data/acpi/q35/DSDT.numamem  | Bin 7684 -> 7956 bytes
>  tests/data/acpi/q35/DSDT.tis  | Bin 8283 -> 8555 bytes
>  19 files changed, 129 insertions(+), 21 deletions(-)
> 
> -- 
> 2.25.4

Re: [PATCH] virtiofsd: document cache=auto default

[Dr. David Alan Gilbert]

* Stefan Hajnoczi (stefa...@redhat.com) wrote:
> From: "Harry G. Coin" 
> 
> The virtiofsd --help output documents the cache=auto default value but
> the man page does not. Fix this.
> 
> Signed-off-by: Harry G. Coin 
> Signed-off-by: Stefan Hajnoczi 

Queued

> ---
>  docs/tools/virtiofsd.rst | 1 +
>  1 file changed, 1 insertion(+)
> 
> diff --git a/docs/tools/virtiofsd.rst b/docs/tools/virtiofsd.rst
> index e33c81ed41..352a29ce3c 100644
> --- a/docs/tools/virtiofsd.rst
> +++ b/docs/tools/virtiofsd.rst
> @@ -103,6 +103,7 @@ Options
>forbids the FUSE client from caching to achieve best coherency at the cost 
> of
>performance.  ``auto`` acts similar to NFS with a 1 second metadata cache
>timeout.  ``always`` sets a long cache lifetime at the expense of 
> coherency.
> +  The default is ``auto``.
>  
>  Examples
>  
> -- 
> 2.26.2
> 
-- 
Dr. David Alan Gilbert / dgilb...@redhat.com / Manchester, UK

[PULL 09/92] target/i386: support KVM_FEATURE_ASYNC_PF_INT

[Paolo Bonzini]

From: Vitaly Kuznetsov 

Linux-5.8 introduced interrupt based mechanism for 'page ready' events
delivery and disabled the old, #PF based one (see commit 2635b5c4a0e4
"KVM: x86: interrupt based APF 'page ready' event delivery"). Linux
guest switches to using in in 5.9 (see commit b1d405751cd5 "KVM: x86:
Switch KVM guest to using interrupts for page ready APF delivery").
The feature has a new KVM_FEATURE_ASYNC_PF_INT bit assigned and
the interrupt vector is set in MSR_KVM_ASYNC_PF_INT MSR. Support this
in QEMU.

Signed-off-by: Vitaly Kuznetsov 
Message-Id: <20200908141206.357450-1-vkuzn...@redhat.com>
Signed-off-by: Paolo Bonzini 
---
 target/i386/cpu.c |  4 +++-
 target/i386/cpu.h |  1 +
 target/i386/kvm.c | 10 ++
 target/i386/machine.c | 19 +++
 4 files changed, 33 insertions(+), 1 deletion(-)

diff --git a/target/i386/cpu.c b/target/i386/cpu.c
index 1c58f764dc..23e9a17a04 100644
--- a/target/i386/cpu.c
+++ b/target/i386/cpu.c
@@ -799,7 +799,7 @@ static FeatureWordInfo feature_word_info[FEATURE_WORDS] = {
 "kvmclock", "kvm-nopiodelay", "kvm-mmu", "kvmclock",
 "kvm-asyncpf", "kvm-steal-time", "kvm-pv-eoi", "kvm-pv-unhalt",
 NULL, "kvm-pv-tlb-flush", NULL, "kvm-pv-ipi",
-"kvm-poll-control", "kvm-pv-sched-yield", NULL, NULL,
+"kvm-poll-control", "kvm-pv-sched-yield", "kvm-asyncpf-int", NULL,
 NULL, NULL, NULL, NULL,
 NULL, NULL, NULL, NULL,
 "kvmclock-stable-bit", NULL, NULL, NULL,
@@ -4105,6 +4105,7 @@ static PropValue kvm_default_props[] = {
 { "kvmclock", "on" },
 { "kvm-nopiodelay", "on" },
 { "kvm-asyncpf", "on" },
+{ "kvm-asyncpf-int", "on" },
 { "kvm-steal-time", "on" },
 { "kvm-pv-eoi", "on" },
 { "kvmclock-stable-bit", "on" },
@@ -6988,6 +6989,7 @@ static void x86_cpu_initfn(Object *obj)
 object_property_add_alias(obj, "kvm_nopiodelay", obj, "kvm-nopiodelay");
 object_property_add_alias(obj, "kvm_mmu", obj, "kvm-mmu");
 object_property_add_alias(obj, "kvm_asyncpf", obj, "kvm-asyncpf");
+object_property_add_alias(obj, "kvm_asyncpf_int", obj, "kvm-asyncpf-int");
 object_property_add_alias(obj, "kvm_steal_time", obj, "kvm-steal-time");
 object_property_add_alias(obj, "kvm_pv_eoi", obj, "kvm-pv-eoi");
 object_property_add_alias(obj, "kvm_pv_unhalt", obj, "kvm-pv-unhalt");
diff --git a/target/i386/cpu.h b/target/i386/cpu.h
index f519d2bfd4..51c1d5f60a 100644
--- a/target/i386/cpu.h
+++ b/target/i386/cpu.h
@@ -1492,6 +1492,7 @@ typedef struct CPUX86State {
 uint64_t wall_clock_msr;
 uint64_t steal_time_msr;
 uint64_t async_pf_en_msr;
+uint64_t async_pf_int_msr;
 uint64_t pv_eoi_en_msr;
 uint64_t poll_control_msr;
 
diff --git a/target/i386/kvm.c b/target/i386/kvm.c
index 9efb07e7c8..06c2025c67 100644
--- a/target/i386/kvm.c
+++ b/target/i386/kvm.c
@@ -287,6 +287,7 @@ static const struct kvm_para_features {
 { KVM_CAP_NOP_IO_DELAY, KVM_FEATURE_NOP_IO_DELAY },
 { KVM_CAP_PV_MMU, KVM_FEATURE_MMU_OP },
 { KVM_CAP_ASYNC_PF, KVM_FEATURE_ASYNC_PF },
+{ KVM_CAP_ASYNC_PF_INT, KVM_FEATURE_ASYNC_PF_INT },
 };
 
 static int get_para_features(KVMState *s)
@@ -2821,6 +2822,9 @@ static int kvm_put_msrs(X86CPU *cpu, int level)
 if (env->features[FEAT_KVM] & (1 << KVM_FEATURE_ASYNC_PF)) {
 kvm_msr_entry_add(cpu, MSR_KVM_ASYNC_PF_EN, env->async_pf_en_msr);
 }
+if (env->features[FEAT_KVM] & (1 << KVM_FEATURE_ASYNC_PF_INT)) {
+kvm_msr_entry_add(cpu, MSR_KVM_ASYNC_PF_EN, env->async_pf_int_msr);
+}
 if (env->features[FEAT_KVM] & (1 << KVM_FEATURE_PV_EOI)) {
 kvm_msr_entry_add(cpu, MSR_KVM_PV_EOI_EN, env->pv_eoi_en_msr);
 }
@@ -3206,6 +3210,9 @@ static int kvm_get_msrs(X86CPU *cpu)
 if (env->features[FEAT_KVM] & (1 << KVM_FEATURE_ASYNC_PF)) {
 kvm_msr_entry_add(cpu, MSR_KVM_ASYNC_PF_EN, 0);
 }
+if (env->features[FEAT_KVM] & (1 << KVM_FEATURE_ASYNC_PF_INT)) {
+kvm_msr_entry_add(cpu, MSR_KVM_ASYNC_PF_INT, 0);
+}
 if (env->features[FEAT_KVM] & (1 << KVM_FEATURE_PV_EOI)) {
 kvm_msr_entry_add(cpu, MSR_KVM_PV_EOI_EN, 0);
 }
@@ -3446,6 +3453,9 @@ static int kvm_get_msrs(X86CPU *cpu)
 case MSR_KVM_ASYNC_PF_EN:
 env->async_pf_en_msr = msrs[i].data;
 break;
+case MSR_KVM_ASYNC_PF_INT:
+env->async_pf_int_msr = msrs[i].data;
+break;
 case MSR_KVM_PV_EOI_EN:
 env->pv_eoi_en_msr = msrs[i].data;
 break;
diff --git a/target/i386/machine.c b/target/i386/machine.c
index b1acf7d0ef..233e46bb70 100644
--- a/target/i386/machine.c
+++ b/target/i386/machine.c
@@ -394,6 +394,13 @@ static bool async_pf_msr_needed(void *opaque)
 return cpu->env.async_pf_en_msr != 0;
 }
 
+static bool async_pf_int_msr_needed(void *opaque)
+{
+X86CPU *cpu = opaque;
+
+return cpu->env.async_pf_int_msr != 0;
+}
+
 s

[PULL 03/92] ninjatool: rebuild multi-output targets if outputs are missing

[Paolo Bonzini]

The "stamp file trick" used to group targets of a single multi-output rule
prevents the user from deleting one such target in order to force its
rebuild.  Doing so will not touch the stamp file, and therefore only
the dummy ":" command will be executed.

With this patch, ninjatool writes rules that force-rebuild the stamp
file if any of its outputs are missing.  Rebuilding the missing
target therefore causes the stamp file to be rebuilt too.

Reported-by: Markus Armbruster 
Signed-off-by: Paolo Bonzini 
---
 scripts/ninjatool.py | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/scripts/ninjatool.py b/scripts/ninjatool.py
index 627a1cab45..6f0e35c727 100755
--- a/scripts/ninjatool.py
+++ b/scripts/ninjatool.py
@@ -908,6 +908,9 @@ class Ninja2Make(NinjaParserEventsWithVars):
 else:
 stamp = '%s@%s.stamp' % (rule, sha1_text(targets)[0:11])
 self.print('%s: %s; @:' % (targets, stamp))
+self.print('ifneq (%s, $(wildcard %s))' % (targets, targets))
+self.print('.PHONY: %s' % (stamp, ))
+self.print('endif')
 self.print('%s: %s | %s; ${ninja-command-restat}' % (stamp, 
inputs, orderonly))
 self.rule_targets[rule].append(stamp)
 self.stamp_targets[rule].append(stamp)
-- 
2.26.2

[PULL 05/92] meson: error out if qemu_suffix starts with /

[Paolo Bonzini]

From: Marc-André Lureau 

Since the variable is used for path concatenation, the result would
ignore the prefix directory altogether.

Signed-off-by: Marc-André Lureau 
Signed-off-by: Paolo Bonzini 
---
 meson.build | 5 +
 1 file changed, 5 insertions(+)

diff --git a/meson.build b/meson.build
index f4d1ab1096..bb4259e7f0 100644
--- a/meson.build
+++ b/meson.build
@@ -17,6 +17,11 @@ config_host = keyval.load(meson.current_build_dir() / 
'config-host.mak')
 enable_modules = 'CONFIG_MODULES' in config_host
 enable_static = 'CONFIG_STATIC' in config_host
 build_docs = 'BUILD_DOCS' in config_host
+
+if get_option('qemu_suffix').startswith('/')
+  error('qemu_suffix cannot start with a /')
+endif
+
 qemu_datadir = get_option('datadir') / get_option('qemu_suffix')
 qemu_docdir = get_option('docdir') / get_option('qemu_suffix')
 config_host_data = configuration_data()
-- 
2.26.2

[PULL 02/92] meson: clean up build_by_default

[Paolo Bonzini]

Build all executables by default except for the known-broken ones.

This also allows running qemu-iotests without manually building
socket_scm_helper.

Reported-by: Max Reitz 
Tested-by: Max Reitz 
Signed-off-by: Paolo Bonzini 
---
 docs/devel/build-system.rst| 5 +
 tests/fp/meson.build   | 2 --
 tests/meson.build  | 5 ++---
 tests/qemu-iotests/meson.build | 3 +--
 trace/meson.build  | 1 -
 ui/shader/meson.build  | 1 -
 6 files changed, 8 insertions(+), 9 deletions(-)

diff --git a/docs/devel/build-system.rst b/docs/devel/build-system.rst
index 08e85c69e1..2ee368fad6 100644
--- a/docs/devel/build-system.rst
+++ b/docs/devel/build-system.rst
@@ -193,6 +193,11 @@ compilation as possible. The Meson "sourceset" 
functionality is used
 to list the files and their dependency on various configuration  
 symbols.
 
+All executables are built by default, except for some `contrib/`
+binaries that are known to fail to build on some platforms (for example
+32-bit or big-endian platforms).  Tests are also built by default,
+though that might change in the future.
+
 Various subsystems that are common to both tools and emulators have
 their own sourceset, for example `block_ss` for the block device subsystem,
 `chardev_ss` for the character device subsystem, etc.  These sourcesets
diff --git a/tests/fp/meson.build b/tests/fp/meson.build
index 8779a17aab..24739ad421 100644
--- a/tests/fp/meson.build
+++ b/tests/fp/meson.build
@@ -541,7 +541,6 @@ fpcflags += [
 fptest = executable(
   'fp-test',
   ['fp-test.c', tfdir / 'slowfloat.c', '../../fpu/softfloat.c'],
-  build_by_default: false,
   link_with: [libtestfloat, libsoftfloat],
   dependencies: [qemuutil],
   include_directories: [sfinc, include_directories(tfdir)],
@@ -628,7 +627,6 @@ test('fp-test:mulAdd', fptest,
 fpbench = executable(
   'fp-bench',
   ['fp-bench.c', '../../fpu/softfloat.c'],
-  build_by_default: false,
   link_with: [libtestfloat, libsoftfloat],
   dependencies: [qemuutil],
   include_directories: [sfinc, include_directories(tfdir)],
diff --git a/tests/meson.build b/tests/meson.build
index 70203890a1..116d9a2654 100644
--- a/tests/meson.build
+++ b/tests/meson.build
@@ -248,12 +248,11 @@ foreach bench_name, deps: benchs
 suite: ['speed'])
 endforeach
 
-if have_tools and 'CONFIG_VHOST_USER' in config_host
+if have_tools and 'CONFIG_VHOST_USER' in config_host and 'CONFIG_LINUX' in 
config_host
   executable('vhost-user-bridge',
  sources: files('vhost-user-bridge.c'),
  link_with: [libvhost_user],
- dependencies: [qemuutil],
- build_by_default: false)
+ dependencies: [qemuutil])
 endif
 
 if have_system and 'CONFIG_POSIX' in config_host
diff --git a/tests/qemu-iotests/meson.build b/tests/qemu-iotests/meson.build
index 60470936b4..67aed1e492 100644
--- a/tests/qemu-iotests/meson.build
+++ b/tests/qemu-iotests/meson.build
@@ -1,6 +1,5 @@
 if 'CONFIG_LINUX' in config_host
-socket_scm_helper = executable('socket_scm_helper', 'socket_scm_helper.c',
-build_by_default: false)
+socket_scm_helper = executable('socket_scm_helper', 'socket_scm_helper.c')
 else
 socket_scm_helper = []
 endif
diff --git a/trace/meson.build b/trace/meson.build
index b36937d3a6..d5fc45c628 100644
--- a/trace/meson.build
+++ b/trace/meson.build
@@ -70,7 +70,6 @@ foreach d : [
 output: d[0],
 input: meson.source_root() / 'trace-events',
 command: [ tracetool, '--group=root', 
'--format=@0@'.format(d[1]), '@INPUT@' ],
-build_by_default: true, # to be removed when added to a target
 capture: true)
   specific_ss.add(gen)
 endforeach
diff --git a/ui/shader/meson.build b/ui/shader/meson.build
index f69e44ed89..592bf596b9 100644
--- a/ui/shader/meson.build
+++ b/ui/shader/meson.build
@@ -9,7 +9,6 @@ foreach e : shaders
   genh += custom_target(output,
 output: output,
 capture: true,
-build_by_default: true, # to be removed when added to a target
 input: files('@0@.@1@'.format(e[0], e[1])),
 command: [shaderinclude, '@INPUT0@'])
 endforeach
-- 
2.26.2

[PULL 06/92] WHPX: vmware cpuid leaf for tsc and apic frequency

[Paolo Bonzini]

From: Sunil Muthuswamy 

Newer versions of WHPX provide the capability to query the tsc
and apic frequency. Expose these through the vmware cpuid leaf.
This patch doesnt support setting the tsc frequency; that will
come as a separate fix.

Signed-off-by: Sunil Muthuswamy 
Message-Id: 

Signed-off-by: Paolo Bonzini 
---
 target/i386/whp-dispatch.h |  3 +-
 target/i386/whpx-all.c | 96 +-
 2 files changed, 87 insertions(+), 12 deletions(-)

diff --git a/target/i386/whp-dispatch.h b/target/i386/whp-dispatch.h
index e4695c349f..b18aba20ed 100644
--- a/target/i386/whp-dispatch.h
+++ b/target/i386/whp-dispatch.h
@@ -2,10 +2,11 @@
 #define WHP_DISPATCH_H
 
 #include 
-
 #include 
 #include 
 
+#define WHV_E_UNKNOWN_CAPABILITY 0x80370300L
+
 #define LIST_WINHVPLATFORM_FUNCTIONS(X) \
   X(HRESULT, WHvGetCapability, (WHV_CAPABILITY_CODE CapabilityCode, VOID* 
CapabilityBuffer, UINT32 CapabilityBufferSizeInBytes, UINT32* 
WrittenSizeInBytes)) \
   X(HRESULT, WHvCreatePartition, (WHV_PARTITION_HANDLE* Partition)) \
diff --git a/target/i386/whpx-all.c b/target/i386/whpx-all.c
index c78baac6df..3fad7928e8 100644
--- a/target/i386/whpx-all.c
+++ b/target/i386/whpx-all.c
@@ -27,6 +27,8 @@
 #include 
 #include 
 
+#define HYPERV_APIC_BUS_FREQUENCY  (2ULL)
+
 struct whpx_state {
 uint64_t mem_quota;
 WHV_PARTITION_HANDLE partition;
@@ -1061,6 +1063,18 @@ static int whpx_vcpu_run(CPUState *cpu)
 cpu_x86_cpuid(env, cpuid_fn, 0, (UINT32 *)&rax, (UINT32 *)&rbx,
 (UINT32 *)&rcx, (UINT32 *)&rdx);
 switch (cpuid_fn) {
+case 0x4000:
+/* Expose the vmware cpu frequency cpuid leaf */
+rax = 0x4010;
+rbx = rcx = rdx = 0;
+break;
+
+case 0x4010:
+rax = env->tsc_khz;
+rbx = env->apic_bus_freq / 1000; /* Hz to KHz */
+rcx = rdx = 0;
+break;
+
 case 0x8001:
 /* Remove any support of OSVW */
 rcx &= ~CPUID_EXT3_OSVW;
@@ -1191,8 +1205,12 @@ int whpx_init_vcpu(CPUState *cpu)
 {
 HRESULT hr;
 struct whpx_state *whpx = &whpx_global;
-struct whpx_vcpu *vcpu;
+struct whpx_vcpu *vcpu = NULL;
 Error *local_error = NULL;
+struct CPUX86State *env = (CPUArchState *)(cpu->env_ptr);
+X86CPU *x86_cpu = X86_CPU(cpu);
+UINT64 freq = 0;
+int ret;
 
 /* Add migration blockers for all unsupported features of the
  * Windows Hypervisor Platform
@@ -1207,7 +1225,8 @@ int whpx_init_vcpu(CPUState *cpu)
 error_report_err(local_error);
 migrate_del_blocker(whpx_migration_blocker);
 error_free(whpx_migration_blocker);
-return -EINVAL;
+ret = -EINVAL;
+goto error;
 }
 }
 
@@ -1215,7 +1234,8 @@ int whpx_init_vcpu(CPUState *cpu)
 
 if (!vcpu) {
 error_report("WHPX: Failed to allocte VCPU context.");
-return -ENOMEM;
+ret = -ENOMEM;
+goto error;
 }
 
 hr = whp_dispatch.WHvEmulatorCreateEmulator(
@@ -1224,8 +1244,8 @@ int whpx_init_vcpu(CPUState *cpu)
 if (FAILED(hr)) {
 error_report("WHPX: Failed to setup instruction completion support,"
  " hr=%08lx", hr);
-g_free(vcpu);
-return -EINVAL;
+ret = -EINVAL;
+goto error;
 }
 
 hr = whp_dispatch.WHvCreateVirtualProcessor(
@@ -1234,17 +1254,72 @@ int whpx_init_vcpu(CPUState *cpu)
 error_report("WHPX: Failed to create a virtual processor,"
  " hr=%08lx", hr);
 whp_dispatch.WHvEmulatorDestroyEmulator(vcpu->emulator);
-g_free(vcpu);
-return -EINVAL;
+ret = -EINVAL;
+goto error;
 }
 
-vcpu->interruptable = true;
+/*
+ * vcpu's TSC frequency is either specified by user, or use the value
+ * provided by Hyper-V if the former is not present. In the latter case, we
+ * query it from Hyper-V and record in env->tsc_khz, so that vcpu's TSC
+ * frequency can be migrated later via this field.
+ */
+if (!env->tsc_khz) {
+hr = whp_dispatch.WHvGetCapability(
+WHvCapabilityCodeProcessorClockFrequency, &freq, sizeof(freq),
+NULL);
+if (hr != WHV_E_UNKNOWN_CAPABILITY) {
+if (FAILED(hr)) {
+printf("WHPX: Failed to query tsc frequency, hr=0x%08lx\n", 
hr);
+} else {
+env->tsc_khz = freq / 1000; /* Hz to KHz */
+}
+}
+}
 
+env->apic_bus_freq = HYPERV_APIC_BUS_FREQUENCY;
+hr = whp_dispatch.WHvGetCapability(
+WHvCapabilityCodeInterruptClockFrequency, &freq, sizeof(freq), NULL);
+if (hr != WHV_E_UNKNOWN_CAPABILITY) {
+if (FAILED(hr)) {
+printf("WHPX: Failed to query apic bus frequency hr=0x%08lx\n", 
hr);
+} else {
+env->a

[PULL 10/92] memory: Convert IOMMUMemoryRegionClass doc comment to kernel-doc

[Paolo Bonzini]

From: Eduardo Habkost 

Convert the existing documentation comments of
IOMMUMemoryRegionClass to kernel-doc format so their contents
will appear in the API reference at docs/devel/memory.html.

Signed-off-by: Eduardo Habkost 
Message-Id: <20200908201129.3407568-1-ehabk...@redhat.com>
Reviewed-by: Philippe Mathieu-Daudé 
Signed-off-by: Paolo Bonzini 
---
 include/exec/memory.h | 50 +++
 1 file changed, 41 insertions(+), 9 deletions(-)

diff --git a/include/exec/memory.h b/include/exec/memory.h
index f1bb2a7df5..ec9edee742 100644
--- a/include/exec/memory.h
+++ b/include/exec/memory.h
@@ -228,8 +228,11 @@ enum IOMMUMemoryRegionAttr {
  * attributes and the output TLB entry depends on the transaction
  * attributes, we represent this using IOMMU indexes. Each index
  * selects a particular translation table that the IOMMU has:
+ *
  *   @attrs_to_index returns the IOMMU index for a set of transaction 
attributes
+ *
  *   @translate takes an input address and an IOMMU index
+ *
  * and the mapping returned can only depend on the input address and the
  * IOMMU index.
  *
@@ -238,10 +241,13 @@ enum IOMMUMemoryRegionAttr {
  * for secure transactions and one for non-secure transactions.
  */
 struct IOMMUMemoryRegionClass {
-/* private */
+/* private: */
 MemoryRegionClass parent_class;
 
-/*
+/* public: */
+/**
+ * @translate:
+ *
  * Return a TLB entry that contains a given address.
  *
  * The IOMMUAccessFlags indicated via @flag are optional and may
@@ -262,26 +268,38 @@ struct IOMMUMemoryRegionClass {
  * information when the IOMMU mapping changes.
  *
  * @iommu: the IOMMUMemoryRegion
+ *
  * @hwaddr: address to be translated within the memory region
- * @flag: requested access permissions
+ *
+ * @flag: requested access permission
+ *
  * @iommu_idx: IOMMU index for the translation
  */
 IOMMUTLBEntry (*translate)(IOMMUMemoryRegion *iommu, hwaddr addr,
IOMMUAccessFlags flag, int iommu_idx);
-/* Returns minimum supported page size in bytes.
+/**
+ * @get_min_page_size:
+ *
+ * Returns minimum supported page size in bytes.
+ *
  * If this method is not provided then the minimum is assumed to
  * be TARGET_PAGE_SIZE.
  *
  * @iommu: the IOMMUMemoryRegion
  */
 uint64_t (*get_min_page_size)(IOMMUMemoryRegion *iommu);
-/* Called when IOMMU Notifier flag changes (ie when the set of
+/**
+ * @notify_flag_changed:
+ *
+ * Called when IOMMU Notifier flag changes (ie when the set of
  * events which IOMMU users are requesting notification for changes).
  * Optional method -- need not be provided if the IOMMU does not
  * need to know exactly which events must be notified.
  *
  * @iommu: the IOMMUMemoryRegion
+ *
  * @old_flags: events which previously needed to be notified
+ *
  * @new_flags: events which now need to be notified
  *
  * Returns 0 on success, or a negative errno; in particular
@@ -293,7 +311,10 @@ struct IOMMUMemoryRegionClass {
IOMMUNotifierFlag old_flags,
IOMMUNotifierFlag new_flags,
Error **errp);
-/* Called to handle memory_region_iommu_replay().
+/**
+ * @replay:
+ *
+ * Called to handle memory_region_iommu_replay().
  *
  * The default implementation of memory_region_iommu_replay() is to
  * call the IOMMU translate method for every page in the address space
@@ -310,7 +331,10 @@ struct IOMMUMemoryRegionClass {
  */
 void (*replay)(IOMMUMemoryRegion *iommu, IOMMUNotifier *notifier);
 
-/* Get IOMMU misc attributes. This is an optional method that
+/**
+ * @get_attr:
+ *
+ * Get IOMMU misc attributes. This is an optional method that
  * can be used to allow users of the IOMMU to get implementation-specific
  * information. The IOMMU implements this method to handle calls
  * by IOMMU users to memory_region_iommu_get_attr() by filling in
@@ -319,7 +343,9 @@ struct IOMMUMemoryRegionClass {
  * memory_region_iommu_get_attr() will always return -EINVAL.
  *
  * @iommu: the IOMMUMemoryRegion
+ *
  * @attr: attribute being queried
+ *
  * @data: memory to fill in with the attribute data
  *
  * Returns 0 on success, or a negative errno; in particular
@@ -328,7 +354,10 @@ struct IOMMUMemoryRegionClass {
 int (*get_attr)(IOMMUMemoryRegion *iommu, enum IOMMUMemoryRegionAttr attr,
 void *data);
 
-/* Return the IOMMU index to use for a given set of transaction attributes.
+/**
+ * @attrs_to_index:
+ *
+ * Return the IOMMU index to use for a given set of transaction attributes.
  *
  * Optional method: if an IOMMU only supports a single IOMMU index then
  * the default implement

[PULL 04/92] meson: fix MSI rule

[Paolo Bonzini]

From: Marc-André Lureau 

The environment variables can't be passed through an env: argument
yet (meson#2723), use 'env' as suggested in:
https://github.com/mesonbuild/meson/issues/2723#issuecomment-348630957

Signed-off-by: Marc-André Lureau 
Signed-off-by: Paolo Bonzini 
---
 qga/meson.build | 1 +
 1 file changed, 1 insertion(+)

diff --git a/qga/meson.build b/qga/meson.build
index e5c5778a3e..c10a0526b2 100644
--- a/qga/meson.build
+++ b/qga/meson.build
@@ -70,6 +70,7 @@ if targetos == 'windows'
 output: 
'qemu-ga-@0@.msi'.format(config_host['ARCH']),
 depends: deps,
 command: [
+  find_program('env'),
   'QEMU_GA_VERSION=' + 
config_host['QEMU_GA_VERSION'],
   'QEMU_GA_MANUFACTURER=' + 
config_host['QEMU_GA_MANUFACTURER'],
   'QEMU_GA_DISTRO=' + 
config_host['QEMU_GA_DISTRO'],
-- 
2.26.2

[PULL 00/92] Misc patches for 2020-09-24

[Paolo Bonzini]

The following changes since commit 0fc0142828b5bc965790a1c5c6e241897d3387cb:

  Merge remote-tracking branch 
'remotes/kraxel/tags/input-20200921-pull-request' into staging (2020-09-22 
21:11:10 +0100)

are available in the Git repository at:

  https://gitlab.com/bonzini/qemu.git tags/for-upstream

for you to fetch changes up to f40b138ec74bfdaf50f77e46e4b9c10a38f43db6:

  Merge tag 'pull-cap-20200922' of https://github.com/rth7680/qemu into HEAD 
(2020-09-23 14:39:20 -0400)


* SCSI fix (Dmitry, Li Feng, Li Qiang)
* memory API fixes (Eduardo)
* removal of deprecated '-numa node', 'cpu-add', '-smp' (Igor)
* ACPI fix for VMBus (Jon)
* relocatable install (myself)
* always remove docker containers (myself)
* serial cleanups (Philippe)
* vmware cpuid leaf for tsc and apic frequency (Sunil)
* KVM_FEATURE_ASYNC_PF_INT support (Vitaly)
* i386 XSAVE bugfix (Xiaoyao)
* QOM developer documentation in docs/devel (Eduardo)
* new checkpatch tests (Dov)
* x86_64 syscall fix (Douglas)
* interrupt-based APF fix (Vitaly)
* always create kvmclock (Vitaly)
* fix bios-tables-test (Eduardo)
* KVM PV features cleanup (myself)
* CAN FD (Pavel)

meson:
* fixes (Marc-André, Max, Stefan, Alexander, myself)
* submodule and environment CFLAGS overhaul (myself)
* moved libmpathpersist, cocoa, malloc tests (myself)
* support for 0.56 introspected test dependencies (myself)


Alexander Bulekov (1):
  oss-fuzz: move linker arg to fix coverage-build

Anthony PERARD (1):
  meson: fix installation of keymaps

Claudio Fontana (1):
  tests: add missing genh dependency

Daniel P. Berrangé (1):
  char: fix logging when chardev write fails

Dmitry Fomichev (1):
  scsi-generic: Fix HM-zoned device scan

Douglas Crosher (1):
  helper_syscall x86_64: clear exception_is_int

Dov Murik (1):
  checkpatch: Detect '%#' or '%0#' in printf-style format strings

Eduardo Habkost (10):
  memory: Convert IOMMUMemoryRegionClass doc comment to kernel-doc
  qom: Document all function parameters in doc comments
  qom: Use kernel-doc private/public tags in structs
  qom: Use ``code`` Sphinx syntax where appropriate
  qom: Add kernel-doc markup to introduction doc comment
  qom: Reformat section titles using Sphinx syntax
  qom: Indent existing code examples
  qom: Add code block markup to all code blocks
  docs: Create docs/devel/qom.rst
  bios-tables-test: Remove kernel-irqchip=off option

Igor Mammedov (5):
  numa: drop support for '-numa node' (without memory specified)
  doc: Cleanup "'-mem-path' fallback to RAM" deprecation text
  numa: remove fixup numa_state->num_nodes to MAX_NODES
  smp: drop support for deprecated (invalid topologies)
  cphp: remove deprecated cpu-add command(s)

Jan Charvat (5):
  net/can: Initial host SocketCan support for CAN FD.
  hw/net/can: sja1000 ignore CAN FD frames
  net/can: Add can_dlc2len and can_len2dlc for CAN FD.
  hw/net/can/ctucafd: Add CTU CAN FD core register definitions.
  hw/net/can: CTU CAN FD IP open hardware core emulation.

Jon Doron (1):
  acpi: i386: Move VMBus DSDT entry to SB

Li Feng (1):
  vhost-scsi: support inflight io track

Li Qiang (2):
  hw: megasas: return -1 when 'megasas_map_sgl' fails
  hw: megasas: consider 'iov_count=0' is an error in megasas_map_sgl

Marc-André Lureau (2):
  meson: fix MSI rule
  meson: error out if qemu_suffix starts with /

Paolo Bonzini (34):
  meson: clean up build_by_default
  ninjatool: rebuild multi-output targets if outputs are missing
  meson: move libudev test
  meson: move libmpathpersist test
  meson: extend libmpathpersist test for static linking
  configure: move malloc_trim/tcmalloc/jemalloc to meson
  configure: fix --meson=/path/to/meson
  configure: move cocoa option to Meson
  configure: do not limit Hypervisor.framework test to Darwin
  meson: qtest: set "depends" correctly
  mtest2make: add support for introspected test dependencies
  meson: report accelerator support
  oslib: do not call g_strdup from qemu_get_exec_dir
  fuzz: use qemu_get_exec_dir
  oslib-posix: default exec_dir to bindir
  cutils: introduce get_relocated_path
  oslib-posix: relocate path to /var
  module: relocate path to modules
  net: relocate paths to helpers and scripts
  vl: relocate paths to data directories
  vl: relocate path to configuration file
  qemu-bridge-helper: relocate path to default ACL
  qga: relocate path to default configuration and hook
  ui: relocate paths to icons and translations
  configure: use a platform-neutral prefix
  configure: fix performance regression due to PIC objects
  tests/tcg: reinstate or replace desired parts of rules.mak
  configure: cleanup invocation of submodule Make
  

[PULL 07/92] configure: Do not intent to build WHPX on 32-bit host

[Paolo Bonzini]

From: Philippe Mathieu-Daudé 

Hyper-V is available on 64-bit versions of Windows,
do not try to build its support on 32-bit versions.

Signed-off-by: Philippe Mathieu-Daudé 
Message-Id: <20200910054516.405777-1-f4...@amsat.org>
Reviewed-by: Stefan Weil 
Signed-off-by: Paolo Bonzini 
---
 configure | 5 -
 1 file changed, 4 insertions(+), 1 deletion(-)

diff --git a/configure b/configure
index e8e8e984f2..db9ec3231f 100755
--- a/configure
+++ b/configure
@@ -2985,7 +2985,10 @@ fi
 
 ##
 # Windows Hypervisor Platform accelerator (WHPX) check
-if test "$whpx" != "no" ; then
+if test "$whpx" = "yes" && test "$ARCH" != "x86_64"; then
+  error_exit "WHPX requires 64-bit host"
+fi
+if test "$whpx" != "no" && test "$ARCH" = "x86_64"; then
 if check_include "WinHvPlatform.h" && check_include "WinHvEmulation.h"; 
then
 whpx="yes"
 else
-- 
2.26.2

[PULL 12/92] acpi: i386: Move VMBus DSDT entry to SB

[Paolo Bonzini]

From: Jon Doron 

Signed-off-by: Jon Doron 
Reviewed-by: Igor Mammedov 
Message-Id: <20200715084326.678715-2-ari...@gmail.com>
Signed-off-by: Paolo Bonzini 
---
 hw/i386/acpi-build.c | 12 +++-
 1 file changed, 7 insertions(+), 5 deletions(-)

diff --git a/hw/i386/acpi-build.c b/hw/i386/acpi-build.c
index 0e0535d2e3..60722fb8b0 100644
--- a/hw/i386/acpi-build.c
+++ b/hw/i386/acpi-build.c
@@ -975,7 +975,6 @@ static Aml *build_vmbus_device_aml(VMBusBridge 
*vmbus_bridge)
 
 static void build_isa_devices_aml(Aml *table)
 {
-VMBusBridge *vmbus_bridge = vmbus_bridge_find();
 bool ambiguous;
 Object *obj = object_resolve_path_type("", TYPE_ISA_BUS, &ambiguous);
 Aml *scope;
@@ -986,10 +985,6 @@ static void build_isa_devices_aml(Aml *table)
 build_acpi_ipmi_devices(scope, BUS(obj), "\\_SB.PCI0.ISA");
 isa_build_aml(ISA_BUS(obj), scope);
 
-if (vmbus_bridge) {
-aml_append(scope, build_vmbus_device_aml(vmbus_bridge));
-}
-
 aml_append(table, scope);
 }
 
@@ -1485,6 +1480,7 @@ build_dsdt(GArray *table_data, BIOSLinker *linker,
 PCIBus *bus = NULL;
 TPMIf *tpm = tpm_find();
 int i;
+VMBusBridge *vmbus_bridge = vmbus_bridge_find();
 
 dsdt = init_aml_allocator();
 
@@ -1526,6 +1522,12 @@ build_dsdt(GArray *table_data, BIOSLinker *linker,
 }
 }
 
+if (vmbus_bridge) {
+sb_scope = aml_scope("_SB");
+aml_append(sb_scope, build_vmbus_device_aml(vmbus_bridge));
+aml_append(dsdt, sb_scope);
+}
+
 if (pcmc->legacy_cpu_hotplug) {
 build_legacy_cpu_hotplug_aml(dsdt, machine, pm->cpu_hp_io_base);
 } else {
-- 
2.26.2

[PULL 01/92] tests: add missing genh dependency

[Paolo Bonzini]

From: Claudio Fontana 

Fix high-parallelism builds by forcing all generated headers
to be created before tests are compiled.

Reported-by: Claudio Fontana 
Signed-off-by: Paolo Bonzini 
Tested-by: Claudio Fontana 
Reviewed-by: Philippe Mathieu-Daudé 
---
 tests/meson.build | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/tests/meson.build b/tests/meson.build
index 8c3e930687..70203890a1 100644
--- a/tests/meson.build
+++ b/tests/meson.build
@@ -56,7 +56,7 @@ test_qapi_files = custom_target('Test QAPI files',
 # perhaps change qapi_gen to replace / with _, like Meson itself does?
 subdir('include')
 
-libtestqapi = static_library('testqapi', sources: [test_qapi_files, 
test_qapi_outputs_extra])
+libtestqapi = static_library('testqapi', sources: [test_qapi_files, genh, 
test_qapi_outputs_extra])
 testqapi = declare_dependency(link_with: libtestqapi)
 
 testblock = declare_dependency(dependencies: [block], sources: 'iothread.c')
@@ -229,7 +229,7 @@ foreach test_name, extra: tests
 src += test_ss.all_sources()
 deps += test_ss.all_dependencies()
   endif
-  exe = executable(test_name, src, dependencies: deps)
+  exe = executable(test_name, src, genh, dependencies: deps)
 
   test(test_name, exe,
depends: test_deps.get(test_name, []),
-- 
2.26.2

[PULL 08/92] MAINTAINERS: add Paolo Bonzini as RCU maintainer

[Paolo Bonzini]

From: Stefan Hajnoczi 

The RCU code that Paolo maintains is missing a MAINTAINERS file entry.

Signed-off-by: Stefan Hajnoczi 
Message-Id: <20200909090851.14458-1-stefa...@redhat.com>
Signed-off-by: Paolo Bonzini 
---
 MAINTAINERS | 8 
 1 file changed, 8 insertions(+)

diff --git a/MAINTAINERS b/MAINTAINERS
index 3d17cad19a..9b01385484 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -2310,6 +2310,14 @@ F: softmmu/cpus.c
 F: softmmu/cpu-throttle.c
 F: qapi/run-state.json
 
+Read, Copy, Update (RCU)
+M: Paolo Bonzini 
+S: Maintained
+F: include/qemu/rcu*.h
+F: tests/rcutorture.c
+F: tests/test-rcu-*.c
+F: util/rcu.c
+
 Human Monitor (HMP)
 M: Dr. David Alan Gilbert 
 S: Maintained
-- 
2.26.2

[PULL 14/92] doc: Cleanup "'-mem-path' fallback to RAM" deprecation text

[Paolo Bonzini]

From: Igor Mammedov 

it was actually removed in 5.0,
commit 68a86dc15c (numa: remove deprecated -mem-path fallback to anonymous RAM)
clean up forgotten remnants in docs.

Signed-off-by: Igor Mammedov 
Message-Id: <20200911084410.788171-3-imamm...@redhat.com>
Signed-off-by: Paolo Bonzini 
---
 docs/system/deprecated.rst | 21 ++---
 1 file changed, 10 insertions(+), 11 deletions(-)

diff --git a/docs/system/deprecated.rst b/docs/system/deprecated.rst
index 6422230fe2..e78d03038f 100644
--- a/docs/system/deprecated.rst
+++ b/docs/system/deprecated.rst
@@ -104,17 +104,6 @@ error in the future.
 The ``-realtime mlock=on|off`` argument has been replaced by the
 ``-overcommit mem-lock=on|off`` argument.
 
-``-mem-path`` fallback to RAM (since 4.1)
-'
-
-Currently if guest RAM allocation from file pointed by ``mem-path``
-fails, QEMU falls back to allocating from RAM, which might result
-in unpredictable behavior since the backing file specified by the user
-is ignored. In the future, users will be responsible for making sure
-the backing storage specified with ``-mem-path`` can actually provide
-the guest RAM configured with ``-m`` and QEMU will fail to start up if
-RAM allocation is unsuccessful.
-
 RISC-V ``-bios`` (since 5.1)
 
 
@@ -647,6 +636,16 @@ New machine versions (since 5.1) will not accept the 
option but it will still
 work with old machine types. User can check the QAPI schema to see if the 
legacy
 option is supported by looking at MachineInfo::numa-mem-supported property.
 
+``-mem-path`` fallback to RAM (removed in 5.0)
+''
+
+If guest RAM allocation from file pointed by ``mem-path`` failed,
+QEMU was falling back to allocating from RAM, which might have resulted
+in unpredictable behavior since the backing file specified by the user
+as ignored. Currently, users are responsible for making sure the backing 
storage
+specified with ``-mem-path`` can actually provide the guest RAM configured with
+``-m`` and QEMU fails to start up if RAM allocation is unsuccessful.
+
 Block devices
 -
 
-- 
2.26.2

[PULL 11/92] vhost-scsi: support inflight io track

[Paolo Bonzini]

From: Li Feng 

Qemu will send GET_INFLIGHT_FD and SET_INFLIGH_FD to backend, and
the backend setup the inflight memory to track the io.

Change-Id: I805d6189996f7a1b44c65f0b12ef7473b1789510
Signed-off-by: Li Feng 
Message-Id: <20200909122021.1055174-1-fen...@smartx.com>
Signed-off-by: Paolo Bonzini 
---
 hw/scsi/vhost-scsi-common.c   | 27 +++
 include/hw/virtio/vhost-scsi-common.h |  2 ++
 2 files changed, 29 insertions(+)

diff --git a/hw/scsi/vhost-scsi-common.c b/hw/scsi/vhost-scsi-common.c
index 8ec49d7fef..767f827e55 100644
--- a/hw/scsi/vhost-scsi-common.c
+++ b/hw/scsi/vhost-scsi-common.c
@@ -32,6 +32,8 @@ int vhost_scsi_common_start(VHostSCSICommon *vsc)
 BusState *qbus = BUS(qdev_get_parent_bus(DEVICE(vdev)));
 VirtioBusClass *k = VIRTIO_BUS_GET_CLASS(qbus);
 
+VirtIOSCSICommon *vs = (VirtIOSCSICommon *)vsc;
+
 if (!k->set_guest_notifiers) {
 error_report("binding does not support guest notifiers");
 return -ENOSYS;
@@ -49,6 +51,23 @@ int vhost_scsi_common_start(VHostSCSICommon *vsc)
 }
 
 vsc->dev.acked_features = vdev->guest_features;
+
+assert(vsc->inflight == NULL);
+vsc->inflight = g_new0(struct vhost_inflight, 1);
+ret = vhost_dev_get_inflight(&vsc->dev,
+ vs->conf.virtqueue_size,
+ vsc->inflight);
+if (ret < 0) {
+error_report("Error get inflight: %d", -ret);
+goto err_guest_notifiers;
+}
+
+ret = vhost_dev_set_inflight(&vsc->dev, vsc->inflight);
+if (ret < 0) {
+error_report("Error set inflight: %d", -ret);
+goto err_guest_notifiers;
+}
+
 ret = vhost_dev_start(&vsc->dev, vdev);
 if (ret < 0) {
 error_report("Error start vhost dev");
@@ -66,6 +85,9 @@ int vhost_scsi_common_start(VHostSCSICommon *vsc)
 return ret;
 
 err_guest_notifiers:
+g_free(vsc->inflight);
+vsc->inflight = NULL;
+
 k->set_guest_notifiers(qbus->parent, vsc->dev.nvqs, false);
 err_host_notifiers:
 vhost_dev_disable_notifiers(&vsc->dev, vdev);
@@ -89,6 +111,11 @@ void vhost_scsi_common_stop(VHostSCSICommon *vsc)
 }
 assert(ret >= 0);
 
+if (vsc->inflight) {
+vhost_dev_free_inflight(vsc->inflight);
+vsc->inflight = NULL;
+}
+
 vhost_dev_disable_notifiers(&vsc->dev, vdev);
 }
 
diff --git a/include/hw/virtio/vhost-scsi-common.h 
b/include/hw/virtio/vhost-scsi-common.h
index 0c8909d12a..18f115527c 100644
--- a/include/hw/virtio/vhost-scsi-common.h
+++ b/include/hw/virtio/vhost-scsi-common.h
@@ -35,6 +35,8 @@ struct VHostSCSICommon {
 int lun;
 uint64_t host_features;
 bool migratable;
+
+struct vhost_inflight *inflight;
 };
 
 int vhost_scsi_common_start(VHostSCSICommon *vsc);
-- 
2.26.2

[PULL 15/92] numa: remove fixup numa_state->num_nodes to MAX_NODES

[Paolo Bonzini]

From: Igor Mammedov 

current code permits only nodeids in [0..MAX_NODES) range
due to nodeid check in

  parse_numa_node()
  if (nodenr >= MAX_NODES) {
  error_setg(errp, "Max number of NUMA nodes reached: %"

so subj fixup is not reachable, drop it.

Signed-off-by: Igor Mammedov 
Message-Id: <20200911084410.788171-4-imamm...@redhat.com>
Signed-off-by: Paolo Bonzini 
---
 hw/core/numa.c | 4 
 1 file changed, 4 deletions(-)

diff --git a/hw/core/numa.c b/hw/core/numa.c
index 706c1e84c6..7d5d413001 100644
--- a/hw/core/numa.c
+++ b/hw/core/numa.c
@@ -677,10 +677,6 @@ void numa_complete_configuration(MachineState *ms)
 if (ms->numa_state->num_nodes > 0) {
 uint64_t numa_total;
 
-if (ms->numa_state->num_nodes > MAX_NODES) {
-ms->numa_state->num_nodes = MAX_NODES;
-}
-
 numa_total = 0;
 for (i = 0; i < ms->numa_state->num_nodes; i++) {
 numa_total += numa_info[i].node_mem;
-- 
2.26.2

[PULL 17/92] hw/char/serial: Remove TYPE_SERIAL_IO

[Paolo Bonzini]

From: Philippe Mathieu-Daudé 

TYPE_SERIAL_IO is a subset of TYPE_SERIAL_MM, and it is
not used anymore. Remove it.

Suggested-by: Paolo Bonzini 
Suggested-by: Peter Maydell 
Signed-off-by: Philippe Mathieu-Daudé 
Reviewed-by: Richard Henderson 
Message-Id: <20200907011538.818996-3-phi...@redhat.com>
Signed-off-by: Paolo Bonzini 
---
 hw/char/serial.c | 41 
 include/hw/char/serial.h |  9 -
 2 files changed, 50 deletions(-)

diff --git a/hw/char/serial.c b/hw/char/serial.c
index 2386479492..fd80ae5592 100644
--- a/hw/char/serial.c
+++ b/hw/char/serial.c
@@ -985,46 +985,6 @@ const MemoryRegionOps serial_io_ops = {
 .endianness = DEVICE_LITTLE_ENDIAN,
 };
 
-static void serial_io_realize(DeviceState *dev, Error **errp)
-{
-SerialIO *sio = SERIAL_IO(dev);
-SerialState *s = &sio->serial;
-
-if (!qdev_realize(DEVICE(s), NULL, errp)) {
-return;
-}
-
-memory_region_init_io(&s->io, OBJECT(dev), &serial_io_ops, s, "serial", 8);
-sysbus_init_mmio(SYS_BUS_DEVICE(sio), &s->io);
-sysbus_init_irq(SYS_BUS_DEVICE(sio), &s->irq);
-}
-
-static void serial_io_class_init(ObjectClass *klass, void* data)
-{
-DeviceClass *dc = DEVICE_CLASS(klass);
-
-dc->realize = serial_io_realize;
-/* No dc->vmsd: class has no migratable state */
-}
-
-static void serial_io_instance_init(Object *o)
-{
-SerialIO *sio = SERIAL_IO(o);
-
-object_initialize_child(o, "serial", &sio->serial, TYPE_SERIAL);
-
-qdev_alias_all_properties(DEVICE(&sio->serial), o);
-}
-
-
-static const TypeInfo serial_io_info = {
-.name = TYPE_SERIAL_IO,
-.parent = TYPE_SYS_BUS_DEVICE,
-.instance_size = sizeof(SerialIO),
-.instance_init = serial_io_instance_init,
-.class_init = serial_io_class_init,
-};
-
 static Property serial_properties[] = {
 DEFINE_PROP_CHR("chardev", SerialState, chr),
 DEFINE_PROP_UINT32("baudbase", SerialState, baudbase, 115200),
@@ -1178,7 +1138,6 @@ static const TypeInfo serial_mm_info = {
 static void serial_register_types(void)
 {
 type_register_static(&serial_info);
-type_register_static(&serial_io_info);
 type_register_static(&serial_mm_info);
 }
 
diff --git a/include/hw/char/serial.h b/include/hw/char/serial.h
index db4f9af18c..23bd7d3dde 100644
--- a/include/hw/char/serial.h
+++ b/include/hw/char/serial.h
@@ -90,12 +90,6 @@ struct SerialMM {
 uint8_t endianness;
 };
 
-struct SerialIO {
-SysBusDevice parent;
-
-SerialState serial;
-};
-
 extern const VMStateDescription vmstate_serial;
 extern const MemoryRegionOps serial_io_ops;
 
@@ -107,9 +101,6 @@ OBJECT_DECLARE_SIMPLE_TYPE(SerialState, SERIAL)
 #define TYPE_SERIAL_MM "serial-mm"
 OBJECT_DECLARE_SIMPLE_TYPE(SerialMM, SERIAL_MM)
 
-#define TYPE_SERIAL_IO "serial-io"
-OBJECT_DECLARE_SIMPLE_TYPE(SerialIO, SERIAL_IO)
-
 SerialMM *serial_mm_init(MemoryRegion *address_space,
  hwaddr base, int regshift,
  qemu_irq irq, int baudbase,
-- 
2.26.2

[PULL 23/92] hw/char/serial: Make 'wakeup' property boolean

[Paolo Bonzini]

From: Philippe Mathieu-Daudé 

Make the "wakeup" property introduced in commit 9826fd597df
("suspend: make serial ports wakeup the guest") a boolean.

As we want to reuse the generic serial properties in the
ISA model (next commit), expose this property.

Signed-off-by: Philippe Mathieu-Daudé 
Reviewed-by: Richard Henderson 
Message-Id: <20200907015535.827885-6-f4...@amsat.org>
Signed-off-by: Paolo Bonzini 
---
 hw/char/serial-isa.c | 2 +-
 hw/char/serial.c | 1 +
 include/hw/char/serial.h | 2 +-
 3 files changed, 3 insertions(+), 2 deletions(-)

diff --git a/hw/char/serial-isa.c b/hw/char/serial-isa.c
index 32c2fc0ebe..fc8ff7823a 100644
--- a/hw/char/serial-isa.c
+++ b/hw/char/serial-isa.c
@@ -117,7 +117,7 @@ static Property serial_isa_properties[] = {
 DEFINE_PROP_UINT32("iobase",  ISASerialState, iobase,  -1),
 DEFINE_PROP_UINT32("irq",ISASerialState, isairq,  -1),
 DEFINE_PROP_CHR("chardev",   ISASerialState, state.chr),
-DEFINE_PROP_UINT32("wakeup", ISASerialState, state.wakeup, 0),
+DEFINE_PROP_BOOL("wakeup",   ISASerialState, state.wakeup, false),
 DEFINE_PROP_END_OF_LIST(),
 };
 
diff --git a/hw/char/serial.c b/hw/char/serial.c
index 7b5ef872bd..4386adabd4 100644
--- a/hw/char/serial.c
+++ b/hw/char/serial.c
@@ -975,6 +975,7 @@ const MemoryRegionOps serial_io_ops = {
 static Property serial_properties[] = {
 DEFINE_PROP_CHR("chardev", SerialState, chr),
 DEFINE_PROP_UINT32("baudbase", SerialState, baudbase, 115200),
+DEFINE_PROP_BOOL("wakeup", SerialState, wakeup, false),
 DEFINE_PROP_END_OF_LIST(),
 };
 
diff --git a/include/hw/char/serial.h b/include/hw/char/serial.h
index 23bd7d3dde..8ba7eca3d6 100644
--- a/include/hw/char/serial.h
+++ b/include/hw/char/serial.h
@@ -61,7 +61,7 @@ struct SerialState {
 uint32_t baudbase;
 uint32_t tsr_retry;
 guint watch_tag;
-uint32_t wakeup;
+bool wakeup;
 
 /* Time when the last byte was successfully sent out of the tsr */
 uint64_t last_xmit_ts;
-- 
2.26.2

[PULL 16/92] hw/mips/mipssim: Use MMIO serial device on fake ISA I/O

[Paolo Bonzini]

From: Philippe Mathieu-Daudé 

The 'mipssim' is not a real hardware, it is a simulator.

There is an ISA MMIO space mapped at 0x1fd0, however
this is not a real ISA bus (no ISA IRQ). So can not use
the TYPE_ISA_SERIAL device...
Instead we have been using a plain MMIO device, but named
it IO.

TYPE_SERIAL_IO is a subset of TYPE_SERIAL_MM, using
regshift=0 and endianness=DEVICE_LITTLE_ENDIAN.

Directly use the TYPE_SERIAL_MM device, enforcing the
regshift/endianness values. 'regshift' default is already
'0'. 'endianness' is meaningless for 8-bit accesses.

This change breaks migration back compatibility, but
this is not an issue for the mipssim machine.

Suggested-by: Peter Maydell 
Signed-off-by: Philippe Mathieu-Daudé 
Reviewed-by: Richard Henderson 
Message-Id: <20200907011538.818996-2-phi...@redhat.com>
Signed-off-by: Paolo Bonzini 
---
 hw/mips/mipssim.c | 5 +++--
 1 file changed, 3 insertions(+), 2 deletions(-)

diff --git a/hw/mips/mipssim.c b/hw/mips/mipssim.c
index 1b3b762203..5d4ad74828 100644
--- a/hw/mips/mipssim.c
+++ b/hw/mips/mipssim.c
@@ -216,10 +216,11 @@ mips_mipssim_init(MachineState *machine)
  * MIPS CPU INT2, which is interrupt 4.
  */
 if (serial_hd(0)) {
-DeviceState *dev = qdev_new(TYPE_SERIAL_IO);
+DeviceState *dev = qdev_new(TYPE_SERIAL_MM);
 
 qdev_prop_set_chr(dev, "chardev", serial_hd(0));
-qdev_set_legacy_instance_id(dev, 0x3f8, 2);
+qdev_prop_set_uint8(dev, "regshift", 0);
+qdev_prop_set_uint8(dev, "endianness", DEVICE_LITTLE_ENDIAN);
 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
 sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0, env->irq[4]);
 sysbus_add_io(SYS_BUS_DEVICE(dev), 0x3f8,
-- 
2.26.2

[PULL 13/92] numa: drop support for '-numa node' (without memory specified)

[Paolo Bonzini]

From: Igor Mammedov 

it was deprecated since 4.1
commit 4bb4a2732e (numa: deprecate implict memory distribution between nodes)

Users of existing VMs, wishing to preserve the same RAM distribution,
should configure it explicitly using ``-numa node,memdev`` options.
Current RAM distribution can be retrieved using HMP command
`info numa` and if separate memory devices (pc|nv-dimm) are present
use `info memory-device` and subtract device memory from output of
`info numa`.

Signed-off-by: Igor Mammedov 
Message-Id: <20200911084410.788171-2-imamm...@redhat.com>
Signed-off-by: Paolo Bonzini 
---
 docs/system/deprecated.rst | 23 +---
 hw/core/machine.c  |  1 -
 hw/core/numa.c | 55 --
 hw/i386/pc_piix.c  |  1 -
 hw/i386/pc_q35.c   |  1 -
 hw/ppc/spapr.c |  1 -
 include/hw/boards.h|  2 --
 include/sysemu/numa.h  |  4 ---
 8 files changed, 14 insertions(+), 74 deletions(-)

diff --git a/docs/system/deprecated.rst b/docs/system/deprecated.rst
index 808c334fe7..6422230fe2 100644
--- a/docs/system/deprecated.rst
+++ b/docs/system/deprecated.rst
@@ -104,15 +104,6 @@ error in the future.
 The ``-realtime mlock=on|off`` argument has been replaced by the
 ``-overcommit mem-lock=on|off`` argument.
 
-``-numa`` node (without memory specified) (since 4.1)
-'
-
-Splitting RAM by default between NUMA nodes has the same issues as ``mem``
-parameter described above with the difference that the role of the user plays
-QEMU using implicit generic or board specific splitting rule.
-Use ``memdev`` with *memory-backend-ram* backend or ``mem`` (if
-it's supported by used machine type) to define mapping explicitly instead.
-
 ``-mem-path`` fallback to RAM (since 4.1)
 '
 
@@ -625,6 +616,20 @@ error when ``-u`` is not used.
 Command line options
 
 
+``-numa`` node (without memory specified) (removed 5.2)
+'''
+
+Splitting RAM by default between NUMA nodes had the same issues as ``mem``
+parameter with the difference that the role of the user plays QEMU using
+implicit generic or board specific splitting rule.
+Use ``memdev`` with *memory-backend-ram* backend or ``mem`` (if
+it's supported by used machine type) to define mapping explictly instead.
+Users of existing VMs, wishing to preserve the same RAM distribution, should
+configure it explicitly using ``-numa node,memdev`` options. Current RAM
+distribution can be retrieved using HMP command ``info numa`` and if separate
+memory devices (pc|nv-dimm) are present use ``info memory-device`` and subtract
+device memory from output of ``info numa``.
+
 ``-numa node,mem=``\ *size* (removed in 5.1)
 
 
diff --git a/hw/core/machine.c b/hw/core/machine.c
index ea26d61237..f70d388e86 100644
--- a/hw/core/machine.c
+++ b/hw/core/machine.c
@@ -797,7 +797,6 @@ static void machine_class_init(ObjectClass *oc, void *data)
  * On Linux, each node's border has to be 8MB aligned
  */
 mc->numa_mem_align_shift = 23;
-mc->numa_auto_assign_ram = numa_default_auto_assign_ram;
 
 object_class_property_add_str(oc, "kernel",
 machine_get_kernel, machine_set_kernel);
diff --git a/hw/core/numa.c b/hw/core/numa.c
index f9593ec716..706c1e84c6 100644
--- a/hw/core/numa.c
+++ b/hw/core/numa.c
@@ -611,42 +611,6 @@ static void complete_init_numa_distance(MachineState *ms)
 }
 }
 
-void numa_legacy_auto_assign_ram(MachineClass *mc, NodeInfo *nodes,
- int nb_nodes, ram_addr_t size)
-{
-int i;
-uint64_t usedmem = 0;
-
-/* Align each node according to the alignment
- * requirements of the machine class
- */
-
-for (i = 0; i < nb_nodes - 1; i++) {
-nodes[i].node_mem = (size / nb_nodes) &
-~((1 << mc->numa_mem_align_shift) - 1);
-usedmem += nodes[i].node_mem;
-}
-nodes[i].node_mem = size - usedmem;
-}
-
-void numa_default_auto_assign_ram(MachineClass *mc, NodeInfo *nodes,
-  int nb_nodes, ram_addr_t size)
-{
-int i;
-uint64_t usedmem = 0, node_mem;
-uint64_t granularity = size / nb_nodes;
-uint64_t propagate = 0;
-
-for (i = 0; i < nb_nodes - 1; i++) {
-node_mem = (granularity + propagate) &
-   ~((1 << mc->numa_mem_align_shift) - 1);
-propagate = granularity + propagate - node_mem;
-nodes[i].node_mem = node_mem;
-usedmem += node_mem;
-}
-nodes[i].node_mem = size - usedmem;
-}
-
 static void numa_init_memdev_container(MachineState *ms, MemoryRegion *ram)
 {
 int i;
@@ -717,25 +681,6 @@ void numa_complete_configuration(MachineState *ms)
 ms->numa_state->num_nodes = MAX_NODES;
 }
 
-/* If no memory size is given for any node, assume the def

[PULL 20/92] hw/char/serial: Replace commented DPRINTF() by trace event

[Paolo Bonzini]

From: Philippe Mathieu-Daudé 

Convert the old debug PRINTF() call to display the UART
baudrate to a trace event.

Reviewed-by: Richard Henderson 
Signed-off-by: Philippe Mathieu-Daudé 
Message-Id: <20200907015535.827885-3-f4...@amsat.org>
Signed-off-by: Paolo Bonzini 
---
 hw/char/serial.c | 4 +---
 hw/char/trace-events | 1 +
 2 files changed, 2 insertions(+), 3 deletions(-)

diff --git a/hw/char/serial.c b/hw/char/serial.c
index 840da89de7..e8029f840a 100644
--- a/hw/char/serial.c
+++ b/hw/char/serial.c
@@ -187,9 +187,7 @@ static void serial_update_parameters(SerialState *s)
 ssp.stop_bits = stop_bits;
 s->char_transmit_time =  (NANOSECONDS_PER_SECOND / speed) * frame_size;
 qemu_chr_fe_ioctl(&s->chr, CHR_IOCTL_SERIAL_SET_PARAMS, &ssp);
-
-DPRINTF("speed=%.2f parity=%c data=%d stop=%d\n",
-   speed, parity, data_bits, stop_bits);
+trace_serial_update_parameters(speed, parity, data_bits, stop_bits);
 }
 
 static void serial_update_msl(SerialState *s)
diff --git a/hw/char/trace-events b/hw/char/trace-events
index 2442a9f7d5..17304bef26 100644
--- a/hw/char/trace-events
+++ b/hw/char/trace-events
@@ -7,6 +7,7 @@ parallel_ioport_write(const char *desc, uint16_t addr, uint8_t 
value) "write [%s
 # serial.c
 serial_ioport_read(uint16_t addr, uint8_t value) "read addr 0x%02x val 0x%02x"
 serial_ioport_write(uint16_t addr, uint8_t value) "write addr 0x%02x val 
0x%02x"
+serial_update_parameters(uint64_t baudrate, char parity, int data_bits, int 
stop_bits) "baudrate=%"PRIu64" parity='%c' data=%d stop=%d"
 
 # virtio-serial-bus.c
 virtio_serial_send_control_event(unsigned int port, uint16_t event, uint16_t 
value) "port %u, event %u, value %u"
-- 
2.26.2

[PULL 18/92] configure: rename QEMU_GA_MSI_ENABLED to CONFIG_QGA_MSI

[Paolo Bonzini]

From: Stefan Hajnoczi 

The QEMU_GA_MSI_ENABLED config-host.mak variable is emitted by
./configure. meson.build actually checks for CONFIG_QGA_MSI_ENABLED:

  summary_info += {'QGA MSI support':   
config_host.has_key('CONFIG_QGA_MSI_ENABLED')}

Rename QEMU_GA_MSI_ENABLED to CONFIG_QGA_MSI for consistency with
CONFIG_QGA_VSS. Also use 'y' instead of 'yes' for consistency.

This fixes the feature summary printed by meson.build.

Signed-off-by: Stefan Hajnoczi 
Message-Id: <20200914095231.621068-4-stefa...@redhat.com>
Signed-off-by: Paolo Bonzini 
---
 Makefile| 2 +-
 configure   | 2 +-
 meson.build | 2 +-
 3 files changed, 3 insertions(+), 3 deletions(-)

diff --git a/Makefile b/Makefile
index 7c60b9dcb8..42d90cb597 100644
--- a/Makefile
+++ b/Makefile
@@ -285,7 +285,7 @@ endif
 ifdef CONFIG_WIN32
@echo  'Windows targets:'
$(call print-help,installer,Build NSIS-based installer for QEMU)
-ifdef QEMU_GA_MSI_ENABLED
+ifdef CONFIG_QGA_MSI
$(call print-help,msi,Build MSI-based installer for qemu-ga)
 endif
@echo  ''
diff --git a/configure b/configure
index db9ec3231f..01fce2e94b 100755
--- a/configure
+++ b/configure
@@ -6576,7 +6576,7 @@ if test "$mingw32" = "yes" ; then
 echo "CONFIG_QGA_NTDDSCSI=y" >> $config_host_mak
   fi
   if test "$guest_agent_msi" = "yes"; then
-echo "QEMU_GA_MSI_ENABLED=yes" >> $config_host_mak
+echo "CONFIG_QGA_MSI=y" >> $config_host_mak
 echo "QEMU_GA_MSI_MINGW_DLL_PATH=${QEMU_GA_MSI_MINGW_DLL_PATH}" >> 
$config_host_mak
 echo "QEMU_GA_MSI_WITH_VSS=${QEMU_GA_MSI_WITH_VSS}" >> $config_host_mak
 echo "QEMU_GA_MSI_ARCH=${QEMU_GA_MSI_ARCH}" >> $config_host_mak
diff --git a/meson.build b/meson.build
index bb4259e7f0..c48ca0d12a 100644
--- a/meson.build
+++ b/meson.build
@@ -1482,7 +1482,7 @@ if targetos == 'windows'
   endif
   summary_info += {'QGA VSS support':   config_host.has_key('CONFIG_QGA_VSS')}
   summary_info += {'QGA w32 disk info': 
config_host.has_key('CONFIG_QGA_NTDDSCSI')}
-  summary_info += {'QGA MSI support':   
config_host.has_key('CONFIG_QGA_MSI_ENABLED')}
+  summary_info += {'QGA MSI support':   config_host.has_key('CONFIG_QGA_MSI')}
 endif
 summary_info += {'seccomp support':   config_host.has_key('CONFIG_SECCOMP')}
 summary_info += {'coroutine backend': config_host['CONFIG_COROUTINE_BACKEND']}
-- 
2.26.2

[PULL 22/92] hw/char/serial: Rename I/O read/write trace events

[Paolo Bonzini]

From: Philippe Mathieu-Daudé 

The serial_mm_read/write() handlers from the TYPE_SERIAL_MM device
call the serial_ioport_read/write() handlers with shifted offset.

When looking at the trace events from this MMIO device, it is
confusing to read the accesses as I/O. Simplify using generic
trace event names which make sense the various uses.

Signed-off-by: Philippe Mathieu-Daudé 
Reviewed-by: Richard Henderson 
Message-Id: <20200907015535.827885-5-f4...@amsat.org>
Signed-off-by: Paolo Bonzini 
---
 hw/char/serial.c | 4 ++--
 hw/char/trace-events | 4 ++--
 2 files changed, 4 insertions(+), 4 deletions(-)

diff --git a/hw/char/serial.c b/hw/char/serial.c
index 26f7fa8a21..7b5ef872bd 100644
--- a/hw/char/serial.c
+++ b/hw/char/serial.c
@@ -333,7 +333,7 @@ static void serial_ioport_write(void *opaque, hwaddr addr, 
uint64_t val,
 SerialState *s = opaque;
 
 assert(size == 1 && addr < 8);
-trace_serial_ioport_write(addr, val);
+trace_serial_write(addr, val);
 switch(addr) {
 default:
 case 0:
@@ -550,7 +550,7 @@ static uint64_t serial_ioport_read(void *opaque, hwaddr 
addr, unsigned size)
 ret = s->scr;
 break;
 }
-trace_serial_ioport_read(addr, ret);
+trace_serial_read(addr, ret);
 return ret;
 }
 
diff --git a/hw/char/trace-events b/hw/char/trace-events
index 17304bef26..609df10fed 100644
--- a/hw/char/trace-events
+++ b/hw/char/trace-events
@@ -5,8 +5,8 @@ parallel_ioport_read(const char *desc, uint16_t addr, uint8_t 
value) "read [%s]
 parallel_ioport_write(const char *desc, uint16_t addr, uint8_t value) "write 
[%s] addr 0x%02x val 0x%02x"
 
 # serial.c
-serial_ioport_read(uint16_t addr, uint8_t value) "read addr 0x%02x val 0x%02x"
-serial_ioport_write(uint16_t addr, uint8_t value) "write addr 0x%02x val 
0x%02x"
+serial_read(uint16_t addr, uint8_t value) "read addr 0x%02x val 0x%02x"
+serial_write(uint16_t addr, uint8_t value) "write addr 0x%02x val 0x%02x"
 serial_update_parameters(uint64_t baudrate, char parity, int data_bits, int 
stop_bits) "baudrate=%"PRIu64" parity='%c' data=%d stop=%d"
 
 # virtio-serial-bus.c
-- 
2.26.2

[PULL 21/92] hw/char/serial: Remove old DEBUG_SERIAL commented code

[Paolo Bonzini]

From: Philippe Mathieu-Daudé 

All useful DPRINTF() calls have been converted to trace
events.  Remove a pointless one in the IOEventHandler,
and drop the DEBUG_SERIAL ifdef'ry.

Reviewed-by: Richard Henderson 
Signed-off-by: Philippe Mathieu-Daudé 
Message-Id: <20200907015535.827885-4-f4...@amsat.org>
Signed-off-by: Paolo Bonzini 
---
 hw/char/serial.c | 11 ---
 1 file changed, 11 deletions(-)

diff --git a/hw/char/serial.c b/hw/char/serial.c
index e8029f840a..26f7fa8a21 100644
--- a/hw/char/serial.c
+++ b/hw/char/serial.c
@@ -36,8 +36,6 @@
 #include "trace.h"
 #include "hw/qdev-properties.h"
 
-//#define DEBUG_SERIAL
-
 #define UART_LCR_DLAB  0x80/* Divisor latch access bit */
 
 #define UART_IER_MSI   0x08/* Enable Modem status interrupt */
@@ -102,14 +100,6 @@
 
 #define MAX_XMIT_RETRY  4
 
-#ifdef DEBUG_SERIAL
-#define DPRINTF(fmt, ...) \
-do { fprintf(stderr, "serial: " fmt , ## __VA_ARGS__); } while (0)
-#else
-#define DPRINTF(fmt, ...) \
-do {} while (0)
-#endif
-
 static void serial_receive1(void *opaque, const uint8_t *buf, int size);
 static void serial_xmit(SerialState *s);
 
@@ -636,7 +626,6 @@ static void serial_receive1(void *opaque, const uint8_t 
*buf, int size)
 static void serial_event(void *opaque, QEMUChrEvent event)
 {
 SerialState *s = opaque;
-DPRINTF("event %x\n", event);
 if (event == CHR_EVENT_BREAK)
 serial_receive_break(s);
 }
-- 
2.26.2

[PULL 25/92] scsi-generic: Fix HM-zoned device scan

[Paolo Bonzini]

From: Dmitry Fomichev 

Several important steps during device scan depend on SCSI type of the
device. For example, max_transfer property is only determined and
assigned if the device has the type of TYPE_DISK.

Host-managed ZBC disks retain most of the properties of regular SCSI
drives, but they have their own SCSI device type, 0x14. This prevents
the proper assignment of max_transfer property for HM-zoned devices in
scsi-generic driver leading to I/O errors if the maximum i/o size
calculated at the guest exceeds the host value.

To fix this, define TYPE_ZBC to have the standard value from SCSI ZBC
standard spec. Several scan steps that were previously done only for
TYPE_DISK devices, are now performed for the SCSI devices having
TYPE_ZBC too.

Reported-by: Johannes Thumshirn 
Signed-off-by: Dmitry Fomichev 
Message-Id: <20200811225122.17342-3-dmitry.fomic...@wdc.com>
Signed-off-by: Paolo Bonzini 
---
 hw/scsi/scsi-generic.c   | 10 ++
 include/scsi/constants.h |  1 +
 2 files changed, 7 insertions(+), 4 deletions(-)

diff --git a/hw/scsi/scsi-generic.c b/hw/scsi/scsi-generic.c
index 86ed0a3822..2cb23ca891 100644
--- a/hw/scsi/scsi-generic.c
+++ b/hw/scsi/scsi-generic.c
@@ -162,7 +162,8 @@ static void scsi_handle_inquiry_reply(SCSIGenericReq *r, 
SCSIDevice *s)
 }
 }
 
-if (s->type == TYPE_DISK && (r->req.cmd.buf[1] & 0x01)) {
+if ((s->type == TYPE_DISK || s->type == TYPE_ZBC) &&
+(r->req.cmd.buf[1] & 0x01)) {
 page = r->req.cmd.buf[2];
 if (page == 0xb0) {
 uint32_t max_transfer =
@@ -299,10 +300,11 @@ static void scsi_read_complete(void * opaque, int ret)
 }
 blk_set_guest_block_size(s->conf.blk, s->blocksize);
 
-/* Patch MODE SENSE device specific parameters if the BDS is opened
+/*
+ * Patch MODE SENSE device specific parameters if the BDS is opened
  * readonly.
  */
-if ((s->type == TYPE_DISK || s->type == TYPE_TAPE) &&
+if ((s->type == TYPE_DISK || s->type == TYPE_TAPE || s->type == TYPE_ZBC) 
&&
 blk_is_read_only(s->conf.blk) &&
 (r->req.cmd.buf[0] == MODE_SENSE ||
  r->req.cmd.buf[0] == MODE_SENSE_10) &&
@@ -617,7 +619,7 @@ static void 
scsi_generic_read_device_identification(SCSIDevice *s)
 void scsi_generic_read_device_inquiry(SCSIDevice *s)
 {
 scsi_generic_read_device_identification(s);
-if (s->type == TYPE_DISK) {
+if (s->type == TYPE_DISK || s->type == TYPE_ZBC) {
 scsi_generic_set_vpd_bl_emulation(s);
 } else {
 s->needs_vpd_bl_emulation = false;
diff --git a/include/scsi/constants.h b/include/scsi/constants.h
index 874176019e..2a32c08b5e 100644
--- a/include/scsi/constants.h
+++ b/include/scsi/constants.h
@@ -218,6 +218,7 @@
 #define TYPE_ENCLOSURE  0x0d/* Enclosure Services Device */
 #define TYPE_RBC0x0e/* Simplified Direct-Access Device */
 #define TYPE_OSD0x11/* Object-storage Device */
+#define TYPE_ZBC0x14/* Host-managed Zoned SCSI Device */
 #define TYPE_WLUN   0x1e/* Well known LUN */
 #define TYPE_NOT_PRESENT0x1f
 #define TYPE_INACTIVE   0x20
-- 
2.26.2

[PULL 19/92] hw/char/serial: Assert serial_ioport_read/write offset fits 8 bytes

[Paolo Bonzini]

From: Philippe Mathieu-Daudé 

The serial device has 8 registers, each 8-bit. The MemoryRegionOps
'serial_io_ops' is initialized with max_access_size=1, and all
memory_region_init_io() callers correctly set the region size to
8 bytes:
- serial_io_realize
- serial_isa_realizefn
- serial_pci_realize
- multi_serial_pci_realize

It is safe to assert the offset argument of serial_ioport_read()
and serial_ioport_write() is always less than 8.

Signed-off-by: Philippe Mathieu-Daudé 
Reviewed-by: Richard Henderson 
Message-Id: <20200907015535.827885-2-f4...@amsat.org>
Signed-off-by: Paolo Bonzini 
---
 hw/char/serial.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/hw/char/serial.c b/hw/char/serial.c
index fd80ae5592..840da89de7 100644
--- a/hw/char/serial.c
+++ b/hw/char/serial.c
@@ -344,7 +344,7 @@ static void serial_ioport_write(void *opaque, hwaddr addr, 
uint64_t val,
 {
 SerialState *s = opaque;
 
-addr &= 7;
+assert(size == 1 && addr < 8);
 trace_serial_ioport_write(addr, val);
 switch(addr) {
 default:
@@ -485,7 +485,7 @@ static uint64_t serial_ioport_read(void *opaque, hwaddr 
addr, unsigned size)
 SerialState *s = opaque;
 uint32_t ret;
 
-addr &= 7;
+assert(size == 1 && addr < 8);
 switch(addr) {
 default:
 case 0:
-- 
2.26.2

[PULL 34/92] configure: move cocoa option to Meson

[Paolo Bonzini]

While detection of the framework was already there, moving
the option allows for better error reporting.

Reported-by: Christophe de Dinechin 
Reviewed-by: Richard Henderson 
Signed-off-by: Paolo Bonzini 
---
 configure | 17 +++--
 meson.build   |  9 +++--
 meson_options.txt |  2 ++
 ui/meson.build|  2 +-
 4 files changed, 17 insertions(+), 13 deletions(-)

diff --git a/configure b/configure
index 50ddfdeb20..f3a2f43250 100755
--- a/configure
+++ b/configure
@@ -457,7 +457,7 @@ bsd="no"
 linux="no"
 solaris="no"
 profiler="no"
-cocoa="no"
+cocoa="auto"
 softmmu="yes"
 linux_user="no"
 bsd_user="no"
@@ -875,7 +875,7 @@ Darwin)
 QEMU_CFLAGS="-arch x86_64 $QEMU_CFLAGS"
 QEMU_LDFLAGS="-arch x86_64 $QEMU_LDFLAGS"
   fi
-  cocoa="yes"
+  cocoa="enabled"
   audio_drv_list="coreaudio try-sdl"
   audio_possible_drivers="coreaudio sdl"
   QEMU_LDFLAGS="-framework CoreFoundation -framework IOKit $QEMU_LDFLAGS"
@@ -1246,10 +1246,10 @@ for opt do
   ;;
   --enable-profiler) profiler="yes"
   ;;
-  --disable-cocoa) cocoa="no"
+  --disable-cocoa) cocoa="disabled"
   ;;
   --enable-cocoa)
-  cocoa="yes" ;
+  cocoa="enabled" ;
   audio_drv_list="coreaudio $(echo $audio_drv_list | sed s,coreaudio,,g)"
   ;;
   --disable-system) softmmu="no"
@@ -2391,8 +2391,8 @@ fi
 # cocoa implies not SDL or GTK
 # (the cocoa UI code currently assumes it is always the active UI
 # and doesn't interact well with other UI frontend code)
-if test "$cocoa" = "yes"; then
-if test "$sdl" = "yes"; then
+if test "$cocoa" = "enabled"; then
+if test "$sdl" = "enabled"; then
 error_exit "Cocoa and SDL UIs cannot both be enabled at once"
 fi
 if test "$gtk" = "yes"; then
@@ -6556,9 +6556,6 @@ if test "$have_x11" = "yes" && test "$need_x11" = "yes"; 
then
   echo "X11_CFLAGS=$x11_cflags" >> $config_host_mak
   echo "X11_LIBS=$x11_libs" >> $config_host_mak
 fi
-if test "$cocoa" = "yes" ; then
-  echo "CONFIG_COCOA=y" >> $config_host_mak
-fi
 if test "$iconv" = "yes" ; then
   echo "CONFIG_ICONV=y" >> $config_host_mak
   echo "ICONV_CFLAGS=$iconv_cflags" >> $config_host_mak
@@ -7860,7 +7857,7 @@ NINJA=${ninja:-$PWD/ninjatool} $meson setup \
 -Db_pie=$(if test "$pie" = yes; then echo true; else echo false; fi) \
 -Db_coverage=$(if test "$gcov" = yes; then echo true; else echo false; 
fi) \
-Dmalloc=$malloc -Dmalloc_trim=$malloc_trim \
-   -Dmpath=$mpath -Dsdl=$sdl -Dsdl_image=$sdl_image \
+   -Dcocoa=$cocoa -Dmpath=$mpath -Dsdl=$sdl -Dsdl_image=$sdl_image \
-Dvnc=$vnc -Dvnc_sasl=$vnc_sasl -Dvnc_jpeg=$vnc_jpeg -Dvnc_png=$vnc_png 
\
-Dgettext=$gettext -Dxkbcommon=$xkbcommon -Du2f=$u2f\
 $cross_arg \
diff --git a/meson.build b/meson.build
index 08ebfca6d0..1e7d2f9a0a 100644
--- a/meson.build
+++ b/meson.build
@@ -101,7 +101,7 @@ socket = []
 version_res = []
 coref = []
 iokit = []
-cocoa = []
+cocoa = not_found
 hvf = []
 if targetos == 'windows'
   socket = cc.find_library('ws2_32')
@@ -114,7 +114,7 @@ if targetos == 'windows'
 elif targetos == 'darwin'
   coref = dependency('appleframeworks', modules: 'CoreFoundation')
   iokit = dependency('appleframeworks', modules: 'IOKit')
-  cocoa = dependency('appleframeworks', modules: 'Cocoa')
+  cocoa = dependency('appleframeworks', modules: 'Cocoa', required: 
get_option('cocoa'))
   hvf = dependency('appleframeworks', modules: 'Hypervisor')
 elif targetos == 'sunos'
   socket = [cc.find_library('socket'),
@@ -126,6 +126,10 @@ elif targetos == 'haiku'
 cc.find_library('bsd')]
 endif
 
+if not cocoa.found() and get_option('cocoa').enabled()
+  error('Cocoa not available on this platform')
+endif
+
 
 # Dependencies #
 
@@ -536,6 +540,7 @@ endif
 
 # Create config-host.h
 
+config_host_data.set('CONFIG_COCOA', cocoa.found())
 config_host_data.set('CONFIG_LIBUDEV', libudev.found())
 config_host_data.set('CONFIG_MPATH', mpathpersist.found())
 config_host_data.set('CONFIG_MPATH_NEW_API', mpathpersist_new_api)
diff --git a/meson_options.txt b/meson_options.txt
index 8a59ec263d..46ea1d889a 100644
--- a/meson_options.txt
+++ b/meson_options.txt
@@ -11,6 +11,8 @@ option('malloc_trim', type : 'feature', value : 'auto',
 option('malloc', type : 'combo', choices : ['system', 'tcmalloc', 'jemalloc'],
value: 'system', description: 'choose memory allocator to use')
 
+option('cocoa', type : 'feature', value : 'auto',
+   description: 'Cocoa user interface (macOS only)')
 option('mpath', type : 'feature', value : 'auto',
description: 'Multipath persistent reservation passthrough')
 option('sdl', type : 'feature', value : 'auto',
diff --git a/ui/meson.build b/ui/meson.build
index dd6c110136..8a080c38e3 100644
--- a/ui/meson.build
+++ b/ui/meson.build
@@ -15,7 +15,7 @@ softmmu_ss.add(files(
 
 softmmu_ss.add(when: 'CONFIG_LINUX', if_true: files('input-linux.c'))
 softmmu_ss.add(when: 'CONFIG_SPICE', if_true: files('spice-core.c', 
'spice

[PULL 30/92] meson: move libmpathpersist test

[Paolo Bonzini]

This is the first compiler/linker test that has been moved to Meson.
Add more section headings to keep things clearer.

This also fixes static linking to libmpathpersist, which has a
dependency on libmultipath but no pkg-config file to describe it.

Signed-off-by: Paolo Bonzini 
---
 configure | 77 +++
 meson.build   | 83 ++-
 meson_options.txt |  2 ++
 3 files changed, 81 insertions(+), 81 deletions(-)

diff --git a/configure b/configure
index c05d1a04e9..6cffe0fde8 100755
--- a/configure
+++ b/configure
@@ -403,7 +403,7 @@ netmap="no"
 sdl="auto"
 sdl_image="auto"
 virtfs=""
-mpath=""
+mpath="auto"
 vnc="enabled"
 sparse="no"
 vde=""
@@ -1116,9 +1116,9 @@ for opt do
   ;;
   --enable-virtfs) virtfs="yes"
   ;;
-  --disable-mpath) mpath="no"
+  --disable-mpath) mpath="disabled"
   ;;
-  --enable-mpath) mpath="yes"
+  --enable-mpath) mpath="enabled"
   ;;
   --disable-vnc) vnc="disabled"
   ;;
@@ -3851,57 +3851,6 @@ if test "$modules" = yes; then
 fi
 fi
 
-##
-# libmpathpersist probe
-
-if test "$mpath" != "no" ; then
-  # probe for the new API
-  cat > $TMPC <
-#include 
-unsigned mpath_mx_alloc_len = 1024;
-int logsink;
-static struct config *multipath_conf;
-extern struct udev *udev;
-extern struct config *get_multipath_config(void);
-extern void put_multipath_config(struct config *conf);
-struct udev *udev;
-struct config *get_multipath_config(void) { return multipath_conf; }
-void put_multipath_config(struct config *conf) { }
-
-int main(void) {
-udev = udev_new();
-multipath_conf = mpath_lib_init();
-return 0;
-}
-EOF
-  if compile_prog "" "-ludev -lmultipath -lmpathpersist" ; then
-mpathpersist=yes
-mpathpersist_new_api=yes
-  else
-# probe for the old API
-cat > $TMPC <
-#include 
-unsigned mpath_mx_alloc_len = 1024;
-int logsink;
-int main(void) {
-struct udev *udev = udev_new();
-mpath_lib_init(udev);
-return 0;
-}
-EOF
-if compile_prog "" "-ludev -lmultipath -lmpathpersist" ; then
-  mpathpersist=yes
-  mpathpersist_new_api=no
-else
-  mpathpersist=no
-fi
-  fi
-else
-  mpathpersist=no
-fi
-
 ##
 # pthread probe
 PTHREADLIBS_LIST="-pthread -lpthread -lpthreadGC2"
@@ -6343,23 +6292,11 @@ if test "$softmmu" = yes ; then
   fi
   virtfs=no
 fi
-if test "$mpath" != no && test "$mpathpersist" = yes ; then
-  mpath=yes
-else
-  if test "$mpath" = yes; then
-error_exit "Multipath requires libmpathpersist devel"
-  fi
-  mpath=no
-fi
   else
 if test "$virtfs" = yes; then
   error_exit "VirtFS is supported only on Linux"
 fi
 virtfs=no
-if test "$mpath" = yes; then
-  error_exit "Multipath is supported only on Linux"
-fi
-mpath=no
   fi
 fi
 
@@ -6900,12 +6837,6 @@ fi
 if test "$virtfs" = "yes" ; then
   echo "CONFIG_VIRTFS=y" >> $config_host_mak
 fi
-if test "$mpath" = "yes" ; then
-  echo "CONFIG_MPATH=y" >> $config_host_mak
-  if test "$mpathpersist_new_api" = "yes"; then
-echo "CONFIG_MPATH_NEW_API=y" >> $config_host_mak
-  fi
-fi
 if test "$vhost_scsi" = "yes" ; then
   echo "CONFIG_VHOST_SCSI=y" >> $config_host_mak
 fi
@@ -7995,7 +7926,7 @@ NINJA=${ninja:-$PWD/ninjatool} $meson setup \
 -Dstrip=$(if test "$strip_opt" = yes; then echo true; else echo false; 
fi) \
 -Db_pie=$(if test "$pie" = yes; then echo true; else echo false; fi) \
 -Db_coverage=$(if test "$gcov" = yes; then echo true; else echo false; 
fi) \
-   -Dsdl=$sdl -Dsdl_image=$sdl_image \
+   -Dmpath=$mpath -Dsdl=$sdl -Dsdl_image=$sdl_image \
-Dvnc=$vnc -Dvnc_sasl=$vnc_sasl -Dvnc_jpeg=$vnc_jpeg -Dvnc_png=$vnc_png 
\
-Dgettext=$gettext -Dxkbcommon=$xkbcommon -Du2f=$u2f\
 $cross_arg \
diff --git a/meson.build b/meson.build
index 76e1f90943..86b6fe49c4 100644
--- a/meson.build
+++ b/meson.build
@@ -86,6 +86,14 @@ if 'SPARSE_CFLAGS' in config_host
'compile_commands.json'])
 endif
 
+###
+# Target-specific checks and dependencies #
+###
+
+if targetos != 'linux' and get_option('mpath').enabled()
+  error('Multipath is supported only on Linux')
+endif
+
 m = cc.find_library('m', required: false)
 util = cc.find_library('util', required: false)
 winmm = []
@@ -117,6 +125,11 @@ elif targetos == 'haiku'
 cc.find_library('network'),
 cc.find_library('bsd')]
 endif
+
+
+# Dependencies #
+
+
 # The path to glib.h is added to all compilation commands.  This was
 # grandfathered in from the QEMU Makefiles.
 add_project_arguments(config_host['GLIB_CFLAGS'].split(),
@@ -223,10 +236,6 @@ if 'CONFIG_SPICE' in config_host
  link_args: config_host['SPICE_LIBS'].split())
 endif
 rt = cc.find_li