Re: [OpenWrt-Devel] [RFC] ar71xx: Reset QCA955x SGMII link on speed change
On Friday 01 April 2016 14:41:47 Sven Eckelmann wrote:
[...]
> static void qca955x_set_speed_xmii(int speed)
> {
> void __iomem *base;
> @@ -381,6 +395,100 @@ static void qca955x_set_speed_xmii(int speed)
> base = ioremap_nocache(AR71XX_PLL_BASE, AR71XX_PLL_SIZE);
> __raw_writel(val, base + QCA955X_PLL_ETH_XMII_CONTROL_REG);
> iounmap(base);
> +
> + // TODO: find out if something like qca955x_reset_xmii(); is needed
> +}
I was told that the GMAC0 also needs some special bits set to fix some
problems when switching between different half/full duplex speeds. The
only thing I was told is that qca955x_soc_gmac_set_link requires
athr_reg_rmw_set(0xb900023c, 0x6801);
Of course, it is not for QCAs current driver (which is a heavily
modified driver from OpenWrt) but their old one
https://github.com/Existed/ethernet_driver/blob/3bde1bb60d31d78fee14cce0d8ea9539d8227a0d/qca955x.c#L587
I know that this register is IG_ACL_CSR for GMAC0 and BIT(0) is
IG_ACL_DISABLE and should only disable the ingress ACL. But I
have absolutely no idea what BIT(27), BIT(29) and BIT(30) are.
Does anyone know what these bits are? I personally don't have
yet feedback if this change really helps. But a equally bad
hack as the earlier one (sgmii) would be:
--- a/target/linux/ar71xx/files/arch/mips/ath79/dev-eth.c
+++ b/target/linux/ar71xx/files/arch/mips/ath79/dev-eth.c
@@ -387,6 +387,15 @@ static void ar934x_set_speed_ge0(int speed)
#define QCA955X_GMAC_REG_SGMII_RESET_TX_CLK_N BIT(1)
#define QCA955X_GMAC_REG_SGMII_RESET_RX_CLK_N BIT(0)
+#define QCA955X_GE0_BASE 0x1900
+#define QCA955X_GE0_SIZE 0x2F0
+
+#define QCA955X_GE0_IG_ACL_CSR 0x23C
+#define QCA955X_GE0_IG_ACL_DISABLE BIT(0)
+#define QCA955X_GE0_IG_ACL_MAGIC0 BIT(27)
+#define QCA955X_GE0_IG_ACL_MAGIC1 BIT(29)
+#define QCA955X_GE0_IG_ACL_MAGIC2 BIT(30)
+
static void qca955x_set_speed_xmii(int speed)
{
void __iomem *base;
@@ -396,7 +405,14 @@ static void qca955x_set_speed_xmii(int speed)
__raw_writel(val, base + QCA955X_PLL_ETH_XMII_CONTROL_REG);
iounmap(base);
- // TODO: find out if something like qca955x_reset_xmii(); is needed
+ /* WARNING ugly PoC code ahead */
+ base = ioremap_nocache(QCA955X_GE0_BASE, QCA955X_GE0_SIZE);
+ val = QCA955X_GE0_IG_ACL_DISABLE |
+ QCA955X_GE0_IG_ACL_MAGIC0 |
+ QCA955X_GE0_IG_ACL_MAGIC1 |
+ QCA955X_GE0_IG_ACL_MAGIC2;
+ __raw_writel(val, base + QCA955X_GE0_IG_ACL_CSR);
+ iounmap(base);
}
static void qca955x_reset_sgmii(void)
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[OpenWrt-Devel] ramips: Disable the SD driver by default on MT7621
The SD driver has been a long and dragging issue on the MT7621 platforms as it hasn't worked for months resulting in unbootable devices. Until it's fixed, disable it in the default profiles. Reports / Discussed here: https://dev.openwrt.org/ticket/21392 https://dev.openwrt.org/ticket/21834 https://dev.openwrt.org/ticket/21995 https://forum.openwrt.org/viewtopic.php?id=59092 Signed-off-by: Daniel Engberg --- diff --git a/target/linux/ramips/mt7621/profiles/firefly.mk b/target/linux/ramips/mt7621/profiles/firefly.mk index bc50ab4..9797527 100644 --- a/target/linux/ramips/mt7621/profiles/firefly.mk +++ b/target/linux/ramips/mt7621/profiles/firefly.mk @@ -8,7 +8,7 @@ define Profile/FIREWRT NAME:=Firefly FireWRT PACKAGES:=\ - kmod-usb-core kmod-usb3 kmod-usb-hid kmod-sdhci-mt7620 \ + kmod-usb-core kmod-usb3 kmod-usb-hid \ kmod-ledtrig-usbdev endef diff --git a/target/linux/ramips/mt7621/profiles/misc.mk b/target/linux/ramips/mt7621/profiles/misc.mk index ee25b95..06a9d44 100644 --- a/target/linux/ramips/mt7621/profiles/misc.mk +++ b/target/linux/ramips/mt7621/profiles/misc.mk @@ -9,7 +9,7 @@ define Profile/PBR-M1 NAME:=PBR-M1 Device FEATURES+=rtc PACKAGES:=\ - kmod-usb-core kmod-usb3 kmod-usb-hid kmod-sdhci-mt7620 \ + kmod-usb-core kmod-usb3 kmod-usb-hid \ kmod-ledtrig-usbdev kmod-ata-core kmod-ata-ahci \ kmod-rtc-pcf8563 endef diff --git a/target/linux/ramips/mt7621/profiles/mqmaker.mk b/target/linux/ramips/mt7621/profiles/mqmaker.mk index ae35e7d..8acc116 100644 --- a/target/linux/ramips/mt7621/profiles/mqmaker.mk +++ b/target/linux/ramips/mt7621/profiles/mqmaker.mk @@ -9,7 +9,7 @@ define Profile/witi NAME:=MQmaker WiTi FEATURES+=rtc PACKAGES:=\ - kmod-usb-core kmod-usb3 kmod-usb-hid kmod-sdhci-mt7620 \ + kmod-usb-core kmod-usb3 kmod-usb-hid \ kmod-ledtrig-usbdev kmod-ata-core kmod-ata-ahci \ kmod-rtc-pcf8563 kmod-i2c-mt7621 endef diff --git a/target/linux/ramips/mt7621/profiles/zbt.mk b/target/linux/ramips/mt7621/profiles/zbt.mk index 07131d1..0073645 100644 --- a/target/linux/ramips/mt7621/profiles/zbt.mk +++ b/target/linux/ramips/mt7621/profiles/zbt.mk @@ -8,7 +8,7 @@ define Profile/ZBT-WG2626 NAME:=ZBT-WG2626 Device PACKAGES:=\ - kmod-usb-core kmod-usb3 kmod-sdhci-mt7620 \ + kmod-usb-core kmod-usb3 \ kmod-ledtrig-usbdev kmod-ata-core kmod-ata-ahci endef ___ openwrt-devel mailing list openwrt-devel@lists.openwrt.org https://lists.openwrt.org/cgi-bin/mailman/listinfo/openwrt-devel
Re: [OpenWrt-Devel] [RFC] ar71xx: Reset QCA955x SGMII link on speed change
On Friday 01 April 2016 14:41:47 Sven Eckelmann wrote: > From: Sven Eckelmann > > The SGMII link of the QCA955x seems to be unstable when the PHY changes the > link speed. Reseting the SGMII and the PHY management control seems to > resolve this problem. > > This was observed with an AR8033 and QCA9558 > > The code of this RFC is not meant to be an actual patch. It should show > what the u-boot for QCA955x does and what seemed to work(tm) in my limited > tests. It would be interesting to know whether this was also noticed by > other people and how they fixed it (when they fixed it). > > If it is already known than it would maybe good to find a better way to > integrate it with ag71xx. Right now it just uses the set_speed callback to > start the reset. > > Signed-off-by: Sven Eckelmann > --- Just did a search in the codeaurora repository. I found at least some extra information: * SGMII reset code (like in this "RFC"/u-boot): https://us.codeaurora.org/cgit/quic/qsdk/oss/system/openwrt/commit/?id=38de68c74bac2147250ce21879a6f1a7adda5d49 * The IG_ACL_CSR (AG71XX_REG_IG_ACL) change from my second hack: https://us.codeaurora.org/cgit/quic/qsdk/oss/system/openwrt/commit/?id=7e0e30d4a5e40927a9fa005a0c9ee9c7e16dc020 (the information about the chip family is not that easily available in the original OpenWrt driver. so it is not that easy to implement without adding more stuff to pdata - but easy when the pdata can also be modified at the same time) * The "description" of the SGMII_DEBUG register can be found in the u-boot sources (955x.h) https://us.codeaurora.org/cgit/quic/qsdk/oss/system/openwrt/commit/?id=96779a2ee2470c15135dc1a7aa80d20eced4dc89 Kind regards, Sven ___ openwrt-devel mailing list openwrt-devel@lists.openwrt.org https://lists.openwrt.org/cgi-bin/mailman/listinfo/openwrt-devel
Re: [OpenWrt-Devel] 15.05.1 - Chaos Calmer
> Great! Thanks for your good work! > Could you please add a tag for 15.05.1 in the git repo? That would be great. I am trying to git bisect a bug and I have no idea on top of what commit is 15.05.1 built. thank you :) Saverio ___ openwrt-devel mailing list openwrt-devel@lists.openwrt.org https://lists.openwrt.org/cgi-bin/mailman/listinfo/openwrt-devel
Re: [OpenWrt-Devel] 15.05.1 - Chaos Calmer
On 04/04/2016 09:34 PM, Saverio Proto wrote: >> Great! Thanks for your good work! >> Could you please add a tag for 15.05.1 in the git repo? > > That would be great. I am trying to git bisect a bug and I have no > idea on top of what commit is 15.05.1 built. There is a tag for it already: https://github.com/openwrt/openwrt/tags bruno ___ openwrt-devel mailing list openwrt-devel@lists.openwrt.org https://lists.openwrt.org/cgi-bin/mailman/listinfo/openwrt-devel
[OpenWrt-Devel] [PATCH 0/2] Fix PCI for cns3xxx platform
Currently, PCI does not work on the cns3xxx platform due to several bugs. Krzysztof Hałasa has authored two patches which fix some regressions. Links to the discussion can be found here: * http://www.spinics.net/lists/arm-kernel/msg490185.html (in the next/fixes-non-critical for ARM) * http://www.spinics.net/lists/linux-pci/msg49796.html (currently pending) Note that I executed 'make target/linux/refresh' to put the patches into the proper 'OpenWrt' format. Pushpal Sidhu (2): cns3xxx: backport pci fix for cns3xxx_write_config cns3xxx: set both MPS 'and' MRSS to 128 target/linux/cns3xxx/patches-4.4/033-CNS3xxx-Fix-PCI-cns3xxx_write_config.patch | 19 +++ .../cns3xxx/patches-4.4/130-Extend-PCIE_BUS_PEER2PEER-to-set-MRSS-128-to-fix-CNS3xxx-BM-DMA..patch | 23 +++ 2 files changed, 42 insertions(+) - Pushpal ___ openwrt-devel mailing list openwrt-devel@lists.openwrt.org https://lists.openwrt.org/cgi-bin/mailman/listinfo/openwrt-devel
[OpenWrt-Devel] [PATCH 1/2] cns3xxx: backport pci fix for cns3xxx_write_config
Fix is required to properly set pci config bits. Original Patch: https://patchwork.ozlabs.org/patch/596170/ Signed-off-by: Pushpal Sidhu --- .../033-CNS3xxx-Fix-PCI-cns3xxx_write_config.patch| 19 +++ 1 file changed, 19 insertions(+) create mode 100644 target/linux/cns3xxx/patches-4.4/033-CNS3xxx-Fix-PCI-cns3xxx_write_config.patch diff --git a/target/linux/cns3xxx/patches-4.4/033-CNS3xxx-Fix-PCI-cns3xxx_write_config.patch b/target/linux/cns3xxx/patches-4.4/033-CNS3xxx-Fix-PCI-cns3xxx_write_config.patch new file mode 100644 index 000..3f5ab06 --- /dev/null +++ b/target/linux/cns3xxx/patches-4.4/033-CNS3xxx-Fix-PCI-cns3xxx_write_config.patch @@ -0,0 +1,19 @@ +--- a/arch/arm/mach-cns3xxx/pcie.c b/arch/arm/mach-cns3xxx/pcie.c +@@ -220,13 +220,13 @@ static void cns3xxx_write_config(struct + u32 mask = (0x1ull << (size * 8)) - 1; + int shift = (where % 4) * 8; + +- v = readl_relaxed(base + (where & 0xffc)); ++ v = readl_relaxed(base); + + v &= ~(mask << shift); + v |= (val & mask) << shift; + +- writel_relaxed(v, base + (where & 0xffc)); +- readl_relaxed(base + (where & 0xffc)); ++ writel_relaxed(v, base); ++ readl_relaxed(base); + } + + static void __init cns3xxx_pcie_hw_init(struct cns3xxx_pcie *cnspci) -- 2.7.2 ___ openwrt-devel mailing list openwrt-devel@lists.openwrt.org https://lists.openwrt.org/cgi-bin/mailman/listinfo/openwrt-devel
[OpenWrt-Devel] [PATCH 2/2] cns3xxx: set both MPS 'and' MRSS to 128
Fixes some DMA issues with this platform. Because this isn't currently accepted,
and can potentially disrupt other platforms (as read in commit log), I will
leave this cns3xxx specific.
Original Patch: https://patchwork.ozlabs.org/patch/600024/
Signed-off-by: Pushpal Sidhu
---
...ER-to-set-MRSS-128-to-fix-CNS3xxx-BM-DMA..patch | 23 ++
1 file changed, 23 insertions(+)
create mode 100644
target/linux/cns3xxx/patches-4.4/130-Extend-PCIE_BUS_PEER2PEER-to-set-MRSS-128-to-fix-CNS3xxx-BM-DMA..patch
diff --git
a/target/linux/cns3xxx/patches-4.4/130-Extend-PCIE_BUS_PEER2PEER-to-set-MRSS-128-to-fix-CNS3xxx-BM-DMA..patch
b/target/linux/cns3xxx/patches-4.4/130-Extend-PCIE_BUS_PEER2PEER-to-set-MRSS-128-to-fix-CNS3xxx-BM-DMA..patch
new file mode 100644
index 000..208c80a
--- /dev/null
+++
b/target/linux/cns3xxx/patches-4.4/130-Extend-PCIE_BUS_PEER2PEER-to-set-MRSS-128-to-fix-CNS3xxx-BM-DMA..patch
@@ -0,0 +1,23 @@
+--- a/drivers/pci/probe.c
b/drivers/pci/probe.c
+@@ -1924,7 +1924,8 @@ static void pcie_write_mrrs(struct pci_d
+ /* In the "safe" case, do not configure the MRRS. There appear to be
+* issues with setting MRRS to 0 on a number of devices.
+*/
+- if (pcie_bus_config != PCIE_BUS_PERFORMANCE)
++ if (pcie_bus_config != PCIE_BUS_PERFORMANCE &&
++ pcie_bus_config != PCIE_BUS_PEER2PEER)
+ return;
+
+ /* For Max performance, the MRRS must be set to the largest supported
+--- a/include/linux/pci.h
b/include/linux/pci.h
+@@ -756,7 +756,7 @@ enum pcie_bus_config_types {
+ PCIE_BUS_DEFAULT, /* ensure MPS matches upstream bridge */
+ PCIE_BUS_SAFE, /* use largest MPS boot-time devices support */
+ PCIE_BUS_PERFORMANCE, /* use MPS and MRRS for best performance */
+- PCIE_BUS_PEER2PEER, /* set MPS = 128 for all devices */
++ PCIE_BUS_PEER2PEER, /* set MPS and MRSS to 128 for all devices */
+ };
+
+ extern enum pcie_bus_config_types pcie_bus_config;
--
2.7.2
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[OpenWrt-Devel] [PATCH] Fixes for LinkIt 7688
Misc fixes for LinkIt 7688 board:
- Copy the right wireless firmware for the mt7688
- Add back '0065-mt7688-fixes.patch', left out after the move to Linux 4.4.
- Remove SPI_DEV from linux config which otherwise causes a massive warning
- Add wmac to LINKIT7688.dts so wireless works
---
package/kernel/mt76/Makefile | 2 +-
target/linux/ramips/dts/LINKIT7688.dts | 4 ++
target/linux/ramips/mt7688/config-4.4 | 2 +-
.../ramips/patches-4.4/0065-mt7688-fixes.patch | 73 ++
4 files changed, 79 insertions(+), 2 deletions(-)
create mode 100644 target/linux/ramips/patches-4.4/0065-mt7688-fixes.patch
diff --git a/package/kernel/mt76/Makefile b/package/kernel/mt76/Makefile
index 8800b13..33f61cb 100644
--- a/package/kernel/mt76/Makefile
+++ b/package/kernel/mt76/Makefile
@@ -55,7 +55,7 @@ endef
define KernelPackage/mt76/install
$(INSTALL_DIR) $(1)/lib/firmware
cp \
- $(if $(CONFIG_TARGET_ramips_mt7628), \
+ $(if $(CONFIG_TARGET_ramips_mt7628) ||
$(CONFIG_TARGET_ramips_mt7688), \
$(PKG_BUILD_DIR)/firmware/mt7628_e1.bin \
$(PKG_BUILD_DIR)/firmware/mt7628_e2.bin \
) \
diff --git a/target/linux/ramips/dts/LINKIT7688.dts
b/target/linux/ramips/dts/LINKIT7688.dts
index 5ec29ac..2dfb98c 100644
--- a/target/linux/ramips/dts/LINKIT7688.dts
+++ b/target/linux/ramips/dts/LINKIT7688.dts
@@ -59,6 +59,10 @@
};
};
+ wmac@1030 {
+ status = "okay";
+ };
+
palmbus@1000 {
spi@b00 {
status = "okay";
diff --git a/target/linux/ramips/mt7688/config-4.4
b/target/linux/ramips/mt7688/config-4.4
index c1e8df2..2bfd3f8 100644
--- a/target/linux/ramips/mt7688/config-4.4
+++ b/target/linux/ramips/mt7688/config-4.4
@@ -193,7 +193,7 @@ CONFIG_SPI=y
CONFIG_SPI_MASTER=y
CONFIG_SPI_MT7621=y
# CONFIG_SPI_RT2880 is not set
-CONFIG_SPI_SPIDEV=y
+# CONFIG_SPI_SPIDEV is not set
CONFIG_SRCU=y
CONFIG_SWCONFIG=y
CONFIG_SYSCTL_EXCEPTION_TRACE=y
diff --git a/target/linux/ramips/patches-4.4/0065-mt7688-fixes.patch
b/target/linux/ramips/patches-4.4/0065-mt7688-fixes.patch
new file mode 100644
index 000..b96be91
--- /dev/null
+++ b/target/linux/ramips/patches-4.4/0065-mt7688-fixes.patch
@@ -0,0 +1,73 @@
+--- a/arch/mips/ralink/mt7620.c
b/arch/mips/ralink/mt7620.c
+@@ -107,31 +107,31 @@ static struct rt2880_pmx_group mt7620a_p
+ };
+
+ static struct rt2880_pmx_func pwm1_grp_mt7628[] = {
+- FUNC("sdcx", 3, 19, 1),
++ FUNC("sdxc", 3, 19, 1),
+ FUNC("utif", 2, 19, 1),
+ FUNC("gpio", 1, 19, 1),
+ FUNC("pwm", 0, 19, 1),
+ };
+
+ static struct rt2880_pmx_func pwm0_grp_mt7628[] = {
+- FUNC("sdcx", 3, 18, 1),
++ FUNC("sdxc", 3, 18, 1),
+ FUNC("utif", 2, 18, 1),
+ FUNC("gpio", 1, 18, 1),
+ FUNC("pwm", 0, 18, 1),
+ };
+
+ static struct rt2880_pmx_func uart2_grp_mt7628[] = {
+- FUNC("sdcx", 3, 20, 2),
++ FUNC("sdxc", 3, 20, 2),
+ FUNC("pwm", 2, 20, 2),
+ FUNC("gpio", 1, 20, 2),
+- FUNC("uart", 0, 20, 2),
++ FUNC("uart2", 0, 20, 2),
+ };
+
+ static struct rt2880_pmx_func uart1_grp_mt7628[] = {
+ FUNC("sdcx", 3, 45, 2),
+ FUNC("pwm", 2, 45, 2),
+ FUNC("gpio", 1, 45, 2),
+- FUNC("uart", 0, 45, 2),
++ FUNC("uart1", 0, 45, 2),
+ };
+
+ static struct rt2880_pmx_func i2c_grp_mt7628[] = {
+@@ -143,21 +143,21 @@ static struct rt2880_pmx_func i2c_grp_mt
+
+ static struct rt2880_pmx_func refclk_grp_mt7628[] = { FUNC("reclk", 0, 36, 1)
};
+ static struct rt2880_pmx_func perst_grp_mt7628[] = { FUNC("perst", 0, 37, 1)
};
+-static struct rt2880_pmx_func wdt_grp_mt7628[] = { FUNC("wdt", 0, 15, 38) };
++static struct rt2880_pmx_func wdt_grp_mt7628[] = { FUNC("wdt", 0, 38, 1) };
+ static struct rt2880_pmx_func spi_grp_mt7628[] = { FUNC("spi", 0, 7, 4) };
+
+ static struct rt2880_pmx_func sd_mode_grp_mt7628[] = {
+ FUNC("jtag", 3, 22, 8),
+ FUNC("utif", 2, 22, 8),
+ FUNC("gpio", 1, 22, 8),
+- FUNC("sdcx", 0, 22, 8),
++ FUNC("sdxc", 0, 22, 8),
+ };
+
+ static struct rt2880_pmx_func uart0_grp_mt7628[] = {
+ FUNC("-", 3, 12, 2),
+ FUNC("-", 2, 12, 2),
+ FUNC("gpio", 1, 12, 2),
+- FUNC("uart", 0, 12, 2),
++ FUNC("uart0", 0, 12, 2),
+ };
+
+ static struct rt2880_pmx_func i2s_grp_mt7628[] = {
+@@ -438,6 +438,8 @@ void __init ralink_clk_init(void)
+ ralink_clk_add("1b00.spi", sys_rate);
+ ralink_clk_add("1b40.spi", sys_rate);
+ ralink_clk_add("1c00.uartlite", periph_rate);
++ ralink_clk_add("1d00.uart1", periph_rate);
++ ralink_clk_add("1e00.uart2", periph_rate);
+ ralink_clk_add("1018.wmac", xtal_rate);
+
+ if (IS_ENABLED(CONFIG_USB) && is_mt76x8()) {
--
1.9.1
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