Fix is required to properly set pci config bits. Original Patch: https://patchwork.ozlabs.org/patch/596170/
Signed-off-by: Pushpal Sidhu <psi...@gateworks.com> --- .../033-CNS3xxx-Fix-PCI-cns3xxx_write_config.patch | 19 +++++++++++++++++++ 1 file changed, 19 insertions(+) create mode 100644 target/linux/cns3xxx/patches-4.4/033-CNS3xxx-Fix-PCI-cns3xxx_write_config.patch diff --git a/target/linux/cns3xxx/patches-4.4/033-CNS3xxx-Fix-PCI-cns3xxx_write_config.patch b/target/linux/cns3xxx/patches-4.4/033-CNS3xxx-Fix-PCI-cns3xxx_write_config.patch new file mode 100644 index 0000000..3f5ab06 --- /dev/null +++ b/target/linux/cns3xxx/patches-4.4/033-CNS3xxx-Fix-PCI-cns3xxx_write_config.patch @@ -0,0 +1,19 @@ +--- a/arch/arm/mach-cns3xxx/pcie.c ++++ b/arch/arm/mach-cns3xxx/pcie.c +@@ -220,13 +220,13 @@ static void cns3xxx_write_config(struct + u32 mask = (0x1ull << (size * 8)) - 1; + int shift = (where % 4) * 8; + +- v = readl_relaxed(base + (where & 0xffc)); ++ v = readl_relaxed(base); + + v &= ~(mask << shift); + v |= (val & mask) << shift; + +- writel_relaxed(v, base + (where & 0xffc)); +- readl_relaxed(base + (where & 0xffc)); ++ writel_relaxed(v, base); ++ readl_relaxed(base); + } + + static void __init cns3xxx_pcie_hw_init(struct cns3xxx_pcie *cnspci) -- 2.7.2 _______________________________________________ openwrt-devel mailing list openwrt-devel@lists.openwrt.org https://lists.openwrt.org/cgi-bin/mailman/listinfo/openwrt-devel
