Re: [Mesa-dev] [PATCH 02/19] i965: Introduce a new brw_inst API.
On Friday, June 13, 2014 11:14:03 PM Matt Turner wrote:
> From: Kenneth Graunke
>
> This is similar to gen8_instruction, and will replace it
>
> For now nothing uses this, but we can incrementally convert.
> The new API takes the existing brw_instruction pointers to ease
> conversion; when done, we can simply drop the old structure and rename
> struct brw_instruction -> brw_inst.
>
> Reviewed-by: Matt Turner
I might add something like:
v2: (by Matt Turner) Make JIP/UIP functions take a signed argument.
(and anything else you did - I think that's the main thing)
Signed-off-by: Kenneth Graunke [v1]
Reviewed-by: Matt Turner [v1]
Signed-off-by: Matt Turner [v2]
[snip]
> +/**
> + * Flow control instruction bits:
> + * @{
> + */
> +static inline void
> +brw_inst_set_uip(const struct brw_context *brw,
> + struct brw_instruction *inst, int16_t value)
int16_t makes sense for Gen4-7, but won't work well for Gen8+. On Broadwell,
you have to multiply the number of instructions by 16, instead of 2 on Gen5-7,
or 1 on Gen4. With a 16-bit integer, this limits you to 2^15 / 16 = 2047
instruction jump distances. We've definitely had shaders which would exceed
that.
Broadwell uses a full 32-bit value, which gives you 2^31 / 16 = 134217728
instruction jump distances - more than enough.
I think the cleanest way to handle this is to make the parameters int32_t and
do this:
static inline void
brw_inst_set_uip(const struct brw_context *brw,
struct brw_instruction *inst, int32_t value)
{
assert(brw->gen >= 6);
if (brw->gen >= 8) {
brw_inst_set_bits(inst, 127, 112, (uint16_t) value);
} else {
brw_inst_set_bits(inst, 95, 64, (uint32_t) value);
}
}
As an example...if you start with int16_t jump = -20 (0xffec)...
- Calling this function promotes it to int32_t (0xffec).
- Casting it to uint16_t truncates it to 0xffec.
- Casting it to uint32_t truncates it to 0xffec.
- Calling brw_inst_set_bits promotes the uint16_t/uint32_t to uint64_t,
adding more zeros, not f's: 0xffec or 0xffec.
So, I'm pretty sure this does what you want.
--Ken
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[Mesa-dev] [PATCH 2/3] i965: Drop Broadwell perf_debugs about missing MOCS that aren't missing.
I actually added MOCS support for these things, but forgot to delete the
corresponding perf_debug() warnings.
Signed-off-by: Kenneth Graunke
Cc: "10.2"
---
src/mesa/drivers/dri/i965/gen8_draw_upload.c | 2 --
src/mesa/drivers/dri/i965/gen8_misc_state.c | 2 --
2 files changed, 4 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/gen8_draw_upload.c
b/src/mesa/drivers/dri/i965/gen8_draw_upload.c
index 05a9c06..4d62739 100644
--- a/src/mesa/drivers/dri/i965/gen8_draw_upload.c
+++ b/src/mesa/drivers/dri/i965/gen8_draw_upload.c
@@ -94,8 +94,6 @@ gen8_emit_vertices(struct brw_context *brw)
if (brw->vb.nr_buffers) {
assert(brw->vb.nr_buffers <= 33);
- perf_debug("Missing MOCS setup for 3DSTATE_VERTEX_BUFFERS.");
-
BEGIN_BATCH(1 + 4*brw->vb.nr_buffers);
OUT_BATCH((_3DSTATE_VERTEX_BUFFERS << 16) | (4*brw->vb.nr_buffers - 1));
for (unsigned i = 0; i < brw->vb.nr_buffers; i++) {
diff --git a/src/mesa/drivers/dri/i965/gen8_misc_state.c
b/src/mesa/drivers/dri/i965/gen8_misc_state.c
index 44966e0..3c27c1a 100644
--- a/src/mesa/drivers/dri/i965/gen8_misc_state.c
+++ b/src/mesa/drivers/dri/i965/gen8_misc_state.c
@@ -31,8 +31,6 @@
*/
static void upload_state_base_address(struct brw_context *brw)
{
- perf_debug("Missing MOCS setup for STATE_BASE_ADDRESS.");
-
BEGIN_BATCH(16);
OUT_BATCH(CMD_STATE_BASE_ADDRESS << 16 | (16 - 2));
/* General state base address: stateless DP read/write requests */
--
1.9.1
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[Mesa-dev] [PATCH 3/3] i965: Add missing newlines to a few perf_debug messages.
Signed-off-by: Kenneth Graunke
Cc: "10.2"
---
src/mesa/drivers/dri/i965/gen6_clip_state.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/gen6_clip_state.c
b/src/mesa/drivers/dri/i965/gen6_clip_state.c
index 0ba190e..25dfb60 100644
--- a/src/mesa/drivers/dri/i965/gen6_clip_state.c
+++ b/src/mesa/drivers/dri/i965/gen6_clip_state.c
@@ -106,7 +106,7 @@ upload_clip_state(struct brw_context *brw)
dw2 &= ~GEN6_CLIP_GB_TEST;
if (brw->gen >= 8) {
perf_debug("Disabling GB clipping due to lack of Gen8 viewport "
- "clipping setup code. This should be fixed.");
+ "clipping setup code. This should be fixed.\n");
}
break;
}
@@ -116,7 +116,7 @@ upload_clip_state(struct brw_context *brw)
if (ctx->RasterDiscard) {
dw2 |= GEN6_CLIP_MODE_REJECT_ALL;
perf_debug("Rasterizer discard is currently implemented via the clipper;
"
- "%s be faster.", brw->gen >= 7 ? "using the SOL unit may" :
+ "%s be faster.\n", brw->gen >= 7 ? "using the SOL unit may" :
"having the GS not write primitives would likely");
}
--
1.9.1
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[Mesa-dev] [PATCH 1/3] i965: Add missing MOCS setup for 3DSTATE_INDEX_BUFFER on Broadwell.
Somehow I missed this when adding all of the other MOCS values.
Signed-off-by: Kenneth Graunke
Cc: "10.2"
---
src/mesa/drivers/dri/i965/gen8_draw_upload.c | 4 +---
1 file changed, 1 insertion(+), 3 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/gen8_draw_upload.c
b/src/mesa/drivers/dri/i965/gen8_draw_upload.c
index 0272892..05a9c06 100644
--- a/src/mesa/drivers/dri/i965/gen8_draw_upload.c
+++ b/src/mesa/drivers/dri/i965/gen8_draw_upload.c
@@ -213,11 +213,9 @@ gen8_emit_index_buffer(struct brw_context *brw)
if (index_buffer == NULL)
return;
- perf_debug("Missing MOCS setup for 3DSTATE_INDEX_BUFFER.");
-
BEGIN_BATCH(5);
OUT_BATCH(CMD_INDEX_BUFFER << 16 | (5 - 2));
- OUT_BATCH(brw_get_index_type(index_buffer->type) << 8);
+ OUT_BATCH(brw_get_index_type(index_buffer->type) << 8 | BDW_MOCS_WB);
OUT_RELOC64(brw->ib.bo, I915_GEM_DOMAIN_VERTEX, 0, 0);
OUT_BATCH(brw->ib.bo->size);
ADVANCE_BATCH();
--
1.9.1
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Re: [Mesa-dev] [PATCH] radeonsi: fixup sizes of shader resource and sampler arrays
Am 14.06.2014 03:46, schrieb Marek Olšák:
From: Marek Olšák
This was wrong for a very long time. I wonder if the array size has any
effect on anything.
We only do a bit of GEP pointer arithmetic with them and so probably
ignore range limits anyway.
Nevertheless it's obviously wrong and should be fixed. Patch is
Reviewed-by: Christian König
Regards,
Christian.
---
src/gallium/drivers/radeonsi/si_shader.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/src/gallium/drivers/radeonsi/si_shader.c
b/src/gallium/drivers/radeonsi/si_shader.c
index a7ca35b..4ed5906 100644
--- a/src/gallium/drivers/radeonsi/si_shader.c
+++ b/src/gallium/drivers/radeonsi/si_shader.c
@@ -2266,9 +2266,9 @@ static void create_function(struct si_shader_context
*si_shader_ctx)
/* We assume at most 16 textures per program at the moment.
* This need probably need to be changed to support bindless textures */
params[SI_PARAM_SAMPLER] = LLVMPointerType(
- LLVMArrayType(LLVMVectorType(i8, 16), NUM_SAMPLER_VIEWS),
CONST_ADDR_SPACE);
+ LLVMArrayType(LLVMVectorType(i8, 16), NUM_SAMPLER_STATES),
CONST_ADDR_SPACE);
params[SI_PARAM_RESOURCE] = LLVMPointerType(
- LLVMArrayType(LLVMVectorType(i8, 32), NUM_SAMPLER_STATES),
CONST_ADDR_SPACE);
+ LLVMArrayType(LLVMVectorType(i8, 32), NUM_SAMPLER_VIEWS),
CONST_ADDR_SPACE);
switch (si_shader_ctx->type) {
case TGSI_PROCESSOR_VERTEX:
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[Mesa-dev] [PATCH 1/2] i965: Add SHADER_OPCODE_SHADER_TIME_ADD to dump_instructions() decode.
"shader_time_add" is a lot more informative than "op152". Signed-off-by: Kenneth Graunke --- src/mesa/drivers/dri/i965/brw_shader.cpp | 2 ++ 1 file changed, 2 insertions(+) diff --git a/src/mesa/drivers/dri/i965/brw_shader.cpp b/src/mesa/drivers/dri/i965/brw_shader.cpp index 6ad0ff4..687356b 100644 --- a/src/mesa/drivers/dri/i965/brw_shader.cpp +++ b/src/mesa/drivers/dri/i965/brw_shader.cpp @@ -451,6 +451,8 @@ brw_instruction_name(enum opcode op) return "tg4"; case SHADER_OPCODE_TG4_OFFSET: return "tg4_offset"; + case SHADER_OPCODE_SHADER_TIME_ADD: + return "shader_time_add"; case SHADER_OPCODE_GEN4_SCRATCH_READ: return "gen4_scratch_read"; -- 2.0.0 ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-dev
[Mesa-dev] [PATCH 2/2] i965/vec4: Fix dead code elimination for VGRFs of size > 1.
When faced with code such as:
mov vgrf31.0:UD, 960D
mov vgrf31.1:UD, vgrf30.:UD
The dead code eliminator brilliantly decided that the second instruction
was writing to the same register as the first one, so the first one
could be eliminated. Except that they're not the same register at all.
This fixes INTEL_DEBUG=shader_time for vertex shaders. In the above
code, vgrf31.0 represents the offset into the shader_time buffer where
the data should be written, and vgrf31.1 represents the actual time
data. With a completely undefined offset, results were...unexpected.
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=79029
Signed-off-by: Kenneth Graunke
Cc: mesa-sta...@lists.freedesktop.org
Cc: Eero Tamminen
---
src/mesa/drivers/dri/i965/brw_vec4.cpp | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/src/mesa/drivers/dri/i965/brw_vec4.cpp
b/src/mesa/drivers/dri/i965/brw_vec4.cpp
index e816b94..ee5be56 100644
--- a/src/mesa/drivers/dri/i965/brw_vec4.cpp
+++ b/src/mesa/drivers/dri/i965/brw_vec4.cpp
@@ -464,7 +464,8 @@ vec4_visitor::dead_code_eliminate()
}
if (inst->dst.file == scan_inst->dst.file &&
- inst->dst.reg == scan_inst->dst.reg) {
+ inst->dst.reg == scan_inst->dst.reg &&
+ inst->dst.reg_offset == scan_inst->dst.reg_offset) {
int new_writemask = scan_inst->dst.writemask & ~dead_channels;
progress = try_eliminate_instruction(scan_inst, new_writemask,
brw) ||
--
2.0.0
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[Mesa-dev] [PATCH 2/3] nvc0: mark scissor in nvc0_clear_{}
Signed-off-by: Tobias Klausmann --- src/gallium/drivers/nouveau/nvc0/nvc0_surface.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/src/gallium/drivers/nouveau/nvc0/nvc0_surface.c b/src/gallium/drivers/nouveau/nvc0/nvc0_surface.c index c28ec6d..72227b8 100644 --- a/src/gallium/drivers/nouveau/nvc0/nvc0_surface.c +++ b/src/gallium/drivers/nouveau/nvc0/nvc0_surface.c @@ -298,6 +298,7 @@ nvc0_clear_render_target(struct pipe_context *pipe, BEGIN_NVC0(push, NVC0_3D(SCREEN_SCISSOR_HORIZ), 2); PUSH_DATA (push, ( width << 16) | dstx); PUSH_DATA (push, (height << 16) | dsty); + nvc0->scissors_dirty |= 1; BEGIN_NVC0(push, NVC0_3D(RT_CONTROL), 1); PUSH_DATA (push, 1); @@ -447,6 +448,7 @@ nvc0_clear_buffer(struct pipe_context *pipe, BEGIN_NVC0(push, NVC0_3D(SCREEN_SCISSOR_HORIZ), 2); PUSH_DATA (push, width << 16); PUSH_DATA (push, height << 16); + nvc0->scissors_dirty |= 1; IMMED_NVC0(push, NVC0_3D(RT_CONTROL), 1); @@ -521,6 +523,7 @@ nvc0_clear_depth_stencil(struct pipe_context *pipe, BEGIN_NVC0(push, NVC0_3D(SCREEN_SCISSOR_HORIZ), 2); PUSH_DATA (push, ( width << 16) | dstx); PUSH_DATA (push, (height << 16) | dsty); + nvc0->scissors_dirty |= 1; BEGIN_NVC0(push, NVC0_3D(ZETA_ADDRESS_HIGH), 5); PUSH_DATAh(push, mt->base.address + sf->offset); -- 1.8.4.5 ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-dev
[Mesa-dev] [PATCH 1/3] nvc0: implement multiple viewports/scissors, enable ARB_viewport_array
Signed-off-by: Tobias Klausmann
---
src/gallium/drivers/nouveau/nvc0/nvc0_context.h| 7 +-
src/gallium/drivers/nouveau/nvc0/nvc0_program.c| 2 +-
src/gallium/drivers/nouveau/nvc0/nvc0_screen.c | 20 ++--
src/gallium/drivers/nouveau/nvc0/nvc0_screen.h | 3 +
src/gallium/drivers/nouveau/nvc0/nvc0_state.c | 27 -
.../drivers/nouveau/nvc0/nvc0_state_validate.c | 121 +
6 files changed, 117 insertions(+), 63 deletions(-)
diff --git a/src/gallium/drivers/nouveau/nvc0/nvc0_context.h
b/src/gallium/drivers/nouveau/nvc0/nvc0_context.h
index 76416a0..674dd3c 100644
--- a/src/gallium/drivers/nouveau/nvc0/nvc0_context.h
+++ b/src/gallium/drivers/nouveau/nvc0/nvc0_context.h
@@ -178,8 +178,11 @@ struct nvc0_context {
struct pipe_blend_color blend_colour;
struct pipe_stencil_ref stencil_ref;
struct pipe_poly_stipple stipple;
- struct pipe_scissor_state scissor;
- struct pipe_viewport_state viewport;
+
+ struct pipe_scissor_state scissors[NVC0_MAX_VIEWPORTS];
+ unsigned scissors_dirty;
+ struct pipe_viewport_state viewports[NVC0_MAX_VIEWPORTS];
+ unsigned viewports_dirty;
struct pipe_clip_state clip;
unsigned sample_mask;
diff --git a/src/gallium/drivers/nouveau/nvc0/nvc0_program.c
b/src/gallium/drivers/nouveau/nvc0/nvc0_program.c
index 1c82a9a..667fbc8 100644
--- a/src/gallium/drivers/nouveau/nvc0/nvc0_program.c
+++ b/src/gallium/drivers/nouveau/nvc0/nvc0_program.c
@@ -64,7 +64,7 @@ nvc0_shader_output_address(unsigned sn, unsigned si, unsigned
ubase)
case NV50_SEMANTIC_TESSFACTOR:return 0x000 + si * 0x4;
case TGSI_SEMANTIC_PRIMID:return 0x060;
case TGSI_SEMANTIC_LAYER: return 0x064;
- case NV50_SEMANTIC_VIEWPORTINDEX: return 0x068;
+ case TGSI_SEMANTIC_VIEWPORT_INDEX:return 0x068;
case TGSI_SEMANTIC_PSIZE: return 0x06c;
case TGSI_SEMANTIC_POSITION: return 0x070;
case TGSI_SEMANTIC_GENERIC: return ubase + si * 0x10;
diff --git a/src/gallium/drivers/nouveau/nvc0/nvc0_screen.c
b/src/gallium/drivers/nouveau/nvc0/nvc0_screen.c
index 3e6b011..3fdb6ae 100644
--- a/src/gallium/drivers/nouveau/nvc0/nvc0_screen.c
+++ b/src/gallium/drivers/nouveau/nvc0/nvc0_screen.c
@@ -183,7 +183,7 @@ nvc0_screen_get_param(struct pipe_screen *pscreen, enum
pipe_cap param)
case PIPE_CAP_FAKE_SW_MSAA:
return 0;
case PIPE_CAP_MAX_VIEWPORTS:
- return 1;
+ return NVC0_MAX_VIEWPORTS;
case PIPE_CAP_TEXTURE_QUERY_LOD:
case PIPE_CAP_SAMPLE_SHADING:
case PIPE_CAP_TEXTURE_GATHER_OFFSETS:
@@ -933,19 +933,23 @@ nvc0_screen_create(struct nouveau_device *dev)
BEGIN_NVC0(push, NVC0_3D(VIEWPORT_TRANSFORM_EN), 1);
PUSH_DATA (push, 1);
- BEGIN_NVC0(push, NVC0_3D(DEPTH_RANGE_NEAR(0)), 2);
- PUSH_DATAf(push, 0.0f);
- PUSH_DATAf(push, 1.0f);
+ for (i = 0; i < NVC0_MAX_VIEWPORTS; i++) {
+ BEGIN_NVC0(push, NVC0_3D(DEPTH_RANGE_NEAR(i)), 2);
+ PUSH_DATAf(push, 0.0f);
+ PUSH_DATAf(push, 1.0f);
+ }
BEGIN_NVC0(push, NVC0_3D(VIEW_VOLUME_CLIP_CTRL), 1);
PUSH_DATA (push, NVC0_3D_VIEW_VOLUME_CLIP_CTRL_UNK1_UNK1);
/* We use scissors instead of exact view volume clipping,
* so they're always enabled.
*/
- BEGIN_NVC0(push, NVC0_3D(SCISSOR_ENABLE(0)), 3);
- PUSH_DATA (push, 1);
- PUSH_DATA (push, 8192 << 16);
- PUSH_DATA (push, 8192 << 16);
+ for (i = 0; i < NVC0_MAX_VIEWPORTS; i++) {
+ BEGIN_NVC0(push, NVC0_3D(SCISSOR_ENABLE(i)), 3);
+ PUSH_DATA (push, 1);
+ PUSH_DATA (push, 8192 << 16);
+ PUSH_DATA (push, 8192 << 16);
+ }
#define MK_MACRO(m, n) i = nvc0_graph_set_macro(screen, m, i, sizeof(n), n);
diff --git a/src/gallium/drivers/nouveau/nvc0/nvc0_screen.h
b/src/gallium/drivers/nouveau/nvc0/nvc0_screen.h
index c58add5..4802057 100644
--- a/src/gallium/drivers/nouveau/nvc0/nvc0_screen.h
+++ b/src/gallium/drivers/nouveau/nvc0/nvc0_screen.h
@@ -20,6 +20,9 @@
#define NVC0_MAX_SURFACE_SLOTS 16
+#define NVC0_MAX_VIEWPORTS 16
+
+
struct nvc0_context;
struct nvc0_blitter;
diff --git a/src/gallium/drivers/nouveau/nvc0/nvc0_state.c
b/src/gallium/drivers/nouveau/nvc0/nvc0_state.c
index 27e5cd8..c92aaac 100644
--- a/src/gallium/drivers/nouveau/nvc0/nvc0_state.c
+++ b/src/gallium/drivers/nouveau/nvc0/nvc0_state.c
@@ -909,10 +909,17 @@ nvc0_set_scissor_states(struct pipe_context *pipe,
unsigned num_scissors,
const struct pipe_scissor_state *scissor)
{
-struct nvc0_context *nvc0 = nvc0_context(pipe);
+ struct nvc0_context *nvc0 = nvc0_context(pipe);
+ int i;
-nvc0->scissor = *scissor;
-nvc0->dirty |= NVC0_NEW_SCISSOR;
+ assert(start_slot + num_scissors <= NVC0_MAX_VIEWPORTS);
+ for (i = 0; i < num_scissors; i++) {
+ if (!memcmp(&nvc0->scissors[start_slot + i], &scissor[i],
sizeof(*scissor)))
+ continue;
+ nvc0->scissors[start_slot + i] = scissor[i];
+ nvc0->scissors_dirty |= 1 << (start_slot + i);
[Mesa-dev] [PATCH 3/3] nv50/ir: Remove NV50_SEMANTIC_VIEWPORTINDEX and its last consumer
We use TGSI_SEMANTIC_VIEWPORT_INDEX for nvc0 now as well. Signed-off-by: Tobias Klausmann --- src/gallium/drivers/nouveau/codegen/nv50_ir_driver.h| 1 - src/gallium/drivers/nouveau/codegen/nv50_ir_target_nv50.cpp | 1 - 2 files changed, 2 deletions(-) diff --git a/src/gallium/drivers/nouveau/codegen/nv50_ir_driver.h b/src/gallium/drivers/nouveau/codegen/nv50_ir_driver.h index f829aac..c885c8c 100644 --- a/src/gallium/drivers/nouveau/codegen/nv50_ir_driver.h +++ b/src/gallium/drivers/nouveau/codegen/nv50_ir_driver.h @@ -70,7 +70,6 @@ struct nv50_ir_varying #endif #define NV50_SEMANTIC_CLIPDISTANCE (TGSI_SEMANTIC_COUNT + 0) -#define NV50_SEMANTIC_VIEWPORTINDEX (TGSI_SEMANTIC_COUNT + 4) #define NV50_SEMANTIC_TESSFACTOR(TGSI_SEMANTIC_COUNT + 7) #define NV50_SEMANTIC_TESSCOORD (TGSI_SEMANTIC_COUNT + 8) #define NV50_SEMANTIC_COUNT (TGSI_SEMANTIC_COUNT + 10) diff --git a/src/gallium/drivers/nouveau/codegen/nv50_ir_target_nv50.cpp b/src/gallium/drivers/nouveau/codegen/nv50_ir_target_nv50.cpp index abadc7f..7e314aa 100644 --- a/src/gallium/drivers/nouveau/codegen/nv50_ir_target_nv50.cpp +++ b/src/gallium/drivers/nouveau/codegen/nv50_ir_target_nv50.cpp @@ -538,7 +538,6 @@ recordLocation(uint16_t *locs, uint8_t *masks, case TGSI_SEMANTIC_VERTEXID: locs[SV_VERTEX_ID] = addr; break; case TGSI_SEMANTIC_PRIMID: locs[SV_PRIMITIVE_ID] = addr; break; case TGSI_SEMANTIC_LAYER: locs[SV_LAYER] = addr; break; - case NV50_SEMANTIC_VIEWPORTINDEX: locs[SV_VIEWPORT_INDEX] = addr; break; default: break; } -- 1.8.4.5 ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-dev
[Mesa-dev] [PATCH 0/3] ARB_viewport_array for nvc0
This patch-series implements the ARB_viewport_array for nvc0 and does
a little house-cleanig afterwords.
Tobias Klausmann (3):
nvc0: implement multiple viewports/scissors, enable ARB_viewport_array
nvc0: mark scissor in nvc0_clear_{}
nv50/ir: Remove NV50_SEMANTIC_VIEWPORTINDEX and its last consumer
.../drivers/nouveau/codegen/nv50_ir_driver.h | 1 -
.../nouveau/codegen/nv50_ir_target_nv50.cpp| 1 -
src/gallium/drivers/nouveau/nvc0/nvc0_context.h| 7 +-
src/gallium/drivers/nouveau/nvc0/nvc0_program.c| 2 +-
src/gallium/drivers/nouveau/nvc0/nvc0_screen.c | 20 ++--
src/gallium/drivers/nouveau/nvc0/nvc0_screen.h | 3 +
src/gallium/drivers/nouveau/nvc0/nvc0_state.c | 27 -
.../drivers/nouveau/nvc0/nvc0_state_validate.c | 121 +
src/gallium/drivers/nouveau/nvc0/nvc0_surface.c| 3 +
9 files changed, 120 insertions(+), 65 deletions(-)
--
1.8.4.5
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Re: [Mesa-dev] [PATCH 2/3] nvc0: mark scissor in nvc0_clear_{}
On Sat, Jun 14, 2014 at 10:41 AM, Tobias Klausmann wrote: > Signed-off-by: Tobias Klausmann > --- > src/gallium/drivers/nouveau/nvc0/nvc0_surface.c | 3 +++ > 1 file changed, 3 insertions(+) > > diff --git a/src/gallium/drivers/nouveau/nvc0/nvc0_surface.c > b/src/gallium/drivers/nouveau/nvc0/nvc0_surface.c > index c28ec6d..72227b8 100644 > --- a/src/gallium/drivers/nouveau/nvc0/nvc0_surface.c > +++ b/src/gallium/drivers/nouveau/nvc0/nvc0_surface.c > @@ -298,6 +298,7 @@ nvc0_clear_render_target(struct pipe_context *pipe, > BEGIN_NVC0(push, NVC0_3D(SCREEN_SCISSOR_HORIZ), 2); > PUSH_DATA (push, ( width << 16) | dstx); > PUSH_DATA (push, (height << 16) | dsty); > + nvc0->scissors_dirty |= 1; Can you explain why these changes are needed? You don't modify the scissor here (only the screen scissor)... > > BEGIN_NVC0(push, NVC0_3D(RT_CONTROL), 1); > PUSH_DATA (push, 1); > @@ -447,6 +448,7 @@ nvc0_clear_buffer(struct pipe_context *pipe, > BEGIN_NVC0(push, NVC0_3D(SCREEN_SCISSOR_HORIZ), 2); > PUSH_DATA (push, width << 16); > PUSH_DATA (push, height << 16); > + nvc0->scissors_dirty |= 1; > > IMMED_NVC0(push, NVC0_3D(RT_CONTROL), 1); > > @@ -521,6 +523,7 @@ nvc0_clear_depth_stencil(struct pipe_context *pipe, > BEGIN_NVC0(push, NVC0_3D(SCREEN_SCISSOR_HORIZ), 2); > PUSH_DATA (push, ( width << 16) | dstx); > PUSH_DATA (push, (height << 16) | dsty); > + nvc0->scissors_dirty |= 1; > > BEGIN_NVC0(push, NVC0_3D(ZETA_ADDRESS_HIGH), 5); > PUSH_DATAh(push, mt->base.address + sf->offset); > -- > 1.8.4.5 > ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-dev
Re: [Mesa-dev] [PATCH 3/3] nv50/ir: Remove NV50_SEMANTIC_VIEWPORTINDEX and its last consumer
On Sat, Jun 14, 2014 at 10:41 AM, Tobias Klausmann wrote: > We use TGSI_SEMANTIC_VIEWPORT_INDEX for nvc0 now as well. > > Signed-off-by: Tobias Klausmann > --- > src/gallium/drivers/nouveau/codegen/nv50_ir_driver.h| 1 - > src/gallium/drivers/nouveau/codegen/nv50_ir_target_nv50.cpp | 1 - > 2 files changed, 2 deletions(-) > > diff --git a/src/gallium/drivers/nouveau/codegen/nv50_ir_driver.h > b/src/gallium/drivers/nouveau/codegen/nv50_ir_driver.h > index f829aac..c885c8c 100644 > --- a/src/gallium/drivers/nouveau/codegen/nv50_ir_driver.h > +++ b/src/gallium/drivers/nouveau/codegen/nv50_ir_driver.h > @@ -70,7 +70,6 @@ struct nv50_ir_varying > #endif > > #define NV50_SEMANTIC_CLIPDISTANCE (TGSI_SEMANTIC_COUNT + 0) > -#define NV50_SEMANTIC_VIEWPORTINDEX (TGSI_SEMANTIC_COUNT + 4) > #define NV50_SEMANTIC_TESSFACTOR(TGSI_SEMANTIC_COUNT + 7) > #define NV50_SEMANTIC_TESSCOORD (TGSI_SEMANTIC_COUNT + 8) > #define NV50_SEMANTIC_COUNT (TGSI_SEMANTIC_COUNT + 10) > diff --git a/src/gallium/drivers/nouveau/codegen/nv50_ir_target_nv50.cpp > b/src/gallium/drivers/nouveau/codegen/nv50_ir_target_nv50.cpp > index abadc7f..7e314aa 100644 > --- a/src/gallium/drivers/nouveau/codegen/nv50_ir_target_nv50.cpp > +++ b/src/gallium/drivers/nouveau/codegen/nv50_ir_target_nv50.cpp > @@ -538,7 +538,6 @@ recordLocation(uint16_t *locs, uint8_t *masks, > case TGSI_SEMANTIC_VERTEXID: locs[SV_VERTEX_ID] = addr; break; > case TGSI_SEMANTIC_PRIMID: locs[SV_PRIMITIVE_ID] = addr; break; > case TGSI_SEMANTIC_LAYER: locs[SV_LAYER] = addr; break; > - case NV50_SEMANTIC_VIEWPORTINDEX: locs[SV_VIEWPORT_INDEX] = addr; break; I know this goes against what I said earlier, but actually do you mind flipping this over to TGSI_SEMANTIC_VIEWPORT_INDEX -- I suspect when ARB_fragment_layer_viewport is implemented, layer/viewport might be system values in the fragment shader. -ilia ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-dev
Re: [Mesa-dev] [PATCH 1/3] nvc0: implement multiple viewports/scissors, enable ARB_viewport_array
On Sat, Jun 14, 2014 at 10:41 AM, Tobias Klausmann
wrote:
> Signed-off-by: Tobias Klausmann
> ---
> src/gallium/drivers/nouveau/nvc0/nvc0_context.h| 7 +-
> src/gallium/drivers/nouveau/nvc0/nvc0_program.c| 2 +-
> src/gallium/drivers/nouveau/nvc0/nvc0_screen.c | 20 ++--
> src/gallium/drivers/nouveau/nvc0/nvc0_screen.h | 3 +
> src/gallium/drivers/nouveau/nvc0/nvc0_state.c | 27 -
> .../drivers/nouveau/nvc0/nvc0_state_validate.c | 121
> +
> 6 files changed, 117 insertions(+), 63 deletions(-)
>
> diff --git a/src/gallium/drivers/nouveau/nvc0/nvc0_context.h
> b/src/gallium/drivers/nouveau/nvc0/nvc0_context.h
> index 76416a0..674dd3c 100644
> --- a/src/gallium/drivers/nouveau/nvc0/nvc0_context.h
> +++ b/src/gallium/drivers/nouveau/nvc0/nvc0_context.h
> @@ -178,8 +178,11 @@ struct nvc0_context {
> struct pipe_blend_color blend_colour;
> struct pipe_stencil_ref stencil_ref;
> struct pipe_poly_stipple stipple;
> - struct pipe_scissor_state scissor;
> - struct pipe_viewport_state viewport;
> +
> + struct pipe_scissor_state scissors[NVC0_MAX_VIEWPORTS];
> + unsigned scissors_dirty;
> + struct pipe_viewport_state viewports[NVC0_MAX_VIEWPORTS];
> + unsigned viewports_dirty;
> struct pipe_clip_state clip;
>
> unsigned sample_mask;
> diff --git a/src/gallium/drivers/nouveau/nvc0/nvc0_program.c
> b/src/gallium/drivers/nouveau/nvc0/nvc0_program.c
> index 1c82a9a..667fbc8 100644
> --- a/src/gallium/drivers/nouveau/nvc0/nvc0_program.c
> +++ b/src/gallium/drivers/nouveau/nvc0/nvc0_program.c
> @@ -64,7 +64,7 @@ nvc0_shader_output_address(unsigned sn, unsigned si,
> unsigned ubase)
> case NV50_SEMANTIC_TESSFACTOR:return 0x000 + si * 0x4;
> case TGSI_SEMANTIC_PRIMID:return 0x060;
> case TGSI_SEMANTIC_LAYER: return 0x064;
> - case NV50_SEMANTIC_VIEWPORTINDEX: return 0x068;
> + case TGSI_SEMANTIC_VIEWPORT_INDEX:return 0x068;
> case TGSI_SEMANTIC_PSIZE: return 0x06c;
> case TGSI_SEMANTIC_POSITION: return 0x070;
> case TGSI_SEMANTIC_GENERIC: return ubase + si * 0x10;
> diff --git a/src/gallium/drivers/nouveau/nvc0/nvc0_screen.c
> b/src/gallium/drivers/nouveau/nvc0/nvc0_screen.c
> index 3e6b011..3fdb6ae 100644
> --- a/src/gallium/drivers/nouveau/nvc0/nvc0_screen.c
> +++ b/src/gallium/drivers/nouveau/nvc0/nvc0_screen.c
> @@ -183,7 +183,7 @@ nvc0_screen_get_param(struct pipe_screen *pscreen, enum
> pipe_cap param)
> case PIPE_CAP_FAKE_SW_MSAA:
>return 0;
> case PIPE_CAP_MAX_VIEWPORTS:
> - return 1;
> + return NVC0_MAX_VIEWPORTS;
> case PIPE_CAP_TEXTURE_QUERY_LOD:
> case PIPE_CAP_SAMPLE_SHADING:
> case PIPE_CAP_TEXTURE_GATHER_OFFSETS:
> @@ -933,19 +933,23 @@ nvc0_screen_create(struct nouveau_device *dev)
>
> BEGIN_NVC0(push, NVC0_3D(VIEWPORT_TRANSFORM_EN), 1);
> PUSH_DATA (push, 1);
> - BEGIN_NVC0(push, NVC0_3D(DEPTH_RANGE_NEAR(0)), 2);
> - PUSH_DATAf(push, 0.0f);
> - PUSH_DATAf(push, 1.0f);
> + for (i = 0; i < NVC0_MAX_VIEWPORTS; i++) {
> + BEGIN_NVC0(push, NVC0_3D(DEPTH_RANGE_NEAR(i)), 2);
> + PUSH_DATAf(push, 0.0f);
> + PUSH_DATAf(push, 1.0f);
> + }
> BEGIN_NVC0(push, NVC0_3D(VIEW_VOLUME_CLIP_CTRL), 1);
> PUSH_DATA (push, NVC0_3D_VIEW_VOLUME_CLIP_CTRL_UNK1_UNK1);
>
> /* We use scissors instead of exact view volume clipping,
> * so they're always enabled.
> */
> - BEGIN_NVC0(push, NVC0_3D(SCISSOR_ENABLE(0)), 3);
> - PUSH_DATA (push, 1);
> - PUSH_DATA (push, 8192 << 16);
> - PUSH_DATA (push, 8192 << 16);
> + for (i = 0; i < NVC0_MAX_VIEWPORTS; i++) {
> + BEGIN_NVC0(push, NVC0_3D(SCISSOR_ENABLE(i)), 3);
> + PUSH_DATA (push, 1);
> + PUSH_DATA (push, 8192 << 16);
> + PUSH_DATA (push, 8192 << 16);
> + }
>
> #define MK_MACRO(m, n) i = nvc0_graph_set_macro(screen, m, i, sizeof(n), n);
>
> diff --git a/src/gallium/drivers/nouveau/nvc0/nvc0_screen.h
> b/src/gallium/drivers/nouveau/nvc0/nvc0_screen.h
> index c58add5..4802057 100644
> --- a/src/gallium/drivers/nouveau/nvc0/nvc0_screen.h
> +++ b/src/gallium/drivers/nouveau/nvc0/nvc0_screen.h
> @@ -20,6 +20,9 @@
>
> #define NVC0_MAX_SURFACE_SLOTS 16
>
> +#define NVC0_MAX_VIEWPORTS 16
> +
> +
> struct nvc0_context;
>
> struct nvc0_blitter;
> diff --git a/src/gallium/drivers/nouveau/nvc0/nvc0_state.c
> b/src/gallium/drivers/nouveau/nvc0/nvc0_state.c
> index 27e5cd8..c92aaac 100644
> --- a/src/gallium/drivers/nouveau/nvc0/nvc0_state.c
> +++ b/src/gallium/drivers/nouveau/nvc0/nvc0_state.c
> @@ -909,10 +909,17 @@ nvc0_set_scissor_states(struct pipe_context *pipe,
> unsigned num_scissors,
> const struct pipe_scissor_state *scissor)
> {
> -struct nvc0_context *nvc0 = nvc0_context(pipe);
> + struct nvc0_context *nvc0 = nvc0_context(pipe);
> + int i;
>
> -nvc0->scissor = *scissor;
> -nvc0->dirty |= NVC0_NEW_SCISSOR;
> + assert(start_slot + num_
Re: [Mesa-dev] [PATCH 0/3] ARB_viewport_array for nvc0
Review comments sent; you should also add a separate patch that marks
off ARB_viewport_array in GL3.txt and adds it to relnotes for 10.3.
On Sat, Jun 14, 2014 at 10:41 AM, Tobias Klausmann
wrote:
> This patch-series implements the ARB_viewport_array for nvc0 and does
> a little house-cleanig afterwords.
>
> Tobias Klausmann (3):
> nvc0: implement multiple viewports/scissors, enable ARB_viewport_array
> nvc0: mark scissor in nvc0_clear_{}
> nv50/ir: Remove NV50_SEMANTIC_VIEWPORTINDEX and its last consumer
>
> .../drivers/nouveau/codegen/nv50_ir_driver.h | 1 -
> .../nouveau/codegen/nv50_ir_target_nv50.cpp| 1 -
> src/gallium/drivers/nouveau/nvc0/nvc0_context.h| 7 +-
> src/gallium/drivers/nouveau/nvc0/nvc0_program.c| 2 +-
> src/gallium/drivers/nouveau/nvc0/nvc0_screen.c | 20 ++--
> src/gallium/drivers/nouveau/nvc0/nvc0_screen.h | 3 +
> src/gallium/drivers/nouveau/nvc0/nvc0_state.c | 27 -
> .../drivers/nouveau/nvc0/nvc0_state_validate.c | 121
> +
> src/gallium/drivers/nouveau/nvc0/nvc0_surface.c| 3 +
> 9 files changed, 120 insertions(+), 65 deletions(-)
>
> --
> 1.8.4.5
>
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Re: [Mesa-dev] [PATCH 1/3] i965: Add missing MOCS setup for 3DSTATE_INDEX_BUFFER on Broadwell.
Series Reviewed-by: Matt Turner ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-dev
Re: [Mesa-dev] [PATCH 2/2] i965/vec4: Fix dead code elimination for VGRFs of size > 1.
On Sat, Jun 14, 2014 at 4:10 AM, Kenneth Graunke wrote: > When faced with code such as: > > mov vgrf31.0:UD, 960D > mov vgrf31.1:UD, vgrf30.:UD > > The dead code eliminator brilliantly decided that the second instruction > was writing to the same register as the first one, so the first one > could be eliminated. Except that they're not the same register at all. I'd appreciate dropping the mockery. Both are Reviewed-by: Matt Turner ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-dev
[Mesa-dev] [Bug 79949] [DRI3] GTK+ Programs Not Updating Correctly
https://bugs.freedesktop.org/show_bug.cgi?id=79949 --- Comment #5 from Joseph Booker --- As an update, this also happens with mesa 10.2.1 with the following configure options: --enable-dri --enable-glx --enable-shared-glapi --enable-texture-float --disable-debug --enable-dri3 --enable-egl --enable-gbm --disable-gles1 --enable-gles2 --enable-glx-tls --enable-osmesa --enable-asm --enable-llvm-shared-libs --with-dri-drivers=,swrast,i965,radeon,r200 --with-gallium-drivers=,swrast,radeonsi,r300,r600 --with-egl-platforms=x11,wayland,drm --enable-gallium-llvm --enable-openvg --enable-gallium-egl --disable-omx --enable-r600-llvm-compiler --enable-vdpau --enable-xa --enable-xvmc --enable-opencl Is there anything like Android's "Show GPU view updates' to see if xorg/mesa/? is getting notified to redraw that part of the screen ? (If that information will help) -- You are receiving this mail because: You are the assignee for the bug. ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-dev
Re: [Mesa-dev] [PATCH 11/19] i965: Convert brw_eu_compact.c to the new brw_inst API.
On Friday, June 13, 2014 11:14:12 PM Matt Turner wrote:
> ---
> src/mesa/drivers/dri/i965/brw_eu_compact.c | 269
+
> 1 file changed, 161 insertions(+), 108 deletions(-)
>
> diff --git a/src/mesa/drivers/dri/i965/brw_eu_compact.c
b/src/mesa/drivers/dri/i965/brw_eu_compact.c
> index 0ae3f2d..7e08d1d 100644
> --- a/src/mesa/drivers/dri/i965/brw_eu_compact.c
> +++ b/src/mesa/drivers/dri/i965/brw_eu_compact.c
> @@ -331,16 +331,25 @@ set_control_index(struct brw_context *brw,
>struct brw_compact_instruction *dst,
>struct brw_instruction *src)
> {
> - uint32_t *src_u32 = (uint32_t *)src;
> - uint32_t uncompacted = 0;
> -
> - uncompacted |= ((src_u32[0] >> 8) & 0x) << 0;
> - uncompacted |= ((src_u32[0] >> 31) & 0x1) << 16;
> - /* On gen7, the flag register number gets integrated into the control
> -* index.
> + uint32_t uncompacted = /* 17b/SNB; 19b/IVB+ */
> + (brw_inst_saturate(brw, src) << 16) | /* 1b */
> + (brw_inst_exec_size(brw, src) << 13) | /* 3b */
> + (brw_inst_pred_inv(brw, src) << 12) | /* 1b */
> + (brw_inst_pred_control(brw, src) << 8) | /* 4b */
> + (brw_inst_thread_control(brw, src) << 6) | /* 2b */
> + (brw_inst_qtr_control(brw, src)<< 4) | /* 2b */
> + (brw_inst_no_dd_check(brw, src)<< 3) | /* 1b */
> + (brw_inst_no_dd_clear(brw, src)<< 2) | /* 1b */
> + (brw_inst_mask_control(brw, src) << 1) | /* 1b */
> + (brw_inst_access_mode(brw, src)<< 0); /* 1b */
> +
> + /* On gen7, the flag register and subregister numbers are integrated
into
> +* the control index.
> */
> if (brw->gen >= 7)
> - uncompacted |= ((src_u32[2] >> 25) & 0x3) << 17;
> + uncompacted |=
> + (brw_inst_flag_reg_nr(brw, src)<< 18) | /* 1b */
> + (brw_inst_flag_subreg_nr(brw, src) << 17); /* 1b */
>
> for (int i = 0; i < 32; i++) {
>if (control_index_table[i] == uncompacted) {
> @@ -353,13 +362,19 @@ set_control_index(struct brw_context *brw,
> }
>
> static bool
> -set_datatype_index(struct brw_compact_instruction *dst,
> +set_datatype_index(struct brw_context *brw,
> + struct brw_compact_instruction *dst,
> struct brw_instruction *src)
> {
> - uint32_t uncompacted = 0;
> -
> - uncompacted |= src->bits1.ud & 0x7fff;
> - uncompacted |= (src->bits1.ud >> 29) << 15;
> + uint32_t uncompacted = /* 18b */
> + (brw_inst_dst_address_mode(brw, src) << 17) | /* 1b */
> + (brw_inst_dst_hstride(brw, src) << 15) | /* 2b */
> + (brw_inst_src1_reg_type(brw, src)<< 12) | /* 3b */
> + (brw_inst_src1_reg_file(brw, src)<< 10) | /* 2b */
> + (brw_inst_src0_reg_type(brw, src)<< 7) | /* 3b */
> + (brw_inst_src0_reg_file(brw, src)<< 5) | /* 2b */
> + (brw_inst_dst_reg_type(brw, src) << 2) | /* 3b */
> + (brw_inst_dst_reg_file(brw, src) << 0); /* 2b */
>
> for (int i = 0; i < 32; i++) {
>if (datatype_table[i] == uncompacted) {
> @@ -372,17 +387,17 @@ set_datatype_index(struct brw_compact_instruction
*dst,
> }
>
> static bool
> -set_subreg_index(struct brw_compact_instruction *dst,
> +set_subreg_index(struct brw_context *brw,
> + struct brw_compact_instruction *dst,
> struct brw_instruction *src,
> bool is_immediate)
> {
> - uint16_t uncompacted = 0;
> -
> - uncompacted |= src->bits1.da1.dest_subreg_nr << 0;
> - uncompacted |= src->bits2.da1.src0_subreg_nr << 5;
> + uint16_t uncompacted =/* 15b */
> + (brw_inst_dst_da1_subreg_nr(brw, src) << 0) | /* 5b */
> + (brw_inst_src0_da1_subreg_nr(brw, src) << 5); /* 5b */
>
> if (!is_immediate)
> - uncompacted |= src->bits3.da1.src1_subreg_nr << 10;
> + uncompacted |= brw_inst_src1_da1_subreg_nr(brw, src) << 10; /* 5b */
>
> for (int i = 0; i < 32; i++) {
>if (subreg_table[i] == uncompacted) {
> @@ -409,12 +424,18 @@ get_src_index(uint16_t uncompacted,
> }
>
> static bool
> -set_src0_index(struct brw_compact_instruction *dst,
> +set_src0_index(struct brw_context *brw,
> + struct brw_compact_instruction *dst,
> struct brw_instruction *src)
> {
> - uint16_t compacted, uncompacted = 0;
> -
> - uncompacted |= (src->bits2.ud >> 13) & 0xfff;
> + uint16_t compacted;
> + uint16_t uncompacted = /* 12b */
> + (brw_inst_src0_vstride(brw, src) << 8) | /* 4b */
> + (brw_inst_src0_width(brw, src)<< 5) | /* 3b */
> + (brw_inst_src0_hstride(brw, src) << 3) | /* 2b */
One thing that's a little funny here...we pull out hstride/width/vstride,
which makes sense for align1 mode...but presumably this function is also used
for align16 mode, where we instead have src0_da16
[Mesa-dev] [PATCH] i965/vec4: Use the sampler for pull constant loads on Broadwell.
We've used the LD sampler message for pull constant loads on earlier hardware for some time, and also were already using it for the FS on Broadwell. This patch makes us use it for Broadwell VS/GS as well. I believe that when I wrote this code in 2012, we still used the data port in some cases, and I somehow neglected to convert it while rebasing. Improves performance in GLBenchmark 2.7 Egypt by 416.978% +/- 2.25821% (n = 17). Many other applications should benefit similarly: this speeds up uniform array access in the VS, which is commonly used for skinning shaders, among other things. Signed-off-by: Kenneth Graunke --- src/mesa/drivers/dri/i965/gen8_vec4_generator.cpp | 16 1 file changed, 8 insertions(+), 8 deletions(-) No Piglit regressions. diff --git a/src/mesa/drivers/dri/i965/gen8_vec4_generator.cpp b/src/mesa/drivers/dri/i965/gen8_vec4_generator.cpp index 14070cd..82ea45a 100644 --- a/src/mesa/drivers/dri/i965/gen8_vec4_generator.cpp +++ b/src/mesa/drivers/dri/i965/gen8_vec4_generator.cpp @@ -444,14 +444,14 @@ gen8_vec4_generator::generate_pull_constant_load(vec4_instruction *inst, gen8_instruction *send = next_inst(BRW_OPCODE_SEND); gen8_set_dst(brw, send, dst); gen8_set_src0(brw, send, offset); - gen8_set_dp_message(brw, send, GEN7_SFID_DATAPORT_DATA_CACHE, - surf_index, - GEN6_DATAPORT_READ_MESSAGE_OWORD_DUAL_BLOCK_READ, - 0, /* message control */ - 1, /* mlen */ - 1, /* rlen */ - false, /* no header */ - false); /* EOT */ + gen8_set_sampler_message(brw, send, +surf_index, +0, /* The LD message ignores the sampler unit. */ +GEN5_SAMPLER_MESSAGE_SAMPLE_LD, +1, /* rlen */ +1, /* mlen */ +false, /* no header */ +BRW_SAMPLER_SIMD_MODE_SIMD4X2); brw_mark_surface_used(&prog_data->base, surf_index); } -- 1.9.1 ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-dev
[Mesa-dev] [Bug 80034] New: compile error eglGetSyncValuesCHROMIUM undeclared
https://bugs.freedesktop.org/show_bug.cgi?id=80034
Priority: medium
Bug ID: 80034
Assignee: mesa-dev@lists.freedesktop.org
Summary: compile error eglGetSyncValuesCHROMIUM undeclared
Severity: normal
Classification: Unclassified
OS: Linux (All)
Reporter: bug0xa...@hushmail.com
Hardware: x86-64 (AMD64)
Status: NEW
Version: git
Component: EGL
Product: Mesa
Created attachment 101063
--> https://bugs.freedesktop.org/attachment.cgi?id=101063&action=edit
mesa build log
mesa compile error:
eglapi.c:1097:48: error: 'eglGetSyncValuesCHROMIUM' undeclared (first use in
this function)
Here are my build flags:
export CONFFLAGS=" \
--enable-${LIBDIRSUFFIX}-bit \
--prefix=${XBUILD} \
--libdir=${XBUILD}/lib${LIBDIRSUFFIX} \
--exec-prefix=${XBUILD} \
--bindir=${XBUILD}/bin \
--sbindir=${XBUILD}/sbin \
--sysconfdir=${XBUILD}/etc \
--datadir=${XBUILD}/share \
--includedir=${XBUILD}/include \
--libexecdir=${XBUILD}/libexec \
--localstatedir=${XBUILD}/var \
--mandir=${XBUILD}/share/man \
--infodir=${XBUILD}/share/info \
--enable-xcb \
--with-kernel-source=/usr/src/linux \
--disable-intel \
--disable-nouveau \
--disable-vmwgfx \
--disable-nouveau-experimental-api \
--enable-xinput \
--silent \
--enable-silent-rules \
--disable-ipv6 \
--enable-egl \
--with-dri-drivers=radeon \
--disable-gallium-r300 \
--enable-glamor \
--with-egl-platforms=drm,x11 \
--sysconfdir=/etc \
--with-llvm-shared-libs\
--enable-gbm \
--enable-gallium-egl \
--enable-gallium-llvm \
--enable-gallium-gbm \
--enable-glx-tls \
--enable-texture-float\
--with-dri-driverdir=${XBUILD}/lib${LIBDIRSUFFIX}/xorg/modules/dri \
--with-dri-searchpath=${XBUILD}/lib${LIBDIRSUFFIX}/xorg/modules/dri,${XBUILD}/lib${LIBDIRSUFFIX}/dri
\
--enable-xa \
--enable-xorg \
--with-gallium-drivers=radeonsi \
--disable-systemd-logind \
--build=$ARCH-pc-linux \
--host=$ARCH-pc-linux \
--target=$ARCH-pc-linux"
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[Mesa-dev] [Bug 79949] [DRI3] GTK+ Programs Not Updating Correctly
https://bugs.freedesktop.org/show_bug.cgi?id=79949 Mike Lothian changed: What|Removed |Added CC||m...@fireburn.co.uk --- Comment #6 from Mike Lothian --- This is really noticeable when using icedtea web browser java plugin to remotely connect into work using Citrix Receiver -- You are receiving this mail because: You are the assignee for the bug. ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-dev
Re: [Mesa-dev] [PATCH] i965/vec4: Use the sampler for pull constant loads on Broadwell.
On Sat, Jun 14, 2014 at 12:58 PM, Kenneth Graunke wrote: > We've used the LD sampler message for pull constant loads on earlier > hardware for some time, and also were already using it for the FS on > Broadwell. This patch makes us use it for Broadwell VS/GS as well. > > I believe that when I wrote this code in 2012, we still used the data > port in some cases, and I somehow neglected to convert it while > rebasing. > > Improves performance in GLBenchmark 2.7 Egypt by 416.978% +/- 2.25821% > (n = 17). Many other applications should benefit similarly: this speeds > up uniform array access in the VS, which is commonly used for skinning > shaders, among other things. Wow. Reviewed-by: Matt Turner ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-dev
[Mesa-dev] [Bug 80034] compile error eglGetSyncValuesCHROMIUM undeclared
https://bugs.freedesktop.org/show_bug.cgi?id=80034
--- Comment #1 from Emil Velikov ---
(In reply to comment #0)
> Created attachment 101063 [details]
> mesa build log
>
Which version of mesa is this ? Is this a regression ?
> mesa compile error:
>
> eglapi.c:1097:48: error: 'eglGetSyncValuesCHROMIUM' undeclared (first use in
> this function)
>
Strange...
The symbols is defined in
include/EGL/eglextchromium.h
with is included via (at least)
include/EGL/eglext.h
src/egl/main/egltypedefs.h
src/egl/main/eglcontext.h
src/egl/main/eglapi.c
I'm assuming that you have some thing that is messing with CFLAGS.
> Here are my build flags:
>
...
> --prefix=${XBUILD} \
> --libdir=${XBUILD}/lib${LIBDIRSUFFIX} \
> --exec-prefix=${XBUILD} \
> --bindir=${XBUILD}/bin \
> --sbindir=${XBUILD}/sbin \
> --sysconfdir=${XBUILD}/etc \
> --datadir=${XBUILD}/share \
> --includedir=${XBUILD}/include \
> --libexecdir=${XBUILD}/libexec \
> --localstatedir=${XBUILD}/var \
> --mandir=${XBUILD}/share/man \
> --infodir=${XBUILD}/share/info \
IMHO from the above flags you should only need the prefix and libdir
> --sysconfdir=/etc \
Missing ${XBUILD} ? Might be worth dropping this one as well.
> --disable-intel \
> --disable-nouveau \
> --disable-vmwgfx \
> --disable-nouveau-experimental-api \
These seem like libdrm configure flags. Not sure what are they doing here.
> --enable-glamor \
> --enable-xcb \
> --with-kernel-source=/usr/src/linux \
> --enable-xinput \
> --disable-ipv6 \
> --disable-systemd-logind \
What are these doing here ?
> --build=$ARCH-pc-linux \
> --host=$ARCH-pc-linux \
> --target=$ARCH-pc-linux"
Please avoid setting these if they are identical. IIRC there was a bug
(automake/autoconf) that was incorrectly setting the cross-compile variable.
If nuking the above does not resolve the problem I would recommend explicitly
purging CFLAGS and CPPFLAGS before calling the configure, and bisecting the
options to see which one is causing the issue.
Cheers
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Re: [Mesa-dev] [PATCH] i965/vec4: Use the sampler for pull constant loads on Broadwell.
Reviewed-by: Jordan Justen On Sat, Jun 14, 2014 at 12:58 PM, Kenneth Graunke wrote: > We've used the LD sampler message for pull constant loads on earlier > hardware for some time, and also were already using it for the FS on > Broadwell. This patch makes us use it for Broadwell VS/GS as well. > > I believe that when I wrote this code in 2012, we still used the data > port in some cases, and I somehow neglected to convert it while > rebasing. > > Improves performance in GLBenchmark 2.7 Egypt by 416.978% +/- 2.25821% > (n = 17). Many other applications should benefit similarly: this speeds > up uniform array access in the VS, which is commonly used for skinning > shaders, among other things. > > Signed-off-by: Kenneth Graunke > --- > src/mesa/drivers/dri/i965/gen8_vec4_generator.cpp | 16 > 1 file changed, 8 insertions(+), 8 deletions(-) > > No Piglit regressions. > > diff --git a/src/mesa/drivers/dri/i965/gen8_vec4_generator.cpp > b/src/mesa/drivers/dri/i965/gen8_vec4_generator.cpp > index 14070cd..82ea45a 100644 > --- a/src/mesa/drivers/dri/i965/gen8_vec4_generator.cpp > +++ b/src/mesa/drivers/dri/i965/gen8_vec4_generator.cpp > @@ -444,14 +444,14 @@ > gen8_vec4_generator::generate_pull_constant_load(vec4_instruction *inst, > gen8_instruction *send = next_inst(BRW_OPCODE_SEND); > gen8_set_dst(brw, send, dst); > gen8_set_src0(brw, send, offset); > - gen8_set_dp_message(brw, send, GEN7_SFID_DATAPORT_DATA_CACHE, > - surf_index, > - GEN6_DATAPORT_READ_MESSAGE_OWORD_DUAL_BLOCK_READ, > - 0, /* message control */ > - 1, /* mlen */ > - 1, /* rlen */ > - false, /* no header */ > - false); /* EOT */ > + gen8_set_sampler_message(brw, send, > +surf_index, > +0, /* The LD message ignores the sampler unit. */ > +GEN5_SAMPLER_MESSAGE_SAMPLE_LD, > +1, /* rlen */ > +1, /* mlen */ > +false, /* no header */ > +BRW_SAMPLER_SIMD_MODE_SIMD4X2); > > brw_mark_surface_used(&prog_data->base, surf_index); > } > -- > 1.9.1 > ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-dev
Re: [Mesa-dev] [PATCH 11/19] i965: Convert brw_eu_compact.c to the new brw_inst API.
On Sat, Jun 14, 2014 at 12:54 PM, Kenneth Graunke wrote: >> - uint16_t compacted, uncompacted = 0; >> - >> - uncompacted |= (src->bits2.ud >> 13) & 0xfff; >> + uint16_t compacted; >> + uint16_t uncompacted = /* 12b */ >> + (brw_inst_src0_vstride(brw, src) << 8) | /* 4b */ >> + (brw_inst_src0_width(brw, src)<< 5) | /* 3b */ >> + (brw_inst_src0_hstride(brw, src) << 3) | /* 2b */ > > One thing that's a little funny here...we pull out hstride/width/vstride, > which makes sense for align1 mode...but presumably this function is also used > for align16 mode, where we instead have src0_da16_swiz_x etc. > > But, it's the same bits, so this ought to work. I'm not objecting, it's > just...a little funny at first glance. > > I don't think it's worth adding conditionals, but would it be worth adding a > comment saying basically /* this also works for align16 mode because they > share the same bits */? > > Whatever you decide is fine. This patch is: > Reviewed-by: Kenneth Graunke I'm glad you mentioned this. I think I want to modify these to use brw_inst_bits/brw_inst_set_bits instead. I know they're different on Broadwell, so we'll have slightly more C, but I think the benefits outweight that. The SandyBridge docs give only the bitfields, while the IVB/HSW docs give the bitfields and a useless list of out of order field names (that regularly alias each other). So you have to rely on the bitfield definitions anyway to make sense of it. Also, the fields corresponding to the indicies are typically contiguous. For instance, 16 of the 17 bits of SNB's control index table are consecutive, so using brw_inst_bits lets us grab those directly, without confusing the compiler into generating garbage by extracting them separately, shifting, and oring them back together. text databssdechex filename 4118 0 32 4150 1036 brw_eu_compact.obefore conversion 6774 0 32 6806 1a96 brw_eu_compact.oafter conversion (this patch) 4662 0 32 4694 1256 brw_eu_compact.oafter bitfield patch There's evidently some overhead in the new approach. I've got an idea how to fix it that I'm not sure is worth implementing, but I think using the bit getter and setter is definitely the right way to go here. ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-dev
[Mesa-dev] [PATCH] glsl: Treat an interface block specifier as a level of struct nesting
Fixes the piglit test: spec/glsl-1.50/compiler/interface-blocks-structs-defined-within-block-instanced.vert Signed-off-by: Chris Forbes --- src/glsl/ast_to_hir.cpp | 8 1 file changed, 8 insertions(+) diff --git a/src/glsl/ast_to_hir.cpp b/src/glsl/ast_to_hir.cpp index 8facf1b..ee68afc 100644 --- a/src/glsl/ast_to_hir.cpp +++ b/src/glsl/ast_to_hir.cpp @@ -5210,6 +5210,12 @@ ast_interface_block::hir(exec_list *instructions, bool block_row_major = this->layout.flags.q.row_major; exec_list declared_variables; glsl_struct_field *fields; + + /* Treat an interface block as one level of nesting, so that embedded struct +* specifiers will be disallowed. +*/ + state->struct_specifier_depth++; + unsigned int num_variables = ast_process_structure_or_interface_block(&declared_variables, state, @@ -5221,6 +5227,8 @@ ast_interface_block::hir(exec_list *instructions, redeclaring_per_vertex, var_mode); + state->struct_specifier_depth--; + if (!redeclaring_per_vertex) validate_identifier(this->block_name, loc, state); -- 2.0.0 ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-dev
Re: [Mesa-dev] [PATCH 11/19] i965: Convert brw_eu_compact.c to the new brw_inst API.
On Saturday, June 14, 2014 05:41:37 PM Matt Turner wrote: > On Sat, Jun 14, 2014 at 12:54 PM, Kenneth Graunke wrote: > >> - uint16_t compacted, uncompacted = 0; > >> - > >> - uncompacted |= (src->bits2.ud >> 13) & 0xfff; > >> + uint16_t compacted; > >> + uint16_t uncompacted = /* 12b */ > >> + (brw_inst_src0_vstride(brw, src) << 8) | /* 4b */ > >> + (brw_inst_src0_width(brw, src)<< 5) | /* 3b */ > >> + (brw_inst_src0_hstride(brw, src) << 3) | /* 2b */ > > > > One thing that's a little funny here...we pull out hstride/width/vstride, > > which makes sense for align1 mode...but presumably this function is also used > > for align16 mode, where we instead have src0_da16_swiz_x etc. > > > > But, it's the same bits, so this ought to work. I'm not objecting, it's > > just...a little funny at first glance. > > > > I don't think it's worth adding conditionals, but would it be worth adding a > > comment saying basically /* this also works for align16 mode because they > > share the same bits */? > > > > Whatever you decide is fine. This patch is: > > Reviewed-by: Kenneth Graunke > > I'm glad you mentioned this. I think I want to modify these to use > brw_inst_bits/brw_inst_set_bits instead. I know they're different on > Broadwell, so we'll have slightly more C, but I think the benefits > outweight that. Yeah, that seems like a good plan to me. --Ken signature.asc Description: This is a digitally signed message part. ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-dev
Re: [Mesa-dev] [PATCH] i965/vec4: Use the sampler for pull constant loads on Broadwell.
On Sat, Jun 14, 2014 at 12:58:03PM -0700, Kenneth Graunke wrote: > We've used the LD sampler message for pull constant loads on earlier > hardware for some time, and also were already using it for the FS on > Broadwell. This patch makes us use it for Broadwell VS/GS as well. > > I believe that when I wrote this code in 2012, we still used the data > port in some cases, and I somehow neglected to convert it while > rebasing. > > Improves performance in GLBenchmark 2.7 Egypt by 416.978% +/- 2.25821% > (n = 17). Many other applications should benefit similarly: this speeds > up uniform array access in the VS, which is commonly used for skinning > shaders, among other things. > > Signed-off-by: Kenneth Graunke My wins weren't quite so massive (I believe I have a slower part than you): 143.064% +/- 0.955119% Nevertheless, results confirmed. Excellent work, Ken! Tested-by: Ben Widawsky -- Ben Widawsky, Intel Open Source Technology Center ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-dev
[Mesa-dev] [PATCH] glsl: Fix clang mismatched-tags warnings with glsl_type.
Fix clang mismatched-tags warnings introduced with commit
4f5445a45d3ed02e00a061b10c943c0b079c6020.
./glsl_symbol_table.h:37:1: warning: class 'glsl_type' was previously declared
as a struct [-Wmismatched-tags]
class glsl_type;
^
./glsl_types.h:86:8: note: previous use is here
struct glsl_type {
^
./glsl_symbol_table.h:37:1: note: did you mean struct here?
class glsl_type;
^
Signed-off-by: Vinson Lee
---
src/glsl/glsl_symbol_table.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/src/glsl/glsl_symbol_table.h b/src/glsl/glsl_symbol_table.h
index 39b84e4..2528264 100644
--- a/src/glsl/glsl_symbol_table.h
+++ b/src/glsl/glsl_symbol_table.h
@@ -34,7 +34,7 @@ extern "C" {
#include "ir.h"
class symbol_table_entry;
-class glsl_type;
+struct glsl_type;
/**
* Facade class for _mesa_symbol_table
--
1.9.2
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