Re: [Mesa-dev] [PATCH 16/20] radeonsi: add FMASK texture binding slots and resource setup
Am 09.08.2013 20:06, schrieb Marek Olšák: [SNIP] What if I kept the current emission code, and only allocated a new buffer at the end of the emit function, copied all descriptors to it using CP_DMA or COPY_DATA, and pointed SPI_SHADER_USER_DATA to it. The buffer where the descriptors are updated using WRITE_DATA would act as a staging buffer only and shaders would always read from the fresh new copy. Does that sound good to you? That sounds like the solution with multiple buffers I already suggest, but I would rather use some RCU approach to it. Basically we just have to handle it like the context based resources on earlier asics. So to me a proper solution should look something like this: We allocate a ring of (let's say) 16 slots for descriptor arrays, fill the first slot with WRITE_DATA packets and then use it in a draw command. As soon as any of the descriptors is about to change we copy it's content to the next slot, let the SPI_SHADER_USER_DATA point to it, make the necessary updates using WRITE_DATA and then use it in a draw command. This repeats over and over again, all we need to make sure is that we have enough slots in the ring to be sure that we never override descriptors when they are still in use, but I'm pretty sure that we should be on the save side with 16 or so. We can even prepare the commands for the switch from one slot to the next only once and then use it for the whole lifetime of the driver. Christian. ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-dev
[Mesa-dev] [PATCH 1/4] nouveau: fix number of surfaces in video buffer, use defines
Signed-off-by: Ilia Mirkin
---
The pipe_surface miscount caused issues for my (failed) attempt at getting
vdpau to work with pmpeg.
src/gallium/drivers/nouveau/nouveau_video.h | 8
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/src/gallium/drivers/nouveau/nouveau_video.h
b/src/gallium/drivers/nouveau/nouveau_video.h
index 1d6ced0..be53758 100644
--- a/src/gallium/drivers/nouveau/nouveau_video.h
+++ b/src/gallium/drivers/nouveau/nouveau_video.h
@@ -10,10 +10,10 @@
struct nouveau_video_buffer {
struct pipe_video_buffer base;
unsigned num_planes;
- struct pipe_resource *resources[3];
- struct pipe_sampler_view *sampler_view_planes[3];
- struct pipe_sampler_view *sampler_view_components[3];
- struct pipe_surface *surfaces[3];
+ struct pipe_resource *resources[VL_NUM_COMPONENTS];
+ struct pipe_sampler_view *sampler_view_planes[VL_NUM_COMPONENTS];
+ struct pipe_sampler_view *sampler_view_components[VL_NUM_COMPONENTS];
+ struct pipe_surface *surfaces[VL_NUM_COMPONENTS * 2];
};
struct nouveau_decoder {
--
1.8.1.5
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[Mesa-dev] [PATCH 3/4] nv30: hook up PMPEG support via nouveau_video, enables XvMC to work
Force the format to be the reasonable format that doesn't require an
inverse z-scan.
Signed-off-by: Ilia Mirkin
---
Tested this on both nv44 and nv96, and it works, all at the same time. Without
the 0x72 command, they default to different scan orders. Putting the 0x72
command only at the beginning (in nouveau_vpe_init) seemed to cause pmpeg to
hang.
src/gallium/drivers/nouveau/nouveau_video.c | 27 ---
src/gallium/drivers/nv30/nv30_context.c | 2 ++
src/gallium/drivers/nv30/nv30_screen.c | 1 +
3 files changed, 15 insertions(+), 15 deletions(-)
diff --git a/src/gallium/drivers/nouveau/nouveau_video.c
b/src/gallium/drivers/nouveau/nouveau_video.c
index 2e7f9b1..cbe2477 100644
--- a/src/gallium/drivers/nouveau/nouveau_video.c
+++ b/src/gallium/drivers/nouveau/nouveau_video.c
@@ -108,21 +108,10 @@ nouveau_vpe_mb_dct_blocks(struct nouveau_decoder *dec,
const struct pipe_mpeg12_
short *db = mb->blocks;
for (cbb = 0x20; cbb > 0; cbb >>= 1) {
if (cbb & cbp) {
- static const int lookup[64] = {
- 0, 1, 8,16, 9, 2, 3,10,
-17,24,32,25,18,11, 4, 5,
-12,19,26,33,40,48,41,34,
-27,20,13, 6, 7,14,21,28,
-35,42,49,56,57,50,43,36,
-29,22,15,23,30,37,44,51,
-58,59,52,45,38,31,39,46,
-53,60,61,54,47,55,62,63
- };
- int i, j = 0, found = 0;
+ int i, found = 0;
for (i = 0; i < 64; ++i) {
-if (!db[lookup[i]]) { j += 2; continue; }
-dec->data[dec->data_pos++] = (db[lookup[i]] << 16) | j;
-j = 0;
+if (!db[i]) continue;
+dec->data[dec->data_pos++] = (db[i] << 16) | (i * 2);
found = 1;
}
if (found)
@@ -443,6 +432,11 @@ nouveau_decoder_decode_macroblock(struct
pipe_video_decoder *decoder,
dec->past = nouveau_decoder_surface_index(dec, desc->ref[0]);
if (nouveau_vpe_init(dec)) return;
+
+ /* initialize scan order */
+ nouveau_vpe_write(dec, 0x72c0);
+ nouveau_vpe_write(dec, dec->data_pos);
+
mb = (const struct pipe_mpeg12_macroblock *)pipe_mb;
for (i = 0; i < num_macroblocks; ++i, mb++) {
if (mb->macroblock_type & PIPE_MPEG12_MB_TYPE_INTRA) {
@@ -528,6 +522,8 @@ nouveau_create_decoder(struct pipe_context *context,
goto vl;
if (screen->device->chipset >= 0x98 && screen->device->chipset != 0xa0)
goto vl;
+ if (screen->device->chipset < 0x31 || screen->device->chipset == 0x35)
+ goto vl;
dec = CALLOC_STRUCT(nouveau_decoder);
if (!dec)
@@ -793,7 +789,8 @@ nouveau_video_buffer_create(struct pipe_context *pipe,
* and it only supports the NV12 format
*/
if (templat->buffer_format != PIPE_FORMAT_NV12 || getenv("XVMC_VL") ||
- (screen->device->chipset >= 0x98 && screen->device->chipset != 0xa0))
+ (screen->device->chipset >= 0x98 && screen->device->chipset != 0xa0) ||
+ screen->device->chipset < 0x31 || screen->device->chipset == 0x35)
return vl_video_buffer_create(pipe, templat);
assert(templat->chroma_format == PIPE_VIDEO_CHROMA_FORMAT_420);
diff --git a/src/gallium/drivers/nv30/nv30_context.c
b/src/gallium/drivers/nv30/nv30_context.c
index bd05042..e872c02 100644
--- a/src/gallium/drivers/nv30/nv30_context.c
+++ b/src/gallium/drivers/nv30/nv30_context.c
@@ -257,5 +257,7 @@ nv30_context_create(struct pipe_screen *pscreen, void *priv)
return NULL;
}
+ nouveau_context_init_vdec(&nv30->base);
+
return pipe;
}
diff --git a/src/gallium/drivers/nv30/nv30_screen.c
b/src/gallium/drivers/nv30/nv30_screen.c
index 3d55d6f..40e8b5f 100644
--- a/src/gallium/drivers/nv30/nv30_screen.c
+++ b/src/gallium/drivers/nv30/nv30_screen.c
@@ -377,6 +377,7 @@ nv30_screen_create(struct nouveau_device *dev)
pscreen->context_create = nv30_context_create;
pscreen->is_format_supported = nv30_screen_is_format_supported;
nv30_resource_screen_init(pscreen);
+ nouveau_screen_init_vdec(&screen->base);
screen->base.fence.emit = nv30_screen_fence_emit;
screen->base.fence.update = nv30_screen_fence_update;
--
1.8.1.5
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[Mesa-dev] [PATCH 2/4] nouveau: set buffer format of video buffer
Signed-off-by: Ilia Mirkin --- I don't think anything looks at this right now, but seems good to store. (Also ran into it with my vdpau attempt.) src/gallium/drivers/nouveau/nouveau_video.c | 1 + 1 file changed, 1 insertion(+) diff --git a/src/gallium/drivers/nouveau/nouveau_video.c b/src/gallium/drivers/nouveau/nouveau_video.c index 9357508..2e7f9b1 100644 --- a/src/gallium/drivers/nouveau/nouveau_video.c +++ b/src/gallium/drivers/nouveau/nouveau_video.c @@ -810,6 +810,7 @@ nouveau_video_buffer_create(struct pipe_context *pipe, buffer->base.get_sampler_view_components = nouveau_video_buffer_sampler_view_components; buffer->base.get_surfaces = nouveau_video_buffer_surfaces; buffer->base.chroma_format = templat->chroma_format; + buffer->base.buffer_format = templat->buffer_format; buffer->base.width = width; buffer->base.height = height; buffer->num_planes = 2; -- 1.8.1.5 ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-dev
[Mesa-dev] [PATCH 4/4] nv50: allow forcing PMPEG use, for ease of testing
This also allows people who don't want to install the binary blobs
required for VP2 to still get MPEG decoding.
Signed-off-by: Ilia Mirkin
---
src/gallium/drivers/nv50/nv50_context.c | 3 ++-
src/gallium/drivers/nv50/nv50_screen.c | 3 ++-
2 files changed, 4 insertions(+), 2 deletions(-)
diff --git a/src/gallium/drivers/nv50/nv50_context.c
b/src/gallium/drivers/nv50/nv50_context.c
index 79a0473..185d241 100644
--- a/src/gallium/drivers/nv50/nv50_context.c
+++ b/src/gallium/drivers/nv50/nv50_context.c
@@ -258,7 +258,8 @@ nv50_create(struct pipe_screen *pscreen, void *priv)
draw_set_rasterize_stage(nv50->draw, nv50_draw_render_stage(nv50));
#endif
- if (screen->base.device->chipset < 0x84) {
+ if (screen->base.device->chipset < 0x84 ||
+ debug_get_bool_option("NOUVEAU_PMPEG", FALSE)) {
/* PMPEG */
nouveau_context_init_vdec(&nv50->base);
} else if (screen->base.device->chipset < 0x98 ||
diff --git a/src/gallium/drivers/nv50/nv50_screen.c
b/src/gallium/drivers/nv50/nv50_screen.c
index 2951eb4..0cbee5d 100644
--- a/src/gallium/drivers/nv50/nv50_screen.c
+++ b/src/gallium/drivers/nv50/nv50_screen.c
@@ -647,7 +647,8 @@ nv50_screen_create(struct nouveau_device *dev)
nv50_screen_init_resource_functions(pscreen);
- if (screen->base.device->chipset < 0x84) {
+ if (screen->base.device->chipset < 0x84 ||
+ debug_get_bool_option("NOUVEAU_PMPEG", FALSE)) {
/* PMPEG */
nouveau_screen_init_vdec(&screen->base);
} else if (screen->base.device->chipset < 0x98 ||
--
1.8.1.5
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Re: [Mesa-dev] [PATCH 16/20] radeonsi: add FMASK texture binding slots and resource setup
The RCU approach sounds good, but you can never know if 16 is enough. We should release the buffer once it is full and allocate a new one. The cache bufmgr in the winsys will assure there won't be any buffer allocation overhead - it would work kinda a like a ring of buffers. Marek On Sat, Aug 10, 2013 at 10:45 AM, Christian König wrote: > Am 09.08.2013 20:06, schrieb Marek Olšák: >> >> [SNIP] >> >> What if I kept the current emission code, and only allocated a new >> buffer at the end of the emit function, copied all descriptors to it >> using CP_DMA or COPY_DATA, and pointed SPI_SHADER_USER_DATA to it. The >> buffer where the descriptors are updated using WRITE_DATA would act as >> a staging buffer only and shaders would always read from the fresh new >> copy. Does that sound good to you? > > > That sounds like the solution with multiple buffers I already suggest, but I > would rather use some RCU approach to it. Basically we just have to handle > it like the context based resources on earlier asics. So to me a proper > solution should look something like this: > > We allocate a ring of (let's say) 16 slots for descriptor arrays, fill the > first slot with WRITE_DATA packets and then use it in a draw command. > > As soon as any of the descriptors is about to change we copy it's content to > the next slot, let the SPI_SHADER_USER_DATA point to it, make the necessary > updates using WRITE_DATA and then use it in a draw command. > > This repeats over and over again, all we need to make sure is that we have > enough slots in the ring to be sure that we never override descriptors when > they are still in use, but I'm pretty sure that we should be on the save > side with 16 or so. > > We can even prepare the commands for the switch from one slot to the next > only once and then use it for the whole lifetime of the driver. > > Christian. ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-dev
Re: [Mesa-dev] [PATCH 16/20] radeonsi: add FMASK texture binding slots and resource setup
Am 10.08.2013 15:53, schrieb Marek Olšák: The RCU approach sounds good, but you can never know if 16 is enough. We should release the buffer once it is full and allocate a new one. The cache bufmgr in the winsys will assure there won't be any buffer allocation overhead - it would work kinda a like a ring of buffers. Are you sure of that? The overhead of allocating a new buffer was what always looked so unfriendly to me with this approach. On the other hand the CP definitely can't handle more than 8 contexts at the same time (and one of them is always the clear context), so I strongly think we should be on the save side with 16 slots here. I'm just not sure if the SQ could add some more depth to our pipeline, maybe Alex knows more on this. Christian. Marek On Sat, Aug 10, 2013 at 10:45 AM, Christian König wrote: Am 09.08.2013 20:06, schrieb Marek Olšák: [SNIP] What if I kept the current emission code, and only allocated a new buffer at the end of the emit function, copied all descriptors to it using CP_DMA or COPY_DATA, and pointed SPI_SHADER_USER_DATA to it. The buffer where the descriptors are updated using WRITE_DATA would act as a staging buffer only and shaders would always read from the fresh new copy. Does that sound good to you? That sounds like the solution with multiple buffers I already suggest, but I would rather use some RCU approach to it. Basically we just have to handle it like the context based resources on earlier asics. So to me a proper solution should look something like this: We allocate a ring of (let's say) 16 slots for descriptor arrays, fill the first slot with WRITE_DATA packets and then use it in a draw command. As soon as any of the descriptors is about to change we copy it's content to the next slot, let the SPI_SHADER_USER_DATA point to it, make the necessary updates using WRITE_DATA and then use it in a draw command. This repeats over and over again, all we need to make sure is that we have enough slots in the ring to be sure that we never override descriptors when they are still in use, but I'm pretty sure that we should be on the save side with 16 or so. We can even prepare the commands for the switch from one slot to the next only once and then use it for the whole lifetime of the driver. Christian. ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-dev
Re: [Mesa-dev] [PATCH 16/20] radeonsi: add FMASK texture binding slots and resource setup
On Sat, Aug 10, 2013 at 5:09 PM, Christian König wrote: > Am 10.08.2013 15:53, schrieb Marek Olšák: > >> The RCU approach sounds good, but you can never know if 16 is enough. >> We should release the buffer once it is full and allocate a new one. >> The cache bufmgr in the winsys will assure there won't be any buffer >> allocation overhead - it would work kinda a like a ring of buffers. > > > Are you sure of that? The overhead of allocating a new buffer was what > always looked so unfriendly to me with this approach. Absolutely. We've had this optimization since 2010 or so. As long as you use winsys->buffer_create(use_reusable_pool=TRUE), you're fine. A deleted buffer is added to a list of deleted buffers and if nobody reclaims it, it will be released after 1 second. During that 1 second, the buffer must first become idle and then anybody can reclaim it with the same buffer_create call. If the buffer had been mapped before, it's still mapped, so there is even no map-buffer overhead. This is a crucial part of our driver stack that makes vertex uploading so efficient. Don't underestimate the Radeon winsys. :) > > On the other hand the CP definitely can't handle more than 8 contexts at the > same time (and one of them is always the clear context), so I strongly think > we should be on the save side with 16 slots here. I'm just not sure if the > SQ could add some more depth to our pipeline, maybe Alex knows more on this. If we needed only 16 slots, that would be even better. Marek ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-dev
Re: [Mesa-dev] [PATCH 4/6] radeonsi: Implement PIPE_QUERY_TIMESTAMP
Reviewed-by: Marek Olšák
On Fri, Aug 9, 2013 at 11:59 AM, Niels Ole Salscheider
wrote:
> Signed-off-by: Niels Ole Salscheider
> ---
> src/gallium/drivers/radeonsi/r600.h| 1 +
> src/gallium/drivers/radeonsi/r600_hw_context.c | 31
> ++
> src/gallium/drivers/radeonsi/r600_query.c | 14 +++-
> src/gallium/drivers/radeonsi/radeonsi_pipe.c | 2 +-
> 4 Dateien geändert, 46 Zeilen hinzugefügt(+), 2 Zeilen entfernt(-)
>
> diff --git a/src/gallium/drivers/radeonsi/r600.h
> b/src/gallium/drivers/radeonsi/r600.h
> index 8f35cc2..ce0468d 100644
> --- a/src/gallium/drivers/radeonsi/r600.h
> +++ b/src/gallium/drivers/radeonsi/r600.h
> @@ -102,6 +102,7 @@ void si_context_emit_fence(struct r600_context *ctx,
> struct si_resource *fence,
> unsigned offset, unsigned value);
>
> void r600_context_draw_opaque_count(struct r600_context *ctx, struct
> r600_so_target *t);
> +bool si_query_needs_begin(unsigned type);
> void si_need_cs_space(struct r600_context *ctx, unsigned num_dw, boolean
> count_draw_in);
>
> int si_context_init(struct r600_context *ctx);
> diff --git a/src/gallium/drivers/radeonsi/r600_hw_context.c
> b/src/gallium/drivers/radeonsi/r600_hw_context.c
> index 25c972b..7de3745 100644
> --- a/src/gallium/drivers/radeonsi/r600_hw_context.c
> +++ b/src/gallium/drivers/radeonsi/r600_hw_context.c
> @@ -110,6 +110,11 @@ err:
> return;
> }
>
> +bool si_query_needs_begin(unsigned type)
> +{
> + return type != PIPE_QUERY_TIMESTAMP;
> +}
> +
> /* initialize */
> void si_need_cs_space(struct r600_context *ctx, unsigned num_dw,
> boolean count_draw_in)
> @@ -340,6 +345,12 @@ static boolean r600_query_result(struct r600_context
> *ctx, struct r600_query *qu
> results_base = (results_base + 16) %
> query->buffer->b.b.width0;
> }
> break;
> + case PIPE_QUERY_TIMESTAMP:
> + {
> + uint32_t *current_result = (uint32_t*)map;
> + query->result.u64 = (uint64_t)current_result[0] |
> (uint64_t)current_result[1] << 32;
> + break;
> + }
> case PIPE_QUERY_TIME_ELAPSED:
> while (results_base != query->results_end) {
> query->result.u64 +=
> @@ -485,6 +496,19 @@ void r600_query_end(struct r600_context *ctx, struct
> r600_query *query)
> {
> struct radeon_winsys_cs *cs = ctx->cs;
> uint64_t va;
> + unsigned new_results_end;
> +
> + /* The queries which need begin already called this in begin_query. */
> + if (!si_query_needs_begin(query->type)) {
> + si_need_cs_space(ctx, query->num_cs_dw, TRUE);
> +
> + new_results_end = (query->results_end + query->result_size) %
> query->buffer->b.b.width0;
> +
> + /* collect current results if query buffer is full */
> + if (new_results_end == query->results_start) {
> + r600_query_result(ctx, query, TRUE);
> + }
> + }
>
> va = r600_resource_va(&ctx->screen->screen, (void*)query->buffer);
> /* emit end query */
> @@ -508,6 +532,8 @@ void r600_query_end(struct r600_context *ctx, struct
> r600_query *query)
> break;
> case PIPE_QUERY_TIME_ELAPSED:
> va += query->results_end + query->result_size/2;
> + /* fall through */
> + case PIPE_QUERY_TIMESTAMP:
> cs->buf[cs->cdw++] = PKT3(PKT3_EVENT_WRITE_EOP, 4, 0);
> cs->buf[cs->cdw++] =
> EVENT_TYPE(EVENT_TYPE_CACHE_FLUSH_AND_INV_TS_EVENT) | EVENT_INDEX(5);
> cs->buf[cs->cdw++] = va;
> @@ -585,6 +611,10 @@ struct r600_query *r600_context_query_create(struct
> r600_context *ctx, unsigned
> query->result_size = 16 * ctx->max_db;
> query->num_cs_dw = 6;
> break;
> + case PIPE_QUERY_TIMESTAMP:
> + query->result_size = 8;
> + query->num_cs_dw = 8;
> + break;
> case PIPE_QUERY_TIME_ELAPSED:
> query->result_size = 16;
> query->num_cs_dw = 8;
> @@ -648,6 +678,7 @@ boolean r600_context_query_result(struct r600_context
> *ctx,
> case PIPE_QUERY_SO_OVERFLOW_PREDICATE:
> *result_b = query->result.b;
> break;
> + case PIPE_QUERY_TIMESTAMP:
> case PIPE_QUERY_TIME_ELAPSED:
> *result_u64 = (100 * query->result.u64) /
> ctx->screen->info.r600_clock_crystal_freq;
> break;
> diff --git a/src/gallium/drivers/radeonsi/r600_query.c
> b/src/gallium/drivers/radeonsi/r600_query.c
> index 0162cce..927577c 100644
> --- a/src/gallium/drivers/radeonsi/r600_query.c
> +++ b/src/gallium/drivers/radeonsi/r600_query.c
> @@ -42,6 +42,11 @@ static void r600_begin_query(struct pipe_context *ctx,
> struct pipe_query *query)
>
Re: [Mesa-dev] [PATCH 5/6] radeonsi: copy r600_get_timestamp
Reviewed-by: Marek Olšák
Marek
On Fri, Aug 9, 2013 at 11:59 AM, Niels Ole Salscheider
wrote:
> Signed-off-by: Niels Ole Salscheider
> ---
> src/gallium/drivers/radeonsi/radeonsi_pipe.c | 9 +
> 1 Datei geändert, 9 Zeilen hinzugefügt(+)
>
> diff --git a/src/gallium/drivers/radeonsi/radeonsi_pipe.c
> b/src/gallium/drivers/radeonsi/radeonsi_pipe.c
> index 3ba8232..7ae5598 100644
> --- a/src/gallium/drivers/radeonsi/radeonsi_pipe.c
> +++ b/src/gallium/drivers/radeonsi/radeonsi_pipe.c
> @@ -779,6 +779,14 @@ static int r600_init_tiling(struct r600_screen *rscreen)
> return evergreen_interpret_tiling(rscreen, tiling_config);
> }
>
> +static uint64_t r600_get_timestamp(struct pipe_screen *screen)
> +{
> + struct r600_screen *rscreen = (struct r600_screen*)screen;
> +
> + return 100 * rscreen->ws->query_value(rscreen->ws,
> RADEON_TIMESTAMP) /
> + rscreen->info.r600_clock_crystal_freq;
> +}
> +
> static unsigned radeon_family_from_device(unsigned device)
> {
> switch (device) {
> @@ -830,6 +838,7 @@ struct pipe_screen *radeonsi_screen_create(struct
> radeon_winsys *ws)
> rscreen->screen.get_shader_param = r600_get_shader_param;
> rscreen->screen.get_paramf = r600_get_paramf;
> rscreen->screen.get_compute_param = r600_get_compute_param;
> + rscreen->screen.get_timestamp = r600_get_timestamp;
> rscreen->screen.is_format_supported = si_is_format_supported;
> rscreen->screen.context_create = r600_create_context;
> rscreen->screen.fence_reference = r600_fence_reference;
> --
> 1.7.11.7
>
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[Mesa-dev] [PATCH 12/20] radeonsi: implement MSAA colorbuffer compression for rendering
v2: simplify flushing in si_context_flush
---
src/gallium/drivers/radeonsi/r600_hw_context.c | 3 +
src/gallium/drivers/radeonsi/r600_resource.h | 21
src/gallium/drivers/radeonsi/r600_texture.c| 133 -
src/gallium/drivers/radeonsi/radeonsi_pipe.h | 2 +
src/gallium/drivers/radeonsi/si_commands.c | 9 ++
src/gallium/drivers/radeonsi/si_state.c| 28 ++
src/gallium/drivers/radeonsi/si_state.h| 2 +
src/gallium/drivers/radeonsi/si_state_draw.c | 11 ++
src/gallium/drivers/radeonsi/sid.h | 1 +
9 files changed, 208 insertions(+), 2 deletions(-)
diff --git a/src/gallium/drivers/radeonsi/r600_hw_context.c
b/src/gallium/drivers/radeonsi/r600_hw_context.c
index 25c972b..19e9d1c 100644
--- a/src/gallium/drivers/radeonsi/r600_hw_context.c
+++ b/src/gallium/drivers/radeonsi/r600_hw_context.c
@@ -176,10 +176,13 @@ static void r600_flush_framebuffer(struct r600_context
*ctx)
S_0085F0_CB7_DEST_BASE_ENA(1) |
S_0085F0_DB_ACTION_ENA(1) |
S_0085F0_DB_DEST_BASE_ENA(1));
+ si_cmd_flush_and_inv_cb_meta(pm4);
+
si_pm4_emit(ctx, pm4);
si_pm4_free_state(ctx, pm4, ~0);
ctx->flags &= ~R600_CONTEXT_DST_CACHES_DIRTY;
+ ctx->flush_and_inv_cb_meta = false;
}
void si_context_flush(struct r600_context *ctx, unsigned flags)
diff --git a/src/gallium/drivers/radeonsi/r600_resource.h
b/src/gallium/drivers/radeonsi/r600_resource.h
index ca8121f..e5dd36a 100644
--- a/src/gallium/drivers/radeonsi/r600_resource.h
+++ b/src/gallium/drivers/radeonsi/r600_resource.h
@@ -40,6 +40,22 @@ struct r600_transfer {
struct pipe_resource*staging;
};
+struct r600_fmask_info {
+ unsigned offset;
+ unsigned size;
+ unsigned alignment;
+ unsigned bank_height;
+ unsigned slice_tile_max;
+ unsigned tile_mode_index;
+};
+
+struct r600_cmask_info {
+ unsigned offset;
+ unsigned size;
+ unsigned alignment;
+ unsigned slice_tile_max;
+};
+
struct r600_texture {
struct si_resource resource;
@@ -48,12 +64,17 @@ struct r600_texture {
* for the stencil buffer below. */
enum pipe_formatreal_format;
+ unsignedsize;
unsignedpitch_override;
unsignedis_depth;
unsigneddirty_level_mask; /* each bit says if
that miplevel is dirty */
struct r600_texture *flushed_depth_texture;
boolean is_flushing_texture;
struct radeon_surface surface;
+
+ /* Colorbuffer compression and fast clear. */
+ struct r600_fmask_info fmask;
+ struct r600_cmask_info cmask;
};
struct r600_surface {
diff --git a/src/gallium/drivers/radeonsi/r600_texture.c
b/src/gallium/drivers/radeonsi/r600_texture.c
index 185d9875..59e3604 100644
--- a/src/gallium/drivers/radeonsi/r600_texture.c
+++ b/src/gallium/drivers/radeonsi/r600_texture.c
@@ -173,6 +173,9 @@ static int r600_setup_surface(struct pipe_screen *screen,
if (r) {
return r;
}
+
+ rtex->size = rtex->surface.bo_size;
+
if (pitch_in_bytes_override && pitch_in_bytes_override !=
rtex->surface.level[0].pitch_bytes) {
/* old ddx on evergreen over estimate alignment for 1d, only 1
level
* for those
@@ -419,6 +422,116 @@ static const struct u_resource_vtbl r600_texture_vtbl =
DEBUG_GET_ONCE_BOOL_OPTION(print_texdepth, "RADEON_PRINT_TEXDEPTH", FALSE);
+/* The number of samples can be specified independently of the texture. */
+static void r600_texture_get_fmask_info(struct r600_screen *rscreen,
+ struct r600_texture *rtex,
+ unsigned nr_samples,
+ struct r600_fmask_info *out)
+{
+ /* FMASK is allocated like an ordinary texture. */
+ struct radeon_surface fmask = rtex->surface;
+
+ memset(out, 0, sizeof(*out));
+
+ fmask.bo_alignment = 0;
+ fmask.bo_size = 0;
+ fmask.nsamples = 1;
+ fmask.flags |= RADEON_SURF_FMASK | RADEON_SURF_HAS_TILE_MODE_INDEX;
+
+ switch (nr_samples) {
+ case 2:
+ case 4:
+ fmask.bpe = 1;
+ break;
+ case 8:
+ fmask.bpe = 4;
+ break;
+ default:
+ R600_ERR("Invalid sample count for FMASK allocation.\n");
+ return;
+ }
+
+ if (rscreen->ws->surface_init(rscreen->ws, &fmask)) {
+ R600_ERR("Got error in surface_init while allocating FMASK.\n");
+ return;
+ }
+
+ assert(fmask.level[0].mode == RADEON_SURF_MODE_2D);
+
+ out->slice_tile_max = (fmask.
[Mesa-dev] [PATCH] radeonsi: scanout buffers cannot be a destination of MSAA resolve
Resolving to scanout buffers just doesn't work. --- src/gallium/drivers/radeonsi/r600_blit.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/src/gallium/drivers/radeonsi/r600_blit.c b/src/gallium/drivers/radeonsi/r600_blit.c index 3f9a184..1840e28 100644 --- a/src/gallium/drivers/radeonsi/r600_blit.c +++ b/src/gallium/drivers/radeonsi/r600_blit.c @@ -471,6 +471,7 @@ static boolean is_simple_msaa_resolve(const struct pipe_blit_info *info) unsigned dst_height = u_minify(info->dst.resource->height0, info->dst.level); struct r600_texture *dst = (struct r600_texture*)info->dst.resource; unsigned dst_tile_mode = dst->surface.level[info->dst.level].mode; + bool dst_is_scanout = (dst->surface.flags & RADEON_SURF_SCANOUT) != 0; return info->dst.resource->format == info->src.resource->format && info->dst.resource->format == info->dst.format && @@ -489,7 +490,8 @@ static boolean is_simple_msaa_resolve(const struct pipe_blit_info *info) info->src.box.height == dst_height && /* Dst must be tiled. If it's not, we have to use a temporary * resource which is tiled. */ - dst_tile_mode >= RADEON_SURF_MODE_1D; + dst_tile_mode >= RADEON_SURF_MODE_1D && + !dst_is_scanout; } /* For MSAA integer resolving to work, we change the format to NORM using this function. */ -- 1.8.1.2 ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-dev
[Mesa-dev] [PATCH 1/4] R600/SI: Add pattern for fp_to_uint
This fixes the F2U opcode for the Mesa driver.
Signed-off-by: Marek Olšák
---
lib/Target/R600/SIInstructions.td | 4 +++-
test/CodeGen/R600/fp_to_uint.ll | 27 ++-
2 files changed, 21 insertions(+), 10 deletions(-)
diff --git a/lib/Target/R600/SIInstructions.td
b/lib/Target/R600/SIInstructions.td
index dc41885..d941035 100644
--- a/lib/Target/R600/SIInstructions.td
+++ b/lib/Target/R600/SIInstructions.td
@@ -615,7 +615,9 @@ defm V_CVT_F32_I32 : VOP1_32 <0x0005, "V_CVT_F32_I32",
defm V_CVT_F32_U32 : VOP1_32 <0x0006, "V_CVT_F32_U32",
[(set f32:$dst, (uint_to_fp i32:$src0))]
>;
-defm V_CVT_U32_F32 : VOP1_32 <0x0007, "V_CVT_U32_F32", []>;
+defm V_CVT_U32_F32 : VOP1_32 <0x0007, "V_CVT_U32_F32",
+ [(set i32:$dst, (fp_to_uint f32:$src0))]
+>;
defm V_CVT_I32_F32 : VOP1_32 <0x0008, "V_CVT_I32_F32",
[(set i32:$dst, (fp_to_sint f32:$src0))]
>;
diff --git a/test/CodeGen/R600/fp_to_uint.ll b/test/CodeGen/R600/fp_to_uint.ll
index 2a365f9..0d07a61 100644
--- a/test/CodeGen/R600/fp_to_uint.ll
+++ b/test/CodeGen/R600/fp_to_uint.ll
@@ -1,8 +1,12 @@
-; RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck %s
+; RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck %s
--check-prefix=R600-CHECK
+; RUN: llc < %s -march=r600 -mcpu=SI | FileCheck %s --check-prefix=SI-CHECK
-; CHECK: @fp_to_uint_v2i32
-; CHECK: FLT_TO_UINT * T{{[0-9]+\.[XYZW], PV\.[XYZW]}}
-; CHECK: FLT_TO_UINT * T{{[0-9]+\.[XYZW], PV\.[XYZW]}}
+; R600-CHECK: @fp_to_uint_v2i32
+; R600-CHECK: FLT_TO_UINT * T{{[0-9]+\.[XYZW], PV\.[XYZW]}}
+; R600-CHECK: FLT_TO_UINT * T{{[0-9]+\.[XYZW], PV\.[XYZW]}}
+; SI-CHECK: @fp_to_uint_v2i32
+; SI-CHECK: V_CVT_U32_F32_e32
+; SI-CHECK: V_CVT_U32_F32_e32
define void @fp_to_uint_v2i32(<2 x i32> addrspace(1)* %out, <2 x float> %in) {
%result = fptoui <2 x float> %in to <2 x i32>
@@ -10,11 +14,16 @@ define void @fp_to_uint_v2i32(<2 x i32> addrspace(1)* %out,
<2 x float> %in) {
ret void
}
-; CHECK: @fp_to_uint_v4i32
-; CHECK: FLT_TO_UINT * T{{[0-9]+\.[XYZW], PV\.[XYZW]}}
-; CHECK: FLT_TO_UINT * T{{[0-9]+\.[XYZW], PV\.[XYZW]}}
-; CHECK: FLT_TO_UINT * T{{[0-9]+\.[XYZW], PV\.[XYZW]}}
-; CHECK: FLT_TO_UINT * T{{[0-9]+\.[XYZW], PV\.[XYZW]}}
+; R600-CHECK: @fp_to_uint_v4i32
+; R600-CHECK: FLT_TO_UINT * T{{[0-9]+\.[XYZW], PV\.[XYZW]}}
+; R600-CHECK: FLT_TO_UINT * T{{[0-9]+\.[XYZW], PV\.[XYZW]}}
+; R600-CHECK: FLT_TO_UINT * T{{[0-9]+\.[XYZW], PV\.[XYZW]}}
+; R600-CHECK: FLT_TO_UINT * T{{[0-9]+\.[XYZW], PV\.[XYZW]}}
+; SI-CHECK: @fp_to_uint_v4i32
+; SI-CHECK: V_CVT_U32_F32_e32
+; SI-CHECK: V_CVT_U32_F32_e32
+; SI-CHECK: V_CVT_U32_F32_e32
+; SI-CHECK: V_CVT_U32_F32_e32
define void @fp_to_uint_v4i32(<4 x i32> addrspace(1)* %out, <4 x float>
addrspace(1)* %in) {
%value = load <4 x float> addrspace(1) * %in
--
1.8.1.2
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[Mesa-dev] [PATCH 2/4] R600/SI: Fix an obvious typo
Signed-off-by: Marek Olšák --- lib/Target/R600/AMDGPUCallingConv.td | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/lib/Target/R600/AMDGPUCallingConv.td b/lib/Target/R600/AMDGPUCallingConv.td index fc95d58..84d3118 100644 --- a/lib/Target/R600/AMDGPUCallingConv.td +++ b/lib/Target/R600/AMDGPUCallingConv.td @@ -24,7 +24,7 @@ def CC_SI : CallingConv<[ CCIfInReg>>, CCIfNotInReghttp://lists.freedesktop.org/mailman/listinfo/mesa-dev
[Mesa-dev] [PATCH 3/4] R600/SI: Allow conversion between v32i8 and v8i32
Signed-off-by: Marek Olšák
---
lib/Target/R600/SIInstructions.td | 5 +
lib/Target/R600/SIRegisterInfo.td | 4 ++--
2 files changed, 7 insertions(+), 2 deletions(-)
diff --git a/lib/Target/R600/SIInstructions.td
b/lib/Target/R600/SIInstructions.td
index d941035..be2e290 100644
--- a/lib/Target/R600/SIInstructions.td
+++ b/lib/Target/R600/SIInstructions.td
@@ -1506,6 +1506,11 @@ def : BitConvert ;
def : BitConvert ;
def : BitConvert ;
+def : BitConvert ;
+def : BitConvert ;
+def : BitConvert ;
+def : BitConvert ;
+
/** === **/
/** Src & Dst modifiers **/
/** === **/
diff --git a/lib/Target/R600/SIRegisterInfo.td
b/lib/Target/R600/SIRegisterInfo.td
index 292b9d2..82d1e71 100644
--- a/lib/Target/R600/SIRegisterInfo.td
+++ b/lib/Target/R600/SIRegisterInfo.td
@@ -159,7 +159,7 @@ def SReg_64 : RegisterClass<"AMDGPU", [v2i32, i64, i1], 64,
def SReg_128 : RegisterClass<"AMDGPU", [v16i8, i128], 128, (add SGPR_128)>;
-def SReg_256 : RegisterClass<"AMDGPU", [v32i8], 256, (add SGPR_256)>;
+def SReg_256 : RegisterClass<"AMDGPU", [v32i8, v8i32, v8f32], 256, (add
SGPR_256)>;
def SReg_512 : RegisterClass<"AMDGPU", [v64i8], 512, (add SGPR_512)>;
@@ -174,7 +174,7 @@ def VReg_96 : RegisterClass<"AMDGPU", [untyped], 96, (add
VGPR_96)> {
def VReg_128 : RegisterClass<"AMDGPU", [v4i32, v4f32], 128, (add VGPR_128)>;
-def VReg_256 : RegisterClass<"AMDGPU", [v8i32, v8f32], 256, (add VGPR_256)>;
+def VReg_256 : RegisterClass<"AMDGPU", [v32i8, v8i32, v8f32], 256, (add
VGPR_256)>;
def VReg_512 : RegisterClass<"AMDGPU", [v16i32, v16f32], 512, (add VGPR_512)>;
--
1.8.1.2
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[Mesa-dev] [PATCH 4/4] R600/SI: Handle MSAA texture targets
Signed-off-by: Marek Olšák
---
lib/Target/R600/R600Instructions.td| 16 +++-
lib/Target/R600/SIInstructions.td | 19 ++-
test/CodeGen/R600/llvm.SI.imageload.ll | 2 +-
3 files changed, 34 insertions(+), 3 deletions(-)
diff --git a/lib/Target/R600/R600Instructions.td
b/lib/Target/R600/R600Instructions.td
index 7e61b18..52205cc 100644
--- a/lib/Target/R600/R600Instructions.td
+++ b/lib/Target/R600/R600Instructions.td
@@ -230,7 +230,7 @@ def TEX_RECT : PatLeaf<
def TEX_ARRAY : PatLeaf<
(imm),
[{uint32_t TType = (uint32_t)N->getZExtValue();
-return TType == 9 || TType == 10 || TType == 15 || TType == 16;
+return TType == 9 || TType == 10 || TType == 16;
}]
>;
@@ -241,6 +241,20 @@ def TEX_SHADOW_ARRAY : PatLeaf<
}]
>;
+def TEX_MSAA : PatLeaf<
+ (imm),
+ [{uint32_t TType = (uint32_t)N->getZExtValue();
+return TType == 14;
+ }]
+>;
+
+def TEX_ARRAY_MSAA : PatLeaf<
+ (imm),
+ [{uint32_t TType = (uint32_t)N->getZExtValue();
+return TType == 15;
+ }]
+>;
+
class EG_CF_RAT cfinst, bits <6> ratinst, bits<4> mask, dag outs,
dag ins, string asm, list pattern> :
InstR600ISA ,
diff --git a/lib/Target/R600/SIInstructions.td
b/lib/Target/R600/SIInstructions.td
index be2e290..30c02e8 100644
--- a/lib/Target/R600/SIInstructions.td
+++ b/lib/Target/R600/SIInstructions.td
@@ -500,7 +500,7 @@ defm S_BUFFER_LOAD_DWORDX16 : SMRD_Helper <
//def S_MEMTIME : SMRD_ <0x001e, "S_MEMTIME", []>;
//def S_DCACHE_INV : SMRD_ <0x001f, "S_DCACHE_INV", []>;
-//def IMAGE_LOAD : MIMG_NoPattern_ <"IMAGE_LOAD", 0x>;
+def IMAGE_LOAD : MIMG_NoSampler_Helper <0x, "IMAGE_LOAD">;
def IMAGE_LOAD_MIP : MIMG_NoSampler_Helper <0x0001, "IMAGE_LOAD_MIP">;
//def IMAGE_LOAD_PCK : MIMG_NoPattern_ <"IMAGE_LOAD_PCK", 0x0002>;
//def IMAGE_LOAD_PCK_SGN : MIMG_NoPattern_ <"IMAGE_LOAD_PCK_SGN", 0x0003>;
@@ -1393,9 +1393,21 @@ class ImageLoadArrayPattern :
(opcode 0xf, 0, 0, 1, 0, 0, 0, 0, $addr, $rsrc)
>;
+class ImageLoadMSAAPattern :
Pat <
+(name addr_type:$addr, v32i8:$rsrc, TEX_MSAA),
+(opcode 0xf, 0, 0, 0, 0, 0, 0, 0, $addr, $rsrc)
+>;
+
+class ImageLoadArrayMSAAPattern : Pat <
+(name addr_type:$addr, v32i8:$rsrc, TEX_ARRAY_MSAA),
+(opcode 0xf, 0, 0, 1, 0, 0, 0, 0, $addr, $rsrc)
+>;
+
multiclass ImageLoadPatterns {
def : ImageLoadPattern ;
def : ImageLoadArrayPattern ;
+ def : ImageLoadMSAAPattern ;
+ def : ImageLoadArrayMSAAPattern ;
}
defm : ImageLoadPatterns;
@@ -1412,6 +1424,11 @@ def : Pat <
(IMAGE_GET_RESINFO 0xf, 0, 0, 1, 0, 0, 0, 0, (V_MOV_B32_e32 $mipid), $rsrc)
>;
+def : Pat <
+ (int_SI_resinfo i32:$mipid, v32i8:$rsrc, TEX_ARRAY_MSAA),
+ (IMAGE_GET_RESINFO 0xf, 0, 0, 1, 0, 0, 0, 0, (V_MOV_B32_e32 $mipid), $rsrc)
+>;
+
/** **/
/** Extraction, Insertion, Building and Casting **/
/** **/
diff --git a/test/CodeGen/R600/llvm.SI.imageload.ll
b/test/CodeGen/R600/llvm.SI.imageload.ll
index 0adcdfc..1ed4dd4 100644
--- a/test/CodeGen/R600/llvm.SI.imageload.ll
+++ b/test/CodeGen/R600/llvm.SI.imageload.ll
@@ -1,6 +1,6 @@
;RUN: llc < %s -march=r600 -mcpu=verde | FileCheck %s
-;CHECK-DAG: IMAGE_LOAD_MIP {{VGPR[0-9]+_VGPR[0-9]+_VGPR[0-9]+_VGPR[0-9]+}},
15, 0, 0, -1
+;CHECK-DAG: IMAGE_LOAD {{VGPR[0-9]+_VGPR[0-9]+_VGPR[0-9]+_VGPR[0-9]+}}, 15, 0,
0, -1
;CHECK-DAG: IMAGE_LOAD_MIP {{VGPR[0-9]+_VGPR[0-9]+}}, 3, 0, 0, 0
;CHECK-DAG: IMAGE_LOAD_MIP {{VGPR[0-9]+}}, 2, 0, 0, 0
;CHECK-DAG: IMAGE_LOAD_MIP {{VGPR[0-9]+}}, 1, 0, 0, 0
--
1.8.1.2
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[Mesa-dev] [PATCH] gbm: fix linking
Link to internal libwayland-drm library if Wayland EGL platform is enabled. Link to libdrm if gbm_dri is enabled. --- src/gbm/Makefile.am | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/src/gbm/Makefile.am b/src/gbm/Makefile.am index e22c55c..1282b14 100644 --- a/src/gbm/Makefile.am +++ b/src/gbm/Makefile.am @@ -24,6 +24,7 @@ libgbm_la_LIBADD = $(LIBUDEV_LIBS) $(LIBKMS_LIBS) $(DLOPEN_LIBS) if HAVE_EGL_PLATFORM_WAYLAND AM_CPPFLAGS = -DHAVE_WAYLAND_PLATFORM AM_CFLAGS += $(WAYLAND_CFLAGS) +libgbm_la_LIBADD += $(top_builddir)/src/egl/wayland/wayland-drm/libwayland-drm.la $(WAYLAND_LIBS) endif if HAVE_DRI @@ -38,7 +39,7 @@ libgbm_dri_la_CFLAGS = \ $(LIBDRM_CFLAGS) libgbm_la_LIBADD += \ - libgbm_dri.la $(top_builddir)/src/mapi/shared-glapi/libglapi.la + libgbm_dri.la $(top_builddir)/src/mapi/shared-glapi/libglapi.la $(LIBDRM_LIBS) endif all-local: libgbm.la -- 1.8.3.4 ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-dev
[Mesa-dev] [Bug 67962] undefined reference to `wayland_drm_buffer_get'
https://bugs.freedesktop.org/show_bug.cgi?id=67962 Hrvoje Senjan changed: What|Removed |Added Assignee|wayland-bugs@lists.freedesk |mesa-dev@lists.freedesktop. |top.org |org Product|Wayland |Mesa Version|unspecified |git Component|weston |Other --- Comment #1 from Hrvoje Senjan --- Also Mesa-demo: [ 79s] xeglgears.c: In function 'main': [ 79s] xeglgears.c:919:9: warning: cast to pointer from integer of different size [-Wint-to-pointer-cast] [ 79s] (EGLClientBuffer) color_rb, NULL); [ 79s] ^ [ 79s] /usr/lib64/libgbm.so.1: undefined reference to `wayland_drm_buffer_get' [ 79s] collect2: error: ld returned 1 exit status and cairo: [ 155s] libtool: link: gcc -D_REENTRANT -I/usr/include/pixman-1 -I/usr/include/freetype2 -I/usr/include/libdrm -I/usr/include/libdrm -I/usr/include/libpng16 -Wall -Wextra -Wold-style-definition -Wdeclaration-after-statement -Wmissing-declarations -Werror-implicit-function-declaration -Wnested-externs -Wpointer-arith -Wwrite-strings -Wsign-compare -Wstrict-prototypes -Wmissing-prototypes -Wpacked -Wswitch-enum -Wmissing-format-attribute -Wbad-function-cast -Wvolatile-register-var -Wstrict-aliasing=2 -Winit-self -Wunsafe-loop-optimizations -Wno-missing-field-initializers -Wno-unused-parameter -Wno-attributes -Wno-long-long -Winline -flto -fno-strict-aliasing -fno-common -Wp,-D_FORTIFY_SOURCE=2 -Wno-unused-but-set-variable -D_REENTRANT -I/usr/include/glib-2.0 -I/usr/lib64/glib-2.0/include -fmessage-length=0 -grecord-gcc-switches -O2 -Wall -D_FORTIFY_SOURCE=2 -fstack-protector -funwind-tables -fasynchronous-unwind-tables -g -o .libs/cairo-sphinx cairo_sphinx-sphinx.o ../../util/cairo-script/.libs/libcairo-script-interpreter.so ../../boilerplate/.libs/libcairoboilerplate.a /home/abuild/rpmbuild/BUILD/cairo-1.12.14/src/.libs/libcairo.so -lpthread -lpixman-1 -lfontconfig -lfreetype -lEGL -lpng16 -lxcb-shm -lxcb-render -lxcb -lXrender -lX11 -lXext -lz -lGL -ldl ../../src/.libs/libcairo.so -lglib-2.0 -lrt -lm -Wl,-rpath -Wl,/usr/lib64 [ 156s] /usr/lib64/libgbm.so.1: undefined reference to `wayland_drm_buffer_get' [ 156s] collect2: error: ld returned 1 exit status [ 156s] make[4]: *** [cairo-sphinx] Error 1 -- You are receiving this mail because: You are the assignee for the bug. ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-dev
[Mesa-dev] [Bug 67962] undefined reference to `wayland_drm_buffer_get'
https://bugs.freedesktop.org/show_bug.cgi?id=67962 --- Comment #2 from Armin K --- I've sent a fix today http://lists.freedesktop.org/archives/mesa-dev/2013-August/043097.html -- You are receiving this mail because: You are the assignee for the bug. ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-dev
Re: [Mesa-dev] [PATCH] gbm: fix linking
On 08/10/2013 09:26 PM, Armin K wrote: > Link to internal libwayland-drm library if Wayland > EGL platform is enabled. > > Link to libdrm if gbm_dri is enabled. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=67962 > --- > src/gbm/Makefile.am | 3 ++- > 1 file changed, 2 insertions(+), 1 deletion(-) > > diff --git a/src/gbm/Makefile.am b/src/gbm/Makefile.am > index e22c55c..1282b14 100644 > --- a/src/gbm/Makefile.am > +++ b/src/gbm/Makefile.am > @@ -24,6 +24,7 @@ libgbm_la_LIBADD = $(LIBUDEV_LIBS) $(LIBKMS_LIBS) > $(DLOPEN_LIBS) > if HAVE_EGL_PLATFORM_WAYLAND > AM_CPPFLAGS = -DHAVE_WAYLAND_PLATFORM > AM_CFLAGS += $(WAYLAND_CFLAGS) > +libgbm_la_LIBADD += > $(top_builddir)/src/egl/wayland/wayland-drm/libwayland-drm.la $(WAYLAND_LIBS) > endif > > if HAVE_DRI > @@ -38,7 +39,7 @@ libgbm_dri_la_CFLAGS = \ > $(LIBDRM_CFLAGS) > > libgbm_la_LIBADD += \ > - libgbm_dri.la $(top_builddir)/src/mapi/shared-glapi/libglapi.la > + libgbm_dri.la $(top_builddir)/src/mapi/shared-glapi/libglapi.la > $(LIBDRM_LIBS) > endif > > all-local: libgbm.la > ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-dev
[Mesa-dev] [PATCH] r600g/sb: use MULADD workaround on R7xx for MULADD_IEEE
Looks like the same issue that was seen with MULADD in trans slot on
R7xx also affects MULADD_IEEE (maybe all OP3 instructions and MULADD is
just a most frequently used?). The workaround is to never put
affected instructions into the trans slot.
IIRC it was mostly observed when affected instructions had kcache operands
and some specific bank swizzles, but I have no R7xx hw to verify that, also
I'm still not sure whether it affects R6xx. Probably the condition can be
narrowed to allow better ALU packing in some cases.
Fixes https://bugs.freedesktop.org/show_bug.cgi?id=67927
Signed-off-by: Vadim Girlin
Cc: "9.2"
---
src/gallium/drivers/r600/sb/sb_sched.cpp | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/src/gallium/drivers/r600/sb/sb_sched.cpp
b/src/gallium/drivers/r600/sb/sb_sched.cpp
index f0e41f5..2792315 100644
--- a/src/gallium/drivers/r600/sb/sb_sched.cpp
+++ b/src/gallium/drivers/r600/sb/sb_sched.cpp
@@ -1490,7 +1490,8 @@ unsigned post_scheduler::try_add_instruction(node *n) {
// FIXME workaround for some problems with MULADD in trans slot
on r700,
// (is it really needed on r600?)
- if (a->bc.op == ALU_OP3_MULADD && !ctx.is_egcm()) {
+ if ((a->bc.op == ALU_OP3_MULADD || a->bc.op ==
ALU_OP3_MULADD_IEEE) &&
+ !ctx.is_egcm()) {
allowed_slots &= 0x0F;
}
--
1.8.3.1
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[Mesa-dev] [PATCH] r300g: enable MSAA on r300-r400, be careful about using color compression
MSAA was tested by one user on RS690 and it works for him with color
compression (CMASK) disabled. Our theory is that his chipset lacks CMASK RAM.
Since we don't have hardware documentation about which chipsets actually have
CMASK RAM, I had to take a guess based on the presence of HiZ.
---
src/gallium/drivers/r300/r300_chipset.c | 8
src/gallium/drivers/r300/r300_chipset.h | 2 ++
src/gallium/drivers/r300/r300_screen.c | 5 -
src/gallium/drivers/r300/r300_texture_desc.c | 4
4 files changed, 14 insertions(+), 5 deletions(-)
diff --git a/src/gallium/drivers/r300/r300_chipset.c
b/src/gallium/drivers/r300/r300_chipset.c
index 30e085a..c1f5e3c 100644
--- a/src/gallium/drivers/r300/r300_chipset.c
+++ b/src/gallium/drivers/r300/r300_chipset.c
@@ -84,6 +84,7 @@ void r300_parse_chipset(uint32_t pci_id, struct
r300_capabilities* caps)
caps->num_vert_fpus = 0;
caps->hiz_ram = 0;
caps->zmask_ram = 0;
+caps->has_cmask = FALSE;
switch (caps->family) {
@@ -91,6 +92,7 @@ void r300_parse_chipset(uint32_t pci_id, struct
r300_capabilities* caps)
case CHIP_R350:
caps->high_second_pipe = TRUE;
caps->num_vert_fpus = 4;
+caps->has_cmask = TRUE; /* guessed because there is also HiZ */
caps->hiz_ram = R300_HIZ_LIMIT;
caps->zmask_ram = PIPE_ZMASK_SIZE;
break;
@@ -105,6 +107,7 @@ void r300_parse_chipset(uint32_t pci_id, struct
r300_capabilities* caps)
case CHIP_RV380:
caps->high_second_pipe = TRUE;
caps->num_vert_fpus = 2;
+caps->has_cmask = TRUE; /* guessed because there is also HiZ */
caps->hiz_ram = R300_HIZ_LIMIT;
caps->zmask_ram = RV3xx_ZMASK_SIZE;
break;
@@ -127,24 +130,28 @@ void r300_parse_chipset(uint32_t pci_id, struct
r300_capabilities* caps)
case CHIP_R481:
case CHIP_RV410:
caps->num_vert_fpus = 6;
+caps->has_cmask = TRUE; /* guessed because there is also HiZ */
caps->hiz_ram = R300_HIZ_LIMIT;
caps->zmask_ram = PIPE_ZMASK_SIZE;
break;
case CHIP_R520:
caps->num_vert_fpus = 8;
+caps->has_cmask = TRUE;
caps->hiz_ram = R300_HIZ_LIMIT;
caps->zmask_ram = PIPE_ZMASK_SIZE;
break;
case CHIP_RV515:
caps->num_vert_fpus = 2;
+caps->has_cmask = TRUE;
caps->hiz_ram = R300_HIZ_LIMIT;
caps->zmask_ram = PIPE_ZMASK_SIZE;
break;
case CHIP_RV530:
caps->num_vert_fpus = 5;
+caps->has_cmask = TRUE;
caps->hiz_ram = RV530_HIZ_LIMIT;
caps->zmask_ram = PIPE_ZMASK_SIZE;
break;
@@ -153,6 +160,7 @@ void r300_parse_chipset(uint32_t pci_id, struct
r300_capabilities* caps)
case CHIP_RV560:
case CHIP_RV570:
caps->num_vert_fpus = 8;
+caps->has_cmask = TRUE;
caps->hiz_ram = RV530_HIZ_LIMIT;
caps->zmask_ram = PIPE_ZMASK_SIZE;
break;
diff --git a/src/gallium/drivers/r300/r300_chipset.h
b/src/gallium/drivers/r300/r300_chipset.h
index f8b5d4e..8e9deb6 100644
--- a/src/gallium/drivers/r300/r300_chipset.h
+++ b/src/gallium/drivers/r300/r300_chipset.h
@@ -55,6 +55,8 @@ struct r300_capabilities {
int hiz_ram;
/* Some chipsets have zmask ram per pipe some don't. */
int zmask_ram;
+/* CMASK is for MSAA colorbuffer compression and fast clear. */
+boolean has_cmask;
/* Compression mode for ZMASK. */
enum r300_zmask_compression z_compress;
/* Whether or not this is RV350 or newer, including all r400 and r500
diff --git a/src/gallium/drivers/r300/r300_screen.c
b/src/gallium/drivers/r300/r300_screen.c
index 7ead292..057008c 100644
--- a/src/gallium/drivers/r300/r300_screen.c
+++ b/src/gallium/drivers/r300/r300_screen.c
@@ -441,11 +441,6 @@ static boolean r300_is_format_supported(struct
pipe_screen* screen,
if (!drm_2_8_0) {
return FALSE;
}
-/* Only support R500, because I didn't test older chipsets,
- * but MSAA should work there too. */
-if (!is_r500 && !debug_get_bool_option("RADEON_MSAA", FALSE)) {
-return FALSE;
-}
/* No texturing and scanout. */
if (usage & (PIPE_BIND_SAMPLER_VIEW |
PIPE_BIND_DISPLAY_TARGET |
diff --git a/src/gallium/drivers/r300/r300_texture_desc.c
b/src/gallium/drivers/r300/r300_texture_desc.c
index 8d96b56..8fa98c5 100644
--- a/src/gallium/drivers/r300/r300_texture_desc.c
+++ b/src/gallium/drivers/r300/r300_texture_desc.c
@@ -417,6 +417,10 @@ static void r300_setup_cmask_properties(struct r300_screen
*screen,
static unsigned cmask_align_y[4] = {16, 16, 16, 32};
unsigned pipes, stride, cmask_num_dw, cmask_max_size;
+if (!screen->caps.has_cmask) {
+return;
+}
+
/* We need an AA colorbuffer, no mipmaps. */
if (tex->b.b.nr_samples <= 1 ||
tex->b.b.last_level > 0 ||
