[llvm-commits] [llvm] r45656 - in /llvm/trunk: include/llvm/ include/llvm/Target/ include/llvm/Transforms/ lib/CodeGen/ lib/Target/ lib/Target/ARM/ lib/Target/IA64/ lib/Target/PowerPC/ utils/TableGen/
Author: lattner
Date: Sun Jan 6 02:36:04 2008
New Revision: 45656
URL: http://llvm.org/viewvc/llvm-project?rev=45656&view=rev
Log:
rename isStore -> mayStore to more accurately reflect what it captures.
Modified:
llvm/trunk/include/llvm/LinkAllPasses.h
llvm/trunk/include/llvm/Target/TargetInstrInfo.h
llvm/trunk/include/llvm/Transforms/Scalar.h
llvm/trunk/lib/CodeGen/BranchFolding.cpp
llvm/trunk/lib/Target/ARM/ARMInstrInfo.td
llvm/trunk/lib/Target/ARM/ARMInstrThumb.td
llvm/trunk/lib/Target/ARM/ARMInstrVFP.td
llvm/trunk/lib/Target/ARM/ARMRegisterInfo.cpp
llvm/trunk/lib/Target/IA64/IA64InstrInfo.td
llvm/trunk/lib/Target/PowerPC/PPCHazardRecognizers.cpp
llvm/trunk/lib/Target/PowerPC/PPCInstr64Bit.td
llvm/trunk/lib/Target/PowerPC/PPCInstrInfo.td
llvm/trunk/lib/Target/Target.td
llvm/trunk/lib/Target/TargetSelectionDAG.td
llvm/trunk/utils/TableGen/CodeGenInstruction.cpp
llvm/trunk/utils/TableGen/CodeGenInstruction.h
llvm/trunk/utils/TableGen/InstrInfoEmitter.cpp
Modified: llvm/trunk/include/llvm/LinkAllPasses.h
URL:
http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/LinkAllPasses.h?rev=45656&r1=45655&r2=45656&view=diff
==
--- llvm/trunk/include/llvm/LinkAllPasses.h (original)
+++ llvm/trunk/include/llvm/LinkAllPasses.h Sun Jan 6 02:36:04 2008
@@ -114,6 +114,7 @@
(void) llvm::createPredicateSimplifierPass();
(void) llvm::createCodeGenPreparePass();
(void) llvm::createGVNPass();
+ (void) llvm::createValueInfoPass();
(void)new llvm::IntervalPartition();
(void)new llvm::FindUsedTypes();
Modified: llvm/trunk/include/llvm/Target/TargetInstrInfo.h
URL:
http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Target/TargetInstrInfo.h?rev=45656&r1=45655&r2=45656&view=diff
==
--- llvm/trunk/include/llvm/Target/TargetInstrInfo.h (original)
+++ llvm/trunk/include/llvm/Target/TargetInstrInfo.h Sun Jan 6 02:36:04 2008
@@ -50,11 +50,11 @@
const unsigned M_DELAY_SLOT_FLAG = 1 << 4;
const unsigned M_LOAD_FLAG = 1 << 5;
-/// M_STORE_FLAG - This flag is set to any instruction that could possibly
+/// M_MAY_STORE_FLAG - This flag is set to any instruction that could possibly
/// modify memory. Instructions with this flag set are not necessarily simple
/// store instructions, they may store a modified value based on their
operands,
/// or may not actually modify anything, for example.
-const unsigned M_STORE_FLAG= 1 << 6;
+const unsigned M_MAY_STORE_FLAG= 1 << 6;
const unsigned M_INDIRECT_FLAG = 1 << 7;
const unsigned M_IMPLICIT_DEF_FLAG = 1 << 8;
@@ -283,12 +283,12 @@
return get(Opcode).Flags & M_LOAD_FLAG;
}
- /// isStore - Return true if this instruction could possibly modify memory.
+ /// mayStore - Return true if this instruction could possibly modify memory.
/// Instructions with this flag set are not necessarily simple store
/// instructions, they may store a modified value based on their operands, or
/// may not actually modify anything, for example.
- bool isStore(MachineOpCode Opcode) const {
-return get(Opcode).Flags & M_STORE_FLAG;
+ bool mayStore(MachineOpCode Opcode) const {
+return get(Opcode).Flags & M_MAY_STORE_FLAG;
}
/// hasDelaySlot - Returns true if the specified instruction has a delay slot
Modified: llvm/trunk/include/llvm/Transforms/Scalar.h
URL:
http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Transforms/Scalar.h?rev=45656&r1=45655&r2=45656&view=diff
==
--- llvm/trunk/include/llvm/Transforms/Scalar.h (original)
+++ llvm/trunk/include/llvm/Transforms/Scalar.h Sun Jan 6 02:36:04 2008
@@ -339,6 +339,12 @@
//===--===//
//
+// ValueInfo - This pass performs FIXME
+//
+FunctionPass *createValueInfoPass();
+
+//===--===//
+//
// CodeGenPrepare - This pass prepares a function for instruction selection.
//
FunctionPass *createCodeGenPreparePass(const TargetLowering *TLI = 0);
Modified: llvm/trunk/lib/CodeGen/BranchFolding.cpp
URL:
http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/BranchFolding.cpp?rev=45656&r1=45655&r2=45656&view=diff
==
--- llvm/trunk/lib/CodeGen/BranchFolding.cpp (original)
+++ llvm/trunk/lib/CodeGen/BranchFolding.cpp Sun Jan 6 02:36:04 2008
@@ -353,7 +353,7 @@
const TargetInstrDescriptor &TID = TII->get(I->getOpcode());
if (TID.Flags & M_CALL_FLAG)
Time += 10;
-else if (TID.Flags & (M_LOAD_FLAG|M_STORE_FLAG))
+else if (TID.Flags & (M_LOAD_FLAG|M_MAY_STORE_FLAG))
[llvm-commits] [llvm] r45657 - in /llvm/trunk: include/llvm/InstrTypes.h lib/Transforms/Scalar/InstructionCombining.cpp lib/VMCore/Instructions.cpp test/Transforms/InstCombine/2008-01-06-CastCrash.ll
Author: baldrick
Date: Sun Jan 6 04:12:28 2008
New Revision: 45657
URL: http://llvm.org/viewvc/llvm-project?rev=45657&view=rev
Log:
When transforming a call to a bitcast function into
a direct call with cast parameters and cast return
value (if any), instcombine was prepared to cast any
non-void return value into any other, whether castable
or not. Add a new predicate for testing whether casting
is valid, and check it both for the return value and
(as a cleanup) for the parameters.
Added:
llvm/trunk/test/Transforms/InstCombine/2008-01-06-CastCrash.ll
llvm/trunk/test/Transforms/InstCombine/2008-01-06-VoidCast.ll
Modified:
llvm/trunk/include/llvm/InstrTypes.h
llvm/trunk/lib/Transforms/Scalar/InstructionCombining.cpp
llvm/trunk/lib/VMCore/Instructions.cpp
Modified: llvm/trunk/include/llvm/InstrTypes.h
URL:
http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/InstrTypes.h?rev=45657&r1=45656&r2=45657&view=diff
==
--- llvm/trunk/include/llvm/InstrTypes.h (original)
+++ llvm/trunk/include/llvm/InstrTypes.h Sun Jan 6 04:12:28 2008
@@ -398,8 +398,14 @@
BasicBlock *InsertAtEnd ///< The block to insert the instruction into
);
+ /// @brief Check whether it is valid to call getCastOpcode for these types.
+ static bool isCastable(
+const Type *SrcTy, ///< The Type from which the value should be cast.
+const Type *DestTy ///< The Type to which the value should be cast.
+ );
+
/// Returns the opcode necessary to cast Val into Ty using usual casting
- /// rules.
+ /// rules.
/// @brief Infer the opcode for cast operand and type
static Instruction::CastOps getCastOpcode(
const Value *Val, ///< The value to cast
Modified: llvm/trunk/lib/Transforms/Scalar/InstructionCombining.cpp
URL:
http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/Scalar/InstructionCombining.cpp?rev=45657&r1=45656&r2=45657&view=diff
==
--- llvm/trunk/lib/Transforms/Scalar/InstructionCombining.cpp (original)
+++ llvm/trunk/lib/Transforms/Scalar/InstructionCombining.cpp Sun Jan 6
04:12:28 2008
@@ -8082,11 +8082,7 @@
const FunctionType *FT = Callee->getFunctionType();
const Type *OldRetTy = Caller->getType();
- const ParamAttrsList* CallerPAL = 0;
- if (CallInst *CallerCI = dyn_cast(Caller))
-CallerPAL = CallerCI->getParamAttrs();
- else if (InvokeInst *CallerII = dyn_cast(Caller))
-CallerPAL = CallerII->getParamAttrs();
+ const ParamAttrsList* CallerPAL = CS.getParamAttrs();
// If the parameter attributes are not compatible, don't do the xform. We
// don't want to lose an sret attribute or something.
@@ -8101,6 +8097,12 @@
TD->getIntPtrType() == OldRetTy))
return false; // Cannot transform this return value.
+if (!Caller->use_empty() &&
+!CastInst::isCastable(FT->getReturnType(), OldRetTy) &&
+// void -> non-void is handled specially
+FT->getReturnType() != Type::VoidTy)
+ return false; // Cannot transform this return value.
+
// If the callsite is an invoke instruction, and the return value is used
by
// a PHI node in a successor, we cannot change the return type of the call
// because there is no place to put the cast instruction (without breaking
@@ -8122,9 +8124,13 @@
for (unsigned i = 0, e = NumCommonArgs; i != e; ++i, ++AI) {
const Type *ParamTy = FT->getParamType(i);
const Type *ActTy = (*AI)->getType();
+
+if (!CastInst::isCastable(ActTy, ParamTy))
+ return false;
+
ConstantInt *c = dyn_cast(*AI);
-//Some conversions are safe even if we do not have a body.
-//Either we can cast directly, or we can upconvert the argument
+// Some conversions are safe even if we do not have a body.
+// Either we can cast directly, or we can upconvert the argument
bool isConvertible = ActTy == ParamTy ||
(isa(ParamTy) && isa(ActTy)) ||
(ParamTy->isInteger() && ActTy->isInteger() &&
@@ -8132,40 +8138,6 @@
(c && ParamTy->getPrimitiveSizeInBits() >=
ActTy->getPrimitiveSizeInBits()
&& c->getValue().isStrictlyPositive());
if (Callee->isDeclaration() && !isConvertible) return false;
-
-// Most other conversions can be done if we have a body, even if these
-// lose information, e.g. int->short.
-// Some conversions cannot be done at all, e.g. float to pointer.
-// Logic here parallels CastInst::getCastOpcode (the design there
-// requires legality checks like this be done before calling it).
-if (ParamTy->isInteger()) {
- if (const VectorType *VActTy = dyn_cast(ActTy)) {
-if (VActTy->getBitWidth() != ParamTy->getPrimitiveSizeInBits())
- return false;
- }
- if (!ActTy->isInteger() && !ActTy->isFloatingPoint() &&
- !isa(ActTy))
-return false;
-} else if (ParamTy->isFloatingPoint()) {
Re: [llvm-commits] [llvm] r45027 - in /llvm/trunk: include/llvm/IntrinsicsX86.td lib/VMCore/AutoUpgrade.cpp test/Assembler/AutoUpgradeIntrinsics.ll
Here's a potential patch as a follow-up for this patch:
mmx.patch
Description: Binary data
It's not tested (I got a compiler error during compilation of
LLVM...not LLVM-GCC). What do you think?
-bw
On Dec 13, 2007, at 10:38 PM, Anders Carlsson wrote:
Author: andersca
Date: Fri Dec 14 00:38:54 2007
New Revision: 45027
URL: http://llvm.org/viewvc/llvm-project?rev=45027&view=rev
Log:
All MMX shift instructions took a <2 x i32> vector as the shift
amount parameter. Change this to be <1 x i64> instead, which
matches the assembler instruction.
Modified:
llvm/trunk/include/llvm/IntrinsicsX86.td
llvm/trunk/lib/VMCore/AutoUpgrade.cpp
llvm/trunk/test/Assembler/AutoUpgradeIntrinsics.ll
Modified: llvm/trunk/include/llvm/IntrinsicsX86.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/
IntrinsicsX86.td?rev=45027&r1=45026&r2=45027&view=diff
==
--- llvm/trunk/include/llvm/IntrinsicsX86.td (original)
+++ llvm/trunk/include/llvm/IntrinsicsX86.td Fri Dec 14 00:38:54 2007
@@ -767,30 +767,30 @@
// Shift left logical
def int_x86_mmx_psll_w : GCCBuiltin<"__builtin_ia32_psllw">,
Intrinsic<[llvm_v4i16_ty, llvm_v4i16_ty,
- llvm_v2i32_ty], [IntrNoMem]>;
+ llvm_v1i64_ty], [IntrNoMem]>;
def int_x86_mmx_psll_d : GCCBuiltin<"__builtin_ia32_pslld">,
Intrinsic<[llvm_v2i32_ty, llvm_v2i32_ty,
- llvm_v2i32_ty], [IntrNoMem]>;
+ llvm_v1i64_ty], [IntrNoMem]>;
def int_x86_mmx_psll_q : GCCBuiltin<"__builtin_ia32_psllq">,
Intrinsic<[llvm_v1i64_ty, llvm_v1i64_ty,
- llvm_v2i32_ty], [IntrNoMem]>;
+ llvm_v1i64_ty], [IntrNoMem]>;
def int_x86_mmx_psrl_w : GCCBuiltin<"__builtin_ia32_psrlw">,
Intrinsic<[llvm_v4i16_ty, llvm_v4i16_ty,
- llvm_v2i32_ty], [IntrNoMem]>;
+ llvm_v1i64_ty], [IntrNoMem]>;
def int_x86_mmx_psrl_d : GCCBuiltin<"__builtin_ia32_psrld">,
Intrinsic<[llvm_v2i32_ty, llvm_v2i32_ty,
- llvm_v2i32_ty], [IntrNoMem]>;
+ llvm_v1i64_ty], [IntrNoMem]>;
def int_x86_mmx_psrl_q : GCCBuiltin<"__builtin_ia32_psrlq">,
Intrinsic<[llvm_v1i64_ty, llvm_v1i64_ty,
- llvm_v2i32_ty], [IntrNoMem]>;
+ llvm_v1i64_ty], [IntrNoMem]>;
def int_x86_mmx_psra_w : GCCBuiltin<"__builtin_ia32_psraw">,
Intrinsic<[llvm_v4i16_ty, llvm_v4i16_ty,
- llvm_v2i32_ty], [IntrNoMem]>;
+ llvm_v1i64_ty], [IntrNoMem]>;
def int_x86_mmx_psra_d : GCCBuiltin<"__builtin_ia32_psrad">,
Intrinsic<[llvm_v2i32_ty, llvm_v2i32_ty,
- llvm_v2i32_ty], [IntrNoMem]>;
+ llvm_v1i64_ty], [IntrNoMem]>;
}
// Pack ops.
Modified: llvm/trunk/lib/VMCore/AutoUpgrade.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/VMCore/
AutoUpgrade.cpp?rev=45027&r1=45026&r2=45027&view=diff
==
--- llvm/trunk/lib/VMCore/AutoUpgrade.cpp (original)
+++ llvm/trunk/lib/VMCore/AutoUpgrade.cpp Fri Dec 14 00:38:54 2007
@@ -12,6 +12,7 @@
//
===---
---===//
#include "llvm/AutoUpgrade.h"
+#include "llvm/Constants.h"
#include "llvm/Function.h"
#include "llvm/Module.h"
#include "llvm/Instructions.h"
@@ -110,6 +111,39 @@
}
break;
+ case 'x':
+// This fixes all MMX shift intrinsic instructions to take a
+// v1i64 instead of a v2i32 as the second parameter.
+if (Name.compare(5,10,"x86.mmx.ps",10) == 0 &&
+(Name.compare(13,4,"psll", 4) == 0 ||
+ Name.compare(13,4,"psra", 4) == 0 ||
+ Name.compare(13,4,"psrl", 4) == 0)) {
+
+ const llvm::Type *VT = VectorType::get(IntegerType::get(64),
1);
+
+ // We don't have to do anything if the parameter already has
+ // the correct type.
+ if (FTy->getParamType(1) == VT)
+break;
+
+ // We first need to change the name of the old (bad)
intrinsic, because
+ // its type is incorrect, but we cannot overload that name. We
+ // arbitrarily unique it here allowing us to construct a
correctly named
+ // and typed function below.
+ F->setName("");
+
+ assert(FTy->getNumParams() == 2 && "MMX shift intrinsics
take 2 args!");
+
+ // Now construct the new intrinsic with the correct name
and type. We
+ // leave the old function around in order to query its
type, whatever it
+ // may be, and correctly convert up to the new type.
+ return cast(M->getOrInsertFunction(Name,
+ FTy-
>getReturnType(),
+
[llvm-commits] [llvm] r45658 - in /llvm/trunk: include/llvm/ParameterAttributes.h lib/Transforms/IPO/DeadArgumentElimination.cpp lib/Transforms/Scalar/InstructionCombining.cpp lib/VMCore/ParameterAttr
Author: baldrick
Date: Sun Jan 6 12:27:01 2008
New Revision: 45658
URL: http://llvm.org/viewvc/llvm-project?rev=45658&view=rev
Log:
The transform that tries to turn calls to bitcast functions into
direct calls bails out unless caller and callee have essentially
equivalent parameter attributes. This is illogical - the callee's
attributes should be of no relevance here. Rework the logic, which
incidentally fixes a crash when removed arguments have attributes.
Added:
llvm/trunk/test/Transforms/InstCombine/2008-01-06-BitCastAttributes.ll
Modified:
llvm/trunk/include/llvm/ParameterAttributes.h
llvm/trunk/lib/Transforms/IPO/DeadArgumentElimination.cpp
llvm/trunk/lib/Transforms/Scalar/InstructionCombining.cpp
llvm/trunk/lib/VMCore/ParameterAttributes.cpp
llvm/trunk/lib/VMCore/Verifier.cpp
Modified: llvm/trunk/include/llvm/ParameterAttributes.h
URL:
http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/ParameterAttributes.h?rev=45658&r1=45657&r2=45658&view=diff
==
--- llvm/trunk/include/llvm/ParameterAttributes.h (original)
+++ llvm/trunk/include/llvm/ParameterAttributes.h Sun Jan 6 12:27:01 2008
@@ -22,6 +22,8 @@
#include
namespace llvm {
+class Type;
+
namespace ParamAttr {
/// Function parameters and results can have attributes to indicate how they
@@ -44,13 +46,6 @@
ReadOnly = 1 << 10 ///< Function only reads from memory
};
-/// These attributes can safely be dropped from a function or a function call:
-/// doing so may reduce the number of optimizations performed, but it will not
-/// change a correct program into an incorrect one.
-/// @brief Attributes that do not change the calling convention.
-const uint16_t Informative = NoReturn | NoUnwind | NoAlias |
- ReadNone | ReadOnly;
-
/// @brief Attributes that only apply to function parameters.
const uint16_t ParameterOnly = ByVal | InReg | Nest | StructRet;
@@ -63,10 +58,6 @@
/// @brief Attributes that only apply to pointers.
const uint16_t PointerTypeOnly = ByVal | Nest | NoAlias | StructRet;
-/// @brief Attributes that do not apply to void type function return values.
-const uint16_t VoidTypeIncompatible = IntegerTypeOnly | PointerTypeOnly |
- ParameterOnly;
-
/// @brief Attributes that are mutually incompatible.
const uint16_t MutuallyIncompatible[3] = {
ByVal | InReg | Nest | StructRet,
@@ -74,6 +65,9 @@
ReadNone | ReadOnly
};
+/// @brief Which of the given attributes do not apply to the type.
+uint16_t incompatibleWithType (const Type *Ty, uint16_t attrs);
+
} // end namespace ParamAttr
/// This is just a pair of values to associate a set of parameter attributes
@@ -158,11 +152,6 @@
static const ParamAttrsList *excludeAttrs(const ParamAttrsList *PAL,
uint16_t idx, uint16_t attrs);
-/// Returns whether each of the specified lists of attributes can be safely
-/// replaced with the other in a function or a function call.
-/// @brief Whether one attribute list can safely replace the other.
-static bool areCompatible(const ParamAttrsList *A, const ParamAttrsList
*B);
-
/// @}
/// @name Accessors
/// @{
Modified: llvm/trunk/lib/Transforms/IPO/DeadArgumentElimination.cpp
URL:
http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/IPO/DeadArgumentElimination.cpp?rev=45658&r1=45657&r2=45658&view=diff
==
--- llvm/trunk/lib/Transforms/IPO/DeadArgumentElimination.cpp (original)
+++ llvm/trunk/lib/Transforms/IPO/DeadArgumentElimination.cpp Sun Jan 6
12:27:01 2008
@@ -505,7 +505,7 @@
const Type *RetTy = FTy->getReturnType();
if (DeadRetVal.count(F)) {
RetTy = Type::VoidTy;
-RAttrs &= ~ParamAttr::VoidTypeIncompatible;
+RAttrs &= ~ParamAttr::incompatibleWithType(RetTy, RAttrs);
DeadRetVal.erase(F);
}
@@ -561,8 +561,7 @@
// The call return attributes.
uint16_t RAttrs = PAL ? PAL->getParamAttrs(0) : 0;
// Adjust in case the function was changed to return void.
-if (NF->getReturnType() == Type::VoidTy)
- RAttrs &= ~ParamAttr::VoidTypeIncompatible;
+RAttrs &= ~ParamAttr::incompatibleWithType(NF->getReturnType(), RAttrs);
if (RAttrs)
ParamAttrsVec.push_back(ParamAttrsWithIndex::get(0, RAttrs));
Modified: llvm/trunk/lib/Transforms/Scalar/InstructionCombining.cpp
URL:
http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/Scalar/InstructionCombining.cpp?rev=45658&r1=45657&r2=45658&view=diff
==
--- llvm/trunk/lib/Transforms/Scalar/InstructionCombining.cpp (original)
+++ llvm/trunk/lib/Transforms/Scalar/InstructionCombining.cpp Sun Jan 6
12:27:01 2008
@@ -8074,6 +8074,7 @@
return false;
Function *Callee = cast(CE->getOperand(0));
[llvm-commits] [llvm] r45659 - /llvm/trunk/include/llvm/LinkAllPasses.h
Author: lattner Date: Sun Jan 6 13:18:52 2008 New Revision: 45659 URL: http://llvm.org/viewvc/llvm-project?rev=45659&view=rev Log: fix an accidental commit that broke all the testers :( Modified: llvm/trunk/include/llvm/LinkAllPasses.h Modified: llvm/trunk/include/llvm/LinkAllPasses.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/LinkAllPasses.h?rev=45659&r1=45658&r2=45659&view=diff == --- llvm/trunk/include/llvm/LinkAllPasses.h (original) +++ llvm/trunk/include/llvm/LinkAllPasses.h Sun Jan 6 13:18:52 2008 @@ -114,7 +114,6 @@ (void) llvm::createPredicateSimplifierPass(); (void) llvm::createCodeGenPreparePass(); (void) llvm::createGVNPass(); - (void) llvm::createValueInfoPass(); (void)new llvm::IntervalPartition(); (void)new llvm::FindUsedTypes(); ___ llvm-commits mailing list llvm-commits@cs.uiuc.edu http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
[llvm-commits] [llvm] r45660 - /llvm/trunk/include/llvm/Transforms/Scalar.h
Author: lattner Date: Sun Jan 6 13:19:32 2008 New Revision: 45660 URL: http://llvm.org/viewvc/llvm-project?rev=45660&view=rev Log: back out accidental commit. Modified: llvm/trunk/include/llvm/Transforms/Scalar.h Modified: llvm/trunk/include/llvm/Transforms/Scalar.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Transforms/Scalar.h?rev=45660&r1=45659&r2=45660&view=diff == --- llvm/trunk/include/llvm/Transforms/Scalar.h (original) +++ llvm/trunk/include/llvm/Transforms/Scalar.h Sun Jan 6 13:19:32 2008 @@ -339,12 +339,6 @@ //===--===// // -// ValueInfo - This pass performs FIXME -// -FunctionPass *createValueInfoPass(); - -//===--===// -// // CodeGenPrepare - This pass prepares a function for instruction selection. // FunctionPass *createCodeGenPreparePass(const TargetLowering *TLI = 0); ___ llvm-commits mailing list llvm-commits@cs.uiuc.edu http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
[llvm-commits] [llvm] r45661 - /llvm/trunk/docs/LangRef.html
Author: lattner Date: Sun Jan 6 13:51:52 2008 New Revision: 45661 URL: http://llvm.org/viewvc/llvm-project?rev=45661&view=rev Log: Fix typo noticed by 'Danny' in PR1901 Modified: llvm/trunk/docs/LangRef.html Modified: llvm/trunk/docs/LangRef.html URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/docs/LangRef.html?rev=45661&r1=45660&r2=45661&view=diff == --- llvm/trunk/docs/LangRef.html (original) +++ llvm/trunk/docs/LangRef.html Sun Jan 6 13:51:52 2008 @@ -4498,7 +4498,7 @@ The 'llvm.memmove.*' intrinsics move a block of memory from the source location to the destination location. It is similar to the -'llvm.memcmp' intrinsic but allows the two memory locations to overlap. +'llvm.memcpy' intrinsic but allows the two memory locations to overlap. ___ llvm-commits mailing list llvm-commits@cs.uiuc.edu http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
[llvm-commits] CVS: llvm-www/OpenProjects.html
Changes in directory llvm-www: OpenProjects.html updated: 1.31 -> 1.32 --- Log message: add some open projects. --- Diffs of the changes: (+13 -1) OpenProjects.html | 14 +- 1 files changed, 13 insertions(+), 1 deletion(-) Index: llvm-www/OpenProjects.html diff -u llvm-www/OpenProjects.html:1.31 llvm-www/OpenProjects.html:1.32 --- llvm-www/OpenProjects.html:1.31 Tue Nov 27 15:10:27 2007 +++ llvm-www/OpenProjects.html Sun Jan 6 14:07:10 2008 @@ -339,6 +339,18 @@ +Implement 'stack slot coloring' to allocate two frame indexes to the same +stack offset if their live ranges don't overlap. This can reuse a bunch of +analysis machinery from LiveIntervals. Making the stack smaller is good +for cache use and very important on targets where loads have limited +displacement like ppc, thumb, mips, sparc, etc. This should be done as +a pass before prolog epilog insertion. +Implement 'shrink wrapping', which is the intelligent placement of callee +saved register save/restores. Right now PrologEpilogInsertion always saves +every (modified) callee save reg in the prolog and restores it in the +epilog. However, some paths through a function (e.g. an early exit) may +not use all regs. Sinking the save down the CFG avoids useless work on +these paths. Rename ISD::BIT_CONVERT to ISD::BITCAST to match the llvm ir concept Change the VECTOR_SHUFFLE to be variadic. Right now, a VECTOR_SHUFFLE takes three operands: two vectors and a shuffle mask. The shuffle mask is @@ -407,7 +419,7 @@ src="http://www.w3.org/Icons/valid-html401"; alt="Valid HTML 4.01!"> http://llvm.org";>LLVM Compiler Infrastructure - Last modified: $Date: 2007/11/27 21:10:27 $ + Last modified: $Date: 2008/01/06 20:07:10 $ ___ llvm-commits mailing list llvm-commits@cs.uiuc.edu http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
[llvm-commits] [llvm] r45662 - /llvm/trunk/docs/LangRef.html
Author: lattner Date: Sun Jan 6 15:04:43 2008 New Revision: 45662 URL: http://llvm.org/viewvc/llvm-project?rev=45662&view=rev Log: improve description of alignment, patch by Alain Frisch. Modified: llvm/trunk/docs/LangRef.html Modified: llvm/trunk/docs/LangRef.html URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/docs/LangRef.html?rev=45662&r1=45661&r2=45662&view=diff == --- llvm/trunk/docs/LangRef.html (original) +++ llvm/trunk/docs/LangRef.html Sun Jan 6 15:04:43 2008 @@ -2843,6 +2843,16 @@ the number or order of execution of this load with other volatile load and store instructions. + +The optional "align" argument specifies the alignment of the operation +(that is, the alignment of the memory address). A value of 0 or an +omitted "align" argument means that the operation has the preferential +alignment for the target. It is the responsibility of the code emitter +to ensure that the alignment information is correct. Overestimating +the alignment results in an undefined behavior. Underestimating the +alignment may produce less efficient code. An alignment of 1 is always +safe. + Semantics: The location of memory pointed to is loaded. Examples: @@ -2870,6 +2880,16 @@ optimizer is not allowed to modify the number or order of execution of this store with other volatile load and store instructions. + +The optional "align" argument specifies the alignment of the operation +(that is, the alignment of the memory address). A value of 0 or an +omitted "align" argument means that the operation has the preferential +alignment for the target. It is the responsibility of the code emitter +to ensure that the alignment information is correct. Overestimating +the alignment results in an undefined behavior. Underestimating the +alignment may produce less efficient code. An alignment of 1 is always +safe. + Semantics: The contents of memory are updated to contain '' at the location specified by the ' ' operand. ___ llvm-commits mailing list llvm-commits@cs.uiuc.edu http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
[llvm-commits] [llvm] r45663 - in /llvm/trunk: Makefile.rules bindings/ocaml/Makefile.ocaml
Author: gordon Date: Sun Jan 6 15:54:35 2008 New Revision: 45663 URL: http://llvm.org/viewvc/llvm-project?rev=45663&view=rev Log: Modify Makefile.rules to allow makefiles to prepend to C.Flags and fiends. Change Makefile.ocaml to not touch CFLAGS. Modified: llvm/trunk/Makefile.rules llvm/trunk/bindings/ocaml/Makefile.ocaml Modified: llvm/trunk/Makefile.rules URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/Makefile.rules?rev=45663&r1=45662&r2=45663&view=diff == --- llvm/trunk/Makefile.rules (original) +++ llvm/trunk/Makefile.rules Sun Jan 6 15:54:35 2008 @@ -210,9 +210,9 @@ ifdef ENABLE_PROFILING BuildMode := Profile - CXX.Flags := $(OPTIMIZE_OPTION) -pg -g - C.Flags := $(OPTIMIZE_OPTION) -pg -g - LD.Flags := $(OPTIMIZE_OPTION) -pg -g + CXX.Flags += $(OPTIMIZE_OPTION) -pg -g + C.Flags += $(OPTIMIZE_OPTION) -pg -g + LD.Flags += $(OPTIMIZE_OPTION) -pg -g KEEP_SYMBOLS := 1 else ifeq ($(ENABLE_OPTIMIZED),1) @@ -229,14 +229,14 @@ EXTRA_OPTIONS += -fstrict-aliasing endif -CXX.Flags := $(OPTIMIZE_OPTION) $(OmitFramePointer) -C.Flags := $(OPTIMIZE_OPTION) $(OmitFramePointer) -LD.Flags := $(OPTIMIZE_OPTION) +CXX.Flags += $(OPTIMIZE_OPTION) $(OmitFramePointer) +C.Flags += $(OPTIMIZE_OPTION) $(OmitFramePointer) +LD.Flags += $(OPTIMIZE_OPTION) else BuildMode := Debug -CXX.Flags := -g -C.Flags := -g -LD.Flags := -g +CXX.Flags += -g +C.Flags += -g +LD.Flags += -g KEEP_SYMBOLS := 1 endif endif Modified: llvm/trunk/bindings/ocaml/Makefile.ocaml URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/bindings/ocaml/Makefile.ocaml?rev=45663&r1=45662&r2=45663&view=diff == --- llvm/trunk/bindings/ocaml/Makefile.ocaml (original) +++ llvm/trunk/bindings/ocaml/Makefile.ocaml Sun Jan 6 15:54:35 2008 @@ -20,7 +20,8 @@ include $(LEVEL)/Makefile.config # CFLAGS needs to be set before Makefile.rules is included. -CFLAGS += -I"$(shell $(OCAMLC) -where)" +CXX.Flags += -I"$(shell $(OCAMLC) -where)" +C.Flags += -I"$(shell $(OCAMLC) -where)" include $(LEVEL)/Makefile.common ___ llvm-commits mailing list llvm-commits@cs.uiuc.edu http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
[llvm-commits] [llvm] r45667 - in /llvm/trunk: include/llvm/Target/ lib/CodeGen/ lib/Target/ lib/Target/ARM/ lib/Target/Alpha/ lib/Target/CellSPU/ lib/Target/IA64/ lib/Target/Mips/ lib/Target/PowerPC/
Author: lattner
Date: Sun Jan 6 17:38:27 2008
New Revision: 45667
URL: http://llvm.org/viewvc/llvm-project?rev=45667&view=rev
Log:
rename isLoad -> isSimpleLoad due to evan's desire to have such a predicate.
Modified:
llvm/trunk/include/llvm/Target/TargetInstrInfo.h
llvm/trunk/lib/CodeGen/BranchFolding.cpp
llvm/trunk/lib/CodeGen/LiveIntervalAnalysis.cpp
llvm/trunk/lib/Target/ARM/ARMInstrInfo.cpp
llvm/trunk/lib/Target/ARM/ARMInstrInfo.td
llvm/trunk/lib/Target/ARM/ARMInstrThumb.td
llvm/trunk/lib/Target/ARM/ARMInstrVFP.td
llvm/trunk/lib/Target/ARM/ARMRegisterInfo.cpp
llvm/trunk/lib/Target/Alpha/AlphaInstrFormats.td
llvm/trunk/lib/Target/Alpha/AlphaInstrInfo.td
llvm/trunk/lib/Target/CellSPU/SPUInstrInfo.td
llvm/trunk/lib/Target/IA64/IA64InstrInfo.td
llvm/trunk/lib/Target/Mips/MipsInstrInfo.td
llvm/trunk/lib/Target/PowerPC/PPCHazardRecognizers.cpp
llvm/trunk/lib/Target/PowerPC/PPCInstr64Bit.td
llvm/trunk/lib/Target/PowerPC/PPCInstrAltivec.td
llvm/trunk/lib/Target/PowerPC/PPCInstrInfo.td
llvm/trunk/lib/Target/Target.td
llvm/trunk/lib/Target/X86/X86InstrFPStack.td
llvm/trunk/lib/Target/X86/X86InstrInfo.td
llvm/trunk/lib/Target/X86/X86InstrMMX.td
llvm/trunk/lib/Target/X86/X86InstrSSE.td
llvm/trunk/lib/Target/X86/X86InstrX86-64.td
llvm/trunk/utils/TableGen/CodeGenInstruction.cpp
llvm/trunk/utils/TableGen/CodeGenInstruction.h
llvm/trunk/utils/TableGen/InstrInfoEmitter.cpp
Modified: llvm/trunk/include/llvm/Target/TargetInstrInfo.h
URL:
http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Target/TargetInstrInfo.h?rev=45667&r1=45666&r2=45667&view=diff
==
--- llvm/trunk/include/llvm/Target/TargetInstrInfo.h (original)
+++ llvm/trunk/include/llvm/Target/TargetInstrInfo.h Sun Jan 6 17:38:27 2008
@@ -48,7 +48,11 @@
const unsigned M_RET_FLAG = 1 << 2;
const unsigned M_BARRIER_FLAG = 1 << 3;
const unsigned M_DELAY_SLOT_FLAG = 1 << 4;
-const unsigned M_LOAD_FLAG = 1 << 5;
+
+/// M_SIMPLE_LOAD_FLAG - This flag is set for instructions that are simple
loads
+/// from memory. This should only be set on instructions that load a value
from
+/// memory and return it in their only virtual register definition.
+const unsigned M_SIMPLE_LOAD_FLAG = 1 << 5;
/// M_MAY_STORE_FLAG - This flag is set to any instruction that could possibly
/// modify memory. Instructions with this flag set are not necessarily simple
@@ -184,6 +188,17 @@
/// findTiedToSrcOperand - Returns the operand that is tied to the specified
/// dest operand. Returns -1 if there isn't one.
int findTiedToSrcOperand(unsigned OpNum) const;
+
+
+ /// isSimpleLoad - Return true for instructions that are simple loads from
+ /// memory. This should only be set on instructions that load a value from
+ /// memory and return it in their only virtual register definition.
+ /// Instructions that return a value loaded from memory and then modified in
+ /// some way should not return true for this.
+ bool isSimpleLoad() const {
+return Flags & M_SIMPLE_LOAD_FLAG;
+ }
+
};
@@ -279,9 +294,6 @@
bool isCall(MachineOpCode Opcode) const {
return get(Opcode).Flags & M_CALL_FLAG;
}
- bool isLoad(MachineOpCode Opcode) const {
-return get(Opcode).Flags & M_LOAD_FLAG;
- }
/// mayStore - Return true if this instruction could possibly modify memory.
/// Instructions with this flag set are not necessarily simple store
Modified: llvm/trunk/lib/CodeGen/BranchFolding.cpp
URL:
http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/BranchFolding.cpp?rev=45667&r1=45666&r2=45667&view=diff
==
--- llvm/trunk/lib/CodeGen/BranchFolding.cpp (original)
+++ llvm/trunk/lib/CodeGen/BranchFolding.cpp Sun Jan 6 17:38:27 2008
@@ -353,7 +353,7 @@
const TargetInstrDescriptor &TID = TII->get(I->getOpcode());
if (TID.Flags & M_CALL_FLAG)
Time += 10;
-else if (TID.Flags & (M_LOAD_FLAG|M_MAY_STORE_FLAG))
+else if (TID.isSimpleLoad() || (TID.Flags & M_MAY_STORE_FLAG))
Time += 2;
else
++Time;
Modified: llvm/trunk/lib/CodeGen/LiveIntervalAnalysis.cpp
URL:
http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/LiveIntervalAnalysis.cpp?rev=45667&r1=45666&r2=45667&view=diff
==
--- llvm/trunk/lib/CodeGen/LiveIntervalAnalysis.cpp (original)
+++ llvm/trunk/lib/CodeGen/LiveIntervalAnalysis.cpp Sun Jan 6 17:38:27 2008
@@ -618,7 +618,7 @@
const TargetInstrDescriptor *TID = MI->getInstrDescriptor();
if ((TID->Flags & M_IMPLICIT_DEF_FLAG) ||
tii_->isTriviallyReMaterializable(MI)) {
-isLoad = TID->Flags & M_LOAD_FLAG;
+isLoad = TID->isSimpleLoad();
return true;
}
@@ -1226,7 +1226,7 @@
int L
[llvm-commits] [llvm] r45668 - /llvm/trunk/lib/Target/X86/X86InstrInfo.td
Author: lattner
Date: Sun Jan 6 17:49:32 2008
New Revision: 45668
URL: http://llvm.org/viewvc/llvm-project?rev=45668&view=rev
Log:
The pic base can't be duplicated.
Modified:
llvm/trunk/lib/Target/X86/X86InstrInfo.td
Modified: llvm/trunk/lib/Target/X86/X86InstrInfo.td
URL:
http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrInfo.td?rev=45668&r1=45667&r2=45668&view=diff
==
--- llvm/trunk/lib/Target/X86/X86InstrInfo.td (original)
+++ llvm/trunk/lib/Target/X86/X86InstrInfo.td Sun Jan 6 17:49:32 2008
@@ -282,7 +282,7 @@
def NOOP : I<0x90, RawFrm, (outs), (ins), "nop", []>;
// PIC base
-let neverHasSideEffects = 1 in {
+let neverHasSideEffects = 1, isNotDuplicable = 1 in {
def MOVPC32r : Ii32<0xE8, Pseudo, (outs GR32:$reg), (ins piclabel:$label),
"call\t$label\n\tpop{l}\t$reg", []>;
}
___
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[llvm-commits] [llvm] r45670 - in /llvm/trunk: include/llvm/CodeGen/LinkAllCodegenComponents.h include/llvm/LinkAllPasses.h include/llvm/Transforms/Scalar.h lib/CodeGen/ShadowStackCollector.cpp lib/Tr
Author: gordon
Date: Sun Jan 6 19:30:53 2008
New Revision: 45670
URL: http://llvm.org/viewvc/llvm-project?rev=45670&view=rev
Log:
With this patch, the LowerGC transformation becomes the
ShadowStackCollector, which additionally has reduced overhead with
no sacrifice in portability.
Considering a function @fun with 8 loop-local roots,
ShadowStackCollector introduces the following overhead
(x86):
; shadowstack prologue
movlL_llvm_gc_root_chain$non_lazy_ptr, %eax
movl(%eax), %ecx
movl$___gc_fun, 20(%esp)
movl$0, 24(%esp)
movl$0, 28(%esp)
movl$0, 32(%esp)
movl$0, 36(%esp)
movl$0, 40(%esp)
movl$0, 44(%esp)
movl$0, 48(%esp)
movl$0, 52(%esp)
movl%ecx, 16(%esp)
leal16(%esp), %ecx
movl%ecx, (%eax)
; shadowstack loop overhead
(none)
; shadowstack epilogue
movl48(%esp), %edx
movl%edx, (%ecx)
; shadowstack metadata
.align 3
___gc_fun: # __gc_fun
.long 8
.space 4
In comparison to LowerGC:
; lowergc prologue
movlL_llvm_gc_root_chain$non_lazy_ptr, %eax
movl(%eax), %ecx
movl%ecx, 48(%esp)
movl$8, 52(%esp)
movl$0, 60(%esp)
movl$0, 56(%esp)
movl$0, 68(%esp)
movl$0, 64(%esp)
movl$0, 76(%esp)
movl$0, 72(%esp)
movl$0, 84(%esp)
movl$0, 80(%esp)
movl$0, 92(%esp)
movl$0, 88(%esp)
movl$0, 100(%esp)
movl$0, 96(%esp)
movl$0, 108(%esp)
movl$0, 104(%esp)
movl$0, 116(%esp)
movl$0, 112(%esp)
; lowergc loop overhead
leal44(%esp), %eax
movl%eax, 56(%esp)
leal40(%esp), %eax
movl%eax, 64(%esp)
leal36(%esp), %eax
movl%eax, 72(%esp)
leal32(%esp), %eax
movl%eax, 80(%esp)
leal28(%esp), %eax
movl%eax, 88(%esp)
leal24(%esp), %eax
movl%eax, 96(%esp)
leal20(%esp), %eax
movl%eax, 104(%esp)
leal16(%esp), %eax
movl%eax, 112(%esp)
; lowergc epilogue
movl48(%esp), %edx
movl%edx, (%ecx)
; lowergc metadata
(none)
Added:
llvm/trunk/lib/CodeGen/ShadowStackCollector.cpp
llvm/trunk/test/CodeGen/Generic/GC/redundant_init.ll
Modified:
llvm/trunk/include/llvm/CodeGen/LinkAllCodegenComponents.h
llvm/trunk/include/llvm/LinkAllPasses.h
llvm/trunk/include/llvm/Transforms/Scalar.h
llvm/trunk/lib/Transforms/Scalar/LowerGC.cpp
llvm/trunk/runtime/GC/SemiSpace/semispace.c
Modified: llvm/trunk/include/llvm/CodeGen/LinkAllCodegenComponents.h
URL:
http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/CodeGen/LinkAllCodegenComponents.h?rev=45670&r1=45669&r2=45670&view=diff
==
--- llvm/trunk/include/llvm/CodeGen/LinkAllCodegenComponents.h (original)
+++ llvm/trunk/include/llvm/CodeGen/LinkAllCodegenComponents.h Sun Jan 6
19:30:53 2008
@@ -17,6 +17,7 @@
#include "llvm/CodeGen/Passes.h"
#include "llvm/CodeGen/ScheduleDAG.h"
+#include "llvm/CodeGen/Collectors.h"
namespace {
struct ForceCodegenLinking {
@@ -35,6 +36,8 @@
(void) llvm::createSimpleRegisterCoalescer();
+ (void) llvm::createShadowStackCollector();
+
(void) llvm::createBURRListDAGScheduler(NULL, NULL, NULL);
(void) llvm::createTDRRListDAGScheduler(NULL, NULL, NULL);
(void) llvm::createTDListDAGScheduler(NULL, NULL, NULL);
Modified: llvm/trunk/include/llvm/LinkAllPasses.h
URL:
http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/LinkAllPasses.h?rev=45670&r1=45669&r2=45670&view=diff
==
--- llvm/trunk/include/llvm/LinkAllPasses.h (original)
+++ llvm/trunk/include/llvm/LinkAllPasses.h Sun Jan 6 19:30:53 2008
@@ -84,7 +84,6 @@
(void) llvm::createLoopRotatePass();
(void) llvm::createLoopIndexSplitPass();
(void) llvm::createLowerAllocationsPass();
- (void) llvm::createLowerGCPass();
(void) llvm::createLowerInvokePass();
(void) llvm::createLowerPackedPass();
(void) llvm::createLowerSelectPass();
Modified: llvm/trunk/include/llvm/Transforms/Scalar.h
URL:
http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Transforms/Scalar.h?rev=45670&r1=45669&r2=45670&view=diff
==
--- llvm/trunk/include/llvm/Transforms/Scalar.h (original)
+++ llvm/trunk/include/llvm/Transforms/Scalar.h Sun Jan 6 19:30:53 2008
@@ -296,13 +296,6 @@
//===--===//
//
-// LowerGCPass -
[llvm-commits] [llvm] r45669 - in /llvm/trunk: include/llvm/CodeGen/AsmPrinter.h include/llvm/CodeGen/SelectionDAGISel.h lib/CodeGen/AsmPrinter.cpp lib/CodeGen/README.txt lib/CodeGen/SelectionDAG/Sele
Author: gordon
Date: Sun Jan 6 19:30:38 2008
New Revision: 45669
URL: http://llvm.org/viewvc/llvm-project?rev=45669&view=rev
Log:
Enabling the target-independent garbage collection infrastructure by hooking it
up to the various compiler pipelines.
This doesn't actually add support for any GC algorithms, which means it
temporarily breaks a few tests. To be fixed shortly.
Modified:
llvm/trunk/include/llvm/CodeGen/AsmPrinter.h
llvm/trunk/include/llvm/CodeGen/SelectionDAGISel.h
llvm/trunk/lib/CodeGen/AsmPrinter.cpp
llvm/trunk/lib/CodeGen/README.txt
llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
llvm/trunk/lib/Target/CBackend/CBackend.cpp
llvm/trunk/lib/Target/MSIL/MSILWriter.cpp
Modified: llvm/trunk/include/llvm/CodeGen/AsmPrinter.h
URL:
http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/CodeGen/AsmPrinter.h?rev=45669&r1=45668&r2=45669&view=diff
==
--- llvm/trunk/include/llvm/CodeGen/AsmPrinter.h (original)
+++ llvm/trunk/include/llvm/CodeGen/AsmPrinter.h Sun Jan 6 19:30:38 2008
@@ -118,6 +118,10 @@
std::string getCurrentFunctionEHName(const MachineFunction *MF);
protected:
+/// getAnalysisUsage - Record analysis usage.
+///
+void getAnalysisUsage(AnalysisUsage &AU) const;
+
/// doInitialization - Set up the AsmPrinter when we are working on a new
/// module. If your pass overrides this, it must make sure to explicitly
/// call this implementation.
Modified: llvm/trunk/include/llvm/CodeGen/SelectionDAGISel.h
URL:
http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/CodeGen/SelectionDAGISel.h?rev=45669&r1=45668&r2=45669&view=diff
==
--- llvm/trunk/include/llvm/CodeGen/SelectionDAGISel.h (original)
+++ llvm/trunk/include/llvm/CodeGen/SelectionDAGISel.h Sun Jan 6 19:30:38 2008
@@ -30,6 +30,7 @@
class TargetLowering;
class FunctionLoweringInfo;
class HazardRecognizer;
+ class CollectorMetadata;
/// SelectionDAGISel - This is the common base class used for
SelectionDAG-based
/// pattern-matching instruction selectors.
@@ -42,10 +43,11 @@
AliasAnalysis *AA;
std::vector TopOrder;
unsigned DAGSize;
+ CollectorMetadata *GCI;
static char ID;
explicit SelectionDAGISel(TargetLowering &tli) :
-FunctionPass((intptr_t)&ID), TLI(tli), DAGSize(0) {}
+FunctionPass((intptr_t)&ID), TLI(tli), DAGSize(0), GCI(0) {}
TargetLowering &getTargetLowering() { return TLI; }
Modified: llvm/trunk/lib/CodeGen/AsmPrinter.cpp
URL:
http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/AsmPrinter.cpp?rev=45669&r1=45668&r2=45669&view=diff
==
--- llvm/trunk/lib/CodeGen/AsmPrinter.cpp (original)
+++ llvm/trunk/lib/CodeGen/AsmPrinter.cpp Sun Jan 6 19:30:38 2008
@@ -16,6 +16,8 @@
#include "llvm/DerivedTypes.h"
#include "llvm/Constants.h"
#include "llvm/Module.h"
+#include "llvm/CodeGen/Collector.h"
+#include "llvm/CodeGen/CollectorMetadata.h"
#include "llvm/CodeGen/MachineConstantPool.h"
#include "llvm/CodeGen/MachineJumpTableInfo.h"
#include "llvm/CodeGen/MachineModuleInfo.h"
@@ -94,9 +96,20 @@
}
+void AsmPrinter::getAnalysisUsage(AnalysisUsage &AU) const {
+ MachineFunctionPass::getAnalysisUsage(AU);
+ AU.addRequired();
+}
+
bool AsmPrinter::doInitialization(Module &M) {
Mang = new Mangler(M, TAI->getGlobalPrefix());
+ CollectorModuleMetadata *CMM =
getAnalysisToUpdate();
+ assert(CMM && "AsmPrinter didn't require CollectorModuleMetadata?");
+ for (CollectorModuleMetadata::iterator I = CMM->begin(),
+ E = CMM->end(); I != E; ++I)
+(*I)->beginAssembly(O, *this, *TAI);
+
if (!M.getModuleInlineAsm().empty())
O << TAI->getCommentString() << " Start of file scope inline assembly\n"
<< M.getModuleInlineAsm()
@@ -158,6 +171,12 @@
}
}
+ CollectorModuleMetadata *CMM =
getAnalysisToUpdate();
+ assert(CMM && "AsmPrinter didn't require CollectorModuleMetadata?");
+ for (CollectorModuleMetadata::iterator I = CMM->end(),
+ E = CMM->begin(); I != E; )
+(*--I)->finishAssembly(O, *this, *TAI);
+
delete Mang; Mang = 0;
return false;
}
Modified: llvm/trunk/lib/CodeGen/README.txt
URL:
http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/README.txt?rev=45669&r1=45668&r2=45669&view=diff
==
--- llvm/trunk/lib/CodeGen/README.txt (original)
+++ llvm/trunk/lib/CodeGen/README.txt Sun Jan 6 19:30:38 2008
@@ -187,3 +187,8 @@
assembly.
//===-===//
+
+It would be good to detect collector/target compatibility instead of silently
+doing the wrong thing.
+
+//===--
[llvm-commits] [llvm] r45671 - /llvm/trunk/lib/CodeGen/LLVMTargetMachine.cpp
Author: gordon
Date: Sun Jan 6 19:33:09 2008
New Revision: 45671
URL: http://llvm.org/viewvc/llvm-project?rev=45671&view=rev
Log:
Ammending r45669 with a missing file.
Modified:
llvm/trunk/lib/CodeGen/LLVMTargetMachine.cpp
Modified: llvm/trunk/lib/CodeGen/LLVMTargetMachine.cpp
URL:
http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/LLVMTargetMachine.cpp?rev=45671&r1=45670&r2=45671&view=diff
==
--- llvm/trunk/lib/CodeGen/LLVMTargetMachine.cpp (original)
+++ llvm/trunk/lib/CodeGen/LLVMTargetMachine.cpp Sun Jan 6 19:33:09 2008
@@ -17,6 +17,7 @@
#include "llvm/Assembly/PrintModulePass.h"
#include "llvm/Analysis/LoopPass.h"
#include "llvm/CodeGen/Passes.h"
+#include "llvm/CodeGen/Collector.h"
#include "llvm/Target/TargetOptions.h"
#include "llvm/Transforms/Scalar.h"
#include "llvm/Support/CommandLine.h"
@@ -28,6 +29,8 @@
cl::desc("Print LLVM IR input to isel pass"));
static cl::opt PrintEmittedAsm("print-emitted-asm", cl::Hidden,
cl::desc("Dump emitter generated instructions as assembly"));
+static cl::opt PrintGCInfo("print-gc", cl::Hidden,
+cl::desc("Dump garbage collector data"));
// Hidden options to help debugging
static cl::opt
@@ -52,8 +55,7 @@
PM.add(new PrintFunctionPass("\n\n*** Code after LSR *** \n", &cerr));
}
- // FIXME: Implement efficient support for garbage collection intrinsics.
- PM.add(createLowerGCPass());
+ PM.add(createGCLoweringPass());
if (!ExceptionHandling)
PM.add(createLowerInvokePass(getTargetLowering()));
@@ -108,6 +110,13 @@
if (!Fast)
PM.add(createBranchFoldingPass(getEnableTailMergeDefault()));
+ PM.add(createGCMachineCodeAnalysisPass());
+ if (PrintMachineCode)
+PM.add(createMachineFunctionPrinterPass(cerr));
+
+ if (PrintGCInfo)
+PM.add(createCollectorMetadataPrinter(*cerr));
+
// Fold redundant debug labels.
PM.add(createDebugLabelFoldingPass());
@@ -142,6 +151,8 @@
bool Fast) {
if (MCE)
addSimpleCodeEmitter(PM, Fast, PrintEmittedAsm, *MCE);
+
+ PM.add(createCollectorMetadataDeleter());
// Delete machine code for this function
PM.add(createMachineCodeDeleter());
@@ -167,8 +178,7 @@
PM.add(new PrintFunctionPass("\n\n*** Code after LSR *** \n", &cerr));
}
- // FIXME: Implement efficient support for garbage collection intrinsics.
- PM.add(createLowerGCPass());
+ PM.add(createGCLoweringPass());
// FIXME: Implement the invoke/unwind instructions!
PM.add(createLowerInvokePass(getTargetLowering()));
@@ -226,11 +236,20 @@
if (!Fast)
PM.add(createBranchFoldingPass(getEnableTailMergeDefault()));
+ PM.add(createGCMachineCodeAnalysisPass());
+ if (PrintMachineCode)
+PM.add(createMachineFunctionPrinterPass(cerr));
+
+ if (PrintGCInfo)
+PM.add(createCollectorMetadataPrinter(*cerr));
+
if (addPreEmitPass(PM, Fast) && PrintMachineCode)
PM.add(createMachineFunctionPrinterPass(cerr));
addCodeEmitter(PM, Fast, PrintEmittedAsm, MCE);
+ PM.add(createCollectorMetadataDeleter());
+
// Delete machine code for this function
PM.add(createMachineCodeDeleter());
___
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[llvm-commits] [llvm] r45673 - in /llvm/trunk/lib/CodeGen: LiveIntervalAnalysis.cpp RegAllocBigBlock.cpp RegAllocLocal.cpp SelectionDAG/ScheduleDAGRRList.cpp VirtRegMap.cpp
Author: resistor
Date: Sun Jan 6 19:35:56 2008
New Revision: 45673
URL: http://llvm.org/viewvc/llvm-project?rev=45673&view=rev
Log:
Update CodeGen for MRegisterInfo --> TargetInstrInfo changes.
Modified:
llvm/trunk/lib/CodeGen/LiveIntervalAnalysis.cpp
llvm/trunk/lib/CodeGen/RegAllocBigBlock.cpp
llvm/trunk/lib/CodeGen/RegAllocLocal.cpp
llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp
llvm/trunk/lib/CodeGen/VirtRegMap.cpp
Modified: llvm/trunk/lib/CodeGen/LiveIntervalAnalysis.cpp
URL:
http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/LiveIntervalAnalysis.cpp?rev=45673&r1=45672&r2=45673&view=diff
==
--- llvm/trunk/lib/CodeGen/LiveIntervalAnalysis.cpp (original)
+++ llvm/trunk/lib/CodeGen/LiveIntervalAnalysis.cpp Sun Jan 6 19:35:56 2008
@@ -709,8 +709,8 @@
FoldOps.push_back(OpIdx);
}
- MachineInstr *fmi = isSS ? mri_->foldMemoryOperand(MI, FoldOps, Slot)
- : mri_->foldMemoryOperand(MI, FoldOps, DefMI);
+ MachineInstr *fmi = isSS ? tii_->foldMemoryOperand(MI, FoldOps, Slot)
+ : tii_->foldMemoryOperand(MI, FoldOps, DefMI);
if (fmi) {
// Attempt to fold the memory reference into the instruction. If
// we can do this, we don't need to insert spill code.
@@ -746,7 +746,7 @@
FoldOps.push_back(OpIdx);
}
- return mri_->canFoldMemoryOperand(MI, FoldOps);
+ return tii_->canFoldMemoryOperand(MI, FoldOps);
}
bool LiveIntervals::intervalIsInOneMBB(const LiveInterval &li) const {
Modified: llvm/trunk/lib/CodeGen/RegAllocBigBlock.cpp
URL:
http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/RegAllocBigBlock.cpp?rev=45673&r1=45672&r2=45673&view=diff
==
--- llvm/trunk/lib/CodeGen/RegAllocBigBlock.cpp (original)
+++ llvm/trunk/lib/CodeGen/RegAllocBigBlock.cpp Sun Jan 6 19:35:56 2008
@@ -505,6 +505,7 @@
MachineInstr *RABigBlock::reloadVirtReg(MachineBasicBlock &MBB, MachineInstr
*MI,
unsigned OpNum) {
unsigned VirtReg = MI->getOperand(OpNum).getReg();
+ const TargetInstrInfo* TII = MBB.getParent()->getTarget().getInstrInfo();
// If the virtual register is already available in a physical register,
// just update the instruction and return.
@@ -525,7 +526,7 @@
// try to fold the spill into the instruction
SmallVector Ops;
Ops.push_back(OpNum);
-if(MachineInstr* FMI = RegInfo->foldMemoryOperand(MI, Ops, FrameIndex)) {
+if(MachineInstr* FMI = TII->foldMemoryOperand(MI, Ops, FrameIndex)) {
++NumFolded;
// Since we changed the address of MI, make sure to update live variables
// to know that the new instruction has the properties of the old one.
@@ -545,7 +546,6 @@
<< RegInfo->getName(PhysReg) << "\n";
// Add move instruction(s)
- const TargetInstrInfo* TII = MBB.getParent()->getTarget().getInstrInfo();
TII->loadRegFromStackSlot(MBB, MI, PhysReg, FrameIndex, RC);
++NumLoads;// Update statistics
Modified: llvm/trunk/lib/CodeGen/RegAllocLocal.cpp
URL:
http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/RegAllocLocal.cpp?rev=45673&r1=45672&r2=45673&view=diff
==
--- llvm/trunk/lib/CodeGen/RegAllocLocal.cpp (original)
+++ llvm/trunk/lib/CodeGen/RegAllocLocal.cpp Sun Jan 6 19:35:56 2008
@@ -50,6 +50,7 @@
const TargetMachine *TM;
MachineFunction *MF;
const MRegisterInfo *MRI;
+const TargetInstrInfo *TII;
LiveVariables *LV;
// StackSlotForVirtReg - Maps virtual regs to the frame index where these
@@ -478,7 +479,7 @@
// If we can fold this spill into this instruction, do so now.
SmallVector Ops;
Ops.push_back(OpNum);
-if (MachineInstr* FMI = MRI->foldMemoryOperand(MI, Ops, FrameIndex)) {
+if (MachineInstr* FMI = TII->foldMemoryOperand(MI, Ops, FrameIndex)) {
++NumFolded;
// Since we changed the address of MI, make sure to update live variables
// to know that the new instruction has the properties of the old one.
@@ -801,6 +802,7 @@
MF = &Fn;
TM = &Fn.getTarget();
MRI = TM->getRegisterInfo();
+ TII = TM->getInstrInfo();
LV = &getAnalysis();
PhysRegsUsed.assign(MRI->getNumRegs(), -1);
Modified: llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp
URL:
http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp?rev=45673&r1=45672&r2=45673&view=diff
==
--- llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp (original)
+++ llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp Sun Jan 6
19:35:56 2008
@@ -413,7 +413,7 @@
if (TryUnfold) {
SmallVector NewNodes;
-if (!MRI->unfoldMemoryOperand(DAG, N, NewNodes))
+if (!
[llvm-commits] [llvm] r45674 - in /llvm/trunk: include/llvm/CodeGen/ include/llvm/Target/ lib/CodeGen/ lib/CodeGen/SelectionDAG/ lib/Target/ lib/Target/ARM/ lib/Target/Mips/ lib/Target/PowerPC/ lib/Ta
Author: lattner
Date: Sun Jan 6 19:56:04 2008
New Revision: 45674
URL: http://llvm.org/viewvc/llvm-project?rev=45674&view=rev
Log:
Rename MachineInstr::getInstrDescriptor -> getDesc(), which reflects
that it is cheap and efficient to get.
Move a variety of predicates from TargetInstrInfo into
TargetInstrDescriptor, which makes it much easier to query a predicate
when you don't have TII around. Now you can use MI->getDesc()->isBranch()
instead of going through TII, and this is much more efficient anyway. Not
all of the predicates have been moved over yet.
Update old code that used MI->getInstrDescriptor()->Flags to use the
new predicates in many places.
Modified:
llvm/trunk/include/llvm/CodeGen/MachineInstr.h
llvm/trunk/include/llvm/Target/TargetInstrInfo.h
llvm/trunk/lib/CodeGen/BranchFolding.cpp
llvm/trunk/lib/CodeGen/Collector.cpp
llvm/trunk/lib/CodeGen/DwarfWriter.cpp
llvm/trunk/lib/CodeGen/IfConversion.cpp
llvm/trunk/lib/CodeGen/LiveIntervalAnalysis.cpp
llvm/trunk/lib/CodeGen/MachineBasicBlock.cpp
llvm/trunk/lib/CodeGen/MachineInstr.cpp
llvm/trunk/lib/CodeGen/MachineLICM.cpp
llvm/trunk/lib/CodeGen/PrologEpilogInserter.cpp
llvm/trunk/lib/CodeGen/RegAllocSimple.cpp
llvm/trunk/lib/CodeGen/RegisterScavenging.cpp
llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAG.cpp
llvm/trunk/lib/CodeGen/TargetInstrInfoImpl.cpp
llvm/trunk/lib/CodeGen/TwoAddressInstructionPass.cpp
llvm/trunk/lib/CodeGen/VirtRegMap.cpp
llvm/trunk/lib/Target/ARM/ARMCodeEmitter.cpp
llvm/trunk/lib/Target/ARM/ARMConstantIslandPass.cpp
llvm/trunk/lib/Target/ARM/ARMInstrInfo.cpp
llvm/trunk/lib/Target/ARM/ARMLoadStoreOptimizer.cpp
llvm/trunk/lib/Target/ARM/ARMRegisterInfo.cpp
llvm/trunk/lib/Target/Mips/MipsDelaySlotFiller.cpp
llvm/trunk/lib/Target/Mips/MipsInstrInfo.cpp
llvm/trunk/lib/Target/PowerPC/PPCISelDAGToDAG.cpp
llvm/trunk/lib/Target/Sparc/DelaySlotFiller.cpp
llvm/trunk/lib/Target/TargetInstrInfo.cpp
llvm/trunk/lib/Target/X86/X86CodeEmitter.cpp
llvm/trunk/lib/Target/X86/X86FloatingPoint.cpp
llvm/trunk/lib/Target/X86/X86InstrInfo.cpp
llvm/trunk/lib/Target/X86/X86RegisterInfo.cpp
Modified: llvm/trunk/include/llvm/CodeGen/MachineInstr.h
URL:
http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/CodeGen/MachineInstr.h?rev=45674&r1=45673&r2=45674&view=diff
==
--- llvm/trunk/include/llvm/CodeGen/MachineInstr.h (original)
+++ llvm/trunk/include/llvm/CodeGen/MachineInstr.h Sun Jan 6 19:56:04 2008
@@ -68,9 +68,9 @@
const MachineBasicBlock* getParent() const { return Parent; }
MachineBasicBlock* getParent() { return Parent; }
- /// getInstrDescriptor - Returns the target instruction descriptor of this
+ /// getDesc - Returns the target instruction descriptor of this
/// MachineInstr.
- const TargetInstrDescriptor *getInstrDescriptor() const { return TID; }
+ const TargetInstrDescriptor *getDesc() const { return TID; }
/// getOpcode - Returns the opcode of this MachineInstr.
///
Modified: llvm/trunk/include/llvm/Target/TargetInstrInfo.h
URL:
http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Target/TargetInstrInfo.h?rev=45674&r1=45673&r2=45674&view=diff
==
--- llvm/trunk/include/llvm/Target/TargetInstrInfo.h (original)
+++ llvm/trunk/include/llvm/Target/TargetInstrInfo.h Sun Jan 6 19:56:04 2008
@@ -191,6 +191,31 @@
/// dest operand. Returns -1 if there isn't one.
int findTiedToSrcOperand(unsigned OpNum) const;
+ bool isCall() const {
+return Flags & M_CALL_FLAG;
+ }
+
+ bool isBranch() const {
+return Flags & M_BRANCH_FLAG;
+ }
+
+ bool isTerminator() const {
+return Flags & M_TERMINATOR_FLAG;
+ }
+
+ bool isIndirectBranch() const {
+return Flags & M_INDIRECT_FLAG;
+ }
+
+ bool isPredicable() const {
+return Flags & M_PREDICABLE;
+ }
+
+ bool isNotDuplicable() const {
+return Flags & M_NOT_DUPLICABLE;
+ }
+
+
/// isSimpleLoad - Return true for instructions that are simple loads from
/// memory. This should only be set on instructions that load a value from
@@ -201,6 +226,26 @@
return Flags & M_SIMPLE_LOAD_FLAG;
}
+ /// mayStore - Return true if this instruction could possibly modify memory.
+ /// Instructions with this flag set are not necessarily simple store
+ /// instructions, they may store a modified value based on their operands, or
+ /// may not actually modify anything, for example.
+ bool mayStore() const {
+return Flags & M_MAY_STORE_FLAG;
+ }
+
+ /// isBarrier - Returns true if the specified instruction stops control flow
+ /// from executing the instruction immediately following it. Examples
include
+ /// unconditional branches and return instructions.
+ bool isBarrier() const {
+return Flags & M_BARRIER_FLAG;
+
Re: [llvm-commits] [llvm] r45626 - /llvm/trunk/lib/Target/X86/X86InstrInfo.cpp
On Jan 5, 2008, at 3:37 PM, Bill Wendling wrote:
> On Jan 5, 2008, at 2:49 AM, Evan Cheng wrote:
>> On Jan 5, 2008, at 1:18 AM, Bill Wendling <[EMAIL PROTECTED]> wrote:
>>
>>> --- llvm/trunk/lib/Target/X86/X86InstrInfo.cpp (original)
>>> +++ llvm/trunk/lib/Target/X86/X86InstrInfo.cpp Sat Jan 5 03:18:04
>>> 2008
>>> @@ -171,12 +171,15 @@
>>> case X86::MOV32rm:
>>> if (MI->getOperand(1).isRegister()) {
>>> unsigned Reg = MI->getOperand(1).getReg();
>>> + const X86Subtarget &ST = TM.getSubtarget();
>>>
>>> // Loads from global addresses which aren't redefined in the
>>> function are
>>> // side effect free.
>>> if (Reg != 0 &&
>>
>> I assume caller ensure this operant is side effect free?
>
> It ensures that all of the operands are loop-invariant. Reg is
> defined outside of the loop at this point.
>
>> Can you change this to accept a list of operands which should be
>> checked? For
>> LICM, that means non-invariant operands.
>>
> I'm not sure why this is necessary. Like I said, all of the operands
> should be loop-invariant at this point...
Never mind. I think this is good for now.
>
>> Also, please fix the comment.
>>
> Okay.
Thx.
Evan
>
> -bw
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[llvm-commits] [llvm] r45675 - /llvm/trunk/lib/Transforms/Scalar/LowerGC.cpp
Author: gordon Date: Sun Jan 6 20:29:04 2008 New Revision: 45675 URL: http://llvm.org/viewvc/llvm-project?rev=45675&view=rev Log: Deleting an empty file. Thanks, /usr/bin/patch! Removed: llvm/trunk/lib/Transforms/Scalar/LowerGC.cpp Removed: llvm/trunk/lib/Transforms/Scalar/LowerGC.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/Scalar/LowerGC.cpp?rev=45674&view=auto == (empty) ___ llvm-commits mailing list llvm-commits@cs.uiuc.edu http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
[llvm-commits] [llvm] r45676 - in /llvm/trunk: include/llvm/CallingConv.h include/llvm/CodeGen/LinkAllCodegenComponents.h lib/CodeGen/OcamlCollector.cpp test/CodeGen/Generic/GC/frame_size.ll test/Code
Author: gordon
Date: Sun Jan 6 20:31:11 2008
New Revision: 45676
URL: http://llvm.org/viewvc/llvm-project?rev=45676&view=rev
Log:
Setting GlobalDirective in TargetAsmInfo by default rather than
providing a misleading facility. It's used once in the MIPS backend
and hardcoded as "\t.globl\t" everywhere else.
Added:
llvm/trunk/lib/CodeGen/OcamlCollector.cpp
llvm/trunk/test/CodeGen/Generic/GC/frame_size.ll
llvm/trunk/test/CodeGen/Generic/GC/simple_ocaml.ll
Modified:
llvm/trunk/include/llvm/CallingConv.h
llvm/trunk/include/llvm/CodeGen/LinkAllCodegenComponents.h
Modified: llvm/trunk/include/llvm/CallingConv.h
URL:
http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/CallingConv.h?rev=45676&r1=45675&r2=45676&view=diff
==
--- llvm/trunk/include/llvm/CallingConv.h (original)
+++ llvm/trunk/include/llvm/CallingConv.h Sun Jan 6 20:31:11 2008
@@ -57,7 +57,12 @@
/// X86_FastCall - 'fast' analog of X86_StdCall. Passes first two arguments
/// in ECX:EDX registers, others - via stack. Callee is responsible for
/// stack cleaning.
-X86_FastCall = 65
+X86_FastCall = 65,
+
+/// X86_Ocaml - This is a weird ABI used by Objective Caml. Formally, it
+/// supports only one to six integer/address arguments, all in-reg. It also
+/// supports tail call emission.
+X86_Ocaml = 66
};
} // End CallingConv namespace
Modified: llvm/trunk/include/llvm/CodeGen/LinkAllCodegenComponents.h
URL:
http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/CodeGen/LinkAllCodegenComponents.h?rev=45676&r1=45675&r2=45676&view=diff
==
--- llvm/trunk/include/llvm/CodeGen/LinkAllCodegenComponents.h (original)
+++ llvm/trunk/include/llvm/CodeGen/LinkAllCodegenComponents.h Sun Jan 6
20:31:11 2008
@@ -36,6 +36,7 @@
(void) llvm::createSimpleRegisterCoalescer();
+ (void) llvm::createOcamlCollector();
(void) llvm::createShadowStackCollector();
(void) llvm::createBURRListDAGScheduler(NULL, NULL, NULL);
Added: llvm/trunk/lib/CodeGen/OcamlCollector.cpp
URL:
http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/OcamlCollector.cpp?rev=45676&view=auto
==
--- llvm/trunk/lib/CodeGen/OcamlCollector.cpp (added)
+++ llvm/trunk/lib/CodeGen/OcamlCollector.cpp Sun Jan 6 20:31:11 2008
@@ -0,0 +1,177 @@
+//===-- OcamlCollector.cpp - Ocaml frametable emitter
-===//
+//
+// The LLVM Compiler Infrastructure
+//
+// This file is distributed under the University of Illinois Open Source
+// License. See LICENSE.TXT for details.
+//
+//===--===//
+//
+// This file implements lowering for the llvm.gc* intrinsics compatible with
+// Objective Caml 3.10.0, which uses a liveness-accurate static stack map.
+//
+//===--===//
+
+#include "llvm/CodeGen/Collectors.h"
+#include "llvm/ADT/DenseMap.h"
+#include "llvm/CodeGen/AsmPrinter.h"
+#include "llvm/CodeGen/Collector.h"
+#include "llvm/CodeGen/CollectorMetadata.h"
+#include "llvm/Function.h"
+#include "llvm/Module.h"
+#include "llvm/PassManager.h"
+#include "llvm/Support/Compiler.h"
+#include "llvm/Target/TargetAsmInfo.h"
+#include "llvm/Target/TargetData.h"
+#include "llvm/Target/TargetMachine.h"
+#include
+
+using namespace llvm;
+
+namespace {
+
+ class VISIBILITY_HIDDEN OcamlCollector : public Collector {
+ public:
+OcamlCollector();
+
+void beginAssembly(std::ostream &OS, AsmPrinter &AP,
+ const TargetAsmInfo &TAI);
+
+void finishAssembly(std::ostream &OS, AsmPrinter &AP,
+const TargetAsmInfo &TAI);
+ };
+
+ CollectorRegistry::Add
+ X("ocaml", "ocaml 3.10-compatible collector");
+
+}
+
+//
-
+
+static void EmitCamlGlobal(const Module &M, std::ostream &OS, AsmPrinter &AP,
+ const TargetAsmInfo &TAI, const char *Id) {
+ const std::string &MId = M.getModuleIdentifier();
+
+ std::string Mangled;
+ Mangled += TAI.getGlobalPrefix();
+ Mangled += "caml";
+ size_t Letter = Mangled.size();
+ Mangled.append(MId.begin(), std::find(MId.begin(), MId.end(), '.'));
+ Mangled += "__";
+ Mangled += Id;
+
+ // Capitalize the first letter of the module name.
+ Mangled[Letter] = toupper(Mangled[Letter]);
+
+ if (const char *GlobalDirective = TAI.getGlobalDirective())
+OS << GlobalDirective << Mangled << "\n";
+ OS << Mangled << ":\n";
+}
+
+Collector *llvm::createOcamlCollector() {
+ return new OcamlCollector();
+}
+
+OcamlCollector::OcamlCollector() {
+ NeededSafePoints = 1 << GC::PostCall;
+}
+
[llvm-commits] [llvm] r45677 - in /llvm/trunk: include/llvm/Target/TargetInstrInfo.h lib/CodeGen/MachineInstr.cpp lib/CodeGen/SelectionDAG/ScheduleDAG.cpp lib/CodeGen/TargetInstrInfoImpl.cpp lib/Targe
Author: lattner
Date: Sun Jan 6 20:39:19 2008
New Revision: 45677
URL: http://llvm.org/viewvc/llvm-project?rev=45677&view=rev
Log:
Add predicates methods to TargetOperandInfo, and switch all clients
over to using them, instead of diddling Flags directly. Change the
various flags from const variables to enums.
Modified:
llvm/trunk/include/llvm/Target/TargetInstrInfo.h
llvm/trunk/lib/CodeGen/MachineInstr.cpp
llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAG.cpp
llvm/trunk/lib/CodeGen/TargetInstrInfoImpl.cpp
llvm/trunk/lib/Target/X86/X86InstrInfo.cpp
llvm/trunk/utils/TableGen/InstrInfoEmitter.cpp
Modified: llvm/trunk/include/llvm/Target/TargetInstrInfo.h
URL:
http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Target/TargetInstrInfo.h?rev=45677&r1=45676&r2=45677&view=diff
==
--- llvm/trunk/include/llvm/Target/TargetInstrInfo.h (original)
+++ llvm/trunk/include/llvm/Target/TargetInstrInfo.h Sun Jan 6 20:39:19 2008
@@ -32,14 +32,14 @@
template class SmallVectorImpl;
-//---
+//===--===//
// Data types used to define information about a single machine instruction
-//---
+//===--===//
typedef short MachineOpCode;
typedef unsigned InstrSchedClass;
-//---
+//===--===//
// struct TargetInstrDescriptor:
// Predefined information about each machine instruction.
// Designed to initialized statically.
@@ -124,24 +124,25 @@
// both! If neither flag is set, then the instruction *always* has side
effects.
const unsigned M_MAY_HAVE_SIDE_EFFECTS = 1 << 19;
+
+//===--===//
// Machine operand flags
-// M_LOOK_UP_PTR_REG_CLASS - Set if this operand is a pointer value and it
-// requires a callback to look up its register class.
-const unsigned M_LOOK_UP_PTR_REG_CLASS = 1 << 0;
-
-/// M_PREDICATE_OPERAND - Set if this is one of the operands that made up of
the
-/// predicate operand that controls an M_PREDICATED instruction.
-const unsigned M_PREDICATE_OPERAND = 1 << 1;
-
-/// M_OPTIONAL_DEF_OPERAND - Set if this operand is a optional def.
-///
-const unsigned M_OPTIONAL_DEF_OPERAND = 1 << 2;
-
+//===--===//
+
namespace TOI {
// Operand constraints: only "tied_to" for now.
enum OperandConstraint {
TIED_TO = 0 // Must be allocated the same register as.
};
+
+ /// OperandFlags - These are flags set on operands, but should be considered
+ /// private, all access should go through the TargetOperandInfo accessors.
+ /// See the accessors for a description of what these are.
+ enum OperandFlags {
+LookupPtrRegClass = 1 << 0,
+Predicate = 1 << 1,
+OptionalDef = 1 << 2
+ };
}
/// TargetOperandInfo - This holds information about one operand of a machine
@@ -157,6 +158,18 @@
/// bits are used to specify the value of constraints (4 bits each).
unsigned int Constraints;
/// Currently no other information.
+
+ /// isLookupPtrRegClass - Set if this operand is a pointer value and it
+ /// requires a callback to look up its register class.
+ bool isLookupPtrRegClass() const { return Flags & TOI::LookupPtrRegClass; }
+
+ /// isPredicate - Set if this is one of the operands that made up of
+ /// the predicate operand that controls an M_PREDICATED instruction.
+ bool isPredicate() const { return Flags & TOI::Predicate; }
+
+ /// isOptionalDef - Set if this operand is a optional def.
+ ///
+ bool isOptionalDef() const { return Flags & TOI::OptionalDef; }
};
Modified: llvm/trunk/lib/CodeGen/MachineInstr.cpp
URL:
http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/MachineInstr.cpp?rev=45677&r1=45676&r2=45677&view=diff
==
--- llvm/trunk/lib/CodeGen/MachineInstr.cpp (original)
+++ llvm/trunk/lib/CodeGen/MachineInstr.cpp Sun Jan 6 20:39:19 2008
@@ -541,7 +541,7 @@
const TargetInstrDescriptor *TID = getDesc();
if (TID->isPredicable()) {
for (unsigned i = 0, e = getNumOperands(); i != e; ++i)
- if ((TID->OpInfo[i].Flags & M_PREDICATE_OPERAND))
+ if (TID->OpInfo[i].isPredicate())
return i;
}
@@ -591,7 +591,7 @@
const TargetInstrDescriptor *TID = MI->getDesc();
if (TID->isPredicable()) {
for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
- if ((TID->OpInfo[i].Flags & M_PREDICATE_OPERAND)) {
+ if (TID->OpInfo[i].isPredicate()) {
// P
[llvm-commits] [llvm] r45678 - in /llvm/trunk: include/llvm/Target/TargetInstrInfo.h lib/CodeGen/SelectionDAG/ScheduleDAG.cpp
Author: lattner
Date: Sun Jan 6 20:46:03 2008
New Revision: 45678
URL: http://llvm.org/viewvc/llvm-project?rev=45678&view=rev
Log:
remove some uses of MachineOpCode, move getSchedClass
into TargetInstrDescriptor from TargetInstrInfo.
Modified:
llvm/trunk/include/llvm/Target/TargetInstrInfo.h
llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAG.cpp
Modified: llvm/trunk/include/llvm/Target/TargetInstrInfo.h
URL:
http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Target/TargetInstrInfo.h?rev=45678&r1=45677&r2=45678&view=diff
==
--- llvm/trunk/include/llvm/Target/TargetInstrInfo.h (original)
+++ llvm/trunk/include/llvm/Target/TargetInstrInfo.h Sun Jan 6 20:46:03 2008
@@ -37,7 +37,6 @@
//===--===//
typedef short MachineOpCode;
-typedef unsigned InstrSchedClass;
//===--===//
// struct TargetInstrDescriptor:
@@ -175,11 +174,11 @@
class TargetInstrDescriptor {
public:
- MachineOpCode Opcode;// The opcode.
+ unsigned short Opcode;// The opcode.
unsigned short numOperands; // Num of args (may be more if variable_ops).
unsigned short numDefs; // Num of args that are definitions.
const char *Name; // Assembly language mnemonic for the opcode.
- InstrSchedClass schedClass;// enum identifying instr sched class
+ unsignedSchedClass;// enum identifying instr sched class
unsignedFlags; // flags identifying machine instr class
unsignedTSFlags; // Target Specific Flag values
const unsigned *ImplicitUses; // Registers implicitly read by this instr
@@ -259,6 +258,10 @@
bool hasDelaySlot() const {
return Flags & M_DELAY_SLOT_FLAG;
}
+
+ unsigned getSchedClass() const {
+return SchedClass;
+ }
};
@@ -291,32 +294,28 @@
/// get - Return the machine instruction descriptor that corresponds to the
/// specified instruction opcode.
///
- const TargetInstrDescriptor& get(MachineOpCode Opcode) const {
-assert((unsigned)Opcode < NumOpcodes);
+ const TargetInstrDescriptor& get(unsigned Opcode) const {
+assert(Opcode < NumOpcodes);
return desc[Opcode];
}
- const char *getName(MachineOpCode Opcode) const {
+ const char *getName(unsigned Opcode) const {
return get(Opcode).Name;
}
- int getNumOperands(MachineOpCode Opcode) const {
+ int getNumOperands(unsigned Opcode) const {
return get(Opcode).numOperands;
}
- int getNumDefs(MachineOpCode Opcode) const {
+ int getNumDefs(unsigned Opcode) const {
return get(Opcode).numDefs;
}
- InstrSchedClass getSchedClass(MachineOpCode Opcode) const {
-return get(Opcode).schedClass;
- }
-
- const unsigned *getImplicitUses(MachineOpCode Opcode) const {
+ const unsigned *getImplicitUses(unsigned Opcode) const {
return get(Opcode).ImplicitUses;
}
- const unsigned *getImplicitDefs(MachineOpCode Opcode) const {
+ const unsigned *getImplicitDefs(unsigned Opcode) const {
return get(Opcode).ImplicitDefs;
}
@@ -325,26 +324,26 @@
// Query instruction class flags according to the machine-independent
// flags listed above.
//
- bool isReturn(MachineOpCode Opcode) const {
+ bool isReturn(unsigned Opcode) const {
return get(Opcode).Flags & M_RET_FLAG;
}
- bool isCommutableInstr(MachineOpCode Opcode) const {
+ bool isCommutableInstr(unsigned Opcode) const {
return get(Opcode).Flags & M_COMMUTABLE;
}
/// usesCustomDAGSchedInsertionHook - Return true if this instruction
requires
/// custom insertion support when the DAG scheduler is inserting it into a
/// machine basic block.
- bool usesCustomDAGSchedInsertionHook(MachineOpCode Opcode) const {
+ bool usesCustomDAGSchedInsertionHook(unsigned Opcode) const {
return get(Opcode).Flags & M_USES_CUSTOM_DAG_SCHED_INSERTION;
}
- bool hasVariableOperands(MachineOpCode Opcode) const {
+ bool hasVariableOperands(unsigned Opcode) const {
return get(Opcode).Flags & M_VARIABLE_OPS;
}
- bool hasOptionalDef(MachineOpCode Opcode) const {
+ bool hasOptionalDef(unsigned Opcode) const {
return get(Opcode).Flags & M_HAS_OPTIONAL_DEF;
}
@@ -390,7 +389,7 @@
public:
/// getOperandConstraint - Returns the value of the specific constraint if
/// it is set. Returns -1 if it is not set.
- int getOperandConstraint(MachineOpCode Opcode, unsigned OpNum,
+ int getOperandConstraint(unsigned Opcode, unsigned OpNum,
TOI::OperandConstraint Constraint) const {
return get(Opcode).getOperandConstraint(OpNum, Constraint);
}
Modified: llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAG.cpp
URL:
http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAG.cpp?rev=45678&r1=45677&r2=45678&view=diff
==
Re: [llvm-commits] [llvm] r45626 - /llvm/trunk/lib/Target/X86/X86InstrInfo.cpp
By the way. This check is still not quite right.
// Loads from stubs of global addresses are side effect free.
if (Reg != 0 && MRegisterInfo::isVirtualRegister(Reg) &&
In dynamic-no-pic mode, Reg can be 0. So it should be Reg == 0 || ...
Evan
On Jan 5, 2008, at 3:37 PM, Bill Wendling wrote:
> On Jan 5, 2008, at 2:49 AM, Evan Cheng wrote:
>> On Jan 5, 2008, at 1:18 AM, Bill Wendling <[EMAIL PROTECTED]> wrote:
>>
>>> --- llvm/trunk/lib/Target/X86/X86InstrInfo.cpp (original)
>>> +++ llvm/trunk/lib/Target/X86/X86InstrInfo.cpp Sat Jan 5 03:18:04
>>> 2008
>>> @@ -171,12 +171,15 @@
>>> case X86::MOV32rm:
>>> if (MI->getOperand(1).isRegister()) {
>>> unsigned Reg = MI->getOperand(1).getReg();
>>> + const X86Subtarget &ST = TM.getSubtarget();
>>>
>>> // Loads from global addresses which aren't redefined in the
>>> function are
>>> // side effect free.
>>> if (Reg != 0 &&
>>
>> I assume caller ensure this operant is side effect free?
>
> It ensures that all of the operands are loop-invariant. Reg is
> defined outside of the loop at this point.
>
>> Can you change this to accept a list of operands which should be
>> checked? For
>> LICM, that means non-invariant operands.
>>
> I'm not sure why this is necessary. Like I said, all of the operands
> should be loop-invariant at this point...
>
>> Also, please fix the comment.
>>
> Okay.
>
> -bw
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[llvm-commits] [llvm] r45679 - in /llvm/trunk: include/llvm/Target/TargetInstrInfo.h lib/Target/ARM/ARMInstrInfo.cpp lib/Target/Alpha/AlphaInstrInfo.cpp lib/Target/CellSPU/SPUInstrInfo.cpp lib/Target/
Author: lattner
Date: Sun Jan 6 20:48:55 2008
New Revision: 45679
URL: http://llvm.org/viewvc/llvm-project?rev=45679&view=rev
Log:
remove MachineOpCode typedef.
Modified:
llvm/trunk/include/llvm/Target/TargetInstrInfo.h
llvm/trunk/lib/Target/ARM/ARMInstrInfo.cpp
llvm/trunk/lib/Target/Alpha/AlphaInstrInfo.cpp
llvm/trunk/lib/Target/CellSPU/SPUInstrInfo.cpp
llvm/trunk/lib/Target/IA64/IA64InstrInfo.cpp
llvm/trunk/lib/Target/PowerPC/PPCInstrInfo.cpp
llvm/trunk/lib/Target/X86/X86InstrInfo.cpp
llvm/trunk/lib/Target/X86/X86InstrInfo.h
Modified: llvm/trunk/include/llvm/Target/TargetInstrInfo.h
URL:
http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Target/TargetInstrInfo.h?rev=45679&r1=45678&r2=45679&view=diff
==
--- llvm/trunk/include/llvm/Target/TargetInstrInfo.h (original)
+++ llvm/trunk/include/llvm/Target/TargetInstrInfo.h Sun Jan 6 20:48:55 2008
@@ -33,12 +33,6 @@
template class SmallVectorImpl;
//===--===//
-// Data types used to define information about a single machine instruction
-//===--===//
-
-typedef short MachineOpCode;
-
-//===--===//
// struct TargetInstrDescriptor:
// Predefined information about each machine instruction.
// Designed to initialized statically.
Modified: llvm/trunk/lib/Target/ARM/ARMInstrInfo.cpp
URL:
http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrInfo.cpp?rev=45679&r1=45678&r2=45679&view=diff
==
--- llvm/trunk/lib/Target/ARM/ARMInstrInfo.cpp (original)
+++ llvm/trunk/lib/Target/ARM/ARMInstrInfo.cpp Sun Jan 6 20:48:55 2008
@@ -52,7 +52,7 @@
///
bool ARMInstrInfo::isMoveInstr(const MachineInstr &MI,
unsigned &SrcReg, unsigned &DstReg) const {
- MachineOpCode oc = MI.getOpcode();
+ unsigned oc = MI.getOpcode();
switch (oc) {
default:
return false;
Modified: llvm/trunk/lib/Target/Alpha/AlphaInstrInfo.cpp
URL:
http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Alpha/AlphaInstrInfo.cpp?rev=45679&r1=45678&r2=45679&view=diff
==
--- llvm/trunk/lib/Target/Alpha/AlphaInstrInfo.cpp (original)
+++ llvm/trunk/lib/Target/Alpha/AlphaInstrInfo.cpp Sun Jan 6 20:48:55 2008
@@ -26,7 +26,7 @@
bool AlphaInstrInfo::isMoveInstr(const MachineInstr& MI,
unsigned& sourceReg,
unsigned& destReg) const {
- MachineOpCode oc = MI.getOpcode();
+ unsigned oc = MI.getOpcode();
if (oc == Alpha::BISr ||
oc == Alpha::CPYSS ||
oc == Alpha::CPYST ||
Modified: llvm/trunk/lib/Target/CellSPU/SPUInstrInfo.cpp
URL:
http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/CellSPU/SPUInstrInfo.cpp?rev=45679&r1=45678&r2=45679&view=diff
==
--- llvm/trunk/lib/Target/CellSPU/SPUInstrInfo.cpp (original)
+++ llvm/trunk/lib/Target/CellSPU/SPUInstrInfo.cpp Sun Jan 6 20:48:55 2008
@@ -225,7 +225,7 @@
unsigned SrcReg, bool isKill, int
FrameIdx,
const TargetRegisterClass *RC) const
{
- MachineOpCode opc;
+ unsigned opc;
if (RC == SPU::GPRCRegisterClass) {
opc = (FrameIdx < SPUFrameInfo::maxFrameOffset())
? SPU::STQDr128
@@ -308,7 +308,7 @@
unsigned DestReg, int FrameIdx,
const TargetRegisterClass *RC) const
{
- MachineOpCode opc;
+ unsigned opc;
if (RC == SPU::GPRCRegisterClass) {
opc = (FrameIdx < SPUFrameInfo::maxFrameOffset())
? SPU::LQDr128
Modified: llvm/trunk/lib/Target/IA64/IA64InstrInfo.cpp
URL:
http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/IA64/IA64InstrInfo.cpp?rev=45679&r1=45678&r2=45679&view=diff
==
--- llvm/trunk/lib/Target/IA64/IA64InstrInfo.cpp (original)
+++ llvm/trunk/lib/Target/IA64/IA64InstrInfo.cpp Sun Jan 6 20:48:55 2008
@@ -27,7 +27,7 @@
bool IA64InstrInfo::isMoveInstr(const MachineInstr& MI,
unsigned& sourceReg,
unsigned& destReg) const {
- MachineOpCode oc = MI.getOpcode();
+ unsigned oc = MI.getOpcode();
if (oc == IA64::MOV || oc == IA64::FMOV) {
// TODO: this doesn't detect predicate moves
assert(MI.getNumOperands() >= 2 &&
Modified: llvm/trunk/lib/Target/PowerPC/PPCInstrInfo.cpp
URL:
http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PowerPC/PPCInstrInfo.cpp?rev=45679&r1=45678&r2=45679&view=diff
===
[llvm-commits] [llvm] r45680 - in /llvm/trunk: include/llvm/Target/ lib/CodeGen/ lib/CodeGen/SelectionDAG/ lib/Target/ lib/Target/ARM/ lib/Target/Mips/ lib/Target/PowerPC/ lib/Target/X86/
Author: lattner
Date: Sun Jan 6 21:13:06 2008
New Revision: 45680
URL: http://llvm.org/viewvc/llvm-project?rev=45680&view=rev
Log:
Move a bunch more accessors from TargetInstrInfo to TargetInstrDescriptor
Modified:
llvm/trunk/include/llvm/Target/TargetInstrInfo.h
llvm/trunk/lib/CodeGen/LiveVariables.cpp
llvm/trunk/lib/CodeGen/MachineInstr.cpp
llvm/trunk/lib/CodeGen/PrologEpilogInserter.cpp
llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAG.cpp
llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp
llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
llvm/trunk/lib/CodeGen/TwoAddressInstructionPass.cpp
llvm/trunk/lib/CodeGen/VirtRegMap.cpp
llvm/trunk/lib/Target/ARM/ARMInstrInfo.cpp
llvm/trunk/lib/Target/ARM/ARMLoadStoreOptimizer.cpp
llvm/trunk/lib/Target/Mips/MipsInstrInfo.cpp
llvm/trunk/lib/Target/PowerPC/PPCISelDAGToDAG.cpp
llvm/trunk/lib/Target/PowerPC/PPCRegisterInfo.cpp
llvm/trunk/lib/Target/TargetInstrInfo.cpp
llvm/trunk/lib/Target/X86/X86CodeEmitter.cpp
llvm/trunk/lib/Target/X86/X86FloatingPoint.cpp
llvm/trunk/lib/Target/X86/X86InstrInfo.cpp
Modified: llvm/trunk/include/llvm/Target/TargetInstrInfo.h
URL:
http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Target/TargetInstrInfo.h?rev=45680&r1=45679&r2=45680&view=diff
==
--- llvm/trunk/include/llvm/Target/TargetInstrInfo.h (original)
+++ llvm/trunk/include/llvm/Target/TargetInstrInfo.h Sun Jan 6 21:13:06 2008
@@ -169,8 +169,8 @@
class TargetInstrDescriptor {
public:
unsigned short Opcode;// The opcode.
- unsigned short numOperands; // Num of args (may be more if variable_ops).
- unsigned short numDefs; // Num of args that are definitions.
+ unsigned short NumOperands; // Num of args (may be more if variable_ops).
+ unsigned short NumDefs; // Num of args that are definitions.
const char *Name; // Assembly language mnemonic for the opcode.
unsignedSchedClass;// enum identifying instr sched class
unsignedFlags; // flags identifying machine instr class
@@ -183,9 +183,9 @@
/// it is set. Returns -1 if it is not set.
int getOperandConstraint(unsigned OpNum,
TOI::OperandConstraint Constraint) const {
-assert((OpNum < numOperands || (Flags & M_VARIABLE_OPS)) &&
+assert((OpNum < NumOperands || hasVariableOperands()) &&
"Invalid operand # of TargetInstrInfo");
-if (OpNum < numOperands &&
+if (OpNum < NumOperands &&
(OpInfo[OpNum].Constraints & (1 << Constraint))) {
unsigned Pos = 16 + Constraint * 4;
return (int)(OpInfo[OpNum].Constraints >> Pos) & 0xf;
@@ -197,18 +197,50 @@
/// dest operand. Returns -1 if there isn't one.
int findTiedToSrcOperand(unsigned OpNum) const;
- bool isCall() const {
-return Flags & M_CALL_FLAG;
+ const char *getName() const {
+return Name;
}
- bool isBranch() const {
-return Flags & M_BRANCH_FLAG;
+ unsigned getNumOperands() const {
+return NumOperands;
+ }
+
+ unsigned getNumDefs() const {
+return NumDefs;
+ }
+
+ bool hasVariableOperands() const {
+return Flags & M_VARIABLE_OPS;
+ }
+
+ bool hasOptionalDef() const {
+return Flags & M_HAS_OPTIONAL_DEF;
+ }
+
+ const unsigned *getImplicitUses() const {
+return ImplicitUses;
+ }
+
+ const unsigned *getImplicitDefs() const {
+return ImplicitDefs;
+ }
+
+ bool isReturn() const {
+return Flags & M_RET_FLAG;
+ }
+
+ bool isCall() const {
+return Flags & M_CALL_FLAG;
}
bool isTerminator() const {
return Flags & M_TERMINATOR_FLAG;
}
+ bool isBranch() const {
+return Flags & M_BRANCH_FLAG;
+ }
+
bool isIndirectBranch() const {
return Flags & M_INDIRECT_FLAG;
}
@@ -221,7 +253,16 @@
return Flags & M_NOT_DUPLICABLE;
}
+ bool isCommutableInstr() const {
+return Flags & M_COMMUTABLE;
+ }
+ /// usesCustomDAGSchedInsertionHook - Return true if this instruction
requires
+ /// custom insertion support when the DAG scheduler is inserting it into a
+ /// machine basic block.
+ bool usesCustomDAGSchedInsertionHook() const {
+return Flags & M_USES_CUSTOM_DAG_SCHED_INSERTION;
+ }
/// isSimpleLoad - Return true for instructions that are simple loads from
/// memory. This should only be set on instructions that load a value from
@@ -293,54 +334,6 @@
return desc[Opcode];
}
- const char *getName(unsigned Opcode) const {
-return get(Opcode).Name;
- }
-
- int getNumOperands(unsigned Opcode) const {
-return get(Opcode).numOperands;
- }
-
- int getNumDefs(unsigned Opcode) const {
-return get(Opcode).numDefs;
- }
-
- const unsigned *getImplicitUses(unsigned Opcode) const {
-return get(Opcode).ImplicitUses;
- }
-
- const unsigned *getImplicitDefs(unsigned Opcode) const {
-
[llvm-commits] [llvm] r45681 - /llvm/trunk/include/llvm/CallingConv.h
Author: gordon Date: Sun Jan 6 21:23:52 2008 New Revision: 45681 URL: http://llvm.org/viewvc/llvm-project?rev=45681&view=rev Log: Removing a leaked file. Modified: llvm/trunk/include/llvm/CallingConv.h Modified: llvm/trunk/include/llvm/CallingConv.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/CallingConv.h?rev=45681&r1=45680&r2=45681&view=diff == --- llvm/trunk/include/llvm/CallingConv.h (original) +++ llvm/trunk/include/llvm/CallingConv.h Sun Jan 6 21:23:52 2008 @@ -57,12 +57,7 @@ /// X86_FastCall - 'fast' analog of X86_StdCall. Passes first two arguments /// in ECX:EDX registers, others - via stack. Callee is responsible for /// stack cleaning. -X86_FastCall = 65, - -/// X86_Ocaml - This is a weird ABI used by Objective Caml. Formally, it -/// supports only one to six integer/address arguments, all in-reg. It also -/// supports tail call emission. -X86_Ocaml = 66 +X86_FastCall = 65 }; } // End CallingConv namespace ___ llvm-commits mailing list llvm-commits@cs.uiuc.edu http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
[llvm-commits] CVS: llvm-www/OpenProjects.html
Changes in directory llvm-www: OpenProjects.html updated: 1.32 -> 1.33 --- Log message: add a project. --- Diffs of the changes: (+6 -1) OpenProjects.html |7 ++- 1 files changed, 6 insertions(+), 1 deletion(-) Index: llvm-www/OpenProjects.html diff -u llvm-www/OpenProjects.html:1.32 llvm-www/OpenProjects.html:1.33 --- llvm-www/OpenProjects.html:1.32 Sun Jan 6 14:07:10 2008 +++ llvm-www/OpenProjects.html Sun Jan 6 21:42:46 2008 @@ -212,6 +212,11 @@ These projects tend to be more involved and perhaps require more work, but can also be very rewarding. +Add support for Type Based Alias Analysis (TBAA) to LLVM. This is not an + easy or straight-forward project, but the wins can be big. For an intro to + what this is and an extreme example http://www.ice.gelato.org/oct07/pres_pdf/gelato_ICE07oct_aliasing_isaev_intel.pdf";>see this presentation. + @@ -419,7 +424,7 @@ src="http://www.w3.org/Icons/valid-html401"; alt="Valid HTML 4.01!"> http://llvm.org";>LLVM Compiler Infrastructure - Last modified: $Date: 2008/01/06 20:07:10 $ + Last modified: $Date: 2008/01/07 03:42:46 $ ___ llvm-commits mailing list llvm-commits@cs.uiuc.edu http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
[llvm-commits] [llvm] r45683 - in /llvm/trunk/lib/Target: CellSPU/SPUInstrFormats.td PowerPC/PPCInstrFormats.td
Author: lattner
Date: Sun Jan 6 22:55:09 2008
New Revision: 45683
URL: http://llvm.org/viewvc/llvm-project?rev=45683&view=rev
Log:
no need to explicitly clear these fields.
Modified:
llvm/trunk/lib/Target/CellSPU/SPUInstrFormats.td
llvm/trunk/lib/Target/PowerPC/PPCInstrFormats.td
Modified: llvm/trunk/lib/Target/CellSPU/SPUInstrFormats.td
URL:
http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/CellSPU/SPUInstrFormats.td?rev=45683&r1=45682&r2=45683&view=diff
==
--- llvm/trunk/lib/Target/CellSPU/SPUInstrFormats.td (original)
+++ llvm/trunk/lib/Target/CellSPU/SPUInstrFormats.td Sun Jan 6 22:55:09 2008
@@ -18,7 +18,6 @@
: Instruction {
field bits<32> Inst;
- let Name = "";
let Namespace = "SPU";
let OutOperandList = OOL;
let InOperandList = IOL;
Modified: llvm/trunk/lib/Target/PowerPC/PPCInstrFormats.td
URL:
http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PowerPC/PPCInstrFormats.td?rev=45683&r1=45682&r2=45683&view=diff
==
--- llvm/trunk/lib/Target/PowerPC/PPCInstrFormats.td (original)
+++ llvm/trunk/lib/Target/PowerPC/PPCInstrFormats.td Sun Jan 6 22:55:09 2008
@@ -17,7 +17,6 @@
bit PPC64 = 0; // Default value, override with isPPC64
- let Name = "";
let Namespace = "PPC";
let Inst{0-5} = opcode;
let OutOperandList = OOL;
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[llvm-commits] [llvm] r45685 - /llvm/trunk/lib/Target/Target.td
Author: lattner
Date: Sun Jan 6 22:57:42 2008
New Revision: 45685
URL: http://llvm.org/viewvc/llvm-project?rev=45685&view=rev
Log:
remove a dead field.
Modified:
llvm/trunk/lib/Target/Target.td
Modified: llvm/trunk/lib/Target/Target.td
URL:
http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Target.td?rev=45685&r1=45684&r2=45685&view=diff
==
--- llvm/trunk/lib/Target/Target.td (original)
+++ llvm/trunk/lib/Target/Target.td Sun Jan 6 22:57:42 2008
@@ -156,7 +156,6 @@
// the Target/TargetInstrInfo.h file.
//
class Instruction {
- string Name = ""; // The opcode string for this instruction
string Namespace = "";
dag OutOperandList; // An dag containing the MI def operand list.
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[llvm-commits] [llvm] r45684 - in /llvm/trunk/utils/TableGen: CodeGenInstruction.cpp CodeGenInstruction.h InstrInfoEmitter.cpp
Author: lattner
Date: Sun Jan 6 22:57:31 2008
New Revision: 45684
URL: http://llvm.org/viewvc/llvm-project?rev=45684&view=rev
Log:
the name field of instructions is never set to a non-empty string,
just unconditionally use the def name of the instruction.
Modified:
llvm/trunk/utils/TableGen/CodeGenInstruction.cpp
llvm/trunk/utils/TableGen/CodeGenInstruction.h
llvm/trunk/utils/TableGen/InstrInfoEmitter.cpp
Modified: llvm/trunk/utils/TableGen/CodeGenInstruction.cpp
URL:
http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/TableGen/CodeGenInstruction.cpp?rev=45684&r1=45683&r2=45684&view=diff
==
--- llvm/trunk/utils/TableGen/CodeGenInstruction.cpp (original)
+++ llvm/trunk/utils/TableGen/CodeGenInstruction.cpp Sun Jan 6 22:57:31 2008
@@ -76,7 +76,6 @@
CodeGenInstruction::CodeGenInstruction(Record *R, const std::string &AsmStr)
: TheDef(R), AsmString(AsmStr) {
- Name = R->getValueAsString("Name");
Namespace = R->getValueAsString("Namespace");
isReturn = R->getValueAsBit("isReturn");
@@ -214,14 +213,6 @@
}
}
-/// getName - Return the contents of the instruction Name field if set,
-/// otherwise return the name of the def.
-std::string CodeGenInstruction::getName() const {
- if (!Name.empty()) return Name;
- return TheDef->getName();
-}
-
-
/// getOperandNamed - Return the index of the operand with the specified
/// non-empty name. If the instruction does not have an operand with the
/// specified name, throw an exception.
Modified: llvm/trunk/utils/TableGen/CodeGenInstruction.h
URL:
http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/TableGen/CodeGenInstruction.h?rev=45684&r1=45683&r2=45684&view=diff
==
--- llvm/trunk/utils/TableGen/CodeGenInstruction.h (original)
+++ llvm/trunk/utils/TableGen/CodeGenInstruction.h Sun Jan 6 22:57:31 2008
@@ -26,17 +26,12 @@
class CodeGenInstruction {
public:
Record *TheDef;// The actual record defining this instruction.
-std::string Name; // Contents of the 'Name' field.
std::string Namespace; // The namespace the instruction is in.
/// AsmString - The format string used to emit a .s file for the
/// instruction.
std::string AsmString;
-/// getName - Return the contents of the instruction Name field if set,
-/// otherwise return the name of the def.
-std::string getName() const;
-
/// OperandInfo - The information we keep track of for each operand in the
/// operand list for a tablegen instruction.
struct OperandInfo {
Modified: llvm/trunk/utils/TableGen/InstrInfoEmitter.cpp
URL:
http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/TableGen/InstrInfoEmitter.cpp?rev=45684&r1=45683&r2=45684&view=diff
==
--- llvm/trunk/utils/TableGen/InstrInfoEmitter.cpp (original)
+++ llvm/trunk/utils/TableGen/InstrInfoEmitter.cpp Sun Jan 6 22:57:31 2008
@@ -205,7 +205,7 @@
fprintf(stderr,
"Warning: mayStore flag explicitly set on instruction '%s'"
" but flag already inferred from pattern.\n",
- Inst.getName().c_str());
+ Inst.TheDef->getName().c_str());
mayStore = true;
}
@@ -285,7 +285,7 @@
InferFromPattern(Inst, mayStore, isLoad, NeverHasSideEffects);
if (NeverHasSideEffects && Inst.mayHaveSideEffects) {
-std::cerr << "error: Instruction '" << Inst.getName()
+std::cerr << "error: Instruction '" << Inst.TheDef->getName()
<< "' is marked with 'mayHaveSideEffects', but it can never have
them!\n";
exit(1);
}
@@ -298,7 +298,7 @@
OS << " { ";
OS << Num << ",\t" << MinOperands << ",\t"
- << Inst.NumDefs << ",\t\"" << Inst.getName();
+ << Inst.NumDefs << ",\t\"" << Inst.TheDef->getName();
OS << "\",\t" << getItinClassNumber(Inst.TheDef) << ", 0";
// Emit all of the target indepedent flags...
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[llvm-commits] [llvm] r45686 - in /llvm/trunk: include/llvm/Target/TargetInstrInfo.h utils/TableGen/InstrInfoEmitter.cpp
Author: lattner
Date: Sun Jan 6 23:06:49 2008
New Revision: 45686
URL: http://llvm.org/viewvc/llvm-project?rev=45686&view=rev
Log:
Move M_* flags down in the file. Move SchedClass up in the
TargetInstrDescriptor class and shrink to 16-bits, saving a
word in TargetInstrDescriptor. Add some comments.
Modified:
llvm/trunk/include/llvm/Target/TargetInstrInfo.h
llvm/trunk/utils/TableGen/InstrInfoEmitter.cpp
Modified: llvm/trunk/include/llvm/Target/TargetInstrInfo.h
URL:
http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Target/TargetInstrInfo.h?rev=45686&r1=45685&r2=45686&view=diff
==
--- llvm/trunk/include/llvm/Target/TargetInstrInfo.h (original)
+++ llvm/trunk/include/llvm/Target/TargetInstrInfo.h Sun Jan 6 23:06:49 2008
@@ -33,28 +33,74 @@
template class SmallVectorImpl;
//===--===//
-// struct TargetInstrDescriptor:
-// Predefined information about each machine instruction.
-// Designed to initialized statically.
-//
+// Machine Operand Flags and Description
+//===--===//
+
+namespace TOI {
+ // Operand constraints: only "tied_to" for now.
+ enum OperandConstraint {
+TIED_TO = 0 // Must be allocated the same register as.
+ };
+
+ /// OperandFlags - These are flags set on operands, but should be considered
+ /// private, all access should go through the TargetOperandInfo accessors.
+ /// See the accessors for a description of what these are.
+ enum OperandFlags {
+LookupPtrRegClass = 1 << 0,
+Predicate = 1 << 1,
+OptionalDef = 1 << 2
+ };
+}
+
+/// TargetOperandInfo - This holds information about one operand of a machine
+/// instruction, indicating the register class for register operands, etc.
+///
+class TargetOperandInfo {
+public:
+ /// RegClass - This specifies the register class enumeration of the operand
+ /// if the operand is a register. If not, this contains 0.
+ unsigned short RegClass;
+ unsigned short Flags;
+ /// Lower 16 bits are used to specify which constraints are set. The higher
16
+ /// bits are used to specify the value of constraints (4 bits each).
+ unsigned int Constraints;
+ /// Currently no other information.
+
+ /// isLookupPtrRegClass - Set if this operand is a pointer value and it
+ /// requires a callback to look up its register class.
+ bool isLookupPtrRegClass() const { return Flags & TOI::LookupPtrRegClass; }
+
+ /// isPredicate - Set if this is one of the operands that made up of
+ /// the predicate operand that controls an M_PREDICATED instruction.
+ bool isPredicate() const { return Flags & TOI::Predicate; }
+
+ /// isOptionalDef - Set if this operand is a optional def.
+ ///
+ bool isOptionalDef() const { return Flags & TOI::OptionalDef; }
+};
+
+
+//===--===//
+// Machine Instruction Flags and Description
+//===--===//
const unsigned M_BRANCH_FLAG = 1 << 0;
const unsigned M_CALL_FLAG = 1 << 1;
const unsigned M_RET_FLAG = 1 << 2;
const unsigned M_BARRIER_FLAG = 1 << 3;
const unsigned M_DELAY_SLOT_FLAG = 1 << 4;
-
+
/// M_SIMPLE_LOAD_FLAG - This flag is set for instructions that are simple
loads
/// from memory. This should only be set on instructions that load a value
from
/// memory and return it in their only virtual register definition.
const unsigned M_SIMPLE_LOAD_FLAG = 1 << 5;
-
+
/// M_MAY_STORE_FLAG - This flag is set to any instruction that could possibly
/// modify memory. Instructions with this flag set are not necessarily simple
/// store instructions, they may store a modified value based on their
operands,
/// or may not actually modify anything, for example.
const unsigned M_MAY_STORE_FLAG= 1 << 6;
-
+
const unsigned M_INDIRECT_FLAG = 1 << 7;
const unsigned M_IMPLICIT_DEF_FLAG = 1 << 8;
@@ -117,62 +163,15 @@
// both! If neither flag is set, then the instruction *always* has side
effects.
const unsigned M_MAY_HAVE_SIDE_EFFECTS = 1 << 19;
-
-//===--===//
-// Machine operand flags
-//===--===//
-
-namespace TOI {
- // Operand constraints: only "tied_to" for now.
- enum OperandConstraint {
-TIED_TO = 0 // Must be allocated the same register as.
- };
-
- /// OperandFlags - These are flags set on operands, but should be considered
- /// private, all access should go through the TargetOperandInfo accessors.
- /// See the accessors for a description of what these are.
- enum OperandFlags {
-LookupPtrRegClass = 1 << 0,
-Predicate = 1 << 1,
-
[llvm-commits] [llvm] r45687 - in /llvm/trunk: include/llvm/Target/TargetInstrInfo.h lib/CodeGen/MachineInstr.cpp lib/CodeGen/SelectionDAG/ScheduleDAG.cpp lib/Target/X86/X86CodeEmitter.cpp utils/Table
Author: lattner
Date: Sun Jan 6 23:19:29 2008
New Revision: 45687
URL: http://llvm.org/viewvc/llvm-project?rev=45687&view=rev
Log:
rename hasVariableOperands() -> isVariadic(). Add some comments.
Evan, please review the comments I added to getNumDefs to make sure
that they are accurate, thx.
Modified:
llvm/trunk/include/llvm/Target/TargetInstrInfo.h
llvm/trunk/lib/CodeGen/MachineInstr.cpp
llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAG.cpp
llvm/trunk/lib/Target/X86/X86CodeEmitter.cpp
llvm/trunk/utils/TableGen/CodeGenInstruction.cpp
llvm/trunk/utils/TableGen/CodeGenInstruction.h
llvm/trunk/utils/TableGen/DAGISelEmitter.cpp
llvm/trunk/utils/TableGen/InstrInfoEmitter.cpp
Modified: llvm/trunk/include/llvm/Target/TargetInstrInfo.h
URL:
http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Target/TargetInstrInfo.h?rev=45687&r1=45686&r2=45687&view=diff
==
--- llvm/trunk/include/llvm/Target/TargetInstrInfo.h (original)
+++ llvm/trunk/include/llvm/Target/TargetInstrInfo.h Sun Jan 6 23:19:29 2008
@@ -125,9 +125,7 @@
// block.
const unsigned M_USES_CUSTOM_DAG_SCHED_INSERTION = 1 << 12;
-// M_VARIABLE_OPS - Set if this instruction can have a variable number of extra
-// operands in addition to the minimum number operands specified.
-const unsigned M_VARIABLE_OPS = 1 << 13;
+const unsigned M_VARIADIC = 1 << 13;
// M_PREDICABLE - Set if this instruction has a predicate operand that
// controls execution. It may be set to 'always'.
@@ -141,8 +139,6 @@
// (e.g. instructions with unique labels attached).
const unsigned M_NOT_DUPLICABLE= 1 << 16;
-// M_HAS_OPTIONAL_DEF - Set if this instruction has an optional definition,
e.g.
-// ARM instructions which can set condition code if 's' bit is set.
const unsigned M_HAS_OPTIONAL_DEF = 1 << 17;
// M_NEVER_HAS_SIDE_EFFECTS - Set if this instruction has no side effects that
@@ -182,7 +178,7 @@
/// it is set. Returns -1 if it is not set.
int getOperandConstraint(unsigned OpNum,
TOI::OperandConstraint Constraint) const {
-assert((OpNum < NumOperands || hasVariableOperands()) &&
+assert((OpNum < NumOperands || isVariadic()) &&
"Invalid operand # of TargetInstrInfo");
if (OpNum < NumOperands &&
(OpInfo[OpNum].Constraints & (1 << Constraint))) {
@@ -202,18 +198,32 @@
return Name;
}
+ /// getNumOperands - Return the number of declared MachineOperands for this
+ /// MachineInstruction. Note that variadic (isVariadic() returns true)
+ /// instructions may have additional operands at the end of the list, and
note
+ /// that the machine instruction may include implicit register def/uses as
+ /// well.
unsigned getNumOperands() const {
return NumOperands;
}
+ /// getNumDefs - Return the number of MachineOperands that are register
+ /// definitions. Register definitions always occur at the start of the
+ /// machine operand list. This is the number of "outs" in the .td file.
unsigned getNumDefs() const {
return NumDefs;
}
- bool hasVariableOperands() const {
-return Flags & M_VARIABLE_OPS;
+ /// isVariadic - Return true if this instruction can have a variable number
of
+ /// operands. In this case, the variable operands will be after the normal
+ /// operands but before the implicit definitions and uses (if any are
+ /// present).
+ bool isVariadic() const {
+return Flags & M_VARIADIC;
}
+ /// hasOptionalDef - Set if this instruction has an optional definition, e.g.
+ /// ARM instructions which can set condition code if 's' bit is set.
bool hasOptionalDef() const {
return Flags & M_HAS_OPTIONAL_DEF;
}
Modified: llvm/trunk/lib/CodeGen/MachineInstr.cpp
URL:
http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/MachineInstr.cpp?rev=45687&r1=45686&r2=45687&view=diff
==
--- llvm/trunk/lib/CodeGen/MachineInstr.cpp (original)
+++ llvm/trunk/lib/CodeGen/MachineInstr.cpp Sun Jan 6 23:19:29 2008
@@ -488,8 +488,7 @@
///
bool MachineInstr::OperandsComplete() const {
unsigned short NumOperands = TID->getNumOperands();
- if (TID->hasVariableOperands() == 0 &&
- getNumOperands()-NumImplicitOps >= NumOperands)
+ if (!TID->isVariadic() && getNumOperands()-NumImplicitOps >= NumOperands)
return true; // Broken: we have all the operands of this instruction!
return false;
}
@@ -498,7 +497,7 @@
///
unsigned MachineInstr::getNumExplicitOperands() const {
unsigned NumOperands = TID->getNumOperands();
- if (TID->hasVariableOperands() == 0)
+ if (!TID->isVariadic())
return NumOperands;
for (unsigned e = getNumOperands(); NumOperands != e; ++NumOperands) {
Modified: llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAG.cpp
URL:
http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/C
[llvm-commits] [llvm] r45688 - /llvm/trunk/include/llvm/Target/TargetInstrInfo.h
Author: lattner
Date: Sun Jan 6 23:38:38 2008
New Revision: 45688
URL: http://llvm.org/viewvc/llvm-project?rev=45688&view=rev
Log:
add some mroe comments, add a isImplicitDef() method, add
isConditionalBranch() and isUnconditionalBranch() methods.
Modified:
llvm/trunk/include/llvm/Target/TargetInstrInfo.h
Modified: llvm/trunk/include/llvm/Target/TargetInstrInfo.h
URL:
http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Target/TargetInstrInfo.h?rev=45688&r1=45687&r2=45688&view=diff
==
--- llvm/trunk/include/llvm/Target/TargetInstrInfo.h (original)
+++ llvm/trunk/include/llvm/Target/TargetInstrInfo.h Sun Jan 6 23:38:38 2008
@@ -114,10 +114,6 @@
// Z), which produces the same result if Y and Z are exchanged.
const unsigned M_COMMUTABLE= 1 << 10;
-// M_TERMINATOR_FLAG - Is this instruction part of the terminator for a basic
-// block? Typically this is things like return and branch instructions.
-// Various passes use this to insert code into the bottom of a basic block, but
-// before control flow occurs.
const unsigned M_TERMINATOR_FLAG = 1 << 11;
// M_USES_CUSTOM_DAG_SCHED_INSERTION - Set if this instruction requires custom
@@ -228,10 +224,29 @@
return Flags & M_HAS_OPTIONAL_DEF;
}
+ /// getImplicitUses - Return a list of machine operands that are potentially
+ /// read by any instance of this machine instruction. For example, on X86,
+ /// the "adc" instruction adds two register operands and adds the carry bit
in
+ /// from the flags register. In this case, the instruction is marked as
+ /// implicitly reading the flags. Likewise, the variable shift instruction
on
+ /// X86 is marked as implicitly reading the 'CL' register, which it always
+ /// does.
+ ///
+ /// This method returns null if the instruction has no implicit uses.
const unsigned *getImplicitUses() const {
return ImplicitUses;
}
+ /// getImplicitDefs - Return a list of machine operands that are potentially
+ /// written by any instance of this machine instruction. For example, on
X86,
+ /// many instructions implicitly set the flags register. In this case, they
+ /// are marked as setting the FLAGS. Likewise, many instructions always
+ /// deposit their result in a physical register. For example, the X86 divide
+ /// instruction always deposits the quotient and remainder in the EAX/EDX
+ /// registers. For that instruction, this will return a list containing the
+ /// EAX/EDX/EFLAGS registers.
+ ///
+ /// This method returns null if the instruction has no implicit uses.
const unsigned *getImplicitDefs() const {
return ImplicitDefs;
}
@@ -244,18 +259,60 @@
return Flags & M_CALL_FLAG;
}
+ /// isImplicitDef - Return true if this is an "IMPLICIT_DEF" instruction,
+ /// which defines a register to an unspecified value. These basically
+ /// correspond to x = undef.
+ bool isImplicitDef() const {
+return Flags & M_IMPLICIT_DEF_FLAG;
+ }
+
+ /// isBarrier - Returns true if the specified instruction stops control flow
+ /// from executing the instruction immediately following it. Examples
include
+ /// unconditional branches and return instructions.
+ bool isBarrier() const {
+return Flags & M_BARRIER_FLAG;
+ }
+
+ /// isTerminator - Returns true if this instruction part of the terminator
for
+ /// a basic block. Typically this is things like return and branch
+ /// instructions.
+ ///
+ /// Various passes use this to insert code into the bottom of a basic block,
+ /// but before control flow occurs.
bool isTerminator() const {
return Flags & M_TERMINATOR_FLAG;
}
+ /// isBranch - Returns true if this is a conditional, unconditional, or
+ /// indirect branch. Predicates below can be used to discriminate between
+ /// these cases, and the TargetInstrInfo::AnalyzeBranch method can be used to
+ /// get more information.
bool isBranch() const {
return Flags & M_BRANCH_FLAG;
}
-
+
+ /// isIndirectBranch - Return true if this is an indirect branch, such as a
+ /// branch through a register.
bool isIndirectBranch() const {
return Flags & M_INDIRECT_FLAG;
}
+ /// isConditionalBranch - Return true if this is a branch which may fall
+ /// through to the next instruction or may transfer control flow to some
other
+ /// block. The TargetInstrInfo::AnalyzeBranch method can be used to get more
+ /// information about this branch.
+ bool isConditionalBranch() const {
+return isBranch() & !isBarrier() & !isIndirectBranch();
+ }
+
+ /// isUnconditionalBranch - Return true if this is a branch which always
+ /// transfers control flow to some other block. The
+ /// TargetInstrInfo::AnalyzeBranch method can be used to get more information
+ /// about this branch.
+ bool isUnconditionalBranch() const {
+return isBranch() & isBarrier() & !isIndirectBranch();
+ }
+
[llvm-commits] [llvm] r45689 - in /llvm/trunk/lib/CodeGen: IfConversion.cpp LiveIntervalAnalysis.cpp
Author: lattner
Date: Sun Jan 6 23:40:58 2008
New Revision: 45689
URL: http://llvm.org/viewvc/llvm-project?rev=45689&view=rev
Log:
simplify some code using new predicates
Modified:
llvm/trunk/lib/CodeGen/IfConversion.cpp
llvm/trunk/lib/CodeGen/LiveIntervalAnalysis.cpp
Modified: llvm/trunk/lib/CodeGen/IfConversion.cpp
URL:
http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/IfConversion.cpp?rev=45689&r1=45688&r2=45689&view=diff
==
--- llvm/trunk/lib/CodeGen/IfConversion.cpp (original)
+++ llvm/trunk/lib/CodeGen/IfConversion.cpp Sun Jan 6 23:40:58 2008
@@ -26,26 +26,24 @@
#include "llvm/ADT/STLExtras.h"
using namespace llvm;
-namespace {
- // Hidden options for help debugging.
- cl::opt IfCvtFnStart("ifcvt-fn-start", cl::init(-1), cl::Hidden);
- cl::opt IfCvtFnStop("ifcvt-fn-stop", cl::init(-1), cl::Hidden);
- cl::opt IfCvtLimit("ifcvt-limit", cl::init(-1), cl::Hidden);
- cl::opt DisableSimple("disable-ifcvt-simple",
- cl::init(false), cl::Hidden);
- cl::opt DisableSimpleF("disable-ifcvt-simple-false",
- cl::init(false), cl::Hidden);
- cl::opt DisableTriangle("disable-ifcvt-triangle",
-cl::init(false), cl::Hidden);
- cl::opt DisableTriangleR("disable-ifcvt-triangle-rev",
- cl::init(false), cl::Hidden);
- cl::opt DisableTriangleF("disable-ifcvt-triangle-false",
- cl::init(false), cl::Hidden);
- cl::opt DisableTriangleFR("disable-ifcvt-triangle-false-rev",
- cl::init(false), cl::Hidden);
- cl::opt DisableDiamond("disable-ifcvt-diamond",
- cl::init(false), cl::Hidden);
-}
+// Hidden options for help debugging.
+static cl::opt IfCvtFnStart("ifcvt-fn-start", cl::init(-1), cl::Hidden);
+static cl::opt IfCvtFnStop("ifcvt-fn-stop", cl::init(-1), cl::Hidden);
+static cl::opt IfCvtLimit("ifcvt-limit", cl::init(-1), cl::Hidden);
+static cl::opt DisableSimple("disable-ifcvt-simple",
+ cl::init(false), cl::Hidden);
+static cl::opt DisableSimpleF("disable-ifcvt-simple-false",
+cl::init(false), cl::Hidden);
+static cl::opt DisableTriangle("disable-ifcvt-triangle",
+ cl::init(false), cl::Hidden);
+static cl::opt DisableTriangleR("disable-ifcvt-triangle-rev",
+ cl::init(false), cl::Hidden);
+static cl::opt DisableTriangleF("disable-ifcvt-triangle-false",
+ cl::init(false), cl::Hidden);
+static cl::opt DisableTriangleFR("disable-ifcvt-triangle-false-rev",
+ cl::init(false), cl::Hidden);
+static cl::opt DisableDiamond("disable-ifcvt-diamond",
+cl::init(false), cl::Hidden);
STATISTIC(NumSimple, "Number of simple if-conversions performed");
STATISTIC(NumSimpleFalse, "Number of simple (F) if-conversions performed");
@@ -555,7 +553,7 @@
BBI.CannotBeCopied = true;
bool isPredicated = TII->isPredicated(I);
-bool isCondBr = BBI.IsBrAnalyzable && TID->isBranch() && !TID->isBarrier();
+bool isCondBr = BBI.IsBrAnalyzable && TID->isConditionalBranch();
if (!isCondBr) {
if (!isPredicated)
Modified: llvm/trunk/lib/CodeGen/LiveIntervalAnalysis.cpp
URL:
http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/LiveIntervalAnalysis.cpp?rev=45689&r1=45688&r2=45689&view=diff
==
--- llvm/trunk/lib/CodeGen/LiveIntervalAnalysis.cpp (original)
+++ llvm/trunk/lib/CodeGen/LiveIntervalAnalysis.cpp Sun Jan 6 23:40:58 2008
@@ -616,8 +616,7 @@
isLoad = false;
const TargetInstrDescriptor *TID = MI->getDesc();
- if ((TID->Flags & M_IMPLICIT_DEF_FLAG) ||
- tii_->isTriviallyReMaterializable(MI)) {
+ if (TID->isImplicitDef() || tii_->isTriviallyReMaterializable(MI)) {
isLoad = TID->isSimpleLoad();
return true;
}
@@ -682,7 +681,7 @@
unsigned MRInfo = 0;
const TargetInstrDescriptor *TID = MI->getDesc();
// If it is an implicit def instruction, just delete it.
- if (TID->Flags & M_IMPLICIT_DEF_FLAG) {
+ if (TID->isImplicitDef()) {
RemoveMachineInstrFromMaps(MI);
vrm.RemoveMachineInstrFromMaps(MI);
MI->eraseFromParent();
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Re: [llvm-commits] [llvm] r45676 - in /llvm/trunk: include/llvm/CallingConv.h include/llvm/CodeGen/LinkAllCodegenComponents.h lib/CodeGen/OcamlCollector.cpp test/CodeGen/Generic/GC/frame_size.ll test/
On Jan 6, 2008, at 6:31 PM, Gordon Henriksen wrote: > URL: http://llvm.org/viewvc/llvm-project?rev=45676&view=rev > Log: > Setting GlobalDirective in TargetAsmInfo by default rather than > providing a misleading facility. It's used once in the MIPS backend > and hardcoded as "\t.globl\t" everywhere else. Hi Gordon, this commit message doesn't line up. > = > = > = > = > = > = > = > = > == > --- llvm/trunk/include/llvm/CallingConv.h (original) > +++ llvm/trunk/include/llvm/CallingConv.h Sun Jan 6 20:31:11 2008 > @@ -57,7 +57,12 @@ > /// X86_FastCall - 'fast' analog of X86_StdCall. Passes first > two arguments > /// in ECX:EDX registers, others - via stack. Callee is > responsible for > /// stack cleaning. > -X86_FastCall = 65 > +X86_FastCall = 65, > + > +/// X86_Ocaml - This is a weird ABI used by Objective Caml. > Formally, it > +/// supports only one to six integer/address arguments, all in- > reg. It also > +/// supports tail call emission. > +X86_Ocaml = 66 This looks dead, accidental commit? > +#include "llvm/CodeGen/Collectors.h" > +#include "llvm/ADT/DenseMap.h" > +#include "llvm/CodeGen/AsmPrinter.h" > +#include "llvm/CodeGen/Collector.h" > +#include "llvm/CodeGen/CollectorMetadata.h" > +#include "llvm/Function.h" > +#include "llvm/Module.h" Please try to prune down the #includes to a minimum, Function.h can certainly go, if others can too, please remove them as well. > +#include "llvm/Target/TargetData.h" > +#include "llvm/Target/TargetMachine.h" > +#include How about ? Otherwise, looks great :) -Chris ___ llvm-commits mailing list llvm-commits@cs.uiuc.edu http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
Re: [llvm-commits] [llvm] r45626 - /llvm/trunk/lib/Target/X86/X86InstrInfo.cpp
On Jan 6, 2008, at 6:45 PM, Evan Cheng wrote: > By the way. This check is still not quite right. > > // Loads from stubs of global addresses are side effect free. > if (Reg != 0 && MRegisterInfo::isVirtualRegister(Reg) && > > In dynamic-no-pic mode, Reg can be 0. So it should be Reg == 0 || ... Why is this code even looking at that operand? -Chris ___ llvm-commits mailing list llvm-commits@cs.uiuc.edu http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
[llvm-commits] [llvm] r45690 - in /llvm/trunk: include/llvm/Target/TargetInstrInfo.h lib/CodeGen/SelectionDAG/ScheduleDAG.cpp lib/CodeGen/TwoAddressInstructionPass.cpp
Author: lattner
Date: Mon Jan 7 00:21:53 2008
New Revision: 45690
URL: http://llvm.org/viewvc/llvm-project?rev=45690&view=rev
Log:
add more and significantly better comments to the rest of the machineinstr
flags that can be set. Add predicates for the ones lacking it, and switch
some clients over to using the predicates instead of Flags directly.
Modified:
llvm/trunk/include/llvm/Target/TargetInstrInfo.h
llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAG.cpp
llvm/trunk/lib/CodeGen/TwoAddressInstructionPass.cpp
Modified: llvm/trunk/include/llvm/Target/TargetInstrInfo.h
URL:
http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Target/TargetInstrInfo.h?rev=45690&r1=45689&r2=45690&view=diff
==
--- llvm/trunk/include/llvm/Target/TargetInstrInfo.h (original)
+++ llvm/trunk/include/llvm/Target/TargetInstrInfo.h Mon Jan 7 00:21:53 2008
@@ -71,7 +71,7 @@
bool isLookupPtrRegClass() const { return Flags & TOI::LookupPtrRegClass; }
/// isPredicate - Set if this is one of the operands that made up of
- /// the predicate operand that controls an M_PREDICATED instruction.
+ /// the predicate operand that controls an isPredicable() instruction.
bool isPredicate() const { return Flags & TOI::Predicate; }
/// isOptionalDef - Set if this operand is a optional def.
@@ -89,70 +89,20 @@
const unsigned M_RET_FLAG = 1 << 2;
const unsigned M_BARRIER_FLAG = 1 << 3;
const unsigned M_DELAY_SLOT_FLAG = 1 << 4;
-
-/// M_SIMPLE_LOAD_FLAG - This flag is set for instructions that are simple
loads
-/// from memory. This should only be set on instructions that load a value
from
-/// memory and return it in their only virtual register definition.
const unsigned M_SIMPLE_LOAD_FLAG = 1 << 5;
-
-/// M_MAY_STORE_FLAG - This flag is set to any instruction that could possibly
-/// modify memory. Instructions with this flag set are not necessarily simple
-/// store instructions, they may store a modified value based on their
operands,
-/// or may not actually modify anything, for example.
const unsigned M_MAY_STORE_FLAG= 1 << 6;
-
const unsigned M_INDIRECT_FLAG = 1 << 7;
const unsigned M_IMPLICIT_DEF_FLAG = 1 << 8;
-
-// M_CONVERTIBLE_TO_3_ADDR - This is a 2-address instruction which can be
-// changed into a 3-address instruction if the first two operands cannot be
-// assigned to the same register. The target must implement the
-// TargetInstrInfo::convertToThreeAddress method for this instruction.
const unsigned M_CONVERTIBLE_TO_3_ADDR = 1 << 9;
-
-// This M_COMMUTABLE - is a 2- or 3-address instruction (of the form X = op Y,
-// Z), which produces the same result if Y and Z are exchanged.
const unsigned M_COMMUTABLE= 1 << 10;
-
const unsigned M_TERMINATOR_FLAG = 1 << 11;
-
-// M_USES_CUSTOM_DAG_SCHED_INSERTION - Set if this instruction requires custom
-// insertion support when the DAG scheduler is inserting it into a machine
basic
-// block.
const unsigned M_USES_CUSTOM_DAG_SCHED_INSERTION = 1 << 12;
-
-const unsigned M_VARIADIC = 1 << 13;
-
-// M_PREDICABLE - Set if this instruction has a predicate operand that
-// controls execution. It may be set to 'always'.
+const unsigned M_VARIADIC = 1 << 13;
const unsigned M_PREDICABLE= 1 << 14;
-
-// M_REMATERIALIZIBLE - Set if this instruction can be trivally re-materialized
-// at any time, e.g. constant generation, load from constant pool.
const unsigned M_REMATERIALIZIBLE = 1 << 15;
-
-// M_NOT_DUPLICABLE - Set if this instruction cannot be safely duplicated.
-// (e.g. instructions with unique labels attached).
const unsigned M_NOT_DUPLICABLE= 1 << 16;
-
const unsigned M_HAS_OPTIONAL_DEF = 1 << 17;
-
-// M_NEVER_HAS_SIDE_EFFECTS - Set if this instruction has no side effects that
-// are not captured by any operands of the instruction or other flags, and when
-// *all* instances of the instruction of that opcode have no side effects.
-//
-// Note: This and M_MAY_HAVE_SIDE_EFFECTS are mutually exclusive. You can't set
-// both! If neither flag is set, then the instruction *always* has side
effects.
const unsigned M_NEVER_HAS_SIDE_EFFECTS = 1 << 18;
-
-// M_MAY_HAVE_SIDE_EFFECTS - Set if some instances of this instruction can have
-// side effects. The virtual method "isReallySideEffectFree" is called to
-// determine this. Load instructions are an example of where this is useful. In
-// general, loads always have side effects. However, loads from constant pools
-// don't. We let the specific back end make this determination.
-//
-// Note: This and M_NEVER_HAS_SIDE_EFFECTS are mutually exclusive. You can't
set
-// both! If neither flag is set, then the instruction *always* has side
effects.
const unsigned M_MAY_HAVE_SIDE_EFFECTS = 1 << 19;
@@ -250,6 +200,15 @@
const unsigned *getImplicitDefs() const {
return ImplicitDefs;
[llvm-commits] [llvm] r45691 - /llvm/trunk/lib/Target/PowerPC/PPCHazardRecognizers.cpp
Author: lattner Date: Mon Jan 7 00:37:29 2008 New Revision: 45691 URL: http://llvm.org/viewvc/llvm-project?rev=45691&view=rev Log: use predicate. Modified: llvm/trunk/lib/Target/PowerPC/PPCHazardRecognizers.cpp Modified: llvm/trunk/lib/Target/PowerPC/PPCHazardRecognizers.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PowerPC/PPCHazardRecognizers.cpp?rev=45691&r1=45690&r2=45691&view=diff == --- llvm/trunk/lib/Target/PowerPC/PPCHazardRecognizers.cpp (original) +++ llvm/trunk/lib/Target/PowerPC/PPCHazardRecognizers.cpp Mon Jan 7 00:37:29 2008 @@ -73,7 +73,7 @@ const TargetInstrDescriptor &TID = TII.get(Opcode); isLoad = TID.isSimpleLoad(); - isStore = TID.Flags & M_MAY_STORE_FLAG; + isStore = TID.mayStore(); unsigned TSFlags = TID.TSFlags; ___ llvm-commits mailing list llvm-commits@cs.uiuc.edu http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
[llvm-commits] [llvm] r45692 - in /llvm/trunk: include/llvm/Target/TargetInstrInfo.h lib/CodeGen/SelectionDAG/ScheduleDAG.cpp lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp lib/CodeGen/TwoAddressInstr
Author: lattner
Date: Mon Jan 7 00:42:05 2008
New Revision: 45692
URL: http://llvm.org/viewvc/llvm-project?rev=45692&view=rev
Log:
Rename all the M_* flags to be namespace qualified enums, and switch
all clients over to using predicates instead of these flags directly.
These are now private values which are only to be used to statically
initialize the tables.
Modified:
llvm/trunk/include/llvm/Target/TargetInstrInfo.h
llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAG.cpp
llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp
llvm/trunk/lib/CodeGen/TwoAddressInstructionPass.cpp
llvm/trunk/lib/Target/ARM/ARMInstrInfo.cpp
llvm/trunk/utils/TableGen/InstrInfoEmitter.cpp
Modified: llvm/trunk/include/llvm/Target/TargetInstrInfo.h
URL:
http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Target/TargetInstrInfo.h?rev=45692&r1=45691&r2=45692&view=diff
==
--- llvm/trunk/include/llvm/Target/TargetInstrInfo.h (original)
+++ llvm/trunk/include/llvm/Target/TargetInstrInfo.h Mon Jan 7 00:42:05 2008
@@ -22,8 +22,6 @@
namespace llvm {
-class MachineInstr;
-class TargetMachine;
class TargetRegisterClass;
class LiveVariables;
class CalleeSavedInfo;
@@ -46,9 +44,9 @@
/// private, all access should go through the TargetOperandInfo accessors.
/// See the accessors for a description of what these are.
enum OperandFlags {
-LookupPtrRegClass = 1 << 0,
-Predicate = 1 << 1,
-OptionalDef = 1 << 2
+LookupPtrRegClass = 0,
+Predicate,
+OptionalDef
};
}
@@ -68,15 +66,15 @@
/// isLookupPtrRegClass - Set if this operand is a pointer value and it
/// requires a callback to look up its register class.
- bool isLookupPtrRegClass() const { return Flags & TOI::LookupPtrRegClass; }
+ bool isLookupPtrRegClass() const { return Flags&(1
isCommutable = true;
}
Modified: llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp
URL:
http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp?rev=45692&r1=45691&r2=45692&view=diff
==
--- llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp (original)
+++ llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp Mon Jan 7
00:42:05 2008
@@ -437,7 +437,7 @@
break;
}
}
-if (TID->Flags & M_COMMUTABLE)
+if (TID->isCommutable())
NewSU->isCommutable = true;
// FIXME: Calculate height / depth and propagate the changes?
NewSU->Depth = SU->Depth;
Modified: llvm/trunk/lib/CodeGen/TwoAddressInstructionPass.cpp
URL:
http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/TwoAddressInstructionPass.cpp?rev=45692&r1=45691&r2=45692&view=diff
==
--- llvm/trunk/lib/CodeGen/TwoAddressInstructionPass.cpp (original)
+++ llvm/trunk/lib/CodeGen/TwoAddressInstructionPass.cpp Mon Jan 7 00:42:05
2008
@@ -144,7 +144,7 @@
// so, swap the B and C operands. This makes the live ranges of A
// and C joinable.
// FIXME: This code also works for A := B op C instructions.
-if ((TID->Flags & M_COMMUTABLE) && mi->getNumOperands() >= 3) {
+if (TID->isCommutable() && mi->getNumOperands() >= 3) {
assert(mi->getOperand(3-si).isRegister() &&
"Not a proper commutative instruction!");
unsigned regC = mi->getOperand(3-si).getReg();
Modified: llvm/trunk/lib/Target/ARM/ARMInstrInfo.cpp
URL:
http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrInfo.cpp?rev=45692&r1=45691&r2=45692&view=diff
==
--- llvm/trunk/lib/Target/ARM/ARMInstrInfo.cpp (original)
+++ llvm/trunk/lib/Target/ARM/ARMInstrInfo.cpp Mon Jan 7 00:42:05 2008
@@ -838,7 +838,7 @@
bool ARMInstrInfo::DefinesPredicate(MachineInstr *MI,
std::vector &Pred) const {
const TargetInstrDescriptor *TID = MI->getDesc();
- if (!TID->ImplicitDefs && (TID->Flags & M_HAS_OPTIONAL_DEF) == 0)
+ if (!TID->getImplicitDefs() && !TID->hasOptionalDef())
return false;
bool Found = false;
Modified: llvm/trunk/utils/TableGen/InstrInfoEmitter.cpp
URL:
http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/TableGen/InstrInfoEmitter.cp
[llvm-commits] [llvm] r45693 - /llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp
Author: lattner
Date: Mon Jan 7 00:47:00 2008
New Revision: 45693
URL: http://llvm.org/viewvc/llvm-project?rev=45693&view=rev
Log:
simplify some code.
Modified:
llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp
Modified: llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp
URL:
http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp?rev=45693&r1=45692&r2=45693&view=diff
==
--- llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp (original)
+++ llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp Mon Jan 7
00:47:00 2008
@@ -148,10 +148,11 @@
if (!SU || !SU->Node) continue;
if (SU->isCommutable) {
unsigned Opc = SU->Node->getTargetOpcode();
- unsigned NumRes = TII->get(Opc).getNumDefs();
+ const TargetInstrDescriptor &TID = TII->get(Opc);
+ unsigned NumRes = TID.getNumDefs();
unsigned NumOps = CountOperands(SU->Node);
for (unsigned j = 0; j != NumOps; ++j) {
-if (TII->getOperandConstraint(Opc, j+NumRes, TOI::TIED_TO) == -1)
+if (TID.getOperandConstraint(j+NumRes, TOI::TIED_TO) == -1)
continue;
SDNode *OpN = SU->Node->getOperand(j).Val;
@@ -430,14 +431,14 @@
SUnit *NewSU = NewSUnit(N);
SUnitMap[N].push_back(NewSU);
-const TargetInstrDescriptor *TID = &TII->get(N->getTargetOpcode());
-for (unsigned i = 0; i != TID->getNumOperands(); ++i) {
- if (TID->getOperandConstraint(i, TOI::TIED_TO) != -1) {
+const TargetInstrDescriptor &TID = TII->get(N->getTargetOpcode());
+for (unsigned i = 0; i != TID.getNumOperands(); ++i) {
+ if (TID.getOperandConstraint(i, TOI::TIED_TO) != -1) {
NewSU->isTwoAddress = true;
break;
}
}
-if (TID->isCommutable())
+if (TID.isCommutable())
NewSU->isCommutable = true;
// FIXME: Calculate height / depth and propagate the changes?
NewSU->Depth = SU->Depth;
@@ -1287,10 +1288,11 @@
bool BURegReductionPriorityQueue::canClobber(SUnit *SU, SUnit *Op) {
if (SU->isTwoAddress) {
unsigned Opc = SU->Node->getTargetOpcode();
-unsigned NumRes = TII->get(Opc).getNumDefs();
+const TargetInstrDescriptor &TID = TII->get(Opc);
+unsigned NumRes = TID.getNumDefs();
unsigned NumOps = ScheduleDAG::CountOperands(SU->Node);
for (unsigned i = 0; i != NumOps; ++i) {
- if (TII->getOperandConstraint(Opc, i+NumRes, TOI::TIED_TO) != -1) {
+ if (TID.getOperandConstraint(i+NumRes, TOI::TIED_TO) != -1) {
SDNode *DU = SU->Node->getOperand(i).Val;
if ((*SUnitMap).find(DU) != (*SUnitMap).end() &&
Op == (*SUnitMap)[DU][SU->InstanceNo])
@@ -1362,10 +1364,11 @@
continue;
unsigned Opc = Node->getTargetOpcode();
-unsigned NumRes = TII->get(Opc).getNumDefs();
+const TargetInstrDescriptor &TID = TII->get(Opc);
+unsigned NumRes = TID.getNumDefs();
unsigned NumOps = ScheduleDAG::CountOperands(Node);
for (unsigned j = 0; j != NumOps; ++j) {
- if (TII->getOperandConstraint(Opc, j+NumRes, TOI::TIED_TO) != -1) {
+ if (TID.getOperandConstraint(j+NumRes, TOI::TIED_TO) != -1) {
SDNode *DU = SU->Node->getOperand(j).Val;
if ((*SUnitMap).find(DU) == (*SUnitMap).end())
continue;
___
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[llvm-commits] [llvm] r45694 - /llvm/trunk/include/llvm/Target/TargetInstrInfo.h
Author: lattner
Date: Mon Jan 7 00:47:10 2008
New Revision: 45694
URL: http://llvm.org/viewvc/llvm-project?rev=45694&view=rev
Log:
remove a dead method.
Modified:
llvm/trunk/include/llvm/Target/TargetInstrInfo.h
Modified: llvm/trunk/include/llvm/Target/TargetInstrInfo.h
URL:
http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Target/TargetInstrInfo.h?rev=45694&r1=45693&r2=45694&view=diff
==
--- llvm/trunk/include/llvm/Target/TargetInstrInfo.h (original)
+++ llvm/trunk/include/llvm/Target/TargetInstrInfo.h Mon Jan 7 00:47:10 2008
@@ -490,13 +490,6 @@
return false;
}
public:
- /// getOperandConstraint - Returns the value of the specific constraint if
- /// it is set. Returns -1 if it is not set.
- int getOperandConstraint(unsigned Opcode, unsigned OpNum,
- TOI::OperandConstraint Constraint) const {
-return get(Opcode).getOperandConstraint(OpNum, Constraint);
- }
-
/// Return true if the instruction is a register to register move
/// and leave the source and dest operands in the passed parameters.
virtual bool isMoveInstr(const MachineInstr& MI,
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