Author: resistor
Date: Sun Jan 6 19:35:56 2008
New Revision: 45673
URL: http://llvm.org/viewvc/llvm-project?rev=45673&view=rev
Log:
Update CodeGen for MRegisterInfo --> TargetInstrInfo changes.
Modified:
llvm/trunk/lib/CodeGen/LiveIntervalAnalysis.cpp
llvm/trunk/lib/CodeGen/RegAllocBigBlock.cpp
llvm/trunk/lib/CodeGen/RegAllocLocal.cpp
llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp
llvm/trunk/lib/CodeGen/VirtRegMap.cpp
Modified: llvm/trunk/lib/CodeGen/LiveIntervalAnalysis.cpp
URL:
http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/LiveIntervalAnalysis.cpp?rev=45673&r1=45672&r2=45673&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/LiveIntervalAnalysis.cpp (original)
+++ llvm/trunk/lib/CodeGen/LiveIntervalAnalysis.cpp Sun Jan 6 19:35:56 2008
@@ -709,8 +709,8 @@
FoldOps.push_back(OpIdx);
}
- MachineInstr *fmi = isSS ? mri_->foldMemoryOperand(MI, FoldOps, Slot)
- : mri_->foldMemoryOperand(MI, FoldOps, DefMI);
+ MachineInstr *fmi = isSS ? tii_->foldMemoryOperand(MI, FoldOps, Slot)
+ : tii_->foldMemoryOperand(MI, FoldOps, DefMI);
if (fmi) {
// Attempt to fold the memory reference into the instruction. If
// we can do this, we don't need to insert spill code.
@@ -746,7 +746,7 @@
FoldOps.push_back(OpIdx);
}
- return mri_->canFoldMemoryOperand(MI, FoldOps);
+ return tii_->canFoldMemoryOperand(MI, FoldOps);
}
bool LiveIntervals::intervalIsInOneMBB(const LiveInterval &li) const {
Modified: llvm/trunk/lib/CodeGen/RegAllocBigBlock.cpp
URL:
http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/RegAllocBigBlock.cpp?rev=45673&r1=45672&r2=45673&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/RegAllocBigBlock.cpp (original)
+++ llvm/trunk/lib/CodeGen/RegAllocBigBlock.cpp Sun Jan 6 19:35:56 2008
@@ -505,6 +505,7 @@
MachineInstr *RABigBlock::reloadVirtReg(MachineBasicBlock &MBB, MachineInstr
*MI,
unsigned OpNum) {
unsigned VirtReg = MI->getOperand(OpNum).getReg();
+ const TargetInstrInfo* TII = MBB.getParent()->getTarget().getInstrInfo();
// If the virtual register is already available in a physical register,
// just update the instruction and return.
@@ -525,7 +526,7 @@
// try to fold the spill into the instruction
SmallVector<unsigned, 2> Ops;
Ops.push_back(OpNum);
- if(MachineInstr* FMI = RegInfo->foldMemoryOperand(MI, Ops, FrameIndex)) {
+ if(MachineInstr* FMI = TII->foldMemoryOperand(MI, Ops, FrameIndex)) {
++NumFolded;
// Since we changed the address of MI, make sure to update live variables
// to know that the new instruction has the properties of the old one.
@@ -545,7 +546,6 @@
<< RegInfo->getName(PhysReg) << "\n";
// Add move instruction(s)
- const TargetInstrInfo* TII = MBB.getParent()->getTarget().getInstrInfo();
TII->loadRegFromStackSlot(MBB, MI, PhysReg, FrameIndex, RC);
++NumLoads; // Update statistics
Modified: llvm/trunk/lib/CodeGen/RegAllocLocal.cpp
URL:
http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/RegAllocLocal.cpp?rev=45673&r1=45672&r2=45673&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/RegAllocLocal.cpp (original)
+++ llvm/trunk/lib/CodeGen/RegAllocLocal.cpp Sun Jan 6 19:35:56 2008
@@ -50,6 +50,7 @@
const TargetMachine *TM;
MachineFunction *MF;
const MRegisterInfo *MRI;
+ const TargetInstrInfo *TII;
LiveVariables *LV;
// StackSlotForVirtReg - Maps virtual regs to the frame index where these
@@ -478,7 +479,7 @@
// If we can fold this spill into this instruction, do so now.
SmallVector<unsigned, 2> Ops;
Ops.push_back(OpNum);
- if (MachineInstr* FMI = MRI->foldMemoryOperand(MI, Ops, FrameIndex)) {
+ if (MachineInstr* FMI = TII->foldMemoryOperand(MI, Ops, FrameIndex)) {
++NumFolded;
// Since we changed the address of MI, make sure to update live variables
// to know that the new instruction has the properties of the old one.
@@ -801,6 +802,7 @@
MF = &Fn;
TM = &Fn.getTarget();
MRI = TM->getRegisterInfo();
+ TII = TM->getInstrInfo();
LV = &getAnalysis<LiveVariables>();
PhysRegsUsed.assign(MRI->getNumRegs(), -1);
Modified: llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp
URL:
http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp?rev=45673&r1=45672&r2=45673&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp (original)
+++ llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp Sun Jan 6
19:35:56 2008
@@ -413,7 +413,7 @@
if (TryUnfold) {
SmallVector<SDNode*, 4> NewNodes;
- if (!MRI->unfoldMemoryOperand(DAG, N, NewNodes))
+ if (!TII->unfoldMemoryOperand(DAG, N, NewNodes))
return NULL;
DOUT << "Unfolding SU # " << SU->NodeNum << "\n";
Modified: llvm/trunk/lib/CodeGen/VirtRegMap.cpp
URL:
http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/VirtRegMap.cpp?rev=45673&r1=45672&r2=45673&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/VirtRegMap.cpp (original)
+++ llvm/trunk/lib/CodeGen/VirtRegMap.cpp Sun Jan 6 19:35:56 2008
@@ -793,7 +793,7 @@
DeadStore->findRegisterUseOperandIdx(PhysReg, true) == -1)
continue;
UnfoldPR = PhysReg;
- UnfoldedOpc = MRI->getOpcodeAfterMemoryUnfold(MI.getOpcode(),
+ UnfoldedOpc = TII->getOpcodeAfterMemoryUnfold(MI.getOpcode(),
false, true);
}
}
@@ -831,7 +831,7 @@
// unfolded. This allows us to perform the store unfolding
// optimization.
SmallVector<MachineInstr*, 4> NewMIs;
- if (MRI->unfoldMemoryOperand(MF, &MI, UnfoldVR, false, false, NewMIs)) {
+ if (TII->unfoldMemoryOperand(MF, &MI, UnfoldVR, false, false, NewMIs)) {
assert(NewMIs.size() == 1);
MachineInstr *NewMI = NewMIs.back();
NewMIs.clear();
@@ -839,7 +839,7 @@
assert(Idx != -1);
SmallVector<unsigned, 2> Ops;
Ops.push_back(Idx);
- MachineInstr *FoldedMI = MRI->foldMemoryOperand(NewMI, Ops, SS);
+ MachineInstr *FoldedMI = TII->foldMemoryOperand(NewMI, Ops, SS);
if (FoldedMI) {
if (!VRM.hasPhys(UnfoldVR))
VRM.assignVirt2Phys(UnfoldVR, UnfoldPR);
@@ -1294,7 +1294,7 @@
unsigned PhysReg = Spills.getSpillSlotOrReMatPhysReg(SS);
SmallVector<MachineInstr*, 4> NewMIs;
if (PhysReg &&
- MRI->unfoldMemoryOperand(MF, &MI, PhysReg, false, false,
NewMIs)) {
+ TII->unfoldMemoryOperand(MF, &MI, PhysReg, false, false,
NewMIs)) {
MBB.insert(MII, NewMIs[0]);
VRM.RemoveMachineInstrFromMaps(&MI);
MBB.erase(&MI);
@@ -1321,7 +1321,7 @@
if (PhysReg &&
!TII->isStoreToStackSlot(&MI, SS) && // Not profitable!
DeadStore->findRegisterUseOperandIdx(PhysReg, true) != -1 &&
- MRI->unfoldMemoryOperand(MF, &MI, PhysReg, false, true, NewMIs))
{
+ TII->unfoldMemoryOperand(MF, &MI, PhysReg, false, true, NewMIs))
{
MBB.insert(MII, NewMIs[0]);
NewStore = NewMIs[1];
MBB.insert(MII, NewStore);
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