Re: [llvm-commits] Patch for X86 to use subregs
On Jul 29, 2007, at 10:20 PM, Evan Cheng wrote: On Jul 29, 2007, at 9:37 PM, Christopher Lamb wrote: On Jul 29, 2007, at 6:20 PM, Evan Cheng wrote: Sent from my iPhone On Jul 28, 2007, at 4:36 PM, Christopher Lamb <[EMAIL PROTECTED]> wrote: On Jul 28, 2007, at 2:26 PM, Evan Cheng wrote: On Jul 28, 2007, at 11:52 AM, Christopher Lamb <[EMAIL PROTECTED]> wrote: On Jul 28, 2007, at 1:48 AM, Evan Cheng wrote: Very cool! I need to read it more carefully. But I see you are lowering zext to a single insert_subreg. Is that right? It won't zero out the top part, no? It's only lowering (zext i32 to i64) to an insert_subreg on x86-64 where all writes to 32-bit registers implicitly zero- extend into the upper 32-bits. I know. But thy mismatch semantically. A insert_subreg to the lower part should not change the upper half. I think this is only legal for anyext. On x86-64 the semantics of a 2 operand i32 insert_subreg is that the input super-value is implicitly zero. So in this sense the insert isn't changing the upper half, it's just that the upper half is being set to zero implicitly rather than explicitly. If you'll notice the insert_subreg is a two operand (implicit super value) not a three operand version. If the insert were the three operand version, and the super value as coming from an implicit def I'd agree with you, but it's not. Ok, let's step back for a second. There are a couple of issues that should be addressed. Plz help me understand. :) 1: Semantics of insert_subreg should be the same across all targets, right? I'm not certain that this should be so. x86-64 clearly has a target specific semantics of a 32-bit into 64-bit insert. No, that won't do. insert_subreg and extract_subreg are by definition target independent. They must have the same semantics. You are forcing x86-64 32-bit zero-extending move to fit insert_subreg when they are really not the same thing. If target independence is a requirement, then I agree that using insert_subreg for x86-64 zero-ext isn't currently feasible. 2: two operant variant of insert_subreg should mean the superreg is undef. If you insert a value into a low part, the rest of the superreg is still undef. I think the meaning of insert_subreg instruction (both 2 and 3 operand versions) must have semantics specific to the target. For example, on x86-64 there is no valid 3 operand insert_subreg for a 32-bit value into 64-bits, because the 32-bit result is always going to be zero extended and overwrite the upper 32-bits. It just means there is no way to implement a insert_subreg with a single instruction under x86-64. But that is perfectly ok. Apart from anyext, x86-64 just isn't going to benefit from it. It's also impossible to read or modify the higher 32-bits. Currently the move that's generated isn't handled by coalescing because the source and destination belong to different register classes. The insert_subreg is meant to be a means to move values implicitly between register classes that have a subreg relationship. So if insert_subreg semantics must be target independent, then I think you isel the zero-extending move to be: (i64 (INSERT_SUBREG (i64 0), GR32:$src, 3)) The thing is that the general coalescing will be able to determine that the copy from undef is unneeded for (INSERT_SUBREG (i64 undef), GR32:$src, 3), but it would take a target specific hook to know that the constant zero is unneeded on x86-64. A target specific hook for this might be useful, but I think that this is in the realm of future work now. 3: why is there a two operant variant in the first place? Why not use undef for the superreg operant? To note, the two operand variant is of the MachineInstr. The DAG form would be to represent the superregister as coming from an undef node, but this gets isel'd to the two operand MachineInstr of insert_subreg. The reason is that undef is typically selected to an implicit def of a register. This causes an unnecessary move to be generated later on. This move can be optimized away later with more difficulty during subreg lowering by checking whether the input register is defined by an implicit def pseudo instruction, but instead I decided to perform the optimization during ISel on the DAG form during instruction selection. With what you're suggesting reg1024 = ... reg1026 = insert_subreg undef, reg1024, 1 reg1027 = insert_subreg reg1026, reg1025, 1 use reg1027 would be isel'd to then subreg lowered to: R6 = ... implicit def R01 <= this implicit def is unecessary That's a pseudo instruction, it doesn't cost anything. R23 = R01 <= this copy is unnecessary It can be coalesced to: R23 = undef R2 = R6 R45 = R23 R5 = R6 use R45 Using undef explicit is the right way to go. There is a good reason it's there. Having the two operand version of insert_subreg that implicitly use an undef value doesn't fi
[llvm-commits] [llvm] r40586 - in /llvm/trunk/lib/Target/PowerPC: PPCISelLowering.cpp PPCISelLowering.h PPCInstrAltivec.td
Author: evancheng
Date: Mon Jul 30 02:51:22 2007
New Revision: 40586
URL: http://llvm.org/viewvc/llvm-project?rev=40586&view=rev
Log:
Vector fneg must be expanded into fsub -0.0, X.
Modified:
llvm/trunk/lib/Target/PowerPC/PPCISelLowering.cpp
llvm/trunk/lib/Target/PowerPC/PPCISelLowering.h
llvm/trunk/lib/Target/PowerPC/PPCInstrAltivec.td
Modified: llvm/trunk/lib/Target/PowerPC/PPCISelLowering.cpp
URL:
http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PowerPC/PPCISelLowering.cpp?rev=40586&r1=40585&r2=40586&view=diff
==
--- llvm/trunk/lib/Target/PowerPC/PPCISelLowering.cpp (original)
+++ llvm/trunk/lib/Target/PowerPC/PPCISelLowering.cpp Mon Jul 30 02:51:22 2007
@@ -259,6 +259,7 @@
setOperationAction(ISD::UDIV, (MVT::ValueType)VT, Expand);
setOperationAction(ISD::UREM, (MVT::ValueType)VT, Expand);
setOperationAction(ISD::FDIV, (MVT::ValueType)VT, Expand);
+ setOperationAction(ISD::FNEG, (MVT::ValueType)VT, Expand);
setOperationAction(ISD::EXTRACT_VECTOR_ELT, (MVT::ValueType)VT, Expand);
setOperationAction(ISD::INSERT_VECTOR_ELT, (MVT::ValueType)VT, Expand);
setOperationAction(ISD::BUILD_VECTOR, (MVT::ValueType)VT, Expand);
@@ -523,6 +524,16 @@
return true;
}
+/// isAllNegativeZeroVector - Returns true if all elements of build_vector
+/// are -0.0.
+bool PPC::isAllNegativeZeroVector(SDNode *N) {
+ assert(N->getOpcode() == ISD::BUILD_VECTOR);
+ if (PPC::isSplatShuffleMask(N, N->getNumOperands()))
+if (ConstantFPSDNode *CFP = dyn_cast(N))
+ return CFP->isExactlyValue(-0.0);
+ return false;
+}
+
/// getVSPLTImmediate - Return the appropriate VSPLT* immediate to splat the
/// specified isSplatShuffleMask VECTOR_SHUFFLE mask.
unsigned PPC::getVSPLTImmediate(SDNode *N, unsigned EltSize) {
Modified: llvm/trunk/lib/Target/PowerPC/PPCISelLowering.h
URL:
http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PowerPC/PPCISelLowering.h?rev=40586&r1=40585&r2=40586&view=diff
==
--- llvm/trunk/lib/Target/PowerPC/PPCISelLowering.h (original)
+++ llvm/trunk/lib/Target/PowerPC/PPCISelLowering.h Mon Jul 30 02:51:22 2007
@@ -160,6 +160,10 @@
/// VSPLTB/VSPLTH/VSPLTW.
bool isSplatShuffleMask(SDNode *N, unsigned EltSize);
+/// isAllNegativeZeroVector - Returns true if all elements of build_vector
+/// are -0.0.
+bool isAllNegativeZeroVector(SDNode *N);
+
/// getVSPLTImmediate - Return the appropriate VSPLT* immediate to splat
the
/// specified isSplatShuffleMask VECTOR_SHUFFLE mask.
unsigned getVSPLTImmediate(SDNode *N, unsigned EltSize);
Modified: llvm/trunk/lib/Target/PowerPC/PPCInstrAltivec.td
URL:
http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PowerPC/PPCInstrAltivec.td?rev=40586&r1=40585&r2=40586&view=diff
==
--- llvm/trunk/lib/Target/PowerPC/PPCInstrAltivec.td (original)
+++ llvm/trunk/lib/Target/PowerPC/PPCInstrAltivec.td Mon Jul 30 02:51:22 2007
@@ -70,7 +70,6 @@
return PPC::isVMRGHShuffleMask(N, 4, true);
}]>;
-
def VSLDOI_get_imm : SDNodeXForm;
@@ -133,6 +132,10 @@
return PPC::get_VSPLTI_elt(N, 4, *CurDAG).Val != 0;
}], VSPLTISW_get_imm>;
+def V_immneg0 : PatLeaf<(build_vector), [{
+ return PPC::isAllNegativeZeroVector(N);
+}]>;
+
//===--===//
// Helpers for defining instructions that directly correspond to intrinsics.
@@ -228,7 +231,8 @@
Requires<[FPContractions]>;
def VNMSUBFP: VAForm_1<47, (outs VRRC:$vD), (ins VRRC:$vA, VRRC:$vC, VRRC:$vB),
"vnmsubfp $vD, $vA, $vC, $vB", VecFP,
- [(set VRRC:$vD, (fneg (fsub (fmul VRRC:$vA, VRRC:$vC),
+ [(set VRRC:$vD, (fsub V_immneg0,
+ (fsub (fmul VRRC:$vA, VRRC:$vC),
VRRC:$vB)))]>,
Requires<[FPContractions]>;
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[llvm-commits] [llvm] r40587 - /llvm/trunk/test/CodeGen/PowerPC/vec_fneg.ll
Author: evancheng
Date: Mon Jul 30 02:52:03 2007
New Revision: 40587
URL: http://llvm.org/viewvc/llvm-project?rev=40587&view=rev
Log:
New test case.
Added:
llvm/trunk/test/CodeGen/PowerPC/vec_fneg.ll
Added: llvm/trunk/test/CodeGen/PowerPC/vec_fneg.ll
URL:
http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/PowerPC/vec_fneg.ll?rev=40587&view=auto
==
--- llvm/trunk/test/CodeGen/PowerPC/vec_fneg.ll (added)
+++ llvm/trunk/test/CodeGen/PowerPC/vec_fneg.ll Mon Jul 30 02:52:03 2007
@@ -0,0 +1,8 @@
+; RUN: llvm-as < %s | llc -march=ppc32 -mcpu=g5 | grep vsubfp
+
+define void @t(<4 x float>* %A) {
+ %tmp2 = load <4 x float>* %A
+ %tmp3 = sub <4 x float> < float -0.00e+00, float -0.00e+00,
float -0.00e+00, float -0.00e+00 >, %tmp2
+ store <4 x float> %tmp3, <4 x float>* %A
+ ret void
+}
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Re: [llvm-commits] [llvm-gcc-4.0] r40582 - /llvm-gcc-4.0/trunk/gcc/llvm-types.cpp
Hello, Christopher. > URL: http://llvm.org/viewvc/llvm-project?rev=40582&view=rev > Log: > Add support to emit noalias attribute on function parameters when the > __restrict qualifier is used. Please, don't forget, that we have two llvm-gcc versions now. -- With best regards, Anton Korobeynikov. Faculty of Mathematics & Mechanics, Saint Petersburg State University. ___ llvm-commits mailing list llvm-commits@cs.uiuc.edu http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
[llvm-commits] [llvm] r40588 - in /llvm/trunk: include/llvm/PassManager.h include/llvm/PassManagers.h lib/VMCore/PassManager.cpp
Author: djg
Date: Mon Jul 30 09:51:13 2007
New Revision: 40588
URL: http://llvm.org/viewvc/llvm-project?rev=40588&view=rev
Log:
Fix pastos in comments for doFinalization functions.
Modified:
llvm/trunk/include/llvm/PassManager.h
llvm/trunk/include/llvm/PassManagers.h
llvm/trunk/lib/VMCore/PassManager.cpp
Modified: llvm/trunk/include/llvm/PassManager.h
URL:
http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/PassManager.h?rev=40588&r1=40587&r2=40588&view=diff
==
--- llvm/trunk/include/llvm/PassManager.h (original)
+++ llvm/trunk/include/llvm/PassManager.h Mon Jul 30 09:51:13 2007
@@ -79,7 +79,7 @@
///
bool doInitialization();
- /// doFinalization - Run all of the initializers for the function passes.
+ /// doFinalization - Run all of the finalizers for the function passes.
///
bool doFinalization();
private:
Modified: llvm/trunk/include/llvm/PassManagers.h
URL:
http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/PassManagers.h?rev=40588&r1=40587&r2=40588&view=diff
==
--- llvm/trunk/include/llvm/PassManagers.h (original)
+++ llvm/trunk/include/llvm/PassManagers.h Mon Jul 30 09:51:13 2007
@@ -349,7 +349,7 @@
///
bool doInitialization(Module &M);
- /// doFinalization - Run all of the initializers for the function passes.
+ /// doFinalization - Run all of the finalizers for the function passes.
///
bool doFinalization(Module &M);
Modified: llvm/trunk/lib/VMCore/PassManager.cpp
URL:
http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/VMCore/PassManager.cpp?rev=40588&r1=40587&r2=40588&view=diff
==
--- llvm/trunk/lib/VMCore/PassManager.cpp (original)
+++ llvm/trunk/lib/VMCore/PassManager.cpp Mon Jul 30 09:51:13 2007
@@ -140,7 +140,7 @@
///
bool doInitialization(Module &M);
- /// doFinalization - Run all of the initializers for the function passes.
+ /// doFinalization - Run all of the finalizers for the function passes.
///
bool doFinalization(Module &M);
@@ -1078,7 +1078,7 @@
return FPM->doInitialization(*MP->getModule());
}
-/// doFinalization - Run all of the initializers for the function passes.
+/// doFinalization - Run all of the finalizers for the function passes.
///
bool FunctionPassManager::doFinalization() {
return FPM->doFinalization(*MP->getModule());
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[llvm-commits] [llvm] r40589 - in /llvm/trunk: include/llvm/Target/TargetData.h lib/ExecutionEngine/Interpreter/Interpreter.h lib/Target/ARM/ARMFrameInfo.h utils/TableGen/CallingConvEmitter.h
Author: djg
Date: Mon Jul 30 09:51:59 2007
New Revision: 40589
URL: http://llvm.org/viewvc/llvm-project?rev=40589&view=rev
Log:
More explicit keywords.
Modified:
llvm/trunk/include/llvm/Target/TargetData.h
llvm/trunk/lib/ExecutionEngine/Interpreter/Interpreter.h
llvm/trunk/lib/Target/ARM/ARMFrameInfo.h
llvm/trunk/utils/TableGen/CallingConvEmitter.h
Modified: llvm/trunk/include/llvm/Target/TargetData.h
URL:
http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Target/TargetData.h?rev=40589&r1=40588&r2=40589&view=diff
==
--- llvm/trunk/include/llvm/Target/TargetData.h (original)
+++ llvm/trunk/include/llvm/Target/TargetData.h Mon Jul 30 09:51:59 2007
@@ -115,13 +115,13 @@
}
/// Constructs a TargetData from a specification string. See init().
- TargetData(const std::string &TargetDescription)
+ explicit TargetData(const std::string &TargetDescription)
: ImmutablePass((intptr_t)&ID) {
init(TargetDescription);
}
/// Initialize target data from properties stored in the module.
- TargetData(const Module *M);
+ explicit TargetData(const Module *M);
TargetData(const TargetData &TD) :
ImmutablePass((intptr_t)&ID),
Modified: llvm/trunk/lib/ExecutionEngine/Interpreter/Interpreter.h
URL:
http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/ExecutionEngine/Interpreter/Interpreter.h?rev=40589&r1=40588&r2=40589&view=diff
==
--- llvm/trunk/lib/ExecutionEngine/Interpreter/Interpreter.h (original)
+++ llvm/trunk/lib/ExecutionEngine/Interpreter/Interpreter.h Mon Jul 30
09:51:59 2007
@@ -94,7 +94,7 @@
std::vector AtExitHandlers;
public:
- Interpreter(Module *M);
+ explicit Interpreter(Module *M);
~Interpreter();
/// runAtExitHandlers - Run any functions registered by the program's calls
to
Modified: llvm/trunk/lib/Target/ARM/ARMFrameInfo.h
URL:
http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMFrameInfo.h?rev=40589&r1=40588&r2=40589&view=diff
==
--- llvm/trunk/lib/Target/ARM/ARMFrameInfo.h (original)
+++ llvm/trunk/lib/Target/ARM/ARMFrameInfo.h Mon Jul 30 09:51:59 2007
@@ -23,7 +23,7 @@
class ARMFrameInfo : public TargetFrameInfo {
public:
- ARMFrameInfo(const ARMSubtarget &ST)
+ explicit ARMFrameInfo(const ARMSubtarget &ST)
: TargetFrameInfo(StackGrowsDown, ST.getStackAlignment(), 0) {
}
};
Modified: llvm/trunk/utils/TableGen/CallingConvEmitter.h
URL:
http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/TableGen/CallingConvEmitter.h?rev=40589&r1=40588&r2=40589&view=diff
==
--- llvm/trunk/utils/TableGen/CallingConvEmitter.h (original)
+++ llvm/trunk/utils/TableGen/CallingConvEmitter.h Mon Jul 30 09:51:59 2007
@@ -24,7 +24,7 @@
class CallingConvEmitter : public TableGenBackend {
RecordKeeper &Records;
public:
-CallingConvEmitter(RecordKeeper &R) : Records(R) {}
+explicit CallingConvEmitter(RecordKeeper &R) : Records(R) {}
// run - Output the asmwriter, returning true on failure.
void run(std::ostream &o);
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[llvm-commits] [llvm] r40590 - in /llvm/trunk: include/llvm/Target/TargetMachineRegistry.h lib/Target/TargetMachineRegistry.cpp
Author: djg
Date: Mon Jul 30 09:58:59 2007
New Revision: 40590
URL: http://llvm.org/viewvc/llvm-project?rev=40590&view=rev
Log:
Fix the comment for getClosestTargetForJIT to reflect the fact that
it does not have a Module parameter.
Modified:
llvm/trunk/include/llvm/Target/TargetMachineRegistry.h
llvm/trunk/lib/Target/TargetMachineRegistry.cpp
Modified: llvm/trunk/include/llvm/Target/TargetMachineRegistry.h
URL:
http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Target/TargetMachineRegistry.h?rev=40590&r1=40589&r2=40590&view=diff
==
--- llvm/trunk/include/llvm/Target/TargetMachineRegistry.h (original)
+++ llvm/trunk/include/llvm/Target/TargetMachineRegistry.h Mon Jul 30 09:58:59
2007
@@ -36,10 +36,9 @@
static const Entry *getClosestStaticTargetForModule(const Module &M,
std::string &Error);
-/// getClosestTargetForJIT - Given an LLVM module, pick the best target
that
-/// is compatible with the current host and the specified module. If no
-/// close target can be found, this returns null and sets the Error string
-/// to a reason.
+/// getClosestTargetForJIT - Pick the best target that is compatible with
+/// the current host. If no close target can be found, this returns null
+/// and sets the Error string to a reason.
static const Entry *getClosestTargetForJIT(std::string &Error);
Modified: llvm/trunk/lib/Target/TargetMachineRegistry.cpp
URL:
http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/TargetMachineRegistry.cpp?rev=40590&r1=40589&r2=40590&view=diff
==
--- llvm/trunk/lib/Target/TargetMachineRegistry.cpp (original)
+++ llvm/trunk/lib/Target/TargetMachineRegistry.cpp Mon Jul 30 09:58:59 2007
@@ -75,10 +75,9 @@
return UsableTargets.back().second;
}
-/// getClosestTargetForJIT - Given an LLVM module, pick the best target that
-/// is compatible with the current host and the specified module. If no
-/// close target can be found, this returns null and sets the Error string
-/// to a reason.
+/// getClosestTargetForJIT - Pick the best target that is compatible with
+/// the current host. If no close target can be found, this returns null
+/// and sets the Error string to a reason.
const TargetMachineRegistry::Entry *
TargetMachineRegistry::getClosestTargetForJIT(std::string &Error) {
std::vector > UsableTargets;
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[llvm-commits] [llvm] r40591 - /llvm/trunk/tools/opt/opt.cpp
Author: djg Date: Mon Jul 30 10:01:09 2007 New Revision: 40591 URL: http://llvm.org/viewvc/llvm-project?rev=40591&view=rev Log: Remove a FIXME comment that wasn't removed when the code it accompanied was removed. Modified: llvm/trunk/tools/opt/opt.cpp Modified: llvm/trunk/tools/opt/opt.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/tools/opt/opt.cpp?rev=40591&r1=40590&r2=40591&view=diff == --- llvm/trunk/tools/opt/opt.cpp (original) +++ llvm/trunk/tools/opt/opt.cpp Mon Jul 30 10:01:09 2007 @@ -267,7 +267,6 @@ addPass(PM, createTailDuplicationPass()); // Simplify cfg by copying code addPass(PM, createInstructionCombiningPass()); // Cleanup for scalarrepl. addPass(PM, createCFGSimplificationPass());// Merge & remove BBs - // FIXME: Temporary! addPass(PM, createScalarReplAggregatesPass()); // Break up aggregate allocas addPass(PM, createInstructionCombiningPass()); // Combine silly seq's addPass(PM, createCondPropagationPass()); // Propagate conditionals ___ llvm-commits mailing list llvm-commits@cs.uiuc.edu http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
[llvm-commits] [llvm] r40592 - /llvm/trunk/include/llvm/Target/TargetMachine.h
Author: djg Date: Mon Jul 30 10:04:59 2007 New Revision: 40592 URL: http://llvm.org/viewvc/llvm-project?rev=40592&view=rev Log: Fix the comments for the 'fast' parameter in addPassesToEmitFile. Modified: llvm/trunk/include/llvm/Target/TargetMachine.h Modified: llvm/trunk/include/llvm/Target/TargetMachine.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Target/TargetMachine.h?rev=40592&r1=40591&r2=40592&view=diff == --- llvm/trunk/include/llvm/Target/TargetMachine.h (original) +++ llvm/trunk/include/llvm/Target/TargetMachine.h Mon Jul 30 10:04:59 2007 @@ -192,8 +192,9 @@ /// addPassesToEmitFile - Add passes to the specified pass manager to get the /// specified file emitted. Typically this will involve several steps of code /// generation. If Fast is set to true, the code generator should emit code - /// as fast as possible, without regard for compile time. This method should - /// return FileModel::Error if emission of this file type is not supported. + /// as fast as possible, though the generated code may be less efficient. + /// This method should return FileModel::Error if emission of this file type + /// is not supported. /// virtual FileModel::Model addPassesToEmitFile(FunctionPassManager &PM, std::ostream &Out, @@ -243,8 +244,9 @@ /// addPassesToEmitFile - Add passes to the specified pass manager to get the /// specified file emitted. Typically this will involve several steps of code /// generation. If Fast is set to true, the code generator should emit code - /// as fast as possible, without regard for compile time. This method should - /// return FileModel::Error if emission of this file type is not supported. + /// as fast as possible, though the generated code may be less efficient. + /// This method should return FileModel::Error if emission of this file type + /// is not supported. /// /// The default implementation of this method adds components from the /// LLVM retargetable code generator, invoking the methods below to get ___ llvm-commits mailing list llvm-commits@cs.uiuc.edu http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
[llvm-commits] [llvm] r40593 - /llvm/trunk/lib/CodeGen/AsmPrinter.cpp
Author: djg Date: Mon Jul 30 10:06:25 2007 New Revision: 40593 URL: http://llvm.org/viewvc/llvm-project?rev=40593&view=rev Log: Print a space between the comment character and the basic block name, for prettiness. Modified: llvm/trunk/lib/CodeGen/AsmPrinter.cpp Modified: llvm/trunk/lib/CodeGen/AsmPrinter.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/AsmPrinter.cpp?rev=40593&r1=40592&r2=40593&view=diff == --- llvm/trunk/lib/CodeGen/AsmPrinter.cpp (original) +++ llvm/trunk/lib/CodeGen/AsmPrinter.cpp Mon Jul 30 10:06:25 2007 @@ -1144,7 +1144,8 @@ if (printColon) O << ':'; if (printComment && MBB->getBasicBlock()) -O << '\t' << TAI->getCommentString() << MBB->getBasicBlock()->getName(); +O << '\t' << TAI->getCommentString() << ' ' + << MBB->getBasicBlock()->getName(); } /// printSetLabel - This method prints a set label for the specified ___ llvm-commits mailing list llvm-commits@cs.uiuc.edu http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
[llvm-commits] [llvm] r40594 - in /llvm/trunk/lib/Target/X86: X86ATTAsmPrinter.cpp X86AsmPrinter.cpp
Author: djg
Date: Mon Jul 30 10:08:02 2007
New Revision: 40594
URL: http://llvm.org/viewvc/llvm-project?rev=40594&view=rev
Log:
Use tabs more consistently in assembler pseudo-ops.
Modified:
llvm/trunk/lib/Target/X86/X86ATTAsmPrinter.cpp
llvm/trunk/lib/Target/X86/X86AsmPrinter.cpp
Modified: llvm/trunk/lib/Target/X86/X86ATTAsmPrinter.cpp
URL:
http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86ATTAsmPrinter.cpp?rev=40594&r1=40593&r2=40594&view=diff
==
--- llvm/trunk/lib/Target/X86/X86ATTAsmPrinter.cpp (original)
+++ llvm/trunk/lib/Target/X86/X86ATTAsmPrinter.cpp Mon Jul 30 10:08:02 2007
@@ -129,7 +129,7 @@
O << "\t.linkonce discard\n";
} else {
EmitAlignment(4, F); // FIXME: This should be parameterized
somewhere.
- O << "\t.weak " << CurrentFnName << "\n";
+ O << "\t.weak\t" << CurrentFnName << "\n";
}
break;
}
@@ -142,7 +142,7 @@
}
if (Subtarget->isTargetELF())
-O << "\t.type " << CurrentFnName << ",@function\n";
+O << "\t.type\t" << CurrentFnName << ",@function\n";
else if (Subtarget->isTargetCygMing()) {
O << "\t.def\t " << CurrentFnName
<< ";\t.scl\t" <<
Modified: llvm/trunk/lib/Target/X86/X86AsmPrinter.cpp
URL:
http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86AsmPrinter.cpp?rev=40594&r1=40593&r2=40594&view=diff
==
--- llvm/trunk/lib/Target/X86/X86AsmPrinter.cpp (original)
+++ llvm/trunk/lib/Target/X86/X86AsmPrinter.cpp Mon Jul 30 10:08:02 2007
@@ -168,7 +168,7 @@
}
if (Subtarget->isTargetELF())
- O << "\t.type " << name << ",@object\n";
+ O << "\t.type\t" << name << ",@object\n";
if (C->isNullValue()) {
if (I->hasExternalLinkage()) {
@@ -228,7 +228,7 @@
name +
",\"aw\",@progbits");
SwitchToDataSection(SectionName.c_str(), I);
-O << "\t.weak " << name << "\n";
+O << "\t.weak\t" << name << "\n";
}
break;
case GlobalValue::AppendingLinkage:
@@ -305,7 +305,7 @@
O << name << ":\t\t\t\t" << TAI->getCommentString() << " " << I->getName()
<< "\n";
if (TAI->hasDotTypeDotSizeDirective())
- O << "\t.size " << name << ", " << Size << "\n";
+ O << "\t.size\t" << name << ", " << Size << "\n";
// If the initializer is a extern weak symbol, remember to emit the weak
// reference!
if (const GlobalValue *GV = dyn_cast(C))
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[llvm-commits] [llvm] r40595 - in /llvm/trunk: lib/Transforms/Scalar/GVN.cpp test/Transforms/GVN/2007-07-30-PredIDom.ll
Author: resistor
Date: Mon Jul 30 11:57:08 2007
New Revision: 40595
URL: http://llvm.org/viewvc/llvm-project?rev=40595&view=rev
Log:
Fix a bug caused by indiscriminantly asking for the dominators of a predecessor.
Added:
llvm/trunk/test/Transforms/GVN/2007-07-30-PredIDom.ll
Modified:
llvm/trunk/lib/Transforms/Scalar/GVN.cpp
Modified: llvm/trunk/lib/Transforms/Scalar/GVN.cpp
URL:
http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/Scalar/GVN.cpp?rev=40595&r1=40594&r2=40595&view=diff
==
--- llvm/trunk/lib/Transforms/Scalar/GVN.cpp (original)
+++ llvm/trunk/lib/Transforms/Scalar/GVN.cpp Mon Jul 30 11:57:08 2007
@@ -723,7 +723,8 @@
return V = GetValueForBlock(IDom->getBlock(), orig, Phis);
}
-
+ if (std::distance(pred_begin(BB), pred_end(BB)) == 1)
+return V = GetValueForBlock(IDom->getBlock(), orig, Phis);
// Otherwise, the idom is the loop, so we need to insert a PHI node. Do so
// now, then get values to fill in the incoming values for the PHI.
@@ -731,10 +732,10 @@
BB->begin());
PN->reserveOperandSpace(std::distance(pred_begin(BB), pred_end(BB)));
V = PN;
-
+
// Fill in the incoming values for the block.
for (pred_iterator PI = pred_begin(BB), E = pred_end(BB); PI != E; ++PI)
-PN->addIncoming(GetValueForBlock(DT.getNode(*PI)->getBlock(), orig, Phis),
*PI);
+PN->addIncoming(GetValueForBlock(*PI, orig, Phis), *PI);
return PN;
}
Added: llvm/trunk/test/Transforms/GVN/2007-07-30-PredIDom.ll
URL:
http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Transforms/GVN/2007-07-30-PredIDom.ll?rev=40595&view=auto
==
--- llvm/trunk/test/Transforms/GVN/2007-07-30-PredIDom.ll (added)
+++ llvm/trunk/test/Transforms/GVN/2007-07-30-PredIDom.ll Mon Jul 30 11:57:08
2007
@@ -0,0 +1,274 @@
+; RUN: llvm-as < %s | opt -gvn | llvm-dis
+
+ %"struct.Block::$_16" = type { i32 }
+ %struct.Exp = type { %struct.Exp_*, i32, i32, i32, %struct.Exp*,
%struct.Exp*, %"struct.Exp::$_10", %"struct.Block::$_16", %"struct.Exp::$_12" }
+ %"struct.Exp::$_10" = type { %struct.Exp* }
+ %"struct.Exp::$_12" = type { %struct.Exp** }
+ %struct.Exp_ = type { i32, i32, i32, i32, %struct.Id* }
+ %struct.Id = type { i8*, i32, i32, i32, %"struct.Id::$_13" }
+ %"struct.Id::$_13" = type { double }
+
+define i8* @_ZN3Exp8toStringEj(%struct.Exp* %this, i32 %nextpc) {
+entry:
+ switch i32 0, label %bb970 [
+i32 1, label %bb
+i32 2, label %bb39
+i32 3, label %bb195
+i32 4, label %bb270
+i32 5, label %bb418
+i32 6, label %bb633
+i32 7, label %bb810
+i32 8, label %bb882
+i32 9, label %bb925
+ ]
+
+bb:; preds = %entry
+ store i8* null, i8** null
+ br label %return
+
+bb39: ; preds = %entry
+ br i1 false, label %cond_true, label %cond_false132
+
+cond_true: ; preds = %bb39
+ br i1 false, label %cond_true73, label %cond_false
+
+cond_true73: ; preds = %cond_true
+ br i1 false, label %cond_true108, label %cond_next
+
+cond_true108: ; preds = %cond_true73
+ br label %cond_next
+
+cond_next: ; preds = %cond_true108, %cond_true73
+ br label %cond_next131
+
+cond_false:; preds = %cond_true
+ br label %cond_next131
+
+cond_next131: ; preds = %cond_false, %cond_next
+ br label %cond_next141
+
+cond_false132: ; preds = %bb39
+ br label %cond_next141
+
+cond_next141: ; preds = %cond_false132, %cond_next131
+ br i1 false, label %cond_true169, label %cond_false175
+
+cond_true169: ; preds = %cond_next141
+ br label %cond_next181
+
+cond_false175: ; preds = %cond_next141
+ br label %cond_next181
+
+cond_next181: ; preds = %cond_false175, %cond_true169
+ br i1 false, label %cond_true189, label %cond_next191
+
+cond_true189: ; preds = %cond_next181
+ br label %cond_next191
+
+cond_next191: ; preds = %cond_true189, %cond_next181
+ store i8* null, i8** null
+ br label %return
+
+bb195: ; preds = %entry
+ br i1 false, label %cond_true248, label %cond_false250
+
+cond_true248: ; preds = %bb195
+ br label %cond_next252
+
+cond_false250: ; preds = %bb195
+ br label %cond_next252
+
+cond_next252: ; preds = %cond_false250, %cond_true248
+ br i1 false, label %cond_true265, label %cond_next267
+
+cond_true265: ; preds = %cond_next252
+ br label %cond_next267
+
+cond_next267: ; preds = %cond_true265, %cond_next252
+ store i8* null, i8** null
+ br label %return
+
+bb270:
[llvm-commits] [llvm] r40596 - in /llvm/trunk/lib: Analysis/MemoryDependenceAnalysis.cpp Transforms/Scalar/GVN.cpp
Author: resistor
Date: Mon Jul 30 12:29:24 2007
New Revision: 40596
URL: http://llvm.org/viewvc/llvm-project?rev=40596&view=rev
Log:
Use more caching when computing non-local dependence. This makes bzip2 not
use up the entire 32-bit address space.
Modified:
llvm/trunk/lib/Analysis/MemoryDependenceAnalysis.cpp
llvm/trunk/lib/Transforms/Scalar/GVN.cpp
Modified: llvm/trunk/lib/Analysis/MemoryDependenceAnalysis.cpp
URL:
http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Analysis/MemoryDependenceAnalysis.cpp?rev=40596&r1=40595&r2=40596&view=diff
==
--- llvm/trunk/lib/Analysis/MemoryDependenceAnalysis.cpp (original)
+++ llvm/trunk/lib/Analysis/MemoryDependenceAnalysis.cpp Mon Jul 30 12:29:24
2007
@@ -129,6 +129,8 @@
if (!inserted && !predOnStack)
resp.insert(std::make_pair(block, None));
+ else if (inserted && predOnStack)
+resp.insert(std::make_pair(block, NonLocal));
return inserted;
}
Modified: llvm/trunk/lib/Transforms/Scalar/GVN.cpp
URL:
http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/Scalar/GVN.cpp?rev=40596&r1=40595&r2=40596&view=diff
==
--- llvm/trunk/lib/Transforms/Scalar/GVN.cpp (original)
+++ llvm/trunk/lib/Transforms/Scalar/GVN.cpp Mon Jul 30 12:29:24 2007
@@ -752,7 +752,9 @@
I != E; ++I)
if (I->second == MemoryDependenceAnalysis::None) {
return false;
-} else if (StoreInst* S = dyn_cast(I->second)) {
+} else if (I->second == MemoryDependenceAnalysis::NonLocal) {
+ continue;
+}else if (StoreInst* S = dyn_cast(I->second)) {
if (S->getPointerOperand() == L->getPointerOperand())
repl.insert(std::make_pair(I->first, S->getOperand(0)));
else
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Re: [llvm-commits] [llvm] r40069 - in /llvm/trunk: docs/ lib/AsmParser/ lib/VMCore/ test/ test/Assembler/ test/CFrontend/ test/CodeGen/ARM/ test/CodeGen/Alpha/ test/CodeGen/PowerPC/ test/CodeGen/X86/
On Jul 19, 2007, at 8:53 PM, Reid Spencer wrote: > On Thu, 2007-07-19 at 20:32 -0700, Chris Lattner wrote: >> On Jul 19, 2007, at 4:13 PM, Reid Spencer wrote: >> >>> Author: reid >>> Date: Thu Jul 19 18:13:04 2007 >>> New Revision: 40069 >>> >>> URL: http://llvm.org/viewvc/llvm-project?rev=40069&view=rev >>> Log: >>> For PR1553: >>> Change the keywords for the zext and sext parameter attributes to be >>> zeroext and signext so they don't conflict with the keywords for the >>> instructions of the same name. This gets around the ambiguity. >> >> Thanks Reid! >> >> Shouldn't the .ll parser autoupgrade llvm 2.0 .ll files? > > There isn't a good way to do it and still fix PR1553. That is, I'd > have > to reinstate the zext and sext keywords as parameter attributes so > that > the ambiguity between a function level zext/sext and a sext/zext > instruction would remain. It isn't acceptable to break backwards compatibility with old files. Can we just do a hack where we handle the common case by looking at the line that the token comes from? For example: call foo() zext would be treated different than: call foo() zext because the zext is not on the same line. This seems to be a good solution, thoughts? -Chris ___ llvm-commits mailing list llvm-commits@cs.uiuc.edu http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
Re: [llvm-commits] Patch for X86 to use subregs
On Jul 30, 2007, at 12:02 AM, Christopher Lamb wrote: On Jul 29, 2007, at 10:20 PM, Evan Cheng wrote: On Jul 29, 2007, at 9:37 PM, Christopher Lamb wrote: On Jul 29, 2007, at 6:20 PM, Evan Cheng wrote: Sent from my iPhone On Jul 28, 2007, at 4:36 PM, Christopher Lamb <[EMAIL PROTECTED]> wrote: On Jul 28, 2007, at 2:26 PM, Evan Cheng wrote: On Jul 28, 2007, at 11:52 AM, Christopher Lamb <[EMAIL PROTECTED]> wrote: On Jul 28, 2007, at 1:48 AM, Evan Cheng wrote: Very cool! I need to read it more carefully. But I see you are lowering zext to a single insert_subreg. Is that right? It won't zero out the top part, no? It's only lowering (zext i32 to i64) to an insert_subreg on x86-64 where all writes to 32-bit registers implicitly zero- extend into the upper 32-bits. I know. But thy mismatch semantically. A insert_subreg to the lower part should not change the upper half. I think this is only legal for anyext. On x86-64 the semantics of a 2 operand i32 insert_subreg is that the input super-value is implicitly zero. So in this sense the insert isn't changing the upper half, it's just that the upper half is being set to zero implicitly rather than explicitly. If you'll notice the insert_subreg is a two operand (implicit super value) not a three operand version. If the insert were the three operand version, and the super value as coming from an implicit def I'd agree with you, but it's not. Ok, let's step back for a second. There are a couple of issues that should be addressed. Plz help me understand. :) 1: Semantics of insert_subreg should be the same across all targets, right? I'm not certain that this should be so. x86-64 clearly has a target specific semantics of a 32-bit into 64-bit insert. No, that won't do. insert_subreg and extract_subreg are by definition target independent. They must have the same semantics. You are forcing x86-64 32-bit zero-extending move to fit insert_subreg when they are really not the same thing. If target independence is a requirement, then I agree that using insert_subreg for x86-64 zero-ext isn't currently feasible. Right. 2: two operant variant of insert_subreg should mean the superreg is undef. If you insert a value into a low part, the rest of the superreg is still undef. I think the meaning of insert_subreg instruction (both 2 and 3 operand versions) must have semantics specific to the target. For example, on x86-64 there is no valid 3 operand insert_subreg for a 32-bit value into 64-bits, because the 32-bit result is always going to be zero extended and overwrite the upper 32-bits. It just means there is no way to implement a insert_subreg with a single instruction under x86-64. But that is perfectly ok. Apart from anyext, x86-64 just isn't going to benefit from it. It's also impossible to read or modify the higher 32-bits. Currently the move that's generated isn't handled by coalescing because the source and destination belong to different register classes. The insert_subreg is meant to be a means to move values implicitly between register classes that have a subreg relationship. So if insert_subreg semantics must be target independent, then I think you isel the zero-extending move to be: (i64 (INSERT_SUBREG (i64 0), GR32:$src, 3)) But that's wrong. Remember the superreg argument is an read / mod / write operand. That is, the first operand is a use, the def is the LHS but we are forcing the allocator to target the same physical register. v1 = some existing value v1 = insert_subreg v1, GR32:$src, 3 But zext is zeroing out the top part. i.e. zext is equal to mov v1, 0 v1 = insert_subreg v1, GR32:$src, 3 The thing is that the general coalescing will be able to determine that the copy from undef is unneeded for (INSERT_SUBREG (i64 undef), GR32:$src, 3), but it would take a target specific hook to know that the constant zero is unneeded on x86-64. A target specific hook for this might be useful, but I think that this is in the realm of future work now. Sorry, I am not following. zext on x86-64, i.e. the 32-bit move, cannot be coalesced away. No need for target specific hook. 3: why is there a two operant variant in the first place? Why not use undef for the superreg operant? To note, the two operand variant is of the MachineInstr. The DAG form would be to represent the superregister as coming from an undef node, but this gets isel'd to the two operand MachineInstr of insert_subreg. The reason is that undef is typically selected to an implicit def of a register. This causes an unnecessary move to be generated later on. This move can be optimized away later with more difficulty during subreg lowering by checking whether the input register is defined by an implicit def pseudo instruction, but instead I decided to perform the optimization during ISel on the DAG form during instruction selection. With wha
Re: [llvm-commits] [llvm-gcc-4.2] r40571 - in /llvm-gcc-4.2/trunk/gcc: llvm-backend.cpp toplev.c
On Jul 28, 2007, at 11:28 AM, Anton Korobeynikov wrote: > -- llvm-gcc-4.2/trunk/gcc/llvm-backend.cpp (original) > +++ llvm-gcc-4.2/trunk/gcc/llvm-backend.cpp Sat Jul 28 13:28:30 2007 > @@ -234,7 +234,11 @@ > delete PerModulePasses; > delete CodeGenPasses; > > -createOptimizationPasses(); > +// Don't run codegen, when we should output PCH > +if (!flag_pch_file) > + createOptimizationPasses(); > +else > + llvm_pch_write_init(); > } Does this handle inline method definition in C++ and function bodies in C header well ? - Devang ___ llvm-commits mailing list llvm-commits@cs.uiuc.edu http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
[llvm-commits] [llvm] r40598 - in /llvm/trunk: lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp test/CodeGen/Alpha/illegal-element-type.ll test/CodeGen/PowerPC/illegal-element-type.ll
Author: djg
Date: Mon Jul 30 14:09:17 2007
New Revision: 40598
URL: http://llvm.org/viewvc/llvm-project?rev=40598&view=rev
Log:
Fix a bug in getCopyFromParts turned up in the testcase for PR1132.
Added:
llvm/trunk/test/CodeGen/Alpha/illegal-element-type.ll
llvm/trunk/test/CodeGen/PowerPC/illegal-element-type.ll
Modified:
llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
Modified: llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
URL:
http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp?rev=40598&r1=40597&r2=40598&view=diff
==
--- llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp (original)
+++ llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp Mon Jul 30
14:09:17 2007
@@ -695,9 +695,9 @@
} else if (NumParts > 0) {
// If the intermediate type was expanded, build the intermediate operands
// from the parts.
-assert(NumIntermediates % NumParts == 0 &&
+assert(NumParts % NumIntermediates == 0 &&
"Must expand into a divisible number of parts!");
-unsigned Factor = NumIntermediates / NumParts;
+unsigned Factor = NumParts / NumIntermediates;
for (unsigned i = 0; i != NumIntermediates; ++i)
Ops[i] = getCopyFromParts(DAG, &Parts[i * Factor], Factor,
PartVT, IntermediateVT);
@@ -708,7 +708,7 @@
return DAG.getNode(MVT::isVector(IntermediateVT) ?
ISD::CONCAT_VECTORS :
ISD::BUILD_VECTOR,
- ValueVT, &Ops[0], NumParts);
+ ValueVT, &Ops[0], NumIntermediates);
}
/// getCopyToParts - Create a series of nodes that contain the
Added: llvm/trunk/test/CodeGen/Alpha/illegal-element-type.ll
URL:
http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Alpha/illegal-element-type.ll?rev=40598&view=auto
==
--- llvm/trunk/test/CodeGen/Alpha/illegal-element-type.ll (added)
+++ llvm/trunk/test/CodeGen/Alpha/illegal-element-type.ll Mon Jul 30 14:09:17
2007
@@ -0,0 +1,23 @@
+; RUN: llvm-as < %s | llc -mtriple=alphaev6-unknown-linux-gnu
+
+define void @foo() {
+entry:
+br label %bb
+
+bb: ; preds = %bb, %entry
+br i1 false, label %bb26, label %bb
+
+bb19: ; preds = %bb26
+ret void
+
+bb26: ; preds = %bb
+br i1 false, label %bb30, label %bb19
+
+bb30: ; preds = %bb26
+br label %bb45
+
+bb45: ; preds = %bb45, %bb30
+%V.0 = phi <8 x i16> [ %tmp42, %bb45 ], [ zeroinitializer, %bb30 ]
; <<8 x i16>> [#uses=1]
+%tmp42 = mul <8 x i16> zeroinitializer, %V.0; <<8 x i16>>
[#uses=1]
+br label %bb45
+}
Added: llvm/trunk/test/CodeGen/PowerPC/illegal-element-type.ll
URL:
http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/PowerPC/illegal-element-type.ll?rev=40598&view=auto
==
--- llvm/trunk/test/CodeGen/PowerPC/illegal-element-type.ll (added)
+++ llvm/trunk/test/CodeGen/PowerPC/illegal-element-type.ll Mon Jul 30 14:09:17
2007
@@ -0,0 +1,23 @@
+; RUN: llvm-as < %s | llc -march=ppc32 -mcpu=g3
+
+define void @foo() {
+entry:
+br label %bb
+
+bb: ; preds = %bb, %entry
+br i1 false, label %bb26, label %bb
+
+bb19: ; preds = %bb26
+ret void
+
+bb26: ; preds = %bb
+br i1 false, label %bb30, label %bb19
+
+bb30: ; preds = %bb26
+br label %bb45
+
+bb45: ; preds = %bb45, %bb30
+%V.0 = phi <8 x i16> [ %tmp42, %bb45 ], [ zeroinitializer, %bb30 ]
; <<8 x i16>> [#uses=1]
+%tmp42 = mul <8 x i16> zeroinitializer, %V.0; <<8 x i16>>
[#uses=1]
+br label %bb45
+}
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Re: [llvm-commits] Patch: JIT support for ARM
Very nice!
+def NoneFormat : Format<0>; def Pseudo: Format<1>;
+def Multiply: Format<2>; def Branch: Format<3>;
Some naming suggestions. NoneFormat -> Pseudo, Multiply ->
MultiplyFrm (or MulFrm).
+class AIlist pattern>
+ : Iasm,"",pattern>;
Please watch out for "80 col violations" (tm)! :-)
+static const unsigned InstBits[] = {
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0XE2B0,
+ 0XE0B0,
+ 0XE0B0,
+ 0XE290,
This is impossible to maintain. Please move opcode bits into .td
files. That is, please add it to each instruction definition:
// FIXME: Set all opcodes to 0 for now.
: InstARM<0, am, sz, im, cstr> {
Thanks,
Evan
On Jul 30, 2007, at 10:51 AM, Raul Fernandes Herbster wrote:
JIT support for ARM is now generating machine code (Thumb and VFP
are not supported). Relocation has not been implemented yet. Next
patch must provide such feature. Please, send me any feedback.
Thanks in advance, Raul.
--
Raul Fernandes Herbster
Embedded and Pervasive Computing Laboratory - embedded.dee.ufcg.edu.br
Electrical Engineering Department - DEE - www.dee.ufcg.edu.br
Electrical Engineering and Informatics Center - CEEI
Federal University of Campina Grande - UFCG - www.ufcg.edu.br
Caixa Postal 10105
58109-970 Campina Grande - PB - Brasil
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Re: [llvm-commits] Patch for X86 to use subregs
On Jul 30, 2007, at 11:06 AM, Evan Cheng wrote: On Jul 30, 2007, at 12:02 AM, Christopher Lamb wrote: On Jul 29, 2007, at 10:20 PM, Evan Cheng wrote: On Jul 29, 2007, at 9:37 PM, Christopher Lamb wrote: On Jul 29, 2007, at 6:20 PM, Evan Cheng wrote: Sent from my iPhone On Jul 28, 2007, at 4:36 PM, Christopher Lamb <[EMAIL PROTECTED]> wrote: On Jul 28, 2007, at 2:26 PM, Evan Cheng wrote: On Jul 28, 2007, at 11:52 AM, Christopher Lamb <[EMAIL PROTECTED]> wrote: On Jul 28, 2007, at 1:48 AM, Evan Cheng wrote: Very cool! I need to read it more carefully. But I see you are lowering zext to a single insert_subreg. Is that right? It won't zero out the top part, no? It's only lowering (zext i32 to i64) to an insert_subreg on x86-64 where all writes to 32-bit registers implicitly zero- extend into the upper 32-bits. I know. But thy mismatch semantically. A insert_subreg to the lower part should not change the upper half. I think this is only legal for anyext. On x86-64 the semantics of a 2 operand i32 insert_subreg is that the input super-value is implicitly zero. So in this sense the insert isn't changing the upper half, it's just that the upper half is being set to zero implicitly rather than explicitly. If you'll notice the insert_subreg is a two operand (implicit super value) not a three operand version. If the insert were the three operand version, and the super value as coming from an implicit def I'd agree with you, but it's not. Ok, let's step back for a second. There are a couple of issues that should be addressed. Plz help me understand. :) 1: Semantics of insert_subreg should be the same across all targets, right? I'm not certain that this should be so. x86-64 clearly has a target specific semantics of a 32-bit into 64-bit insert. No, that won't do. insert_subreg and extract_subreg are by definition target independent. They must have the same semantics. You are forcing x86-64 32-bit zero-extending move to fit insert_subreg when they are really not the same thing. If target independence is a requirement, then I agree that using insert_subreg for x86-64 zero-ext isn't currently feasible. I contend that insert_subreg is target specific already. It currently requires a target specific subreg index, which is a kind of target specific hook, that tells coalescing how to deal with it. A two operand insert_subreg (or an insert_subreg from undef) is a move between target register classes that have subreg relationship. insert_subreg defines the entire superreg value, and I don't see why it's so bad to allow targets to specify their own semantics for what happens to the register being inserted into? This is essentially what the subreg index is already, we could even put semantics in the SubRegSet in the RegisterInfo.td allowing the semantics to be checked by the compiler. A parameter of the set that indicates that an insert into the subreg i either leaves the rest of the superreg value untouched (insert_subreg reg, reg, i), or it implicitly sets the rest of the register to a known value (insert_subreg constant_value, reg, i), or to undef (insert_subreg undef, reg, i). Only the specified semantics for that SubRegSet of the register class of the result of the insert_subreg would be valid, and could be ensured so. This seems to me to allow insert_subreg to capture may useful cases, and it captures the register set semantics in the RegisterInfo.td file, where I think it belongs. 2: two operant variant of insert_subreg should mean the superreg is undef. If you insert a value into a low part, the rest of the superreg is still undef. I think the meaning of insert_subreg instruction (both 2 and 3 operand versions) must have semantics specific to the target. For example, on x86-64 there is no valid 3 operand insert_subreg for a 32-bit value into 64-bits, because the 32-bit result is always going to be zero extended and overwrite the upper 32-bits. It just means there is no way to implement a insert_subreg with a single instruction under x86-64. But that is perfectly ok. Apart from anyext, x86-64 just isn't going to benefit from it. It's also impossible to read or modify the higher 32-bits. Currently the move that's generated isn't handled by coalescing because the source and destination belong to different register classes. The insert_subreg is meant to be a means to move values implicitly between register classes that have a subreg relationship. So if insert_subreg semantics must be target independent, then I think you isel the zero-extending move to be: (i64 (INSERT_SUBREG (i64 0), GR32:$src, 3)) But that's wrong. Remember the superreg argument is an read / mod / write operand. That is, the first operand is a use, the def is the LHS but we are forcing the allocator to target the same physical register. v1 = some existing value v1 = insert_subreg
[llvm-commits] [llvm] r40599 - /llvm/trunk/lib/Transforms/Scalar/InstructionCombining.cpp
Author: reid
Date: Mon Jul 30 14:53:57 2007
New Revision: 40599
URL: http://llvm.org/viewvc/llvm-project?rev=40599&view=rev
Log:
Fix a typo/thinko.
Modified:
llvm/trunk/lib/Transforms/Scalar/InstructionCombining.cpp
Modified: llvm/trunk/lib/Transforms/Scalar/InstructionCombining.cpp
URL:
http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/Scalar/InstructionCombining.cpp?rev=40599&r1=40598&r2=40599&view=diff
==
--- llvm/trunk/lib/Transforms/Scalar/InstructionCombining.cpp (original)
+++ llvm/trunk/lib/Transforms/Scalar/InstructionCombining.cpp Mon Jul 30
14:53:57 2007
@@ -7974,7 +7974,7 @@
if (InvokeInst *II = dyn_cast(Caller)) {
NC = new InvokeInst(Callee, II->getNormalDest(), II->getUnwindDest(),
&Args[0], Args.size(), Caller->getName(), Caller);
-cast(II)->setCallingConv(II->getCallingConv());
+cast(NC)->setCallingConv(II->getCallingConv());
} else {
NC = new CallInst(Callee, &Args[0], Args.size(), Caller->getName(),
Caller);
if (cast(Caller)->isTailCall())
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[llvm-commits] [llvm] r40600 - in /llvm/trunk: autoconf/configure.ac include/llvm/Config/config.h.in lib/ExecutionEngine/JIT/JIT.cpp
Author: asl
Date: Mon Jul 30 15:02:02 2007
New Revision: 40600
URL: http://llvm.org/viewvc/llvm-project?rev=40600&view=rev
Log:
Add detection of __dso_handle presence during configure. Use this information
in the
JITer (short path is added for darwin). This is needed to properly JIT
llvm-gcc-4.2-built
binaries, since cxa_atexit is enabled by default on much more targets.
Modified:
llvm/trunk/autoconf/configure.ac
llvm/trunk/include/llvm/Config/config.h.in
llvm/trunk/lib/ExecutionEngine/JIT/JIT.cpp
Modified: llvm/trunk/autoconf/configure.ac
URL:
http://llvm.org/viewvc/llvm-project/llvm/trunk/autoconf/configure.ac?rev=40600&r1=40599&r2=40600&view=diff
==
--- llvm/trunk/autoconf/configure.ac (original)
+++ llvm/trunk/autoconf/configure.ac Mon Jul 30 15:02:02 2007
@@ -766,6 +766,9 @@
dnl===
dnl===---===
+dnl Check, whether __dso_handle is present
+AC_CHECK_FUNCS([__dso_handle])
+
dnl See if the llvm-gcc executable can compile to LLVM assembly
AC_CACHE_CHECK([whether llvm-gcc is sane],[llvm_cv_llvmgcc_sanity],
[llvm_cv_llvmgcc_sanity="no"
Modified: llvm/trunk/include/llvm/Config/config.h.in
URL:
http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Config/config.h.in?rev=40600&r1=40599&r2=40600&view=diff
==
--- llvm/trunk/include/llvm/Config/config.h.in (original)
+++ llvm/trunk/include/llvm/Config/config.h.in Mon Jul 30 15:02:02 2007
@@ -437,6 +437,9 @@
/* Define to 1 if you have the header file. */
#undef HAVE_WINDOWS_H
+/* Define to 1 if you have the `__dso_handle' function. */
+#undef HAVE___DSO_HANDLE
+
/* Installation directory for binary executables */
#undef LLVM_BINDIR
Modified: llvm/trunk/lib/ExecutionEngine/JIT/JIT.cpp
URL:
http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/ExecutionEngine/JIT/JIT.cpp?rev=40600&r1=40599&r2=40600&view=diff
==
--- llvm/trunk/lib/ExecutionEngine/JIT/JIT.cpp (original)
+++ llvm/trunk/lib/ExecutionEngine/JIT/JIT.cpp Mon Jul 30 15:02:02 2007
@@ -27,17 +27,29 @@
#include "llvm/Target/TargetData.h"
#include "llvm/Target/TargetMachine.h"
#include "llvm/Target/TargetJITInfo.h"
+
+#include "llvm/Config/config.h"
+
using namespace llvm;
#ifdef __APPLE__
-#include
-#if defined(MAC_OS_X_VERSION_10_4) && \
-((MAC_OS_X_VERSION_MIN_REQUIRED > MAC_OS_X_VERSION_10_4) || \
- (MAC_OS_X_VERSION_MIN_REQUIRED == MAC_OS_X_VERSION_10_4 && \
- __APPLE_CC__ >= 5330))
-// __dso_handle is resolved by Mac OS X dynamic linker.
-extern void *__dso_handle __attribute__ ((__visibility__ ("hidden")));
+// Apple gcc defaults to -fuse-cxa-atexit (i.e. calls __cxa_atexit instead
+// of atexit). It passes the address of linker generated symbol __dso_handle
+// to the function.
+// This configuration change happened at version 5330.
+# include
+# if defined(MAC_OS_X_VERSION_10_4) && \
+ ((MAC_OS_X_VERSION_MIN_REQUIRED > MAC_OS_X_VERSION_10_4) || \
+ (MAC_OS_X_VERSION_MIN_REQUIRED == MAC_OS_X_VERSION_10_4 && \
+ __APPLE_CC__ >= 5330))
+# ifndef HAVE___DSO_HANDLE
+# define HAVE___DSO_HANDLE 1
+# endif
+# endif
#endif
+
+#if HAVE___DSO_HANDLE
+extern void *__dso_handle __attribute__ ((__visibility__ ("hidden")));
#endif
static struct RegisterJIT {
@@ -302,14 +314,7 @@
// If the global is external, just remember the address.
if (GV->isDeclaration()) {
-#if defined(__APPLE__) && defined(MAC_OS_X_VERSION_10_4) && \
-((MAC_OS_X_VERSION_MIN_REQUIRED > MAC_OS_X_VERSION_10_4) || \
- (MAC_OS_X_VERSION_MIN_REQUIRED == MAC_OS_X_VERSION_10_4 && \
- __APPLE_CC__ >= 5330))
-// Apple gcc defaults to -fuse-cxa-atexit (i.e. calls __cxa_atexit instead
-// of atexit). It passes the address of linker generated symbol
__dso_handle
-// to the function.
-// This configuration change happened at version 5330.
+#if HAVE___DSO_HANDLE
if (GV->getName() == "__dso_handle")
return (void*)&__dso_handle;
#endif
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[llvm-commits] [llvm] r40601 - /llvm/trunk/configure
Author: reid
Date: Mon Jul 30 15:13:24 2007
New Revision: 40601
URL: http://llvm.org/viewvc/llvm-project?rev=40601&view=rev
Log:
Regenerate for __dso_handle, per Anton's request.
Modified:
llvm/trunk/configure
Modified: llvm/trunk/configure
URL:
http://llvm.org/viewvc/llvm-project/llvm/trunk/configure?rev=40601&r1=40600&r2=40601&view=diff
==
--- llvm/trunk/configure (original)
+++ llvm/trunk/configure Mon Jul 30 15:13:24 2007
@@ -2087,7 +2087,7 @@
;;
llvm-poolalloc) subdirs="$subdirs projects/llvm-poolalloc"
;;
- poolalloc) subdirs="$subdirs projects/poolalloc"
+ poolalloc)subdirs="$subdirs projects/poolalloc"
;;
llvm-kernel) subdirs="$subdirs projects/llvm-kernel"
;;
@@ -10369,7 +10369,7 @@
lt_dlunknown=0; lt_dlno_uscore=1; lt_dlneed_uscore=2
lt_status=$lt_dlunknown
cat > conftest.$ac_ext < conftest.$ac_ext
+ echo '#line 12516 "configure"' > conftest.$ac_ext
if { (eval echo "$as_me:$LINENO: \"$ac_compile\"") >&5
(eval $ac_compile) 2>&5
ac_status=$?
@@ -14231,11 +14231,11 @@
-e 's:.*FLAGS}\{0,1\} :&$lt_compiler_flag :; t' \
-e 's: [^ ]*conftest\.: $lt_compiler_flag&:; t' \
-e 's:$: $lt_compiler_flag:'`
- (eval echo "\"\$as_me:14231: $lt_compile\"" >&5)
+ (eval echo "\"\$as_me:14234: $lt_compile\"" >&5)
(eval "$lt_compile" 2>conftest.err)
ac_status=$?
cat conftest.err >&5
- echo "$as_me:14235: \$? = $ac_status" >&5
+ echo "$as_me:14238: \$? = $ac_status" >&5
if (exit $ac_status) && test -s "$ac_outfile"; then
# The compiler can only warn and ignore the option if not recognized
# So say no if there are warnings other than the usual output.
@@ -14499,11 +14499,11 @@
-e 's:.*FLAGS}\{0,1\} :&$lt_compiler_flag :; t' \
-e 's: [^ ]*conftest\.: $lt_compiler_flag&:; t' \
-e 's:$: $lt_compiler_flag:'`
- (eval echo "\"\$as_me:14499: $lt_compile\"" >&5)
+ (eval echo "\"\$as_me:14502: $lt_compile\"" >&5)
(eval "$lt_compile" 2>conftest.err)
ac_status=$?
cat conftest.err >&5
- echo "$as_me:14503: \$? = $ac_status" >&5
+ echo "$as_me:14506: \$? = $ac_status" >&5
if (exit $ac_status) && test -s "$ac_outfile"; then
# The compiler can only warn and ignore the option if not recognized
# So say no if there are warnings other than the usual output.
@@ -14603,11 +14603,11 @@
-e 's:.*FLAGS}\{0,1\} :&$lt_compiler_flag :; t' \
-e 's: [^ ]*conftest\.: $lt_compiler_flag&:; t' \
-e 's:$: $lt_compiler_flag:'`
- (eval echo "\"\$as_me:14603: $lt_compile\"" >&5)
+ (eval echo "\"\$as_me:14606: $lt_compile\"" >&5)
(eval "$lt_compile" 2>out/conftest.err)
ac_status=$?
cat out/conftest.err >&5
- echo "$as_me:14607: \$? = $ac_status" >&5
+ echo "$as_me:14610: \$? = $ac_status" >&5
if (exit $ac_status) && test -s out/conftest2.$ac_objext
then
# The compiler can only warn and ignore the option if not recognized
@@ -17055,7 +17055,7 @@
lt_dlunknown=0; lt_dlno_uscore=1; lt_dlneed_uscore=2
lt_status=$lt_dlunknown
cat > conftest.$ac_ext < conftest.$ac_ext <&5)
+ (eval echo "\"\$as_me:19526: $lt_compile\"" >&5)
(eval "$lt_compile" 2>conftest.err)
ac_status=$?
cat conftest.err >&5
- echo "$as_me:19527: \$? = $ac_status" >&5
+ echo "$as_me:19530: \$? = $ac_status" >&5
if (exit $ac_status) && test -s "$ac_outfile"; then
# The compiler can only warn and ignore the option if not recognized
# So say no if there are warnings other than the usual output.
@@ -19627,11 +19627,11 @@
-e 's:.*FLAGS}\{0,1\} :&$lt_compiler_flag :; t' \
-e 's: [^ ]*conftest\.: $lt_compiler_flag&:; t' \
-e 's:$: $lt_compiler_flag:'`
- (eval echo "\"\$as_me:19627: $lt_compile\"" >&5)
+ (eval echo "\"\$as_me:19630: $lt_compile\"" >&5)
(eval "$lt_compile" 2>out/conftest.err)
ac_status=$?
cat out/conftest.err >&5
- echo "$as_me:19631: \$? = $ac_status" >&5
+ echo "$as_me:19634: \$? = $ac_status" >&5
if (exit $ac_status) && test -s out/conftest2.$ac_objext
then
# The compiler can only warn and ignore the option if not recognized
@@ -21197,11 +21197,11 @@
-e 's:.*FLAGS}\{0,1\} :&$lt_compiler_flag :; t' \
-e 's: [^ ]*conftest\.: $lt_compiler_flag&:; t' \
-e 's:$: $lt_compiler_flag:'`
- (eval echo "\"\$as_me:21197: $lt_compile\"" >&5)
+ (eval echo "\"\$as_me:21200: $lt_compile\"" >&5)
(eval "$lt_compile" 2>conftest.err)
ac_status=$?
cat conftest.err >&5
- echo "$as_me:21201: \$? = $ac_status" >&5
+ echo "$as_me:21204: \$? = $ac_status" >&5
if (exit $ac_status) && test -s "$ac_outfile"; then
# The compiler can only warn and ignore the option if not recognized
# So say no if there are warnings other than the usual output.
@@ -21301,11 +21301,11 @@
-e 's:.*FLAGS}\{0,1\} :&$lt_compiler_flag :; t' \
-e 's: [^ ]*conftest\.: $lt_compiler_flag&:; t' \
-e 's:$: $lt_compiler_fl
[llvm-commits] [llvm] r40602 - /llvm/trunk/lib/Transforms/Scalar/LICM.cpp
Author: dpatel
Date: Mon Jul 30 15:19:59 2007
New Revision: 40602
URL: http://llvm.org/viewvc/llvm-project?rev=40602&view=rev
Log:
LICM preserves scalar evolution and dom frontier.
Modified:
llvm/trunk/lib/Transforms/Scalar/LICM.cpp
Modified: llvm/trunk/lib/Transforms/Scalar/LICM.cpp
URL:
http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/Scalar/LICM.cpp?rev=40602&r1=40601&r2=40602&view=diff
==
--- llvm/trunk/lib/Transforms/Scalar/LICM.cpp (original)
+++ llvm/trunk/lib/Transforms/Scalar/LICM.cpp Mon Jul 30 15:19:59 2007
@@ -42,6 +42,7 @@
#include "llvm/Analysis/AliasAnalysis.h"
#include "llvm/Analysis/AliasSetTracker.h"
#include "llvm/Analysis/Dominators.h"
+#include "llvm/Analysis/ScalarEvolution.h"
#include "llvm/Transforms/Utils/PromoteMemToReg.h"
#include "llvm/Support/CFG.h"
#include "llvm/Support/Compiler.h"
@@ -78,6 +79,8 @@
AU.addRequired();
AU.addRequired(); // For scalar promotion (mem2reg)
AU.addRequired();
+ AU.addPreserved();
+ AU.addPreserved();
}
bool doFinalization() {
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[llvm-commits] [llvm] r40603 - /llvm/trunk/lib/Transforms/Scalar/LoopRotation.cpp
Author: dpatel Date: Mon Jul 30 15:22:53 2007 New Revision: 40603 URL: http://llvm.org/viewvc/llvm-project?rev=40603&view=rev Log: Loop Rotation pass preserves dominator tree and frontier. Modified: llvm/trunk/lib/Transforms/Scalar/LoopRotation.cpp Modified: llvm/trunk/lib/Transforms/Scalar/LoopRotation.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/Scalar/LoopRotation.cpp?rev=40603&r1=40602&r2=40603&view=diff == --- llvm/trunk/lib/Transforms/Scalar/LoopRotation.cpp (original) +++ llvm/trunk/lib/Transforms/Scalar/LoopRotation.cpp Mon Jul 30 15:22:53 2007 @@ -62,6 +62,8 @@ AU.addPreserved(); AU.addRequiredID(LoopSimplifyID); AU.addPreservedID(LoopSimplifyID); + AU.addPreserved(); + AU.addPreserved(); } // Helper functions ___ llvm-commits mailing list llvm-commits@cs.uiuc.edu http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
[llvm-commits] [llvm] r40604 - /llvm/trunk/lib/Transforms/Utils/LCSSA.cpp
Author: dpatel Date: Mon Jul 30 15:23:45 2007 New Revision: 40604 URL: http://llvm.org/viewvc/llvm-project?rev=40604&view=rev Log: LCSSA preserves dom info. Modified: llvm/trunk/lib/Transforms/Utils/LCSSA.cpp Modified: llvm/trunk/lib/Transforms/Utils/LCSSA.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/Utils/LCSSA.cpp?rev=40604&r1=40603&r2=40604&view=diff == --- llvm/trunk/lib/Transforms/Utils/LCSSA.cpp (original) +++ llvm/trunk/lib/Transforms/Utils/LCSSA.cpp Mon Jul 30 15:23:45 2007 @@ -73,6 +73,14 @@ AU.addPreserved(); AU.addRequired(); AU.addPreserved(); + AU.addPreserved(); + + // Request DominanceFrontier now, even though LCSSA does + // not use it. This allows Pass Manager to schedule Dominance + // Frontier early enough such that one LPPassManager can handle + // multiple loop transformation passes. + AU.addRequired(); + AU.addPreserved(); } private: void getLoopValuesUsedOutsideLoop(Loop *L, ___ llvm-commits mailing list llvm-commits@cs.uiuc.edu http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
[llvm-commits] [llvm] r40605 - /llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
Author: pingbak
Date: Mon Jul 30 16:00:31 2007
New Revision: 40605
URL: http://llvm.org/viewvc/llvm-project?rev=40605&view=rev
Log:
- Allow custom lowering for CTPOP, CTTZ, CTLZ.
- Fixed an existing unexpanded tab.
Modified:
llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
Modified: llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
URL:
http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp?rev=40605&r1=40604&r2=40605&view=diff
==
--- llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp (original)
+++ llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp Mon Jul 30 16:00:31 2007
@@ -2738,9 +2738,16 @@
case ISD::CTLZ:
Tmp1 = LegalizeOp(Node->getOperand(0)); // Op
switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) {
-case TargetLowering::Custom: assert(0 && "Cannot custom handle this yet!");
+case TargetLowering::Custom:
case TargetLowering::Legal:
Result = DAG.UpdateNodeOperands(Result, Tmp1);
+ if (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0)) ==
+ TargetLowering::Custom) {
+ Tmp1 = TLI.LowerOperation(Result, DAG);
+ if (Tmp1.Val) {
+ Result = Tmp1;
+ }
+ }
break;
case TargetLowering::Promote: {
MVT::ValueType OVT = Tmp1.getValueType();
@@ -2760,7 +2767,7 @@
DAG.getConstant(MVT::getSizeInBits(NVT), NVT),
ISD::SETEQ);
Result = DAG.getNode(ISD::SELECT, NVT, Tmp2,
- DAG.getConstant(MVT::getSizeInBits(OVT),NVT), Tmp1);
+ DAG.getConstant(MVT::getSizeInBits(OVT),NVT),
Tmp1);
break;
case ISD::CTLZ:
// Tmp1 = Tmp1 - (sizeinbits(NVT) - sizeinbits(Old VT))
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[llvm-commits] [llvm] r40606 - /llvm/trunk/lib/Transforms/Scalar/LoopUnswitch.cpp
Author: dpatel
Date: Mon Jul 30 16:10:44 2007
New Revision: 40606
URL: http://llvm.org/viewvc/llvm-project?rev=40606&view=rev
Log:
Remove dead code.
Modified:
llvm/trunk/lib/Transforms/Scalar/LoopUnswitch.cpp
Modified: llvm/trunk/lib/Transforms/Scalar/LoopUnswitch.cpp
URL:
http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/Scalar/LoopUnswitch.cpp?rev=40606&r1=40605&r2=40606&view=diff
==
--- llvm/trunk/lib/Transforms/Scalar/LoopUnswitch.cpp (original)
+++ llvm/trunk/lib/Transforms/Scalar/LoopUnswitch.cpp Mon Jul 30 16:10:44 2007
@@ -452,28 +452,22 @@
else
OrigIDom = OrigIDomNode->getBlock();
- // Initially use Orig's immediate dominator as NewBB's immediate dominator.
- BasicBlock *NewIDom = OrigIDom;
- DenseMap::iterator I = VM.find(OrigIDom);
- if (I != VM.end()) {
- //if (!DT->getNode(OrigIDom))
- // CloneDomInfo(NewIDom, OrigIDom, NewPreheader, OrigPreheader,
- // OrigHeader, DT, DF, VM);
-
- NewIDom = cast(I->second);
-
- // If NewIDom does not have corresponding dominatore tree node then
- // get one.
- if (!DT->getNode(NewIDom))
+ // Initially use Orig's immediate dominator as NewBB's immediate dominator.
+ BasicBlock *NewIDom = OrigIDom;
+ DenseMap::iterator I = VM.find(OrigIDom);
+ if (I != VM.end()) {
+NewIDom = cast(I->second);
+
+// If NewIDom does not have corresponding dominatore tree node then
+// get one.
+if (!DT->getNode(NewIDom))
CloneDomInfo(NewIDom, OrigIDom, NewPreheader, OrigPreheader,
OrigHeader, DT, DF, VM);
}
- // if (NewBB == NewIDom) {
- // DT->addNewBlock(NewBB, OrigIDom);
- // DT->changeImmediateDominator(NewBB, NewIDom);
- //} else
-DT->addNewBlock(NewBB, NewIDom);
-
+
+ DT->addNewBlock(NewBB, NewIDom);
+
+ // Copy cloned dominance frontiner set
DominanceFrontier::DomSetType NewDFSet;
if (DF) {
DominanceFrontier::iterator DFI = DF->find(Orig);
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[llvm-commits] [llvm] r40607 - /llvm/trunk/lib/Transforms/Scalar/GVN.cpp
Author: resistor
Date: Mon Jul 30 16:26:39 2007
New Revision: 40607
URL: http://llvm.org/viewvc/llvm-project?rev=40607&view=rev
Log:
Avoid potential iterator invalidation problems.
Modified:
llvm/trunk/lib/Transforms/Scalar/GVN.cpp
Modified: llvm/trunk/lib/Transforms/Scalar/GVN.cpp
URL:
http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/Scalar/GVN.cpp?rev=40607&r1=40606&r2=40607&view=diff
==
--- llvm/trunk/lib/Transforms/Scalar/GVN.cpp (original)
+++ llvm/trunk/lib/Transforms/Scalar/GVN.cpp Mon Jul 30 16:26:39 2007
@@ -895,11 +895,14 @@
currAvail = availableOut[DI->getIDom()->getBlock()];
for (BasicBlock::iterator BI = BB->begin(), BE = BB->end();
- BI != BE; ++BI) {
+ BI != BE; ) {
changed_function |= processInstruction(BI, currAvail, lastSeenLoad,
toErase);
NumGVNInstr += toErase.size();
+ // Avoid iterator invalidation
+ ++BI;
+
for (SmallVector::iterator I = toErase.begin(),
E = toErase.end(); I != E; ++I)
(*I)->eraseFromParent();
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Re: [llvm-commits] Patch for X86 to use subregs
On Jul 30, 2007, at 12:42 PM, Christopher Lamb wrote: I contend that insert_subreg is target specific already. It currently requires a target specific subreg index, which is a kind of target specific hook, that tells coalescing how to deal with it. A two operand insert_subreg (or an insert_subreg from undef) is a move between target register classes that have subreg relationship. insert_subreg defines the entire superreg value, and I don't see why it's so bad to allow targets to specify their own semantics for what happens to the register being inserted into? This is essentially what the subreg index is already, we could even put semantics in the SubRegSet in the RegisterInfo.td allowing the semantics to be checked by the compiler. A parameter of the set that indicates that an insert into the subreg i either leaves the rest of the superreg value untouched (insert_subreg reg, reg, i), or it implicitly sets the rest of the register to a known value (insert_subreg constant_value, reg, i), or to undef (insert_subreg undef, reg, i). Only the specified semantics for that SubRegSet of the register class of the result of the insert_subreg would be valid, and could be ensured so. This seems to me to allow insert_subreg to capture may useful cases, and it captures the register set semantics in the RegisterInfo.td file, where I think it belongs. No. I am sorry, that cannot be allowed. insert_subreg must mean the same for all targets. We cannot allow x86-64 insert_subreg (and only the 32-bit variant of this, not 16-bit or 8-bit ones) to mean insert the lower 32-bit while zero-ing the upper 32-bit. The deviates from llvm philosophy. 2: two operant variant of insert_subreg should mean the superreg is undef. If you insert a value into a low part, the rest of the superreg is still undef. I think the meaning of insert_subreg instruction (both 2 and 3 operand versions) must have semantics specific to the target. For example, on x86-64 there is no valid 3 operand insert_subreg for a 32-bit value into 64-bits, because the 32- bit result is always going to be zero extended and overwrite the upper 32-bits. It just means there is no way to implement a insert_subreg with a single instruction under x86-64. But that is perfectly ok. Apart from anyext, x86-64 just isn't going to benefit from it. It's also impossible to read or modify the higher 32-bits. Currently the move that's generated isn't handled by coalescing because the source and destination belong to different register classes. The insert_subreg is meant to be a means to move values implicitly between register classes that have a subreg relationship. So if insert_subreg semantics must be target independent, then I think you isel the zero-extending move to be: (i64 (INSERT_SUBREG (i64 0), GR32:$src, 3)) But that's wrong. Remember the superreg argument is an read / mod / write operand. That is, the first operand is a use, the def is the LHS but we are forcing the allocator to target the same physical register. v1 = some existing value v1 = insert_subreg v1, GR32:$src, 3 But zext is zeroing out the top part. i.e. zext is equal to mov v1, 0 v1 = insert_subreg v1, GR32:$src, 3 I'm suggesting to expand the semantics of insert_subreg as described above. The thing is that the general coalescing will be able to determine that the copy from undef is unneeded for (INSERT_SUBREG (i64 undef), GR32:$src, 3), but it would take a target specific hook to know that the constant zero is unneeded on x86-64. A target specific hook for this might be useful, but I think that this is in the realm of future work now. Sorry, I am not following. zext on x86-64, i.e. the 32-bit move, cannot be coalesced away. No need for target specific hook. I simply disagree here: http://www.x86-64.org/documentation/assembly.html see the section 'Implicit Zero Extend' EAX = op RAX = mov EAX <= this may be removed ... = use RAX The mov can only be removed some of the time. It's different from moves (which can always be removed if both lhs and rhs match), nor is it the same for the moves generated from lowering insert_subreg (which can be removed if rhs is a sub-register of rhs). It's a different problem that should be handled differently, it's not a register coalescing problem. 3: why is there a two operant variant in the first place? Why not use undef for the superreg operant? To note, the two operand variant is of the MachineInstr. The DAG form would be to represent the superregister as coming from an undef node, but this gets isel'd to the two operand MachineInstr of insert_subreg. The reason is that undef is typically selected to an implicit def of a register. This causes an unnecessary move to be generated later on. This move can be optimized away later with more difficulty during subreg lowering by checking whether the input register is de
Re: [llvm-commits] Patch for X86 to use subregs
On Jul 30, 2007, at 2:40 PM, Evan Cheng wrote: > > I appreciate you're trying to think of ways to expand the use of > subreg work. But x86-64 implicit zero-extension is not the same > problem. Trying to solve the x86-64 optimization issue this way is > a unacceptable hack. Your subreg pass is a general pass. Please > keep it that way. Settled. There are other cases where I think it would be interesting to model implicit operations or more complex register constrains in a way that the register allocator an coalescing has a way to deal with them. For instance, the kind of constraints that cause MOV16to16_ to be necessary. Here I'd think that coalescing could be taught how to coalesce moves between register classes and sub classes of that class. Currently the following MOV16to16_ wouldn't be coalesced, though it could be, because CX is in class GR32_ and AX is in class GR32. CX = mov AX Coalescing would see this as GR32_:reg1025 = mov GR32:reg1024 So it isn't as simple as it may seem at first because you'd potentially have to tighten the register class constraint on the def of reg1024, but I think it's doable... There is an internal architecture here that it would be interesting to target with LLVM, but it happens to have a highly constrained register file, requiring many of these currently un-coalesced moves between register sub classes and their parent. Do you think I should open a PR on that? -- Christopher Lamb ___ llvm-commits mailing list llvm-commits@cs.uiuc.edu http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
[llvm-commits] [llvm] r40608 - /llvm/trunk/lib/ExecutionEngine/Interpreter/ExternalFunctions.cpp
Author: asl
Date: Mon Jul 30 18:03:25 2007
New Revision: 40608
URL: http://llvm.org/viewvc/llvm-project?rev=40608&view=rev
Log:
Add a comment: don't expect from external function resolver in interpreter
things, it wasn't designed to handle.
Modified:
llvm/trunk/lib/ExecutionEngine/Interpreter/ExternalFunctions.cpp
Modified: llvm/trunk/lib/ExecutionEngine/Interpreter/ExternalFunctions.cpp
URL:
http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/ExecutionEngine/Interpreter/ExternalFunctions.cpp?rev=40608&r1=40607&r2=40608&view=diff
==
--- llvm/trunk/lib/ExecutionEngine/Interpreter/ExternalFunctions.cpp (original)
+++ llvm/trunk/lib/ExecutionEngine/Interpreter/ExternalFunctions.cpp Mon Jul 30
18:03:25 2007
@@ -62,6 +62,11 @@
}
}
+// Try to find address of external function given a Function object.
+// Please note, that interpreter doesn't know how to assemble a
+// real call in general case (this is JIT job), that's why it assumes,
+// that all external functions has the same (and pretty "general") signature.
+// The typical example of such functions are "lle_X_" ones.
static ExFunc lookupFunction(const Function *F) {
// Function not found, look it up... start by figuring out what the
// composite function name should be.
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[llvm-commits] [llvm] r40609 - /llvm/trunk/lib/Transforms/Scalar/LoopUnswitch.cpp
Author: dpatel
Date: Mon Jul 30 18:07:10 2007
New Revision: 40609
URL: http://llvm.org/viewvc/llvm-project?rev=40609&view=rev
Log:
If loop can be unswitched again, then do it yourself.
Modified:
llvm/trunk/lib/Transforms/Scalar/LoopUnswitch.cpp
Modified: llvm/trunk/lib/Transforms/Scalar/LoopUnswitch.cpp
URL:
http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/Scalar/LoopUnswitch.cpp?rev=40609&r1=40608&r2=40609&view=diff
==
--- llvm/trunk/lib/Transforms/Scalar/LoopUnswitch.cpp (original)
+++ llvm/trunk/lib/Transforms/Scalar/LoopUnswitch.cpp Mon Jul 30 18:07:10 2007
@@ -70,12 +70,14 @@
SmallPtrSet UnswitchedVals;
bool OptimizeForSize;
+bool redoLoop;
public:
static char ID; // Pass ID, replacement for typeid
LoopUnswitch(bool Os = false) :
- LoopPass((intptr_t)&ID), OptimizeForSize(Os) {}
+ LoopPass((intptr_t)&ID), OptimizeForSize(Os), redoLoop(false) {}
bool runOnLoop(Loop *L, LPPassManager &LPM);
+bool processLoop(Loop *L);
/// This transformation requires natural loop information & requires that
/// loop preheaders be inserted into the CFG...
@@ -152,11 +154,23 @@
}
bool LoopUnswitch::runOnLoop(Loop *L, LPPassManager &LPM_Ref) {
- assert(L->isLCSSAForm());
LI = &getAnalysis();
LPM = &LPM_Ref;
bool Changed = false;
-
+
+ do {
+redoLoop = false;
+Changed |= processLoop(L);
+ } while(redoLoop);
+
+ return Changed;
+}
+
+/// processLoop - Do actual work and unswitch loop if possible and profitable.
+bool LoopUnswitch::processLoop(Loop *L) {
+ assert(L->isLCSSAForm());
+ bool Changed = false;
+
// Loop over all of the basic blocks in the loop. If we find an interior
// block that is branching on a loop-invariant condition, we can unswitch
this
// loop.
@@ -576,7 +590,7 @@
OrigPH->getTerminator()->eraseFromParent();
// We need to reprocess this loop, it could be unswitched again.
- LPM->redoLoop(L);
+ redoLoop = true;
// Now that we know that the loop is never entered when this condition is a
// particular value, rewrite the loop with this info. We know that this will
@@ -740,7 +754,7 @@
OldBR->eraseFromParent();
LoopProcessWorklist.push_back(NewLoop);
- LPM->redoLoop(L);
+ redoLoop = true;
// Now we rewrite the original code to know that the condition is true and
the
// new code to know that the condition is false.
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[llvm-commits] [llvm] r40610 - in /llvm/trunk: lib/AsmParser/Lexer.l lib/AsmParser/llvmAsmParser.y test/Assembler/2007-07-30-AutoUpgradeZextSext.ll
Author: reid
Date: Mon Jul 30 21:57:37 2007
New Revision: 40610
URL: http://llvm.org/viewvc/llvm-project?rev=40610&view=rev
Log:
For PR1553:
Make the AsmParser auto-upgrade the old zext and sext
keywords for parameter attributes and handle the
end-of-line ambiguity.
Added:
llvm/trunk/test/Assembler/2007-07-30-AutoUpgradeZextSext.ll
Modified:
llvm/trunk/lib/AsmParser/Lexer.l
llvm/trunk/lib/AsmParser/llvmAsmParser.y
Modified: llvm/trunk/lib/AsmParser/Lexer.l
URL:
http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/AsmParser/Lexer.l?rev=40610&r1=40609&r2=40610&view=diff
==
--- llvm/trunk/lib/AsmParser/Lexer.l (original)
+++ llvm/trunk/lib/AsmParser/Lexer.l Mon Jul 30 21:57:37 2007
@@ -177,6 +177,8 @@
*/
HexIntConstant [us]0x[0-9A-Fa-f]+
+/* WSNL - shorthand for newline followed by whitespace */
+WSNL [ \r\t\n]*$
%%
{Comment} { /* Ignore comments for now */ }
@@ -234,6 +236,10 @@
noalias { return NOALIAS; }
byval { return BYVAL; }
nest{ return NEST; }
+sext{WSNL} { // For auto-upgrade only, drop in LLVM 3.0
+ return SIGNEXT; }
+zext{WSNL} { // For auto-upgrade only, drop in LLVM 3.0
+ return ZEROEXT; }
void{ RET_TY(Type::VoidTy, VOID); }
float { RET_TY(Type::FloatTy, FLOAT); }
Modified: llvm/trunk/lib/AsmParser/llvmAsmParser.y
URL:
http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/AsmParser/llvmAsmParser.y?rev=40610&r1=40609&r2=40610&view=diff
==
--- llvm/trunk/lib/AsmParser/llvmAsmParser.y (original)
+++ llvm/trunk/lib/AsmParser/llvmAsmParser.y Mon Jul 30 21:57:37 2007
@@ -1225,7 +1225,9 @@
};
ParamAttr : ZEROEXT { $$ = ParamAttr::ZExt; }
+ | ZEXT{ $$ = ParamAttr::ZExt; }
| SIGNEXT { $$ = ParamAttr::SExt; }
+ | SEXT{ $$ = ParamAttr::SExt; }
| INREG { $$ = ParamAttr::InReg; }
| SRET{ $$ = ParamAttr::StructRet; }
| NOALIAS { $$ = ParamAttr::NoAlias; }
Added: llvm/trunk/test/Assembler/2007-07-30-AutoUpgradeZextSext.ll
URL:
http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Assembler/2007-07-30-AutoUpgradeZextSext.ll?rev=40610&view=auto
==
--- llvm/trunk/test/Assembler/2007-07-30-AutoUpgradeZextSext.ll (added)
+++ llvm/trunk/test/Assembler/2007-07-30-AutoUpgradeZextSext.ll Mon Jul 30
21:57:37 2007
@@ -0,0 +1,12 @@
+; Test that upgrading zext/sext attributes to zeroext and signext
+; works correctly.
+; PR1553
+; RUN: llvm-as < %s > /dev/null
+
+define i32 @bar() {
+%t = call i8 @foo( i8 10 sext ) zext
+%x = zext i8 %t to i32
+ret i32 %x
+}
+
+declare i8 @foo(i8 signext ) zeroext
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[llvm-commits] [llvm] r40612 - /llvm/trunk/lib/AsmParser/Lexer.l
Author: reid
Date: Mon Jul 30 22:55:43 2007
New Revision: 40612
URL: http://llvm.org/viewvc/llvm-project?rev=40612&view=rev
Log:
Don't include newlines in the whitespace before newline (WSNL) rule.
Fix the comment for WSNL to describe its actual function.
Modified:
llvm/trunk/lib/AsmParser/Lexer.l
Modified: llvm/trunk/lib/AsmParser/Lexer.l
URL:
http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/AsmParser/Lexer.l?rev=40612&r1=40611&r2=40612&view=diff
==
--- llvm/trunk/lib/AsmParser/Lexer.l (original)
+++ llvm/trunk/lib/AsmParser/Lexer.l Mon Jul 30 22:55:43 2007
@@ -177,8 +177,8 @@
*/
HexIntConstant [us]0x[0-9A-Fa-f]+
-/* WSNL - shorthand for newline followed by whitespace */
-WSNL [ \r\t\n]*$
+/* WSNL - shorthand for whitespace followed by newline */
+WSNL [ \r\t]*$
%%
{Comment} { /* Ignore comments for now */ }
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[llvm-commits] [llvm] r40613 - in /llvm/trunk/lib/AsmParser: Lexer.cpp.cvs Lexer.l.cvs
Author: reid
Date: Mon Jul 30 22:55:56 2007
New Revision: 40613
URL: http://llvm.org/viewvc/llvm-project?rev=40613&view=rev
Log:
Regenerate (again).
Modified:
llvm/trunk/lib/AsmParser/Lexer.cpp.cvs
llvm/trunk/lib/AsmParser/Lexer.l.cvs
Modified: llvm/trunk/lib/AsmParser/Lexer.cpp.cvs
URL:
http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/AsmParser/Lexer.cpp.cvs?rev=40613&r1=40612&r2=40613&view=diff
==
--- llvm/trunk/lib/AsmParser/Lexer.cpp.cvs (original)
+++ llvm/trunk/lib/AsmParser/Lexer.cpp.cvs Mon Jul 30 22:55:56 2007
@@ -459,71 +459,71 @@
static yyconst short int yy_base[595] =
{ 0,
-0,0, 1276, 1277, 1277, 1277, 1271, 1260, 41, 36,
+0,0, 1272, 1273, 1273, 1273, 1267, 1256, 41, 36,
45, 51, 57, 63,0, 74, 66, 69, 68, 90,
92, 121, 78, 36, 148, 93, 117, 114, 167, 138,
- 67, 194, 152, 226, 134, 95, 103, 101, 1269, 1277,
- 1258, 1277, 1267,0, 199, 216, 232, 131, 253, 269,
- 274,0, 1266,0, 203, 119, 154, 150, 115, 163,
- 149, 80, 1255, 191, 49, 164, 157, 108, 279, 81,
- 184, 169, 1254, 223, 239, 188, 220, 224, 276, 182,
+ 67, 194, 152, 226, 134, 95, 103, 101, 1265, 1273,
+ 1254, 1273, 1263,0, 199, 216, 232, 131, 253, 269,
+ 274,0, 1262,0, 203, 119, 154, 150, 115, 163,
+ 149, 80, 1251, 191, 49, 164, 157, 108, 279, 81,
+ 184, 169, 1250, 223, 239, 188, 220, 224, 276, 182,
237, 241, 245, 295, 258, 288, 118, 289, 296, 233,
297, 306, 301, 298, 303, 304, 305, 308, 319, 323,
316, 327, 324, 330, 331, 334, 335, 337, 339, 340,
- 341, 356, 352, 344, 342, 186, 345, 360, 348, 1253,
+ 341, 356, 352, 344, 342, 186, 345, 360, 348, 1249,
369, 371, 372, 375, 377, 373, 378, 389, 385, 379,
- 390, 403, 407, 392, 393, 1252, 1261, 1277,0, 421,
- 1250, 436, 454,0, 1259, 1277,0, 1248, 437, 381,
- 1247, 412, 423, 1246, 410, 430, 455, 413, 1245, 456,
- 439, 457, 426, 427, 428, 458, 459, 1244, 460, 464,
+ 390, 403, 407, 392, 393, 1248, 1257, 1273,0, 421,
+ 1246, 436, 454,0, 1255, 1273,0, 1244, 437, 381,
+ 1243, 412, 423, 1242, 410, 430, 455, 413, 1241, 456,
+ 439, 457, 426, 427, 428, 458, 459, 1240, 460, 464,
467, 469, 471, 473, 474, 476, 475, 478, 477, 481,
480, 483, 486, 494, 501, 499, 506, 503, 505, 507,
- 508, 1243, 510, 513, 514, 517, 515, 1242, 1241, 1240,
+ 508, 1239, 510, 513, 514, 517, 515, 1238, 1237, 1236,
- 1239, 1238, 1237, 511, 1236, 1235, 516, 519, 1234, 548,
- 522, 525, 526, 537, 1233, 1232, 1231, 528, 550, 553,
- 562, 1230, 1229, 563, 542, 1228, 541, 566, 567, 568,
- 569, 573, 574, 570, 1227, 1226, 1225, 575, 1224, 1223,
- 576, 1222, 1221, 585, 588, 590, 592, 597, 593, 600,
- 572, 1220, 601, 603, 1277, 612, 632, 636, 640, 645,
- 623, 647, 530, 648, 1219, 649, 612, 605, 1218, 650,
+ 1235, 1234, 1233, 511, 1232, 1231, 516, 519, 1230, 548,
+ 522, 525, 526, 537, 1229, 1228, 1227, 528, 550, 553,
+ 562, 1226, 1225, 563, 542, 1224, 541, 566, 567, 568,
+ 569, 573, 574, 570, 1223, 1222, 1221, 575, 1220, 1219,
+ 576, 1218, 1217, 585, 588, 590, 592, 597, 593, 600,
+ 572, 1216, 601, 603, 1273, 612, 632, 636, 640, 645,
+ 623, 647, 530, 648, 1215, 649, 612, 605, 1214, 650,
651, 652, 613, 653, 655, 654, 656, 660, 657, 664,
- 604, 672, 1217, 1216, 659, 661, 663, 662, 1215, 1214,
- 674, 678, 681, 1213, 677, 692, 693, 694, 695, 696,
+ 604, 672, 1213, 1212, 659, 661, 663, 662, 1211, 1210,
+ 674, 678, 681, 1209, 677, 692, 693, 694, 695, 696,
- 697, 1212, 1211, 698, 702, 1210, 705, 699, 700, 1209,
- 701, 711, 703,0, 1208, 706, 724, 740, 725, 731,
- 733, 734, 1207, 1206, 737, 730, 1205, 739, 742, 735,
- 1204, 744, 1203, 1202, 746, 750, 753, 754, 1201, 755,
- 1200, 756, 1199, 758, 760, 775, 769, 1198, 1197, 773,
- 762, 1196, 776, 1195, 778, 782, 783, 784, 785, 617,
- 787, 790, 791, 793, 792, 1194, 794, 1193, 1192, 798,
- 803, 796, 805, 797, 804, 1191, 808, 809, 816, 818,
- 1190, 819, 821, 820, 825, 823, 824, 833, 826, 835,
- 839, 840, 59, 719, 841, 842, 844, 845, 1189, 846,
-
- 847, 851, 852, 1188, 850, 1187, 855, 866, 856, 867,
- 873, 854, 861, 869, 888, 894, 1186, 874, 880, 1185,
- 884, 885, 886, 1184, 890, 891, 892, 1183, 893, 894,
- 1182, 1181, 1180, 895, 900, 1179, 1178, 897, 906, 901,
- 11
[llvm-commits] [llvm] r40616 - /llvm/trunk/lib/System/DynamicLibrary.cpp
Author: lattner Date: Tue Jul 31 01:00:51 2007 New Revision: 40616 URL: http://llvm.org/viewvc/llvm-project?rev=40616&view=rev Log: Fix PR1581, patch by Timo Savola Modified: llvm/trunk/lib/System/DynamicLibrary.cpp Modified: llvm/trunk/lib/System/DynamicLibrary.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/System/DynamicLibrary.cpp?rev=40616&r1=40615&r2=40616&view=diff == --- llvm/trunk/lib/System/DynamicLibrary.cpp (original) +++ llvm/trunk/lib/System/DynamicLibrary.cpp Tue Jul 31 01:00:51 2007 @@ -62,7 +62,7 @@ lt_dlhandle a_handle = lt_dlopen(0); - assert(a_handle == 0 || "Can't open program as dynamic library"); + assert(a_handle == 0 && "Can't open program as dynamic library"); handle = a_handle; OpenedHandles.push_back(a_handle); ___ llvm-commits mailing list llvm-commits@cs.uiuc.edu http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
[llvm-commits] [llvm] r40617 - /llvm/trunk/lib/Target/X86/X86ISelLowering.cpp
Author: evancheng
Date: Tue Jul 31 01:21:44 2007
New Revision: 40617
URL: http://llvm.org/viewvc/llvm-project?rev=40617&view=rev
Log:
This isn't safe when there are uses of load's chain result.
Modified:
llvm/trunk/lib/Target/X86/X86ISelLowering.cpp
Modified: llvm/trunk/lib/Target/X86/X86ISelLowering.cpp
URL:
http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86ISelLowering.cpp?rev=40617&r1=40616&r2=40617&view=diff
==
--- llvm/trunk/lib/Target/X86/X86ISelLowering.cpp (original)
+++ llvm/trunk/lib/Target/X86/X86ISelLowering.cpp Tue Jul 31 01:21:44 2007
@@ -3010,17 +3010,10 @@
// Use two pinsrw instructions to insert a 32 bit value.
Idx <<= 1;
if (MVT::isFloatingPoint(N1.getValueType())) {
-if (ISD::isNON_EXTLoad(N1.Val)) {
- // Just load directly from f32mem to GR32.
- LoadSDNode *LD = cast(N1);
- N1 = DAG.getLoad(MVT::i32, LD->getChain(), LD->getBasePtr(),
- LD->getSrcValue(), LD->getSrcValueOffset());
-} else {
- N1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, MVT::v4f32, N1);
- N1 = DAG.getNode(ISD::BIT_CONVERT, MVT::v4i32, N1);
- N1 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, MVT::i32, N1,
- DAG.getConstant(0, getPointerTy()));
-}
+N1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, MVT::v4f32, N1);
+N1 = DAG.getNode(ISD::BIT_CONVERT, MVT::v4i32, N1);
+N1 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, MVT::i32, N1,
+ DAG.getConstant(0, getPointerTy()));
}
N0 = DAG.getNode(ISD::BIT_CONVERT, MVT::v8i16, N0);
N0 = DAG.getNode(X86ISD::PINSRW, MVT::v8i16, N0, N1,
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[llvm-commits] [llvm] r40618 - /llvm/trunk/lib/VMCore/Verifier.cpp
Author: reid Date: Tue Jul 31 01:33:37 2007 New Revision: 40618 URL: http://llvm.org/viewvc/llvm-project?rev=40618&view=rev Log: The InReg parameter attribute is valid on function results. The llvm-gcc-4.0 front end converts regparm attribute on the gcc function into InReg attribute on the llvm function. This fixes test/CFrontend/2002-07-30-SubrefSetAssertion.c Modified: llvm/trunk/lib/VMCore/Verifier.cpp Modified: llvm/trunk/lib/VMCore/Verifier.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/VMCore/Verifier.cpp?rev=40618&r1=40617&r2=40618&view=diff == --- llvm/trunk/lib/VMCore/Verifier.cpp (original) +++ llvm/trunk/lib/VMCore/Verifier.cpp Tue Jul 31 01:33:37 2007 @@ -358,8 +358,7 @@ "Invalid struct-return function!", &F); const uint16_t ReturnIncompatible = -ParamAttr::ByVal | ParamAttr::InReg | -ParamAttr::Nest | ParamAttr::StructRet; +ParamAttr::ByVal | ParamAttr::Nest | ParamAttr::StructRet; const uint16_t ParameterIncompatible = ParamAttr::NoReturn | ParamAttr::NoUnwind; ___ llvm-commits mailing list llvm-commits@cs.uiuc.edu http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
[llvm-commits] [llvm] r40619 - /llvm/trunk/lib/AsmParser/llvmAsmParser.y
Author: reid
Date: Tue Jul 31 01:37:27 2007
New Revision: 40619
URL: http://llvm.org/viewvc/llvm-project?rev=40619&view=rev
Log:
Allow the INREG parameter attribute to be added to functions. This permits the
function result to be passed in a register. This implements the GCC regparm
function attribute for llvm by translation to the InReg parameter attribute
and fixes test/CFrontend/2002-07-30-SubregSetAssertion.c
Modified:
llvm/trunk/lib/AsmParser/llvmAsmParser.y
Modified: llvm/trunk/lib/AsmParser/llvmAsmParser.y
URL:
http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/AsmParser/llvmAsmParser.y?rev=40619&r1=40618&r2=40619&view=diff
==
--- llvm/trunk/lib/AsmParser/llvmAsmParser.y (original)
+++ llvm/trunk/lib/AsmParser/llvmAsmParser.y Tue Jul 31 01:37:27 2007
@@ -1245,6 +1245,7 @@
| NOUNWIND { $$ = ParamAttr::NoUnwind; }
| ZEROEXT { $$ = ParamAttr::ZExt; }
| SIGNEXT { $$ = ParamAttr::SExt; }
+ | INREG{ $$ = ParamAttr::InReg;}
;
OptFuncAttrs : /* empty */ { $$ = ParamAttr::None; }
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[llvm-commits] [llvm-gcc-4.0] r40622 - in /llvm-gcc-4.0/trunk/gcc: llvm-backend.cpp llvm-convert.cpp llvm-internal.h llvm-types.cpp
Author: clamb
Date: Tue Jul 31 01:50:25 2007
New Revision: 40622
URL: http://llvm.org/viewvc/llvm-project?rev=40622&view=rev
Log:
Add support for scraping the function decl for restrict qualifiers to handle
restrict function parameters for both C/C++. Thanks to Sheng Zhou for pointing
the way...
Modified:
llvm-gcc-4.0/trunk/gcc/llvm-backend.cpp
llvm-gcc-4.0/trunk/gcc/llvm-convert.cpp
llvm-gcc-4.0/trunk/gcc/llvm-internal.h
llvm-gcc-4.0/trunk/gcc/llvm-types.cpp
Modified: llvm-gcc-4.0/trunk/gcc/llvm-backend.cpp
URL:
http://llvm.org/viewvc/llvm-project/llvm-gcc-4.0/trunk/gcc/llvm-backend.cpp?rev=40622&r1=40621&r2=40622&view=diff
==
--- llvm-gcc-4.0/trunk/gcc/llvm-backend.cpp (original)
+++ llvm-gcc-4.0/trunk/gcc/llvm-backend.cpp Tue Jul 31 01:50:25 2007
@@ -988,7 +988,7 @@
if (FnEntry == 0) {
unsigned CC;
const FunctionType *Ty =
-TheTypeConverter->ConvertFunctionType(TREE_TYPE(decl), NULL, CC);
+TheTypeConverter->ConvertFunctionType(TREE_TYPE(decl), decl, NULL, CC);
FnEntry = new Function(Ty, Function::ExternalLinkage, Name, TheModule);
FnEntry->setCallingConv(CC);
Modified: llvm-gcc-4.0/trunk/gcc/llvm-convert.cpp
URL:
http://llvm.org/viewvc/llvm-project/llvm-gcc-4.0/trunk/gcc/llvm-convert.cpp?rev=40622&r1=40621&r2=40622&view=diff
==
--- llvm-gcc-4.0/trunk/gcc/llvm-convert.cpp (original)
+++ llvm-gcc-4.0/trunk/gcc/llvm-convert.cpp Tue Jul 31 01:50:25 2007
@@ -514,8 +514,9 @@
} else {
// Otherwise, just get the type from the function itself.
FTy = TheTypeConverter->ConvertFunctionType(TREE_TYPE(FnDecl),
- static_chain,
- CallingConv);
+FnDecl,
+static_chain,
+CallingConv);
}
// If we've already seen this function and created a prototype, and if the
@@ -2546,6 +2547,7 @@
unsigned CallingConv;
const Type *Ty = TheTypeConverter->ConvertFunctionType(function_type,
+ fndecl,
static_chain,
CallingConv);
Callee = CastToType(Instruction::BitCast, Callee, PointerType::get(Ty));
Modified: llvm-gcc-4.0/trunk/gcc/llvm-internal.h
URL:
http://llvm.org/viewvc/llvm-project/llvm-gcc-4.0/trunk/gcc/llvm-internal.h?rev=40622&r1=40621&r2=40622&view=diff
==
--- llvm-gcc-4.0/trunk/gcc/llvm-internal.h (original)
+++ llvm-gcc-4.0/trunk/gcc/llvm-internal.h Tue Jul 31 01:50:25 2007
@@ -139,6 +139,7 @@
/// tree to an LLVM type. This does the same thing that ConvertType does,
but
/// it also returns the function's LLVM calling convention.
const FunctionType *ConvertFunctionType(tree_node *type,
+ tree_node *decl,
tree_node *static_chain,
unsigned &CallingConv);
Modified: llvm-gcc-4.0/trunk/gcc/llvm-types.cpp
URL:
http://llvm.org/viewvc/llvm-project/llvm-gcc-4.0/trunk/gcc/llvm-types.cpp?rev=40622&r1=40621&r2=40622&view=diff
==
--- llvm-gcc-4.0/trunk/gcc/llvm-types.cpp (original)
+++ llvm-gcc-4.0/trunk/gcc/llvm-types.cpp Tue Jul 31 01:50:25 2007
@@ -785,7 +785,7 @@
return Ty;
unsigned CallingConv;
-return TypeDB.setType(type, ConvertFunctionType(type, NULL, CallingConv));
+return TypeDB.setType(type, ConvertFunctionType(type, orig_type, NULL,
CallingConv));
}
case ARRAY_TYPE: {
if (const Type *Ty = GET_TYPE_LLVM(type))
@@ -927,6 +927,7 @@
}
const FunctionType *TypeConverter::ConvertFunctionType(tree type,
+ tree decl,
tree static_chain,
unsigned &CallingConv) {
const Type *RetTy = 0;
@@ -979,6 +980,7 @@
// Loop over all of the arguments, adding them as we go.
tree Args = TYPE_ARG_TYPES(type);
+ tree DeclArgs = DECL_ARGUMENTS(decl);
for (; Args && TREE_VALUE(Args) != void_type_node; Args = TREE_CHAIN(Args)){
tree ArgTy = TREE_VALUE(Args);
if (!isPassedByInvisibleReference(ArgTy) &&
@@ -1012,8 +1014,11 @@
}
// Compute noalias attributes.
-if (TREE_CODE(ArgTy) == POINTER_TYPE || TREE_CODE(ArgTy) == REFERENCE_TYPE)
- if (TYPE_RESTRICT(ArgTy))
+tree RestrictArgTy = (DeclArgs) ? DeclArgs->type.common.type : ArgTy;
+Restric
