Author: evancheng
Date: Mon Jul 30 02:51:22 2007
New Revision: 40586
URL: http://llvm.org/viewvc/llvm-project?rev=40586&view=rev
Log:
Vector fneg must be expanded into fsub -0.0, X.
Modified:
llvm/trunk/lib/Target/PowerPC/PPCISelLowering.cpp
llvm/trunk/lib/Target/PowerPC/PPCISelLowering.h
llvm/trunk/lib/Target/PowerPC/PPCInstrAltivec.td
Modified: llvm/trunk/lib/Target/PowerPC/PPCISelLowering.cpp
URL:
http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PowerPC/PPCISelLowering.cpp?rev=40586&r1=40585&r2=40586&view=diff
==============================================================================
--- llvm/trunk/lib/Target/PowerPC/PPCISelLowering.cpp (original)
+++ llvm/trunk/lib/Target/PowerPC/PPCISelLowering.cpp Mon Jul 30 02:51:22 2007
@@ -259,6 +259,7 @@
setOperationAction(ISD::UDIV, (MVT::ValueType)VT, Expand);
setOperationAction(ISD::UREM, (MVT::ValueType)VT, Expand);
setOperationAction(ISD::FDIV, (MVT::ValueType)VT, Expand);
+ setOperationAction(ISD::FNEG, (MVT::ValueType)VT, Expand);
setOperationAction(ISD::EXTRACT_VECTOR_ELT, (MVT::ValueType)VT, Expand);
setOperationAction(ISD::INSERT_VECTOR_ELT, (MVT::ValueType)VT, Expand);
setOperationAction(ISD::BUILD_VECTOR, (MVT::ValueType)VT, Expand);
@@ -523,6 +524,16 @@
return true;
}
+/// isAllNegativeZeroVector - Returns true if all elements of build_vector
+/// are -0.0.
+bool PPC::isAllNegativeZeroVector(SDNode *N) {
+ assert(N->getOpcode() == ISD::BUILD_VECTOR);
+ if (PPC::isSplatShuffleMask(N, N->getNumOperands()))
+ if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(N))
+ return CFP->isExactlyValue(-0.0);
+ return false;
+}
+
/// getVSPLTImmediate - Return the appropriate VSPLT* immediate to splat the
/// specified isSplatShuffleMask VECTOR_SHUFFLE mask.
unsigned PPC::getVSPLTImmediate(SDNode *N, unsigned EltSize) {
Modified: llvm/trunk/lib/Target/PowerPC/PPCISelLowering.h
URL:
http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PowerPC/PPCISelLowering.h?rev=40586&r1=40585&r2=40586&view=diff
==============================================================================
--- llvm/trunk/lib/Target/PowerPC/PPCISelLowering.h (original)
+++ llvm/trunk/lib/Target/PowerPC/PPCISelLowering.h Mon Jul 30 02:51:22 2007
@@ -160,6 +160,10 @@
/// VSPLTB/VSPLTH/VSPLTW.
bool isSplatShuffleMask(SDNode *N, unsigned EltSize);
+ /// isAllNegativeZeroVector - Returns true if all elements of build_vector
+ /// are -0.0.
+ bool isAllNegativeZeroVector(SDNode *N);
+
/// getVSPLTImmediate - Return the appropriate VSPLT* immediate to splat
the
/// specified isSplatShuffleMask VECTOR_SHUFFLE mask.
unsigned getVSPLTImmediate(SDNode *N, unsigned EltSize);
Modified: llvm/trunk/lib/Target/PowerPC/PPCInstrAltivec.td
URL:
http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PowerPC/PPCInstrAltivec.td?rev=40586&r1=40585&r2=40586&view=diff
==============================================================================
--- llvm/trunk/lib/Target/PowerPC/PPCInstrAltivec.td (original)
+++ llvm/trunk/lib/Target/PowerPC/PPCInstrAltivec.td Mon Jul 30 02:51:22 2007
@@ -70,7 +70,6 @@
return PPC::isVMRGHShuffleMask(N, 4, true);
}]>;
-
def VSLDOI_get_imm : SDNodeXForm<build_vector, [{
return getI32Imm(PPC::isVSLDOIShuffleMask(N, false));
}]>;
@@ -133,6 +132,10 @@
return PPC::get_VSPLTI_elt(N, 4, *CurDAG).Val != 0;
}], VSPLTISW_get_imm>;
+def V_immneg0 : PatLeaf<(build_vector), [{
+ return PPC::isAllNegativeZeroVector(N);
+}]>;
+
//===----------------------------------------------------------------------===//
// Helpers for defining instructions that directly correspond to intrinsics.
@@ -228,7 +231,8 @@
Requires<[FPContractions]>;
def VNMSUBFP: VAForm_1<47, (outs VRRC:$vD), (ins VRRC:$vA, VRRC:$vC, VRRC:$vB),
"vnmsubfp $vD, $vA, $vC, $vB", VecFP,
- [(set VRRC:$vD, (fneg (fsub (fmul VRRC:$vA, VRRC:$vC),
+ [(set VRRC:$vD, (fsub V_immneg0,
+ (fsub (fmul VRRC:$vA, VRRC:$vC),
VRRC:$vB)))]>,
Requires<[FPContractions]>;
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