[llvm-commits] CVS: llvm/include/llvm/CodeGen/SelectionDAGNodes.h
Changes in directory llvm/include/llvm/CodeGen:
SelectionDAGNodes.h updated: 1.179 -> 1.180
---
Log message:
Add a utility function to test whether a load is unindexed.
---
Diffs of the changes: (+7 -0)
SelectionDAGNodes.h |7 +++
1 files changed, 7 insertions(+)
Index: llvm/include/llvm/CodeGen/SelectionDAGNodes.h
diff -u llvm/include/llvm/CodeGen/SelectionDAGNodes.h:1.179
llvm/include/llvm/CodeGen/SelectionDAGNodes.h:1.180
--- llvm/include/llvm/CodeGen/SelectionDAGNodes.h:1.179 Sun Mar 4 14:40:06 2007
+++ llvm/include/llvm/CodeGen/SelectionDAGNodes.h Wed Mar 7 02:04:41 2007
@@ -1620,6 +1620,13 @@
cast(N)->getExtensionType() == ISD::ZEXTLOAD;
}
+ /// isUNINDEXEDLoad - Returns true if the specified node is a unindexed load.
+ ///
+ inline bool isUNINDEXEDLoad(const SDNode *N) {
+return N->getOpcode() == ISD::LOAD &&
+ cast(N)->getAddressingMode() == ISD::UNINDEXED;
+ }
+
/// isNON_TRUNCStore - Returns true if the specified node is a non-truncating
/// store.
inline bool isNON_TRUNCStore(const SDNode *N) {
___
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[llvm-commits] CVS: llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
Changes in directory llvm/lib/CodeGen/SelectionDAG:
DAGCombiner.cpp updated: 1.274 -> 1.275
---
Log message:
Avoid combining indexed load further.
---
Diffs of the changes: (+14 -8)
DAGCombiner.cpp | 22 ++
1 files changed, 14 insertions(+), 8 deletions(-)
Index: llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
diff -u llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp:1.274
llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp:1.275
--- llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp:1.274 Sun Mar 4 14:40:38 2007
+++ llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp Wed Mar 7 02:07:03 2007
@@ -1245,7 +1245,7 @@
SimplifyDemandedBits(SDOperand(N, 0)))
return SDOperand(N, 0);
// fold (zext_inreg (extload x)) -> (zextload x)
- if (ISD::isEXTLoad(N0.Val)) {
+ if (ISD::isEXTLoad(N0.Val) && ISD::isUNINDEXEDLoad(N0.Val)) {
LoadSDNode *LN0 = cast(N0);
MVT::ValueType EVT = LN0->getLoadedVT();
// If we zero all the possible extended bits, then we can turn this into
@@ -1261,7 +1261,8 @@
}
}
// fold (zext_inreg (sextload x)) -> (zextload x) iff load has one use
- if (ISD::isSEXTLoad(N0.Val) && N0.hasOneUse()) {
+ if (ISD::isSEXTLoad(N0.Val) && ISD::isUNINDEXEDLoad(N0.Val) &&
+ N0.hasOneUse()) {
LoadSDNode *LN0 = cast(N0);
MVT::ValueType EVT = LN0->getLoadedVT();
// If we zero all the possible extended bits, then we can turn this into
@@ -1282,6 +1283,7 @@
if (N1C && N0.getOpcode() == ISD::LOAD) {
LoadSDNode *LN0 = cast(N0);
if (LN0->getExtensionType() != ISD::SEXTLOAD &&
+LN0->getAddressingMode() == ISD::UNINDEXED &&
N0.hasOneUse()) {
MVT::ValueType EVT, LoadedVT;
if (N1C->getValue() == 255)
@@ -2064,7 +2066,8 @@
// fold (sext (sextload x)) -> (sext (truncate (sextload x)))
// fold (sext ( extload x)) -> (sext (truncate (sextload x)))
- if ((ISD::isSEXTLoad(N0.Val) || ISD::isEXTLoad(N0.Val)) && N0.hasOneUse()) {
+ if ((ISD::isSEXTLoad(N0.Val) || ISD::isEXTLoad(N0.Val)) &&
+ ISD::isUNINDEXEDLoad(N0.Val) && N0.hasOneUse()) {
LoadSDNode *LN0 = cast(N0);
MVT::ValueType EVT = LN0->getLoadedVT();
if (!AfterLegalize || TLI.isLoadXLegal(ISD::SEXTLOAD, EVT)) {
@@ -2135,7 +2138,8 @@
// fold (zext (zextload x)) -> (zext (truncate (zextload x)))
// fold (zext ( extload x)) -> (zext (truncate (zextload x)))
- if ((ISD::isZEXTLoad(N0.Val) || ISD::isEXTLoad(N0.Val)) && N0.hasOneUse()) {
+ if ((ISD::isZEXTLoad(N0.Val) || ISD::isEXTLoad(N0.Val)) &&
+ ISD::isUNINDEXEDLoad(N0.Val) && N0.hasOneUse()) {
LoadSDNode *LN0 = cast(N0);
MVT::ValueType EVT = LN0->getLoadedVT();
SDOperand ExtLoad = DAG.getExtLoad(ISD::ZEXTLOAD, VT, LN0->getChain(),
@@ -2205,7 +2209,8 @@
// fold (aext (zextload x)) -> (aext (truncate (zextload x)))
// fold (aext (sextload x)) -> (aext (truncate (sextload x)))
// fold (aext ( extload x)) -> (aext (truncate (extload x)))
- if (N0.getOpcode() == ISD::LOAD && !ISD::isNON_EXTLoad(N0.Val) &&
+ if (N0.getOpcode() == ISD::LOAD &&
+ !ISD::isNON_EXTLoad(N0.Val) && ISD::isUNINDEXEDLoad(N0.Val) &&
N0.hasOneUse()) {
LoadSDNode *LN0 = cast(N0);
MVT::ValueType EVT = LN0->getLoadedVT();
@@ -2263,6 +2268,7 @@
// fold (sext_inreg (extload x)) -> (sextload x)
if (ISD::isEXTLoad(N0.Val) &&
+ ISD::isUNINDEXEDLoad(N0.Val) &&
EVT == cast(N0)->getLoadedVT() &&
(!AfterLegalize || TLI.isLoadXLegal(ISD::SEXTLOAD, EVT))) {
LoadSDNode *LN0 = cast(N0);
@@ -2274,7 +2280,8 @@
return SDOperand(N, 0); // Return N so it doesn't get rechecked!
}
// fold (sext_inreg (zextload x)) -> (sextload x) iff load has one use
- if (ISD::isZEXTLoad(N0.Val) && N0.hasOneUse() &&
+ if (ISD::isZEXTLoad(N0.Val) && ISD::isUNINDEXEDLoad(N0.Val) &&
+ N0.hasOneUse() &&
EVT == cast(N0)->getLoadedVT() &&
(!AfterLegalize || TLI.isLoadXLegal(ISD::SEXTLOAD, EVT))) {
LoadSDNode *LN0 = cast(N0);
@@ -2868,8 +2875,7 @@
if (LD->getAddressingMode() != ISD::UNINDEXED)
return false;
VT = LD->getLoadedVT();
-if (LD->getAddressingMode() != ISD::UNINDEXED &&
-!TLI.isIndexedLoadLegal(ISD::PRE_INC, VT) &&
+if (!TLI.isIndexedLoadLegal(ISD::PRE_INC, VT) &&
!TLI.isIndexedLoadLegal(ISD::PRE_DEC, VT))
return false;
Ptr = LD->getBasePtr();
___
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[llvm-commits] CVS: llvm/test/CodeGen/ARM/2007-03-07-CombinerCrash.ll
Changes in directory llvm/test/CodeGen/ARM:
2007-03-07-CombinerCrash.ll added (r1.1)
---
Log message:
New test case.
---
Diffs of the changes: (+21 -0)
2007-03-07-CombinerCrash.ll | 21 +
1 files changed, 21 insertions(+)
Index: llvm/test/CodeGen/ARM/2007-03-07-CombinerCrash.ll
diff -c /dev/null llvm/test/CodeGen/ARM/2007-03-07-CombinerCrash.ll:1.1
*** /dev/null Wed Mar 7 02:12:49 2007
--- llvm/test/CodeGen/ARM/2007-03-07-CombinerCrash.ll Wed Mar 7 02:12:39 2007
***
*** 0
--- 1,21
+ ; RUN: llvm-as < %s | llc -mtriple=arm-apple-darwin -mattr=+v6,+vfp2
+
+ define fastcc i8* @read_sleb128(i8* %p, i32* %val) {
+ br label %bb
+
+ bb:
+ %p_addr.0 = getelementptr i8* %p, i32 0
+ %tmp2 = load i8* %p_addr.0
+ %tmp4.rec = add i32 0, 1
+ %tmp4 = getelementptr i8* %p, i32 %tmp4.rec
+ %tmp56 = zext i8 %tmp2 to i32
+ %tmp7 = and i32 %tmp56, 127
+ %tmp9 = shl i32 %tmp7, 0
+ %tmp11 = or i32 %tmp9, 0
+ icmp slt i8 %tmp2, 0
+ br i1 %0, label %bb, label %cond_next28
+
+ cond_next28:
+ store i32 %tmp11, i32* %val
+ ret i8* %tmp4
+ }
___
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[llvm-commits] CVS: llvm/lib/CodeGen/DwarfWriter.cpp
Changes in directory llvm/lib/CodeGen:
DwarfWriter.cpp updated: 1.131 -> 1.132
---
Log message:
Cleanup: make SetCounter an instance variable
---
Diffs of the changes: (+26 -28)
DwarfWriter.cpp | 54 ++
1 files changed, 26 insertions(+), 28 deletions(-)
Index: llvm/lib/CodeGen/DwarfWriter.cpp
diff -u llvm/lib/CodeGen/DwarfWriter.cpp:1.131
llvm/lib/CodeGen/DwarfWriter.cpp:1.132
--- llvm/lib/CodeGen/DwarfWriter.cpp:1.131 Tue Mar 6 20:47:57 2007
+++ llvm/lib/CodeGen/DwarfWriter.cppWed Mar 7 02:25:02 2007
@@ -237,7 +237,7 @@
unsigned getOffset() const { return Offset; }
unsigned getSize() const { return Size; }
const std::vector &getChildren()const { return Children; }
- const std::vector &getValues() const { return Values; }
+ std::vector &getValues() { return Values; }
void setTag(unsigned Tag) { Abbrev.setTag(Tag); }
void setOffset(unsigned O) { Offset = O; }
void setSize(unsigned S) { Size = S; }
@@ -315,7 +315,7 @@
/// EmitValue - Emit value via the Dwarf writer.
///
- virtual void EmitValue(const DwarfDebug &DD, unsigned Form) const = 0;
+ virtual void EmitValue(DwarfDebug &DD, unsigned Form) = 0;
/// SizeOf - Return the size of a value in bytes.
///
@@ -365,7 +365,7 @@
/// EmitValue - Emit integer of appropriate size.
///
- virtual void EmitValue(const DwarfDebug &DD, unsigned Form) const;
+ virtual void EmitValue(DwarfDebug &DD, unsigned Form);
/// SizeOf - Determine size of integer value in bytes.
///
@@ -402,7 +402,7 @@
/// EmitValue - Emit string value.
///
- virtual void EmitValue(const DwarfDebug &DD, unsigned Form) const;
+ virtual void EmitValue(DwarfDebug &DD, unsigned Form);
/// SizeOf - Determine size of string value in bytes.
///
@@ -441,7 +441,7 @@
/// EmitValue - Emit label value.
///
- virtual void EmitValue(const DwarfDebug &DD, unsigned Form) const;
+ virtual void EmitValue(DwarfDebug &DD, unsigned Form);
/// SizeOf - Determine size of label value in bytes.
///
@@ -479,7 +479,7 @@
/// EmitValue - Emit label value.
///
- virtual void EmitValue(const DwarfDebug &DD, unsigned Form) const;
+ virtual void EmitValue(DwarfDebug &DD, unsigned Form);
/// SizeOf - Determine size of label value in bytes.
///
@@ -517,7 +517,7 @@
/// EmitValue - Emit delta value.
///
- virtual void EmitValue(const DwarfDebug &DD, unsigned Form) const;
+ virtual void EmitValue(DwarfDebug &DD, unsigned Form);
/// SizeOf - Determine size of delta value in bytes.
///
@@ -559,7 +559,7 @@
/// EmitValue - Emit debug information entry offset.
///
- virtual void EmitValue(const DwarfDebug &DD, unsigned Form) const;
+ virtual void EmitValue(DwarfDebug &DD, unsigned Form);
/// SizeOf - Determine size of debug information entry in bytes.
///
@@ -624,7 +624,7 @@
/// EmitValue - Emit block data.
///
- virtual void EmitValue(const DwarfDebug &DD, unsigned Form) const;
+ virtual void EmitValue(DwarfDebug &DD, unsigned Form);
/// SizeOf - Determine size of block data in bytes.
///
@@ -795,7 +795,8 @@
/// SubprogramCount - The running count of functions being compiled.
///
unsigned SubprogramCount;
-
+
+ unsigned SetCounter;
Dwarf(std::ostream &OS, AsmPrinter *A, const TargetAsmInfo *T)
: O(OS)
, Asm(A)
@@ -806,6 +807,7 @@
, MF(NULL)
, MMI(NULL)
, SubprogramCount(0)
+ , SetCounter(1)
{
}
@@ -873,17 +875,15 @@
/// assemblers do not behave with absolute expressions with data directives,
/// so there is an option (needsSet) to use an intermediary set expression.
void EmitDifference(DWLabel LabelHi, DWLabel LabelLo,
- bool IsSmall = false) const {
+ bool IsSmall = false) {
EmitDifference(LabelHi.Tag, LabelHi.Number,
LabelLo.Tag, LabelLo.Number,
IsSmall);
}
void EmitDifference(const char *TagHi, unsigned NumberHi,
const char *TagLo, unsigned NumberLo,
- bool IsSmall = false) const {
+ bool IsSmall = false) {
if (TAI->needsSet()) {
- static unsigned SetCounter = 1;
-
O << "\t.set\t";
PrintLabelName("set", SetCounter);
O << ",";
@@ -914,10 +914,8 @@
void EmitSectionOffset(const char* Label, const char* Section,
unsigned LabelNumber, unsigned SectionNumber,
- bool IsSmall = false) const {
+ bool IsSmall = false) {
if (TAI->needsSet()) {
- static unsigned SetCounter = 1;
-
O << "\t.set\t";
PrintLabelName("set", SetCounter);
O << ",";
@@ -1978,7 +1976,7 @@
/// EmitDIE - Recusively Emits a debug information entry.
[llvm-commits] CVS: llvm/lib/Target/ARM/ARMISelLowering.cpp
Changes in directory llvm/lib/Target/ARM: ARMISelLowering.cpp updated: 1.18 -> 1.19 --- Log message: Refactoring of formal parameter flags. Enable properly use of zext/sext/aext stuff. --- Diffs of the changes: (+1 -2) ARMISelLowering.cpp |3 +-- 1 files changed, 1 insertion(+), 2 deletions(-) Index: llvm/lib/Target/ARM/ARMISelLowering.cpp diff -u llvm/lib/Target/ARM/ARMISelLowering.cpp:1.18 llvm/lib/Target/ARM/ARMISelLowering.cpp:1.19 --- llvm/lib/Target/ARM/ARMISelLowering.cpp:1.18Tue Mar 6 02:12:33 2007 +++ llvm/lib/Target/ARM/ARMISelLowering.cpp Wed Mar 7 10:25:08 2007 @@ -27,7 +27,6 @@ #include "llvm/CodeGen/MachineFunction.h" #include "llvm/CodeGen/MachineInstrBuilder.h" #include "llvm/CodeGen/SelectionDAG.h" -#include "llvm/CodeGen/SelectionDAGISel.h" #include "llvm/CodeGen/SSARegMap.h" #include "llvm/Target/TargetOptions.h" #include "llvm/ADT/VectorExtras.h" @@ -347,7 +346,7 @@ NeededGPRs = 0; StackPad = 0; GPRPad = 0; - unsigned align = (Flags >> SDISelParamFlags::OrigAlignmentOffs); + unsigned align = (Flags >> ISD::ParamFlags::OrigAlignmentOffs); GPRPad = NumGPRs % ((align + 3)/4); StackPad = StackOffset % align; unsigned firstGPR = NumGPRs + GPRPad; ___ llvm-commits mailing list llvm-commits@cs.uiuc.edu http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
[llvm-commits] CVS: llvm/include/llvm/CodeGen/SelectionDAGISel.h SelectionDAGNodes.h
Changes in directory llvm/include/llvm/CodeGen:
SelectionDAGISel.h updated: 1.32 -> 1.33
SelectionDAGNodes.h updated: 1.180 -> 1.181
---
Log message:
Refactoring of formal parameter flags. Enable properly use of
zext/sext/aext stuff.
---
Diffs of the changes: (+17 -16)
SelectionDAGISel.h | 16 +---
SelectionDAGNodes.h | 17 -
2 files changed, 17 insertions(+), 16 deletions(-)
Index: llvm/include/llvm/CodeGen/SelectionDAGISel.h
diff -u llvm/include/llvm/CodeGen/SelectionDAGISel.h:1.32
llvm/include/llvm/CodeGen/SelectionDAGISel.h:1.33
--- llvm/include/llvm/CodeGen/SelectionDAGISel.h:1.32 Tue Mar 6 00:10:33 2007
+++ llvm/include/llvm/CodeGen/SelectionDAGISel.hWed Mar 7 10:25:08 2007
@@ -30,21 +30,7 @@
class TargetLowering;
class FunctionLoweringInfo;
class HazardRecognizer;
-
- namespace SDISelParamFlags {
-enum Flags {
- NoFlagSet = 0,
- Signed= 1<<0,
- SignedOffs= 0,
- InReg = 1<<1,
- InRegOffs = 1,
- StructReturn = 1<<2,
- StructReturnOffs = 2,
- OrigAlignment = 0x1F<<27,
- OrigAlignmentOffs = 27
-};
- }
-
+
/// SelectionDAGISel - This is the common base class used for
SelectionDAG-based
/// pattern-matching instruction selectors.
class SelectionDAGISel : public FunctionPass {
Index: llvm/include/llvm/CodeGen/SelectionDAGNodes.h
diff -u llvm/include/llvm/CodeGen/SelectionDAGNodes.h:1.180
llvm/include/llvm/CodeGen/SelectionDAGNodes.h:1.181
--- llvm/include/llvm/CodeGen/SelectionDAGNodes.h:1.180 Wed Mar 7 02:04:41 2007
+++ llvm/include/llvm/CodeGen/SelectionDAGNodes.h Wed Mar 7 10:25:08 2007
@@ -48,11 +48,26 @@
unsigned short NumVTs;
};
-
/// ISD namespace - This namespace contains an enum which represents all of the
/// SelectionDAG node types and value types.
///
namespace ISD {
+ namespace ParamFlags {
+ enum Flags {
+NoFlagSet = 0,
+ZExt = 1<<0, ///< Parameter should be zero extended
+ZExtOffs = 0,
+SExt = 1<<1, ///< Parameter should be sign extended
+SExtOffs = 1,
+InReg = 1<<2, ///< Parameter should be passed in register
+InRegOffs = 2,
+StructReturn = 1<<3, ///< Hidden struct-return pointer
+StructReturnOffs = 3,
+OrigAlignment = 0x1F<<27,
+OrigAlignmentOffs = 27
+ };
+ }
+
//======//
/// ISD::NodeType enum - This enum defines all of the operators valid in a
/// SelectionDAG.
___
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[llvm-commits] CVS: llvm/lib/Target/X86/X86ISelLowering.cpp
Changes in directory llvm/lib/Target/X86: X86ISelLowering.cpp updated: 1.363 -> 1.364 --- Log message: Refactoring of formal parameter flags. Enable properly use of zext/sext/aext stuff. --- Diffs of the changes: (+2 -12) X86ISelLowering.cpp | 14 ++ 1 files changed, 2 insertions(+), 12 deletions(-) Index: llvm/lib/Target/X86/X86ISelLowering.cpp diff -u llvm/lib/Target/X86/X86ISelLowering.cpp:1.363 llvm/lib/Target/X86/X86ISelLowering.cpp:1.364 --- llvm/lib/Target/X86/X86ISelLowering.cpp:1.363 Tue Mar 6 23:43:18 2007 +++ llvm/lib/Target/X86/X86ISelLowering.cpp Wed Mar 7 10:25:09 2007 @@ -29,7 +29,6 @@ #include "llvm/CodeGen/MachineFunction.h" #include "llvm/CodeGen/MachineInstrBuilder.h" #include "llvm/CodeGen/SelectionDAG.h" -#include "llvm/CodeGen/SelectionDAGISel.h" #include "llvm/CodeGen/SSARegMap.h" #include "llvm/Support/MathExtras.h" #include "llvm/Target/TargetOptions.h" @@ -677,7 +676,7 @@ // If this is an sret function, the return should pop the hidden pointer. if (NumArgs && (cast(Op.getOperand(3))->getValue() & - SDISelParamFlags::StructReturn)) + ISD::ParamFlags::StructReturn)) BytesToPopOnReturn = 4; BytesCallerReserves = StackSize; @@ -751,7 +750,7 @@ // If the first argument is an sret pointer, remember it. bool isSRet = NumOps && (cast(Op.getOperand(6))->getValue() & - SDISelParamFlags::StructReturn); + ISD::ParamFlags::StructReturn); if (!MemOpChains.empty()) Chain = DAG.getNode(ISD::TokenFactor, MVT::Other, @@ -3408,16 +3407,10 @@ TargetLowering::ArgListEntry Entry; Entry.Node = Op.getOperand(1); Entry.Ty = IntPtrTy; -Entry.isSigned = false; -Entry.isInReg = false; -Entry.isSRet = false; Args.push_back(Entry); // Extend the unsigned i8 argument to be an int value for the call. Entry.Node = DAG.getNode(ISD::ZERO_EXTEND, MVT::i32, Op.getOperand(2)); Entry.Ty = IntPtrTy; -Entry.isSigned = false; -Entry.isInReg = false; -Entry.isSRet = false; Args.push_back(Entry); Entry.Node = Op.getOperand(3); Args.push_back(Entry); @@ -3568,9 +3561,6 @@ TargetLowering::ArgListTy Args; TargetLowering::ArgListEntry Entry; Entry.Ty = getTargetData()->getIntPtrType(); -Entry.isSigned = false; -Entry.isInReg = false; -Entry.isSRet = false; Entry.Node = Op.getOperand(1); Args.push_back(Entry); Entry.Node = Op.getOperand(2); Args.push_back(Entry); Entry.Node = Op.getOperand(3); Args.push_back(Entry); ___ llvm-commits mailing list llvm-commits@cs.uiuc.edu http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
[llvm-commits] CVS: llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp SelectionDAGISel.cpp
Changes in directory llvm/lib/CodeGen/SelectionDAG:
LegalizeDAG.cpp updated: 1.483 -> 1.484
SelectionDAGISel.cpp updated: 1.381 -> 1.382
---
Log message:
Refactoring of formal parameter flags. Enable properly use of
zext/sext/aext stuff.
---
Diffs of the changes: (+31 -31)
LegalizeDAG.cpp | 11 ---
SelectionDAGISel.cpp | 51 +++
2 files changed, 31 insertions(+), 31 deletions(-)
Index: llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
diff -u llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp:1.483
llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp:1.484
--- llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp:1.483 Tue Mar 6 14:01:06 2007
+++ llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp Wed Mar 7 10:25:08 2007
@@ -2242,8 +2242,7 @@
const char *FnName = 0;
if (Node->getOpcode() == ISD::MEMSET) {
-Entry.Node = Tmp2; Entry.isSigned = false; Entry.Ty = IntPtrTy;
-Entry.isInReg = false; Entry.isSRet = false;
+Entry.Node = Tmp2; Entry.Ty = IntPtrTy;
Args.push_back(Entry);
// Extend the (previously legalized) ubyte argument to be an int value
// for the call.
@@ -2251,17 +2250,15 @@
Tmp3 = DAG.getNode(ISD::TRUNCATE, MVT::i32, Tmp3);
else
Tmp3 = DAG.getNode(ISD::ZERO_EXTEND, MVT::i32, Tmp3);
-Entry.Node = Tmp3; Entry.Ty = Type::Int32Ty; Entry.isSigned = true;
-Entry.isInReg = false; Entry.isSRet = false;
+Entry.Node = Tmp3; Entry.Ty = Type::Int32Ty; Entry.isSExt = true;
Args.push_back(Entry);
-Entry.Node = Tmp4; Entry.Ty = IntPtrTy; Entry.isSigned = false;
+Entry.Node = Tmp4; Entry.Ty = IntPtrTy; Entry.isSExt = false;
Args.push_back(Entry);
FnName = "memset";
} else if (Node->getOpcode() == ISD::MEMCPY ||
Node->getOpcode() == ISD::MEMMOVE) {
Entry.Ty = IntPtrTy;
-Entry.isSigned = false; Entry.isInReg = false; Entry.isSRet = false;
Entry.Node = Tmp2; Args.push_back(Entry);
Entry.Node = Tmp3; Args.push_back(Entry);
Entry.Node = Tmp4; Args.push_back(Entry);
@@ -4228,7 +4225,7 @@
MVT::ValueType ArgVT = Node->getOperand(i).getValueType();
const Type *ArgTy = MVT::getTypeForValueType(ArgVT);
Entry.Node = Node->getOperand(i); Entry.Ty = ArgTy;
-Entry.isSigned = isSigned; Entry.isInReg = false; Entry.isSRet = false;
+Entry.isSExt = isSigned;
Args.push_back(Entry);
}
SDOperand Callee = DAG.getExternalSymbol(Name, TLI.getPointerTy());
Index: llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
diff -u llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp:1.381
llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp:1.382
--- llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp:1.381Tue Mar 6
00:10:33 2007
+++ llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp Wed Mar 7 10:25:08 2007
@@ -2279,7 +2279,8 @@
Value *Arg = I.getOperand(i);
SDOperand ArgNode = getValue(Arg);
Entry.Node = ArgNode; Entry.Ty = Arg->getType();
-Entry.isSigned = FTy->paramHasAttr(i, FunctionType::SExtAttribute);
+Entry.isSExt = FTy->paramHasAttr(i, FunctionType::SExtAttribute);
+Entry.isZExt = FTy->paramHasAttr(i, FunctionType::ZExtAttribute);
Entry.isInReg = FTy->paramHasAttr(i, FunctionType::InRegAttribute);
Entry.isSRet = FTy->paramHasAttr(i, FunctionType::StructRetAttribute);
Args.push_back(Entry);
@@ -2983,9 +2984,6 @@
TargetLowering::ArgListEntry Entry;
Entry.Node = Src;
Entry.Ty = TLI.getTargetData()->getIntPtrType();
- Entry.isSigned = false;
- Entry.isInReg = false;
- Entry.isSRet = false;
Args.push_back(Entry);
std::pair Result =
@@ -3001,9 +2999,6 @@
TargetLowering::ArgListEntry Entry;
Entry.Node = getValue(I.getOperand(0));
Entry.Ty = TLI.getTargetData()->getIntPtrType();
- Entry.isSigned = false;
- Entry.isInReg = false;
- Entry.isSRet = false;
Args.push_back(Entry);
MVT::ValueType IntPtr = TLI.getPointerTy();
std::pair Result =
@@ -3099,21 +3094,21 @@
for (Function::arg_iterator I = F.arg_begin(), E = F.arg_end();
I != E; ++I, ++j) {
MVT::ValueType VT = getValueType(I->getType());
-unsigned Flags = SDISelParamFlags::NoFlagSet;
+unsigned Flags = ISD::ParamFlags::NoFlagSet;
unsigned OriginalAlignment =
getTargetData()->getABITypeAlignment(I->getType());
// FIXME: Distinguish between a formal with no [sz]ext attribute from one
// that is zero extended!
if (FTy->paramHasAttr(j, FunctionType::ZExtAttribute))
- Flags &= ~(SDISelParamFlags::Signed);
+ Flags &= ~(ISD::ParamFlags::SExt);
if (FTy->paramHasAttr(j, FunctionType::SExtAttribute))
- Flags |= SDISelParamFlags::Signed;
+ Flags |= ISD::ParamFlags::SExt;
if (FTy->paramHasAttr(j, FunctionType::InRegAttribute))
- Flags |= SDISelParamFlags::InReg;
+ Flags |= ISD::ParamFlags::InReg;
[llvm-commits] CVS: llvm/lib/Target/Sparc/SparcISelDAGToDAG.cpp
Changes in directory llvm/lib/Target/Sparc:
SparcISelDAGToDAG.cpp updated: 1.121 -> 1.122
---
Log message:
Refactoring of formal parameter flags. Enable properly use of
zext/sext/aext stuff.
---
Diffs of the changes: (+4 -2)
SparcISelDAGToDAG.cpp |6 --
1 files changed, 4 insertions(+), 2 deletions(-)
Index: llvm/lib/Target/Sparc/SparcISelDAGToDAG.cpp
diff -u llvm/lib/Target/Sparc/SparcISelDAGToDAG.cpp:1.121
llvm/lib/Target/Sparc/SparcISelDAGToDAG.cpp:1.122
--- llvm/lib/Target/Sparc/SparcISelDAGToDAG.cpp:1.121 Thu Feb 22 08:56:36 2007
+++ llvm/lib/Target/Sparc/SparcISelDAGToDAG.cpp Wed Mar 7 10:25:09 2007
@@ -516,9 +516,11 @@
case MVT::i16: {
// Promote the integer to 32-bits. If the input type is signed, use a
// sign extend, otherwise use a zero extend.
- ISD::NodeType ExtendKind = ISD::ZERO_EXTEND;
- if (Args[i].isSigned)
+ ISD::NodeType ExtendKind = ISD::ANY_EXTEND;
+ if (Args[i].isSExt)
ExtendKind = ISD::SIGN_EXTEND;
+ else if (Args[i].isZExt)
+ExtendKind = ISD::ZERO_EXTEND;
Val = DAG.getNode(ExtendKind, MVT::i32, Val);
// FALL THROUGH
}
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[llvm-commits] CVS: llvm/lib/Target/IA64/IA64ISelLowering.cpp
Changes in directory llvm/lib/Target/IA64:
IA64ISelLowering.cpp updated: 1.55 -> 1.56
---
Log message:
Refactoring of formal parameter flags. Enable properly use of
zext/sext/aext stuff.
---
Diffs of the changes: (+4 -2)
IA64ISelLowering.cpp |6 --
1 files changed, 4 insertions(+), 2 deletions(-)
Index: llvm/lib/Target/IA64/IA64ISelLowering.cpp
diff -u llvm/lib/Target/IA64/IA64ISelLowering.cpp:1.55
llvm/lib/Target/IA64/IA64ISelLowering.cpp:1.56
--- llvm/lib/Target/IA64/IA64ISelLowering.cpp:1.55 Thu Feb 22 08:56:36 2007
+++ llvm/lib/Target/IA64/IA64ISelLowering.cpp Wed Mar 7 10:25:09 2007
@@ -341,9 +341,11 @@
case MVT::i32: {
//promote to 64-bits, sign/zero extending based on type
//of the argument
-ISD::NodeType ExtendKind = ISD::ZERO_EXTEND;
-if (Args[i].isSigned)
+ISD::NodeType ExtendKind = ISD::ANY_EXTEND;
+if (Args[i].isSExt)
ExtendKind = ISD::SIGN_EXTEND;
+else if (Args[i].isZExt)
+ ExtendKind = ISD::ZERO_EXTEND;
Val = DAG.getNode(ExtendKind, MVT::i64, Val);
// XXX: fall through
}
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[llvm-commits] CVS: llvm/utils/TableGen/CallingConvEmitter.cpp
Changes in directory llvm/utils/TableGen:
CallingConvEmitter.cpp updated: 1.5 -> 1.6
---
Log message:
Refactoring of formal parameter flags. Enable properly use of
zext/sext/aext stuff.
---
Diffs of the changes: (+6 -2)
CallingConvEmitter.cpp |8 ++--
1 files changed, 6 insertions(+), 2 deletions(-)
Index: llvm/utils/TableGen/CallingConvEmitter.cpp
diff -u llvm/utils/TableGen/CallingConvEmitter.cpp:1.5
llvm/utils/TableGen/CallingConvEmitter.cpp:1.6
--- llvm/utils/TableGen/CallingConvEmitter.cpp:1.5 Tue Mar 6 02:12:33 2007
+++ llvm/utils/TableGen/CallingConvEmitter.cpp Wed Mar 7 10:25:09 2007
@@ -123,8 +123,12 @@
} else if (Action->isSubClassOf("CCPromoteToType")) {
Record *DestTy = Action->getValueAsDef("DestTy");
O << IndentStr << "LocVT = " << getEnumName(getValueType(DestTy))
<<";\n";
- O << IndentStr << "LocInfo = (ArgFlags & SDISelParamFlags::Signed) ? \n"
-<< IndentStr << IndentStr << "CCValAssign::SExt :
CCValAssign::ZExt;\n";
+ O << IndentStr << "if (ArgFlags & ISD::ParamFlags::SExt)\n"
+<< IndentStr << IndentStr << "LocInfo = CCValAssign::SExt;\n"
+<< IndentStr << "else if (ArgFlags & ISD::ParamFlags::ZExt)\n"
+<< IndentStr << IndentStr << "LocInfo = CCValAssign::ZExt;\n"
+<< IndentStr << "else\n"
+<< IndentStr << IndentStr << "LocInfo = CCValAssign::AExt;\n";
} else {
Action->dump();
throw "Unknown CCAction!";
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[llvm-commits] CVS: llvm/include/llvm/Target/TargetLowering.h
Changes in directory llvm/include/llvm/Target:
TargetLowering.h updated: 1.110 -> 1.111
---
Log message:
Refactoring of formal parameter flags. Enable properly use of
zext/sext/aext stuff.
---
Diffs of the changes: (+3 -2)
TargetLowering.h |5 +++--
1 files changed, 3 insertions(+), 2 deletions(-)
Index: llvm/include/llvm/Target/TargetLowering.h
diff -u llvm/include/llvm/Target/TargetLowering.h:1.110
llvm/include/llvm/Target/TargetLowering.h:1.111
--- llvm/include/llvm/Target/TargetLowering.h:1.110 Thu Feb 22 09:37:19 2007
+++ llvm/include/llvm/Target/TargetLowering.h Wed Mar 7 10:25:08 2007
@@ -765,11 +765,12 @@
struct ArgListEntry {
SDOperand Node;
const Type* Ty;
-bool isSigned;
+bool isSExt;
+bool isZExt;
bool isInReg;
bool isSRet;
-ArgListEntry():isSigned(false), isInReg(false), isSRet(false) { };
+ArgListEntry():isSExt(false), isZExt(false), isInReg(false), isSRet(false)
{ };
};
typedef std::vector ArgListTy;
virtual std::pair
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[llvm-commits] CVS: llvm/lib/Target/Alpha/AlphaISelLowering.cpp
Changes in directory llvm/lib/Target/Alpha: AlphaISelLowering.cpp updated: 1.83 -> 1.84 --- Log message: Refactoring of formal parameter flags. Enable properly use of zext/sext/aext stuff. --- Diffs of the changes: (+4 -2) AlphaISelLowering.cpp |6 -- 1 files changed, 4 insertions(+), 2 deletions(-) Index: llvm/lib/Target/Alpha/AlphaISelLowering.cpp diff -u llvm/lib/Target/Alpha/AlphaISelLowering.cpp:1.83 llvm/lib/Target/Alpha/AlphaISelLowering.cpp:1.84 --- llvm/lib/Target/Alpha/AlphaISelLowering.cpp:1.83Thu Feb 22 08:56:36 2007 +++ llvm/lib/Target/Alpha/AlphaISelLowering.cpp Wed Mar 7 10:25:08 2007 @@ -337,10 +337,12 @@ case MVT::i32: // Promote the integer to 64 bits. If the input type is signed use a // sign extend, otherwise use a zero extend. - if (Args[i].isSigned) + if (Args[i].isSExt) Args[i].Node = DAG.getNode(ISD::SIGN_EXTEND, MVT::i64, Args[i].Node); - else + else if (Args[i].isZExt) Args[i].Node = DAG.getNode(ISD::ZERO_EXTEND, MVT::i64, Args[i].Node); + else +Args[i].Node = DAG.getNode(ISD::ANY_EXTEND, MVT::i64, Args[i].Node); break; case MVT::i64: case MVT::f64: ___ llvm-commits mailing list llvm-commits@cs.uiuc.edu http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
[llvm-commits] CVS: llvm/lib/Target/TargetCallingConv.td
Changes in directory llvm/lib/Target:
TargetCallingConv.td updated: 1.4 -> 1.5
---
Log message:
Refactoring of formal parameter flags. Enable properly use of
zext/sext/aext stuff.
---
Diffs of the changes: (+1 -1)
TargetCallingConv.td |2 +-
1 files changed, 1 insertion(+), 1 deletion(-)
Index: llvm/lib/Target/TargetCallingConv.td
diff -u llvm/lib/Target/TargetCallingConv.td:1.4
llvm/lib/Target/TargetCallingConv.td:1.5
--- llvm/lib/Target/TargetCallingConv.td:1.4Tue Mar 6 02:12:33 2007
+++ llvm/lib/Target/TargetCallingConv.tdWed Mar 7 10:25:08 2007
@@ -38,7 +38,7 @@
/// CCIfInReg - If this argument is marked with the 'inreg' attribute, apply
/// the specified action.
-class CCIfInReg : CCIf<"ArgFlags & SDISelParamFlags::InReg", A> {}
+class CCIfInReg : CCIf<"ArgFlags & ISD::ParamFlags::InReg", A> {}
/// CCAssignToReg - This action matches if there is a register in the specified
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Re: [llvm-commits] CVS: llvm/lib/Target/Sparc/SparcISelDAGToDAG.cpp
> Refactoring of formal parameter flags. Enable properly use of
> zext/sext/aext stuff.
Thanks Anton!
-Chris
>
> ---
> Diffs of the changes: (+4 -2)
>
> SparcISelDAGToDAG.cpp |6 --
> 1 files changed, 4 insertions(+), 2 deletions(-)
>
>
> Index: llvm/lib/Target/Sparc/SparcISelDAGToDAG.cpp
> diff -u llvm/lib/Target/Sparc/SparcISelDAGToDAG.cpp:1.121 llvm/lib/
> Target/Sparc/SparcISelDAGToDAG.cpp:1.122
> --- llvm/lib/Target/Sparc/SparcISelDAGToDAG.cpp:1.121 Thu Feb 22
> 08:56:36 2007
> +++ llvm/lib/Target/Sparc/SparcISelDAGToDAG.cpp Wed Mar 7 10:25:09
> 2007
> @@ -516,9 +516,11 @@
> case MVT::i16: {
>// Promote the integer to 32-bits. If the input type is
> signed, use a
>// sign extend, otherwise use a zero extend.
> - ISD::NodeType ExtendKind = ISD::ZERO_EXTEND;
> - if (Args[i].isSigned)
> + ISD::NodeType ExtendKind = ISD::ANY_EXTEND;
> + if (Args[i].isSExt)
> ExtendKind = ISD::SIGN_EXTEND;
> + else if (Args[i].isZExt)
> +ExtendKind = ISD::ZERO_EXTEND;
>Val = DAG.getNode(ExtendKind, MVT::i32, Val);
>// FALL THROUGH
> }
>
>
>
> ___
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[llvm-commits] CVS: llvm/lib/Target/X86/X86InstrMMX.td
Changes in directory llvm/lib/Target/X86: X86InstrMMX.td updated: 1.16 -> 1.17 --- Log message: Remove useless pattern fragments. --- Diffs of the changes: (+0 -2) X86InstrMMX.td |2 -- 1 files changed, 2 deletions(-) Index: llvm/lib/Target/X86/X86InstrMMX.td diff -u llvm/lib/Target/X86/X86InstrMMX.td:1.16 llvm/lib/Target/X86/X86InstrMMX.td:1.17 --- llvm/lib/Target/X86/X86InstrMMX.td:1.16 Tue Mar 6 23:43:18 2007 +++ llvm/lib/Target/X86/X86InstrMMX.td Wed Mar 7 12:23:09 2007 @@ -42,8 +42,6 @@ // MMX Pattern Fragments //===--===// -def loadv8i8 : PatFrag<(ops node:$ptr), (v8i8 (load node:$ptr))>; -def loadv4i16 : PatFrag<(ops node:$ptr), (v4i16 (load node:$ptr))>; def loadv2i32 : PatFrag<(ops node:$ptr), (v2i32 (load node:$ptr))>; //===--===// ___ llvm-commits mailing list llvm-commits@cs.uiuc.edu http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
[llvm-commits] CVS: llvm/lib/Target/ARM/ARMLoadStoreOptimizer.cpp
Changes in directory llvm/lib/Target/ARM:
ARMLoadStoreOptimizer.cpp updated: 1.4 -> 1.5
---
Log message:
Only safe to use a call-clobbered or spilled callee-saved register as scratch
register.
---
Diffs of the changes: (+8 -2)
ARMLoadStoreOptimizer.cpp | 10 --
1 files changed, 8 insertions(+), 2 deletions(-)
Index: llvm/lib/Target/ARM/ARMLoadStoreOptimizer.cpp
diff -u llvm/lib/Target/ARM/ARMLoadStoreOptimizer.cpp:1.4
llvm/lib/Target/ARM/ARMLoadStoreOptimizer.cpp:1.5
--- llvm/lib/Target/ARM/ARMLoadStoreOptimizer.cpp:1.4 Tue Mar 6 20:38:05 2007
+++ llvm/lib/Target/ARM/ARMLoadStoreOptimizer.cpp Wed Mar 7 14:30:36 2007
@@ -15,6 +15,7 @@
#define DEBUG_TYPE "arm-ldst-opt"
#include "ARM.h"
#include "ARMAddressingModes.h"
+#include "ARMMachineFunctionInfo.h"
#include "ARMRegisterInfo.h"
#include "llvm/ADT/STLExtras.h"
#include "llvm/ADT/SmallVector.h"
@@ -39,6 +40,7 @@
struct VISIBILITY_HIDDEN ARMLoadStoreOpt : public MachineFunctionPass {
const TargetInstrInfo *TII;
const MRegisterInfo *MRI;
+ARMFunctionInfo *AFI;
RegScavenger *RS;
MachineBasicBlock::iterator RSI;
@@ -587,8 +589,11 @@
// First advance to the instruction just before the start of the chain.
if (RSI != MBB.begin())
RS->forward(prior(RSI));
-// Find a scratch register.
-Scratch = RS->FindUnusedReg(&ARM::GPRRegClass);
+// Find a scratch register. Make sure it's a call clobbered register or
+// a spilled callee-saved register.
+Scratch = RS->FindUnusedReg(&ARM::GPRRegClass, true);
+if (!Scratch)
+ RS->FindUnusedReg(&ARM::GPRRegClass, AFI->getSpilledCSRegisters());
// Process the load / store instructions.
RS->forward(prior(MBBI));
@@ -661,6 +666,7 @@
bool ARMLoadStoreOpt::runOnMachineFunction(MachineFunction &Fn) {
const TargetMachine &TM = Fn.getTarget();
+ AFI = Fn.getInfo();
TII = TM.getInstrInfo();
MRI = TM.getRegisterInfo();
RS = new RegScavenger();
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[llvm-commits] [see] CVS: llvm-poolalloc/lib/DSA/DataStructure.cpp
Changes in directory llvm-poolalloc/lib/DSA: DataStructure.cpp updated: 1.248.2.4.2.2 -> 1.248.2.4.2.3 --- Log message: Mark globals that are accessable to external functions incomplete. --- Diffs of the changes: (+3 -1) DataStructure.cpp |4 +++- 1 files changed, 3 insertions(+), 1 deletion(-) Index: llvm-poolalloc/lib/DSA/DataStructure.cpp diff -u llvm-poolalloc/lib/DSA/DataStructure.cpp:1.248.2.4.2.2 llvm-poolalloc/lib/DSA/DataStructure.cpp:1.248.2.4.2.3 --- llvm-poolalloc/lib/DSA/DataStructure.cpp:1.248.2.4.2.2 Tue Mar 6 16:44:38 2007 +++ llvm-poolalloc/lib/DSA/DataStructure.cppWed Mar 7 16:49:43 2007 @@ -1996,7 +1996,9 @@ for (DSScalarMap::global_iterator I = ScalarMap.global_begin(), E = ScalarMap.global_end(); I != E; ++I) if (GlobalVariable *GV = dyn_cast(*I)) - if (!GV->hasInitializer() ||// Always mark external globals incomp. + if (!GV->hasInitializer() || // Always mark external globals incomp. + GV->hasExternalLinkage() || + GV->hasExternalWeakLinkage() || (!GV->isConstant() && (Flags & DSGraph::IgnoreGlobals) == 0)) markIncompleteNode(ScalarMap[GV].getNode()); } ___ llvm-commits mailing list llvm-commits@cs.uiuc.edu http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
[llvm-commits] [see] CVS: llvm-poolalloc/lib/DSA/TopDownClosure.cpp
Changes in directory llvm-poolalloc/lib/DSA:
TopDownClosure.cpp updated: 1.92.2.1.2.1 -> 1.92.2.1.2.2
---
Log message:
It is possible that MetaPools may be added which have no DSNode.
Skip them properly.
---
Diffs of the changes: (+1 -1)
TopDownClosure.cpp |2 +-
1 files changed, 1 insertion(+), 1 deletion(-)
Index: llvm-poolalloc/lib/DSA/TopDownClosure.cpp
diff -u llvm-poolalloc/lib/DSA/TopDownClosure.cpp:1.92.2.1.2.1
llvm-poolalloc/lib/DSA/TopDownClosure.cpp:1.92.2.1.2.2
--- llvm-poolalloc/lib/DSA/TopDownClosure.cpp:1.92.2.1.2.1 Wed Feb 28
11:35:33 2007
+++ llvm-poolalloc/lib/DSA/TopDownClosure.cpp Wed Mar 7 16:53:59 2007
@@ -73,7 +73,7 @@
for (DSScalarMap::global_iterator I=GGSM.global_begin(), E=GGSM.global_end();
I != E; ++I) {
DSNode *N = GGSM.find(*I)->second.getNode();
-if (N->isIncomplete())
+if ((N) && (N->isIncomplete()))
markReachableFunctionsExternallyAccessible(N, Visited);
}
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[llvm-commits] [see] CVS: llvm-poolalloc/lib/DSA/Local.cpp
Changes in directory llvm-poolalloc/lib/DSA:
Local.cpp updated: 1.158.2.4.2.2 -> 1.158.2.4.2.3
---
Log message:
Nodes returned from llva_save_stackp() are now collapsed.
Ensure that all globals with a DSNode have a MetaPool.
Disabled debugging and random kernel hacks.
---
Diffs of the changes: (+56 -2)
Local.cpp | 58 --
1 files changed, 56 insertions(+), 2 deletions(-)
Index: llvm-poolalloc/lib/DSA/Local.cpp
diff -u llvm-poolalloc/lib/DSA/Local.cpp:1.158.2.4.2.2
llvm-poolalloc/lib/DSA/Local.cpp:1.158.2.4.2.3
--- llvm-poolalloc/lib/DSA/Local.cpp:1.158.2.4.2.2 Wed Feb 28 11:35:32 2007
+++ llvm-poolalloc/lib/DSA/Local.cppWed Mar 7 17:42:43 2007
@@ -386,7 +386,7 @@
void GraphBuilder::visitGetElementPtrInst(User &GEP) {
#ifdef LLVA_KERNEL
-#if 1
+#if 0
int debug = 0;
if (isa(GEP)) {
Instruction * IGEP = (Instruction *)(&GEP);
@@ -589,7 +589,7 @@
if (isPointerType(StoredTy))
Dest.addEdgeTo(getValueDest(*SI.getOperand(0)));
#ifdef LLVA_KERNEL
-#if 1
+#if 0
{
if (SI.getParent()->getParent()->getName() == "alloc_vfsmnt") {
DSNode * N = getValueDest(*SI.getOperand(1)).getNode();
@@ -1120,7 +1120,9 @@
} else {
Value *actualPD = *(CS.arg_begin());
if (!isa(actualPD)) {
+#if 0
std::cerr << "WARNING: Pool is not global. Function = " <<
CS.getCaller()->getName() << "\n";
+#endif
} else {
++GlobalPools;
}
@@ -1183,7 +1185,9 @@
} else {
Value *actualPD = *(CS.arg_begin());
if (!isa(actualPD)) {
+#if 0
std::cerr << "WARNING: Pool is not global. Function = " <<
CS.getCaller()->getName() << "\n";
+#endif
} else {
++GlobalPools;
}
@@ -1241,6 +1245,7 @@
N->setAllocaNodeMarker();
N->setUnknownNodeMarker();
N->setIncompleteMarker();
+ N->foldNodeCompletely();
//
// TODO:
@@ -1248,6 +1253,7 @@
// are ignored by our analysis.
//
#endif
+#if 0
} else if (F->getName() == "__generic_copy_from_user") {
if (CS.getCaller()->getName() == "kmem_cache_alloc")
return false;
@@ -1260,6 +1266,7 @@
return true;
#endif
}
+#endif
return false;
}
@@ -1291,7 +1298,9 @@
} else {
Value *actualPD = *(CS.arg_begin());
if (!isa(actualPD)) {
+#if 0
std::cerr << "WARNING: Pool is not global. Function = " <<
CS.getCaller()->getName() << "\n";
+#endif
} else {
++GlobalPools;
}
@@ -1377,7 +1386,9 @@
} else {
Value *actualPD = *(CS.arg_begin());
if (!isa(actualPD)) {
+#if 0
std::cerr << "WARNING: Pool is not global. Function = " <<
CS.getCaller()->getName() << "\n";
+#endif
} else {
++GlobalPools;
}
@@ -1702,6 +1713,49 @@
DEBUG(std::cerr << "Eliminating " << ECGlobals.size() << " EC Globals!\n");
ECGlobals.clear();
+#ifdef LLVA_KERNEL
+ //
+ // Scan through all the globals; if they have a DSNode but no MetaPool, give
+ // them a MetaPool.
+ //
+ const Type * VoidPtrType = PointerType::get(Type::SByteTy);
+ for (Module::global_iterator I = M.global_begin(), E = M.global_end();
+ I != E; ++I) {
+// Skip functions and externally declared variables
+if (!isa(I)) continue;
+if (I->isExternal()) continue;
+
+GlobalValue * GV = I;
+GlobalValue * GVL = GlobalsGraph->getScalarMap().getLeaderForGlobal(I);
+DSNode *Node = GlobalsGraph->getNodeForValue(GVL).getNode();
+
+// If this global happens to be a MetaPool, it will have no DSNode.
+// In that case, do not assign a MetaPool.
+if (!Node) continue;
+
+//
+// Add the MetaPool for the DSNode if it does not already have one.
+//
+if (GlobalsGraph->getPoolDescriptorsMap().count(Node) == 0) {
+ Value * TheMetaPool = 0;
+ TheMetaPool = new GlobalVariable(
+ /*type=*/ VoidPtrType,
+ /*isConstant=*/ false,
+ /*Linkage=*/
GlobalValue::InternalLinkage,
+ /*initializer=*/
Constant::getNullValue(VoidPtrType),
+ /*name=*/ "_metaPool_",
+ /*parent=*/ &M );
+
+ //
+ // Create the internal data structure for the MetaPool and associate the
+ // DSNode with it.
+ //
+ MetaPoolHandle* tmpvh = new MetaPoolHandle(new MetaPool(TheMetaPool),
NULL);
+ GlobalsGraph->getPoolDescriptorsMap()[Node] = tmpvh;
+}
+ }
+#endif
+
// Calculate all of the graphs...
for (Module::iterator I = M.begin(), E = M.end(); I != E; ++I)
if (!I->isExternal())
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[llvm-commits] CVS: llvm/lib/VMCore/Constants.cpp
Changes in directory llvm/lib/VMCore:
Constants.cpp updated: 1.226 -> 1.227
---
Log message:
Added ContainsRelocations() to check if a constant might only be resolvable at
load time.
---
Diffs of the changes: (+11 -0)
Constants.cpp | 11 +++
1 files changed, 11 insertions(+)
Index: llvm/lib/VMCore/Constants.cpp
diff -u llvm/lib/VMCore/Constants.cpp:1.226 llvm/lib/VMCore/Constants.cpp:1.227
--- llvm/lib/VMCore/Constants.cpp:1.226 Thu Mar 1 13:30:34 2007
+++ llvm/lib/VMCore/Constants.cpp Wed Mar 7 18:59:12 2007
@@ -90,6 +90,17 @@
}
}
+/// ContaintsRelocations - Return true if the constant value contains
+/// relocations which cannot be resolved at compile time.
+bool Constant::ContainsRelocations() const {
+ if (isa(this))
+return true;
+ for (unsigned i = 0, e = getNumOperands(); i != e; ++i)
+if (getOperand(i)->ContainsRelocations())
+ return true;
+ return false;
+}
+
// Static constructor to create a '0' constant of arbitrary type...
Constant *Constant::getNullValue(const Type *Ty) {
switch (Ty->getTypeID()) {
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[llvm-commits] CVS: llvm/include/llvm/Constant.h
Changes in directory llvm/include/llvm:
Constant.h updated: 1.34 -> 1.35
---
Log message:
Added ContainsRelocations() to check if a constant might only be resolvable at
load time.
---
Diffs of the changes: (+4 -0)
Constant.h |4
1 files changed, 4 insertions(+)
Index: llvm/include/llvm/Constant.h
diff -u llvm/include/llvm/Constant.h:1.34 llvm/include/llvm/Constant.h:1.35
--- llvm/include/llvm/Constant.h:1.34 Sun Feb 11 23:18:08 2007
+++ llvm/include/llvm/Constant.hWed Mar 7 18:59:12 2007
@@ -59,6 +59,10 @@
/// true for things like constant expressions that could divide by zero.
bool canTrap() const;
+ /// ContaintsRelocations - Return true if the constant value contains
+ /// relocations which cannot be resolved at compile time.
+ bool ContainsRelocations() const;
+
// Specialize get/setOperand for Constant's as their operands are always
// constants as well.
Constant *getOperand(unsigned i) {
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[llvm-commits] CVS: llvm/include/llvm/Target/TargetAsmInfo.h
Changes in directory llvm/include/llvm/Target:
TargetAsmInfo.h updated: 1.27 -> 1.28
---
Log message:
Add ReadOnlySection directive.
---
Diffs of the changes: (+9 -1)
TargetAsmInfo.h | 10 +-
1 files changed, 9 insertions(+), 1 deletion(-)
Index: llvm/include/llvm/Target/TargetAsmInfo.h
diff -u llvm/include/llvm/Target/TargetAsmInfo.h:1.27
llvm/include/llvm/Target/TargetAsmInfo.h:1.28
--- llvm/include/llvm/Target/TargetAsmInfo.h:1.27 Tue Mar 6 20:47:57 2007
+++ llvm/include/llvm/Target/TargetAsmInfo.hWed Mar 7 19:00:38 2007
@@ -203,7 +203,12 @@
const char *FourByteConstantSection;
const char *EightByteConstantSection;
const char *SixteenByteConstantSection;
-
+
+/// ReadOnlySection - This is the directive that is emitted to switch to a
+/// read-only section for constant data (e.g. data declared const,
+/// jump tables).
+const char *ReadOnlySection; // Defaults to NULL
+
//===--- Global Variable Emission Directives
--===//
/// GlobalDirective - This is the directive used to declare a global
entity.
@@ -474,6 +479,9 @@
const char *getSixteenByteConstantSection() const {
return SixteenByteConstantSection;
}
+const char *getReadOnlySection() const {
+ return ReadOnlySection;
+}
const char *getGlobalDirective() const {
return GlobalDirective;
}
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[llvm-commits] CVS: llvm/lib/Target/TargetAsmInfo.cpp
Changes in directory llvm/lib/Target: TargetAsmInfo.cpp updated: 1.20 -> 1.21 --- Log message: Add ReadOnlySection directive. --- Diffs of the changes: (+1 -0) TargetAsmInfo.cpp |1 + 1 files changed, 1 insertion(+) Index: llvm/lib/Target/TargetAsmInfo.cpp diff -u llvm/lib/Target/TargetAsmInfo.cpp:1.20 llvm/lib/Target/TargetAsmInfo.cpp:1.21 --- llvm/lib/Target/TargetAsmInfo.cpp:1.20 Tue Mar 6 20:47:57 2007 +++ llvm/lib/Target/TargetAsmInfo.cpp Wed Mar 7 19:00:38 2007 @@ -60,6 +60,7 @@ FourByteConstantSection(0), EightByteConstantSection(0), SixteenByteConstantSection(0), + ReadOnlySection(0), GlobalDirective(0), SetDirective(0), LCOMMDirective(0), ___ llvm-commits mailing list llvm-commits@cs.uiuc.edu http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
[llvm-commits] CVS: llvm/lib/Target/X86/X86AsmPrinter.cpp X86TargetAsmInfo.cpp
Changes in directory llvm/lib/Target/X86:
X86AsmPrinter.cpp updated: 1.235 -> 1.236
X86TargetAsmInfo.cpp updated: 1.33 -> 1.34
---
Log message:
Put constant data to .const, .const_data, .literal{4|8|16} sections.
---
Diffs of the changes: (+25 -2)
X86AsmPrinter.cpp| 25 +++--
X86TargetAsmInfo.cpp |2 ++
2 files changed, 25 insertions(+), 2 deletions(-)
Index: llvm/lib/Target/X86/X86AsmPrinter.cpp
diff -u llvm/lib/Target/X86/X86AsmPrinter.cpp:1.235
llvm/lib/Target/X86/X86AsmPrinter.cpp:1.236
--- llvm/lib/Target/X86/X86AsmPrinter.cpp:1.235 Thu Mar 1 10:29:22 2007
+++ llvm/lib/Target/X86/X86AsmPrinter.cpp Wed Mar 7 19:07:07 2007
@@ -145,7 +145,8 @@
std::string name = Mang->getValueName(I);
Constant *C = I->getInitializer();
-unsigned Size = TD->getTypeSize(C->getType());
+const Type *Type = C->getType();
+unsigned Size = TD->getTypeSize(Type);
unsigned Align = TD->getPreferredAlignmentLog(I);
if (I->hasHiddenVisibility())
@@ -250,8 +251,28 @@
} else {
if (C->isNullValue() && !NoZerosInBSS && TAI->getBSSSection())
SwitchToDataSection(TAI->getBSSSection(), I);
-else
+else if (!I->isConstant())
SwitchToDataSection(TAI->getDataSection(), I);
+else {
+ // Read-only data.
+ bool isIntFPLiteral = Type->isInteger() || Type->isFloatingPoint();
+ if (C->ContainsRelocations() && Subtarget->isTargetDarwin() &&
+ TM.getRelocationModel() != Reloc::Static)
+SwitchToDataSection("\t.const_data\n");
+ else if (isIntFPLiteral && Size == 4 &&
+ TAI->getFourByteConstantSection())
+SwitchToDataSection(TAI->getFourByteConstantSection(), I);
+ else if (isIntFPLiteral && Size == 8 &&
+ TAI->getEightByteConstantSection())
+SwitchToDataSection(TAI->getEightByteConstantSection(), I);
+ else if (isIntFPLiteral && Size == 16 &&
+ TAI->getSixteenByteConstantSection())
+SwitchToDataSection(TAI->getSixteenByteConstantSection(), I);
+ else if (TAI->getReadOnlySection())
+SwitchToDataSection(TAI->getReadOnlySection(), I);
+ else
+SwitchToDataSection(TAI->getDataSection(), I);
+}
}
break;
Index: llvm/lib/Target/X86/X86TargetAsmInfo.cpp
diff -u llvm/lib/Target/X86/X86TargetAsmInfo.cpp:1.33
llvm/lib/Target/X86/X86TargetAsmInfo.cpp:1.34
--- llvm/lib/Target/X86/X86TargetAsmInfo.cpp:1.33 Tue Mar 6 20:47:57 2007
+++ llvm/lib/Target/X86/X86TargetAsmInfo.cppWed Mar 7 19:07:07 2007
@@ -56,6 +56,7 @@
EightByteConstantSection = "\t.literal8\n";
if (Subtarget->is64Bit())
SixteenByteConstantSection = "\t.literal16\n";
+ReadOnlySection = "\t.const\n";
LCOMMDirective = "\t.lcomm\t";
COMMDirectiveTakesAlignment = false;
HasDotTypeDotSizeDirective = false;
@@ -103,6 +104,7 @@
// bool HasDotLoc; // Defaults to false.
// HasDotFile - True if target asm supports .file directives.
// bool HasDotFile; // Defaults to false.
+ReadOnlySection = "\t.section\t.rodata\n";
PrivateGlobalPrefix = ".L";
WeakRefDirective = "\t.weak\t";
DwarfRequiresFrameSection = false;
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[llvm-commits] CVS: llvm/lib/Target/PowerPC/PPCAsmPrinter.cpp PPCTargetAsmInfo.cpp
Changes in directory llvm/lib/Target/PowerPC:
PPCAsmPrinter.cpp updated: 1.235 -> 1.236
PPCTargetAsmInfo.cpp updated: 1.18 -> 1.19
---
Log message:
For Darwin, put constant data into .const, .const_data, .literal{4|8|16}
sections.
---
Diffs of the changes: (+27 -2)
PPCAsmPrinter.cpp| 26 --
PPCTargetAsmInfo.cpp |3 +++
2 files changed, 27 insertions(+), 2 deletions(-)
Index: llvm/lib/Target/PowerPC/PPCAsmPrinter.cpp
diff -u llvm/lib/Target/PowerPC/PPCAsmPrinter.cpp:1.235
llvm/lib/Target/PowerPC/PPCAsmPrinter.cpp:1.236
--- llvm/lib/Target/PowerPC/PPCAsmPrinter.cpp:1.235 Fri Mar 2 23:29:51 2007
+++ llvm/lib/Target/PowerPC/PPCAsmPrinter.cpp Wed Mar 7 19:25:25 2007
@@ -893,7 +893,8 @@
O << Directive << name << "\n";
Constant *C = I->getInitializer();
-unsigned Size = TD->getTypeSize(C->getType());
+const Type *Type = C->getType();
+unsigned Size = TD->getTypeSize(Type);
unsigned Align = TD->getPreferredAlignmentLog(I);
if (C->isNullValue() && /* FIXME: Verify correct */
@@ -937,7 +938,28 @@
}
}
-SwitchToDataSection("\t.data", I);
+if (!I->isConstant())
+ SwitchToDataSection(TAI->getDataSection(), I);
+else {
+ // Read-only data.
+ bool isIntFPLiteral = Type->isInteger() || Type->isFloatingPoint();
+ if (C->ContainsRelocations() &&
+ TM.getRelocationModel() != Reloc::Static)
+SwitchToDataSection("\t.const_data\n");
+ else if (isIntFPLiteral && Size == 4 &&
+ TAI->getFourByteConstantSection())
+SwitchToDataSection(TAI->getFourByteConstantSection(), I);
+ else if (isIntFPLiteral && Size == 8 &&
+ TAI->getEightByteConstantSection())
+SwitchToDataSection(TAI->getEightByteConstantSection(), I);
+ else if (isIntFPLiteral && Size == 16 &&
+ TAI->getSixteenByteConstantSection())
+SwitchToDataSection(TAI->getSixteenByteConstantSection(), I);
+ else if (TAI->getReadOnlySection())
+SwitchToDataSection(TAI->getReadOnlySection(), I);
+ else
+SwitchToDataSection(TAI->getDataSection(), I);
+}
break;
default:
cerr << "Unknown linkage type!";
Index: llvm/lib/Target/PowerPC/PPCTargetAsmInfo.cpp
diff -u llvm/lib/Target/PowerPC/PPCTargetAsmInfo.cpp:1.18
llvm/lib/Target/PowerPC/PPCTargetAsmInfo.cpp:1.19
--- llvm/lib/Target/PowerPC/PPCTargetAsmInfo.cpp:1.18 Wed Feb 21 16:43:40 2007
+++ llvm/lib/Target/PowerPC/PPCTargetAsmInfo.cppWed Mar 7 19:25:25 2007
@@ -57,6 +57,9 @@
JumpTableDataSection = ".const";
GlobalDirective = "\t.globl\t";
CStringSection = "\t.cstring";
+ FourByteConstantSection = "\t.literal4\n";
+ EightByteConstantSection = "\t.literal8\n";
+ ReadOnlySection = "\t.const\n";
if (TM.getRelocationModel() == Reloc::Static) {
StaticCtorsSection = ".constructor";
StaticDtorsSection = ".destructor";
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[llvm-commits] CVS: llvm/lib/Target/ARM/ARMAsmPrinter.cpp ARMTargetAsmInfo.cpp
Changes in directory llvm/lib/Target/ARM:
ARMAsmPrinter.cpp updated: 1.58 -> 1.59
ARMTargetAsmInfo.cpp updated: 1.12 -> 1.13
---
Log message:
For Darwin, put constant data into .const, .const_data, .literal{4|8|16}
sections.
---
Diffs of the changes: (+26 -2)
ARMAsmPrinter.cpp| 25 +++--
ARMTargetAsmInfo.cpp |3 +++
2 files changed, 26 insertions(+), 2 deletions(-)
Index: llvm/lib/Target/ARM/ARMAsmPrinter.cpp
diff -u llvm/lib/Target/ARM/ARMAsmPrinter.cpp:1.58
llvm/lib/Target/ARM/ARMAsmPrinter.cpp:1.59
--- llvm/lib/Target/ARM/ARMAsmPrinter.cpp:1.58 Thu Mar 1 00:05:39 2007
+++ llvm/lib/Target/ARM/ARMAsmPrinter.cpp Wed Mar 7 19:25:25 2007
@@ -743,7 +743,8 @@
std::string name = Mang->getValueName(I);
Constant *C = I->getInitializer();
-unsigned Size = TD->getTypeSize(C->getType());
+const Type *Type = C->getType();
+unsigned Size = TD->getTypeSize(Type);
unsigned Align = TD->getPreferredAlignmentLog(I);
if (I->hasHiddenVisibility())
@@ -829,8 +830,28 @@
} else {
if (C->isNullValue() && !NoZerosInBSS && TAI->getBSSSection())
SwitchToDataSection(TAI->getBSSSection(), I);
-else
+else if (!I->isConstant())
SwitchToDataSection(TAI->getDataSection(), I);
+else {
+ // Read-only data.
+ bool isIntFPLiteral = Type->isInteger() || Type->isFloatingPoint();
+ if (C->ContainsRelocations() && Subtarget->isTargetDarwin() &&
+ TM.getRelocationModel() != Reloc::Static)
+SwitchToDataSection("\t.const_data\n");
+ else if (isIntFPLiteral && Size == 4 &&
+ TAI->getFourByteConstantSection())
+SwitchToDataSection(TAI->getFourByteConstantSection(), I);
+ else if (isIntFPLiteral && Size == 8 &&
+ TAI->getEightByteConstantSection())
+SwitchToDataSection(TAI->getEightByteConstantSection(), I);
+ else if (isIntFPLiteral && Size == 16 &&
+ TAI->getSixteenByteConstantSection())
+SwitchToDataSection(TAI->getSixteenByteConstantSection(), I);
+ else if (TAI->getReadOnlySection())
+SwitchToDataSection(TAI->getReadOnlySection(), I);
+ else
+SwitchToDataSection(TAI->getDataSection(), I);
+}
}
break;
Index: llvm/lib/Target/ARM/ARMTargetAsmInfo.cpp
diff -u llvm/lib/Target/ARM/ARMTargetAsmInfo.cpp:1.12
llvm/lib/Target/ARM/ARMTargetAsmInfo.cpp:1.13
--- llvm/lib/Target/ARM/ARMTargetAsmInfo.cpp:1.12 Mon Mar 5 11:59:58 2007
+++ llvm/lib/Target/ARM/ARMTargetAsmInfo.cppWed Mar 7 19:25:25 2007
@@ -27,6 +27,9 @@
HiddenDirective = "\t.private_extern\t";
JumpTableDataSection = ".const";
CStringSection = "\t.cstring";
+FourByteConstantSection = "\t.literal4\n";
+EightByteConstantSection = "\t.literal8\n";
+ReadOnlySection = "\t.const\n";
HasDotTypeDotSizeDirective = false;
if (TM.getRelocationModel() == Reloc::Static) {
StaticCtorsSection = ".constructor";
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[llvm-commits] CVS: llvm/lib/Transforms/Scalar/InstructionCombining.cpp
Changes in directory llvm/lib/Transforms/Scalar:
InstructionCombining.cpp updated: 1.648 -> 1.649
---
Log message:
For PR1205: http://llvm.org/PR1205 :
Add a new ComputeMaskedBits function that is APIntified. We'll slowly
convert things over to use this version. When its all done, we'll remove
the existing version.
---
Diffs of the changes: (+206 -1)
InstructionCombining.cpp | 207 ++-
1 files changed, 206 insertions(+), 1 deletion(-)
Index: llvm/lib/Transforms/Scalar/InstructionCombining.cpp
diff -u llvm/lib/Transforms/Scalar/InstructionCombining.cpp:1.648
llvm/lib/Transforms/Scalar/InstructionCombining.cpp:1.649
--- llvm/lib/Transforms/Scalar/InstructionCombining.cpp:1.648 Mon Mar 5
17:36:13 2007
+++ llvm/lib/Transforms/Scalar/InstructionCombining.cpp Wed Mar 7 19:46:38 2007
@@ -568,9 +568,214 @@
/// ComputeMaskedBits - Determine which of the bits specified in Mask are
/// known to be either zero or one and return them in the KnownZero/KnownOne
+/// bit sets. This code only analyzes bits in Mask, in order to short-circuit
+/// processing.
+/// NOTE: we cannot consider 'undef' to be "IsZero" here. The problem is that
+/// we cannot optimize based on the assumption that it is zero without changing
+/// it to be an explicit zero. If we don't change it to zero, other code could
+/// optimized based on the contradictory assumption that it is non-zero.
+/// Because instcombine aggressively folds operations with undef args anyway,
+/// this won't lose us code quality.
+static void ComputeMaskedBits(Value *V, APInt Mask, APInt& KnownZero,
+ APInt& KnownOne, unsigned Depth = 0) {
+ uint32_t BitWidth = Mask.getBitWidth();
+ assert(KnownZero.getBitWidth() == BitWidth &&
+ KnownOne.getBitWidth() == BitWidth &&
+ "Mask, KnownOne and KnownZero should have same BitWidth");
+ if (ConstantInt *CI = dyn_cast(V)) {
+// We know all of the bits for a constant!
+APInt Tmp(CI->getValue());
+Tmp.zextOrTrunc(BitWidth);
+KnownOne = Tmp & Mask;
+KnownZero = ~KnownOne & Mask;
+return;
+ }
+
+ KnownZero.clear(); KnownOne.clear(); // Don't know anything.
+ if (Depth == 6 || Mask == 0)
+return; // Limit search depth.
+
+ Instruction *I = dyn_cast(V);
+ if (!I) return;
+
+ APInt KnownZero2(KnownZero), KnownOne2(KnownOne);
+ Mask &= APInt::getAllOnesValue(
+cast(V->getType())->getBitWidth()).zextOrTrunc(BitWidth);
+
+ switch (I->getOpcode()) {
+ case Instruction::And:
+// If either the LHS or the RHS are Zero, the result is zero.
+ComputeMaskedBits(I->getOperand(1), Mask, KnownZero, KnownOne, Depth+1);
+Mask &= ~KnownZero;
+ComputeMaskedBits(I->getOperand(0), Mask, KnownZero2, KnownOne2, Depth+1);
+assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
+assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?");
+
+// Output known-1 bits are only known if set in both the LHS & RHS.
+KnownOne &= KnownOne2;
+// Output known-0 are known to be clear if zero in either the LHS | RHS.
+KnownZero |= KnownZero2;
+return;
+ case Instruction::Or:
+ComputeMaskedBits(I->getOperand(1), Mask, KnownZero, KnownOne, Depth+1);
+Mask &= ~KnownOne;
+ComputeMaskedBits(I->getOperand(0), Mask, KnownZero2, KnownOne2, Depth+1);
+assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
+assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?");
+
+// Output known-0 bits are only known if clear in both the LHS & RHS.
+KnownZero &= KnownZero2;
+// Output known-1 are known to be set if set in either the LHS | RHS.
+KnownOne |= KnownOne2;
+return;
+ case Instruction::Xor: {
+ComputeMaskedBits(I->getOperand(1), Mask, KnownZero, KnownOne, Depth+1);
+ComputeMaskedBits(I->getOperand(0), Mask, KnownZero2, KnownOne2, Depth+1);
+assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
+assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?");
+
+// Output known-0 bits are known if clear or set in both the LHS & RHS.
+APInt KnownZeroOut = (KnownZero & KnownZero2) | (KnownOne & KnownOne2);
+// Output known-1 are known to be set if set in only one of the LHS, RHS.
+KnownOne = (KnownZero & KnownOne2) | (KnownOne & KnownZero2);
+KnownZero = KnownZeroOut;
+return;
+ }
+ case Instruction::Select:
+ComputeMaskedBits(I->getOperand(2), Mask, KnownZero, KnownOne, Depth+1);
+ComputeMaskedBits(I->getOperand(1), Mask, KnownZero2, KnownOne2, Depth+1);
+assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
+assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?");
+
+// Only known if known in both the LHS and RHS.
+KnownOne &= KnownOne2;
+KnownZero &= KnownZero2;
+return;
+ case Instruction::FPTrunc:
+ case Instructio
[llvm-commits] CVS: llvm/lib/Transforms/Scalar/InstructionCombining.cpp
Changes in directory llvm/lib/Transforms/Scalar:
InstructionCombining.cpp updated: 1.649 -> 1.650
---
Log message:
For PR1205: http://llvm.org/PR1205 :
Provide an APIntified version of MaskedValueIsZero. This will (temporarily)
cause a "defined but not used" message from the compiler. It will be used
in the next patch in this series.
Patch by Sheng Zhou.
---
Diffs of the changes: (+10 -0)
InstructionCombining.cpp | 10 ++
1 files changed, 10 insertions(+)
Index: llvm/lib/Transforms/Scalar/InstructionCombining.cpp
diff -u llvm/lib/Transforms/Scalar/InstructionCombining.cpp:1.649
llvm/lib/Transforms/Scalar/InstructionCombining.cpp:1.650
--- llvm/lib/Transforms/Scalar/InstructionCombining.cpp:1.649 Wed Mar 7
19:46:38 2007
+++ llvm/lib/Transforms/Scalar/InstructionCombining.cpp Wed Mar 7 19:52:58 2007
@@ -979,6 +979,16 @@
return (KnownZero & Mask) == Mask;
}
+/// MaskedValueIsZero - Return true if 'V & Mask' is known to be zero. We use
+/// this predicate to simplify operations downstream. Mask is known to be zero
+/// for bits that V cannot have.
+static bool MaskedValueIsZero(Value *V, const APInt& Mask, unsigned Depth = 0)
{
+ APInt KnownZero(Mask), KnownOne(Mask);
+ ComputeMaskedBits(V, Mask, KnownZero, KnownOne, Depth);
+ assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
+ return (KnownZero & Mask) == Mask;
+}
+
/// ShrinkDemandedConstant - Check to see if the specified operand of the
/// specified instruction is a constant integer. If so, check to see if there
/// are any bits set in the constant that are not demanded. If so, shrink the
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[llvm-commits] CVS: llvm/lib/Target/ARM/ARMLoadStoreOptimizer.cpp
Changes in directory llvm/lib/Target/ARM:
ARMLoadStoreOptimizer.cpp updated: 1.5 -> 1.6
---
Log message:
Bug fix. Not advancing the register scavenger iterator correctly.
---
Diffs of the changes: (+21 -8)
ARMLoadStoreOptimizer.cpp | 29 +
1 files changed, 21 insertions(+), 8 deletions(-)
Index: llvm/lib/Target/ARM/ARMLoadStoreOptimizer.cpp
diff -u llvm/lib/Target/ARM/ARMLoadStoreOptimizer.cpp:1.5
llvm/lib/Target/ARM/ARMLoadStoreOptimizer.cpp:1.6
--- llvm/lib/Target/ARM/ARMLoadStoreOptimizer.cpp:1.5 Wed Mar 7 14:30:36 2007
+++ llvm/lib/Target/ARM/ARMLoadStoreOptimizer.cpp Wed Mar 7 20:55:08 2007
@@ -42,7 +42,6 @@
const MRegisterInfo *MRI;
ARMFunctionInfo *AFI;
RegScavenger *RS;
-MachineBasicBlock::iterator RSI;
virtual bool runOnMachineFunction(MachineFunction &Fn);
@@ -67,6 +66,7 @@
int Opcode, unsigned Size, unsigned Scratch,
MemOpQueue &MemOps);
+void AdvanceRS(MachineBasicBlock &MBB, MemOpQueue &MemOps);
bool LoadStoreMultipleOpti(MachineBasicBlock &MBB);
bool MergeReturnIntoLDM(MachineBasicBlock &MBB);
};
@@ -492,6 +492,22 @@
return false;
}
+/// AdvanceRS - Advance register scavenger to just before the earliest memory
+/// op that is being merged.
+void ARMLoadStoreOpt::AdvanceRS(MachineBasicBlock &MBB, MemOpQueue &MemOps) {
+ MachineBasicBlock::iterator Loc = MemOps[0].MBBI;
+ unsigned Position = MemOps[0].Position;
+ for (unsigned i = 1, e = MemOps.size(); i != e; ++i) {
+if (MemOps[i].Position < Position) {
+ Position = MemOps[i].Position;
+ Loc = MemOps[i].MBBI;
+}
+ }
+
+ if (Loc != MBB.begin())
+RS->forward(prior(Loc));
+}
+
/// LoadStoreMultipleOpti - An optimization pass to turn multiple LDR / STR
/// ops of the same base and incrementing offset into LDM / STM ops.
bool ARMLoadStoreOpt::LoadStoreMultipleOpti(MachineBasicBlock &MBB) {
@@ -504,7 +520,6 @@
unsigned Position = 0;
RS->enterBasicBlock(&MBB);
- RSI = MBB.begin();
MachineBasicBlock::iterator MBBI = MBB.begin(), E = MBB.end();
while (MBBI != E) {
bool Advance = false;
@@ -585,15 +600,14 @@
if (TryMerge) {
if (NumMemOps > 1) {
// Try to find a free register to use as a new base in case it's
needed.
-unsigned Scratch = ARM::R12;
// First advance to the instruction just before the start of the chain.
-if (RSI != MBB.begin())
- RS->forward(prior(RSI));
+AdvanceRS(MBB, MemOps);
// Find a scratch register. Make sure it's a call clobbered register or
// a spilled callee-saved register.
-Scratch = RS->FindUnusedReg(&ARM::GPRRegClass, true);
+unsigned Scratch = RS->FindUnusedReg(&ARM::GPRRegClass, true);
if (!Scratch)
- RS->FindUnusedReg(&ARM::GPRRegClass, AFI->getSpilledCSRegisters());
+ Scratch = RS->FindUnusedReg(&ARM::GPRRegClass,
+ AFI->getSpilledCSRegisters());
// Process the load / store instructions.
RS->forward(prior(MBBI));
@@ -617,7 +631,6 @@
// RS may be pointing to an instruction that's deleted.
RS->skipTo(prior(MBBI));
-RSI = MBBI;
}
CurrBase = 0;
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[llvm-commits] CVS: llvm/lib/Target/ARM/ARMRegisterInfo.td
Changes in directory llvm/lib/Target/ARM:
ARMRegisterInfo.td updated: 1.14 -> 1.15
---
Log message:
Change register allocation order to Dale's suggestion.
---
Diffs of the changes: (+18 -14)
ARMRegisterInfo.td | 32 ++--
1 files changed, 18 insertions(+), 14 deletions(-)
Index: llvm/lib/Target/ARM/ARMRegisterInfo.td
diff -u llvm/lib/Target/ARM/ARMRegisterInfo.td:1.14
llvm/lib/Target/ARM/ARMRegisterInfo.td:1.15
--- llvm/lib/Target/ARM/ARMRegisterInfo.td:1.14 Tue Mar 6 20:46:23 2007
+++ llvm/lib/Target/ARM/ARMRegisterInfo.td Wed Mar 7 20:56:40 2007
@@ -99,30 +99,34 @@
// generate large stack offset. Make it available once we have register
// scavenging. Similarly r3 is reserved in Thumb mode for now.
let MethodBodies = [{
-// FP is R11, R9 is available, R12 is available.
+// FP is R11, R9 is available.
static const unsigned ARM_GPR_AO_1[] = {
ARM::R3, ARM::R2, ARM::R1, ARM::R0,
+ ARM::R12,ARM::LR,
ARM::R4, ARM::R5, ARM::R6, ARM::R7,
- ARM::R8, ARM::R9, ARM::R10,ARM::R12,
- ARM::LR, ARM::R11 };
-// FP is R11, R9 is not available, R12 is available.
+ ARM::R8, ARM::R9, ARM::R10,
+ ARM::R11 };
+// FP is R11, R9 is not available.
static const unsigned ARM_GPR_AO_2[] = {
ARM::R3, ARM::R2, ARM::R1, ARM::R0,
+ ARM::R12,ARM::LR,
ARM::R4, ARM::R5, ARM::R6, ARM::R7,
- ARM::R8, ARM::R10,ARM::R12,
- ARM::LR, ARM::R11 };
-// FP is R7, R9 is available, R12 is available.
+ ARM::R8, ARM::R10,
+ ARM::R11 };
+// FP is R7, R9 is available.
static const unsigned ARM_GPR_AO_3[] = {
ARM::R3, ARM::R2, ARM::R1, ARM::R0,
- ARM::R4, ARM::R5, ARM::R6, ARM::R8,
- ARM::R9, ARM::R10,ARM::R11,ARM::R12,
- ARM::LR, ARM::R7 };
-// FP is R7, R9 is not available, R12 is available.
+ ARM::R12,ARM::LR,
+ ARM::R4, ARM::R5, ARM::R6,
+ ARM::R8, ARM::R9, ARM::R10,ARM::R11,
+ ARM::R7 };
+// FP is R7, R9 is not available.
static const unsigned ARM_GPR_AO_4[] = {
ARM::R3, ARM::R2, ARM::R1, ARM::R0,
- ARM::R4, ARM::R5, ARM::R6, ARM::R8,
- ARM::R10,ARM::R11,ARM::R12,
- ARM::LR, ARM::R7 };
+ ARM::R12,ARM::LR,
+ ARM::R4, ARM::R5, ARM::R6,
+ ARM::R8, ARM::R10,ARM::R11,
+ ARM::R7 };
// FP is R7, only low registers available.
static const unsigned THUMB_GPR_AO[] = {
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Re: [llvm-commits] CVS: llvm/lib/Target/X86/X86AsmPrinter.cpp X86TargetAsmInfo.cpp
> + // Read-only data.
> + bool isIntFPLiteral = Type->isInteger() || Type-
> >isFloatingPoint();
> + if (C->ContainsRelocations() && Subtarget->isTargetDarwin
> () &&
> + TM.getRelocationModel() != Reloc::Static)
Please rearrange this to:
if (isdarwin && not static && containsrelocations)
putting the expensive check last.
> +SwitchToDataSection("\t.const_data\n");
> + else if (isIntFPLiteral && Size == 4 &&
> + TAI->getFourByteConstantSection())
> +SwitchToDataSection(TAI->getFourByteConstantSection(),
> I);
> + else if (isIntFPLiteral && Size == 8 &&
> + TAI->getEightByteConstantSection())
> +SwitchToDataSection(TAI->getEightByteConstantSection
> (), I);
> + else if (isIntFPLiteral && Size == 16 &&
> + TAI->getSixteenByteConstantSection())
> +SwitchToDataSection(TAI->getSixteenByteConstantSection
> (), I);
Do we really need to check isIntFPLiteral here? Why can't something
like {short,short} go in literal4 ?
-Chris
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[llvm-commits] CVS: llvm/lib/Transforms/Scalar/InstructionCombining.cpp
Changes in directory llvm/lib/Transforms/Scalar:
InstructionCombining.cpp updated: 1.650 -> 1.651
---
Log message:
Fix a bug in APIntified ComputeMaskedBits().
---
Diffs of the changes: (+4 -8)
InstructionCombining.cpp | 12
1 files changed, 4 insertions(+), 8 deletions(-)
Index: llvm/lib/Transforms/Scalar/InstructionCombining.cpp
diff -u llvm/lib/Transforms/Scalar/InstructionCombining.cpp:1.650
llvm/lib/Transforms/Scalar/InstructionCombining.cpp:1.651
--- llvm/lib/Transforms/Scalar/InstructionCombining.cpp:1.650 Wed Mar 7
19:52:58 2007
+++ llvm/lib/Transforms/Scalar/InstructionCombining.cpp Wed Mar 7 23:42:00 2007
@@ -675,11 +675,9 @@
case Instruction::ZExt: {
// Compute the bits in the result that are not present in the input.
const IntegerType *SrcTy = cast(I->getOperand(0)->getType());
-APInt NotIn(~SrcTy->getMask());
-APInt NewBits = APInt::getAllOnesValue(BitWidth) &
-NotIn.zext(BitWidth);
+APInt NewBits(APInt::getAllOnesValue(BitWidth).shl(SrcTy->getBitWidth()));
-Mask &= ~NotIn;
+Mask &= SrcTy->getMask().zext(BitWidth);
ComputeMaskedBits(I->getOperand(0), Mask, KnownZero, KnownOne, Depth+1);
assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
// The top bits are known to be zero.
@@ -689,11 +687,9 @@
case Instruction::SExt: {
// Compute the bits in the result that are not present in the input.
const IntegerType *SrcTy = cast(I->getOperand(0)->getType());
-APInt NotIn(~SrcTy->getMask());
-APInt NewBits = APInt::getAllOnesValue(BitWidth) &
-NotIn.zext(BitWidth);
+APInt NewBits(APInt::getAllOnesValue(BitWidth).shl(SrcTy->getBitWidth()));
-Mask &= ~NotIn;
+Mask &= SrcTy->getMask().zext(BitWidth);
ComputeMaskedBits(I->getOperand(0), Mask, KnownZero, KnownOne, Depth+1);
assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
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[llvm-commits] CVS: llvm/lib/Transforms/Scalar/ScalarReplAggregates.cpp
Changes in directory llvm/lib/Transforms/Scalar:
ScalarReplAggregates.cpp updated: 1.76 -> 1.77
---
Log message:
Second half of PR1226: http://llvm.org/PR1226 . This is currently still
disabled, until I have a chance to
do the correctness/performance analysis testing.
---
Diffs of the changes: (+67 -9)
ScalarReplAggregates.cpp | 76 +--
1 files changed, 67 insertions(+), 9 deletions(-)
Index: llvm/lib/Transforms/Scalar/ScalarReplAggregates.cpp
diff -u llvm/lib/Transforms/Scalar/ScalarReplAggregates.cpp:1.76
llvm/lib/Transforms/Scalar/ScalarReplAggregates.cpp:1.77
--- llvm/lib/Transforms/Scalar/ScalarReplAggregates.cpp:1.76Mon Mar 5
01:52:57 2007
+++ llvm/lib/Transforms/Scalar/ScalarReplAggregates.cpp Thu Mar 8 00:36:54 2007
@@ -460,20 +460,77 @@
ConstantInt::get(Type::Int32Ty, i),
OtherPtr->getNameStr()+"."+utostr(i),
MI);
-if (OtherElt->getType() != BytePtrTy)
- OtherElt = new BitCastInst(OtherElt,
BytePtrTy,OtherElt->getNameStr(),
- MI);
}
Value *EltPtr = NewElts[i];
- unsigned EltSize =
-TD.getTypeSize(cast(EltPtr->getType())->getElementType());
+ const Type *EltTy
=cast(EltPtr->getType())->getElementType();
+
+ // If we got down to a scalar, insert a load or store as appropriate.
+ if (EltTy->isFirstClassType()) {
+if (isa(MI) || isa(MI)) {
+ Value *Elt = new LoadInst(SROADest ? OtherElt : EltPtr, "tmp",
+MI);
+ new StoreInst(Elt, SROADest ? EltPtr : OtherElt, MI);
+ continue;
+} else {
+ assert(isa(MI));
+
+ // If the stored element is zero (common case), just store a null
+ // constant.
+ Constant *StoreVal;
+ if (ConstantInt *CI = dyn_cast(MI->getOperand(2))) {
+if (CI->isZero()) {
+ StoreVal = Constant::getNullValue(EltTy); // 0.0, null, 0, <0,0>
+} else {
+ // If EltTy is a packed type, get the element type.
+ const Type *ValTy = EltTy;
+ if (const VectorType *VTy = dyn_cast(ValTy))
+ValTy = VTy->getElementType();
+
+ // Construct an integer with the right value.
+ unsigned EltSize = TD.getTypeSize(ValTy);
+ APInt OneVal(EltSize*8, CI->getZExtValue());
+ APInt TotalVal(OneVal);
+ // Set each byte.
+ for (unsigned i = 0; i != EltSize-1; ++i) {
+TotalVal = TotalVal.shl(8);
+TotalVal |= OneVal;
+ }
+
+ // Convert the integer value to the appropriate type.
+ StoreVal = ConstantInt::get(TotalVal);
+ if (isa(ValTy))
+StoreVal = ConstantExpr::getIntToPtr(StoreVal, ValTy);
+ else if (ValTy->isFloatingPoint())
+StoreVal = ConstantExpr::getBitCast(StoreVal, ValTy);
+ assert(StoreVal->getType() == ValTy && "Type mismatch!");
+
+ // If the requested value was a vector constant, create it.
+ if (EltTy != ValTy) {
+unsigned NumElts = cast(ValTy)->getNumElements();
+SmallVector Elts(NumElts, StoreVal);
+StoreVal = ConstantVector::get(&Elts[0], NumElts);
+ }
+}
+new StoreInst(StoreVal, EltPtr, MI);
+continue;
+ }
+ // Otherwise, if we're storing a byte variable, use a memset call for
+ // this element.
+}
+ }
// Cast the element pointer to BytePtrTy.
if (EltPtr->getType() != BytePtrTy)
EltPtr = new BitCastInst(EltPtr, BytePtrTy, EltPtr->getNameStr(), MI);
-
-
+
+ // Cast the other pointer (if we have one) to BytePtrTy.
+ if (OtherElt && OtherElt->getType() != BytePtrTy)
+OtherElt = new BitCastInst(OtherElt, BytePtrTy,OtherElt->getNameStr(),
+ MI);
+
+ unsigned EltSize = TD.getTypeSize(EltTy);
+
// Finally, insert the meminst for this element.
if (isa(MI) || isa(MI)) {
Value *Ops[] = {
@@ -483,7 +540,8 @@
Zero // Align
};
new CallInst(TheFn, Ops, 4, "", MI);
- } else if (isa(MI)) {
+ } else {
+assert(isa(MI));
Value *Ops[] = {
EltPtr, MI->getOperand(2), // Dest, Value,
ConstantInt::get(MI->getOperand(3)->getType(), EltSize), // Size
@@ -491,7 +549,7 @@
};
new CallInst(TheFn, Ops, 4, "", MI);
}
- }
+}
// Finally, MI is now dead, as we've modified its actions to occur on all
of
// the elements of the aggregate.
_
[llvm-commits] CVS: llvm/lib/Transforms/Scalar/ScalarReplAggregates.cpp
Changes in directory llvm/lib/Transforms/Scalar:
ScalarReplAggregates.cpp updated: 1.77 -> 1.78
---
Log message:
This appears correct, enable it so we can see perf changes on testers
---
Diffs of the changes: (+1 -1)
ScalarReplAggregates.cpp |2 +-
1 files changed, 1 insertion(+), 1 deletion(-)
Index: llvm/lib/Transforms/Scalar/ScalarReplAggregates.cpp
diff -u llvm/lib/Transforms/Scalar/ScalarReplAggregates.cpp:1.77
llvm/lib/Transforms/Scalar/ScalarReplAggregates.cpp:1.78
--- llvm/lib/Transforms/Scalar/ScalarReplAggregates.cpp:1.77Thu Mar 8
00:36:54 2007
+++ llvm/lib/Transforms/Scalar/ScalarReplAggregates.cpp Thu Mar 8 01:03:55 2007
@@ -303,7 +303,7 @@
///
int SROA::isSafeUseOfAllocation(Instruction *User, AllocationInst *AI) {
if (BitCastInst *C = dyn_cast(User))
-return 0 && (isSafeUseOfBitCastedAllocation(C, AI) ? 3 : 0);
+return isSafeUseOfBitCastedAllocation(C, AI) ? 3 : 0;
if (!isa(User)) return 0;
GetElementPtrInst *GEPI = cast(User);
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[llvm-commits] CVS: llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
Changes in directory llvm/lib/CodeGen/SelectionDAG:
SelectionDAGISel.cpp updated: 1.382 -> 1.383
---
Log message:
make this fail even in non-assert builds.
---
Diffs of the changes: (+4 -2)
SelectionDAGISel.cpp |6 --
1 files changed, 4 insertions(+), 2 deletions(-)
Index: llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
diff -u llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp:1.382
llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp:1.383
--- llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp:1.382Wed Mar 7
10:25:08 2007
+++ llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp Thu Mar 8 01:07:03 2007
@@ -2883,8 +2883,10 @@
// Memory input.
// Check that the operand isn't a float.
-if (!MVT::isInteger(InOperandVal.getValueType()))
- assert(0 && "MATCH FAIL!");
+if (!MVT::isInteger(InOperandVal.getValueType())) {
+ cerr << "Match failed, can't handle floats yet!\n";
+ exit(1);
+}
// Extend/truncate to the right pointer type if needed.
MVT::ValueType PtrType = TLI.getPointerTy();
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Re: [llvm-commits] CVS: llvm/lib/Target/X86/X86AsmPrinter.cpp X86TargetAsmInfo.cpp
On Mar 7, 2007, at 9:15 PM, Chris Lattner wrote:
>> + // Read-only data.
>> + bool isIntFPLiteral = Type->isInteger() || Type-
>> >isFloatingPoint();
>> + if (C->ContainsRelocations() && Subtarget-
>> >isTargetDarwin() &&
>> + TM.getRelocationModel() != Reloc::Static)
>
> Please rearrange this to:
> if (isdarwin && not static && containsrelocations)
>
> putting the expensive check last.
>
>> +SwitchToDataSection("\t.const_data\n");
>> + else if (isIntFPLiteral && Size == 4 &&
>> + TAI->getFourByteConstantSection())
>> +SwitchToDataSection(TAI->getFourByteConstantSection
>> (), I);
>> + else if (isIntFPLiteral && Size == 8 &&
>> + TAI->getEightByteConstantSection())
>> +SwitchToDataSection(TAI->getEightByteConstantSection
>> (), I);
>> + else if (isIntFPLiteral && Size == 16 &&
>> + TAI->getSixteenByteConstantSection())
>> +SwitchToDataSection(TAI->getSixteenByteConstantSection
>> (), I);
>
> Do we really need to check isIntFPLiteral here? Why can't
> something like {short,short} go in literal4 ?
We don't. But ContainsRelocations has to be checked first. We can't
use FourByteConstantSection, etc. if the constant has relocations.
Evan
>
> -Chris
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Re: [llvm-commits] CVS: llvm/lib/Target/X86/X86AsmPrinter.cpp X86TargetAsmInfo.cpp
On Mar 7, 2007, at 11:22 PM, Evan Cheng wrote:
>
> On Mar 7, 2007, at 9:15 PM, Chris Lattner wrote:
>
>>> + // Read-only data.
>>> + bool isIntFPLiteral = Type->isInteger() || Type-
>>> >isFloatingPoint();
>>> + if (C->ContainsRelocations() && Subtarget-
>>> >isTargetDarwin() &&
>>> + TM.getRelocationModel() != Reloc::Static)
>>
>> Please rearrange this to:
>> if (isdarwin && not static && containsrelocations)
>>
>> putting the expensive check last.
>>
>>> +SwitchToDataSection("\t.const_data\n");
>>> + else if (isIntFPLiteral && Size == 4 &&
>>> + TAI->getFourByteConstantSection())
>>> +SwitchToDataSection(TAI->getFourByteConstantSection
>>> (), I);
>>> + else if (isIntFPLiteral && Size == 8 &&
>>> + TAI->getEightByteConstantSection())
>>> +SwitchToDataSection(TAI->getEightByteConstantSection
>>> (), I);
>>> + else if (isIntFPLiteral && Size == 16 &&
>>> + TAI->getSixteenByteConstantSection())
>>> +SwitchToDataSection(TAI-
>>> >getSixteenByteConstantSection(), I);
>>
>> Do we really need to check isIntFPLiteral here? Why can't
>> something like {short,short} go in literal4 ?
>
> We don't. But ContainsRelocations has to be checked first. We can't
> use FourByteConstantSection, etc. if the constant has relocations.
Ah, ok, so instead of "isIntFPLiteral", you really mean "!contains
relocations"
-Chris
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