[llvm-commits] CVS: llvm/lib/VMCore/Constants.cpp Dominators.cpp SymbolTable.cpp Type.cpp Value.cpp ValueSymbolTable.cpp
Changes in directory llvm/lib/VMCore:
Constants.cpp updated: 1.170 -> 1.171
Dominators.cpp updated: 1.77 -> 1.78
SymbolTable.cpp updated: 1.62 -> 1.63
Type.cpp updated: 1.149 -> 1.150
Value.cpp updated: 1.58 -> 1.59
ValueSymbolTable.cpp updated: 1.2 -> 1.3
---
Log message:
Removed iostream #includes. Replaced std::cerr with DOUT.
---
Diffs of the changes: (+71 -74)
Constants.cpp| 12 +-
Dominators.cpp |1
SymbolTable.cpp | 58 +--
Type.cpp | 47 -
Value.cpp|8 +++
ValueSymbolTable.cpp | 19 +++-
6 files changed, 71 insertions(+), 74 deletions(-)
Index: llvm/lib/VMCore/Constants.cpp
diff -u llvm/lib/VMCore/Constants.cpp:1.170 llvm/lib/VMCore/Constants.cpp:1.171
--- llvm/lib/VMCore/Constants.cpp:1.170 Wed Nov 8 00:47:33 2006
+++ llvm/lib/VMCore/Constants.cpp Fri Nov 17 02:03:48 2006
@@ -19,11 +19,11 @@
#include "llvm/SymbolTable.h"
#include "llvm/Module.h"
#include "llvm/ADT/StringExtras.h"
-#include "llvm/Support/MathExtras.h"
#include "llvm/Support/Compiler.h"
+#include "llvm/Support/Debug.h"
#include "llvm/Support/ManagedStatic.h"
+#include "llvm/Support/MathExtras.h"
#include
-#include
using namespace llvm;
//===--===//
@@ -42,9 +42,9 @@
Value *V = use_back();
#ifndef NDEBUG // Only in -g mode...
if (!isa(V))
- std::cerr << "While deleting: " << *this
-<< "\n\nUse still stuck around after Def is destroyed: "
-<< *V << "\n\n";
+ DOUT << "While deleting: " << *this
+ << "\n\nUse still stuck around after Def is destroyed: "
+ << *V << "\n\n";
#endif
assert(isa(V) && "References remain to Constant being
destroyed");
Constant *CV = cast(V);
@@ -870,7 +870,7 @@
}
void dump() const {
- std::cerr << "Constant.cpp: ValueMap\n";
+ DOUT << "Constant.cpp: ValueMap\n";
}
};
}
Index: llvm/lib/VMCore/Dominators.cpp
diff -u llvm/lib/VMCore/Dominators.cpp:1.77 llvm/lib/VMCore/Dominators.cpp:1.78
--- llvm/lib/VMCore/Dominators.cpp:1.77 Thu Sep 21 20:07:57 2006
+++ llvm/lib/VMCore/Dominators.cpp Fri Nov 17 02:03:48 2006
@@ -20,7 +20,6 @@
#include "llvm/ADT/DepthFirstIterator.h"
#include "llvm/ADT/SetOperations.h"
#include
-#include
using namespace llvm;
//===--===//
Index: llvm/lib/VMCore/SymbolTable.cpp
diff -u llvm/lib/VMCore/SymbolTable.cpp:1.62
llvm/lib/VMCore/SymbolTable.cpp:1.63
--- llvm/lib/VMCore/SymbolTable.cpp:1.62Mon May 29 07:54:52 2006
+++ llvm/lib/VMCore/SymbolTable.cpp Fri Nov 17 02:03:48 2006
@@ -16,9 +16,8 @@
#include "llvm/DerivedTypes.h"
#include "llvm/Module.h"
#include "llvm/ADT/StringExtras.h"
+#include "llvm/Support/Debug.h"
#include
-#include
-
using namespace llvm;
#define DEBUG_SYMBOL_TABLE 0
@@ -39,9 +38,9 @@
for (plane_iterator PI = pmap.begin(); PI != pmap.end(); ++PI) {
for (value_iterator VI = PI->second.begin(); VI != PI->second.end(); ++VI)
if (!isa(VI->second) ) {
-std::cerr << "Value still in symbol table! Type = '"
- << PI->first->getDescription() << "' Name = '"
- << VI->first << "'\n";
+DOUT << "Value still in symbol table! Type = '"
+ << PI->first->getDescription() << "' Name = '"
+ << VI->first << "'\n";
LeftoverValues = false;
}
}
@@ -136,7 +135,7 @@
#if DEBUG_SYMBOL_TABLE
dump();
- std::cerr << " Removing Value: " << Entry->second->getName() << "\n";
+ DOUT << " Removing Value: " << Entry->second->getName() << "\n";
#endif
// Remove the value from the plane...
@@ -149,8 +148,8 @@
//
if (N->getType()->isAbstract()) {
#if DEBUG_ABSTYPE
- std::cerr << "Plane Empty: Removing type: "
-<< N->getType()->getDescription() << "\n";
+ DOUT << "Plane Empty: Removing type: "
+ << N->getType()->getDescription() << "\n";
#endif
cast(N->getType())->removeAbstractTypeUser(this);
}
@@ -167,7 +166,7 @@
#if DEBUG_SYMBOL_TABLE
dump();
- std::cerr << " Removing type: " << Entry->first << "\n";
+ DOUT << " Removing type: " << Entry->first << "\n";
#endif
tmap.erase(Entry);
@@ -176,7 +175,8 @@
// list...
if (Result->isAbstract()) {
#if DEBUG_ABSTYPE
-std::cerr << "Removing abstract type from symtab" <<
Result->getDescription()<<"\n";
+DOUT << "Removing abstract type from symtab"
+ << Result->getDescription() << "\n";
#endif
cast(Result)->removeAbstractTypeUser(this);
}
@@ -194,8 +194,8 @@
#if DEBUG_SYMBOL_TABLE
dump();
- std::cerr << " Inserting definition: " << Name << ": "
-<< VTy->getDescription() << "\n";
+ DOUT << " Inserting definition: " << Name << ": "
+
Re: [llvm-commits] Priority-Based Coloring Approach to Register Allocation
Hi Bill,
It's great to have a graph coloring regalloc to compare the current
implement against. Thanks!
Comments:
1. INode NeighborList is a std::set which is very slow.
Please use a more efficient data structure. You may have to wrap
LiveIntervals in something else and give each one a unique id.
2. Here is something I do have the answer for. But it's wonder
considering. Graph coloring can be slow. Does it make sense to
separate nodes by regclasses which cannot conflict. e.g. Do graph
coloring for all integer nodes and then do another round for all
floating point ones. This reduces the size of the graph.
3. Is LINodeMap a std::map? Again, you can probably use a more
efficient data structure if you assign each interval unique id. You
already have INode, why not use it?
4. CalculateInterference(). Why pass LINeighbors.begin() and .end().
LINodeMap is a RegAlloc ivar.
5.
/// Test if this live range interferes with the current live
range and that
/// they're both in the same register class.
if (CurNode->interferes(NeighborNode) &&
RelatedRegClasses.getLeaderValue(RegRC) == RCLeader)
CurNode->addNeighbor(NeighborNode);
else
CurNode->removeNeighbor(NeighborNode);
Why is removeNeighbor() needed? If it is not a neighbor, just don't
add it to the list?
6. Making ForbiddenRegs a map seems unnecessary. Why not add a ivar
to each INode that keeps track which registers are forbbiden?
7. SepareUnconstrainedLiveIntervals(): is it possible to create
separate lists in BuildGraph() rather than separate them later?
8. CalculatePriority(): The formula in paper is based on spill cost.
But it doesn't look like you are using this? For future please
consider LI's which can be rematerialized. Should we give LI's which
are more restricted (e.g. greater # of ForbiddenRegs, register pairs)
higher priorities?
9. PriorityBasedColoring():
/// FIXME: This algorithm is pretty gross and will probably
result in
/// massive performance issues!
if (IsUncolorable(CLI)) {
RemoveNodeFromGraph(LINodeMap[CLI]);
UncolorableLIs.insert(CLI);
DEBUG(std::cerr << "Removing uncolorable LiveInterval: "
<< *CLI << "\n");
}
Instead of inserting into the UncolorableLIs set and remove them
outside the loop, perhaps a worklist based approach can be used?
10. GetFreeReg(): That goto inside the nested for loop is evil. :-)
How about something like this:
while (I != E) {
bool TryAgain = false;
for () {
if () {
TryAgain = true;
break;
}
}
if (!TryAgain)
break;
++I;
}
I am not sure how to fix it. But GetFreeReg() seems to be pretty
expensive? After a register is picked, you update ForbbidenRegs set
of the neighbors. Is it more desirable to keep track a list of
candidates? Perhaps we can use a bitmap representation of a register
class and calculate a unique mask for each physical register before
coloring?
11. Please give INode::begin() end() more descriptive names.
12. Loop c in PriorityBasedColoring() seems very expensive. There
should be a cheaper way to detect whether a LI has to be split. Can
we cache the result of GetNumMappableRegs()?
I haven't read SplitLiveInterval in details, so no comment about it yet.
Cheers,
Evan
On Nov 15, 2006, at 5:03 PM, Bill Wendling wrote:
> Hi all,
>
> This is meant for a code review and NOT for submission (just yet).
> This is my implementation of Chow & Hennesey's Priority-Based
> Coloring Approach to Register Allocation. It's still in the
> experimental stages (though it compiles the tests). I'd like people
> to look at it and let me know what you think. The patch included is
> needed for compilation. You'd place the "RegAllocGraphColoring.cpp"
> file in the llvm/lib/CodeGen directory. You can use the graph
> coloring with the commandline:
>
> llc -regalloc=graphcoloring foo.bc
>
> All comments are welcome!
>
> -bw
>
>
>
>
> ___
> llvm-commits mailing list
> llvm-commits@cs.uiuc.edu
> http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
___
llvm-commits mailing list
llvm-commits@cs.uiuc.edu
http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
[llvm-commits] CVS: llvm/lib/Analysis/DataStructure/Printer.cpp
Changes in directory llvm/lib/Analysis/DataStructure: Printer.cpp updated: 1.86 -> 1.87 --- Log message: Needed for now. --- Diffs of the changes: (+1 -0) Printer.cpp |1 + 1 files changed, 1 insertion(+) Index: llvm/lib/Analysis/DataStructure/Printer.cpp diff -u llvm/lib/Analysis/DataStructure/Printer.cpp:1.86 llvm/lib/Analysis/DataStructure/Printer.cpp:1.87 --- llvm/lib/Analysis/DataStructure/Printer.cpp:1.86Mon Oct 2 07:26:53 2006 +++ llvm/lib/Analysis/DataStructure/Printer.cpp Fri Nov 17 03:44:28 2006 @@ -21,6 +21,7 @@ #include "llvm/Support/GraphWriter.h" #include "llvm/ADT/Statistic.h" #include "llvm/Config/config.h" +#include #include #include using namespace llvm; ___ llvm-commits mailing list llvm-commits@cs.uiuc.edu http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
[llvm-commits] CVS: llvm/lib/Analysis/CFGPrinter.cpp
Changes in directory llvm/lib/Analysis: CFGPrinter.cpp updated: 1.17 -> 1.18 --- Log message: Needs the iostream include. --- Diffs of the changes: (+1 -0) CFGPrinter.cpp |1 + 1 files changed, 1 insertion(+) Index: llvm/lib/Analysis/CFGPrinter.cpp diff -u llvm/lib/Analysis/CFGPrinter.cpp:1.17 llvm/lib/Analysis/CFGPrinter.cpp:1.18 --- llvm/lib/Analysis/CFGPrinter.cpp:1.17 Sun Aug 27 17:30:17 2006 +++ llvm/lib/Analysis/CFGPrinter.cppFri Nov 17 03:38:03 2006 @@ -25,6 +25,7 @@ #include "llvm/Support/CFG.h" #include "llvm/Support/GraphWriter.h" #include "llvm/Config/config.h" +#include #include #include using namespace llvm; ___ llvm-commits mailing list llvm-commits@cs.uiuc.edu http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
[llvm-commits] CVS: llvm/lib/Support/Streams.cpp
Changes in directory llvm/lib/Support: Streams.cpp added (r1.1) --- Log message: Added wrappers for the std::cerr/std::cout objects. The wrappers will soon replace all uses of those objects. --- Diffs of the changes: (+21 -0) Streams.cpp | 21 + 1 files changed, 21 insertions(+) Index: llvm/lib/Support/Streams.cpp diff -c /dev/null llvm/lib/Support/Streams.cpp:1.1 *** /dev/null Fri Nov 17 03:51:32 2006 --- llvm/lib/Support/Streams.cppFri Nov 17 03:51:22 2006 *** *** 0 --- 1,21 + //===-- Streams.cpp - Wrappers for iostreams --===// + // + // The LLVM Compiler Infrastructure + // + // This file was developed by Bill Wendling and is distributed under the + // University of Illinois Open Source License. See LICENSE.TXT for details. + // + //===--===// + // + // This file implements a wrapper for the std::cout and std::cerr I/O streams. + // It prevents the need to include to each file just to get I/O. + // + //===--===// + + #include "llvm/Support/Streams.h" + #include + using namespace llvm; + + llvm_ostream llvm::llvm_null; + llvm_ostream llvm::llvm_cout(std::cout); + llvm_ostream llvm::llvm_cerr(std::cerr); ___ llvm-commits mailing list llvm-commits@cs.uiuc.edu http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
[llvm-commits] CVS: llvm/include/llvm/Support/Streams.h
Changes in directory llvm/include/llvm/Support:
Streams.h added (r1.1)
---
Log message:
Added wrappers for the std::cerr/std::cout objects. The wrappers will
soon replace all uses of those objects.
---
Diffs of the changes: (+47 -0)
Streams.h | 47 +++
1 files changed, 47 insertions(+)
Index: llvm/include/llvm/Support/Streams.h
diff -c /dev/null llvm/include/llvm/Support/Streams.h:1.1
*** /dev/null Fri Nov 17 03:51:32 2006
--- llvm/include/llvm/Support/Streams.h Fri Nov 17 03:51:22 2006
***
*** 0
--- 1,47
+ //===- llvm/Support/Streams.h - Wrappers for iostreams --*- C++
-*-===//
+ //
+ // The LLVM Compiler Infrastructure
+ //
+ // This file was developed by Bill Wendling and is distributed under the
+ // University of Illinois Open Source License. See LICENSE.TXT for details.
+ //
+
//===--===//
+ //
+ // This file implements a wrapper for the std::cout and std::cerr I/O streams.
+ // It prevents the need to include to each file just to get I/O.
+ //
+
//===--===//
+
+ #ifndef LLVM_SUPPORT_STREAMS_H
+ #define LLVM_SUPPORT_STREAMS_H
+
+ #include // Doesn't have static d'tors!!
+
+ namespace llvm {
+
+ /// llvm_ostream - Acts like an ostream. It's a wrapper for the std::cerr
and
+ /// std::cout ostreams. However, it doesn't require #including in
+ /// every file, which increases static c'tors & d'tors in the object code.
+ ///
+ class llvm_ostream {
+ std::ostream* Stream;
+ public:
+ llvm_ostream() : Stream(0) {}
+ llvm_ostream(std::ostream &OStream) : Stream(&OStream) {}
+
+ template
+ llvm_ostream &operator << (const Ty &Thing) {
+ if (Stream) *Stream << Thing;
+ return *this;
+ }
+
+ bool operator == (const std::ostream &OS) { return &OS == Stream; }
+ };
+
+ extern llvm_ostream llvm_null;
+ extern llvm_ostream llvm_cout;
+ extern llvm_ostream llvm_cerr;
+
+ } // End llvm namespace
+
+ #endif
___
llvm-commits mailing list
llvm-commits@cs.uiuc.edu
http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
[llvm-commits] CVS: llvm/include/llvm/Support/Casting.h Debug.h GraphWriter.h PassNameParser.h
Changes in directory llvm/include/llvm/Support:
Casting.h updated: 1.15 -> 1.16
Debug.h updated: 1.10 -> 1.11
GraphWriter.h updated: 1.30 -> 1.31
PassNameParser.h updated: 1.12 -> 1.13
---
Log message:
Used llvm_ostream instead of std::ostream objects. This will reduce use
of the icky class.
---
Diffs of the changes: (+13 -31)
Casting.h|6 +++---
Debug.h | 20 +---
GraphWriter.h| 14 +++---
PassNameParser.h |4 ++--
4 files changed, 13 insertions(+), 31 deletions(-)
Index: llvm/include/llvm/Support/Casting.h
diff -u llvm/include/llvm/Support/Casting.h:1.15
llvm/include/llvm/Support/Casting.h:1.16
--- llvm/include/llvm/Support/Casting.h:1.15Sat May 13 12:50:38 2006
+++ llvm/include/llvm/Support/Casting.h Fri Nov 17 03:52:49 2006
@@ -235,7 +235,7 @@
#ifdef DEBUG_CAST_OPERATORS
-#include
+#include "llvm/Support/Debug.h"
struct bar {
bar() {}
@@ -245,13 +245,13 @@
struct foo {
void ext() const;
/* static bool classof(const bar *X) {
-cerr << "Classof: " << X << "\n";
+llvm_cerr << "Classof: " << X << "\n";
return true;
}*/
};
template <> inline bool isa_impl(const bar &Val) {
- cerr << "Classof: " << &Val << "\n";
+ llvm_cerr << "Classof: " << &Val << "\n";
return true;
}
Index: llvm/include/llvm/Support/Debug.h
diff -u llvm/include/llvm/Support/Debug.h:1.10
llvm/include/llvm/Support/Debug.h:1.11
--- llvm/include/llvm/Support/Debug.h:1.10 Thu Nov 16 19:43:48 2006
+++ llvm/include/llvm/Support/Debug.h Fri Nov 17 03:52:49 2006
@@ -26,7 +26,7 @@
#ifndef LLVM_SUPPORT_DEBUG_H
#define LLVM_SUPPORT_DEBUG_H
-#include // Doesn't have static d'tors!!
+#include "llvm/Support/Streams.h"
namespace llvm {
@@ -61,24 +61,6 @@
do { if (DebugFlag && isCurrentDebugType(DEBUG_TYPE)) { X; } } while (0)
#endif
-/// llvm_ostream - Acts like an ostream. However, it doesn't print things out
if
-/// an ostream isn't specified.
-///
-class llvm_ostream {
- std::ostream* Stream;
-public:
- llvm_ostream() : Stream(0) {}
- llvm_ostream(std::ostream& OStream) : Stream(&OStream) {}
-
- template
- llvm_ostream& operator << (const Ty& Thing) {
-#ifndef NDEBUG
-if (Stream) *Stream << Thing;
-#endif
-return *this;
- }
-};
-
/// getErrorOutputStream - Returns the error output stream (std::cerr). This
/// places the std::c* I/O streams into one .cpp file and relieves the whole
/// program from having to have hundreds of static c'tor/d'tors for them.
Index: llvm/include/llvm/Support/GraphWriter.h
diff -u llvm/include/llvm/Support/GraphWriter.h:1.30
llvm/include/llvm/Support/GraphWriter.h:1.31
--- llvm/include/llvm/Support/GraphWriter.h:1.30Mon Oct 2 07:26:53 2006
+++ llvm/include/llvm/Support/GraphWriter.h Fri Nov 17 03:52:49 2006
@@ -23,12 +23,12 @@
#ifndef LLVM_SUPPORT_GRAPHWRITER_H
#define LLVM_SUPPORT_GRAPHWRITER_H
+#include "llvm/Support/Debug.h"
#include "llvm/Support/DOTGraphTraits.h"
#include "llvm/ADT/GraphTraits.h"
#include "llvm/System/Path.h"
-#include
-#include
#include
+#include
namespace llvm {
@@ -247,16 +247,16 @@
std::string ErrMsg;
sys::Path Filename = sys::Path::GetTemporaryDirectory(&ErrMsg);
if (Filename.isEmpty()) {
-std::cerr << "Error: " << ErrMsg << "\n";
+llvm_cerr << "Error: " << ErrMsg << "\n";
return Filename;
}
Filename.appendComponent(Name + ".dot");
if (Filename.makeUnique(true,&ErrMsg)) {
-std::cerr << "Error: " << ErrMsg << "\n";
+llvm_cerr << "Error: " << ErrMsg << "\n";
return sys::Path();
}
- std::cerr << "Writing '" << Filename << "'... ";
+ llvm_cerr << "Writing '" << Filename << "'... ";
std::ofstream O(Filename.c_str());
@@ -275,12 +275,12 @@
// Output the end of the graph
W.writeFooter();
-std::cerr << " done. \n";
+llvm_cerr << " done. \n";
O.close();
} else {
-std::cerr << "error opening file for writing!\n";
+llvm_cerr << "error opening file for writing!\n";
Filename.clear();
}
Index: llvm/include/llvm/Support/PassNameParser.h
diff -u llvm/include/llvm/Support/PassNameParser.h:1.12
llvm/include/llvm/Support/PassNameParser.h:1.13
--- llvm/include/llvm/Support/PassNameParser.h:1.12 Sun Aug 27 17:11:07 2006
+++ llvm/include/llvm/Support/PassNameParser.h Fri Nov 17 03:52:49 2006
@@ -24,9 +24,9 @@
#define LLVM_SUPPORT_PASS_NAME_PARSER_H
#include "llvm/Support/CommandLine.h"
+#include "llvm/Support/Debug.h"
#include "llvm/Pass.h"
#include
-#include
namespace llvm {
@@ -66,7 +66,7 @@
virtual void passRegistered(const PassInfo *P) {
if (ignorablePass(P) || !Opt) return;
if (findOption(P->getPassArgument()) != getNumOptions()) {
- std::cerr << "Two passes with the same argument (-"
+ llvm_cerr << "Two passes with the same argument (-"
<< P->getPassArgument() << ") attempted to be registered!\n";
abort();
}
_
[llvm-commits] CVS: llvm/lib/Support/Debug.cpp
Changes in directory llvm/lib/Support:
Debug.cpp updated: 1.8 -> 1.9
---
Log message:
Moved definition of llvm_ostream wrappers to the Streams.cpp file.
---
Diffs of the changes: (+3 -4)
Debug.cpp |7 +++
1 files changed, 3 insertions(+), 4 deletions(-)
Index: llvm/lib/Support/Debug.cpp
diff -u llvm/lib/Support/Debug.cpp:1.8 llvm/lib/Support/Debug.cpp:1.9
--- llvm/lib/Support/Debug.cpp:1.8 Thu Nov 16 18:49:12 2006
+++ llvm/lib/Support/Debug.cpp Fri Nov 17 03:54:47 2006
@@ -23,9 +23,8 @@
//
//===--===//
-#include "llvm/Support/Debug.h"
#include "llvm/Support/CommandLine.h"
-#include
+#include "llvm/Support/Debug.h"
using namespace llvm;
bool llvm::DebugFlag; // DebugFlag - Exported boolean set by the -debug option
@@ -71,7 +70,7 @@
//
llvm_ostream llvm::getErrorOutputStream(const char *DebugType) {
if (DebugFlag && isCurrentDebugType(DebugType))
-return llvm_ostream(std::cerr);
+return llvm_cerr;
else
-return llvm_ostream();
+return llvm_null;
}
___
llvm-commits mailing list
llvm-commits@cs.uiuc.edu
http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
[llvm-commits] CVS: llvm/tools/llvm-ld/Optimize.cpp
Changes in directory llvm/tools/llvm-ld: Optimize.cpp updated: 1.13 -> 1.14 --- Log message: Need for the time being. --- Diffs of the changes: (+1 -0) Optimize.cpp |1 + 1 files changed, 1 insertion(+) Index: llvm/tools/llvm-ld/Optimize.cpp diff -u llvm/tools/llvm-ld/Optimize.cpp:1.13 llvm/tools/llvm-ld/Optimize.cpp:1.14 --- llvm/tools/llvm-ld/Optimize.cpp:1.13Sun Aug 27 17:07:43 2006 +++ llvm/tools/llvm-ld/Optimize.cpp Fri Nov 17 04:09:22 2006 @@ -24,6 +24,7 @@ #include "llvm/Transforms/Scalar.h" #include "llvm/Support/PassNameParser.h" #include "llvm/Support/PluginLoader.h" +#include using namespace llvm; // Pass Name Options as generated by the PassNameParser ___ llvm-commits mailing list llvm-commits@cs.uiuc.edu http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
[llvm-commits] CVS: llvm/tools/opt/GraphPrinters.cpp
Changes in directory llvm/tools/opt: GraphPrinters.cpp updated: 1.13 -> 1.14 --- Log message: Need iostream to be included for the time being. --- Diffs of the changes: (+1 -0) GraphPrinters.cpp |1 + 1 files changed, 1 insertion(+) Index: llvm/tools/opt/GraphPrinters.cpp diff -u llvm/tools/opt/GraphPrinters.cpp:1.13 llvm/tools/opt/GraphPrinters.cpp:1.14 --- llvm/tools/opt/GraphPrinters.cpp:1.13 Sun Aug 27 20:02:49 2006 +++ llvm/tools/opt/GraphPrinters.cppFri Nov 17 04:05:07 2006 @@ -18,6 +18,7 @@ #include "llvm/Pass.h" #include "llvm/Value.h" #include "llvm/Analysis/CallGraph.h" +#include #include using namespace llvm; ___ llvm-commits mailing list llvm-commits@cs.uiuc.edu http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
[llvm-commits] CVS: llvm/tools/bugpoint/bugpoint.cpp
Changes in directory llvm/tools/bugpoint: bugpoint.cpp updated: 1.33 -> 1.34 --- Log message: Need for the time being. --- Diffs of the changes: (+1 -0) bugpoint.cpp |1 + 1 files changed, 1 insertion(+) Index: llvm/tools/bugpoint/bugpoint.cpp diff -u llvm/tools/bugpoint/bugpoint.cpp:1.33 llvm/tools/bugpoint/bugpoint.cpp:1.34 --- llvm/tools/bugpoint/bugpoint.cpp:1.33 Mon Aug 21 00:34:03 2006 +++ llvm/tools/bugpoint/bugpoint.cppFri Nov 17 04:07:24 2006 @@ -22,6 +22,7 @@ #include "llvm/System/Process.h" #include "llvm/System/Signals.h" #include "llvm/LinkAllVMCore.h" +#include using namespace llvm; // AsChild - Specifies that this invocation of bugpoint is being generated ___ llvm-commits mailing list llvm-commits@cs.uiuc.edu http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
[llvm-commits] CVS: llvm/lib/CodeGen/SelectionDAG/SelectionDAGPrinter.cpp
Changes in directory llvm/lib/CodeGen/SelectionDAG:
SelectionDAGPrinter.cpp updated: 1.43 -> 1.44
---
Log message:
Fixing the ENABLE_OPTIMIZED=1 DISABLE_ASSERTIONS=1 build.
---
Diffs of the changes: (+1 -0)
SelectionDAGPrinter.cpp |1 +
1 files changed, 1 insertion(+)
Index: llvm/lib/CodeGen/SelectionDAG/SelectionDAGPrinter.cpp
diff -u llvm/lib/CodeGen/SelectionDAG/SelectionDAGPrinter.cpp:1.43
llvm/lib/CodeGen/SelectionDAG/SelectionDAGPrinter.cpp:1.44
--- llvm/lib/CodeGen/SelectionDAG/SelectionDAGPrinter.cpp:1.43 Thu Nov 9
12:43:20 2006
+++ llvm/lib/CodeGen/SelectionDAG/SelectionDAGPrinter.cpp Fri Nov 17
07:07:55 2006
@@ -24,6 +24,7 @@
#include "llvm/Config/config.h"
#include
#include
+#include
using namespace llvm;
namespace llvm {
___
llvm-commits mailing list
llvm-commits@cs.uiuc.edu
http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
[llvm-commits] CVS: llvm/lib/Target/PowerPC/PPCBranchSelector.cpp
Changes in directory llvm/lib/Target/PowerPC:
PPCBranchSelector.cpp updated: 1.33 -> 1.34
---
Log message:
Typo. Fix the nightly tests.
---
Diffs of the changes: (+1 -1)
PPCBranchSelector.cpp |2 +-
1 files changed, 1 insertion(+), 1 deletion(-)
Index: llvm/lib/Target/PowerPC/PPCBranchSelector.cpp
diff -u llvm/lib/Target/PowerPC/PPCBranchSelector.cpp:1.33
llvm/lib/Target/PowerPC/PPCBranchSelector.cpp:1.34
--- llvm/lib/Target/PowerPC/PPCBranchSelector.cpp:1.33 Thu Nov 16 19:52:23 2006
+++ llvm/lib/Target/PowerPC/PPCBranchSelector.cpp Fri Nov 17 08:06:41 2006
@@ -137,7 +137,7 @@
} else {
// Long branch, skip next branch instruction (i.e. $PC+8).
++NumExpanded;
-BuildMI(*MBB, MBBJ, Inverted, 2).addReg(CRReg).addImm(2);
+BuildMI(*MBB, MBBI, Inverted, 2).addReg(CRReg).addImm(2);
MBBJ = BuildMI(*MBB, MBBI, PPC::B, 1).addMBB(DestMBB);
}
___
llvm-commits mailing list
llvm-commits@cs.uiuc.edu
http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
[llvm-commits] CVS: llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp
Changes in directory llvm/lib/Target/PowerPC:
PPCRegisterInfo.cpp updated: 1.86 -> 1.87
---
Log message:
1. Ignore the -disable-fp-elim when the routine is a leaf.
2. Offsets on 64-bit stores are still in bytes.
---
Diffs of the changes: (+2 -2)
PPCRegisterInfo.cpp |4 ++--
1 files changed, 2 insertions(+), 2 deletions(-)
Index: llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp
diff -u llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp:1.86
llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp:1.87
--- llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp:1.86Thu Nov 16 16:43:37 2006
+++ llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp Fri Nov 17 10:09:31 2006
@@ -704,7 +704,7 @@
// don't have a frame pointer, calls, or dynamic alloca then we do not need
// to adjust the stack pointer (we fit in the Red Zone).
if (FrameSize <= 224 && // Fits in red zone.
- !needsFP(MF) && // Frame pointer can be eliminated.
+ !MFI->hasVarSizedObjects() && // No dynamic alloca.
!MFI->hasCalls() && // No calls.
MaxAlign <= TargetAlign) { // No special alignment.
// No need for frame
@@ -818,7 +818,7 @@
.addImm(NegFrameSize);
BuildMI(MBB, MBBI, PPC::STDUX, 3)
.addReg(PPC::X1).addReg(PPC::X1).addReg(PPC::X0);
-} else if (isInt16(NegFrameSize/4)) {
+} else if (isInt16(NegFrameSize)) {
BuildMI(MBB, MBBI, PPC::STDU, 3, PPC::X1)
.addReg(PPC::X1).addImm(NegFrameSize/4).addReg(PPC::X1);
} else {
___
llvm-commits mailing list
llvm-commits@cs.uiuc.edu
http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
[llvm-commits] CVS: llvm/test/Regression/CodeGen/PowerPC/Frames-alloca.ll Frames-large.ll Frames-leaf.ll Frames-small.ll
Changes in directory llvm/test/Regression/CodeGen/PowerPC:
Frames-alloca.ll added (r1.1)
Frames-large.ll added (r1.1)
Frames-leaf.ll added (r1.1)
Frames-small.ll added (r1.1)
---
Log message:
Tests to verify PowerPC ABI.
---
Diffs of the changes: (+104 -0)
Frames-alloca.ll | 24
Frames-large.ll | 32
Frames-leaf.ll | 24
Frames-small.ll | 24
4 files changed, 104 insertions(+)
Index: llvm/test/Regression/CodeGen/PowerPC/Frames-alloca.ll
diff -c /dev/null llvm/test/Regression/CodeGen/PowerPC/Frames-alloca.ll:1.1
*** /dev/null Fri Nov 17 10:54:31 2006
--- llvm/test/Regression/CodeGen/PowerPC/Frames-alloca.ll Fri Nov 17
10:54:21 2006
***
*** 0
--- 1,24
+ ; RUN: llvm-as < %s | llc -march=ppc32 | grep 'stw r31, 20(r1)' &&
+ ; RUN: llvm-as < %s | llc -march=ppc32 | grep 'stwu r1, -64(r1)' &&
+ ; RUN: llvm-as < %s | llc -march=ppc32 | grep 'lwz r1, 0(r1)' &&
+ ; RUN: llvm-as < %s | llc -march=ppc32 | grep 'lwz r31, 20(r1)' &&
+ ; RUN: llvm-as < %s | llc -march=ppc32 -disable-fp-elim | grep 'stw r31,
20(r1)' &&
+ ; RUN: llvm-as < %s | llc -march=ppc32 -disable-fp-elim | grep 'stwu r1,
-64(r1)' &&
+ ; RUN: llvm-as < %s | llc -march=ppc32 -disable-fp-elim | grep 'lwz r1,
0(r1)' &&
+ ; RUN: llvm-as < %s | llc -march=ppc32 -disable-fp-elim | grep 'lwz r31,
20(r1)' &&
+ ; RUN: llvm-as < %s | llc -march=ppc64 | grep 'std r31, 40(r1)' &&
+ ; RUN: llvm-as < %s | llc -march=ppc64 | grep 'stdu r1, -112(r1)' &&
+ ; RUN: llvm-as < %s | llc -march=ppc64 | grep 'ld r1, 0(r1)' &&
+ ; RUN: llvm-as < %s | llc -march=ppc64 | grep 'ld r31, 40(r1)' &&
+ ; RUN: llvm-as < %s | llc -march=ppc64 -disable-fp-elim | grep 'std r31,
40(r1)' &&
+ ; RUN: llvm-as < %s | llc -march=ppc64 -disable-fp-elim | grep 'stdu r1,
-112(r1)' &&
+ ; RUN: llvm-as < %s | llc -march=ppc64 -disable-fp-elim | grep 'ld r1, 0(r1)'
&&
+ ; RUN: llvm-as < %s | llc -march=ppc64 -disable-fp-elim | grep 'ld r31,
40(r1)'
+
+
+ implementation
+
+ int* %f1(uint %n) {
+ %tmp = alloca int, uint %n
+ ret int* %tmp
+ }
Index: llvm/test/Regression/CodeGen/PowerPC/Frames-large.ll
diff -c /dev/null llvm/test/Regression/CodeGen/PowerPC/Frames-large.ll:1.1
*** /dev/null Fri Nov 17 10:54:36 2006
--- llvm/test/Regression/CodeGen/PowerPC/Frames-large.llFri Nov 17
10:54:21 2006
***
*** 0
--- 1,32
+ ; RUN: llvm-as < %s | llc -march=ppc32 | NOT grep 'stw r31, 20(r1)' &&
+ ; RUN: llvm-as < %s | llc -march=ppc32 | grep 'lis r0, -1' &&
+ ; RUN: llvm-as < %s | llc -march=ppc32 | grep 'ori r0, r0, 32704' &&
+ ; RUN: llvm-as < %s | llc -march=ppc32 | grep 'stwux r1, r1, r0' &&
+ ; RUN: llvm-as < %s | llc -march=ppc32 | grep 'lwz r1, 0(r1)' &&
+ ; RUN: llvm-as < %s | llc -march=ppc32 | NOT grep 'lwz r31, 20(r1)' &&
+ ; RUN: llvm-as < %s | llc -march=ppc32 -disable-fp-elim | grep 'stw r31,
20(r1)' &&
+ ; RUN: llvm-as < %s | llc -march=ppc32 -disable-fp-elim | grep 'lis r0, -1' &&
+ ; RUN: llvm-as < %s | llc -march=ppc32 -disable-fp-elim | grep 'ori r0, r0,
32704' &&
+ ; RUN: llvm-as < %s | llc -march=ppc32 -disable-fp-elim | grep 'stwux r1, r1,
r0' &&
+ ; RUN: llvm-as < %s | llc -march=ppc32 -disable-fp-elim | grep 'lwz r1,
0(r1)' &&
+ ; RUN: llvm-as < %s | llc -march=ppc32 -disable-fp-elim | grep 'lwz r31,
20(r1)' &&
+ ; RUN: llvm-as < %s | llc -march=ppc64 | NOT grep 'std r31, 40(r1)' &&
+ ; RUN: llvm-as < %s | llc -march=ppc64 | grep 'lis r0, -1' &&
+ ; RUN: llvm-as < %s | llc -march=ppc64 | grep 'ori r0, r0, 32656' &&
+ ; RUN: llvm-as < %s | llc -march=ppc64 | grep 'stdux r1, r1, r0' &&
+ ; RUN: llvm-as < %s | llc -march=ppc64 | grep 'ld r1, 0(r1)' &&
+ ; RUN: llvm-as < %s | llc -march=ppc64 | NOT grep 'ld r31, 40(r1)' &&
+ ; RUN: llvm-as < %s | llc -march=ppc64 -disable-fp-elim | grep 'std r31,
40(r1)' &&
+ ; RUN: llvm-as < %s | llc -march=ppc64 -disable-fp-elim | grep 'lis r0, -1' &&
+ ; RUN: llvm-as < %s | llc -march=ppc64 -disable-fp-elim | grep 'ori r0, r0,
32656' &&
+ ; RUN: llvm-as < %s | llc -march=ppc64 -disable-fp-elim | grep 'stdux r1, r1,
r0' &&
+ ; RUN: llvm-as < %s | llc -march=ppc64 -disable-fp-elim | grep 'ld r1, 0(r1)'
&&
+ ; RUN: llvm-as < %s | llc -march=ppc64 -disable-fp-elim | grep 'ld r31,
40(r1)'
+
+
+ implementation
+
+ int* %f1() {
+ %tmp = alloca int, uint 8191
+ ret int* %tmp
+ }
Index: llvm/test/Regression/CodeGen/PowerPC/Frames-leaf.ll
diff -c /dev/null llvm/test/Regression/CodeGen/PowerPC/Frames-leaf.ll:1.1
*** /dev/null Fri Nov 17 10:54:36 2006
--- llvm/test/Regression/CodeGen/PowerPC/Frames-leaf.ll Fri Nov 17 10:54:21 2006
***
*** 0
--- 1,24
+ ; RUN: llvm-as < %s | llc -march=ppc32 | NOT grep 'stw r31, 20(r1)' &&
+ ; RUN: llvm-as < %s | llc -march=ppc32 | NOT grep 'stwu r1, -.*(r1)' &&
+ ; RUN: llvm-as < %s | llc -march=ppc32 | NOT grep 'addi r1, r1, ' &&
+ ; RUN: llvm-as < %s | llc -march=ppc3
[llvm-commits] CVS: llvm/test/Regression/CodeGen/PowerPC/Frames-align.ll
Changes in directory llvm/test/Regression/CodeGen/PowerPC:
Frames-align.ll added (r1.1)
---
Log message:
Check for MaxAlign.
---
Diffs of the changes: (+11 -0)
Frames-align.ll | 11 +++
1 files changed, 11 insertions(+)
Index: llvm/test/Regression/CodeGen/PowerPC/Frames-align.ll
diff -c /dev/null llvm/test/Regression/CodeGen/PowerPC/Frames-align.ll:1.1
*** /dev/null Fri Nov 17 11:19:59 2006
--- llvm/test/Regression/CodeGen/PowerPC/Frames-align.llFri Nov 17
11:19:49 2006
***
*** 0
--- 1,11
+ ; RUN: llvm-as < %s | llc -march=ppc32 | grep 'rlwinm r0, r1, 0, 22, 31' &&
+ ; RUN: llvm-as < %s | llc -march=ppc32 | grep 'subfic r0, r0, -17408' &&
+ ; RUN: llvm-as < %s | llc -march=ppc64 | grep 'rldicl r0, r1, 0, 54'
+
+
+ implementation
+
+ int* %f1() {
+ %tmp = alloca int, uint 4095, align 1024
+ ret int* %tmp
+ }
___
llvm-commits mailing list
llvm-commits@cs.uiuc.edu
http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
[llvm-commits] CVS: llvm/test/Regression/CodeGen/PowerPC/Frames-large.ll Frames-leaf.ll Frames-small.ll
Changes in directory llvm/test/Regression/CodeGen/PowerPC: Frames-large.ll updated: 1.1 -> 1.2 Frames-leaf.ll updated: 1.1 -> 1.2 Frames-small.ll updated: 1.1 -> 1.2 --- Log message: Case sensitive not. --- Diffs of the changes: (+24 -24) Frames-large.ll |8 Frames-leaf.ll | 32 Frames-small.ll |8 3 files changed, 24 insertions(+), 24 deletions(-) Index: llvm/test/Regression/CodeGen/PowerPC/Frames-large.ll diff -u llvm/test/Regression/CodeGen/PowerPC/Frames-large.ll:1.1 llvm/test/Regression/CodeGen/PowerPC/Frames-large.ll:1.2 --- llvm/test/Regression/CodeGen/PowerPC/Frames-large.ll:1.1Fri Nov 17 10:54:21 2006 +++ llvm/test/Regression/CodeGen/PowerPC/Frames-large.llFri Nov 17 12:00:39 2006 @@ -1,21 +1,21 @@ -; RUN: llvm-as < %s | llc -march=ppc32 | NOT grep 'stw r31, 20(r1)' && +; RUN: llvm-as < %s | llc -march=ppc32 | not grep 'stw r31, 20(r1)' && ; RUN: llvm-as < %s | llc -march=ppc32 | grep 'lis r0, -1' && ; RUN: llvm-as < %s | llc -march=ppc32 | grep 'ori r0, r0, 32704' && ; RUN: llvm-as < %s | llc -march=ppc32 | grep 'stwux r1, r1, r0' && ; RUN: llvm-as < %s | llc -march=ppc32 | grep 'lwz r1, 0(r1)' && -; RUN: llvm-as < %s | llc -march=ppc32 | NOT grep 'lwz r31, 20(r1)' && +; RUN: llvm-as < %s | llc -march=ppc32 | not grep 'lwz r31, 20(r1)' && ; RUN: llvm-as < %s | llc -march=ppc32 -disable-fp-elim | grep 'stw r31, 20(r1)' && ; RUN: llvm-as < %s | llc -march=ppc32 -disable-fp-elim | grep 'lis r0, -1' && ; RUN: llvm-as < %s | llc -march=ppc32 -disable-fp-elim | grep 'ori r0, r0, 32704' && ; RUN: llvm-as < %s | llc -march=ppc32 -disable-fp-elim | grep 'stwux r1, r1, r0' && ; RUN: llvm-as < %s | llc -march=ppc32 -disable-fp-elim | grep 'lwz r1, 0(r1)' && ; RUN: llvm-as < %s | llc -march=ppc32 -disable-fp-elim | grep 'lwz r31, 20(r1)' && -; RUN: llvm-as < %s | llc -march=ppc64 | NOT grep 'std r31, 40(r1)' && +; RUN: llvm-as < %s | llc -march=ppc64 | not grep 'std r31, 40(r1)' && ; RUN: llvm-as < %s | llc -march=ppc64 | grep 'lis r0, -1' && ; RUN: llvm-as < %s | llc -march=ppc64 | grep 'ori r0, r0, 32656' && ; RUN: llvm-as < %s | llc -march=ppc64 | grep 'stdux r1, r1, r0' && ; RUN: llvm-as < %s | llc -march=ppc64 | grep 'ld r1, 0(r1)' && -; RUN: llvm-as < %s | llc -march=ppc64 | NOT grep 'ld r31, 40(r1)' && +; RUN: llvm-as < %s | llc -march=ppc64 | not grep 'ld r31, 40(r1)' && ; RUN: llvm-as < %s | llc -march=ppc64 -disable-fp-elim | grep 'std r31, 40(r1)' && ; RUN: llvm-as < %s | llc -march=ppc64 -disable-fp-elim | grep 'lis r0, -1' && ; RUN: llvm-as < %s | llc -march=ppc64 -disable-fp-elim | grep 'ori r0, r0, 32656' && Index: llvm/test/Regression/CodeGen/PowerPC/Frames-leaf.ll diff -u llvm/test/Regression/CodeGen/PowerPC/Frames-leaf.ll:1.1 llvm/test/Regression/CodeGen/PowerPC/Frames-leaf.ll:1.2 --- llvm/test/Regression/CodeGen/PowerPC/Frames-leaf.ll:1.1 Fri Nov 17 10:54:21 2006 +++ llvm/test/Regression/CodeGen/PowerPC/Frames-leaf.ll Fri Nov 17 12:00:39 2006 @@ -1,19 +1,19 @@ -; RUN: llvm-as < %s | llc -march=ppc32 | NOT grep 'stw r31, 20(r1)' && -; RUN: llvm-as < %s | llc -march=ppc32 | NOT grep 'stwu r1, -.*(r1)' && -; RUN: llvm-as < %s | llc -march=ppc32 | NOT grep 'addi r1, r1, ' && -; RUN: llvm-as < %s | llc -march=ppc32 | NOT grep 'lwz r31, 20(r1)' && -; RUN: llvm-as < %s | llc -march=ppc32 -disable-fp-elim | NOT grep 'stw r31, 20(r1)' && -; RUN: llvm-as < %s | llc -march=ppc32 -disable-fp-elim | NOT grep 'stwu r1, -.*(r1)' && -; RUN: llvm-as < %s | llc -march=ppc32 -disable-fp-elim | NOT grep 'addi r1, r1, ' && -; RUN: llvm-as < %s | llc -march=ppc32 -disable-fp-elim | NOT grep 'lwz r31, 20(r1)' && -; RUN: llvm-as < %s | llc -march=ppc64 | NOT grep 'std r31, 40(r1)' && -; RUN: llvm-as < %s | llc -march=ppc64 | NOT grep 'stdu r1, -.*(r1)' && -; RUN: llvm-as < %s | llc -march=ppc64 | NOT grep 'addi r1, r1, ' && -; RUN: llvm-as < %s | llc -march=ppc64 | NOT grep 'ld r31, 40(r1)' && -; RUN: llvm-as < %s | llc -march=ppc64 -disable-fp-elim | NOT grep 'stw r31, 40(r1)' && -; RUN: llvm-as < %s | llc -march=ppc64 -disable-fp-elim | NOT grep 'stdu r1, -.*(r1)' && -; RUN: llvm-as < %s | llc -march=ppc64 -disable-fp-elim | NOT grep 'addi r1, r1, ' && -; RUN: llvm-as < %s | llc -march=ppc64 -disable-fp-elim | NOT grep 'ld r31, 40(r1)' +; RUN: llvm-as < %s | llc -march=ppc32 | not grep 'stw r31, 20(r1)' && +; RUN: llvm-as < %s | llc -march=ppc32 | not grep 'stwu r1, -.*(r1)' && +; RUN: llvm-as < %s | llc -march=ppc32 | not grep 'addi r1, r1, ' && +; RUN: llvm-as < %s | llc -march=ppc32 | not grep 'lwz r31, 20(r1)' && +; RUN: llvm-as < %s | llc -march=ppc32 -disable-fp-elim | not grep 'stw r31, 20(r1)' && +; RUN: llvm-as < %s | llc -march=ppc32 -disable-fp-elim | not grep 'stwu r1, -.*(r1)' && +; RUN: llvm-as < %s | llc -march=ppc32 -disable-fp-elim | not grep 'addi r1, r1, ' && +; RUN: llvm-as < %s | llc -march=ppc32 -disable-fp-elim | not grep 'lwz r31, 20(r1)' && +; RUN: llvm-as <
[llvm-commits] CVS: llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp
Changes in directory llvm/lib/Target/PowerPC: PPCRegisterInfo.cpp updated: 1.87 -> 1.88 --- Log message: Assert unhandled case. --- Diffs of the changes: (+2 -0) PPCRegisterInfo.cpp |2 ++ 1 files changed, 2 insertions(+) Index: llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp diff -u llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp:1.87 llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp:1.88 --- llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp:1.87Fri Nov 17 10:09:31 2006 +++ llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp Fri Nov 17 12:49:39 2006 @@ -445,6 +445,8 @@ // Get stack alignments. unsigned TargetAlign = MF.getTarget().getFrameInfo()->getStackAlignment(); unsigned MaxAlign = MFI->getMaxAlignment(); + assert(MaxAlign <= TargetAlign && + "Dynamic alloca with large aligns not supported"); // Determine the previous frame's address. If FrameSize can't be // represented as 16 bits or we need special alignment, then we load the ___ llvm-commits mailing list llvm-commits@cs.uiuc.edu http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
[llvm-commits] llvm-gcc4 implement VIEW_CONVERT_EXPR
This implements an unimplemented tree code:
Index: llvm-convert.cpp
===
--- llvm-convert.cpp(revision 120289)
+++ llvm-convert.cpp(working copy)
@@ -522,6 +522,7 @@ Value *TreeToLLVM::Emit(tree exp, Value
case FIX_TRUNC_EXPR:
case FLOAT_EXPR:
case CONVERT_EXPR: Result = EmitCONVERT_EXPR(exp, DestLoc); break;
+ case VIEW_CONVERT_EXPR: Result = EmitVIEW_CONVERT_EXPR(exp, DestLoc); break;
case NEGATE_EXPR:Result = EmitNEGATE_EXPR(exp, DestLoc); break;
case CONJ_EXPR: Result = EmitCONJ_EXPR(exp, DestLoc); break;
case ABS_EXPR: Result = EmitABS_EXPR(exp); break;
@@ -2136,20 +2137,20 @@ Value *TreeToLLVM::EmitNOP_EXPR(tree exp
if (DestLoc == 0) {
// Scalar to scalar copy.
assert(!isAggregateType(TREE_TYPE(Op)) && "Aggregate to scalar nop_expr!");
-Value *Op = Emit(TREE_OPERAND(exp, 0), DestLoc);
+Value *OpVal = Emit(Op, DestLoc);
if (Ty == Type::VoidTy) return 0;
-return CastToType(Op, Ty);
+return CastToType(OpVal, Ty);
} else if (isAggregateType(TREE_TYPE(Op))) {
// Aggregate to aggregate copy.
DestLoc = CastToType(DestLoc, PointerType::get(Ty));
-Value *Op = Emit(TREE_OPERAND(exp, 0), DestLoc);
-assert(Op == 0 && "Shouldn't cast scalar to aggregate!");
+Value *OpVal = Emit(Op, DestLoc);
+assert(OpVal == 0 && "Shouldn't cast scalar to aggregate!");
return 0;
} else {
// Scalar to aggregate copy.
-Value *Op = Emit(TREE_OPERAND(exp, 0), 0);
-DestLoc = CastToType(DestLoc, PointerType::get(Op->getType()));
-new StoreInst(Op, DestLoc, CurBB);
+Value *OpVal = Emit(Op, 0);
+DestLoc = CastToType(DestLoc, PointerType::get(OpVal->getType()));
+new StoreInst(OpVal, DestLoc, CurBB);
return 0;
}
}
@@ -2160,6 +2161,52 @@ Value *TreeToLLVM::EmitCONVERT_EXPR(tree
return CastToType(Op, ConvertType(TREE_TYPE(exp)));
}
+Value *TreeToLLVM::EmitVIEW_CONVERT_EXPR(tree exp, Value *DestLoc) {
+ tree Op = TREE_OPERAND(exp, 0);
+ const Type *OpTy = ConvertType(TREE_TYPE(Op));
+
+ if (isAggregateType(TREE_TYPE(Op))) {
+if (DestLoc) {
+ // This is an aggregate-to-agg VIEW_CONVERT_EXPR, just evaluate in place.
+ Value *OpVal = Emit(Op, CastToType(DestLoc, PointerType::get(OpTy)));
+ assert(OpVal == 0 && "Expected an aggregate operand!");
+ return 0;
+} else {
+ // This is an aggregate-to-scalar VIEW_CONVERT_EXPR, evaluate, then load.
+ Value *DestLoc = CreateTemporary(OpTy);
+ Value *OpVal = Emit(Op, DestLoc);
+ assert(OpVal == 0 && "Expected an aggregate operand!");
+
+ const Type *ExpTy = ConvertType(TREE_TYPE(exp));
+ return new LoadInst(CastToType(DestLoc, PointerType::get(ExpTy)), "tmp",
+ CurBB);
+}
+ }
+
+ if (DestLoc) {
+// The input is a scalar the output is an aggregate, just eval the input,
+// then store into DestLoc.
+Value *OpVal = Emit(Op, 0);
+assert(OpVal && "Expected a scalar result!");
+DestLoc = CastToType(DestLoc, PointerType::get(OpVal->getType()));
+new StoreInst(OpVal, DestLoc, CurBB);
+return 0;
+ }
+
+ // Otherwise, this is a scalar to scalar conversion. FIXME: this should use
+ // a bitcast or int_to_ptr/ptr_to_int when cast changes land. For now, go
+ // through memory. :P
+ Value *OpVal = Emit(Op, 0);
+ assert(OpVal && "Expected a scalar result!");
+
+ Value *TmpLoc = CreateTemporary(OpVal->getType());
+ new StoreInst(OpVal, TmpLoc, CurBB);
+
+ // Cast the memory to the right type.
+ TmpLoc = CastToType(TmpLoc, PointerType::get(ConvertType(TREE_TYPE(exp;
+ return new LoadInst(TmpLoc, "tmp", CurBB);
+}
+
Value *TreeToLLVM::EmitNEGATE_EXPR(tree exp, Value *DestLoc) {
if (!DestLoc)
return BinaryOperator::createNeg(Emit(TREE_OPERAND(exp, 0), 0),
Index: llvm-internal.h
===
--- llvm-internal.h (revision 120289)
+++ llvm-internal.h (working copy)
@@ -382,6 +382,7 @@ private:
Value *EmitMODIFY_EXPR(tree_node *exp, Value *DestLoc);
Value *EmitNOP_EXPR(tree_node *exp, Value *DestLoc);
Value *EmitCONVERT_EXPR(tree_node *exp, Value *DestLoc);
+ Value *EmitVIEW_CONVERT_EXPR(tree_node *exp, Value *DestLoc);
Value *EmitNEGATE_EXPR(tree_node *exp, Value *DestLoc);
Value *EmitCONJ_EXPR(tree_node *exp, Value *DestLoc);
Value *EmitABS_EXPR(tree_node *exp);
It will get nicer once bitcast lands :)
-Chris___
llvm-commits mailing list
llvm-commits@cs.uiuc.edu
http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
[llvm-commits] Fix PR 1008
Fix cut-n-pasto. Fix PR 1008.
Thanks Chris!
-
Devang
Index: llvm-convert.cpp
===
--- llvm-convert.cpp(revision 119923)
+++ llvm-convert.cpp(working copy)
@@ -4135,7 +4135,7 @@ Constant *TreeConstantToLLVM::ConvertSTR
const signed short *InStr = (const signed short
*)TREE_STRING_POINTER(exp);
for (unsigned i = 0; i != Len; ++i)
Elts.push_back(ConstantInt::get(Type::ShortTy, InStr[i]));
- } else if (ElTy == Type::UByteTy) {
+ } else if (ElTy == Type::UShortTy) {
const unsigned short *InStr =
(const unsigned short *)TREE_STRING_POINTER(exp);
for (unsigned i = 0; i != Len; ++i)
___
llvm-commits mailing list
llvm-commits@cs.uiuc.edu
http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
[llvm-commits] CVS: llvm/test/Regression/CodeGen/X86/2006-11-17-IllegalMove.ll
Changes in directory llvm/test/Regression/CodeGen/X86:
2006-11-17-IllegalMove.ll added (r1.1)
---
Log message:
Add a x86-64 test case: movb %sil, %ah is illegal.
---
Diffs of the changes: (+41 -0)
2006-11-17-IllegalMove.ll | 41 +
1 files changed, 41 insertions(+)
Index: llvm/test/Regression/CodeGen/X86/2006-11-17-IllegalMove.ll
diff -c /dev/null llvm/test/Regression/CodeGen/X86/2006-11-17-IllegalMove.ll:1.1
*** /dev/null Fri Nov 17 14:42:05 2006
--- llvm/test/Regression/CodeGen/X86/2006-11-17-IllegalMove.ll Fri Nov 17
14:41:55 2006
***
*** 0
--- 1,41
+ ; RUN: llvm-as < %s | llc -march=x86-64 &&
+ ; RUN: llvm-as < %s | llc -march=x86-64 | not grep 'movb %sil, %ah' &&
+ ; RUN: llvm-as < %s | llc -march=x86-64 | grep 'movzbw %al, %ax'
+
+ void %handle_vector_size_attribute() {
+ entry:
+ %tmp69 = load uint* null; [#uses=1]
+ switch uint %tmp69, label %bb84 [
+uint 2, label %bb77
+uint 1, label %bb77
+ ]
+
+ bb77: ; preds = %entry, %entry
+ %tmp99 = udiv ulong 0, 0; [#uses=1]
+ %tmp = load ubyte* null ; [#uses=1]
+ %tmp114 = seteq ulong 0, 0 ; [#uses=1]
+ br bool %tmp114, label %cond_true115, label %cond_next136
+
+ bb84: ; preds = %entry
+ ret void
+
+ cond_true115: ; preds = %bb77
+ %tmp118 = load ubyte* null ; [#uses=1]
+ br bool false, label %cond_next129, label %cond_true120
+
+ cond_true120: ; preds = %cond_true115
+ %tmp127 = udiv ubyte %tmp, %tmp118 ; [#uses=1]
+ %tmp127 = cast ubyte %tmp127 to ulong ; [#uses=1]
+ br label %cond_next129
+
+ cond_next129: ; preds = %cond_true120, %cond_true115
+ %iftmp.30.0 = phi ulong [ %tmp127, %cond_true120 ], [ 0, %cond_true115
]; [#uses=1]
+ %tmp132 = seteq ulong %iftmp.30.0, %tmp99 ;
[#uses=1]
+ br bool %tmp132, label %cond_false148, label %cond_next136
+
+ cond_next136: ; preds = %cond_next129, %bb77
+ ret void
+
+ cond_false148:; preds = %cond_next129
+ ret void
+ }
___
llvm-commits mailing list
llvm-commits@cs.uiuc.edu
http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
[llvm-commits] CVS: llvm/lib/Target/X86/X86RegisterInfo.cpp
Changes in directory llvm/lib/Target/X86: X86RegisterInfo.cpp updated: 1.179 -> 1.180 --- Log message: Hopefully a good crack at making debugging work on intel -disable-fp-elim. --- Diffs of the changes: (+3 -1) X86RegisterInfo.cpp |4 +++- 1 files changed, 3 insertions(+), 1 deletion(-) Index: llvm/lib/Target/X86/X86RegisterInfo.cpp diff -u llvm/lib/Target/X86/X86RegisterInfo.cpp:1.179 llvm/lib/Target/X86/X86RegisterInfo.cpp:1.180 --- llvm/lib/Target/X86/X86RegisterInfo.cpp:1.179 Thu Nov 16 17:33:25 2006 +++ llvm/lib/Target/X86/X86RegisterInfo.cpp Fri Nov 17 15:19:15 2006 @@ -1029,7 +1029,9 @@ // Get the offset of the stack slot for the EBP register... which is // guaranteed to be the last slot by processFunctionBeforeFrameFinalized. int EBPOffset = MFI->getObjectOffset(MFI->getObjectIndexBegin())+SlotSize; - +// Update the frame offset adjustment. +MFI->setOffsetAdjustment(SlotSize-NumBytes); + // Save EBP into the appropriate stack slot... // mov [ESP-], EBP MI = addRegOffset(BuildMI(TII, Is64Bit ? X86::MOV64mr : X86::MOV32mr, 5), ___ llvm-commits mailing list llvm-commits@cs.uiuc.edu http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
[llvm-commits] CVS: llvm/lib/Target/MRegisterInfo.cpp
Changes in directory llvm/lib/Target: MRegisterInfo.cpp updated: 1.16 -> 1.17 --- Log message: Hopefully a good crack at making debugging work on intel -disable-fp-elim. --- Diffs of the changes: (+2 -1) MRegisterInfo.cpp |3 ++- 1 files changed, 2 insertions(+), 1 deletion(-) Index: llvm/lib/Target/MRegisterInfo.cpp diff -u llvm/lib/Target/MRegisterInfo.cpp:1.16 llvm/lib/Target/MRegisterInfo.cpp:1.17 --- llvm/lib/Target/MRegisterInfo.cpp:1.16 Thu Aug 3 12:27:09 2006 +++ llvm/lib/Target/MRegisterInfo.cpp Fri Nov 17 15:19:15 2006 @@ -57,7 +57,8 @@ ML.set(getFrameRegister(MF), MFI->getObjectOffset(Index) + MFI->getStackSize() - - TFI.getOffsetOfLocalArea()); + TFI.getOffsetOfLocalArea() + + MFI->getOffsetAdjustment()); } /// getInitialFrameState - Returns a list of machine moves that are assumed ___ llvm-commits mailing list llvm-commits@cs.uiuc.edu http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
[llvm-commits] CVS: llvm/include/llvm/CodeGen/MachineFrameInfo.h
Changes in directory llvm/include/llvm/CodeGen:
MachineFrameInfo.h updated: 1.20 -> 1.21
---
Log message:
Hopefully a good crack at making debugging work on intel -disable-fp-elim.
---
Diffs of the changes: (+17 -1)
MachineFrameInfo.h | 18 +-
1 files changed, 17 insertions(+), 1 deletion(-)
Index: llvm/include/llvm/CodeGen/MachineFrameInfo.h
diff -u llvm/include/llvm/CodeGen/MachineFrameInfo.h:1.20
llvm/include/llvm/CodeGen/MachineFrameInfo.h:1.21
--- llvm/include/llvm/CodeGen/MachineFrameInfo.h:1.20 Fri Aug 25 17:56:30 2006
+++ llvm/include/llvm/CodeGen/MachineFrameInfo.hFri Nov 17 15:19:15 2006
@@ -112,6 +112,14 @@
///
unsigned StackSize;
+ /// OffsetAdjustment - The amount that a frame offset needs to be adjusted to
+ /// have the actual offset from the stack/frame pointer. The calculation is
+ /// MFI->getObjectOffset(Index) + StackSize - TFI.getOffsetOfLocalArea() +
+ /// OffsetAdjustment. If OffsetAdjustment is zero (default) then offsets are
+ /// away from TOS. If OffsetAdjustment == StackSize then offsets are toward
+ /// TOS.
+ int OffsetAdjustment;
+
/// MaxAlignment - The prolog/epilog code inserter may process objects
/// that require greater alignment than the default alignment the target
/// provides. To handle this, MaxAlignment is set to the maximum alignment
@@ -148,7 +156,7 @@
public:
MachineFrameInfo() {
-NumFixedObjects = StackSize = MaxAlignment = 0;
+NumFixedObjects = StackSize = OffsetAdjustment = MaxAlignment = 0;
HasVarSizedObjects = false;
HasCalls = false;
MaxCallFrameSize = 0;
@@ -212,6 +220,14 @@
/// setStackSize - Set the size of the stack...
///
void setStackSize(unsigned Size) { StackSize = Size; }
+
+ /// getOffsetAdjustment - Return the correction for frame offsets.
+ ///
+ int getOffsetAdjustment() const { return OffsetAdjustment; }
+
+ /// setOffsetAdjustment - Set the correction for frame offsets.
+ ///
+ void setOffsetAdjustment(int Adj) { OffsetAdjustment = Adj; }
/// getMaxAlignment - Return the alignment in bytes that this function must
be
/// aligned to, which is greater than the default stack alignment provided
by
___
llvm-commits mailing list
llvm-commits@cs.uiuc.edu
http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
[llvm-commits] CVS: llvm-test/SingleSource/Benchmarks/Shootout-C++/sieve.cpp
Changes in directory llvm-test/SingleSource/Benchmarks/Shootout-C++:
sieve.cpp updated: 1.2 -> 1.3
---
Log message:
Fix indentation of this program, remove tabs. No functional change.
---
Diffs of the changes: (+26 -27)
sieve.cpp | 53 ++---
1 files changed, 26 insertions(+), 27 deletions(-)
Index: llvm-test/SingleSource/Benchmarks/Shootout-C++/sieve.cpp
diff -u llvm-test/SingleSource/Benchmarks/Shootout-C++/sieve.cpp:1.2
llvm-test/SingleSource/Benchmarks/Shootout-C++/sieve.cpp:1.3
--- llvm-test/SingleSource/Benchmarks/Shootout-C++/sieve.cpp:1.2Tue Jun
15 15:48:16 2004
+++ llvm-test/SingleSource/Benchmarks/Shootout-C++/sieve.cppFri Nov 17
15:22:26 2006
@@ -7,38 +7,37 @@
void sieve(list& unknown, vector& primes)
{
- while (!unknown.empty())
- {
- int p = unknown.front();
- unknown.pop_front();
- list::iterator i = unknown.begin();
- while (i != unknown.end())
- {
- if (*i % p)
- ++i;
- else
- i = unknown.erase(i);
- }
- primes.push_back(p);
- }
+ while (!unknown.empty())
+ {
+int p = unknown.front();
+unknown.pop_front();
+list::iterator i = unknown.begin();
+while (i != unknown.end())
+{
+ if (*i % p)
+++i;
+ else
+i = unknown.erase(i);
+}
+primes.push_back(p);
+ }
}
int main(int argc, char *argv[])
{
-size_t NUM = (argc == 2 ? (atoi(argv[1]) < 1 ? 1 : atoi(argv[1])):
- 500);
+ size_t NUM = (argc == 2 ? (atoi(argv[1]) < 1 ? 1 : atoi(argv[1])): 500);
- vector primes;
+ vector primes;
- // run the sieve repeatedly
-while (NUM--) {
- list integers;
- for (int i = 2; i < 8192; ++i)
- integers.push_back(i);
- primes.clear();
- sieve(integers, primes);
-}
+ // run the sieve repeatedly
+ while (NUM--) {
+list integers;
+for (int i = 2; i < 8192; ++i)
+ integers.push_back(i);
+primes.clear();
+sieve(integers, primes);
+ }
-cout << "Count: " << primes.size() << endl;
- return 0;
+ cout << "Count: " << primes.size() << endl;
+ return 0;
}
___
llvm-commits mailing list
llvm-commits@cs.uiuc.edu
http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
[llvm-commits] CVS: llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
Changes in directory llvm/lib/Target/X86:
X86ISelDAGToDAG.cpp updated: 1.128 -> 1.129
---
Log message:
For unsigned 8-bit division. Use movzbw to set the lower 8 bits of AX while
clearing the upper 8-bits instead of issuing two instructions. This also
eliminates the need to target the AH register which can be problematic on
x86-64.
---
Diffs of the changes: (+46 -29)
X86ISelDAGToDAG.cpp | 75 +++-
1 files changed, 46 insertions(+), 29 deletions(-)
Index: llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
diff -u llvm/lib/Target/X86/X86ISelDAGToDAG.cpp:1.128
llvm/lib/Target/X86/X86ISelDAGToDAG.cpp:1.129
--- llvm/lib/Target/X86/X86ISelDAGToDAG.cpp:1.128 Fri Nov 17 01:52:03 2006
+++ llvm/lib/Target/X86/X86ISelDAGToDAG.cpp Fri Nov 17 16:10:14 2006
@@ -1141,7 +1141,7 @@
default: assert(0 && "Unsupported VT!");
case MVT::i8:
LoReg = X86::AL; HiReg = X86::AH;
-ClrOpcode = X86::MOV8r0;
+ClrOpcode = 0;
SExtOpcode = X86::CBW;
break;
case MVT::i16:
@@ -1163,53 +1163,70 @@
SDOperand N0 = Node->getOperand(0);
SDOperand N1 = Node->getOperand(1);
-
- bool foldedLoad = false;
- SDOperand Tmp0, Tmp1, Tmp2, Tmp3;
- foldedLoad = TryFoldLoad(N, N1, Tmp0, Tmp1, Tmp2, Tmp3);
- SDOperand Chain;
- if (foldedLoad) {
-Chain = N1.getOperand(0);
-AddToISelQueue(Chain);
- } else
-Chain = CurDAG->getEntryNode();
-
SDOperand InFlag(0, 0);
- AddToISelQueue(N0);
- Chain = CurDAG->getCopyToReg(Chain, CurDAG->getRegister(LoReg, NVT),
-N0, InFlag);
- InFlag = Chain.getValue(1);
-
- if (isSigned) {
-// Sign extend the low part into the high part.
-InFlag =
- SDOperand(CurDAG->getTargetNode(SExtOpcode, MVT::Flag, InFlag), 0);
- } else {
-// Zero out the high part, effectively zero extending the input.
-SDOperand ClrNode = SDOperand(CurDAG->getTargetNode(ClrOpcode, NVT),
0);
-Chain = CurDAG->getCopyToReg(Chain, CurDAG->getRegister(HiReg, NVT),
- ClrNode, InFlag);
+ if (NVT == MVT::i8 && !isSigned) {
+// Special case for div8, just use a move with zero extension to AX to
+// clear the upper 8 bits (AH).
+SDOperand Tmp0, Tmp1, Tmp2, Tmp3, Move, Chain;
+if (TryFoldLoad(N, N0, Tmp0, Tmp1, Tmp2, Tmp3)) {
+ SDOperand Ops[] = { Tmp0, Tmp1, Tmp2, Tmp3, N0.getOperand(0) };
+ AddToISelQueue(N0.getOperand(0));
+ AddToISelQueue(Tmp0);
+ AddToISelQueue(Tmp1);
+ AddToISelQueue(Tmp2);
+ AddToISelQueue(Tmp3);
+ Move =
+SDOperand(CurDAG->getTargetNode(X86::MOVZX16rm8, MVT::i16,
MVT::Other,
+Ops, 5), 0);
+ Chain = Move.getValue(1);
+ ReplaceUses(N0.getValue(1), Chain);
+} else {
+ AddToISelQueue(N0);
+ Move =
+SDOperand(CurDAG->getTargetNode(X86::MOVZX16rr8, MVT::i16, N0), 0);
+ Chain = CurDAG->getEntryNode();
+}
+Chain = CurDAG->getCopyToReg(Chain, X86::AX, Move, InFlag);
InFlag = Chain.getValue(1);
+ } else {
+AddToISelQueue(N0);
+InFlag =
+ CurDAG->getCopyToReg(CurDAG->getEntryNode(), LoReg, N0,
+ InFlag).getValue(1);
+if (isSigned) {
+ // Sign extend the low part into the high part.
+ InFlag =
+SDOperand(CurDAG->getTargetNode(SExtOpcode, MVT::Flag, InFlag), 0);
+} else {
+ // Zero out the high part, effectively zero extending the input.
+ SDOperand ClrNode = SDOperand(CurDAG->getTargetNode(ClrOpcode, NVT),
0);
+ InFlag = CurDAG->getCopyToReg(CurDAG->getEntryNode(), HiReg, ClrNode,
+InFlag).getValue(1);
+}
}
+ SDOperand Tmp0, Tmp1, Tmp2, Tmp3, Chain;
+ bool foldedLoad = TryFoldLoad(N, N1, Tmp0, Tmp1, Tmp2, Tmp3);
if (foldedLoad) {
+AddToISelQueue(N1.getOperand(0));
AddToISelQueue(Tmp0);
AddToISelQueue(Tmp1);
AddToISelQueue(Tmp2);
AddToISelQueue(Tmp3);
-SDOperand Ops[] = { Tmp0, Tmp1, Tmp2, Tmp3, Chain, InFlag };
+SDOperand Ops[] = { Tmp0, Tmp1, Tmp2, Tmp3, N1.getOperand(0), InFlag };
SDNode *CNode =
CurDAG->getTargetNode(MOpc, MVT::Other, MVT::Flag, Ops, 6);
Chain = SDOperand(CNode, 0);
InFlag = SDOperand(CNode, 1);
} else {
AddToISelQueue(N1);
+Chain = CurDAG->getEntryNode();
InFlag =
SDOperand(CurDAG->getTargetNode(Opc, MVT::Flag, N1, InFlag), 0);
}
- SDOperand Result = CurDAG->getCopyFromReg(Chain, isDiv ? LoReg : HiReg,
-NVT, InFlag);
+ SDOperand Result
[llvm-commits] CVS: llvm/lib/Target/PowerPC/PPCBranchSelector.cpp PPCISelDAGToDAG.cpp PPCISelLowering.cpp PPCInstrInfo.cpp PPCInstrInfo.td
Changes in directory llvm/lib/Target/PowerPC:
PPCBranchSelector.cpp updated: 1.35 -> 1.36
PPCISelDAGToDAG.cpp updated: 1.222 -> 1.223
PPCISelLowering.cpp updated: 1.229 -> 1.230
PPCInstrInfo.cpp updated: 1.32 -> 1.33
PPCInstrInfo.td updated: 1.267 -> 1.268
---
Log message:
rename PPC::COND_BRANCH to PPC::BCC
---
Diffs of the changes: (+18 -17)
PPCBranchSelector.cpp |6 +++---
PPCISelDAGToDAG.cpp |2 +-
PPCISelLowering.cpp |2 +-
PPCInstrInfo.cpp | 14 +++---
PPCInstrInfo.td | 11 ++-
5 files changed, 18 insertions(+), 17 deletions(-)
Index: llvm/lib/Target/PowerPC/PPCBranchSelector.cpp
diff -u llvm/lib/Target/PowerPC/PPCBranchSelector.cpp:1.35
llvm/lib/Target/PowerPC/PPCBranchSelector.cpp:1.36
--- llvm/lib/Target/PowerPC/PPCBranchSelector.cpp:1.35 Fri Nov 17 16:10:59 2006
+++ llvm/lib/Target/PowerPC/PPCBranchSelector.cpp Fri Nov 17 16:14:47 2006
@@ -54,7 +54,7 @@
///
static unsigned getNumBytesForInstruction(MachineInstr *MI) {
switch (MI->getOpcode()) {
- case PPC::COND_BRANCH:
+ case PPC::BCC:
// while this will be 4 most of the time, if we emit 8 it is just a
// minor pessimization that saves us from having to worry about
// keeping the offsets up to date later when we emit long branch glue.
@@ -116,7 +116,7 @@
// We may end up deleting the MachineInstr that MBBI points to, so
// remember its opcode now so we can refer to it after calling erase()
unsigned ByteSize = getNumBytesForInstruction(MBBI);
- if (MBBI->getOpcode() != PPC::COND_BRANCH) {
+ if (MBBI->getOpcode() != PPC::BCC) {
ByteCount += ByteSize;
continue;
}
@@ -159,7 +159,7 @@
MBBJ = BuildMI(*MBB, MBBI, PPC::B, 1).addMBB(DestMBB);
}
- // Erase the psuedo COND_BRANCH instruction, and then back up the
+ // Erase the psuedo BCC instruction, and then back up the
// iterator so that when the for loop increments it, we end up in
// the correct place rather than iterating off the end.
MBB->erase(MBBI);
Index: llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp
diff -u llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp:1.222
llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp:1.223
--- llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp:1.222 Fri Nov 17 16:10:59 2006
+++ llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp Fri Nov 17 16:14:47 2006
@@ -1007,7 +1007,7 @@
SDOperand CondCode = SelectCC(N->getOperand(2), N->getOperand(3), CC);
SDOperand Ops[] = { CondCode, getI32Imm(getPredicateForSetCC(CC)),
N->getOperand(4), N->getOperand(0) };
-return CurDAG->SelectNodeTo(N, PPC::COND_BRANCH, MVT::Other, Ops, 4);
+return CurDAG->SelectNodeTo(N, PPC::BCC, MVT::Other, Ops, 4);
}
case ISD::BRIND: {
// FIXME: Should custom lower this.
Index: llvm/lib/Target/PowerPC/PPCISelLowering.cpp
diff -u llvm/lib/Target/PowerPC/PPCISelLowering.cpp:1.229
llvm/lib/Target/PowerPC/PPCISelLowering.cpp:1.230
--- llvm/lib/Target/PowerPC/PPCISelLowering.cpp:1.229 Fri Nov 17 16:10:59 2006
+++ llvm/lib/Target/PowerPC/PPCISelLowering.cpp Fri Nov 17 16:14:47 2006
@@ -2613,7 +2613,7 @@
MachineBasicBlock *copy0MBB = new MachineBasicBlock(LLVM_BB);
MachineBasicBlock *sinkMBB = new MachineBasicBlock(LLVM_BB);
unsigned SelectPred = MI->getOperand(4).getImm();
- BuildMI(BB, PPC::COND_BRANCH, 3)
+ BuildMI(BB, PPC::BCC, 3)
.addReg(MI->getOperand(1).getReg()).addImm(SelectPred).addMBB(sinkMBB);
MachineFunction *F = BB->getParent();
F->getBasicBlockList().insert(It, copy0MBB);
Index: llvm/lib/Target/PowerPC/PPCInstrInfo.cpp
diff -u llvm/lib/Target/PowerPC/PPCInstrInfo.cpp:1.32
llvm/lib/Target/PowerPC/PPCInstrInfo.cpp:1.33
--- llvm/lib/Target/PowerPC/PPCInstrInfo.cpp:1.32 Fri Nov 17 16:10:59 2006
+++ llvm/lib/Target/PowerPC/PPCInstrInfo.cppFri Nov 17 16:14:47 2006
@@ -192,7 +192,7 @@
if (LastInst->getOpcode() == PPC::B) {
TBB = LastInst->getOperand(0).getMachineBasicBlock();
return false;
-} else if (LastInst->getOpcode() == PPC::COND_BRANCH) {
+} else if (LastInst->getOpcode() == PPC::BCC) {
// Block ends with fall-through condbranch.
TBB = LastInst->getOperand(2).getMachineBasicBlock();
Cond.push_back(LastInst->getOperand(0));
@@ -211,8 +211,8 @@
isTerminatorInstr((--I)->getOpcode()))
return true;
- // If the block ends with PPC::B and PPC:COND_BRANCH, handle it.
- if (SecondLastInst->getOpcode() == PPC::COND_BRANCH &&
+ // If the block ends with PPC::B and PPC:BCC, handle it.
+ if (SecondLastInst->getOpcode() == PPC::BCC &&
LastInst->getOpcode() == PPC::B) {
TBB = SecondLastInst->getOperand(2).getMachineBasicBlock();
Cond.push_back(SecondLastInst->getOperand(0));
@@ -229,7 +229,7 @@
MachineBasicBlock::iterator I = MBB.end();
if (I == MBB.begin()) return;
--I;
- if (I->getOpcode() != PPC::B && I->getOpcode() != PPC::COND_BRANCH)
+ if (I->
[llvm-commits] CVS: llvm/lib/Target/PowerPC/PPCPredicates.cpp PPCPredicates.h PPC.h PPCAsmPrinter.cpp PPCBranchSelector.cpp PPCISelDAGToDAG.cpp PPCISelLowering.cpp PPCInstrInfo.cpp PPCInstrInfo.h PPCI
Changes in directory llvm/lib/Target/PowerPC:
PPCPredicates.cpp added (r1.1)
PPCPredicates.h added (r1.1)
PPC.h updated: 1.36 -> 1.37
PPCAsmPrinter.cpp updated: 1.208 -> 1.209
PPCBranchSelector.cpp updated: 1.34 -> 1.35
PPCISelDAGToDAG.cpp updated: 1.221 -> 1.222
PPCISelLowering.cpp updated: 1.228 -> 1.229
PPCInstrInfo.cpp updated: 1.31 -> 1.32
PPCInstrInfo.h updated: 1.19 -> 1.20
PPCInstrInfo.td updated: 1.266 -> 1.267
---
Log message:
start using PPC predicates more consistently.
---
Diffs of the changes: (+118 -60)
PPC.h | 15 ---
PPCAsmPrinter.cpp |1 +
PPCBranchSelector.cpp | 28 +++-
PPCISelDAGToDAG.cpp | 26 --
PPCISelLowering.cpp | 16 +---
PPCInstrInfo.cpp |3 ++-
PPCInstrInfo.h| 16
PPCInstrInfo.td |4 ++--
PPCPredicates.cpp | 30 ++
PPCPredicates.h | 39 +++
10 files changed, 118 insertions(+), 60 deletions(-)
Index: llvm/lib/Target/PowerPC/PPCPredicates.cpp
diff -c /dev/null llvm/lib/Target/PowerPC/PPCPredicates.cpp:1.1
*** /dev/null Fri Nov 17 16:11:09 2006
--- llvm/lib/Target/PowerPC/PPCPredicates.cpp Fri Nov 17 16:10:59 2006
***
*** 0
--- 1,30
+ //===-- PPCPredicates.cpp - PPC Branch Predicate Information
--===//
+ //
+ // The LLVM Compiler Infrastructure
+ //
+ // This file was developed by Chris Lattner and is distributed under
+ // the University of Illinois Open Source License. See LICENSE.TXT for
details.
+ //
+
//===--===//
+ //
+ // This file implements the PowerPC branch predicates.
+ //
+
//===--===//
+
+ #include "PPCPredicates.h"
+ #include
+ using namespace llvm;
+
+ PPC::Predicate PPC::InvertPredicate(PPC::Predicate Opcode) {
+ switch (Opcode) {
+ default: assert(0 && "Unknown PPC branch opcode!");
+ case PPC::PRED_EQ: return PPC::PRED_NE;
+ case PPC::PRED_NE: return PPC::PRED_EQ;
+ case PPC::PRED_LT: return PPC::PRED_GE;
+ case PPC::PRED_GE: return PPC::PRED_LT;
+ case PPC::PRED_GT: return PPC::PRED_LE;
+ case PPC::PRED_LE: return PPC::PRED_GT;
+ case PPC::PRED_NU: return PPC::PRED_UN;
+ case PPC::PRED_UN: return PPC::PRED_NU;
+ }
+ }
Index: llvm/lib/Target/PowerPC/PPCPredicates.h
diff -c /dev/null llvm/lib/Target/PowerPC/PPCPredicates.h:1.1
*** /dev/null Fri Nov 17 16:11:14 2006
--- llvm/lib/Target/PowerPC/PPCPredicates.h Fri Nov 17 16:10:59 2006
***
*** 0
--- 1,39
+ //===-- PPCPredicates.h - PPC Branch Predicate Information --*- C++
-*-===//
+ //
+ // The LLVM Compiler Infrastructure
+ //
+ // This file was developed by Chris Lattner and is distributed under
+ // the University of Illinois Open Source License. See LICENSE.TXT for
details.
+ //
+
//===--===//
+ //
+ // This file describes the PowerPC branch predicates.
+ //
+
//===--===//
+
+ #ifndef LLVM_TARGET_POWERPC_PPCPREDICATES_H
+ #define LLVM_TARGET_POWERPC_PPCPREDICATES_H
+
+ #include "PPC.h"
+
+ namespace llvm {
+ namespace PPC {
+ /// Predicate - These are "(BI << 5) | BO" for various predicates.
+ enum Predicate {
+ PRED_ALWAYS = (0 << 5) | 20,
+ PRED_LT = (0 << 5) | 12,
+ PRED_LE = (1 << 5) | 4,
+ PRED_EQ = (2 << 5) | 12,
+ PRED_GE = (0 << 5) | 4,
+ PRED_GT = (1 << 5) | 12,
+ PRED_NE = (2 << 5) | 4,
+ PRED_UN = (3 << 5) | 12,
+ PRED_NU = (3 << 5) | 4
+ };
+
+ /// Invert the specified predicate. != -> ==, < -> >=.
+ Predicate InvertPredicate(Predicate Opcode);
+ }
+ }
+
+ #endif
Index: llvm/lib/Target/PowerPC/PPC.h
diff -u llvm/lib/Target/PowerPC/PPC.h:1.36 llvm/lib/Target/PowerPC/PPC.h:1.37
--- llvm/lib/Target/PowerPC/PPC.h:1.36 Fri Nov 3 23:42:48 2006
+++ llvm/lib/Target/PowerPC/PPC.h Fri Nov 17 16:10:59 2006
@@ -27,21 +27,6 @@
class FunctionPass;
class MachineCodeEmitter;
- namespace PPC {
-/// Predicate - These are "(BI << 5) | BO" for various predicates.
-enum Predicate {
- PRED_ALWAYS = (0 << 5) | 20,
- PRED_LT = (0 << 5) | 12,
- PRED_LE = (1 << 5) | 4,
- PRED_EQ = (2 << 5) | 12,
- PRED_GE = (0 << 5) | 4,
- PRED_GT = (1 << 5) | 12,
- PRED_NE = (2 << 5) | 4,
- PRED_UN = (3 << 5) | 12,
- PRED_NU = (3 << 5) | 4
-};
- }
-
FunctionPass *createPPCBranchSelectionPass();
FunctionPass *createPPCISelDag(PPCTargetMachine &TM);
FunctionPass *createPPCAsmPrinterPass(std::ostream &OS,
Index: llvm/lib/Target/PowerPC/PPCAsmPrinter.cpp
diff -u llvm/lib/Target/PowerPC/P
[llvm-commits] CVS: llvm/lib/Target/PowerPC/PPCBranchSelector.cpp PPCISelDAGToDAG.cpp PPCISelLowering.cpp PPCInstrInfo.cpp PPCInstrInfo.td
Changes in directory llvm/lib/Target/PowerPC:
PPCBranchSelector.cpp updated: 1.36 -> 1.37
PPCISelDAGToDAG.cpp updated: 1.223 -> 1.224
PPCISelLowering.cpp updated: 1.230 -> 1.231
PPCInstrInfo.cpp updated: 1.33 -> 1.34
PPCInstrInfo.td updated: 1.268 -> 1.269
---
Log message:
convert PPC::BCC to use the 'pred' operand instead of separate predicate
value and CR reg #. This requires swapping the order of these everywhere
that touches BCC and requires us to write custom matching logic for
PPCcondbranch :(
---
Diffs of the changes: (+25 -14)
PPCBranchSelector.cpp |4 ++--
PPCISelDAGToDAG.cpp | 12 +++-
PPCISelLowering.cpp |4 ++--
PPCInstrInfo.cpp |6 +++---
PPCInstrInfo.td | 13 +++--
5 files changed, 25 insertions(+), 14 deletions(-)
Index: llvm/lib/Target/PowerPC/PPCBranchSelector.cpp
diff -u llvm/lib/Target/PowerPC/PPCBranchSelector.cpp:1.36
llvm/lib/Target/PowerPC/PPCBranchSelector.cpp:1.37
--- llvm/lib/Target/PowerPC/PPCBranchSelector.cpp:1.36 Fri Nov 17 16:14:47 2006
+++ llvm/lib/Target/PowerPC/PPCBranchSelector.cpp Fri Nov 17 16:37:34 2006
@@ -126,8 +126,8 @@
// 1. PPC branch opcode
// 2. Target MBB
MachineBasicBlock *DestMBB = MBBI->getOperand(2).getMachineBasicBlock();
- PPC::Predicate Pred = (PPC::Predicate)MBBI->getOperand(1).getImm();
- unsigned CRReg = MBBI->getOperand(0).getReg();
+ PPC::Predicate Pred = (PPC::Predicate)MBBI->getOperand(0).getImm();
+ unsigned CRReg = MBBI->getOperand(1).getReg();
int Displacement = OffsetMap[DestMBB->getNumber()] - ByteCount;
bool ShortBranchOk = Displacement >= -32768 && Displacement <= 32767;
Index: llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp
diff -u llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp:1.223
llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp:1.224
--- llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp:1.223 Fri Nov 17 16:14:47 2006
+++ llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp Fri Nov 17 16:37:34 2006
@@ -1001,11 +1001,21 @@
getI32Imm(BROpc) };
return CurDAG->SelectNodeTo(N, SelectCCOp, N->getValueType(0), Ops, 4);
}
+ case PPCISD::COND_BRANCH: {
+AddToISelQueue(N->getOperand(0)); // Op #0 is the Chain.
+// Op #1 is the PPC::PRED_* number.
+// Op #2 is the CR#
+// Op #3 is the Dest MBB
+AddToISelQueue(N->getOperand(4)); // Op #4 is the Flag.
+SDOperand Ops[] = { N->getOperand(1), N->getOperand(2), N->getOperand(3),
+ N->getOperand(0), N->getOperand(4) };
+return CurDAG->SelectNodeTo(N, PPC::BCC, MVT::Other, Ops, 5);
+ }
case ISD::BR_CC: {
AddToISelQueue(N->getOperand(0));
ISD::CondCode CC = cast(N->getOperand(1))->get();
SDOperand CondCode = SelectCC(N->getOperand(2), N->getOperand(3), CC);
-SDOperand Ops[] = { CondCode, getI32Imm(getPredicateForSetCC(CC)),
+SDOperand Ops[] = { getI32Imm(getPredicateForSetCC(CC)), CondCode,
N->getOperand(4), N->getOperand(0) };
return CurDAG->SelectNodeTo(N, PPC::BCC, MVT::Other, Ops, 4);
}
Index: llvm/lib/Target/PowerPC/PPCISelLowering.cpp
diff -u llvm/lib/Target/PowerPC/PPCISelLowering.cpp:1.230
llvm/lib/Target/PowerPC/PPCISelLowering.cpp:1.231
--- llvm/lib/Target/PowerPC/PPCISelLowering.cpp:1.230 Fri Nov 17 16:14:47 2006
+++ llvm/lib/Target/PowerPC/PPCISelLowering.cpp Fri Nov 17 16:37:34 2006
@@ -2614,7 +2614,7 @@
MachineBasicBlock *sinkMBB = new MachineBasicBlock(LLVM_BB);
unsigned SelectPred = MI->getOperand(4).getImm();
BuildMI(BB, PPC::BCC, 3)
-.addReg(MI->getOperand(1).getReg()).addImm(SelectPred).addMBB(sinkMBB);
+.addImm(SelectPred).addReg(MI->getOperand(1).getReg()).addMBB(sinkMBB);
MachineFunction *F = BB->getParent();
F->getBasicBlockList().insert(It, copy0MBB);
F->getBasicBlockList().insert(It, sinkMBB);
@@ -2890,8 +2890,8 @@
}
return DAG.getNode(PPCISD::COND_BRANCH, MVT::Other, N->getOperand(0),
- DAG.getRegister(PPC::CR6, MVT::i32),
DAG.getConstant(CompOpc, MVT::i32),
+ DAG.getRegister(PPC::CR6, MVT::i32),
N->getOperand(4), CompNode.getValue(1));
}
break;
Index: llvm/lib/Target/PowerPC/PPCInstrInfo.cpp
diff -u llvm/lib/Target/PowerPC/PPCInstrInfo.cpp:1.33
llvm/lib/Target/PowerPC/PPCInstrInfo.cpp:1.34
--- llvm/lib/Target/PowerPC/PPCInstrInfo.cpp:1.33 Fri Nov 17 16:14:47 2006
+++ llvm/lib/Target/PowerPC/PPCInstrInfo.cppFri Nov 17 16:37:34 2006
@@ -260,13 +260,13 @@
BuildMI(&MBB, PPC::B, 1).addMBB(TBB);
else// Conditional branch
BuildMI(&MBB, PPC::BCC, 3)
-.addReg(Cond[0].getReg()).addImm(Cond[1].getImm()).addMBB(TBB);
+.addImm(Cond[0].getImm()).addReg(Cond[1].getReg()).addMBB(TBB);
return;
}
// Two-way Conditional Branch.
BuildMI(&MBB, PPC::BCC, 3)
-.addReg(Cond[0].getReg()).addImm(Cond[1].getImm()).addMBB(TBB);
+.addImm
[llvm-commits] CVS: llvm/lib/Target/PowerPC/PPCInstrInfo.td PPCInstrFormats.td
Changes in directory llvm/lib/Target/PowerPC:
PPCInstrInfo.td updated: 1.269 -> 1.270
PPCInstrFormats.td updated: 1.84 -> 1.85
---
Log message:
add encoding for BCC, after finally wrestling strange ppc/tblgen endianness
issues to the ground.
---
Diffs of the changes: (+22 -3)
PPCInstrFormats.td | 18 ++
PPCInstrInfo.td|7 ---
2 files changed, 22 insertions(+), 3 deletions(-)
Index: llvm/lib/Target/PowerPC/PPCInstrInfo.td
diff -u llvm/lib/Target/PowerPC/PPCInstrInfo.td:1.269
llvm/lib/Target/PowerPC/PPCInstrInfo.td:1.270
--- llvm/lib/Target/PowerPC/PPCInstrInfo.td:1.269 Fri Nov 17 16:37:34 2006
+++ llvm/lib/Target/PowerPC/PPCInstrInfo.td Fri Nov 17 17:53:28 2006
@@ -361,10 +361,11 @@
// BCC represents an arbitrary conditional branch on a predicate.
// FIXME: should be able to write a pattern for PPCcondbranch, but can't use
// a two-value operand where a dag node expects two operands. :(
- def BCC : Pseudo<(ops pred:$cond, target:$dst),
- "b${cond:cc} ${cond:reg}, $dst",
- [/*(PPCcondbranch CRRC:$crS, imm:$opc, bb:$dst)*/]>;
+ def BCC : CBForm<16, 0, 0, (ops pred:$cond, target:$dst),
+ "b${cond:cc} ${cond:reg}, $dst"
+ /*[(PPCcondbranch CRRC:$crS, imm:$opc, bb:$dst)]*/>;
+// REMOVE BForm when these go away.
def BLT : BForm<16, 0, 0, 12, 0, (ops CRRC:$crS, target:$block),
"blt $crS, $block", BrB>;
def BLE : BForm<16, 0, 0, 4, 1, (ops CRRC:$crS, target:$block),
Index: llvm/lib/Target/PowerPC/PPCInstrFormats.td
diff -u llvm/lib/Target/PowerPC/PPCInstrFormats.td:1.84
llvm/lib/Target/PowerPC/PPCInstrFormats.td:1.85
--- llvm/lib/Target/PowerPC/PPCInstrFormats.td:1.84 Wed Nov 15 17:24:18 2006
+++ llvm/lib/Target/PowerPC/PPCInstrFormats.td Fri Nov 17 17:53:28 2006
@@ -74,6 +74,24 @@
let Inst{31}= lk;
}
+class CBForm opcode, bit aa, bit lk, dag OL,
+ string asmstr> : I {
+ bits<7> BIBO; // 2 bits of BI and 5 bits of BO.
+ bits<3> CR;
+ bits<14> BD;
+
+ bits<5> BI;
+ let BI{0-1} = BIBO{5-6};
+ let BI{2-4} = CR{0-2};
+
+ let Inst{6-10} = BIBO{4-0};
+ let Inst{11-15} = BI;
+ let Inst{16-29} = BD;
+ let Inst{30}= aa;
+ let Inst{31}= lk;
+}
+
+
// 1.7.4 D-Form
class DForm_base opcode, dag OL, string asmstr, InstrItinClass itin,
list pattern>
___
llvm-commits mailing list
llvm-commits@cs.uiuc.edu
http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
[llvm-commits] CVS: llvm/lib/Target/PowerPC/PPCBranchSelector.cpp PPCInstrFormats.td PPCInstrInfo.td README.txt
Changes in directory llvm/lib/Target/PowerPC:
PPCBranchSelector.cpp updated: 1.37 -> 1.38
PPCInstrFormats.td updated: 1.85 -> 1.86
PPCInstrInfo.td updated: 1.270 -> 1.271
README.txt updated: 1.105 -> 1.106
---
Log message:
Rewrite the branch selector to be correct in the face of large functions.
The algorithm it used before wasn't 100% correct, we now use an iterative
expansion model. This fixes assembler errors when compiling 403.gcc with
tail merging enabled.
Change the way the branch selector works overall: Now, the isel generates
PPC::BCC instructions (as it used to) directly, and these BCC instructions
are emitted to the output or jitted directly if branches don't need
expansion. Only if branches need expansion are instructions rewritten
and created. This should make branch select faster, and eliminates the
Bxx instructions from the .td file.
---
Diffs of the changes: (+108 -128)
PPCBranchSelector.cpp | 189 +++---
PPCInstrFormats.td| 18
PPCInstrInfo.td | 24 --
README.txt|5 -
4 files changed, 108 insertions(+), 128 deletions(-)
Index: llvm/lib/Target/PowerPC/PPCBranchSelector.cpp
diff -u llvm/lib/Target/PowerPC/PPCBranchSelector.cpp:1.37
llvm/lib/Target/PowerPC/PPCBranchSelector.cpp:1.38
--- llvm/lib/Target/PowerPC/PPCBranchSelector.cpp:1.37 Fri Nov 17 16:37:34 2006
+++ llvm/lib/Target/PowerPC/PPCBranchSelector.cpp Fri Nov 17 18:32:03 2006
@@ -24,6 +24,7 @@
#include "llvm/Target/TargetAsmInfo.h"
#include "llvm/ADT/Statistic.h"
#include "llvm/Support/Compiler.h"
+#include "llvm/Support/MathExtras.h"
using namespace llvm;
static Statistic<> NumExpanded("ppc-branch-select",
@@ -31,13 +32,13 @@
namespace {
struct VISIBILITY_HIDDEN PPCBSel : public MachineFunctionPass {
-/// OffsetMap - Mapping between BB # and byte offset from start of
function.
-std::vector OffsetMap;
+/// BlockSizes - The sizes of the basic blocks in the function.
+std::vector BlockSizes;
virtual bool runOnMachineFunction(MachineFunction &Fn);
virtual const char *getPassName() const {
- return "PowerPC Branch Selection";
+ return "PowerPC Branch Selector";
}
};
}
@@ -54,11 +55,6 @@
///
static unsigned getNumBytesForInstruction(MachineInstr *MI) {
switch (MI->getOpcode()) {
- case PPC::BCC:
-// while this will be 4 most of the time, if we emit 8 it is just a
-// minor pessimization that saves us from having to worry about
-// keeping the offsets up to date later when we emit long branch glue.
-return 8;
case PPC::IMPLICIT_DEF_GPRC: // no asm emitted
case PPC::IMPLICIT_DEF_G8RC: // no asm emitted
case PPC::IMPLICIT_DEF_F4: // no asm emitted
@@ -77,98 +73,119 @@
bool PPCBSel::runOnMachineFunction(MachineFunction &Fn) {
- // Running total of instructions encountered since beginning of function
- unsigned ByteCount = 0;
-
- OffsetMap.resize(Fn.getNumBlockIDs());
-
- // For each MBB, add its offset to the offset map, and count up its
- // instructions
+ // Give the blocks of the function a dense, in-order, numbering.
+ Fn.RenumberBlocks();
+ BlockSizes.resize(Fn.getNumBlockIDs());
+
+ // Measure each MBB and compute a size for the entire function.
+ unsigned FuncSize = 0;
for (MachineFunction::iterator MFI = Fn.begin(), E = Fn.end(); MFI != E;
++MFI) {
MachineBasicBlock *MBB = MFI;
-OffsetMap[MBB->getNumber()] = ByteCount;
-
+
+unsigned BlockSize = 0;
for (MachineBasicBlock::iterator MBBI = MBB->begin(), EE = MBB->end();
MBBI != EE; ++MBBI)
- ByteCount += getNumBytesForInstruction(MBBI);
+ BlockSize += getNumBytesForInstruction(MBBI);
+
+BlockSizes[MBB->getNumber()] = BlockSize;
+FuncSize += BlockSize;
}
- // We're about to run over the MBB's again, so reset the ByteCount
- ByteCount = 0;
+ // If the entire function is smaller than the displacement of a branch field,
+ // we know we don't need to shrink any branches in this function. This is a
+ // common case.
+ if (FuncSize < (1 << 15)) {
+BlockSizes.clear();
+return false;
+ }
- // For each MBB, find the conditional branch pseudo instructions, and
- // calculate the difference between the target MBB and the current ICount
- // to decide whether or not to emit a short or long branch.
- //
- // short branch:
- // bCC .L_TARGET_MBB
+ // For each conditional branch, if the offset to its destination is larger
+ // than the offset field allows, transform it into a long branch sequence
+ // like this:
+ // short branch:
+ // bCC MBB
+ // long branch:
+ // b!CC $PC+8
+ // b MBB
//
- // long branch:
- // bInverseCC $PC+8
- // b .L_TARGET_MBB
- for (MachineFunction::iterator MFI = Fn.begin(), E = Fn.end(); MFI != E;
- ++MFI) {
-MachineBasicBlock *MBB = MFI;
-
-for (MachineBasicBlock::iterator MBBI = MBB->begin(), EE = MBB->end();
-
[llvm-commits] CVS: llvm/lib/Target/PowerPC/PPCAsmPrinter.cpp
Changes in directory llvm/lib/Target/PowerPC:
PPCAsmPrinter.cpp updated: 1.209 -> 1.210
---
Log message:
Pretty print 'rldicr r2, r2, 2, 61' as 'sldi r2, r2, 2'.
---
Diffs of the changes: (+12 -0)
PPCAsmPrinter.cpp | 12
1 files changed, 12 insertions(+)
Index: llvm/lib/Target/PowerPC/PPCAsmPrinter.cpp
diff -u llvm/lib/Target/PowerPC/PPCAsmPrinter.cpp:1.209
llvm/lib/Target/PowerPC/PPCAsmPrinter.cpp:1.210
--- llvm/lib/Target/PowerPC/PPCAsmPrinter.cpp:1.209 Fri Nov 17 16:10:59 2006
+++ llvm/lib/Target/PowerPC/PPCAsmPrinter.cpp Fri Nov 17 19:23:56 2006
@@ -438,6 +438,18 @@
O << "\n";
return;
}
+ } else if (MI->getOpcode() == PPC::RLDICR) {
+unsigned char SH = MI->getOperand(2).getImmedValue();
+unsigned char ME = MI->getOperand(3).getImmedValue();
+// rldicr RA, RS, SH, 63-SH == sldi RA, RS, SH
+if (63-SH == ME) {
+ O << "sldi ";
+ printOperand(MI, 0);
+ O << ", ";
+ printOperand(MI, 1);
+ O << ", " << (unsigned int)SH << "\n";
+ return;
+}
}
if (printInstruction(MI))
___
llvm-commits mailing list
llvm-commits@cs.uiuc.edu
http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
[llvm-commits] CVS: llvm/lib/Target/PowerPC/PPCFrameInfo.h PPCTargetMachine.cpp
Changes in directory llvm/lib/Target/PowerPC:
PPCFrameInfo.h updated: 1.10 -> 1.11
PPCTargetMachine.cpp updated: 1.107 -> 1.108
---
Log message:
make sure to safe LR8 in the right stack slot for PPC64
---
Diffs of the changes: (+8 -3)
PPCFrameInfo.h |9 +++--
PPCTargetMachine.cpp |2 +-
2 files changed, 8 insertions(+), 3 deletions(-)
Index: llvm/lib/Target/PowerPC/PPCFrameInfo.h
diff -u llvm/lib/Target/PowerPC/PPCFrameInfo.h:1.10
llvm/lib/Target/PowerPC/PPCFrameInfo.h:1.11
--- llvm/lib/Target/PowerPC/PPCFrameInfo.h:1.10 Thu Nov 16 16:43:37 2006
+++ llvm/lib/Target/PowerPC/PPCFrameInfo.h Fri Nov 17 19:34:43 2006
@@ -26,8 +26,13 @@
public:
PPCFrameInfo(const TargetMachine &tm, bool LP64)
: TargetFrameInfo(TargetFrameInfo::StackGrowsDown, 16, 0), TM(tm) {
-LR[0].first = PPC::LR;
-LR[0].second = LP64 ? 16 : 8;
+if (LP64) {
+ LR[0].first = PPC::LR8;
+ LR[0].second = 16;
+} else {
+ LR[0].first = PPC::LR;
+ LR[0].second = 8;
+}
}
const std::pair *
Index: llvm/lib/Target/PowerPC/PPCTargetMachine.cpp
diff -u llvm/lib/Target/PowerPC/PPCTargetMachine.cpp:1.107
llvm/lib/Target/PowerPC/PPCTargetMachine.cpp:1.108
--- llvm/lib/Target/PowerPC/PPCTargetMachine.cpp:1.107 Wed Sep 20 12:12:19 2006
+++ llvm/lib/Target/PowerPC/PPCTargetMachine.cppFri Nov 17 19:34:43 2006
@@ -83,7 +83,7 @@
bool is64Bit)
: Subtarget(M, FS, is64Bit),
DataLayout(Subtarget.getTargetDataString()), InstrInfo(*this),
-FrameInfo(*this, false), JITInfo(*this, is64Bit), TLInfo(*this),
+FrameInfo(*this, is64Bit), JITInfo(*this, is64Bit), TLInfo(*this),
InstrItins(Subtarget.getInstrItineraryData()) {
if (getRelocationModel() == Reloc::Default)
___
llvm-commits mailing list
llvm-commits@cs.uiuc.edu
http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
[llvm-commits] CVS: llvm/lib/Target/PowerPC/PPCISelLowering.cpp
Changes in directory llvm/lib/Target/PowerPC:
PPCISelLowering.cpp updated: 1.231 -> 1.232
---
Log message:
on ppc64, float arguments take 8-byte stack slots not 4-byte stack slots.
Also, valist should create a pointer RC reg class value, not a GPRC value.
---
Diffs of the changes: (+8 -3)
PPCISelLowering.cpp | 11 ---
1 files changed, 8 insertions(+), 3 deletions(-)
Index: llvm/lib/Target/PowerPC/PPCISelLowering.cpp
diff -u llvm/lib/Target/PowerPC/PPCISelLowering.cpp:1.231
llvm/lib/Target/PowerPC/PPCISelLowering.cpp:1.232
--- llvm/lib/Target/PowerPC/PPCISelLowering.cpp:1.231 Fri Nov 17 16:37:34 2006
+++ llvm/lib/Target/PowerPC/PPCISelLowering.cpp Fri Nov 17 19:57:19 2006
@@ -1155,13 +1155,13 @@
case MVT::f32:
case MVT::f64:
// All FP arguments reserve stack space.
- ArgOffset += ObjSize;
+ ArgOffset += isPPC64 ? 8 : ObjSize;
// Every 4 bytes of argument space consumes one of the GPRs available for
// argument passing.
if (GPR_idx != Num_GPR_Regs) {
++GPR_idx;
-if (ObjSize == 8 && GPR_idx != Num_GPR_Regs)
+if (ObjSize == 8 && GPR_idx != Num_GPR_Regs && !isPPC64)
++GPR_idx;
}
if (FPR_idx != Num_FPR_Regs) {
@@ -1226,7 +1226,12 @@
// result of va_next.
SmallVector MemOps;
for (; GPR_idx != Num_GPR_Regs; ++GPR_idx) {
- unsigned VReg = RegMap->createVirtualRegister(&PPC::GPRCRegClass);
+ unsigned VReg;
+ if (isPPC64)
+VReg = RegMap->createVirtualRegister(&PPC::G8RCRegClass);
+ else
+VReg = RegMap->createVirtualRegister(&PPC::GPRCRegClass);
+
MF.addLiveIn(GPR[GPR_idx], VReg);
SDOperand Val = DAG.getCopyFromReg(Root, VReg, PtrVT);
SDOperand Store = DAG.getStore(Val.getValue(1), Val, FIN, NULL, 0);
___
llvm-commits mailing list
llvm-commits@cs.uiuc.edu
http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
[llvm-commits] CVS: llvm/lib/Bytecode/Reader/Reader.cpp
Changes in directory llvm/lib/Bytecode/Reader:
Reader.cpp updated: 1.205 -> 1.206
---
Log message:
Have ConstantExprs upgrade opcodes the same way as instructions.
---
Diffs of the changes: (+11 -1)
Reader.cpp | 12 +++-
1 files changed, 11 insertions(+), 1 deletion(-)
Index: llvm/lib/Bytecode/Reader/Reader.cpp
diff -u llvm/lib/Bytecode/Reader/Reader.cpp:1.205
llvm/lib/Bytecode/Reader/Reader.cpp:1.206
--- llvm/lib/Bytecode/Reader/Reader.cpp:1.205 Mon Nov 13 22:47:22 2006
+++ llvm/lib/Bytecode/Reader/Reader.cpp Fri Nov 17 22:37:19 2006
@@ -1506,9 +1506,19 @@
Opcode = 10; // Div
else if (Opcode >=13 && Opcode <= 15) // URem through FRem
Opcode = 11; // Rem
-else if (Opcode > 15) // Everything above FRem
+else if (Opcode >= 16 && Opcode <= 35) // And through Shr
// Adjust for new instruction codes
Opcode -= 4;
+else if (Opcode >= 36 && Opcode <= 42) // Everything after Select
+ // In vers 6 bytecode we eliminated the placeholders for the obsolete
+ // VAARG and VANEXT instructions. Consequently those two slots were
+ // filled starting with Select (36) which was 34. So now we only need
+ // to subtract two. This circumvents hitting opcodes 32 and 33
+ Opcode -= 2;
+else { // Opcode < 10 or > 42
+ // No upgrade necessary.
+ return 0;
+}
}
switch (Opcode) {
___
llvm-commits mailing list
llvm-commits@cs.uiuc.edu
http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
[llvm-commits] CVS: llvm/test/Regression/Analysis/BasicAA/modref.ll
Changes in directory llvm/test/Regression/Analysis/BasicAA:
modref.ll added (r1.1)
---
Log message:
Add a simple test to make sure getModRefInfo is 1/2 way sane.
---
Diffs of the changes: (+12 -0)
modref.ll | 12
1 files changed, 12 insertions(+)
Index: llvm/test/Regression/Analysis/BasicAA/modref.ll
diff -c /dev/null llvm/test/Regression/Analysis/BasicAA/modref.ll:1.1
*** /dev/null Fri Nov 17 23:52:28 2006
--- llvm/test/Regression/Analysis/BasicAA/modref.ll Fri Nov 17 23:52:18 2006
***
*** 0
--- 1,12
+ ; RUN: llvm-as < %s | opt -print-all-alias-modref-info -aa-eval
-disable-output 2>&1 | not grep NoModRef
+
+ int %callee() {
+ %X = alloca struct { int, int }
+ %Y = int* getelementptr struct { int, int }*, uint 1
+ %Z = int load struct { int, int }*
+ ret %Z
+ }
+
+ int %caller() {
+ %X = int callee();
+ }
___
llvm-commits mailing list
llvm-commits@cs.uiuc.edu
http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
[llvm-commits] CVS: llvm-test/SingleSource/UnitTests/SignlessTypes/.cvsignore
Changes in directory llvm-test/SingleSource/UnitTests/SignlessTypes: .cvsignore added (r1.1) --- Log message: Ignore the Output directory --- Diffs of the changes: (+1 -0) .cvsignore |1 + 1 files changed, 1 insertion(+) Index: llvm-test/SingleSource/UnitTests/SignlessTypes/.cvsignore diff -c /dev/null llvm-test/SingleSource/UnitTests/SignlessTypes/.cvsignore:1.1 *** /dev/null Sat Nov 18 00:02:07 2006 --- llvm-test/SingleSource/UnitTests/SignlessTypes/.cvsignore Sat Nov 18 00:01:57 2006 *** *** 0 --- 1 + Output ___ llvm-commits mailing list llvm-commits@cs.uiuc.edu http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
[llvm-commits] CVS: llvm-test/SingleSource/UnitTests/Vector/SSE/.cvsignore
Changes in directory llvm-test/SingleSource/UnitTests/Vector/SSE: .cvsignore added (r1.1) --- Log message: Ignore the Output directory --- Diffs of the changes: (+1 -0) .cvsignore |1 + 1 files changed, 1 insertion(+) Index: llvm-test/SingleSource/UnitTests/Vector/SSE/.cvsignore diff -c /dev/null llvm-test/SingleSource/UnitTests/Vector/SSE/.cvsignore:1.1 *** /dev/null Sat Nov 18 00:02:07 2006 --- llvm-test/SingleSource/UnitTests/Vector/SSE/.cvsignore Sat Nov 18 00:01:57 2006 *** *** 0 --- 1 + Output ___ llvm-commits mailing list llvm-commits@cs.uiuc.edu http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
[llvm-commits] CVS: llvm/test/Regression/Analysis/BasicAA/modref.ll
Changes in directory llvm/test/Regression/Analysis/BasicAA:
modref.ll updated: 1.1 -> 1.2
---
Log message:
Fail even if opt doesn't print anything.
---
Diffs of the changes: (+3 -0)
modref.ll |3 +++
1 files changed, 3 insertions(+)
Index: llvm/test/Regression/Analysis/BasicAA/modref.ll
diff -u llvm/test/Regression/Analysis/BasicAA/modref.ll:1.1
llvm/test/Regression/Analysis/BasicAA/modref.ll:1.2
--- llvm/test/Regression/Analysis/BasicAA/modref.ll:1.1 Fri Nov 17 23:52:18 2006
+++ llvm/test/Regression/Analysis/BasicAA/modref.ll Sat Nov 18 00:08:21 2006
@@ -1,3 +1,6 @@
+; A very rudimentary test on AliasAnalysis::getModRefInfo.
+; RUN: llvm-as < %s | opt -print-all-alias-modref-info -aa-eval -disable-output
+&&
; RUN: llvm-as < %s | opt -print-all-alias-modref-info -aa-eval
-disable-output 2>&1 | not grep NoModRef
int %callee() {
___
llvm-commits mailing list
llvm-commits@cs.uiuc.edu
http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
[llvm-commits] CVS: llvm/docs/ReleaseNotes.html
Changes in directory llvm/docs:
ReleaseNotes.html updated: 1.363 -> 1.364
---
Log message:
first draft of 1.9 release notes
---
Diffs of the changes: (+252 -223)
ReleaseNotes.html | 475 --
1 files changed, 252 insertions(+), 223 deletions(-)
Index: llvm/docs/ReleaseNotes.html
diff -u llvm/docs/ReleaseNotes.html:1.363 llvm/docs/ReleaseNotes.html:1.364
--- llvm/docs/ReleaseNotes.html:1.363 Wed Nov 1 10:15:04 2006
+++ llvm/docs/ReleaseNotes.html Sat Nov 18 01:51:14 2006
@@ -62,7 +62,8 @@
This is the tenth public release of the LLVM Compiler Infrastructure. This
-release incorporates a large number of enhancements and new features.
+release incorporates a large number of enhancements, new features, and bug
+fixes. We recommend that all users of previous LLVM versions upgrade.
@@ -73,41 +74,106 @@
-DWARF debugging
-support for X86/ELF
+New X86-64 Backend
-The llvm-gcc4 C front-end now generates debugging info for C and C++ for
-X86/ELF platforms (Linux). This extends the PPC/Darwin and X86/Darwin
debugging
-support available in release 18.8 DWARF is a standard debugging format used on
-many platforms.
+LLVM 1.9 now fully supports the x86-64 instruction set on Mac OS/X, and
+supports it on Linux (and other operating systems) when compiling in -static
+mode. LLVM includes JIT support for X86-64, and supports both Intel EMT-64T
+and AMD-64 architectures. The X86-64 instruction set permits addressing a
+64-bit addressing space and provides the compiler with twice the
+number of integer registers to use.
-Signed
Instructions
+Link-Time Optimization integration
+with native linkers
-As a step towards making LLVM's integer types signless, several new
-instructions have been added to LLVM. The DIV instruction has become UDIV,
SDIV,
-and FDIV. The REM instruction has become UREM, SREM and FREM. The SHR
-instruction has become ASHR and LSHR. See the Language
- Reference for details on these new instructions.
+LLVM now includes liblto which can
+be used to integrate LLVM Link-Time Optimization support into a native linker.
+This allows LLVM .bc to transparently participate with linking an application,
+even when some .o files are in LLVM form and some are not.
-New Feature C
+DWARF debugging
+support for Linux, Cygwin and MinGW on X86
-Describe feature C here.
+llvm-gcc4 now supports generating debugging info for Linux, Cygwin and
MinGW.
+This extends the PPC/Darwin and X86/Darwin debugging support available in the
+1.8 release. DWARF is a standard debugging format used on many platforms.
-New Feature D
+Optimizer
+Improvements
-Describe feature D here.
+The mid-level optimizer is now faster and produces better code in many
cases.
+ Significant changes include:
+
+
+LLVM includes a new 'predicate simplifier' pass, which
+currently performs dominator tree-based optimizations.
+The complete loop unroll pass now supports unrolling of
+ multiple basic block loops.
+The 'globalopt' pass can now perform the scalar replacement of
+aggregates transformation on some heap allocations.
+The globalsmodref-aa alias analysis can now track 'indirect pointer
+ globals' more accurately.
+The instruction combiner can now perform element propagation
+analysis of vector expressions, eliminating computation of vector elements
+that are not used.
+
+
-New Feature E
+Code
+Generator Enhancements
+
-Describe feature E here.
+
+The LLVM Target-Independent code generator now supports more target features
and
+optimizes many cases more aggressively. New features include:
+
+
+
+LLVM now includes a late branch folding pass which optimizes code
+layout, performs several branch optzns, and deletes unreachable code.
+The code generator now support targets that have pre/post-increment
+addressing modes.
+LLVM now supports dynamically-loadable register allocators and
+ schedulers.
+LLVM 1.9 includes several improvements to inline asm support,
+including support for new constraints and modifiers.
+The register coalescer is now more aggressive than before,
+ allowing it to eliminate more copies.
+
+
+In addition, the LLVM target description format has itself been extended in
+ several ways:
+
+
+tblgen now allows definition of 'multiclasses' which can be
+ used to factor instruction patterns more aggressively in .td files.
+LLVM has a new TargetAsmInfo class which captures a variety of
+ information about the target assembly language format.
+.td files now support "${:foo}" syntax for encoding
+ subtarget-specific assembler syntax into instruction descriptions.
+
+
+Further, several significant target-specific enhancements are included in
+LLVM 1.9:
+
+
+The LLVM ARM backend now supports more instructions
+and the use of a frame pointer. It is now possible to build
+ libgcc and a simple cross compiler, but it is not considered "complete" yet.
+
+LLVM s
[llvm-commits] CVS: llvm/docs/ReleaseNotes.html
Changes in directory llvm/docs: ReleaseNotes.html updated: 1.364 -> 1.365 --- Log message: fix bug --- Diffs of the changes: (+2 -2) ReleaseNotes.html |4 ++-- 1 files changed, 2 insertions(+), 2 deletions(-) Index: llvm/docs/ReleaseNotes.html diff -u llvm/docs/ReleaseNotes.html:1.364 llvm/docs/ReleaseNotes.html:1.365 --- llvm/docs/ReleaseNotes.html:1.364 Sat Nov 18 01:51:14 2006 +++ llvm/docs/ReleaseNotes.html Sat Nov 18 01:52:10 2006 @@ -307,7 +307,7 @@ The X86 backend does not yet support http://llvm.org/PR879";>inline -assembly that uses the X86 floating point stack. See the http://llvm.org/PR879";>bug for details on workarounds on Linux. @@ -679,7 +679,7 @@ src="http://www.w3.org/Icons/valid-html401"; alt="Valid HTML 4.01!" /> http://llvm.org/";>The LLVM Compiler Infrastructure - Last modified: $Date: 2006/11/18 07:51:14 $ + Last modified: $Date: 2006/11/18 07:52:10 $ ___ llvm-commits mailing list llvm-commits@cs.uiuc.edu http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
