Changes in directory llvm/lib/Target/PowerPC:
PPCInstrInfo.td updated: 1.269 -> 1.270 PPCInstrFormats.td updated: 1.84 -> 1.85 --- Log message: add encoding for BCC, after finally wrestling strange ppc/tblgen endianness issues to the ground. --- Diffs of the changes: (+22 -3) PPCInstrFormats.td | 18 ++++++++++++++++++ PPCInstrInfo.td | 7 ++++--- 2 files changed, 22 insertions(+), 3 deletions(-) Index: llvm/lib/Target/PowerPC/PPCInstrInfo.td diff -u llvm/lib/Target/PowerPC/PPCInstrInfo.td:1.269 llvm/lib/Target/PowerPC/PPCInstrInfo.td:1.270 --- llvm/lib/Target/PowerPC/PPCInstrInfo.td:1.269 Fri Nov 17 16:37:34 2006 +++ llvm/lib/Target/PowerPC/PPCInstrInfo.td Fri Nov 17 17:53:28 2006 @@ -361,10 +361,11 @@ // BCC represents an arbitrary conditional branch on a predicate. // FIXME: should be able to write a pattern for PPCcondbranch, but can't use // a two-value operand where a dag node expects two operands. :( - def BCC : Pseudo<(ops pred:$cond, target:$dst), - "b${cond:cc} ${cond:reg}, $dst", - [/*(PPCcondbranch CRRC:$crS, imm:$opc, bb:$dst)*/]>; + def BCC : CBForm<16, 0, 0, (ops pred:$cond, target:$dst), + "b${cond:cc} ${cond:reg}, $dst" + /*[(PPCcondbranch CRRC:$crS, imm:$opc, bb:$dst)]*/>; +// REMOVE BForm when these go away. def BLT : BForm<16, 0, 0, 12, 0, (ops CRRC:$crS, target:$block), "blt $crS, $block", BrB>; def BLE : BForm<16, 0, 0, 4, 1, (ops CRRC:$crS, target:$block), Index: llvm/lib/Target/PowerPC/PPCInstrFormats.td diff -u llvm/lib/Target/PowerPC/PPCInstrFormats.td:1.84 llvm/lib/Target/PowerPC/PPCInstrFormats.td:1.85 --- llvm/lib/Target/PowerPC/PPCInstrFormats.td:1.84 Wed Nov 15 17:24:18 2006 +++ llvm/lib/Target/PowerPC/PPCInstrFormats.td Fri Nov 17 17:53:28 2006 @@ -74,6 +74,24 @@ let Inst{31} = lk; } +class CBForm<bits<6> opcode, bit aa, bit lk, dag OL, + string asmstr> : I<opcode, OL, asmstr, BrB> { + bits<7> BIBO; // 2 bits of BI and 5 bits of BO. + bits<3> CR; + bits<14> BD; + + bits<5> BI; + let BI{0-1} = BIBO{5-6}; + let BI{2-4} = CR{0-2}; + + let Inst{6-10} = BIBO{4-0}; + let Inst{11-15} = BI; + let Inst{16-29} = BD; + let Inst{30} = aa; + let Inst{31} = lk; +} + + // 1.7.4 D-Form class DForm_base<bits<6> opcode, dag OL, string asmstr, InstrItinClass itin, list<dag> pattern> _______________________________________________ llvm-commits mailing list llvm-commits@cs.uiuc.edu http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits