[llvm-commits] CVS: llvm/test/Regression/CodeGen/ARM/long.ll
Changes in directory llvm/test/Regression/CodeGen/ARM:
long.ll updated: 1.5 -> 1.6
---
Log message:
implement smull and umull
---
Diffs of the changes: (+19 -1)
long.ll | 20 +++-
1 files changed, 19 insertions(+), 1 deletion(-)
Index: llvm/test/Regression/CodeGen/ARM/long.ll
diff -u llvm/test/Regression/CodeGen/ARM/long.ll:1.5
llvm/test/Regression/CodeGen/ARM/long.ll:1.6
--- llvm/test/Regression/CodeGen/ARM/long.ll:1.5Fri Oct 13 12:19:20 2006
+++ llvm/test/Regression/CodeGen/ARM/long.llMon Oct 16 11:33:29 2006
@@ -7,7 +7,9 @@
; RUN: llvm-as < %s | llc -march=arm | grep "adds" | wc -l | grep 1 &&
; RUN: llvm-as < %s | llc -march=arm | grep "adcs" | wc -l | grep 1 &&
; RUN: llvm-as < %s | llc -march=arm | grep "subs" | wc -l | grep 1 &&
-; RUN: llvm-as < %s | llc -march=arm | grep "sbcs" | wc -l | grep 1
+; RUN: llvm-as < %s | llc -march=arm | grep "sbcs" | wc -l | grep 1 &&
+; RUN: llvm-as < %s | llc -march=arm | grep "smull" | wc -l | grep 1 &&
+; RUN: llvm-as < %s | llc -march=arm | grep "umull" | wc -l | grep 1
long %f1() {
entry:
@@ -52,3 +54,19 @@
%tmp = sub long %a, %b
ret long %tmp
}
+
+long %f(int %a, int %b) {
+entry:
+ %tmp = cast int %a to long
+ %tmp1 = cast int %b to long
+ %tmp2 = mul long %tmp1, %tmp
+ ret long %tmp2
+}
+
+ulong %g(uint %a, uint %b) {
+entry:
+ %tmp = cast uint %a to ulong
+ %tmp1 = cast uint %b to ulong
+ %tmp2 = mul ulong %tmp1, %tmp
+ ret ulong %tmp2
+}
___
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[llvm-commits] CVS: llvm/lib/Target/ARM/ARMInstrInfo.td ARMMul.cpp README.txt
Changes in directory llvm/lib/Target/ARM:
ARMInstrInfo.td updated: 1.49 -> 1.50
ARMMul.cpp updated: 1.2 -> 1.3
README.txt updated: 1.5 -> 1.6
---
Log message:
implement smull and umull
---
Diffs of the changes: (+24 -5)
ARMInstrInfo.td | 10 ++
ARMMul.cpp | 14 +-
README.txt |5 +
3 files changed, 24 insertions(+), 5 deletions(-)
Index: llvm/lib/Target/ARM/ARMInstrInfo.td
diff -u llvm/lib/Target/ARM/ARMInstrInfo.td:1.49
llvm/lib/Target/ARM/ARMInstrInfo.td:1.50
--- llvm/lib/Target/ARM/ARMInstrInfo.td:1.49Sat Oct 14 08:42:53 2006
+++ llvm/lib/Target/ARM/ARMInstrInfo.td Mon Oct 16 11:33:29 2006
@@ -174,6 +174,16 @@
"mul $dst, $a, $b",
[(set IntRegs:$dst, (mul IntRegs:$a, IntRegs:$b))]>;
+let Defs = [R0] in {
+ def SMULL : InstARM<(ops IntRegs:$dst, IntRegs:$a, IntRegs:$b),
+ "smull r12, $dst, $a, $b",
+ [(set IntRegs:$dst, (mulhs IntRegs:$a, IntRegs:$b))]>;
+
+ def UMULL : InstARM<(ops IntRegs:$dst, IntRegs:$a, IntRegs:$b),
+ "umull r12, $dst, $a, $b",
+ [(set IntRegs:$dst, (mulhu IntRegs:$a, IntRegs:$b))]>;
+}
+
def bcond : InstARM<(ops brtarget:$dst, CCOp:$cc),
"b$cc $dst",
[(armbr bb:$dst, imm:$cc)]>;
Index: llvm/lib/Target/ARM/ARMMul.cpp
diff -u llvm/lib/Target/ARM/ARMMul.cpp:1.2 llvm/lib/Target/ARM/ARMMul.cpp:1.3
--- llvm/lib/Target/ARM/ARMMul.cpp:1.2 Tue Sep 19 11:41:40 2006
+++ llvm/lib/Target/ARM/ARMMul.cpp Mon Oct 16 11:33:29 2006
@@ -8,7 +8,7 @@
//
//===--===//
//
-// Modify the ARM multiplication instructions so that Rd and Rm are distinct
+// Modify the ARM multiplication instructions so that Rd{Hi,Lo} and Rm are
distinct
//
//===--===//
@@ -39,7 +39,10 @@
I != E; ++I) {
MachineInstr *MI = I;
- if (MI->getOpcode() == ARM::MUL) {
+ int Op = MI->getOpcode();
+ if (Op == ARM::MUL ||
+ Op == ARM::SMULL ||
+ Op == ARM::UMULL) {
MachineOperand &RdOp = MI->getOperand(0);
MachineOperand &RmOp = MI->getOperand(1);
MachineOperand &RsOp = MI->getOperand(2);
@@ -48,7 +51,7 @@
unsigned Rm = RmOp.getReg();
unsigned Rs = RsOp.getReg();
-if(Rd == Rm) {
+if (Rd == Rm) {
Changed = true;
if (Rd != Rs) {
//Rd and Rm must be distinct, but Rd can be equal to Rs.
@@ -56,9 +59,10 @@
RmOp.setReg(Rs);
RsOp.setReg(Rm);
} else {
-BuildMI(MBB, I, ARM::MOV, 3, ARM::R12).addReg(Rm).addImm(0)
+unsigned scratch = Op == ARM::MUL ? ARM::R12 : ARM::R0;
+BuildMI(MBB, I, ARM::MOV, 3, scratch).addReg(Rm).addImm(0)
.addImm(ARMShift::LSL);
-RmOp.setReg(ARM::R12);
+RmOp.setReg(scratch);
}
}
}
Index: llvm/lib/Target/ARM/README.txt
diff -u llvm/lib/Target/ARM/README.txt:1.5 llvm/lib/Target/ARM/README.txt:1.6
--- llvm/lib/Target/ARM/README.txt:1.5 Mon Oct 9 09:18:33 2006
+++ llvm/lib/Target/ARM/README.txt Mon Oct 16 11:33:29 2006
@@ -46,3 +46,8 @@
Only needs 8 bytes of stack space. We currently allocate 16.
--
+
+32 x 32 -> 64 multiplications currently uses two instructions. We
+should try to declare smull and umull as returning two values.
+
+--
___
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[llvm-commits] CVS: llvm/lib/Target/ARM/ARMInstrInfo.td README.txt
Changes in directory llvm/lib/Target/ARM: ARMInstrInfo.td updated: 1.50 -> 1.51 README.txt updated: 1.6 -> 1.7 --- Log message: implement LDRB, LDRSB, LDRH and LDRSH --- Diffs of the changes: (+20 -0) ARMInstrInfo.td | 16 README.txt |4 2 files changed, 20 insertions(+) Index: llvm/lib/Target/ARM/ARMInstrInfo.td diff -u llvm/lib/Target/ARM/ARMInstrInfo.td:1.50 llvm/lib/Target/ARM/ARMInstrInfo.td:1.51 --- llvm/lib/Target/ARM/ARMInstrInfo.td:1.50Mon Oct 16 11:33:29 2006 +++ llvm/lib/Target/ARM/ARMInstrInfo.td Mon Oct 16 12:17:21 2006 @@ -113,6 +113,22 @@ "ldr $dst, $addr", [(set IntRegs:$dst, (load iaddr:$addr))]>; +def LDRB: InstARM<(ops IntRegs:$dst, IntRegs:$addr), + "ldrb $dst, $addr", + [(set IntRegs:$dst, (zextloadi8 IntRegs:$addr))]>; + +def LDRSB : InstARM<(ops IntRegs:$dst, IntRegs:$addr), + "ldrsb $dst, $addr", + [(set IntRegs:$dst, (sextloadi8 IntRegs:$addr))]>; + +def LDRH: InstARM<(ops IntRegs:$dst, IntRegs:$addr), + "ldrh $dst, $addr", + [(set IntRegs:$dst, (zextloadi16 IntRegs:$addr))]>; + +def LDRSH : InstARM<(ops IntRegs:$dst, IntRegs:$addr), + "ldrsh $dst, $addr", + [(set IntRegs:$dst, (sextloadi16 IntRegs:$addr))]>; + def str : InstARM<(ops IntRegs:$src, memri:$addr), "str $src, $addr", [(store IntRegs:$src, iaddr:$addr)]>; Index: llvm/lib/Target/ARM/README.txt diff -u llvm/lib/Target/ARM/README.txt:1.6 llvm/lib/Target/ARM/README.txt:1.7 --- llvm/lib/Target/ARM/README.txt:1.6 Mon Oct 16 11:33:29 2006 +++ llvm/lib/Target/ARM/README.txt Mon Oct 16 12:17:21 2006 @@ -51,3 +51,7 @@ should try to declare smull and umull as returning two values. -- + +Implement addressing modes 2 (ldrb) and 3 (ldrsb) + +-- ___ llvm-commits mailing list llvm-commits@cs.uiuc.edu http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
[llvm-commits] CVS: llvm/test/Regression/CodeGen/ARM/load.ll
Changes in directory llvm/test/Regression/CodeGen/ARM:
load.ll added (r1.1)
---
Log message:
implement LDRB, LDRSB, LDRH and LDRSH
---
Diffs of the changes: (+33 -0)
load.ll | 33 +
1 files changed, 33 insertions(+)
Index: llvm/test/Regression/CodeGen/ARM/load.ll
diff -c /dev/null llvm/test/Regression/CodeGen/ARM/load.ll:1.1
*** /dev/null Mon Oct 16 12:17:32 2006
--- llvm/test/Regression/CodeGen/ARM/load.llMon Oct 16 12:17:22 2006
***
*** 0
--- 1,33
+ ; RUN: llvm-as < %s | llc -march=arm &&
+ ; RUN: llvm-as < %s | llc -march=arm | grep ldrsb &&
+ ; RUN: llvm-as < %s | llc -march=arm | grep ldrb &&
+ ; RUN: llvm-as < %s | llc -march=arm | grep ldrsh &&
+ ; RUN: llvm-as < %s | llc -march=arm | grep ldrh
+
+ int %f1(sbyte* %p) {
+ entry:
+ %tmp = load sbyte* %p ; [#uses=1]
+ %tmp = cast sbyte %tmp to int ; [#uses=1]
+ ret int %tmp
+ }
+
+ int %f2(ubyte* %p) {
+ entry:
+ %tmp = load ubyte* %p ; [#uses=1]
+ %tmp = cast ubyte %tmp to int ; [#uses=1]
+ ret int %tmp
+ }
+
+ int %f3(short* %p) {
+ entry:
+ %tmp = load short* %p ; [#uses=1]
+ %tmp = cast short %tmp to int ; [#uses=1]
+ ret int %tmp
+ }
+
+ int %f4(ushort* %p) {
+ entry:
+ %tmp = load ushort* %p ; [#uses=1]
+ %tmp = cast ushort %tmp to int ; [#uses=1]
+ ret int %tmp
+ }
___
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[llvm-commits] CVS: llvm/lib/Target/ARM/ARMInstrInfo.td
Changes in directory llvm/lib/Target/ARM: ARMInstrInfo.td updated: 1.51 -> 1.52 --- Log message: fix assembly syntax --- Diffs of the changes: (+4 -4) ARMInstrInfo.td |8 1 files changed, 4 insertions(+), 4 deletions(-) Index: llvm/lib/Target/ARM/ARMInstrInfo.td diff -u llvm/lib/Target/ARM/ARMInstrInfo.td:1.51 llvm/lib/Target/ARM/ARMInstrInfo.td:1.52 --- llvm/lib/Target/ARM/ARMInstrInfo.td:1.51Mon Oct 16 12:17:21 2006 +++ llvm/lib/Target/ARM/ARMInstrInfo.td Mon Oct 16 12:38:12 2006 @@ -114,19 +114,19 @@ [(set IntRegs:$dst, (load iaddr:$addr))]>; def LDRB: InstARM<(ops IntRegs:$dst, IntRegs:$addr), - "ldrb $dst, $addr", + "ldrb $dst, [$addr]", [(set IntRegs:$dst, (zextloadi8 IntRegs:$addr))]>; def LDRSB : InstARM<(ops IntRegs:$dst, IntRegs:$addr), - "ldrsb $dst, $addr", + "ldrsb $dst, [$addr]", [(set IntRegs:$dst, (sextloadi8 IntRegs:$addr))]>; def LDRH: InstARM<(ops IntRegs:$dst, IntRegs:$addr), - "ldrh $dst, $addr", + "ldrh $dst, [$addr]", [(set IntRegs:$dst, (zextloadi16 IntRegs:$addr))]>; def LDRSH : InstARM<(ops IntRegs:$dst, IntRegs:$addr), - "ldrsh $dst, $addr", + "ldrsh $dst, [$addr]", [(set IntRegs:$dst, (sextloadi16 IntRegs:$addr))]>; def str : InstARM<(ops IntRegs:$src, memri:$addr), ___ llvm-commits mailing list llvm-commits@cs.uiuc.edu http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
[llvm-commits] CVS: llvm/lib/Target/ARM/ARMInstrInfo.td
Changes in directory llvm/lib/Target/ARM:
ARMInstrInfo.td updated: 1.52 -> 1.53
---
Log message:
define the IntBinOp class and use it to implement the multiply instructions
---
Diffs of the changes: (+13 -12)
ARMInstrInfo.td | 25 +
1 files changed, 13 insertions(+), 12 deletions(-)
Index: llvm/lib/Target/ARM/ARMInstrInfo.td
diff -u llvm/lib/Target/ARM/ARMInstrInfo.td:1.52
llvm/lib/Target/ARM/ARMInstrInfo.td:1.53
--- llvm/lib/Target/ARM/ARMInstrInfo.td:1.52Mon Oct 16 12:38:12 2006
+++ llvm/lib/Target/ARM/ARMInstrInfo.td Mon Oct 16 12:57:20 2006
@@ -36,9 +36,8 @@
//def raddr : ComplexPattern;
//===--===//
-// Instructions
+// Instruction Class Templates
//===--===//
-
class InstARM pattern> : Instruction {
let Namespace = "ARM";
@@ -47,6 +46,15 @@
let Pattern = pattern;
}
+class IntBinOp :
+InstARM<(ops IntRegs:$dst, IntRegs:$a, IntRegs:$b),
+ !strconcat(OpcStr, " $dst, $a, $b"),
+ [(set IntRegs:$dst, (OpNode IntRegs:$a, IntRegs:$b))]>;
+
+//===--===//
+// Instructions
+//===--===//
+
def brtarget : Operand;
// Operand for printing out a condition code.
@@ -186,18 +194,11 @@
IntRegs:$false, imm:$cc))]>;
}
-def MUL : InstARM<(ops IntRegs:$dst, IntRegs:$a, IntRegs:$b),
- "mul $dst, $a, $b",
- [(set IntRegs:$dst, (mul IntRegs:$a, IntRegs:$b))]>;
+def MUL : IntBinOp<"mul", mul>;
let Defs = [R0] in {
- def SMULL : InstARM<(ops IntRegs:$dst, IntRegs:$a, IntRegs:$b),
- "smull r12, $dst, $a, $b",
- [(set IntRegs:$dst, (mulhs IntRegs:$a, IntRegs:$b))]>;
-
- def UMULL : InstARM<(ops IntRegs:$dst, IntRegs:$a, IntRegs:$b),
- "umull r12, $dst, $a, $b",
- [(set IntRegs:$dst, (mulhu IntRegs:$a, IntRegs:$b))]>;
+ def SMULL : IntBinOp<"smull r12,", mulhs>;
+ def UMULL : IntBinOp<"umull r12,", mulhu>;
}
def bcond : InstARM<(ops brtarget:$dst, CCOp:$cc),
___
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[llvm-commits] CVS: llvm/lib/Target/ARM/ARMInstrInfo.td
Changes in directory llvm/lib/Target/ARM:
ARMInstrInfo.td updated: 1.53 -> 1.54
---
Log message:
define the Addr1BinOp class
---
Diffs of the changes: (+14 -34)
ARMInstrInfo.td | 48 ++--
1 files changed, 14 insertions(+), 34 deletions(-)
Index: llvm/lib/Target/ARM/ARMInstrInfo.td
diff -u llvm/lib/Target/ARM/ARMInstrInfo.td:1.53
llvm/lib/Target/ARM/ARMInstrInfo.td:1.54
--- llvm/lib/Target/ARM/ARMInstrInfo.td:1.53Mon Oct 16 12:57:20 2006
+++ llvm/lib/Target/ARM/ARMInstrInfo.td Mon Oct 16 13:18:14 2006
@@ -51,6 +51,11 @@
!strconcat(OpcStr, " $dst, $a, $b"),
[(set IntRegs:$dst, (OpNode IntRegs:$a, IntRegs:$b))]>;
+class Addr1BinOp :
+InstARM<(ops IntRegs:$dst, IntRegs:$a, op_addr_mode1:$b),
+ !strconcat(OpcStr, " $dst, $a, $b"),
+ [(set IntRegs:$dst, (OpNode IntRegs:$a, addr_mode1:$b))]>;
+
//===--===//
// Instructions
//===--===//
@@ -144,17 +149,9 @@
def MOV : InstARM<(ops IntRegs:$dst, op_addr_mode1:$src),
"mov $dst, $src", [(set IntRegs:$dst, addr_mode1:$src)]>;
-def ADD : InstARM<(ops IntRegs:$dst, IntRegs:$a, op_addr_mode1:$b),
- "add $dst, $a, $b",
- [(set IntRegs:$dst, (add IntRegs:$a, addr_mode1:$b))]>;
-
-def ADCS: InstARM<(ops IntRegs:$dst, IntRegs:$a, op_addr_mode1:$b),
- "adcs $dst, $a, $b",
- [(set IntRegs:$dst, (adde IntRegs:$a, addr_mode1:$b))]>;
-
-def ADDS: InstARM<(ops IntRegs:$dst, IntRegs:$a, op_addr_mode1:$b),
- "adds $dst, $a, $b",
- [(set IntRegs:$dst, (addc IntRegs:$a, addr_mode1:$b))]>;
+def ADD : Addr1BinOp<"add", add>;
+def ADCS: Addr1BinOp<"adcs", adde>;
+def ADDS: Addr1BinOp<"adds", addc>;
// "LEA" forms of add
def lea_addri : InstARM<(ops IntRegs:$dst, memri:$addr),
@@ -162,29 +159,12 @@
[(set IntRegs:$dst, iaddr:$addr)]>;
-def SUB : InstARM<(ops IntRegs:$dst, IntRegs:$a, op_addr_mode1:$b),
- "sub $dst, $a, $b",
- [(set IntRegs:$dst, (sub IntRegs:$a, addr_mode1:$b))]>;
-
-def SBCS: InstARM<(ops IntRegs:$dst, IntRegs:$a, op_addr_mode1:$b),
- "sbcs $dst, $a, $b",
- [(set IntRegs:$dst, (sube IntRegs:$a, addr_mode1:$b))]>;
-
-def SUBS: InstARM<(ops IntRegs:$dst, IntRegs:$a, op_addr_mode1:$b),
- "subs $dst, $a, $b",
- [(set IntRegs:$dst, (subc IntRegs:$a, addr_mode1:$b))]>;
-
-def AND : InstARM<(ops IntRegs:$dst, IntRegs:$a, op_addr_mode1:$b),
- "and $dst, $a, $b",
- [(set IntRegs:$dst, (and IntRegs:$a, addr_mode1:$b))]>;
-
-def EOR : InstARM<(ops IntRegs:$dst, IntRegs:$a, op_addr_mode1:$b),
- "eor $dst, $a, $b",
- [(set IntRegs:$dst, (xor IntRegs:$a, addr_mode1:$b))]>;
-
-def ORR : InstARM<(ops IntRegs:$dst, IntRegs:$a, op_addr_mode1:$b),
- "orr $dst, $a, $b",
- [(set IntRegs:$dst, (or IntRegs:$a, addr_mode1:$b))]>;
+def SUB : Addr1BinOp<"sub", sub>;
+def SBCS: Addr1BinOp<"sbcs", sube>;
+def SUBS: Addr1BinOp<"subs", subc>;
+def AND : Addr1BinOp<"and", and>;
+def EOR : Addr1BinOp<"eor", xor>;
+def ORR : Addr1BinOp<"orr", or>;
let isTwoAddress = 1 in {
def movcond : InstARM<(ops IntRegs:$dst, IntRegs:$false,
___
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[llvm-commits] CVS: llvm/lib/Target/ARM/ARMInstrInfo.td
Changes in directory llvm/lib/Target/ARM: ARMInstrInfo.td updated: 1.55 -> 1.56 --- Log message: define the DFPBinOp class --- Diffs of the changes: (+10 -15) ARMInstrInfo.td | 25 ++--- 1 files changed, 10 insertions(+), 15 deletions(-) Index: llvm/lib/Target/ARM/ARMInstrInfo.td diff -u llvm/lib/Target/ARM/ARMInstrInfo.td:1.55 llvm/lib/Target/ARM/ARMInstrInfo.td:1.56 --- llvm/lib/Target/ARM/ARMInstrInfo.td:1.55Mon Oct 16 13:32:36 2006 +++ llvm/lib/Target/ARM/ARMInstrInfo.td Mon Oct 16 13:39:22 2006 @@ -56,6 +56,11 @@ !strconcat(OpcStr, " $dst, $a, $b"), [(set FPRegs:$dst, (OpNode FPRegs:$a, FPRegs:$b))]>; +class DFPBinOp : +InstARM<(ops DFPRegs:$dst, DFPRegs:$a, DFPRegs:$b), + !strconcat(OpcStr, " $dst, $a, $b"), + [(set DFPRegs:$dst, (OpNode DFPRegs:$a, DFPRegs:$b))]>; + class Addr1BinOp : InstARM<(ops IntRegs:$dst, IntRegs:$a, op_addr_mode1:$b), !strconcat(OpcStr, " $dst, $a, $b"), @@ -256,17 +261,10 @@ def FMSTAT : InstARM<(ops ), "fmstat", [(armfmstat)]>; // Floating Point Arithmetic -def FADDS : FPBinOp<"fadds", fadd>; - -def FADDD : InstARM<(ops DFPRegs:$dst, DFPRegs:$a, DFPRegs:$b), - "faddd $dst, $a, $b", - [(set DFPRegs:$dst, (fadd DFPRegs:$a, DFPRegs:$b))]>; - -def FSUBS : FPBinOp<"fsubs", fsub>; - -def FSUBD : InstARM<(ops DFPRegs:$dst, DFPRegs:$a, DFPRegs:$b), - "fsubd $dst, $a, $b", - [(set DFPRegs:$dst, (fsub DFPRegs:$a, DFPRegs:$b))]>; +def FADDS : FPBinOp<"fadds", fadd>; +def FADDD : DFPBinOp<"faddd", fadd>; +def FSUBS : FPBinOp<"fsubs", fsub>; +def FSUBD : DFPBinOp<"fsubd", fsub>; def FNEGS : InstARM<(ops FPRegs:$dst, FPRegs:$src), "fnegs $dst, $src", @@ -277,10 +275,7 @@ [(set DFPRegs:$dst, (fneg DFPRegs:$src))]>; def FMULS : FPBinOp<"fmuls", fmul>; - -def FMULD : InstARM<(ops DFPRegs:$dst, DFPRegs:$a, DFPRegs:$b), - "fmuld $dst, $a, $b", - [(set DFPRegs:$dst, (fmul DFPRegs:$a, DFPRegs:$b))]>; +def FMULD : DFPBinOp<"fmuld", fmul>; // Floating Point Load ___ llvm-commits mailing list llvm-commits@cs.uiuc.edu http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
[llvm-commits] CVS: llvm/lib/Target/ARM/ARMInstrInfo.td
Changes in directory llvm/lib/Target/ARM: ARMInstrInfo.td updated: 1.54 -> 1.55 --- Log message: add the FPBinOp class --- Diffs of the changes: (+8 -9) ARMInstrInfo.td | 17 - 1 files changed, 8 insertions(+), 9 deletions(-) Index: llvm/lib/Target/ARM/ARMInstrInfo.td diff -u llvm/lib/Target/ARM/ARMInstrInfo.td:1.54 llvm/lib/Target/ARM/ARMInstrInfo.td:1.55 --- llvm/lib/Target/ARM/ARMInstrInfo.td:1.54Mon Oct 16 13:18:14 2006 +++ llvm/lib/Target/ARM/ARMInstrInfo.td Mon Oct 16 13:32:36 2006 @@ -51,6 +51,11 @@ !strconcat(OpcStr, " $dst, $a, $b"), [(set IntRegs:$dst, (OpNode IntRegs:$a, IntRegs:$b))]>; +class FPBinOp : +InstARM<(ops FPRegs:$dst, FPRegs:$a, FPRegs:$b), + !strconcat(OpcStr, " $dst, $a, $b"), + [(set FPRegs:$dst, (OpNode FPRegs:$a, FPRegs:$b))]>; + class Addr1BinOp : InstARM<(ops IntRegs:$dst, IntRegs:$a, op_addr_mode1:$b), !strconcat(OpcStr, " $dst, $a, $b"), @@ -251,17 +256,13 @@ def FMSTAT : InstARM<(ops ), "fmstat", [(armfmstat)]>; // Floating Point Arithmetic -def FADDS : InstARM<(ops FPRegs:$dst, FPRegs:$a, FPRegs:$b), - "fadds $dst, $a, $b", - [(set FPRegs:$dst, (fadd FPRegs:$a, FPRegs:$b))]>; +def FADDS : FPBinOp<"fadds", fadd>; def FADDD : InstARM<(ops DFPRegs:$dst, DFPRegs:$a, DFPRegs:$b), "faddd $dst, $a, $b", [(set DFPRegs:$dst, (fadd DFPRegs:$a, DFPRegs:$b))]>; -def FSUBS : InstARM<(ops FPRegs:$dst, FPRegs:$a, FPRegs:$b), - "fsubs $dst, $a, $b", - [(set FPRegs:$dst, (fsub FPRegs:$a, FPRegs:$b))]>; +def FSUBS : FPBinOp<"fsubs", fsub>; def FSUBD : InstARM<(ops DFPRegs:$dst, DFPRegs:$a, DFPRegs:$b), "fsubd $dst, $a, $b", @@ -275,9 +276,7 @@ "fnegd $dst, $src", [(set DFPRegs:$dst, (fneg DFPRegs:$src))]>; -def FMULS : InstARM<(ops FPRegs:$dst, FPRegs:$a, FPRegs:$b), - "fmuls $dst, $a, $b", - [(set FPRegs:$dst, (fmul FPRegs:$a, FPRegs:$b))]>; +def FMULS : FPBinOp<"fmuls", fmul>; def FMULD : InstARM<(ops DFPRegs:$dst, DFPRegs:$a, DFPRegs:$b), "fmuld $dst, $a, $b", ___ llvm-commits mailing list llvm-commits@cs.uiuc.edu http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
[llvm-commits] CVS: llvm/lib/CodeGen/DwarfWriter.cpp
Changes in directory llvm/lib/CodeGen: DwarfWriter.cpp updated: 1.79 -> 1.80 --- Log message: Global name regression. --- Diffs of the changes: (+5 -1) DwarfWriter.cpp |6 +- 1 files changed, 5 insertions(+), 1 deletion(-) Index: llvm/lib/CodeGen/DwarfWriter.cpp diff -u llvm/lib/CodeGen/DwarfWriter.cpp:1.79 llvm/lib/CodeGen/DwarfWriter.cpp:1.80 --- llvm/lib/CodeGen/DwarfWriter.cpp:1.79 Fri Oct 13 08:02:19 2006 +++ llvm/lib/CodeGen/DwarfWriter.cppMon Oct 16 14:38:41 2006 @@ -1632,11 +1632,15 @@ // Add source line info if available. AddSourceLine(VariableDie, UnitDesc, GVD->getLine()); + + // Work up linkage name. + std::string LinkageName(TAI->getGlobalPrefix()); + LinkageName += GV->getName(); // Add address. DIEBlock *Block = new DIEBlock(); Block->AddUInt(DW_FORM_data1, DW_OP_addr); - Block->AddObjectLabel(DW_FORM_udata, MangledName); + Block->AddObjectLabel(DW_FORM_udata, LinkageName); Block->ComputeSize(*this); VariableDie->AddBlock(DW_AT_location, 0, Block); ___ llvm-commits mailing list llvm-commits@cs.uiuc.edu http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
[llvm-commits] CVS: llvm/include/llvm/CodeGen/MachineJumpTableInfo.h
Changes in directory llvm/include/llvm/CodeGen:
MachineJumpTableInfo.h updated: 1.3 -> 1.4
---
Log message:
add a ReplaceMBBInJumpTables method
---
Diffs of the changes: (+12 -0)
MachineJumpTableInfo.h | 12
1 files changed, 12 insertions(+)
Index: llvm/include/llvm/CodeGen/MachineJumpTableInfo.h
diff -u llvm/include/llvm/CodeGen/MachineJumpTableInfo.h:1.3
llvm/include/llvm/CodeGen/MachineJumpTableInfo.h:1.4
--- llvm/include/llvm/CodeGen/MachineJumpTableInfo.h:1.3Tue May 2
20:29:56 2006
+++ llvm/include/llvm/CodeGen/MachineJumpTableInfo.hMon Oct 16 15:41:42 2006
@@ -26,6 +26,7 @@
namespace llvm {
class MachineBasicBlock;
+class TargetData;
/// MachineJumpTableEntry - One jump table in the jump table info.
///
@@ -54,6 +55,17 @@
return JumpTables;
}
+ /// ReplaceMBBInJumpTables - If Old is the target of any jump tables, update
+ /// the jump tables to branch to New instead.
+ void ReplaceMBBInJumpTables(MachineBasicBlock *Old, MachineBasicBlock *New) {
+for (unsigned i = 0, e = JumpTables.size(); i != e; ++i) {
+ MachineJumpTableEntry &JTE = JumpTables[i];
+ for (unsigned j = 0, e = JTE.MBBs.size(); j != e; ++j)
+if (JTE.MBBs[j] == Old)
+ JTE.MBBs[j] = New;
+}
+ }
+
/// getEntrySize - returns the size of an individual field in a jump table
unsigned getEntrySize() const;
___
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[llvm-commits] CVS: llvm/include/llvm/CodeGen/SelectionDAG.h
Changes in directory llvm/include/llvm/CodeGen:
SelectionDAG.h updated: 1.137 -> 1.138
---
Log message:
Pass AliasAnalysis thru to DAGCombiner.
---
Diffs of the changes: (+2 -1)
SelectionDAG.h |3 ++-
1 files changed, 2 insertions(+), 1 deletion(-)
Index: llvm/include/llvm/CodeGen/SelectionDAG.h
diff -u llvm/include/llvm/CodeGen/SelectionDAG.h:1.137
llvm/include/llvm/CodeGen/SelectionDAG.h:1.138
--- llvm/include/llvm/CodeGen/SelectionDAG.h:1.137 Fri Oct 13 19:41:01 2006
+++ llvm/include/llvm/CodeGen/SelectionDAG.hMon Oct 16 15:52:31 2006
@@ -25,6 +25,7 @@
#include
namespace llvm {
+ class AliasAnalysis;
class TargetLowering;
class TargetMachine;
class MachineDebugInfo;
@@ -116,7 +117,7 @@
/// certain types of nodes together, or eliminating superfluous nodes. When
/// the AfterLegalize argument is set to 'true', Combine takes care not to
/// generate any nodes that will be illegal on the target.
- void Combine(bool AfterLegalize);
+ void Combine(bool AfterLegalize, AliasAnalysis &AA);
/// Legalize - This transforms the SelectionDAG into a SelectionDAG that is
/// compatible with the target instruction selector, as indicated by the
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[llvm-commits] CVS: llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp SelectionDAGISel.cpp
Changes in directory llvm/lib/CodeGen/SelectionDAG:
DAGCombiner.cpp updated: 1.224 -> 1.225
SelectionDAGISel.cpp updated: 1.288 -> 1.289
---
Log message:
Pass AliasAnalysis thru to DAGCombiner.
---
Diffs of the changes: (+18 -6)
DAGCombiner.cpp | 15 +++
SelectionDAGISel.cpp |9 +++--
2 files changed, 18 insertions(+), 6 deletions(-)
Index: llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
diff -u llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp:1.224
llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp:1.225
--- llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp:1.224 Sat Oct 14 07:14:27 2006
+++ llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp Mon Oct 16 15:52:31 2006
@@ -30,6 +30,7 @@
#define DEBUG_TYPE "dagcombine"
#include "llvm/ADT/Statistic.h"
+#include "llvm/Analysis/AliasAnalysis.h"
#include "llvm/CodeGen/SelectionDAG.h"
#include "llvm/Support/Debug.h"
#include "llvm/Support/MathExtras.h"
@@ -60,6 +61,9 @@
// Worklist of all of the nodes that need to be simplified.
std::vector WorkList;
+// AA - Used for DAG load/store alias analysis.
+AliasAnalysis &AA;
+
/// AddUsersToWorkList - When an instruction is simplified, add all users
of
/// the instruction to the work lists because they might get more
simplified
/// now.
@@ -262,8 +266,11 @@
SDOperand FindBetterChain(SDNode *N, SDOperand Chain);
public:
-DAGCombiner(SelectionDAG &D)
- : DAG(D), TLI(D.getTargetLoweringInfo()), AfterLegalize(false) {}
+DAGCombiner(SelectionDAG &D, AliasAnalysis &A)
+ : DAG(D),
+TLI(D.getTargetLoweringInfo()),
+AfterLegalize(false),
+AA(A) {}
/// Run - runs the dag combiner on all nodes in the work list
void Run(bool RunningAfterLegalize);
@@ -4133,8 +4140,8 @@
// SelectionDAG::Combine - This is the entry point for the file.
//
-void SelectionDAG::Combine(bool RunningAfterLegalize) {
+void SelectionDAG::Combine(bool RunningAfterLegalize, AliasAnalysis &AA) {
/// run - This is the main entry point to this class.
///
- DAGCombiner(*this).Run(RunningAfterLegalize);
+ DAGCombiner(*this, AA).Run(RunningAfterLegalize);
}
Index: llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
diff -u llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp:1.288
llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp:1.289
--- llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp:1.288Fri Oct 13
16:12:22 2006
+++ llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp Mon Oct 16 15:52:31 2006
@@ -12,6 +12,7 @@
//===--===//
#define DEBUG_TYPE "isel"
+#include "llvm/Analysis/AliasAnalysis.h"
#include "llvm/CodeGen/SelectionDAGISel.h"
#include "llvm/CodeGen/ScheduleDAG.h"
#include "llvm/CallingConv.h"
@@ -2951,6 +2952,7 @@
void SelectionDAGISel::getAnalysisUsage(AnalysisUsage &AU) const {
// FIXME: we only modify the CFG to split critical edges. This
// updates dom and loop info.
+ AU.addRequired();
}
@@ -3546,8 +3548,11 @@
}
void SelectionDAGISel::CodeGenAndEmitDAG(SelectionDAG &DAG) {
+ // Get alias analysis for load/store combining.
+ AliasAnalysis &AA = getAnalysis();
+
// Run the DAG combiner in pre-legalize mode.
- DAG.Combine(false);
+ DAG.Combine(false, AA);
DEBUG(std::cerr << "Lowered selection DAG:\n");
DEBUG(DAG.dump());
@@ -3560,7 +3565,7 @@
DEBUG(DAG.dump());
// Run the DAG combiner in post-legalize mode.
- DAG.Combine(true);
+ DAG.Combine(true, AA);
if (ViewISelDAGs) DAG.viewGraph();
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[llvm-commits] CVS: llvm/lib/Target/X86/X86Subtarget.cpp X86Subtarget.h
Changes in directory llvm/lib/Target/X86:
X86Subtarget.cpp updated: 1.36 -> 1.37
X86Subtarget.h updated: 1.19 -> 1.20
---
Log message:
Proper fix for rdar://problem/4770604 Thanks to Stuart Hastings!
---
Diffs of the changes: (+21 -12)
X86Subtarget.cpp | 25 +
X86Subtarget.h |8
2 files changed, 21 insertions(+), 12 deletions(-)
Index: llvm/lib/Target/X86/X86Subtarget.cpp
diff -u llvm/lib/Target/X86/X86Subtarget.cpp:1.36
llvm/lib/Target/X86/X86Subtarget.cpp:1.37
--- llvm/lib/Target/X86/X86Subtarget.cpp:1.36 Fri Oct 6 13:57:51 2006
+++ llvm/lib/Target/X86/X86Subtarget.cppMon Oct 16 16:00:37 2006
@@ -26,21 +26,22 @@
clEnumValN(X86Subtarget::intel, "intel", " Emit Intel-style assembly"),
clEnumValEnd));
+
/// GetCpuIDAndInfo - Execute the specified cpuid and return the 4 values in
the
/// specified arguments. If we can't run cpuid on the host, return true.
-static inline bool GetCpuIDAndInfo(unsigned value, unsigned *rEAX,
- unsigned *rEBX, unsigned *rECX,
- unsigned *rEDX) {
+bool X86::GetCpuIDAndInfo(unsigned value, unsigned *rEAX, unsigned *rEBX,
+ unsigned *rECX, unsigned *rEDX) {
#if defined(__x86_64__)
- asm ("pushq\t%%rbx\n\t"
- "cpuid\n\t"
+ unsigned long long saveRBX;
+ asm ("nop" : "=b" (saveRBX));
+ asm ("cpuid\n\t"
"movl\t%%ebx, %%esi\n\t"
- "popq\t%%rbx"
: "=a" (*rEAX),
"=S" (*rEBX),
"=c" (*rECX),
"=d" (*rEDX)
: "a" (value));
+ asm ("nop" :: "b" (saveRBX));
return false;
#elif defined(i386) || defined(__i386__) || defined(__x86__) ||
defined(_M_IX86)
#if defined(__GNUC__)
@@ -80,30 +81,30 @@
char c[12];
} text;
- if (GetCpuIDAndInfo(0, &EAX, text.u+0, text.u+2, text.u+1))
+ if (X86::GetCpuIDAndInfo(0, &EAX, text.u+0, text.u+2, text.u+1))
return;
// FIXME: support for AMD family of processors.
if (memcmp(text.c, "GenuineIntel", 12) == 0) {
-GetCpuIDAndInfo(0x1, &EAX, &EBX, &ECX, &EDX);
+X86::GetCpuIDAndInfo(0x1, &EAX, &EBX, &ECX, &EDX);
if ((EDX >> 23) & 0x1) X86SSELevel = MMX;
if ((EDX >> 25) & 0x1) X86SSELevel = SSE1;
if ((EDX >> 26) & 0x1) X86SSELevel = SSE2;
if (ECX & 0x1) X86SSELevel = SSE3;
-GetCpuIDAndInfo(0x8001, &EAX, &EBX, &ECX, &EDX);
+X86::GetCpuIDAndInfo(0x8001, &EAX, &EBX, &ECX, &EDX);
HasX86_64 = (EDX >> 29) & 0x1;
}
}
static const char *GetCurrentX86CPU() {
unsigned EAX = 0, EBX = 0, ECX = 0, EDX = 0;
- if (GetCpuIDAndInfo(0x1, &EAX, &EBX, &ECX, &EDX))
+ if (X86::GetCpuIDAndInfo(0x1, &EAX, &EBX, &ECX, &EDX))
return "generic";
unsigned Family = (EAX >> 8) & 0xf; // Bits 8 - 11
unsigned Model = (EAX >> 4) & 0xf; // Bits 4 - 7
- GetCpuIDAndInfo(0x8001, &EAX, &EBX, &ECX, &EDX);
+ X86::GetCpuIDAndInfo(0x8001, &EAX, &EBX, &ECX, &EDX);
bool Em64T = (EDX >> 29) & 0x1;
union {
@@ -111,7 +112,7 @@
char c[12];
} text;
- GetCpuIDAndInfo(0, &EAX, text.u+0, text.u+2, text.u+1);
+ X86::GetCpuIDAndInfo(0, &EAX, text.u+0, text.u+2, text.u+1);
if (memcmp(text.c, "GenuineIntel", 12) == 0) {
switch (Family) {
case 3:
Index: llvm/lib/Target/X86/X86Subtarget.h
diff -u llvm/lib/Target/X86/X86Subtarget.h:1.19
llvm/lib/Target/X86/X86Subtarget.h:1.20
--- llvm/lib/Target/X86/X86Subtarget.h:1.19 Fri Oct 6 04:17:41 2006
+++ llvm/lib/Target/X86/X86Subtarget.h Mon Oct 16 16:00:37 2006
@@ -106,6 +106,14 @@
bool isTargetWindows() const { return TargetType == isWindows; }
bool isTargetCygwin() const { return TargetType == isCygwin; }
};
+
+namespace X86 {
+ /// GetCpuIDAndInfo - Execute the specified cpuid and return the 4 values in
+ /// the specified arguments. If we can't run cpuid on the host, return true.
+ bool GetCpuIDAndInfo(unsigned value, unsigned *rEAX, unsigned *rEBX,
+ unsigned *rECX, unsigned *rEDX);
+}
+
} // End llvm namespace
#endif
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[llvm-commits] CVS: llvm/lib/Target/X86/X86JITInfo.cpp
Changes in directory llvm/lib/Target/X86:
X86JITInfo.cpp updated: 1.27 -> 1.28
---
Log message:
Added a X86CompilationCallback variant which saves XMM argument registers for
targets with SSE.
---
Diffs of the changes: (+58 -1)
X86JITInfo.cpp | 59 -
1 files changed, 58 insertions(+), 1 deletion(-)
Index: llvm/lib/Target/X86/X86JITInfo.cpp
diff -u llvm/lib/Target/X86/X86JITInfo.cpp:1.27
llvm/lib/Target/X86/X86JITInfo.cpp:1.28
--- llvm/lib/Target/X86/X86JITInfo.cpp:1.27 Fri Sep 8 12:03:56 2006
+++ llvm/lib/Target/X86/X86JITInfo.cpp Mon Oct 16 16:01:55 2006
@@ -14,6 +14,7 @@
#define DEBUG_TYPE "jit"
#include "X86JITInfo.h"
#include "X86Relocations.h"
+#include "X86Subtarget.h"
#include "llvm/CodeGen/MachineCodeEmitter.h"
#include "llvm/Config/alloca.h"
#include
@@ -138,6 +139,45 @@
#endif
"popl%ebp\n"
"ret\n");
+
+ // Same as X86CompilationCallback but also saves XMM argument registers.
+ void X86CompilationCallback_SSE(void);
+ asm(
+".text\n"
+".align 8\n"
+".globl " ASMPREFIX "X86CompilationCallback_SSE\n"
+ ASMPREFIX "X86CompilationCallback_SSE:\n"
+"pushl %ebp\n"
+"movl%esp, %ebp\n"// Standard prologue
+#if FASTCC_NUM_INT_ARGS_INREGS > 0
+"pushl %eax\n"
+"pushl %edx\n" // Save EAX/EDX
+#endif
+"andl$-16, %esp\n"// Align ESP on 16-byte boundary
+// Save all XMM arg registers
+"subl$64, %esp\n"
+"movaps %xmm0, (%esp)\n"
+"movaps %xmm1, 16(%esp)\n"
+"movaps %xmm2, 32(%esp)\n"
+"movaps %xmm3, 48(%esp)\n"
+"subl$16, %esp\n"
+"movl4(%ebp), %eax\n" // Pass prev frame and return address
+"movl%eax, 4(%esp)\n"
+"movl%ebp, (%esp)\n"
+"call" ASMPREFIX "X86CompilationCallback2\n"
+"addl$16, %esp\n"
+"movaps 48(%esp), %xmm3\n"
+"movaps 32(%esp), %xmm2\n"
+"movaps 16(%esp), %xmm1\n"
+"movaps (%esp), %xmm0\n"
+"movl%ebp, %esp\n"// Restore ESP
+#if FASTCC_NUM_INT_ARGS_INREGS > 0
+"subl$8, %esp\n"
+"popl%edx\n"
+"popl%eax\n"
+#endif
+"popl%ebp\n"
+"ret\n");
#else
void X86CompilationCallback2(void);
@@ -215,13 +255,30 @@
TargetJITInfo::LazyResolverFn
X86JITInfo::getLazyResolverFunction(JITCompilerFn F) {
JITCompilerFunction = F;
+
+ unsigned EAX = 0, EBX = 0, ECX = 0, EDX = 0;
+ union {
+unsigned u[3];
+char c[12];
+ } text;
+
+ if (!X86::GetCpuIDAndInfo(0, &EAX, text.u+0, text.u+2, text.u+1)) {
+// FIXME: support for AMD family of processors.
+if (memcmp(text.c, "GenuineIntel", 12) == 0) {
+ X86::GetCpuIDAndInfo(0x1, &EAX, &EBX, &ECX, &EDX);
+ if ((EDX >> 25) & 0x1)
+return X86CompilationCallback_SSE;
+}
+ }
+
return X86CompilationCallback;
}
void *X86JITInfo::emitFunctionStub(void *Fn, MachineCodeEmitter &MCE) {
// Note, we cast to intptr_t here to silence a -pedantic warning that
// complains about casting a function pointer to a normal pointer.
- if (Fn != (void*)(intptr_t)X86CompilationCallback) {
+ if (Fn != (void*)(intptr_t)X86CompilationCallback &&
+ Fn != (void*)(intptr_t)X86CompilationCallback_SSE) {
MCE.startFunctionStub(5);
MCE.emitByte(0xE9);
MCE.emitWordLE((intptr_t)Fn-MCE.getCurrentPCValue()-4);
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[llvm-commits] CVS: llvm/lib/Target/ARM/ARMAsmPrinter.cpp ARMISelDAGToDAG.cpp ARMInstrInfo.td
Changes in directory llvm/lib/Target/ARM:
ARMAsmPrinter.cpp updated: 1.22 -> 1.23
ARMISelDAGToDAG.cpp updated: 1.70 -> 1.71
ARMInstrInfo.td updated: 1.56 -> 1.57
---
Log message:
expand ISD::SHL_PARTS, ISD::SRA_PARTS and ISD::SRL_PARTS
---
Diffs of the changes: (+20 -8)
ARMAsmPrinter.cpp |3 +--
ARMISelDAGToDAG.cpp | 15 +++
ARMInstrInfo.td | 10 --
3 files changed, 20 insertions(+), 8 deletions(-)
Index: llvm/lib/Target/ARM/ARMAsmPrinter.cpp
diff -u llvm/lib/Target/ARM/ARMAsmPrinter.cpp:1.22
llvm/lib/Target/ARM/ARMAsmPrinter.cpp:1.23
--- llvm/lib/Target/ARM/ARMAsmPrinter.cpp:1.22 Wed Oct 4 22:01:21 2006
+++ llvm/lib/Target/ARM/ARMAsmPrinter.cpp Mon Oct 16 16:10:32 2006
@@ -216,8 +216,7 @@
}
break;
case MachineOperand::MO_ExternalSymbol:
-assert(0 && "not implemented");
-abort();
+O << TAI->getGlobalPrefix() << MO.getSymbolName();
break;
case MachineOperand::MO_ConstantPoolIndex:
O << TAI->getPrivateGlobalPrefix() << "CPI" << getFunctionNumber()
Index: llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp
diff -u llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp:1.70
llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp:1.71
--- llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp:1.70Sat Oct 14 12:59:54 2006
+++ llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp Mon Oct 16 16:10:32 2006
@@ -72,6 +72,10 @@
setOperationAction(ISD::BRCOND,MVT::Other, Expand);
+ setOperationAction(ISD::SHL_PARTS, MVT::i32, Expand);
+ setOperationAction(ISD::SRA_PARTS, MVT::i32, Expand);
+ setOperationAction(ISD::SRL_PARTS, MVT::i32, Expand);
+
setOperationAction(ISD::VASTART, MVT::Other, Custom);
setOperationAction(ISD::VAEND, MVT::Other, Expand);
@@ -321,11 +325,14 @@
Chain = DAG.getNode(ISD::TokenFactor, MVT::Other,
&MemOpChains[0], MemOpChains.size());
- // If the callee is a GlobalAddress/ExternalSymbol node (quite common, every
- // direct call is) turn it into a TargetGlobalAddress/TargetExternalSymbol
- // node so that legalize doesn't hack it.
+ // If the callee is a GlobalAddress node (quite common, every direct call is)
+ // turn it into a TargetGlobalAddress node so that legalize doesn't hack it.
+ // Likewise ExternalSymbol -> TargetExternalSymbol.
+ assert(Callee.getValueType() == MVT::i32);
if (GlobalAddressSDNode *G = dyn_cast(Callee))
-Callee = DAG.getTargetGlobalAddress(G->getGlobal(), Callee.getValueType());
+Callee = DAG.getTargetGlobalAddress(G->getGlobal(), MVT::i32);
+ else if (ExternalSymbolSDNode *E = dyn_cast(Callee))
+Callee = DAG.getTargetExternalSymbol(E->getSymbol(), MVT::i32);
// If this is a direct call, pass the chain and the callee.
assert (Callee.Val);
Index: llvm/lib/Target/ARM/ARMInstrInfo.td
diff -u llvm/lib/Target/ARM/ARMInstrInfo.td:1.56
llvm/lib/Target/ARM/ARMInstrInfo.td:1.57
--- llvm/lib/Target/ARM/ARMInstrInfo.td:1.56Mon Oct 16 13:39:22 2006
+++ llvm/lib/Target/ARM/ARMInstrInfo.td Mon Oct 16 16:10:32 2006
@@ -128,8 +128,8 @@
def bx: InstARM<(ops), "bx r14", [(retflag)]>;
}
-let Defs = [R0, R1, R2, R3, R14] in {
- def bl: InstARM<(ops i32imm:$func, variable_ops), "bl $func", [(ARMcall
tglobaladdr:$func)]>;
+let noResults = 1, Defs = [R0, R1, R2, R3, R14] in {
+ def bl: InstARM<(ops i32imm:$func, variable_ops), "bl $func", []>;
}
def ldr : InstARM<(ops IntRegs:$dst, memri:$addr),
@@ -286,3 +286,9 @@
def FLDD : InstARM<(ops DFPRegs:$dst, IntRegs:$addr),
"fldd $dst, $addr",
[(set DFPRegs:$dst, (load IntRegs:$addr))]>;
+
+def : Pat<(ARMcall tglobaladdr:$dst),
+ (bl tglobaladdr:$dst)>;
+
+def : Pat<(ARMcall texternalsym:$dst),
+ (bl texternalsym:$dst)>;
___
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[llvm-commits] CVS: llvm/test/Regression/CodeGen/ARM/longarith.ll
Changes in directory llvm/test/Regression/CodeGen/ARM:
longarith.ll added (r1.1)
---
Log message:
expand ISD::SHL_PARTS, ISD::SRA_PARTS and ISD::SRL_PARTS
---
Diffs of the changes: (+24 -0)
longarith.ll | 24
1 files changed, 24 insertions(+)
Index: llvm/test/Regression/CodeGen/ARM/longarith.ll
diff -c /dev/null llvm/test/Regression/CodeGen/ARM/longarith.ll:1.1
*** /dev/null Mon Oct 16 16:10:42 2006
--- llvm/test/Regression/CodeGen/ARM/longarith.ll Mon Oct 16 16:10:32 2006
***
*** 0
--- 1,24
+ ; RUN: llvm-as < %s | llc -march=arm &&
+ ; RUN: llvm-as < %s | llc -march=arm | grep __ashldi3 &&
+ ; RUN: llvm-as < %s | llc -march=arm | grep __ashrdi3 &&
+ ; RUN: llvm-as < %s | llc -march=arm | grep __lshrdi3
+ uint %f1(ulong %x, ubyte %y) {
+ entry:
+ %a = shl ulong %x, ubyte %y
+ %b = cast ulong %a to uint
+ ret uint %b
+ }
+
+ uint %f2(long %x, ubyte %y) {
+ entry:
+ %a = shr long %x, ubyte %y
+ %b = cast long %a to uint
+ ret uint %b
+ }
+
+ uint %f3(ulong %x, ubyte %y) {
+ entry:
+ %a = shr ulong %x, ubyte %y
+ %b = cast ulong %a to uint
+ ret uint %b
+ }
___
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[llvm-commits] CVS: llvm/lib/Target/ARM/ARMInstrInfo.td
Changes in directory llvm/lib/Target/ARM: ARMInstrInfo.td updated: 1.57 -> 1.58 --- Log message: add fdivs e fdivd --- Diffs of the changes: (+2 -1) ARMInstrInfo.td |3 ++- 1 files changed, 2 insertions(+), 1 deletion(-) Index: llvm/lib/Target/ARM/ARMInstrInfo.td diff -u llvm/lib/Target/ARM/ARMInstrInfo.td:1.57 llvm/lib/Target/ARM/ARMInstrInfo.td:1.58 --- llvm/lib/Target/ARM/ARMInstrInfo.td:1.57Mon Oct 16 16:10:32 2006 +++ llvm/lib/Target/ARM/ARMInstrInfo.td Mon Oct 16 16:50:04 2006 @@ -276,7 +276,8 @@ def FMULS : FPBinOp<"fmuls", fmul>; def FMULD : DFPBinOp<"fmuld", fmul>; - +def FDIVS : FPBinOp<"fdivs", fdiv>; +def FDIVD : DFPBinOp<"fdivd", fdiv>; // Floating Point Load def FLDS : InstARM<(ops FPRegs:$dst, IntRegs:$addr), ___ llvm-commits mailing list llvm-commits@cs.uiuc.edu http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
[llvm-commits] CVS: llvm/test/Regression/CodeGen/ARM/fparith.ll
Changes in directory llvm/test/Regression/CodeGen/ARM:
fparith.ll updated: 1.3 -> 1.4
---
Log message:
add fdivs e fdivd
---
Diffs of the changes: (+15 -1)
fparith.ll | 16 +++-
1 files changed, 15 insertions(+), 1 deletion(-)
Index: llvm/test/Regression/CodeGen/ARM/fparith.ll
diff -u llvm/test/Regression/CodeGen/ARM/fparith.ll:1.3
llvm/test/Regression/CodeGen/ARM/fparith.ll:1.4
--- llvm/test/Regression/CodeGen/ARM/fparith.ll:1.3 Fri Oct 13 12:37:35 2006
+++ llvm/test/Regression/CodeGen/ARM/fparith.ll Mon Oct 16 16:50:04 2006
@@ -4,7 +4,9 @@
; RUN: llvm-as < %s | llc -march=arm | grep fmuls &&
; RUN: llvm-as < %s | llc -march=arm | grep fmuld &&
; RUN: llvm-as < %s | llc -march=arm | grep fnegs &&
-; RUN: llvm-as < %s | llc -march=arm | grep fnegd
+; RUN: llvm-as < %s | llc -march=arm | grep fnegd &&
+; RUN: llvm-as < %s | llc -march=arm | grep fdivs &&
+; RUN: llvm-as < %s | llc -march=arm | grep fdivd
float %f1(float %a, float %b) {
entry:
@@ -53,3 +55,15 @@
%tmp1 = sub double -0.00e+00, %a
ret double %tmp1
}
+
+float %f9(float %a, float %b) {
+entry:
+ %tmp1 = div float %a, %b
+ ret float %tmp1
+}
+
+double %f10(double %a, double %b) {
+entry:
+ %tmp1 = div double %a, %b
+ ret double %tmp1
+}
___
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[llvm-commits] CVS: llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
Changes in directory llvm/lib/CodeGen/SelectionDAG:
DAGCombiner.cpp updated: 1.225 -> 1.226
---
Log message:
Be careful when looking through a vbit_convert. Optimizing this:
(vector_shuffle
(vbitconvert (vbuildvector (copyfromreg v4f32), 1, v4f32), 4, f32),
(undef, undef, undef, undef), (0, 0, 0, 0), 4, f32)
to the
vbitconvert
is a very bad idea.
---
Diffs of the changes: (+11 -2)
DAGCombiner.cpp | 13 +++--
1 files changed, 11 insertions(+), 2 deletions(-)
Index: llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
diff -u llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp:1.225
llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp:1.226
--- llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp:1.225 Mon Oct 16 15:52:31 2006
+++ llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp Mon Oct 16 17:49:37 2006
@@ -3108,8 +3108,17 @@
// all scalar elements the same.
if (isSplat) {
SDNode *V = N0.Val;
-if (V->getOpcode() == ISD::VBIT_CONVERT)
- V = V->getOperand(0).Val;
+
+// If this is a vbit convert that changes the element type of the vector
but
+// not the number of vector elements, look through it. Be careful not to
+// look though conversions that change things like v4f32 to v2f64.
+if (V->getOpcode() == ISD::VBIT_CONVERT) {
+ SDOperand ConvInput = V->getOperand(0);
+ if (NumElts ==
+ ConvInput.getConstantOperandVal(ConvInput.getNumOperands()-2))
+V = ConvInput.Val;
+}
+
if (V->getOpcode() == ISD::VBUILD_VECTOR) {
unsigned NumElems = V->getNumOperands()-2;
if (NumElems > BaseIdx) {
___
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[llvm-commits] CVS: llvm/lib/Target/X86/X86JITInfo.cpp
Changes in directory llvm/lib/Target/X86:
X86JITInfo.cpp updated: 1.28 -> 1.29
---
Log message:
Unbreak x86-64 build.
---
Diffs of the changes: (+9 -2)
X86JITInfo.cpp | 11 +--
1 files changed, 9 insertions(+), 2 deletions(-)
Index: llvm/lib/Target/X86/X86JITInfo.cpp
diff -u llvm/lib/Target/X86/X86JITInfo.cpp:1.28
llvm/lib/Target/X86/X86JITInfo.cpp:1.29
--- llvm/lib/Target/X86/X86JITInfo.cpp:1.28 Mon Oct 16 16:01:55 2006
+++ llvm/lib/Target/X86/X86JITInfo.cpp Mon Oct 16 17:53:28 2006
@@ -256,6 +256,7 @@
X86JITInfo::getLazyResolverFunction(JITCompilerFn F) {
JITCompilerFunction = F;
+#if !defined(__x86_64__)
unsigned EAX = 0, EBX = 0, ECX = 0, EDX = 0;
union {
unsigned u[3];
@@ -270,6 +271,7 @@
return X86CompilationCallback_SSE;
}
}
+#endif
return X86CompilationCallback;
}
@@ -277,8 +279,13 @@
void *X86JITInfo::emitFunctionStub(void *Fn, MachineCodeEmitter &MCE) {
// Note, we cast to intptr_t here to silence a -pedantic warning that
// complains about casting a function pointer to a normal pointer.
- if (Fn != (void*)(intptr_t)X86CompilationCallback &&
- Fn != (void*)(intptr_t)X86CompilationCallback_SSE) {
+#if defined(__x86_64__)
+ bool NotCC = Fn != (void*)(intptr_t)X86CompilationCallback;
+#else
+ bool NotCC = (Fn != (void*)(intptr_t)X86CompilationCallback &&
+Fn != (void*)(intptr_t)X86CompilationCallback_SSE);
+#endif
+ if (NotCC) {
MCE.startFunctionStub(5);
MCE.emitByte(0xE9);
MCE.emitWordLE((intptr_t)Fn-MCE.getCurrentPCValue()-4);
___
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[llvm-commits] CVS: llvm/lib/Transforms/Scalar/InstructionCombining.cpp
Changes in directory llvm/lib/Transforms/Scalar: InstructionCombining.cpp updated: 1.519 -> 1.520 --- Log message: Undo Chris' last patch, it caused a regression. --- Diffs of the changes: (+2 -2) InstructionCombining.cpp |4 ++-- 1 files changed, 2 insertions(+), 2 deletions(-) Index: llvm/lib/Transforms/Scalar/InstructionCombining.cpp diff -u llvm/lib/Transforms/Scalar/InstructionCombining.cpp:1.519 llvm/lib/Transforms/Scalar/InstructionCombining.cpp:1.520 --- llvm/lib/Transforms/Scalar/InstructionCombining.cpp:1.519 Sun Oct 15 17:42:15 2006 +++ llvm/lib/Transforms/Scalar/InstructionCombining.cpp Mon Oct 16 18:08:08 2006 @@ -1970,10 +1970,10 @@ return BinaryOperator::createAnd(Op0, NewNot); } - // -(X sdiv C) -> (X sdiv -C) + // 0 - (X sdiv C) -> (X sdiv -C) if (Op1I->getOpcode() == Instruction::Div) if (ConstantSInt *CSI = dyn_cast(Op0)) - if (!CSI->isNullValue()) + if (CSI->isNullValue()) if (Constant *DivRHS = dyn_cast(Op1I->getOperand(1))) return BinaryOperator::createDiv(Op1I->getOperand(0), ConstantExpr::getNeg(DivRHS)); ___ llvm-commits mailing list llvm-commits@cs.uiuc.edu http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
[llvm-commits] CVS: llvm/lib/Target/X86/X86JITInfo.cpp
Changes in directory llvm/lib/Target/X86:
X86JITInfo.cpp updated: 1.29 -> 1.30
---
Log message:
One more try.
---
Diffs of the changes: (+6 -4)
X86JITInfo.cpp | 10 ++
1 files changed, 6 insertions(+), 4 deletions(-)
Index: llvm/lib/Target/X86/X86JITInfo.cpp
diff -u llvm/lib/Target/X86/X86JITInfo.cpp:1.29
llvm/lib/Target/X86/X86JITInfo.cpp:1.30
--- llvm/lib/Target/X86/X86JITInfo.cpp:1.29 Mon Oct 16 17:53:28 2006
+++ llvm/lib/Target/X86/X86JITInfo.cpp Mon Oct 16 18:44:08 2006
@@ -256,7 +256,8 @@
X86JITInfo::getLazyResolverFunction(JITCompilerFn F) {
JITCompilerFunction = F;
-#if !defined(__x86_64__)
+#if (defined(__i386__) || defined(i386) || defined(_M_IX86)) && \
+ !defined(_MSC_VER) && !defined(__x86_64__)
unsigned EAX = 0, EBX = 0, ECX = 0, EDX = 0;
union {
unsigned u[3];
@@ -279,11 +280,12 @@
void *X86JITInfo::emitFunctionStub(void *Fn, MachineCodeEmitter &MCE) {
// Note, we cast to intptr_t here to silence a -pedantic warning that
// complains about casting a function pointer to a normal pointer.
-#if defined(__x86_64__)
- bool NotCC = Fn != (void*)(intptr_t)X86CompilationCallback;
-#else
+#if (defined(__i386__) || defined(i386) || defined(_M_IX86)) && \
+ !defined(_MSC_VER) && !defined(__x86_64__)
bool NotCC = (Fn != (void*)(intptr_t)X86CompilationCallback &&
Fn != (void*)(intptr_t)X86CompilationCallback_SSE);
+#else
+ bool NotCC = Fn != (void*)(intptr_t)X86CompilationCallback;
#endif
if (NotCC) {
MCE.startFunctionStub(5);
___
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[llvm-commits] CVS: llvm/lib/Target/X86/X86Subtarget.cpp
Changes in directory llvm/lib/Target/X86:
X86Subtarget.cpp updated: 1.37 -> 1.38
---
Log message:
Proper fix.
---
Diffs of the changes: (+4 -5)
X86Subtarget.cpp |9 -
1 files changed, 4 insertions(+), 5 deletions(-)
Index: llvm/lib/Target/X86/X86Subtarget.cpp
diff -u llvm/lib/Target/X86/X86Subtarget.cpp:1.37
llvm/lib/Target/X86/X86Subtarget.cpp:1.38
--- llvm/lib/Target/X86/X86Subtarget.cpp:1.37 Mon Oct 16 16:00:37 2006
+++ llvm/lib/Target/X86/X86Subtarget.cppMon Oct 16 19:24:49 2006
@@ -32,16 +32,15 @@
bool X86::GetCpuIDAndInfo(unsigned value, unsigned *rEAX, unsigned *rEBX,
unsigned *rECX, unsigned *rEDX) {
#if defined(__x86_64__)
- unsigned long long saveRBX;
- asm ("nop" : "=b" (saveRBX));
- asm ("cpuid\n\t"
- "movl\t%%ebx, %%esi\n\t"
+ // gcc doesn't know cpuid would clobber ebx/rbx. Preseve it manually.
+ asm ("movq\t%%rbx, %%rsi\n\t"
+ "cpuid\n\t"
+ "xchgq\t%%rbx, %%rsi\n\t"
: "=a" (*rEAX),
"=S" (*rEBX),
"=c" (*rECX),
"=d" (*rEDX)
: "a" (value));
- asm ("nop" :: "b" (saveRBX));
return false;
#elif defined(i386) || defined(__i386__) || defined(__x86__) ||
defined(_M_IX86)
#if defined(__GNUC__)
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