[llvm-commits] CVS: llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp
Changes in directory llvm/lib/Target/ARM: ARMISelDAGToDAG.cpp updated: 1.58 -> 1.59 --- Log message: expand ISD::EXTLOAD --- Diffs of the changes: (+2 -0) ARMISelDAGToDAG.cpp |2 ++ 1 files changed, 2 insertions(+) Index: llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp diff -u llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp:1.58 llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp:1.59 --- llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp:1.58Sat Oct 7 09:24:52 2006 +++ llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp Mon Oct 9 09:13:40 2006 @@ -47,6 +47,8 @@ addRegisterClass(MVT::f32, ARM::FPRegsRegisterClass); addRegisterClass(MVT::f64, ARM::DFPRegsRegisterClass); + setLoadXAction(ISD::EXTLOAD, MVT::f32, Expand); + setOperationAction(ISD::SINT_TO_FP, MVT::i32, Custom); setOperationAction(ISD::UINT_TO_FP, MVT::i32, Custom); ___ llvm-commits mailing list llvm-commits@cs.uiuc.edu http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
[llvm-commits] CVS: llvm/lib/Target/ARM/README.txt
Changes in directory llvm/lib/Target/ARM:
README.txt updated: 1.4 -> 1.5
---
Log message:
add a note
---
Diffs of the changes: (+14 -0)
README.txt | 14 ++
1 files changed, 14 insertions(+)
Index: llvm/lib/Target/ARM/README.txt
diff -u llvm/lib/Target/ARM/README.txt:1.4 llvm/lib/Target/ARM/README.txt:1.5
--- llvm/lib/Target/ARM/README.txt:1.4 Sat Oct 7 09:03:39 2006
+++ llvm/lib/Target/ARM/README.txt Mon Oct 9 09:18:33 2006
@@ -32,3 +32,17 @@
add an offset to FLDS/FLDD addressing mode
--
+
+the function
+
+void %f() {
+entry:
+ call void %g( int 1, int 2, int 3, int 4, int 5 )
+ ret void
+}
+
+declare void %g(int, int, int, int, int)
+
+Only needs 8 bytes of stack space. We currently allocate 16.
+
+--
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[llvm-commits] CVS: llvm/lib/Target/ARM/ARMTargetMachine.cpp
Changes in directory llvm/lib/Target/ARM:
ARMTargetMachine.cpp updated: 1.10 -> 1.11
---
Log message:
most ARM targets are little endian
---
Diffs of the changes: (+1 -1)
ARMTargetMachine.cpp |2 +-
1 files changed, 1 insertion(+), 1 deletion(-)
Index: llvm/lib/Target/ARM/ARMTargetMachine.cpp
diff -u llvm/lib/Target/ARM/ARMTargetMachine.cpp:1.10
llvm/lib/Target/ARM/ARMTargetMachine.cpp:1.11
--- llvm/lib/Target/ARM/ARMTargetMachine.cpp:1.10 Tue Sep 19 10:49:24 2006
+++ llvm/lib/Target/ARM/ARMTargetMachine.cppMon Oct 9 09:12:15 2006
@@ -34,7 +34,7 @@
/// TargetMachine ctor - Create an ILP32 architecture model
///
ARMTargetMachine::ARMTargetMachine(const Module &M, const std::string &FS)
- : DataLayout("E-p:32:32") {
+ : DataLayout("e-p:32:32") {
}
unsigned ARMTargetMachine::getModuleMatchQuality(const Module &M) {
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[llvm-commits] CVS: llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp
Changes in directory llvm/lib/Target/ARM: ARMISelDAGToDAG.cpp updated: 1.59 -> 1.60 --- Log message: expand ISD::SELECT --- Diffs of the changes: (+2 -0) ARMISelDAGToDAG.cpp |2 ++ 1 files changed, 2 insertions(+) Index: llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp diff -u llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp:1.59 llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp:1.60 --- llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp:1.59Mon Oct 9 09:13:40 2006 +++ llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp Mon Oct 9 11:28:33 2006 @@ -57,6 +57,8 @@ setOperationAction(ISD::GlobalAddress, MVT::i32, Custom); setOperationAction(ISD::ConstantPool, MVT::i32, Custom); + setOperationAction(ISD::SELECT, MVT::i32, Expand); + setOperationAction(ISD::SETCC, MVT::i32, Expand); setOperationAction(ISD::SELECT_CC, MVT::i32, Custom); setOperationAction(ISD::BR_CC, MVT::i32, Custom); ___ llvm-commits mailing list llvm-commits@cs.uiuc.edu http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
[llvm-commits] CVS: llvm/lib/Target/ARM/ARMInstrInfo.td
Changes in directory llvm/lib/Target/ARM:
ARMInstrInfo.td updated: 1.36 -> 1.37
---
Log message:
add ADDS and ADCS
---
Diffs of the changes: (+8 -0)
ARMInstrInfo.td |8
1 files changed, 8 insertions(+)
Index: llvm/lib/Target/ARM/ARMInstrInfo.td
diff -u llvm/lib/Target/ARM/ARMInstrInfo.td:1.36
llvm/lib/Target/ARM/ARMInstrInfo.td:1.37
--- llvm/lib/Target/ARM/ARMInstrInfo.td:1.36Sat Oct 7 09:24:52 2006
+++ llvm/lib/Target/ARM/ARMInstrInfo.td Mon Oct 9 12:18:28 2006
@@ -117,6 +117,14 @@
"add $dst, $a, $b",
[(set IntRegs:$dst, (add IntRegs:$a, addr_mode1:$b))]>;
+def ADCS: InstARM<(ops IntRegs:$dst, IntRegs:$a, op_addr_mode1:$b),
+ "adcs $dst, $a, $b",
+ [(set IntRegs:$dst, (adde IntRegs:$a, addr_mode1:$b))]>;
+
+def ADDS: InstARM<(ops IntRegs:$dst, IntRegs:$a, op_addr_mode1:$b),
+ "adds $dst, $a, $b",
+ [(set IntRegs:$dst, (addc IntRegs:$a, addr_mode1:$b))]>;
+
// "LEA" forms of add
def lea_addri : InstARM<(ops IntRegs:$dst, memri:$addr),
"add $dst, ${addr:arith}",
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[llvm-commits] CVS: llvm/test/Regression/CodeGen/ARM/long.ll
Changes in directory llvm/test/Regression/CodeGen/ARM:
long.ll updated: 1.2 -> 1.3
---
Log message:
add a test for adds adcs
---
Diffs of the changes: (+9 -1)
long.ll | 10 +-
1 files changed, 9 insertions(+), 1 deletion(-)
Index: llvm/test/Regression/CodeGen/ARM/long.ll
diff -u llvm/test/Regression/CodeGen/ARM/long.ll:1.2
llvm/test/Regression/CodeGen/ARM/long.ll:1.3
--- llvm/test/Regression/CodeGen/ARM/long.ll:1.2Thu Sep 21 06:29:52 2006
+++ llvm/test/Regression/CodeGen/ARM/long.llMon Oct 9 12:30:15 2006
@@ -3,7 +3,9 @@
; RUN: llvm-as < %s | llc -march=arm | grep "mov r0, #1" | wc -l | grep 1 &&
; RUN: llvm-as < %s | llc -march=arm | grep ".word.*2147483647" | wc -l | grep
2 &&
; RUN: llvm-as < %s | llc -march=arm | grep "mov r0, #-2147483648" | wc -l |
grep 1 &&
-; RUN: llvm-as < %s | llc -march=arm | grep ".word.*4294967295" | wc -l | grep
1
+; RUN: llvm-as < %s | llc -march=arm | grep ".word.*4294967295" | wc -l | grep
1 &&
+; RUN: llvm-as < %s | llc -march=arm | grep "adds" | wc -l | grep 1 &&
+; RUN: llvm-as < %s | llc -march=arm | grep "adcs" | wc -l | grep 1
long %f1() {
entry:
@@ -29,3 +31,9 @@
entry:
ret long 9223372036854775807
}
+
+ulong %f6(ulong %x, ulong %y) {
+entry:
+ %tmp1 = add ulong %y, 1
+ ret ulong %tmp1
+}
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[llvm-commits] CVS: llvm/test/Regression/CodeGen/Alpha/jmp_table.ll
Changes in directory llvm/test/Regression/CodeGen/Alpha: jmp_table.ll updated: 1.3 -> 1.4 --- Log message: xfail this until andrew has a chance to implement the alpha TM method. --- Diffs of the changes: (+2 -0) jmp_table.ll |2 ++ 1 files changed, 2 insertions(+) Index: llvm/test/Regression/CodeGen/Alpha/jmp_table.ll diff -u llvm/test/Regression/CodeGen/Alpha/jmp_table.ll:1.3 llvm/test/Regression/CodeGen/Alpha/jmp_table.ll:1.4 --- llvm/test/Regression/CodeGen/Alpha/jmp_table.ll:1.3 Wed Oct 4 22:27:52 2006 +++ llvm/test/Regression/CodeGen/Alpha/jmp_table.ll Mon Oct 9 12:34:40 2006 @@ -4,6 +4,8 @@ ; RUN: llvm-as < %s | llc -march=alpha | grep 'ldl' && ; RUN: llvm-as < %s | llc -march=alpha | grep 'rodata' +; XFAIL: * + target endian = little target pointersize = 64 target triple = "alphaev67-unknown-linux-gnu" ___ llvm-commits mailing list llvm-commits@cs.uiuc.edu http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
[llvm-commits] CVS: llvm/lib/Analysis/IPA/CallGraph.cpp
Changes in directory llvm/lib/Analysis/IPA:
CallGraph.cpp updated: 1.57 -> 1.58
---
Log message:
Fix a bug pointed out by Zhongxing Xu
---
Diffs of the changes: (+1 -1)
CallGraph.cpp |2 +-
1 files changed, 1 insertion(+), 1 deletion(-)
Index: llvm/lib/Analysis/IPA/CallGraph.cpp
diff -u llvm/lib/Analysis/IPA/CallGraph.cpp:1.57
llvm/lib/Analysis/IPA/CallGraph.cpp:1.58
--- llvm/lib/Analysis/IPA/CallGraph.cpp:1.57Sun Aug 27 19:42:29 2006
+++ llvm/lib/Analysis/IPA/CallGraph.cpp Mon Oct 9 12:28:13 2006
@@ -193,7 +193,7 @@
}
void CallGraph::destroy() {
- if(!FunctionMap.size()) {
+ if (!FunctionMap.empty()) {
for (FunctionMapTy::iterator I = FunctionMap.begin(), E =
FunctionMap.end();
I != E; ++I)
delete I->second;
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[llvm-commits] CVS: llvm/test/Regression/CodeGen/ARM/fpconv.ll
Changes in directory llvm/test/Regression/CodeGen/ARM:
fpconv.ll added (r1.1)
---
Log message:
add float -> double and double -> float conversion
---
Diffs of the changes: (+15 -0)
fpconv.ll | 15 +++
1 files changed, 15 insertions(+)
Index: llvm/test/Regression/CodeGen/ARM/fpconv.ll
diff -c /dev/null llvm/test/Regression/CodeGen/ARM/fpconv.ll:1.1
*** /dev/null Mon Oct 9 12:50:39 2006
--- llvm/test/Regression/CodeGen/ARM/fpconv.ll Mon Oct 9 12:50:29 2006
***
*** 0
--- 1,15
+ ; RUN: llvm-as < %s | llc -march=arm &&
+ ; RUN: llvm-as < %s | llc -march=arm | grep fcvtds &&
+ ; RUN: llvm-as < %s | llc -march=arm | grep fcvtsd
+
+ float %f(double %x) {
+ entry:
+ %tmp1 = cast double %x to float
+ ret float %tmp1
+ }
+
+ double %g(float %x) {
+ entry:
+ %tmp1 = cast float %x to double
+ ret double %tmp1
+ }
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[llvm-commits] CVS: llvm/lib/Target/ARM/ARMInstrInfo.td
Changes in directory llvm/lib/Target/ARM: ARMInstrInfo.td updated: 1.37 -> 1.38 --- Log message: add float -> double and double -> float conversion --- Diffs of the changes: (+5 -0) ARMInstrInfo.td |5 + 1 files changed, 5 insertions(+) Index: llvm/lib/Target/ARM/ARMInstrInfo.td diff -u llvm/lib/Target/ARM/ARMInstrInfo.td:1.37 llvm/lib/Target/ARM/ARMInstrInfo.td:1.38 --- llvm/lib/Target/ARM/ARMInstrInfo.td:1.37Mon Oct 9 12:18:28 2006 +++ llvm/lib/Target/ARM/ARMInstrInfo.td Mon Oct 9 12:50:29 2006 @@ -200,6 +200,11 @@ def FUITOD : InstARM<(ops DFPRegs:$dst, FPRegs:$src), "fuitod $dst, $src", [(set DFPRegs:$dst, (armfuitod FPRegs:$src))]>; +def FCVTDS : InstARM<(ops DFPRegs:$dst, FPRegs:$src), + "fcvtds $dst, $src", [(set DFPRegs:$dst, (fextend FPRegs:$src))]>; + +def FCVTSD : InstARM<(ops FPRegs:$dst, DFPRegs:$src), + "fcvtsd $dst, $src", [(set FPRegs:$dst, (fround DFPRegs:$src))]>; // Floating Point Arithmetic def FADDS : InstARM<(ops FPRegs:$dst, FPRegs:$a, FPRegs:$b), ___ llvm-commits mailing list llvm-commits@cs.uiuc.edu http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
[llvm-commits] CVS: llvm-test/Makefile.tests
Changes in directory llvm-test: Makefile.tests updated: 1.11 -> 1.12 --- Log message: Reverting patch from the weekend so that we have something to compare against for PR928: http://llvm.org/PR928 . --- Diffs of the changes: (+4 -4) Makefile.tests |8 1 files changed, 4 insertions(+), 4 deletions(-) Index: llvm-test/Makefile.tests diff -u llvm-test/Makefile.tests:1.11 llvm-test/Makefile.tests:1.12 --- llvm-test/Makefile.tests:1.11 Sun Oct 8 02:16:29 2006 +++ llvm-test/Makefile.testsMon Oct 9 13:24:03 2006 @@ -50,19 +50,19 @@ # Compile from X.c to Output/X.ll Output/%.ll: %.c $(LCC1) Output/.dir $(INCLUDES) - -$(LLVMGCC) $(CPPFLAGS) $(LCCFLAGS) $(TARGET_FLAGS) -S $< -o $@ -emit-llvm + -$(LLVMGCC) $(CPPFLAGS) $(LCCFLAGS) $(TARGET_FLAGS) -O0 -S $< -o $@ -emit-llvm # Compile from X.cpp to Output/X.ll Output/%.ll: %.cpp $(LCC1XX) Output/.dir $(INCLUDES) - -$(LLVMGXX) $(CPPFLAGS) $(LCXXFLAGS) $(TARGET_FLAGS) -S $< -o $@ -emit-llvm + -$(LLVMGXX) $(CPPFLAGS) $(LCXXFLAGS) $(TARGET_FLAGS) -O0 -S $< -o $@ -emit-llvm # Compile from X.cc to Output/X.ll Output/%.ll: %.cc $(LCC1XX) Output/.dir $(INCLUDES) - -$(LLVMGXX) $(CPPFLAGS) $(LCXXFLAGS) $(TARGET_FLAGS) -S $< -o $@ -emit-llvm + -$(LLVMGXX) $(CPPFLAGS) $(LCXXFLAGS) $(TARGET_FLAGS) -O0 -S $< -o $@ -emit-llvm # Compile from X.C to Output/X.ll Output/%.ll: %.C $(LCC1XX) Output/.dir $(INCLUDES) - -$(LLVMGXX) $(CPPFLAGS) $(LCXXFLAGS) $(TARGET_FLAGS) -S $< -o $@ -emit-llvm + -$(LLVMGXX) $(CPPFLAGS) $(LCXXFLAGS) $(TARGET_FLAGS) -O0 -S $< -o $@ -emit-llvm # LLVM Assemble from Output/X.ll to Output/X.bc. Output/X.ll must have come # from GCC output, so use GCCAS. ___ llvm-commits mailing list llvm-commits@cs.uiuc.edu http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
[llvm-commits] CVS: llvm/include/llvm/Support/InstVisitor.h
Changes in directory llvm/include/llvm/Support:
InstVisitor.h updated: 1.40 -> 1.41
---
Log message:
Fix usage example.
---
Diffs of the changes: (+1 -1)
InstVisitor.h |2 +-
1 files changed, 1 insertion(+), 1 deletion(-)
Index: llvm/include/llvm/Support/InstVisitor.h
diff -u llvm/include/llvm/Support/InstVisitor.h:1.40
llvm/include/llvm/Support/InstVisitor.h:1.41
--- llvm/include/llvm/Support/InstVisitor.h:1.40Wed May 31 10:30:18 2006
+++ llvm/include/llvm/Support/InstVisitor.h Mon Oct 9 13:33:08 2006
@@ -53,7 +53,7 @@
///unsigned Count;
///CountMallocVisitor() : Count(0) {}
///
-///void visitMallocInst(MallocInst *MI) { ++Count; }
+///void visitMallocInst(MallocInst &MI) { ++Count; }
/// };
///
/// And this class would be used like this:
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[llvm-commits] CVS: llvm/include/llvm/ADT/SmallVector.h
Changes in directory llvm/include/llvm/ADT:
SmallVector.h updated: 1.19 -> 1.20
---
Log message:
Fix build error in gcc 3.4 and make more this general
---
Diffs of the changes: (+1 -1)
SmallVector.h |2 +-
1 files changed, 1 insertion(+), 1 deletion(-)
Index: llvm/include/llvm/ADT/SmallVector.h
diff -u llvm/include/llvm/ADT/SmallVector.h:1.19
llvm/include/llvm/ADT/SmallVector.h:1.20
--- llvm/include/llvm/ADT/SmallVector.h:1.19Sun Oct 8 17:28:34 2006
+++ llvm/include/llvm/ADT/SmallVector.h Mon Oct 9 14:05:44 2006
@@ -35,7 +35,7 @@
protected:
#ifdef __GNUC__
typedef char U;
- U FirstEl __attribute__((aligned(__alignof__(double;
+ U FirstEl __attribute__((aligned));
#else
union U {
double D;
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[llvm-commits] CVS: llvm/tools/lto/lto.cpp
Changes in directory llvm/tools/lto:
lto.cpp updated: 1.17 -> 1.18
---
Log message:
Use GetTemporaryDirectory. Fix http://llvm.org/bugs/show_bug.cgi?id=894
---
Diffs of the changes: (+15 -2)
lto.cpp | 17 +++--
1 files changed, 15 insertions(+), 2 deletions(-)
Index: llvm/tools/lto/lto.cpp
diff -u llvm/tools/lto/lto.cpp:1.17 llvm/tools/lto/lto.cpp:1.18
--- llvm/tools/lto/lto.cpp:1.17 Thu Sep 21 12:22:55 2006
+++ llvm/tools/lto/lto.cpp Mon Oct 9 14:04:51 2006
@@ -341,18 +341,28 @@
exportList[i] = allSymbols[name]->getName();
}
- sys::Path tmpAsmFilePath("/tmp/");
+
std::string ErrMsg;
+ sys::Path TempDir = sys::Path::GetTemporaryDirectory(&ErrMsg);
+ sys::Path tmpAsmFilePath(TempDir);
+ if (!tmpAsmFilePath.appendComponent("lto")) {
+std::cerr << "lto: " << ErrMsg << "\n";
+TempDir.eraseFromDisk(true);
+return LTO_WRITE_FAILURE;
+ }
if (tmpAsmFilePath.createTemporaryFileOnDisk(&ErrMsg)) {
std::cerr << "lto: " << ErrMsg << "\n";
+TempDir.eraseFromDisk(true);
return LTO_WRITE_FAILURE;
}
sys::RemoveFileOnSignal(tmpAsmFilePath);
std::ofstream asmFile(tmpAsmFilePath.c_str(), io_mode);
if (!asmFile.is_open() || asmFile.bad()) {
-if (tmpAsmFilePath.exists())
+if (tmpAsmFilePath.exists()) {
tmpAsmFilePath.eraseFromDisk();
+ TempDir.eraseFromDisk(true);
+}
return LTO_WRITE_FAILURE;
}
@@ -360,6 +370,7 @@
asmFile.close();
if (status != LTO_OPT_SUCCESS) {
tmpAsmFilePath.eraseFromDisk();
+TempDir.eraseFromDisk(true);
return status;
}
@@ -374,6 +385,7 @@
const sys::Path gcc = FindExecutable("gcc", "/");
if (gcc.isEmpty()) {
tmpAsmFilePath.eraseFromDisk();
+TempDir.eraseFromDisk(true);
return LTO_ASM_FAILURE;
}
@@ -390,6 +402,7 @@
sys::Program::ExecuteAndWait(gcc, &args[0], 0, 0, 1);
tmpAsmFilePath.eraseFromDisk();
+ TempDir.eraseFromDisk(true);
return LTO_OPT_SUCCESS;
}
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[llvm-commits] CVS: llvm/test/Regression/CodeGen/ARM/fparith.ll
Changes in directory llvm/test/Regression/CodeGen/ARM:
fparith.ll added (r1.1)
---
Log message:
add some tests for floating point arithmetic
---
Diffs of the changes: (+29 -0)
fparith.ll | 29 +
1 files changed, 29 insertions(+)
Index: llvm/test/Regression/CodeGen/ARM/fparith.ll
diff -c /dev/null llvm/test/Regression/CodeGen/ARM/fparith.ll:1.1
*** /dev/null Mon Oct 9 14:15:27 2006
--- llvm/test/Regression/CodeGen/ARM/fparith.ll Mon Oct 9 14:15:17 2006
***
*** 0
--- 1,29
+ ; RUN: llvm-as < %s | llc -march=arm &&
+ ; RUN: llvm-as < %s | llc -march=arm | grep fadds &&
+ ; RUN: llvm-as < %s | llc -march=arm | grep faddd &&
+ ; RUN: llvm-as < %s | llc -march=arm | grep fmuls &&
+ ; RUN: llvm-as < %s | llc -march=arm | grep fmuld
+
+ float %f(float %a, float %b) {
+ entry:
+ %tmp = add float %a, %b
+ ret float %tmp
+ }
+
+ double %g(double %a, double %b) {
+ entry:
+ %tmp = add double %a, %b
+ ret double %tmp
+ }
+
+ float %h(float %a, float %b) {
+ entry:
+ %tmp = mul float %a, %b
+ ret float %tmp
+ }
+
+ double %i(double %a, double %b) {
+ entry:
+ %tmp = mul double %a, %b
+ ret double %tmp
+ }
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Re: [llvm-commits] CVS: llvm/include/llvm/ADT/SmallVector.h
Andrew,
...
On Mon, 2006-10-09 at 14:05 -0500, Andrew Lenharth wrote:
>
> Changes in directory llvm/include/llvm/ADT:
>
> SmallVector.h updated: 1.19 -> 1.20
> ---
> Log message:
>
> Fix build error in gcc 3.4 and make more this general
This compiled on my 3.4.6 compiler on Linux just fine before the patch.
What was the error you were trying to fix?
>
> ---
> Diffs of the changes: (+1 -1)
>
> SmallVector.h |2 +-
> 1 files changed, 1 insertion(+), 1 deletion(-)
>
>
> Index: llvm/include/llvm/ADT/SmallVector.h
> diff -u llvm/include/llvm/ADT/SmallVector.h:1.19
> llvm/include/llvm/ADT/SmallVector.h:1.20
> --- llvm/include/llvm/ADT/SmallVector.h:1.19 Sun Oct 8 17:28:34 2006
> +++ llvm/include/llvm/ADT/SmallVector.h Mon Oct 9 14:05:44 2006
> @@ -35,7 +35,7 @@
> protected:
> #ifdef __GNUC__
>typedef char U;
> - U FirstEl __attribute__((aligned(__alignof__(double;
> + U FirstEl __attribute__((aligned));
Are you sure this is right? In section 5.31 of the GCC Manual it
indicates that if an alignment size is not given with the aligned
attribute keyword then it defaults to:
"the maximum useful alignment for the target machine you are compiling
for. Whenever you leave out the alignment factor in an `aligned'
attribute specification, the compiler automatically sets the alignment
for the declared variable or field to the largest alignment which is
ever used for any data type on the target machine you are compiling
for".
Is this what we want here?
Reid.
> #else
>union U {
> double D;
>
>
>
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Re: [llvm-commits] CVS: llvm/include/llvm/ADT/SmallVector.h
> This compiled on my 3.4.6 compiler on Linux just fine before the patch. > What was the error you were trying to fix? "Allignment Value not constant" was the error. This was gcc 3.4.4 > Are you sure this is right? In section 5.31 of the GCC Manual it > indicates that if an alignment size is not given with the aligned > attribute keyword then it defaults to: > > "the maximum useful alignment for the target machine you are compiling > for. Whenever you leave out the alignment factor in an `aligned' > attribute specification, the compiler automatically sets the alignment > for the declared variable or field to the largest alignment which is > ever used for any data type on the target machine you are compiling > for". > > Is this what we want here? I believe so. The alignment of that field needs to be sufficient for any data type put there. The non-gcc version does that with a union. My reading of the gcc manual is that without a value, this attribute does exactly that (and since doubles are not always the most constrained types, vectors tend to be, this is more general, though I doubt altivec vectors are going to be used directly by LLVM in small vectors anytime soon). Andrew ___ llvm-commits mailing list llvm-commits@cs.uiuc.edu http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
Re: [llvm-commits] CVS: llvm/include/llvm/ADT/SmallVector.h
On Oct 9, 2006, at 12:56 PM, Andrew Lenharth wrote: >> >> Is this what we want here? > > I believe so. I agree, Andrew's patch looks great to me. -Chris ___ llvm-commits mailing list llvm-commits@cs.uiuc.edu http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
[llvm-commits] CVS: llvm/tools/bugpoint/ListReducer.h
Changes in directory llvm/tools/bugpoint:
ListReducer.h updated: 1.16 -> 1.17
---
Log message:
Remove a dead var noticed by Yorion
---
Diffs of the changes: (+0 -1)
ListReducer.h |1 -
1 files changed, 1 deletion(-)
Index: llvm/tools/bugpoint/ListReducer.h
diff -u llvm/tools/bugpoint/ListReducer.h:1.16
llvm/tools/bugpoint/ListReducer.h:1.17
--- llvm/tools/bugpoint/ListReducer.h:1.16 Wed May 24 12:04:04 2006
+++ llvm/tools/bugpoint/ListReducer.h Mon Oct 9 15:12:37 2006
@@ -103,7 +103,6 @@
std::vector EmptyList;
while (Changed) {
Changed = false;
-std::vector TrimmedList;
for (unsigned i = 1; i < TheList.size()-1; ++i) { // Check interior
elts
if (BugpointIsInterrupted) {
std::cerr << "\n\n*** Reduction Interrupted, cleaning up...\n\n";
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[llvm-commits] CVS: llvm/tools/lto/lto.cpp
Changes in directory llvm/tools/lto:
lto.cpp updated: 1.18 -> 1.19
---
Log message:
Do error checking.
---
Diffs of the changes: (+8 -1)
lto.cpp |9 -
1 files changed, 8 insertions(+), 1 deletion(-)
Index: llvm/tools/lto/lto.cpp
diff -u llvm/tools/lto/lto.cpp:1.18 llvm/tools/lto/lto.cpp:1.19
--- llvm/tools/lto/lto.cpp:1.18 Mon Oct 9 14:04:51 2006
+++ llvm/tools/lto/lto.cpp Mon Oct 9 15:20:13 2006
@@ -344,6 +344,10 @@
std::string ErrMsg;
sys::Path TempDir = sys::Path::GetTemporaryDirectory(&ErrMsg);
+ if (TempDir.isEmpty()) {
+std::cerr << "lto: " << ErrMsg << "\n";
+return LTO_WRITE_FAILURE;
+ }
sys::Path tmpAsmFilePath(TempDir);
if (!tmpAsmFilePath.appendComponent("lto")) {
std::cerr << "lto: " << ErrMsg << "\n";
@@ -399,7 +403,10 @@
args.push_back(tmpAsmFilePath.c_str());
args.push_back(0);
- sys::Program::ExecuteAndWait(gcc, &args[0], 0, 0, 1);
+ if (sys::Program::ExecuteAndWait(gcc, &args[0], 0, 0, 1, &ErrMsg)) {
+std::cerr << "lto: " << ErrMsg << "\n";
+return LTO_ASM_FAILURE;
+ }
tmpAsmFilePath.eraseFromDisk();
TempDir.eraseFromDisk(true);
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[llvm-commits] CVS: llvm/include/llvm/Target/TargetLowering.h
Changes in directory llvm/include/llvm/Target:
TargetLowering.h updated: 1.80 -> 1.81
---
Log message:
Merging ISD::LOAD and ISD::LOADX. Added LoadSDNode to represent load nodes.
Chain and address ptr remains as operands. SrcValue, extending mode, extending
VT (or rather loaded VT before extension) are now instance variables of
LoadSDNode.
Introduce load / store addressing modes to represent pre- and post-indexed
load and store. Also added an additional operand offset that is only used in
post-indexed mode (i.e. base ptr += offset after load/store).
Added alignment info (not yet used) and isVolatile fields.
---
Diffs of the changes: (+5 -7)
TargetLowering.h | 12 +---
1 files changed, 5 insertions(+), 7 deletions(-)
Index: llvm/include/llvm/Target/TargetLowering.h
diff -u llvm/include/llvm/Target/TargetLowering.h:1.80
llvm/include/llvm/Target/TargetLowering.h:1.81
--- llvm/include/llvm/Target/TargetLowering.h:1.80 Fri Oct 6 17:46:34 2006
+++ llvm/include/llvm/Target/TargetLowering.h Mon Oct 9 15:55:20 2006
@@ -219,14 +219,12 @@
/// expanded to some other code sequence, or the target has a custom expander
/// for it.
LegalizeAction getOperationAction(unsigned Op, MVT::ValueType VT) const {
-assert(Op != ISD::LOADX && "Should use getLoadXAction instead");
return (LegalizeAction)((OpActions[Op] >> (2*VT)) & 3);
}
/// isOperationLegal - Return true if the specified operation is legal on
this
/// target.
bool isOperationLegal(unsigned Op, MVT::ValueType VT) const {
-assert(Op != ISD::LOADX && "Should use isLoadXLegal instead");
return getOperationAction(Op, VT) == Legal ||
getOperationAction(Op, VT) == Custom;
}
@@ -545,7 +543,6 @@
/// with the specified type and indicate what to do about it.
void setOperationAction(unsigned Op, MVT::ValueType VT,
LegalizeAction Action) {
-assert(Op != ISD::LOADX && "Should use setLoadXAction instead");
assert(VT < 32 && Op < sizeof(OpActions)/sizeof(OpActions[0]) &&
"Table isn't big enough!");
OpActions[Op] &= ~(uint64_t(3UL) << VT*2);
@@ -554,11 +551,12 @@
/// setLoadXAction - Indicate that the specified load with extension does not
/// work with the with specified type and indicate what to do about it.
- void setLoadXAction(unsigned LType, MVT::ValueType VT, LegalizeAction
Action){
-assert(VT < 32 && LType < sizeof(LoadXActions)/sizeof(LoadXActions[0]) &&
+ void setLoadXAction(unsigned ExtType, MVT::ValueType VT,
+ LegalizeAction Action) {
+assert(VT < 32 && ExtType < sizeof(LoadXActions)/sizeof(LoadXActions[0]) &&
"Table isn't big enough!");
-LoadXActions[LType] &= ~(uint64_t(3UL) << VT*2);
-LoadXActions[LType] |= (uint64_t)Action << VT*2;
+LoadXActions[ExtType] &= ~(uint64_t(3UL) << VT*2);
+LoadXActions[ExtType] |= (uint64_t)Action << VT*2;
}
/// AddPromotedToType - If Opc/OrigVT is specified as being promoted, the
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[llvm-commits] CVS: llvm/lib/Target/Sparc/SparcISelDAGToDAG.cpp SparcInstrInfo.td
Changes in directory llvm/lib/Target/Sparc:
SparcISelDAGToDAG.cpp updated: 1.110 -> 1.111
SparcInstrInfo.td updated: 1.127 -> 1.128
---
Log message:
Reflects ISD::LOAD / ISD::LOADX / LoadSDNode changes.
---
Diffs of the changes: (+26 -26)
SparcISelDAGToDAG.cpp | 20 ++--
SparcInstrInfo.td | 32
2 files changed, 26 insertions(+), 26 deletions(-)
Index: llvm/lib/Target/Sparc/SparcISelDAGToDAG.cpp
diff -u llvm/lib/Target/Sparc/SparcISelDAGToDAG.cpp:1.110
llvm/lib/Target/Sparc/SparcISelDAGToDAG.cpp:1.111
--- llvm/lib/Target/Sparc/SparcISelDAGToDAG.cpp:1.110 Thu Oct 5 18:00:34 2006
+++ llvm/lib/Target/Sparc/SparcISelDAGToDAG.cpp Mon Oct 9 15:57:25 2006
@@ -330,7 +330,7 @@
SDOperand FIPtr = DAG.getFrameIndex(FrameIdx, MVT::i32);
SDOperand Load;
if (ObjectVT == MVT::i32) {
- Load = DAG.getLoad(MVT::i32, Root, FIPtr, DAG.getSrcValue(0));
+ Load = DAG.getLoad(MVT::i32, Root, FIPtr, NULL, 0);
} else {
ISD::LoadExtType LoadOp =
I->getType()->isSigned() ? ISD::SEXTLOAD : ISD::ZEXTLOAD;
@@ -340,7 +340,7 @@
FIPtr = DAG.getNode(ISD::ADD, MVT::i32, FIPtr,
DAG.getConstant(Offset, MVT::i32));
Load = DAG.getExtLoad(LoadOp, MVT::i32, Root, FIPtr,
-DAG.getSrcValue(0), ObjectVT);
+NULL, 0, ObjectVT);
Load = DAG.getNode(ISD::TRUNCATE, ObjectVT, Load);
}
ArgValues.push_back(Load);
@@ -363,7 +363,7 @@
} else {
int FrameIdx = MF.getFrameInfo()->CreateFixedObject(4, ArgOffset);
SDOperand FIPtr = DAG.getFrameIndex(FrameIdx, MVT::i32);
-SDOperand Load = DAG.getLoad(MVT::f32, Root, FIPtr,
DAG.getSrcValue(0));
+SDOperand Load = DAG.getLoad(MVT::f32, Root, FIPtr, NULL, 0);
ArgValues.push_back(Load);
}
ArgOffset += 4;
@@ -384,8 +384,7 @@
// because the double wouldn't be aligned!
int FrameIdx = MF.getFrameInfo()->CreateFixedObject(8, ArgOffset);
SDOperand FIPtr = DAG.getFrameIndex(FrameIdx, MVT::i32);
-ArgValues.push_back(DAG.getLoad(MVT::f64, Root, FIPtr,
-DAG.getSrcValue(0)));
+ArgValues.push_back(DAG.getLoad(MVT::f64, Root, FIPtr, NULL, 0));
} else {
SDOperand HiVal;
if (CurArgReg < ArgRegEnd) { // Lives in an incoming GPR
@@ -395,7 +394,7 @@
} else {
int FrameIdx = MF.getFrameInfo()->CreateFixedObject(4, ArgOffset);
SDOperand FIPtr = DAG.getFrameIndex(FrameIdx, MVT::i32);
- HiVal = DAG.getLoad(MVT::i32, Root, FIPtr, DAG.getSrcValue(0));
+ HiVal = DAG.getLoad(MVT::i32, Root, FIPtr, NULL, 0);
}
SDOperand LoVal;
@@ -406,7 +405,7 @@
} else {
int FrameIdx = MF.getFrameInfo()->CreateFixedObject(4, ArgOffset+4);
SDOperand FIPtr = DAG.getFrameIndex(FrameIdx, MVT::i32);
- LoVal = DAG.getLoad(MVT::i32, Root, FIPtr, DAG.getSrcValue(0));
+ LoVal = DAG.getLoad(MVT::i32, Root, FIPtr, NULL, 0);
}
// Compose the two halves together into an i64 unit.
@@ -794,8 +793,9 @@
MVT::ValueType VT = Node->getValueType(0);
SDOperand InChain = Node->getOperand(0);
SDOperand VAListPtr = Node->getOperand(1);
+SrcValueSDNode *SV = cast(Node->getOperand(2));
SDOperand VAList = DAG.getLoad(getPointerTy(), InChain, VAListPtr,
- Node->getOperand(2));
+ SV->getValue(), SV->getOffset());
// Increment the pointer, VAList, to the next vaarg
SDOperand NextPtr = DAG.getNode(ISD::ADD, getPointerTy(), VAList,
DAG.getConstant(MVT::getSizeInBits(VT)/8,
@@ -806,10 +806,10 @@
// Load the actual argument out of the pointer VAList, unless this is an
// f64 load.
if (VT != MVT::f64) {
- return DAG.getLoad(VT, InChain, VAList, DAG.getSrcValue(0));
+ return DAG.getLoad(VT, InChain, VAList, NULL, 0);
} else {
// Otherwise, load it as i64, then do a bitconvert.
- SDOperand V = DAG.getLoad(MVT::i64, InChain, VAList, DAG.getSrcValue(0));
+ SDOperand V = DAG.getLoad(MVT::i64, InChain, VAList, NULL, 0);
std::vector Tys;
Tys.push_back(MVT::f64);
Tys.push_back(MVT::Other);
Index: llvm/lib/Target/Sparc/SparcInstrInfo.td
diff -u llvm/lib/Target/Sparc/SparcInstrInfo.td:1.127
llvm/lib/Target/Sparc/SparcInstrInfo.td:1.128
--- llvm/lib/Target/Sparc/SparcInstrInfo.td:1.127 Fri Sep 1 17:28:02 2006
+++ llvm/lib/Target/Sparc/SparcInstrInfo.td Mon Oct 9 15:57:25 2006
@@ -278,35 +278,35 @@
def LDSBrr : F3_1<3, 0b001001,
(ops IntRegs:$dst, MEMrr:$addr),
"ldsb [$addr], $dst",
- [(set IntRegs:$dst, (sextload ADDRrr:$addr
[llvm-commits] CVS: llvm/lib/Target/PowerPC/PPCISelLowering.cpp PPCInstr64Bit.td PPCInstrInfo.td
Changes in directory llvm/lib/Target/PowerPC:
PPCISelLowering.cpp updated: 1.210 -> 1.211
PPCInstr64Bit.td updated: 1.20 -> 1.21
PPCInstrInfo.td updated: 1.243 -> 1.244
---
Log message:
Reflects ISD::LOAD / ISD::LOADX / LoadSDNode changes.
---
Diffs of the changes: (+49 -50)
PPCISelLowering.cpp | 27 +--
PPCInstr64Bit.td| 40
PPCInstrInfo.td | 32
3 files changed, 49 insertions(+), 50 deletions(-)
Index: llvm/lib/Target/PowerPC/PPCISelLowering.cpp
diff -u llvm/lib/Target/PowerPC/PPCISelLowering.cpp:1.210
llvm/lib/Target/PowerPC/PPCISelLowering.cpp:1.211
--- llvm/lib/Target/PowerPC/PPCISelLowering.cpp:1.210 Thu Oct 5 18:00:19 2006
+++ llvm/lib/Target/PowerPC/PPCISelLowering.cpp Mon Oct 9 15:57:25 2006
@@ -311,7 +311,7 @@
static bool isFloatingPointZero(SDOperand Op) {
if (ConstantFPSDNode *CFP = dyn_cast(Op))
return CFP->isExactlyValue(-0.0) || CFP->isExactlyValue(0.0);
- else if (ISD::isEXTLoad(Op.Val) || Op.getOpcode() == ISD::LOAD) {
+ else if (ISD::isEXTLoad(Op.Val) || ISD::isNON_EXTLoad(Op.Val)) {
// Maybe this has already been legalized into the constant pool?
if (ConstantPoolSDNode *CP =
dyn_cast(Op.getOperand(1)))
if (ConstantFP *CFP = dyn_cast(CP->getConstVal()))
@@ -694,7 +694,7 @@
// If the global is weak or external, we have to go through the lazy
// resolution stub.
- return DAG.getLoad(PtrVT, DAG.getEntryNode(), Lo, DAG.getSrcValue(0));
+ return DAG.getLoad(PtrVT, DAG.getEntryNode(), Lo, NULL, 0);
}
static SDOperand LowerSETCC(SDOperand Op, SelectionDAG &DAG) {
@@ -873,8 +873,7 @@
if (!Op.Val->hasNUsesOfValue(0, ArgNo)) {
int FI = MFI->CreateFixedObject(ObjSize, CurArgOffset);
SDOperand FIN = DAG.getFrameIndex(FI, PtrVT);
-ArgVal = DAG.getLoad(ObjectVT, Root, FIN,
- DAG.getSrcValue(NULL));
+ArgVal = DAG.getLoad(ObjectVT, Root, FIN, NULL, 0);
} else {
// Don't emit a dead load.
ArgVal = DAG.getNode(ISD::UNDEF, ObjectVT);
@@ -1051,16 +1050,14 @@
// Float varargs are always shadowed in available integer registers
if (GPR_idx != NumGPRs) {
-SDOperand Load = DAG.getLoad(PtrVT, Store, PtrOff,
- DAG.getSrcValue(NULL));
+SDOperand Load = DAG.getLoad(PtrVT, Store, PtrOff, NULL, 0);
MemOpChains.push_back(Load.getValue(1));
RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Load));
}
if (GPR_idx != NumGPRs && Arg.getValueType() == MVT::f64) {
SDOperand ConstFour = DAG.getConstant(4, PtrOff.getValueType());
PtrOff = DAG.getNode(ISD::ADD, PtrVT, PtrOff, ConstFour);
-SDOperand Load = DAG.getLoad(PtrVT, Store, PtrOff,
- DAG.getSrcValue(NULL));
+SDOperand Load = DAG.getLoad(PtrVT, Store, PtrOff, NULL, 0);
MemOpChains.push_back(Load.getValue(1));
RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Load));
}
@@ -1401,7 +1398,7 @@
DAG.getEntryNode(), Ext64, FIdx,
DAG.getSrcValue(NULL));
// Load the value as a double.
- SDOperand Ld = DAG.getLoad(MVT::f64, Store, FIdx, DAG.getSrcValue(NULL));
+ SDOperand Ld = DAG.getLoad(MVT::f64, Store, FIdx, NULL, 0);
// FCFID it and return it.
SDOperand FP = DAG.getNode(PPCISD::FCFID, MVT::f64, Ld);
@@ -2124,7 +2121,7 @@
SDOperand Store = DAG.getStore(DAG.getEntryNode(),
Op.getOperand(0), FIdx,DAG.getSrcValue(NULL));
// Load it out.
- return DAG.getLoad(Op.getValueType(), Store, FIdx, DAG.getSrcValue(NULL));
+ return DAG.getLoad(Op.getValueType(), Store, FIdx, NULL, 0);
}
static SDOperand LowerMUL(SDOperand Op, SelectionDAG &DAG) {
@@ -2383,18 +2380,20 @@
break;
case ISD::BSWAP:
// Turn BSWAP (LOAD) -> lhbrx/lwbrx.
-if (N->getOperand(0).getOpcode() == ISD::LOAD &&
+if (ISD::isNON_EXTLoad(N->getOperand(0).Val) &&
N->getOperand(0).hasOneUse() &&
(N->getValueType(0) == MVT::i32 || N->getValueType(0) == MVT::i16)) {
SDOperand Load = N->getOperand(0);
+ LoadSDNode *LD = cast(Load);
// Create the byte-swapping load.
std::vector VTs;
VTs.push_back(MVT::i32);
VTs.push_back(MVT::Other);
+ SDOperand SV = DAG.getSrcValue(LD->getSrcValue(),
LD->getSrcValueOffset());
SDOperand Ops[] = {
-Load.getOperand(0), // Chain
-Load.getOperand(1), // Ptr
-Load.getOperand(2), // SrcValue
+LD->getChain(),// Chain
+LD->getBasePtr(), // Ptr
+SV,// SrcValue
DAG.getValueType(N->getValueType(0)) // VT
};
SDOperand BSLoad = DAG.getNode(PPCISD::LBRX, VTs, Ops, 4);
Index: llvm
[llvm-commits] CVS: llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp
Changes in directory llvm/lib/Target/ARM:
ARMISelDAGToDAG.cpp updated: 1.60 -> 1.61
---
Log message:
Reflects ISD::LOAD / ISD::LOADX / LoadSDNode changes.
---
Diffs of the changes: (+2 -3)
ARMISelDAGToDAG.cpp |5 ++---
1 files changed, 2 insertions(+), 3 deletions(-)
Index: llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp
diff -u llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp:1.60
llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp:1.61
--- llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp:1.60Mon Oct 9 11:28:33 2006
+++ llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp Mon Oct 9 15:57:24 2006
@@ -420,8 +420,7 @@
GlobalValue *GV = cast(Op)->getGlobal();
int alignment = 2;
SDOperand CPAddr = DAG.getConstantPool(GV, MVT::i32, alignment);
- return DAG.getLoad(MVT::i32, DAG.getEntryNode(), CPAddr,
-DAG.getSrcValue(NULL));
+ return DAG.getLoad(MVT::i32, DAG.getEntryNode(), CPAddr, NULL, 0);
}
static SDOperand LowerVASTART(SDOperand Op, SelectionDAG &DAG,
@@ -479,7 +478,7 @@
unsigned Size = MVT::getSizeInBits(VT)/8;
int FI = MFI->CreateFixedObject(Size, Offset);
SDOperand FIN = DAG.getFrameIndex(FI, VT);
-Value = DAG.getLoad(VT, Root, FIN, DAG.getSrcValue(NULL));
+Value = DAG.getLoad(VT, Root, FIN, NULL, 0);
} else {
Value = DAG.getNode(ISD::UNDEF, VT);
}
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[llvm-commits] CVS: llvm/lib/Target/TargetSelectionDAG.td
Changes in directory llvm/lib/Target:
TargetSelectionDAG.td updated: 1.69 -> 1.70
---
Log message:
Reflects ISD::LOAD / ISD::LOADX / LoadSDNode changes.
---
Diffs of the changes: (+74 -16)
TargetSelectionDAG.td | 90 +-
1 files changed, 74 insertions(+), 16 deletions(-)
Index: llvm/lib/Target/TargetSelectionDAG.td
diff -u llvm/lib/Target/TargetSelectionDAG.td:1.69
llvm/lib/Target/TargetSelectionDAG.td:1.70
--- llvm/lib/Target/TargetSelectionDAG.td:1.69 Tue Oct 3 19:53:53 2006
+++ llvm/lib/Target/TargetSelectionDAG.td Mon Oct 9 15:57:24 2006
@@ -164,12 +164,6 @@
SDTCisPtrTy<1>
]>;
-def SDTLoadX : SDTypeProfile<1, 4, [ // loadX
- SDTCisPtrTy<1>, SDTCisVT<2, OtherVT>, SDTCisVT<3, OtherVT>, SDTCisVT<4, i32>
-]>;
-def SDTIntExtLoad : SDTypeProfile<1, 3, [ // extload, sextload, zextload
- SDTCisInt<0>, SDTCisPtrTy<1>, SDTCisVT<2, OtherVT>, SDTCisVT<3, OtherVT>
-]>;
def SDTTruncStore : SDTypeProfile<0, 4, [ // truncstore
SDTCisPtrTy<1>, SDTCisVT<2, OtherVT>, SDTCisVT<3, OtherVT>
]>;
@@ -305,12 +299,10 @@
def br : SDNode<"ISD::BR" , SDTBr, [SDNPHasChain]>;
def ret: SDNode<"ISD::RET", SDTRet,[SDNPHasChain]>;
-def load : SDNode<"ISD::LOAD" , SDTLoad, [SDNPHasChain]>;
+// Do not use ld directly. Use load, extload, sextload, zextload (see below).
+def ld : SDNode<"ISD::LOAD" , SDTLoad, [SDNPHasChain]>;
def store : SDNode<"ISD::STORE" , SDTStore, [SDNPHasChain]>;
-// Do not use loadx directly. Use extload, sextload and zextload (see below)
-// which pass in a dummy srcvalue node which tblgen will skip over.
-def loadx : SDNode<"ISD::LOADX" , SDTLoadX, [SDNPHasChain]>;
def truncst: SDNode<"ISD::TRUNCSTORE" , SDTTruncStore, [SDNPHasChain]>;
def vector_shuffle : SDNode<"ISD::VECTOR_SHUFFLE", SDTVecShuffle, []>;
@@ -412,13 +404,79 @@
def vnot_conv : PatFrag<(ops node:$in), (xor node:$in, immAllOnesV_bc)>;
def ineg : PatFrag<(ops node:$in), (sub 0, node:$in)>;
+def load : PatFrag<(ops node:$ptr), (ld node:$ptr), [{
+ return ISD::isNON_EXTLoad(N);
+}]>;
+
// extending load & truncstore fragments.
-def extload : PatFrag<(ops node:$ptr, node:$vt),
-(loadx node:$ptr, srcvalue:$dummy, node:$vt, 0)>;
-def sextload : PatFrag<(ops node:$ptr, node:$vt),
-(loadx node:$ptr, srcvalue:$dummy, node:$vt, 1)>;
-def zextload : PatFrag<(ops node:$ptr, node:$vt),
-(loadx node:$ptr, srcvalue:$dummy, node:$vt, 2)>;
+def extloadi1 : PatFrag<(ops node:$ptr), (ld node:$ptr), [{
+ if (ISD::isEXTLoad(N))
+return cast(N)->getLoadVT() == MVT::i1;
+ return false;
+}]>;
+def extloadi8 : PatFrag<(ops node:$ptr), (ld node:$ptr), [{
+ if (ISD::isEXTLoad(N))
+return cast(N)->getLoadVT() == MVT::i8;
+ return false;
+}]>;
+def extloadi16 : PatFrag<(ops node:$ptr), (ld node:$ptr), [{
+ if (ISD::isEXTLoad(N))
+return cast(N)->getLoadVT() == MVT::i16;
+ return false;
+}]>;
+def extloadi32 : PatFrag<(ops node:$ptr), (ld node:$ptr), [{
+ if (ISD::isEXTLoad(N))
+return cast(N)->getLoadVT() == MVT::i32;
+ return false;
+}]>;
+def extloadf32 : PatFrag<(ops node:$ptr), (ld node:$ptr), [{
+ if (ISD::isEXTLoad(N))
+return cast(N)->getLoadVT() == MVT::f32;
+ return false;
+}]>;
+
+def sextloadi1 : PatFrag<(ops node:$ptr), (ld node:$ptr), [{
+ if (ISD::isSEXTLoad(N))
+return cast(N)->getLoadVT() == MVT::i1;
+ return false;
+}]>;
+def sextloadi8 : PatFrag<(ops node:$ptr), (ld node:$ptr), [{
+ if (ISD::isSEXTLoad(N))
+return cast(N)->getLoadVT() == MVT::i8;
+ return false;
+}]>;
+def sextloadi16 : PatFrag<(ops node:$ptr), (ld node:$ptr), [{
+ if (ISD::isSEXTLoad(N))
+return cast(N)->getLoadVT() == MVT::i16;
+ return false;
+}]>;
+def sextloadi32 : PatFrag<(ops node:$ptr), (ld node:$ptr), [{
+ if (ISD::isSEXTLoad(N))
+return cast(N)->getLoadVT() == MVT::i32;
+ return false;
+}]>;
+
+def zextloadi1 : PatFrag<(ops node:$ptr), (ld node:$ptr), [{
+ if (ISD::isZEXTLoad(N))
+return cast(N)->getLoadVT() == MVT::i1;
+ return false;
+}]>;
+def zextloadi8 : PatFrag<(ops node:$ptr), (ld node:$ptr), [{
+ if (ISD::isZEXTLoad(N))
+return cast(N)->getLoadVT() == MVT::i8;
+ return false;
+}]>;
+def zextloadi16 : PatFrag<(ops node:$ptr), (ld node:$ptr), [{
+ if (ISD::isZEXTLoad(N))
+return cast(N)->getLoadVT() == MVT::i16;
+ return false;
+}]>;
+def zextloadi32 : PatFrag<(ops node:$ptr), (ld node:$ptr), [{
+ if (ISD::isZEXTLoad(N))
+return cast(N)->getLoadVT() == MVT::i32;
+ return false;
+}]>;
+
def truncstore: PatFrag<(ops node:$val, node:$ptr, node:$vt),
(truncst node:$val, node:$ptr, srcvalue:$dummy,
node:$vt)>;
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[llvm-commits] CVS: llvm/lib/Target/IA64/IA64ISelDAGToDAG.cpp IA64ISelLowering.cpp
Changes in directory llvm/lib/Target/IA64:
IA64ISelDAGToDAG.cpp updated: 1.55 -> 1.56
IA64ISelLowering.cpp updated: 1.45 -> 1.46
---
Log message:
Reflects ISD::LOAD / ISD::LOADX / LoadSDNode changes.
---
Diffs of the changes: (+10 -10)
IA64ISelDAGToDAG.cpp | 11 +--
IA64ISelLowering.cpp |9 +
2 files changed, 10 insertions(+), 10 deletions(-)
Index: llvm/lib/Target/IA64/IA64ISelDAGToDAG.cpp
diff -u llvm/lib/Target/IA64/IA64ISelDAGToDAG.cpp:1.55
llvm/lib/Target/IA64/IA64ISelDAGToDAG.cpp:1.56
--- llvm/lib/Target/IA64/IA64ISelDAGToDAG.cpp:1.55 Tue Oct 3 19:55:13 2006
+++ llvm/lib/Target/IA64/IA64ISelDAGToDAG.cpp Mon Oct 9 15:57:24 2006
@@ -453,15 +453,14 @@
}
*/
- case ISD::LOAD:
- case ISD::LOADX: { // FIXME: load -1, not 1, for bools?
-SDOperand Chain = N->getOperand(0);
-SDOperand Address = N->getOperand(1);
+ case ISD::LOAD: { // FIXME: load -1, not 1, for bools?
+LoadSDNode *LD = cast(N);
+SDOperand Chain = LD->getChain();
+SDOperand Address = LD->getBasePtr();
AddToISelQueue(Chain);
AddToISelQueue(Address);
-MVT::ValueType TypeBeingLoaded = (N->getOpcode() == ISD::LOAD) ?
- N->getValueType(0) : cast(N->getOperand(3))->getVT();
+MVT::ValueType TypeBeingLoaded = LD->getLoadVT();
unsigned Opc;
switch (TypeBeingLoaded) {
default:
Index: llvm/lib/Target/IA64/IA64ISelLowering.cpp
diff -u llvm/lib/Target/IA64/IA64ISelLowering.cpp:1.45
llvm/lib/Target/IA64/IA64ISelLowering.cpp:1.46
--- llvm/lib/Target/IA64/IA64ISelLowering.cpp:1.45 Thu Oct 5 18:00:04 2006
+++ llvm/lib/Target/IA64/IA64ISelLowering.cpp Mon Oct 9 15:57:25 2006
@@ -133,7 +133,7 @@
static bool isFloatingPointZero(SDOperand Op) {
if (ConstantFPSDNode *CFP = dyn_cast(Op))
return CFP->isExactlyValue(-0.0) || CFP->isExactlyValue(0.0);
- else if (Op.getOpcode() == ISD::EXTLOAD || Op.getOpcode() == ISD::LOAD) {
+ else if (ISD::isEXTLoad(Op.Val) || ISD::isNON_EXTLoad(Op.Val)) {
// Maybe this has already been legalized into the constant pool?
if (ConstantPoolSDNode *CP =
dyn_cast(Op.getOperand(1)))
if (ConstantFP *CFP = dyn_cast(CP->getConstVal()))
@@ -226,7 +226,7 @@
//from this parameter
SDOperand FIN = DAG.getFrameIndex(FI, MVT::i64);
argt = newroot = DAG.getLoad(getValueType(I->getType()),
- DAG.getEntryNode(), FIN,
DAG.getSrcValue(NULL));
+ DAG.getEntryNode(), FIN, NULL, 0);
}
++count;
DAG.setRoot(newroot.getValue(1));
@@ -583,8 +583,9 @@
}
case ISD::VAARG: {
MVT::ValueType VT = getPointerTy();
+SrcValueSDNode *SV = cast(Op.getOperand(2));
SDOperand VAList = DAG.getLoad(VT, Op.getOperand(0), Op.getOperand(1),
- Op.getOperand(2));
+ SV->getValue(), SV->getOffset());
// Increment the pointer, VAList, to the next vaarg
SDOperand VAIncr = DAG.getNode(ISD::ADD, VT, VAList,
DAG.getConstant(MVT::getSizeInBits(VT)/8,
@@ -593,7 +594,7 @@
VAIncr = DAG.getStore(VAList.getValue(1), VAIncr,
Op.getOperand(1), Op.getOperand(2));
// Load the actual argument out of the pointer VAList
-return DAG.getLoad(Op.getValueType(), VAIncr, VAList, DAG.getSrcValue(0));
+return DAG.getLoad(Op.getValueType(), VAIncr, VAList, NULL, 0);
}
case ISD::VASTART: {
// vastart just stores the address of the VarArgsFrameIndex slot into the
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[llvm-commits] CVS: llvm/include/llvm/CodeGen/SelectionDAG.h SelectionDAGNodes.h
Changes in directory llvm/include/llvm/CodeGen: SelectionDAG.h updated: 1.133 -> 1.134 SelectionDAGNodes.h updated: 1.149 -> 1.150 --- Log message: Merging ISD::LOAD and ISD::LOADX. Added LoadSDNode to represent load nodes. Chain and address ptr remains as operands. SrcValue, extending mode, extending VT (or rather loaded VT before extension) are now instance variables of LoadSDNode. Introduce load / store addressing modes to represent pre- and post-indexed load and store. Also added an additional operand offset that is only used in post-indexed mode (i.e. base ptr += offset after load/store). Added alignment info (not yet used) and isVolatile fields. --- Diffs of the changes: (+148 -25) SelectionDAG.h |8 +- SelectionDAGNodes.h | 165 +--- 2 files changed, 148 insertions(+), 25 deletions(-) Index: llvm/include/llvm/CodeGen/SelectionDAG.h diff -u llvm/include/llvm/CodeGen/SelectionDAG.h:1.133 llvm/include/llvm/CodeGen/SelectionDAG.h:1.134 --- llvm/include/llvm/CodeGen/SelectionDAG.h:1.133 Thu Oct 5 17:54:31 2006 +++ llvm/include/llvm/CodeGen/SelectionDAG.hMon Oct 9 15:55:20 2006 @@ -300,12 +300,12 @@ /// determined by their operands, and they produce a value AND a token chain. /// SDOperand getLoad(MVT::ValueType VT, SDOperand Chain, SDOperand Ptr, -SDOperand SV); +const Value *SV, int SVOffset, bool isVolatile=false); + SDOperand getExtLoad(ISD::LoadExtType ExtType, MVT::ValueType VT, + SDOperand Chain, SDOperand Ptr, const Value *SV, + int SVOffset, MVT::ValueType EVT, bool isVolatile=false); SDOperand getVecLoad(unsigned Count, MVT::ValueType VT, SDOperand Chain, SDOperand Ptr, SDOperand SV); - SDOperand getExtLoad(ISD::LoadExtType LType, MVT::ValueType VT, - SDOperand Chain, SDOperand Ptr, SDOperand SV, - MVT::ValueType EVT); /// getStore - Helper function to build ISD::STORE nodes. /// Index: llvm/include/llvm/CodeGen/SelectionDAGNodes.h diff -u llvm/include/llvm/CodeGen/SelectionDAGNodes.h:1.149 llvm/include/llvm/CodeGen/SelectionDAGNodes.h:1.150 --- llvm/include/llvm/CodeGen/SelectionDAGNodes.h:1.149 Tue Oct 3 19:50:21 2006 +++ llvm/include/llvm/CodeGen/SelectionDAGNodes.h Mon Oct 9 15:55:20 2006 @@ -380,21 +380,6 @@ // the elements, a token chain, a pointer operand, and a SRCVALUE node. VLOAD, -// Load a value from memory and extend them to a larger value (e.g. load a -// byte into a word register). All three of these have four operands, a -// token chain, a pointer to load from, a SRCVALUE for alias analysis, a -// VALUETYPE node indicating the type to load, and an enum indicating what -// sub-type of LOADX it is: -// -// SEXTLOAD loads the integer operand and sign extends it to a larger -// integer result type. -// ZEXTLOAD loads the integer operand and zero extends it to a larger -// integer result type. -// EXTLOAD is used for three things: floating point extending loads, -// integer extending loads [the top bits are undefined], and vector -// extending loads [load into low elt]. -LOADX, - // TRUNCSTORE - This operators truncates (for integer) or rounds (for FP) a // value and stores it to memory in one operation. This can be used for // either integer or floating point operands. The first four operands of @@ -534,10 +519,52 @@ bool isBuildVectorAllZeros(const SDNode *N); //======// + /// MemOpAddrMode enum - This enum defines the three load / store addressing + /// modes. + /// + /// UNINDEXED"Normal" load / store. The effective address is already + /// computed and is available in the base pointer. The offset + /// operand is always undefined. An unindexed load produces one + /// value (result of the load); an unindexed store does not + /// produces a value. + /// + /// PRE_INDEXED Similar to the unindexed mode where the effective address is + /// the result of computation of the base pointer. However, it + /// considers the computation as being folded into the load / + /// store operation (i.e. the load / store does the address + /// computation as well as performing the memory transaction). + /// The base operand is always undefined. A pre-indexed load + /// produces two values (result of the load and the result of + /// the address computation); a pre-indexed store produces one + /// value (result of the address computation). + /// + /// POST_INDEXED The effective address is the value of the base pointer. The + /// value of the offse
[llvm-commits] CVS: llvm/utils/TableGen/DAGISelEmitter.cpp
Changes in directory llvm/utils/TableGen:
DAGISelEmitter.cpp updated: 1.263 -> 1.264
---
Log message:
Predicate function on the node should be matched before its childrean' matching
code. This is especially important now matching ISD::LOAD also requires a
Predicate_Load call.
---
Diffs of the changes: (+4 -4)
DAGISelEmitter.cpp |8
1 files changed, 4 insertions(+), 4 deletions(-)
Index: llvm/utils/TableGen/DAGISelEmitter.cpp
diff -u llvm/utils/TableGen/DAGISelEmitter.cpp:1.263
llvm/utils/TableGen/DAGISelEmitter.cpp:1.264
--- llvm/utils/TableGen/DAGISelEmitter.cpp:1.263Thu Sep 21 15:46:13 2006
+++ llvm/utils/TableGen/DAGISelEmitter.cpp Mon Oct 9 16:02:17 2006
@@ -2312,6 +2312,10 @@
}
}
+// If there is a node predicate for this, emit the call.
+if (!N->getPredicateFn().empty())
+ emitCheck(N->getPredicateFn() + "(" + RootName + ".Val)");
+
const ComplexPattern *CP;
for (unsigned i = 0, e = N->getNumChildren(); i != e; ++i, ++OpNo) {
emitInit("SDOperand " + RootName + utostr(OpNo) + " = " +
@@ -2420,10 +2424,6 @@
Code += ", CPTmp" + utostr(i);
emitCheck(Code + ")");
}
-
-// If there is a node predicate for this, emit the call.
-if (!N->getPredicateFn().empty())
- emitCheck(N->getPredicateFn() + "(" + RootName + ".Val)");
}
/// EmitResultCode - Emit the action for a pattern. Now that it has matched
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[llvm-commits] CVS: llvm/lib/Target/Alpha/AlphaISelLowering.cpp AlphaInstrInfo.td
Changes in directory llvm/lib/Target/Alpha:
AlphaISelLowering.cpp updated: 1.65 -> 1.66
AlphaInstrInfo.td updated: 1.125 -> 1.126
---
Log message:
Reflects ISD::LOAD / ISD::LOADX / LoadSDNode changes.
---
Diffs of the changes: (+31 -31)
AlphaISelLowering.cpp | 26 +-
AlphaInstrInfo.td | 36 ++--
2 files changed, 31 insertions(+), 31 deletions(-)
Index: llvm/lib/Target/Alpha/AlphaISelLowering.cpp
diff -u llvm/lib/Target/Alpha/AlphaISelLowering.cpp:1.65
llvm/lib/Target/Alpha/AlphaISelLowering.cpp:1.66
--- llvm/lib/Target/Alpha/AlphaISelLowering.cpp:1.65Fri Oct 6 17:46:51 2006
+++ llvm/lib/Target/Alpha/AlphaISelLowering.cpp Mon Oct 9 15:57:24 2006
@@ -254,7 +254,7 @@
// Create the SelectionDAG nodes corresponding to a load
//from this parameter
SDOperand FIN = DAG.getFrameIndex(FI, MVT::i64);
- ArgVal = DAG.getLoad(ObjectVT, Root, FIN, DAG.getSrcValue(NULL));
+ ArgVal = DAG.getLoad(ObjectVT, Root, FIN, NULL, 0);
}
ArgValues.push_back(ArgVal);
}
@@ -430,7 +430,7 @@
SDOperand FI = DAG.getFrameIndex(FrameIdx, MVT::i64);
SDOperand ST = DAG.getStore(DAG.getEntryNode(),
Op.getOperand(0), FI, DAG.getSrcValue(0));
- LD = DAG.getLoad(MVT::f64, ST, FI, DAG.getSrcValue(0));
+ LD = DAG.getLoad(MVT::f64, ST, FI, NULL, 0);
}
SDOperand FP = DAG.getNode(isDouble?AlphaISD::CVTQT_:AlphaISD::CVTQS_,
isDouble?MVT::f64:MVT::f32, LD);
@@ -453,7 +453,7 @@
SDOperand FI = DAG.getFrameIndex(FrameIdx, MVT::i64);
SDOperand ST = DAG.getStore(DAG.getEntryNode(),
src, FI, DAG.getSrcValue(0));
- return DAG.getLoad(MVT::i64, ST, FI, DAG.getSrcValue(0));
+ return DAG.getLoad(MVT::i64, ST, FI, NULL, 0);
}
}
case ISD::ConstantPool: {
@@ -523,13 +523,14 @@
case ISD::VAARG: {
SDOperand Chain = Op.getOperand(0);
SDOperand VAListP = Op.getOperand(1);
-SDOperand VAListS = Op.getOperand(2);
+SrcValueSDNode *VAListS = cast(Op.getOperand(2));
-SDOperand Base = DAG.getLoad(MVT::i64, Chain, VAListP, VAListS);
+SDOperand Base = DAG.getLoad(MVT::i64, Chain, VAListP, VAListS->getValue(),
+ VAListS->getOffset());
SDOperand Tmp = DAG.getNode(ISD::ADD, MVT::i64, VAListP,
DAG.getConstant(8, MVT::i64));
SDOperand Offset = DAG.getExtLoad(ISD::SEXTLOAD, MVT::i64,
Base.getValue(1),
- Tmp, DAG.getSrcValue(0), MVT::i32);
+ Tmp, NULL, 0, MVT::i32);
SDOperand DataPtr = DAG.getNode(ISD::ADD, MVT::i64, Base, Offset);
if (MVT::isFloatingPoint(Op.getValueType()))
{
@@ -551,10 +552,9 @@
SDOperand Result;
if (Op.getValueType() == MVT::i32)
Result = DAG.getExtLoad(ISD::SEXTLOAD, MVT::i64, Update, DataPtr,
- DAG.getSrcValue(0), MVT::i32);
+ NULL, 0, MVT::i32);
else
- Result = DAG.getLoad(Op.getValueType(), Update, DataPtr,
- DAG.getSrcValue(0));
+ Result = DAG.getLoad(Op.getValueType(), Update, DataPtr, NULL, 0);
return Result;
}
case ISD::VACOPY: {
@@ -562,14 +562,14 @@
SDOperand DestP = Op.getOperand(1);
SDOperand SrcP = Op.getOperand(2);
SDOperand DestS = Op.getOperand(3);
-SDOperand SrcS = Op.getOperand(4);
+SrcValueSDNode *SrcS = cast(Op.getOperand(4));
-SDOperand Val = DAG.getLoad(getPointerTy(), Chain, SrcP, SrcS);
+SDOperand Val = DAG.getLoad(getPointerTy(), Chain, SrcP,
+SrcS->getValue(), SrcS->getOffset());
SDOperand Result = DAG.getStore(Val.getValue(1), Val, DestP, DestS);
SDOperand NP = DAG.getNode(ISD::ADD, MVT::i64, SrcP,
DAG.getConstant(8, MVT::i64));
-Val = DAG.getExtLoad(ISD::SEXTLOAD, MVT::i64, Result, NP,
- DAG.getSrcValue(0), MVT::i32);
+Val = DAG.getExtLoad(ISD::SEXTLOAD, MVT::i64, Result, NP, NULL,0,
MVT::i32);
SDOperand NPD = DAG.getNode(ISD::ADD, MVT::i64, DestP,
DAG.getConstant(8, MVT::i64));
return DAG.getNode(ISD::TRUNCSTORE, MVT::Other, Val.getValue(1),
Index: llvm/lib/Target/Alpha/AlphaInstrInfo.td
diff -u llvm/lib/Target/Alpha/AlphaInstrInfo.td:1.125
llvm/lib/Target/Alpha/AlphaInstrInfo.td:1.126
--- llvm/lib/Target/Alpha/AlphaInstrInfo.td:1.125 Wed Sep 20 10:05:49 2006
+++ llvm/lib/Target/Alpha/AlphaInstrInfo.td Mon Oct 9 15:57:24 2006
@@ -484,17 +484,17 @@
def LDQr : MForm<0x29, 0, 1, "ldq $RA,$DISP($RB)\t\t!gprellow",
[(set GPRC:$RA, (load (Alpha_gprello tglobaladdr:$DISP,
GPRC:$RB)))], s_ild>;
def LDL : MForm<0x28, 0, 1, "ldl $RA,$DISP($RB)",
- [(set GPRC:$RA, (sextload (add GPRC:$RB, immS
[llvm-commits] CVS: llvm/lib/Target/X86/X86ISelDAGToDAG.cpp X86ISelLowering.cpp X86InstrFPStack.td X86InstrInfo.td X86InstrSSE.td X86InstrX86-64.td
Changes in directory llvm/lib/Target/X86:
X86ISelDAGToDAG.cpp updated: 1.111 -> 1.112
X86ISelLowering.cpp updated: 1.271 -> 1.272
X86InstrFPStack.td updated: 1.6 -> 1.7
X86InstrInfo.td updated: 1.287 -> 1.288
X86InstrSSE.td updated: 1.162 -> 1.163
X86InstrX86-64.td updated: 1.3 -> 1.4
---
Log message:
Reflects ISD::LOAD / ISD::LOADX / LoadSDNode changes.
---
Diffs of the changes: (+72 -83)
X86ISelDAGToDAG.cpp |8 ++---
X86ISelLowering.cpp | 77 ++--
X86InstrFPStack.td |2 -
X86InstrInfo.td | 38 -
X86InstrSSE.td |2 -
X86InstrX86-64.td | 28 +-
6 files changed, 72 insertions(+), 83 deletions(-)
Index: llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
diff -u llvm/lib/Target/X86/X86ISelDAGToDAG.cpp:1.111
llvm/lib/Target/X86/X86ISelDAGToDAG.cpp:1.112
--- llvm/lib/Target/X86/X86ISelDAGToDAG.cpp:1.111 Sat Oct 7 16:55:32 2006
+++ llvm/lib/Target/X86/X86ISelDAGToDAG.cpp Mon Oct 9 15:57:25 2006
@@ -346,9 +346,9 @@
case ISD::ADDE: {
SDOperand N10 = N1.getOperand(0);
SDOperand N11 = N1.getOperand(1);
-if (N10.Val->getOpcode() == ISD::LOAD)
+if (ISD::isNON_EXTLoad(N10.Val))
RModW = true;
-else if (N11.Val->getOpcode() == ISD::LOAD) {
+else if (ISD::isNON_EXTLoad(N11.Val)) {
RModW = true;
std::swap(N10, N11);
}
@@ -370,7 +370,7 @@
case X86ISD::SHLD:
case X86ISD::SHRD: {
SDOperand N10 = N1.getOperand(0);
-if (N10.Val->getOpcode() == ISD::LOAD)
+if (ISD::isNON_EXTLoad(N10.Val))
RModW = N10.Val->isOperand(Chain.Val) && N10.hasOneUse() &&
(N10.getOperand(1) == N2) &&
(N10.Val->getValueType(0) == N1.getValueType());
@@ -806,7 +806,7 @@
bool X86DAGToDAGISel::TryFoldLoad(SDOperand P, SDOperand N,
SDOperand &Base, SDOperand &Scale,
SDOperand &Index, SDOperand &Disp) {
- if (N.getOpcode() == ISD::LOAD &&
+ if (ISD::isNON_EXTLoad(N.Val) &&
N.hasOneUse() &&
CanBeFoldedBy(N.Val, P.Val))
return SelectAddr(N.getOperand(1), Base, Scale, Index, Disp);
Index: llvm/lib/Target/X86/X86ISelLowering.cpp
diff -u llvm/lib/Target/X86/X86ISelLowering.cpp:1.271
llvm/lib/Target/X86/X86ISelLowering.cpp:1.272
--- llvm/lib/Target/X86/X86ISelLowering.cpp:1.271 Thu Oct 5 18:01:46 2006
+++ llvm/lib/Target/X86/X86ISelLowering.cpp Mon Oct 9 15:57:25 2006
@@ -490,8 +490,7 @@
// Create the frame index object for this incoming parameter...
int FI = MFI->CreateFixedObject(ObjSize, ArgOffset);
SDOperand FIN = DAG.getFrameIndex(FI, getPointerTy());
- ArgValue = DAG.getLoad(Op.Val->getValueType(i), Root, FIN,
- DAG.getSrcValue(NULL));
+ ArgValue = DAG.getLoad(Op.Val->getValueType(i), Root, FIN, NULL, 0);
ArgValues.push_back(ArgValue);
ArgOffset += ArgIncrement; // Move on to the next argument...
}
@@ -763,8 +762,7 @@
Ops.push_back(DAG.getValueType(RetVT));
Ops.push_back(InFlag);
Chain = DAG.getNode(X86ISD::FST, Tys, &Ops[0], Ops.size());
- RetVal = DAG.getLoad(RetVT, Chain, StackSlot,
- DAG.getSrcValue(NULL));
+ RetVal = DAG.getLoad(RetVT, Chain, StackSlot, NULL, 0);
Chain = RetVal.getValue(1);
}
@@ -963,8 +961,7 @@
// parameter.
int FI = MFI->CreateFixedObject(ObjSize, ArgOffset);
SDOperand FIN = DAG.getFrameIndex(FI, getPointerTy());
- ArgValue = DAG.getLoad(Op.Val->getValueType(i), Root, FIN,
- DAG.getSrcValue(NULL));
+ ArgValue = DAG.getLoad(Op.Val->getValueType(i), Root, FIN, NULL, 0);
ArgOffset += ArgIncrement; // Move on to the next argument.
}
@@ -1470,11 +1467,10 @@
SDOperand FIN = DAG.getFrameIndex(FI, getPointerTy());
if (ObjectVT == MVT::i64 && ObjIntRegs) {
SDOperand ArgValue2 = DAG.getLoad(Op.Val->getValueType(i), Root, FIN,
- DAG.getSrcValue(NULL));
+ NULL, 0);
ArgValue = DAG.getNode(ISD::BUILD_PAIR, MVT::i64, ArgValue, ArgValue2);
} else
-ArgValue = DAG.getLoad(Op.Val->getValueType(i), Root, FIN,
- DAG.getSrcValue(NULL));
+ArgValue = DAG.getLoad(Op.Val->getValueType(i), Root, FIN, NULL, 0);
ArgOffset += ArgIncrement; // Move on to the next argument.
}
@@ -1800,8 +1796,7 @@
Ops.push_back(DAG.getValueType(RetVT));
Ops.push_back(InFlag);
Chain = DAG.getNode(X86ISD::FST, Tys, &Ops[0], Ops.size());
- RetVal = DAG.getLoad(RetVT, Chain, StackSlot,
- DAG.getSrcValue(NULL));
+ RetVal = DAG.getLoad(RetVT, Chain, StackSlot, NULL, 0);
Chain = RetVal.getValue(1);
}
@@ -1880,8 +18
[llvm-commits] CVS: llvm/tools/lto/lto.cpp
Changes in directory llvm/tools/lto:
lto.cpp updated: 1.19 -> 1.20
---
Log message:
Use FindProgramByName instead of FindExecutable.
---
Diffs of the changes: (+1 -1)
lto.cpp |2 +-
1 files changed, 1 insertion(+), 1 deletion(-)
Index: llvm/tools/lto/lto.cpp
diff -u llvm/tools/lto/lto.cpp:1.19 llvm/tools/lto/lto.cpp:1.20
--- llvm/tools/lto/lto.cpp:1.19 Mon Oct 9 15:20:13 2006
+++ llvm/tools/lto/lto.cpp Mon Oct 9 16:16:05 2006
@@ -386,7 +386,7 @@
// We can't just assemble and link the file with the system assembler
// and linker because we don't know where to put the _start symbol.
// GCC mysteriously knows how to do it.
- const sys::Path gcc = FindExecutable("gcc", "/");
+ const sys::Path gcc = sys::Program::FindProgramByName("gcc");
if (gcc.isEmpty()) {
tmpAsmFilePath.eraseFromDisk();
TempDir.eraseFromDisk(true);
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[llvm-commits] CVS: llvm/lib/Target/X86/X86ISelLowering.cpp
Changes in directory llvm/lib/Target/X86:
X86ISelLowering.cpp updated: 1.272 -> 1.273
---
Log message:
Don't convert to MOVLP if using shufps etc. may allow load folding.
---
Diffs of the changes: (+6 -2)
X86ISelLowering.cpp |8 ++--
1 files changed, 6 insertions(+), 2 deletions(-)
Index: llvm/lib/Target/X86/X86ISelLowering.cpp
diff -u llvm/lib/Target/X86/X86ISelLowering.cpp:1.272
llvm/lib/Target/X86/X86ISelLowering.cpp:1.273
--- llvm/lib/Target/X86/X86ISelLowering.cpp:1.272 Mon Oct 9 15:57:25 2006
+++ llvm/lib/Target/X86/X86ISelLowering.cpp Mon Oct 9 16:39:25 2006
@@ -3053,9 +3053,13 @@
/// V1 (and in order), and the upper half elements should come from the upper
/// half of V2 (and in order). And since V1 will become the source of the
/// MOVLP, it must be either a vector load or a scalar load to vector.
-static bool ShouldXformToMOVLP(SDNode *V1, SDNode *Mask) {
+static bool ShouldXformToMOVLP(SDNode *V1, SDNode *V2, SDNode *Mask) {
if (!ISD::isNON_EXTLoad(V1) && !isScalarLoadToVector(V1))
return false;
+ // Is V2 is a vector load, don't do this transformation. We will try to use
+ // load folding shufps op.
+ if (ISD::isNON_EXTLoad(V2))
+return false;
unsigned NumElems = Mask->getNumOperands();
if (NumElems != 2 && NumElems != 4)
@@ -3497,7 +3501,7 @@
return Op;
if (ShouldXformToMOVHLPS(PermMask.Val) ||
-ShouldXformToMOVLP(V1.Val, PermMask.Val))
+ShouldXformToMOVLP(V1.Val, V2.Val, PermMask.Val))
return CommuteVectorShuffle(Op, DAG);
bool V1IsSplat = isSplatVector(V1.Val);
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[llvm-commits] CVS: llvm/lib/Target/X86/X86InstrSSE.td
Changes in directory llvm/lib/Target/X86:
X86InstrSSE.td updated: 1.163 -> 1.164
---
Log message:
Don't go too crazy with these AddComplexity. Try matching shufps with load
folding first.
---
Diffs of the changes: (+19 -8)
X86InstrSSE.td | 27 +++
1 files changed, 19 insertions(+), 8 deletions(-)
Index: llvm/lib/Target/X86/X86InstrSSE.td
diff -u llvm/lib/Target/X86/X86InstrSSE.td:1.163
llvm/lib/Target/X86/X86InstrSSE.td:1.164
--- llvm/lib/Target/X86/X86InstrSSE.td:1.163Mon Oct 9 15:57:25 2006
+++ llvm/lib/Target/X86/X86InstrSSE.td Mon Oct 9 16:42:15 2006
@@ -769,7 +769,7 @@
addr:$dst)]>;
let isTwoAddress = 1 in {
-let AddedComplexity = 20 in {
+let AddedComplexity = 15 in {
def MOVLHPSrr : PSI<0x16, MRMSrcReg, (ops VR128:$dst, VR128:$src1,
VR128:$src2),
"movlhps {$src2, $dst|$dst, $src2}",
[(set VR128:$dst,
@@ -1753,7 +1753,7 @@
def MOVLSD2PDrr : SDI<0x10, MRMSrcReg, (ops VR128:$dst, VR128:$src1,
FR64:$src2),
"movsd {$src2, $dst|$dst, $src2}", []>;
-let AddedComplexity = 20 in {
+let AddedComplexity = 15 in {
def MOVLPSrr : SSI<0x10, MRMSrcReg, (ops VR128:$dst, VR128:$src1, VR128:$src2),
"movss {$src2, $dst|$dst, $src2}",
[(set VR128:$dst,
@@ -1785,28 +1785,32 @@
[(set VR128:$dst, (v2f64 (vector_shuffle immAllZerosV,
(v2f64 (scalar_to_vector (loadf64
addr:$src))),
MOVL_shuffle_mask)))]>;
+}
+let AddedComplexity = 15 in
// movd / movq to XMM register zero-extends
def MOVZDI2PDIrr : PDI<0x6E, MRMSrcReg, (ops VR128:$dst, GR32:$src),
"movd {$src, $dst|$dst, $src}",
[(set VR128:$dst, (v4i32 (vector_shuffle immAllZerosV,
(v4i32 (scalar_to_vector
GR32:$src)),
MOVL_shuffle_mask)))]>;
+let AddedComplexity = 20 in
def MOVZDI2PDIrm : PDI<0x6E, MRMSrcMem, (ops VR128:$dst, i32mem:$src),
"movd {$src, $dst|$dst, $src}",
[(set VR128:$dst, (v4i32 (vector_shuffle immAllZerosV,
(v4i32 (scalar_to_vector (loadi32
addr:$src))),
MOVL_shuffle_mask)))]>;
// Moving from XMM to XMM but still clear upper 64 bits.
+let AddedComplexity = 15 in
def MOVZQI2PQIrr : I<0x7E, MRMSrcReg, (ops VR128:$dst, VR128:$src),
"movq {$src, $dst|$dst, $src}",
[(set VR128:$dst, (int_x86_sse2_movl_dq VR128:$src))]>,
XS, Requires<[HasSSE2]>;
+let AddedComplexity = 20 in
def MOVZQI2PQIrm : I<0x7E, MRMSrcMem, (ops VR128:$dst, i64mem:$src),
"movq {$src, $dst|$dst, $src}",
[(set VR128:$dst, (int_x86_sse2_movl_dq
(bitconvert (loadv2i64 addr:$src]>,
XS, Requires<[HasSSE2]>;
-}
//===--===//
// Non-Instruction Patterns
@@ -1884,7 +1888,7 @@
// Move scalar to XMM zero-extended
// movd to XMM register zero-extends
-let AddedComplexity = 20 in {
+let AddedComplexity = 15 in {
def : Pat<(v8i16 (vector_shuffle immAllZerosV,
(v8i16 (X86s2vec GR32:$src)), MOVL_shuffle_mask)),
(MOVZDI2PDIrr GR32:$src)>, Requires<[HasSSE2]>;
@@ -1950,25 +1954,27 @@
(PUNPCKLDQrr VR128:$src, VR128:$src)>, Requires<[HasSSE1]>;
}
-let AddedComplexity = 20 in {
+let AddedComplexity = 15 in
// vector_shuffle v1, <1, 1, 3, 3>
def : Pat<(v4i32 (vector_shuffle VR128:$src, (undef),
MOVSHDUP_shuffle_mask)),
(MOVSHDUPrr VR128:$src)>, Requires<[HasSSE3]>;
+let AddedComplexity = 20 in
def : Pat<(v4i32 (vector_shuffle (bc_v4i32 (loadv2i64 addr:$src)), (undef),
MOVSHDUP_shuffle_mask)),
(MOVSHDUPrm addr:$src)>, Requires<[HasSSE3]>;
// vector_shuffle v1, <0, 0, 2, 2>
+let AddedComplexity = 15 in
def : Pat<(v4i32 (vector_shuffle VR128:$src, (undef),
MOVSLDUP_shuffle_mask)),
(MOVSLDUPrr VR128:$src)>, Requires<[HasSSE3]>;
+let AddedComplexity = 20 in
def : Pat<(v4i32 (vector_shuffle (bc_v4i32 (loadv2i64 addr:$src)), (undef),
MOVSLDUP_shuffle_mask)),
(MOVSLDUPrm addr:$src)>, Requires<[HasSSE3]>;
-}
-let AddedComplexity = 20 in {
+let AddedComplexity = 15 in {
// vector_shuffle v1, v2 <0, 1, 4, 5> using MOVLHPS
def : Pat<(v4i32 (vector_shuffle VR128:$src1, VR128:$src2,
MOVHP_shuffle_mask)),
@@ -1986,7 +1992,9 @@
def : Pat<(v4i32 (vector_shuffle VR128:$src1, (undef),
UNPCKH_shuffle_mask)),
(MOVHLPSrr VR128:$src1, VR128:$src1)>;
+}
+ let AddedComplexity = 20 in {
// vector_shuffle v1,
[llvm-commits] CVS: llvm/test/Regression/CodeGen/X86/vec_shuffle-5.ll
Changes in directory llvm/test/Regression/CodeGen/X86:
vec_shuffle-5.ll updated: 1.1 -> 1.2
---
Log message:
shufps with load folding is better than movaps; movsd.
---
Diffs of the changes: (+2 -1)
vec_shuffle-5.ll |3 ++-
1 files changed, 2 insertions(+), 1 deletion(-)
Index: llvm/test/Regression/CodeGen/X86/vec_shuffle-5.ll
diff -u llvm/test/Regression/CodeGen/X86/vec_shuffle-5.ll:1.1
llvm/test/Regression/CodeGen/X86/vec_shuffle-5.ll:1.2
--- llvm/test/Regression/CodeGen/X86/vec_shuffle-5.ll:1.1 Wed May 3
15:29:34 2006
+++ llvm/test/Regression/CodeGen/X86/vec_shuffle-5.ll Mon Oct 9 17:42:31 2006
@@ -1,4 +1,5 @@
-; RUN: llvm-as < %s | llc -march=x86 -mattr=+sse2 | grep movsd | wc -l | grep 1
+; RUN: llvm-as < %s | llc -march=x86 -mattr=+sse2 | grep movhlps | wc -l |
grep 1 &&
+; RUN: llvm-as < %s | llc -march=x86 -mattr=+sse2 | grep shufps | wc -l |
grep 1
void %test() {
%tmp1 = load <4 x float>* null
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[llvm-commits] CVS: llvm/include/llvm/CodeGen/SelectionDAGNodes.h
Changes in directory llvm/include/llvm/CodeGen:
SelectionDAGNodes.h updated: 1.150 -> 1.151
---
Log message:
Comments; getChain(), getBasePtr(), etc. should return a SDOperand by value.
---
Diffs of the changes: (+51 -23)
SelectionDAGNodes.h | 74 +++-
1 files changed, 51 insertions(+), 23 deletions(-)
Index: llvm/include/llvm/CodeGen/SelectionDAGNodes.h
diff -u llvm/include/llvm/CodeGen/SelectionDAGNodes.h:1.150
llvm/include/llvm/CodeGen/SelectionDAGNodes.h:1.151
--- llvm/include/llvm/CodeGen/SelectionDAGNodes.h:1.150 Mon Oct 9 15:55:20 2006
+++ llvm/include/llvm/CodeGen/SelectionDAGNodes.h Mon Oct 9 20:44:58 2006
@@ -524,26 +524,28 @@
///
/// UNINDEXED"Normal" load / store. The effective address is already
/// computed and is available in the base pointer. The offset
- /// operand is always undefined. An unindexed load produces one
- /// value (result of the load); an unindexed store does not
- /// produces a value.
+ /// operand is always undefined. In addition to producing a
+ /// chain, an unindexed load produces one value (result of the
+ /// load); an unindexed store does not produces a value.
///
/// PRE_INDEXED Similar to the unindexed mode where the effective address is
/// the result of computation of the base pointer. However, it
/// considers the computation as being folded into the load /
/// store operation (i.e. the load / store does the address
/// computation as well as performing the memory transaction).
- /// The base operand is always undefined. A pre-indexed load
- /// produces two values (result of the load and the result of
- /// the address computation); a pre-indexed store produces one
- /// value (result of the address computation).
+ /// The base operand is always undefined. In addition to
+ /// producing a chain, pre-indexed load produces two values
+ /// (result of the load and the result of the address
+ /// computation); a pre-indexed store produces one value (result
+ /// of the address computation).
///
/// POST_INDEXED The effective address is the value of the base pointer. The
/// value of the offset operand is then added to the base after
- /// memory transaction. A post-indexed load produces two values
- /// (the result of the load and the result of the base + offset
- /// computation); a post-indexed store produces one value (the
- /// the result of the base + offset computation).
+ /// memory transaction. In addition to producing a chain,
+ /// post-indexed load produces two values (the result of the
load
+ /// and the result of the base + offset computation); a
+ /// post-indexed store produces one value (the the result of the
+ /// base + offset computation).
///
enum MemOpAddrMode {
UNINDEXED = 0,
@@ -1375,12 +1377,25 @@
/// LoadSDNode - This class is used to represent ISD::LOAD nodes.
///
class LoadSDNode : public SDNode {
- ISD::MemOpAddrMode AddrMode; // unindexed, pre-indexed, post-indexed.
- ISD::LoadExtType ExtType; // non-ext, anyext, sext, zext.
- MVT::ValueType LoadVT;// VT of loaded value before extension.
+ // AddrMode - unindexed, pre-indexed, post-indexed.
+ ISD::MemOpAddrMode AddrMode;
+
+ // ExtType - non-ext, anyext, sext, zext.
+ ISD::LoadExtType ExtType;
+
+ // LoadVT - VT of loaded value before extension.
+ MVT::ValueType LoadVT;
+
+ // SrcValue - Memory location for alias analysis.
const Value *SrcValue;
+
+ // SVOffset - Memory location offset.
int SVOffset;
+
+ // Alignment - Alignment of memory location in bytes.
unsigned Alignment;
+
+ // IsVolatile - True if the load is volatile.
bool IsVolatile;
protected:
friend class SelectionDAG;
@@ -1404,9 +1419,9 @@
}
public:
- const SDOperand &getChain() const { return getOperand(0); }
- const SDOperand &getBasePtr() const { return getOperand(1); }
- const SDOperand &getOffset() const { return getOperand(2); }
+ const SDOperand getChain() const { return getOperand(0); }
+ const SDOperand getBasePtr() const { return getOperand(1); }
+ const SDOperand getOffset() const { return getOperand(2); }
ISD::MemOpAddrMode getAddressingMode() const { return AddrMode; }
ISD::LoadExtType getExtensionType() const { return ExtType; }
MVT::ValueType getLoadVT() const { return LoadVT; }
@@ -1424,12 +1439,25 @@
/// StoreSDNode - This class is used to represent ISD::STORE nodes.
///
class StoreSDNode : public SDNode {
- ISD::MemOpAddrMode AddrMode; // unindexed, pre-indexed, post-indexed.
- bool IsTruncStore;//
[llvm-commits] CVS: llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
Changes in directory llvm/lib/Target/X86:
X86ISelDAGToDAG.cpp updated: 1.112 -> 1.113
---
Log message:
More isel time load folding checking for nodes that produce flag values.
See comment in CanBeFoldedBy() for detailed explanation.
---
Diffs of the changes: (+57 -6)
X86ISelDAGToDAG.cpp | 63 +++-
1 files changed, 57 insertions(+), 6 deletions(-)
Index: llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
diff -u llvm/lib/Target/X86/X86ISelDAGToDAG.cpp:1.112
llvm/lib/Target/X86/X86ISelDAGToDAG.cpp:1.113
--- llvm/lib/Target/X86/X86ISelDAGToDAG.cpp:1.112 Mon Oct 9 15:57:25 2006
+++ llvm/lib/Target/X86/X86ISelDAGToDAG.cpp Mon Oct 9 20:46:56 2006
@@ -213,7 +213,20 @@
};
}
-static void findNonImmUse(SDNode* Use, SDNode* Def, bool &found,
+static SDNode *findFlagUse(SDNode *N) {
+ unsigned FlagResNo = N->getNumValues()-1;
+ for (SDNode::use_iterator I = N->use_begin(), E = N->use_end(); I != E; ++I)
{
+SDNode *User = *I;
+for (unsigned i = 0, e = User->getNumOperands(); i != e; ++i) {
+ SDOperand Op = User->getOperand(i);
+ if (Op.ResNo == FlagResNo)
+return User;
+}
+ }
+ return NULL;
+}
+
+static void findNonImmUse(SDNode* Use, SDNode* Def, SDNode *Ignore, bool
&found,
std::set &Visited) {
if (found ||
Use->getNodeId() > Def->getNodeId() ||
@@ -222,8 +235,10 @@
for (unsigned i = 0, e = Use->getNumOperands(); i != e; ++i) {
SDNode *N = Use->getOperand(i).Val;
+if (N == Ignore)
+ continue;
if (N != Def) {
- findNonImmUse(N, Def, found, Visited);
+ findNonImmUse(N, Def, Ignore, found, Visited);
} else {
found = true;
break;
@@ -231,16 +246,27 @@
}
}
-static inline bool isNonImmUse(SDNode* Use, SDNode* Def) {
+static inline bool isNonImmUse(SDNode* Use, SDNode* Def, SDNode *Ignore=NULL) {
std::set Visited;
bool found = false;
for (unsigned i = 0, e = Use->getNumOperands(); i != e; ++i) {
SDNode *N = Use->getOperand(i).Val;
-if (N != Def) {
- findNonImmUse(N, Def, found, Visited);
+if (N != Def && N != Ignore) {
+ findNonImmUse(N, Def, Ignore, found, Visited);
if (found) break;
}
}
+
+ if (!found && Ignore) {
+// We must be checking for reachability between Def and a flag use. Go down
+// recursively if Use also produces a flag.
+MVT::ValueType VT = Use->getValueType(Use->getNumValues()-1);
+if (VT == MVT::Flag && !Use->use_empty()) {
+ SDNode *FU = findFlagUse(Use);
+ if (FU)
+return !isNonImmUse(FU, Def, Use);
+}
+ }
return found;
}
@@ -258,7 +284,32 @@
// /[X]
// | ^
// [U]|
- return !FastISel && !isNonImmUse(U, N);
+ if (!FastISel && !isNonImmUse(U, N)) {
+// If U produces a flag, then it gets (even more) interesting. Since it
+// would have been "glued" together with its flag use, we need to check if
+// it might reach N:
+//
+// [ N ]
+//^ ^
+//| |
+// [U] \--
+//^ [TF]
+//||
+// \ /
+// [FU]
+//
+// If FU (flag use) indirectly reach N (the load), and U fold N (call it
+// NU), then TF is a predecessor of FU and a successor of NU. But since
+// NU and FU are flagged together, this effectively creates a cycle.
+MVT::ValueType VT = U->getValueType(U->getNumValues()-1);
+if (VT == MVT::Flag && !U->use_empty()) {
+ SDNode *FU = findFlagUse(U);
+ if (FU)
+return !isNonImmUse(FU, N, U);
+}
+return true;
+ }
+ return false;
}
/// MoveBelowTokenFactor - Replace TokenFactor operand with load's chain
operand
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[llvm-commits] CVS: llvm/test/Regression/CodeGen/X86/2006-10-09-CycleInDAG.ll
Changes in directory llvm/test/Regression/CodeGen/X86:
2006-10-09-CycleInDAG.ll added (r1.1)
---
Log message:
Add test case from PR940: http://llvm.org/PR940 .
---
Diffs of the changes: (+10 -0)
2006-10-09-CycleInDAG.ll | 10 ++
1 files changed, 10 insertions(+)
Index: llvm/test/Regression/CodeGen/X86/2006-10-09-CycleInDAG.ll
diff -c /dev/null llvm/test/Regression/CodeGen/X86/2006-10-09-CycleInDAG.ll:1.1
*** /dev/null Mon Oct 9 23:33:56 2006
--- llvm/test/Regression/CodeGen/X86/2006-10-09-CycleInDAG.ll Mon Oct 9
23:33:46 2006
***
*** 0
--- 1,10
+ ; RUN: llvm-as < %s | llc -march=x86
+
+ void %_ZN13QFSFileEngine4readEPcx() {
+ %tmp201 = load int* null
+ %tmp201 = cast int %tmp201 to long
+ %tmp202 = load long* null
+ %tmp203 = add long %tmp201, %tmp202
+ store long %tmp203, long* null
+ ret void
+ }
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