Changes in directory llvm/lib/Target/Alpha:
AlphaISelLowering.cpp updated: 1.65 -> 1.66
AlphaInstrInfo.td updated: 1.125 -> 1.126
---
Log message:
Reflects ISD::LOAD / ISD::LOADX / LoadSDNode changes.
---
Diffs of the changes: (+31 -31)
AlphaISelLowering.cpp | 26 +++++++++++++-------------
AlphaInstrInfo.td | 36 ++++++++++++++++++------------------
2 files changed, 31 insertions(+), 31 deletions(-)
Index: llvm/lib/Target/Alpha/AlphaISelLowering.cpp
diff -u llvm/lib/Target/Alpha/AlphaISelLowering.cpp:1.65
llvm/lib/Target/Alpha/AlphaISelLowering.cpp:1.66
--- llvm/lib/Target/Alpha/AlphaISelLowering.cpp:1.65 Fri Oct 6 17:46:51 2006
+++ llvm/lib/Target/Alpha/AlphaISelLowering.cpp Mon Oct 9 15:57:24 2006
@@ -254,7 +254,7 @@
// Create the SelectionDAG nodes corresponding to a load
//from this parameter
SDOperand FIN = DAG.getFrameIndex(FI, MVT::i64);
- ArgVal = DAG.getLoad(ObjectVT, Root, FIN, DAG.getSrcValue(NULL));
+ ArgVal = DAG.getLoad(ObjectVT, Root, FIN, NULL, 0);
}
ArgValues.push_back(ArgVal);
}
@@ -430,7 +430,7 @@
SDOperand FI = DAG.getFrameIndex(FrameIdx, MVT::i64);
SDOperand ST = DAG.getStore(DAG.getEntryNode(),
Op.getOperand(0), FI, DAG.getSrcValue(0));
- LD = DAG.getLoad(MVT::f64, ST, FI, DAG.getSrcValue(0));
+ LD = DAG.getLoad(MVT::f64, ST, FI, NULL, 0);
}
SDOperand FP = DAG.getNode(isDouble?AlphaISD::CVTQT_:AlphaISD::CVTQS_,
isDouble?MVT::f64:MVT::f32, LD);
@@ -453,7 +453,7 @@
SDOperand FI = DAG.getFrameIndex(FrameIdx, MVT::i64);
SDOperand ST = DAG.getStore(DAG.getEntryNode(),
src, FI, DAG.getSrcValue(0));
- return DAG.getLoad(MVT::i64, ST, FI, DAG.getSrcValue(0));
+ return DAG.getLoad(MVT::i64, ST, FI, NULL, 0);
}
}
case ISD::ConstantPool: {
@@ -523,13 +523,14 @@
case ISD::VAARG: {
SDOperand Chain = Op.getOperand(0);
SDOperand VAListP = Op.getOperand(1);
- SDOperand VAListS = Op.getOperand(2);
+ SrcValueSDNode *VAListS = cast<SrcValueSDNode>(Op.getOperand(2));
- SDOperand Base = DAG.getLoad(MVT::i64, Chain, VAListP, VAListS);
+ SDOperand Base = DAG.getLoad(MVT::i64, Chain, VAListP, VAListS->getValue(),
+ VAListS->getOffset());
SDOperand Tmp = DAG.getNode(ISD::ADD, MVT::i64, VAListP,
DAG.getConstant(8, MVT::i64));
SDOperand Offset = DAG.getExtLoad(ISD::SEXTLOAD, MVT::i64,
Base.getValue(1),
- Tmp, DAG.getSrcValue(0), MVT::i32);
+ Tmp, NULL, 0, MVT::i32);
SDOperand DataPtr = DAG.getNode(ISD::ADD, MVT::i64, Base, Offset);
if (MVT::isFloatingPoint(Op.getValueType()))
{
@@ -551,10 +552,9 @@
SDOperand Result;
if (Op.getValueType() == MVT::i32)
Result = DAG.getExtLoad(ISD::SEXTLOAD, MVT::i64, Update, DataPtr,
- DAG.getSrcValue(0), MVT::i32);
+ NULL, 0, MVT::i32);
else
- Result = DAG.getLoad(Op.getValueType(), Update, DataPtr,
- DAG.getSrcValue(0));
+ Result = DAG.getLoad(Op.getValueType(), Update, DataPtr, NULL, 0);
return Result;
}
case ISD::VACOPY: {
@@ -562,14 +562,14 @@
SDOperand DestP = Op.getOperand(1);
SDOperand SrcP = Op.getOperand(2);
SDOperand DestS = Op.getOperand(3);
- SDOperand SrcS = Op.getOperand(4);
+ SrcValueSDNode *SrcS = cast<SrcValueSDNode>(Op.getOperand(4));
- SDOperand Val = DAG.getLoad(getPointerTy(), Chain, SrcP, SrcS);
+ SDOperand Val = DAG.getLoad(getPointerTy(), Chain, SrcP,
+ SrcS->getValue(), SrcS->getOffset());
SDOperand Result = DAG.getStore(Val.getValue(1), Val, DestP, DestS);
SDOperand NP = DAG.getNode(ISD::ADD, MVT::i64, SrcP,
DAG.getConstant(8, MVT::i64));
- Val = DAG.getExtLoad(ISD::SEXTLOAD, MVT::i64, Result, NP,
- DAG.getSrcValue(0), MVT::i32);
+ Val = DAG.getExtLoad(ISD::SEXTLOAD, MVT::i64, Result, NP, NULL,0,
MVT::i32);
SDOperand NPD = DAG.getNode(ISD::ADD, MVT::i64, DestP,
DAG.getConstant(8, MVT::i64));
return DAG.getNode(ISD::TRUNCSTORE, MVT::Other, Val.getValue(1),
Index: llvm/lib/Target/Alpha/AlphaInstrInfo.td
diff -u llvm/lib/Target/Alpha/AlphaInstrInfo.td:1.125
llvm/lib/Target/Alpha/AlphaInstrInfo.td:1.126
--- llvm/lib/Target/Alpha/AlphaInstrInfo.td:1.125 Wed Sep 20 10:05:49 2006
+++ llvm/lib/Target/Alpha/AlphaInstrInfo.td Mon Oct 9 15:57:24 2006
@@ -484,17 +484,17 @@
def LDQr : MForm<0x29, 0, 1, "ldq $RA,$DISP($RB)\t\t!gprellow",
[(set GPRC:$RA, (load (Alpha_gprello tglobaladdr:$DISP,
GPRC:$RB)))], s_ild>;
def LDL : MForm<0x28, 0, 1, "ldl $RA,$DISP($RB)",
- [(set GPRC:$RA, (sextload (add GPRC:$RB, immSExt16:$DISP),
i32))], s_ild>;
+ [(set GPRC:$RA, (sextloadi32 (add GPRC:$RB,
immSExt16:$DISP)))], s_ild>;
def LDLr : MForm<0x28, 0, 1, "ldl $RA,$DISP($RB)\t\t!gprellow",
- [(set GPRC:$RA, (sextload (Alpha_gprello tglobaladdr:$DISP,
GPRC:$RB), i32))], s_ild>;
+ [(set GPRC:$RA, (sextloadi32 (Alpha_gprello
tglobaladdr:$DISP, GPRC:$RB)))], s_ild>;
def LDBU : MForm<0x0A, 0, 1, "ldbu $RA,$DISP($RB)",
- [(set GPRC:$RA, (zextload (add GPRC:$RB, immSExt16:$DISP),
i8))], s_ild>;
+ [(set GPRC:$RA, (zextloadi8 (add GPRC:$RB,
immSExt16:$DISP)))], s_ild>;
def LDBUr : MForm<0x0A, 0, 1, "ldbu $RA,$DISP($RB)\t\t!gprellow",
- [(set GPRC:$RA, (zextload (Alpha_gprello tglobaladdr:$DISP,
GPRC:$RB), i8))], s_ild>;
+ [(set GPRC:$RA, (zextloadi8 (Alpha_gprello tglobaladdr:$DISP,
GPRC:$RB)))], s_ild>;
def LDWU : MForm<0x0C, 0, 1, "ldwu $RA,$DISP($RB)",
- [(set GPRC:$RA, (zextload (add GPRC:$RB, immSExt16:$DISP),
i16))], s_ild>;
+ [(set GPRC:$RA, (zextloadi16 (add GPRC:$RB,
immSExt16:$DISP)))], s_ild>;
def LDWUr : MForm<0x0C, 0, 1, "ldwu $RA,$DISP($RB)\t\t!gprellow",
- [(set GPRC:$RA, (zextload (Alpha_gprello tglobaladdr:$DISP,
GPRC:$RB), i16))], s_ild>;
+ [(set GPRC:$RA, (zextloadi16 (Alpha_gprello
tglobaladdr:$DISP, GPRC:$RB)))], s_ild>;
def STB : MForm<0x0E, 1, 0, "stb $RA,$DISP($RB)",
[(truncstore GPRC:$RA, (add GPRC:$RB, immSExt16:$DISP), i8)],
s_ist>;
def STBr : MForm<0x0E, 1, 0, "stb $RA,$DISP($RB)\t\t!gprellow",
@@ -548,11 +548,11 @@
//constpool rels
def : Pat<(i64 (load (Alpha_gprello tconstpool:$DISP, GPRC:$RB))),
(LDQr tconstpool:$DISP, GPRC:$RB)>;
-def : Pat<(i64 (sextload (Alpha_gprello tconstpool:$DISP, GPRC:$RB), i32)),
+def : Pat<(i64 (sextloadi32 (Alpha_gprello tconstpool:$DISP, GPRC:$RB))),
(LDLr tconstpool:$DISP, GPRC:$RB)>;
-def : Pat<(i64 (zextload (Alpha_gprello tconstpool:$DISP, GPRC:$RB), i8)),
+def : Pat<(i64 (zextloadi8 (Alpha_gprello tconstpool:$DISP, GPRC:$RB))),
(LDBUr tconstpool:$DISP, GPRC:$RB)>;
-def : Pat<(i64 (zextload (Alpha_gprello tconstpool:$DISP, GPRC:$RB), i16)),
+def : Pat<(i64 (zextloadi16 (Alpha_gprello tconstpool:$DISP, GPRC:$RB))),
(LDWUr tconstpool:$DISP, GPRC:$RB)>;
def : Pat<(i64 (Alpha_gprello tconstpool:$DISP, GPRC:$RB)),
(LDAr tconstpool:$DISP, GPRC:$RB)>;
@@ -571,11 +571,11 @@
//misc ext patterns
-def : Pat<(i64 (extload (add GPRC:$RB, immSExt16:$DISP), i8)),
+def : Pat<(i64 (extloadi8 (add GPRC:$RB, immSExt16:$DISP))),
(LDBU immSExt16:$DISP, GPRC:$RB)>;
-def : Pat<(i64 (extload (add GPRC:$RB, immSExt16:$DISP), i16)),
+def : Pat<(i64 (extloadi16 (add GPRC:$RB, immSExt16:$DISP))),
(LDWU immSExt16:$DISP, GPRC:$RB)>;
-def : Pat<(i64 (extload (add GPRC:$RB, immSExt16:$DISP), i32)),
+def : Pat<(i64 (extloadi32 (add GPRC:$RB, immSExt16:$DISP))),
(LDL immSExt16:$DISP, GPRC:$RB)>;
//0 disp patterns
@@ -585,17 +585,17 @@
(LDT 0, GPRC:$addr)>;
def : Pat<(f32 (load GPRC:$addr)),
(LDS 0, GPRC:$addr)>;
-def : Pat<(i64 (sextload GPRC:$addr, i32)),
+def : Pat<(i64 (sextloadi32 GPRC:$addr)),
(LDL 0, GPRC:$addr)>;
-def : Pat<(i64 (zextload GPRC:$addr, i16)),
+def : Pat<(i64 (zextloadi16 GPRC:$addr)),
(LDWU 0, GPRC:$addr)>;
-def : Pat<(i64 (zextload GPRC:$addr, i8)),
+def : Pat<(i64 (zextloadi8 GPRC:$addr)),
(LDBU 0, GPRC:$addr)>;
-def : Pat<(i64 (extload GPRC:$addr, i8)),
+def : Pat<(i64 (extloadi8 GPRC:$addr)),
(LDBU 0, GPRC:$addr)>;
-def : Pat<(i64 (extload GPRC:$addr, i16)),
+def : Pat<(i64 (extloadi16 GPRC:$addr)),
(LDWU 0, GPRC:$addr)>;
-def : Pat<(i64 (extload GPRC:$addr, i32)),
+def : Pat<(i64 (extloadi32 GPRC:$addr)),
(LDL 0, GPRC:$addr)>;
def : Pat<(store GPRC:$DATA, GPRC:$addr),
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