[llvm-commits] CVS: llvm/test/Regression/CodeGen/PowerPC/vec_shuffle.ll vec_spat.ll
Changes in directory llvm/test/Regression/CodeGen/PowerPC:
vec_shuffle.ll updated: 1.5 -> 1.6
vec_spat.ll updated: 1.3 -> 1.4
---
Log message:
add new testcase
---
Diffs of the changes: (+27 -1)
vec_shuffle.ll | 16
vec_spat.ll| 12 +++-
2 files changed, 27 insertions(+), 1 deletion(-)
Index: llvm/test/Regression/CodeGen/PowerPC/vec_shuffle.ll
diff -u llvm/test/Regression/CodeGen/PowerPC/vec_shuffle.ll:1.5
llvm/test/Regression/CodeGen/PowerPC/vec_shuffle.ll:1.6
--- llvm/test/Regression/CodeGen/PowerPC/vec_shuffle.ll:1.5 Thu Apr 6
17:27:59 2006
+++ llvm/test/Regression/CodeGen/PowerPC/vec_shuffle.ll Sat Apr 8 02:13:46 2006
@@ -253,6 +253,21 @@
entry:
%tmp = load <4 x int>* %A ; <<4 x int>> [#uses=2]
%tmp2 = load <4 x int>* %B ; <<4 x int>> [#uses=2]
+ %tmp = extractelement <4 x int> %tmp2, uint 0 ;
[#uses=1]
+ %tmp3 = extractelement <4 x int> %tmp, uint 0 ;
[#uses=1]
+ %tmp4 = extractelement <4 x int> %tmp2, uint 1 ;
[#uses=1]
+ %tmp5 = extractelement <4 x int> %tmp, uint 1 ;
[#uses=1]
+ %tmp6 = insertelement <4 x int> undef, int %tmp, uint 0 ; <<4 x
int>> [#uses=1]
+ %tmp7 = insertelement <4 x int> %tmp6, int %tmp3, uint 1
; <<4 x int>> [#uses=1]
+ %tmp8 = insertelement <4 x int> %tmp7, int %tmp4, uint 2
; <<4 x int>> [#uses=1]
+ %tmp9 = insertelement <4 x int> %tmp8, int %tmp5, uint 3
; <<4 x int>> [#uses=1]
+ store <4 x int> %tmp9, <4 x int>* %A
+ ret void
+}
+
+void %tw_h_flop(<4 x int>* %A, <4 x int>* %B) {
+ %tmp = load <4 x int>* %A ; <<4 x int>> [#uses=2]
+ %tmp2 = load <4 x int>* %B ; <<4 x int>> [#uses=2]
%tmp = extractelement <4 x int> %tmp, uint 0;
[#uses=1]
%tmp3 = extractelement <4 x int> %tmp2, uint 0 ;
[#uses=1]
%tmp4 = extractelement <4 x int> %tmp, uint 1 ;
[#uses=1]
@@ -265,6 +280,7 @@
ret void
}
+
void %VMRG_UNARY_tb_l(<16 x sbyte>* %A, <16 x sbyte>* %B) {
entry:
%tmp = load <16 x sbyte>* %A; <<16 x sbyte>> [#uses=16]
Index: llvm/test/Regression/CodeGen/PowerPC/vec_spat.ll
diff -u llvm/test/Regression/CodeGen/PowerPC/vec_spat.ll:1.3
llvm/test/Regression/CodeGen/PowerPC/vec_spat.ll:1.4
--- llvm/test/Regression/CodeGen/PowerPC/vec_spat.ll:1.3Tue Apr 4
12:20:45 2006
+++ llvm/test/Regression/CodeGen/PowerPC/vec_spat.llSat Apr 8 02:13:46 2006
@@ -1,7 +1,7 @@
; Test that vectors are scalarized/lowered correctly.
; RUN: llvm-as < %s | llc -march=ppc32 -mcpu=g5 | grep vspltw | wc -l | grep 2
&&
; RUN: llvm-as < %s | llc -march=ppc32 -mcpu=g3 | grep stfs | wc -l | grep 4 &&
-; RUN: llvm-as < %s | llc -march=ppc32 -mcpu=g5 | grep vsplti | wc -l | grep 2
&&
+; RUN: llvm-as < %s | llc -march=ppc32 -mcpu=g5 | grep vsplti | wc -l | grep 3
&&
; RUN: llvm-as < %s | llc -march=ppc32 -mcpu=g5 | grep vsplth | wc -l | grep 1
%f4 = type <4 x float>
@@ -59,3 +59,13 @@
ret void
}
+void %spltish(<16 x ubyte>* %A, <16 x ubyte>* %B) {
+ ; Gets converted to 16 x ubyte
+%tmp = load <16 x ubyte>* %B
+%tmp = cast <16 x ubyte> %tmp to <16 x sbyte>
+%tmp4 = sub <16 x sbyte> %tmp, cast (<8 x short> < short 15, short 15,
short 15, short 15, short 15, short 15, short 15, short 15 > to <16 x sbyte>)
+%tmp4 = cast <16 x sbyte> %tmp4 to <16 x ubyte>
+store <16 x ubyte> %tmp4, <16 x ubyte>* %A
+ret void
+}
+
___
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[llvm-commits] CVS: llvm/lib/Target/PowerPC/PPCISelLowering.cpp
Changes in directory llvm/lib/Target/PowerPC:
PPCISelLowering.cpp updated: 1.139 -> 1.140
---
Log message:
Implement PowerPC/CodeGen/vec_splat.ll:spltish to use vsplish instead of a
constant pool load.
---
Diffs of the changes: (+57 -0)
PPCISelLowering.cpp | 57
1 files changed, 57 insertions(+)
Index: llvm/lib/Target/PowerPC/PPCISelLowering.cpp
diff -u llvm/lib/Target/PowerPC/PPCISelLowering.cpp:1.139
llvm/lib/Target/PowerPC/PPCISelLowering.cpp:1.140
--- llvm/lib/Target/PowerPC/PPCISelLowering.cpp:1.139 Sat Apr 8 01:46:53 2006
+++ llvm/lib/Target/PowerPC/PPCISelLowering.cpp Sat Apr 8 02:14:26 2006
@@ -431,6 +431,63 @@
/// bytes of each element [124] -> [bhw].
SDOperand PPC::get_VSPLI_elt(SDNode *N, unsigned ByteSize, SelectionDAG &DAG) {
SDOperand OpVal(0, 0);
+
+ // If ByteSize of the splat is bigger than the element size of the
+ // build_vector, then we have a case where we are checking for a splat where
+ // multiple elements of the buildvector are folded together into a single
+ // logical element of the splat (e.g. "vsplish 1" to splat {0,1}*8).
+ unsigned EltSize = 16/N->getNumOperands();
+ if (EltSize < ByteSize) {
+unsigned Multiple = ByteSize/EltSize; // Number of BV entries per
spltval.
+SDOperand UniquedVals[4];
+assert(Multiple > 1 && Multiple <= 4 && "How can this happen?");
+
+// See if all of the elements in the buildvector agree across.
+for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) {
+ if (N->getOperand(i).getOpcode() == ISD::UNDEF) continue;
+ // If the element isn't a constant, bail fully out.
+ if (!isa(N->getOperand(i))) return SDOperand();
+
+
+ if (UniquedVals[i&(Multiple-1)].Val == 0)
+UniquedVals[i&(Multiple-1)] = N->getOperand(i);
+ else if (UniquedVals[i&(Multiple-1)] != N->getOperand(i))
+return SDOperand(); // no match.
+}
+
+// Okay, if we reached this point, UniquedVals[0..Multiple-1] contains
+// either constant or undef values that are identical for each chunk. See
+// if these chunks can form into a larger vspltis*.
+
+// Check to see if all of the leading entries are either 0 or -1. If
+// neither, then this won't fit into the immediate field.
+bool LeadingZero = true;
+bool LeadingOnes = true;
+for (unsigned i = 0; i != Multiple-1; ++i) {
+ if (UniquedVals[i].Val == 0) continue; // Must have been undefs.
+
+ LeadingZero &= cast(UniquedVals[i])->isNullValue();
+ LeadingOnes &= cast(UniquedVals[i])->isAllOnesValue();
+}
+// Finally, check the least significant entry.
+if (LeadingZero) {
+ if (UniquedVals[Multiple-1].Val == 0)
+return DAG.getTargetConstant(0, MVT::i32); // 0,0,0,undef
+ int Val = cast(UniquedVals[Multiple-1])->getValue();
+ if (Val < 16)
+return DAG.getTargetConstant(Val, MVT::i32); // 0,0,0,4 -> vspltisw(4)
+}
+if (LeadingOnes) {
+ if (UniquedVals[Multiple-1].Val == 0)
+return DAG.getTargetConstant(~0U, MVT::i32); // -1,-1,-1,undef
+ int Val
=cast(UniquedVals[Multiple-1])->getSignExtended();
+ if (Val >= -16)// -1,-1,-1,-2 -> vspltisw(-2)
+return DAG.getTargetConstant(Val, MVT::i32);
+}
+
+return SDOperand();
+ }
+
// Check to see if this buildvec has a single non-undef value in its
elements.
for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) {
if (N->getOperand(i).getOpcode() == ISD::UNDEF) continue;
___
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[llvm-commits] CVS: llvm/lib/Target/Alpha/AlphaTargetMachine.cpp
Changes in directory llvm/lib/Target/Alpha: AlphaTargetMachine.cpp updated: 1.22 -> 1.23 --- Log message: Disable switch lowering for targets based on the selection dag isel, letting the code generator handle them directly. --- Diffs of the changes: (+0 -6) AlphaTargetMachine.cpp |6 -- 1 files changed, 6 deletions(-) Index: llvm/lib/Target/Alpha/AlphaTargetMachine.cpp diff -u llvm/lib/Target/Alpha/AlphaTargetMachine.cpp:1.22 llvm/lib/Target/Alpha/AlphaTargetMachine.cpp:1.23 --- llvm/lib/Target/Alpha/AlphaTargetMachine.cpp:1.22 Wed Mar 22 23:43:15 2006 +++ llvm/lib/Target/Alpha/AlphaTargetMachine.cppSat Apr 8 14:46:55 2006 @@ -81,9 +81,6 @@ // FIXME: Implement the invoke/unwind instructions! PM.add(createLowerInvokePass()); - // FIXME: Implement the switch instruction in the instruction selector! - PM.add(createLowerSwitchPass()); - // Make sure that no unreachable blocks are instruction selected. PM.add(createUnreachableBlockEliminationPass()); @@ -119,9 +116,6 @@ // FIXME: Implement the invoke/unwind instructions! PM.add(createLowerInvokePass()); - // FIXME: Implement the switch instruction in the instruction selector! - PM.add(createLowerSwitchPass()); - // Make sure that no unreachable blocks are instruction selected. PM.add(createUnreachableBlockEliminationPass()); ___ llvm-commits mailing list llvm-commits@cs.uiuc.edu http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
[llvm-commits] CVS: llvm/lib/Target/PowerPC/PPCTargetMachine.cpp
Changes in directory llvm/lib/Target/PowerPC: PPCTargetMachine.cpp updated: 1.85 -> 1.86 --- Log message: Disable switch lowering for targets based on the selection dag isel, letting the code generator handle them directly. --- Diffs of the changes: (+0 -6) PPCTargetMachine.cpp |6 -- 1 files changed, 6 deletions(-) Index: llvm/lib/Target/PowerPC/PPCTargetMachine.cpp diff -u llvm/lib/Target/PowerPC/PPCTargetMachine.cpp:1.85 llvm/lib/Target/PowerPC/PPCTargetMachine.cpp:1.86 --- llvm/lib/Target/PowerPC/PPCTargetMachine.cpp:1.85 Wed Mar 22 23:43:15 2006 +++ llvm/lib/Target/PowerPC/PPCTargetMachine.cppSat Apr 8 14:46:55 2006 @@ -93,9 +93,6 @@ // Clean up after other passes, e.g. merging critical edges. if (!Fast) PM.add(createCFGSimplificationPass()); - // FIXME: Implement the switch instruction in the instruction selector! - PM.add(createLowerSwitchPass()); - // Make sure that no unreachable blocks are instruction selected. PM.add(createUnreachableBlockEliminationPass()); @@ -147,9 +144,6 @@ // Clean up after other passes, e.g. merging critical edges. PM.add(createCFGSimplificationPass()); - // FIXME: Implement the switch instruction in the instruction selector! - PM.add(createLowerSwitchPass()); - // Make sure that no unreachable blocks are instruction selected. PM.add(createUnreachableBlockEliminationPass()); ___ llvm-commits mailing list llvm-commits@cs.uiuc.edu http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
[llvm-commits] CVS: llvm/lib/Target/Sparc/SparcTargetMachine.cpp
Changes in directory llvm/lib/Target/Sparc: SparcTargetMachine.cpp updated: 1.43 -> 1.44 --- Log message: Disable switch lowering for targets based on the selection dag isel, letting the code generator handle them directly. --- Diffs of the changes: (+0 -3) SparcTargetMachine.cpp |3 --- 1 files changed, 3 deletions(-) Index: llvm/lib/Target/Sparc/SparcTargetMachine.cpp diff -u llvm/lib/Target/Sparc/SparcTargetMachine.cpp:1.43 llvm/lib/Target/Sparc/SparcTargetMachine.cpp:1.44 --- llvm/lib/Target/Sparc/SparcTargetMachine.cpp:1.43 Wed Mar 22 23:43:15 2006 +++ llvm/lib/Target/Sparc/SparcTargetMachine.cppSat Apr 8 14:46:55 2006 @@ -72,9 +72,6 @@ // FIXME: implement the invoke/unwind instructions! PM.add(createLowerInvokePass()); - // FIXME: implement the switch instruction in the instruction selector. - PM.add(createLowerSwitchPass()); - // Print LLVM code input to instruction selector: if (PrintMachineCode) PM.add(new PrintFunctionPass()); ___ llvm-commits mailing list llvm-commits@cs.uiuc.edu http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
[llvm-commits] CVS: llvm/lib/Target/IA64/IA64TargetMachine.cpp
Changes in directory llvm/lib/Target/IA64: IA64TargetMachine.cpp updated: 1.13 -> 1.14 --- Log message: Disable switch lowering for targets based on the selection dag isel, letting the code generator handle them directly. --- Diffs of the changes: (+0 -3) IA64TargetMachine.cpp |3 --- 1 files changed, 3 deletions(-) Index: llvm/lib/Target/IA64/IA64TargetMachine.cpp diff -u llvm/lib/Target/IA64/IA64TargetMachine.cpp:1.13 llvm/lib/Target/IA64/IA64TargetMachine.cpp:1.14 --- llvm/lib/Target/IA64/IA64TargetMachine.cpp:1.13 Wed Mar 22 23:43:15 2006 +++ llvm/lib/Target/IA64/IA64TargetMachine.cpp Sat Apr 8 14:46:55 2006 @@ -96,9 +96,6 @@ PM.add(createLowerInvokePass(704, 16)); // on ia64 linux, jmpbufs are 704 // bytes and must be 16byte aligned - // FIXME: Implement the switch instruction in the instruction selector! - PM.add(createLowerSwitchPass()); - // Make sure that no unreachable blocks are instruction selected. PM.add(createUnreachableBlockEliminationPass()); ___ llvm-commits mailing list llvm-commits@cs.uiuc.edu http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
[llvm-commits] CVS: llvm/lib/Target/X86/X86TargetMachine.cpp
Changes in directory llvm/lib/Target/X86:
X86TargetMachine.cpp updated: 1.111 -> 1.112
---
Log message:
Disable switch lowering for targets based on the selection dag isel,
letting the code generator handle them directly.
---
Diffs of the changes: (+0 -10)
X86TargetMachine.cpp | 10 --
1 files changed, 10 deletions(-)
Index: llvm/lib/Target/X86/X86TargetMachine.cpp
diff -u llvm/lib/Target/X86/X86TargetMachine.cpp:1.111
llvm/lib/Target/X86/X86TargetMachine.cpp:1.112
--- llvm/lib/Target/X86/X86TargetMachine.cpp:1.111 Sun Mar 26 19:32:24 2006
+++ llvm/lib/Target/X86/X86TargetMachine.cppSat Apr 8 14:46:55 2006
@@ -36,8 +36,6 @@
cl::opt DisableOutput("disable-x86-llc-output", cl::Hidden,
cl::desc("Disable the X86 asm printer, for use "
"when profiling the code generator."));
- cl::opt DisableLowerSwitch("disable-lower-switch", cl::Hidden,
- cl::desc("Disable the LowerSwitch pass"));
// Register the target.
RegisterTarget X("x86", " IA-32 (Pentium and above)");
}
@@ -100,10 +98,6 @@
// FIXME: Implement the invoke/unwind instructions!
PM.add(createLowerInvokePass());
- // FIXME: Implement the switch instruction in the instruction selector!
- if (!DisableLowerSwitch)
-PM.add(createLowerSwitchPass());
-
// Make sure that no unreachable blocks are instruction selected.
PM.add(createUnreachableBlockEliminationPass());
@@ -169,10 +163,6 @@
// FIXME: Implement the invoke/unwind instructions!
PM.add(createLowerInvokePass());
- // FIXME: Implement the switch instruction in the instruction selector!
- if (!DisableLowerSwitch)
-PM.add(createLowerSwitchPass());
-
// Make sure that no unreachable blocks are instruction selected.
PM.add(createUnreachableBlockEliminationPass());
___
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[llvm-commits] CVS: llvm-test/Makefile.programs
Changes in directory llvm-test: Makefile.programs updated: 1.202 -> 1.203 --- Log message: switch back to fastcc for x86 llcbeta --- Diffs of the changes: (+1 -1) Makefile.programs |2 +- 1 files changed, 1 insertion(+), 1 deletion(-) Index: llvm-test/Makefile.programs diff -u llvm-test/Makefile.programs:1.202 llvm-test/Makefile.programs:1.203 --- llvm-test/Makefile.programs:1.202 Sun Mar 26 19:34:00 2006 +++ llvm-test/Makefile.programs Sat Apr 8 16:16:16 2006 @@ -197,7 +197,7 @@ LLCBETAOPTION := -sched=simple endif ifeq ($(ARCH),x86) -LLCBETAOPTION := -disable-lower-switch +LLCBETAOPTION := -enable-x86-fastcc endif ifeq ($(ARCH),Sparc) LLCBETAOPTION := -enable-sparc-v9-insts ___ llvm-commits mailing list llvm-commits@cs.uiuc.edu http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
[llvm-commits] CVS: llvm/include/llvm/CodeGen/SelectionDAGNodes.h
Changes in directory llvm/include/llvm/CodeGen: SelectionDAGNodes.h updated: 1.126 -> 1.127 --- Log message: Add a new VSELECT node. --- Diffs of the changes: (+5 -0) SelectionDAGNodes.h |5 + 1 files changed, 5 insertions(+) Index: llvm/include/llvm/CodeGen/SelectionDAGNodes.h diff -u llvm/include/llvm/CodeGen/SelectionDAGNodes.h:1.126 llvm/include/llvm/CodeGen/SelectionDAGNodes.h:1.127 --- llvm/include/llvm/CodeGen/SelectionDAGNodes.h:1.126 Sat Apr 1 20:28:52 2006 +++ llvm/include/llvm/CodeGen/SelectionDAGNodes.h Sat Apr 8 17:16:01 2006 @@ -230,6 +230,11 @@ VADD, VSUB, VMUL, VSDIV, VUDIV, VAND, VOR, VXOR, +/// VSELECT(COND,LHS,RHS, COUNT,TYPE) - Select for MVT::Vector values. +/// COND is a boolean value. This node return LHS if COND is true, RHS if +/// COND is false. +VSELECT, + /// SCALAR_TO_VECTOR(VAL) - This represents the operation of loading a /// scalar value into the low element of the resultant vector type. The top /// elements of the vector are undefined. ___ llvm-commits mailing list llvm-commits@cs.uiuc.edu http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
[llvm-commits] CVS: llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp SelectionDAG.cpp SelectionDAGISel.cpp
Changes in directory llvm/lib/CodeGen/SelectionDAG:
LegalizeDAG.cpp updated: 1.356 -> 1.357
SelectionDAG.cpp updated: 1.296 -> 1.297
SelectionDAGISel.cpp updated: 1.220 -> 1.221
---
Log message:
Add code generator support for VSELECT
---
Diffs of the changes: (+22 -10)
LegalizeDAG.cpp |5 +
SelectionDAG.cpp | 17 +
SelectionDAGISel.cpp | 10 --
3 files changed, 22 insertions(+), 10 deletions(-)
Index: llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
diff -u llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp:1.356
llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp:1.357
--- llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp:1.356 Sat Apr 8 00:34:25 2006
+++ llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp Sat Apr 8 17:22:57 2006
@@ -4773,6 +4773,11 @@
assert(0 && "Cast from unsupported vector type not implemented yet!");
}
}
+ case ISD::VSELECT:
+Result = DAG.getNode(ISD::SELECT, NewVT, Op.getOperand(0),
+ PackVectorOp(Op.getOperand(1), NewVT),
+ PackVectorOp(Op.getOperand(2), NewVT));
+break;
}
if (TLI.isTypeLegal(NewVT))
Index: llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
diff -u llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp:1.296
llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp:1.297
--- llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp:1.296Mon Apr 3
20:02:22 2006
+++ llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp Sat Apr 8 17:22:57 2006
@@ -2760,15 +2760,16 @@
case ISD::SETCC: return "setcc";
case ISD::SELECT: return "select";
case ISD::SELECT_CC: return "select_cc";
- case ISD::INSERT_VECTOR_ELT: return "insert_vector_elt";
- case ISD::VINSERT_VECTOR_ELT: return "vinsert_vector_elt";
- case ISD::EXTRACT_VECTOR_ELT: return "extract_vector_elt";
+ case ISD::VSELECT: return "vselect";
+ case ISD::INSERT_VECTOR_ELT: return "insert_vector_elt";
+ case ISD::VINSERT_VECTOR_ELT: return "vinsert_vector_elt";
+ case ISD::EXTRACT_VECTOR_ELT: return "extract_vector_elt";
case ISD::VEXTRACT_VECTOR_ELT: return "vextract_vector_elt";
- case ISD::SCALAR_TO_VECTOR: return "scalar_to_vector";
- case ISD::VBUILD_VECTOR: return "vbuild_vector";
- case ISD::VECTOR_SHUFFLE: return "vector_shuffle";
- case ISD::VVECTOR_SHUFFLE: return "vvector_shuffle";
- case ISD::VBIT_CONVERT: return "vbit_convert";
+ case ISD::SCALAR_TO_VECTOR:return "scalar_to_vector";
+ case ISD::VBUILD_VECTOR: return "vbuild_vector";
+ case ISD::VECTOR_SHUFFLE: return "vector_shuffle";
+ case ISD::VVECTOR_SHUFFLE: return "vvector_shuffle";
+ case ISD::VBIT_CONVERT:return "vbit_convert";
case ISD::ADDC:return "addc";
case ISD::ADDE:return "adde";
case ISD::SUBC:return "subc";
Index: llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
diff -u llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp:1.220
llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp:1.221
--- llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp:1.220Fri Apr 7
23:15:24 2006
+++ llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp Sat Apr 8 17:22:57 2006
@@ -992,8 +992,14 @@
SDOperand Cond = getValue(I.getOperand(0));
SDOperand TrueVal = getValue(I.getOperand(1));
SDOperand FalseVal = getValue(I.getOperand(2));
- setValue(&I, DAG.getNode(ISD::SELECT, TrueVal.getValueType(), Cond,
- TrueVal, FalseVal));
+ if (!isa(I.getType())) {
+setValue(&I, DAG.getNode(ISD::SELECT, TrueVal.getValueType(), Cond,
+ TrueVal, FalseVal));
+ } else {
+setValue(&I, DAG.getNode(ISD::VSELECT, MVT::Vector, Cond, TrueVal,
FalseVal,
+ *(TrueVal.Val->op_end()-2),
+ *(TrueVal.Val->op_end()-1)));
+ }
}
void SelectionDAGLowering::visitCast(User &I) {
___
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[llvm-commits] CVS: llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp PPCISelLowering.cpp PPCInstrInfo.td
Changes in directory llvm/lib/Target/PowerPC:
PPCISelDAGToDAG.cpp updated: 1.178 -> 1.179
PPCISelLowering.cpp updated: 1.140 -> 1.141
PPCInstrInfo.td updated: 1.214 -> 1.215
---
Log message:
Add VRRC select support
---
Diffs of the changes: (+8 -2)
PPCISelDAGToDAG.cpp |5 -
PPCISelLowering.cpp |3 ++-
PPCInstrInfo.td |2 ++
3 files changed, 8 insertions(+), 2 deletions(-)
Index: llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp
diff -u llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp:1.178
llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp:1.179
--- llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp:1.178 Sun Mar 26 04:06:40 2006
+++ llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp Sat Apr 8 17:45:08 2006
@@ -1219,8 +1219,11 @@
SelectCCOp = PPC::SELECT_CC_Int;
else if (N->getValueType(0) == MVT::f32)
SelectCCOp = PPC::SELECT_CC_F4;
-else
+else if (N->getValueType(0) == MVT::f64)
SelectCCOp = PPC::SELECT_CC_F8;
+else
+ SelectCCOp = PPC::SELECT_CC_VRRC;
+
SDOperand N2, N3;
Select(N2, N->getOperand(2));
Select(N3, N->getOperand(3));
Index: llvm/lib/Target/PowerPC/PPCISelLowering.cpp
diff -u llvm/lib/Target/PowerPC/PPCISelLowering.cpp:1.140
llvm/lib/Target/PowerPC/PPCISelLowering.cpp:1.141
--- llvm/lib/Target/PowerPC/PPCISelLowering.cpp:1.140 Sat Apr 8 02:14:26 2006
+++ llvm/lib/Target/PowerPC/PPCISelLowering.cpp Sat Apr 8 17:45:08 2006
@@ -1484,7 +1484,8 @@
MachineBasicBlock *BB) {
assert((MI->getOpcode() == PPC::SELECT_CC_Int ||
MI->getOpcode() == PPC::SELECT_CC_F4 ||
- MI->getOpcode() == PPC::SELECT_CC_F8) &&
+ MI->getOpcode() == PPC::SELECT_CC_F8 ||
+ MI->getOpcode() == PPC::SELECT_CC_VRRC) &&
"Unexpected instr type to insert");
// To "insert" a SELECT_CC instruction, we actually have to insert the
diamond
Index: llvm/lib/Target/PowerPC/PPCInstrInfo.td
diff -u llvm/lib/Target/PowerPC/PPCInstrInfo.td:1.214
llvm/lib/Target/PowerPC/PPCInstrInfo.td:1.215
--- llvm/lib/Target/PowerPC/PPCInstrInfo.td:1.214 Thu Mar 30 23:13:27 2006
+++ llvm/lib/Target/PowerPC/PPCInstrInfo.td Sat Apr 8 17:45:08 2006
@@ -247,6 +247,8 @@
i32imm:$BROPC), "; SELECT_CC PSEUDO!", []>;
def SELECT_CC_F8 : Pseudo<(ops F8RC:$dst, CRRC:$cond, F8RC:$T, F8RC:$F,
i32imm:$BROPC), "; SELECT_CC PSEUDO!", []>;
+ def SELECT_CC_VRRC: Pseudo<(ops VRRC:$dst, CRRC:$cond, VRRC:$T, VRRC:$F,
+ i32imm:$BROPC), "; SELECT_CC PSEUDO!", []>;
}
let isTerminator = 1, noResults = 1, PPC970_Unit = 7 in {
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[llvm-commits] CVS: llvm/lib/Target/PowerPC/PPCISelLowering.cpp
Changes in directory llvm/lib/Target/PowerPC: PPCISelLowering.cpp updated: 1.141 -> 1.142 --- Log message: properly mark vector selects as expanded to select_cc --- Diffs of the changes: (+4 -0) PPCISelLowering.cpp |4 1 files changed, 4 insertions(+) Index: llvm/lib/Target/PowerPC/PPCISelLowering.cpp diff -u llvm/lib/Target/PowerPC/PPCISelLowering.cpp:1.141 llvm/lib/Target/PowerPC/PPCISelLowering.cpp:1.142 --- llvm/lib/Target/PowerPC/PPCISelLowering.cpp:1.141 Sat Apr 8 17:45:08 2006 +++ llvm/lib/Target/PowerPC/PPCISelLowering.cpp Sat Apr 8 17:59:15 2006 @@ -87,6 +87,10 @@ setOperationAction(ISD::SELECT, MVT::i32, Expand); setOperationAction(ISD::SELECT, MVT::f32, Expand); setOperationAction(ISD::SELECT, MVT::f64, Expand); + setOperationAction(ISD::SELECT, MVT::v4f32, Expand); + setOperationAction(ISD::SELECT, MVT::v4i32, Expand); + setOperationAction(ISD::SELECT, MVT::v8i16, Expand); + setOperationAction(ISD::SELECT, MVT::v16i8, Expand); // PowerPC wants to turn select_cc of FP into fsel when possible. setOperationAction(ISD::SELECT_CC, MVT::f32, Custom); ___ llvm-commits mailing list llvm-commits@cs.uiuc.edu http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
