[llvm-commits] CVS: llvm/test/Regression/Transforms/InstCombine/xor.ll
Changes in directory llvm/test/Regression/Transforms/InstCombine:
xor.ll updated: 1.16 -> 1.17
---
Log message:
new testcases
---
Diffs of the changes: (+15 -0)
xor.ll | 15 +++
1 files changed, 15 insertions(+)
Index: llvm/test/Regression/Transforms/InstCombine/xor.ll
diff -u llvm/test/Regression/Transforms/InstCombine/xor.ll:1.16
llvm/test/Regression/Transforms/InstCombine/xor.ll:1.17
--- llvm/test/Regression/Transforms/InstCombine/xor.ll:1.16 Sun Feb 26
19:43:02 2006
+++ llvm/test/Regression/Transforms/InstCombine/xor.ll Sat Apr 1 02:02:51 2006
@@ -166,3 +166,18 @@
%tmp.4 = setne int %tmp.2, %c
ret bool %tmp.4
}
+
+int %test25(int %g, int %h) {
+ %h2 = xor int %h, -1
+%tmp2 = and int %h2, %g
+%tmp4 = xor int %tmp2, %g ; (h2&g)^g -> ~h2 & g -> h & g
+ret int %tmp4
+}
+
+int %test26(int %a, int %b) {
+ %b2 = xor int %b, -1
+%tmp2 = xor int %a, %b2
+%tmp4 = and int %tmp2, %a ; (a^b2)&a -> ~b2 & a -> b & a
+ret int %tmp4
+}
+
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[llvm-commits] CVS: llvm/lib/Transforms/Scalar/InstructionCombining.cpp
Changes in directory llvm/lib/Transforms/Scalar:
InstructionCombining.cpp updated: 1.456 -> 1.457
---
Log message:
Fold A^(B&A) -> (B&A)^A
Fold (B&A)^A == ~B & A
This implements InstCombine/xor.ll:test2[56]
---
Diffs of the changes: (+46 -7)
InstructionCombining.cpp | 53 ---
1 files changed, 46 insertions(+), 7 deletions(-)
Index: llvm/lib/Transforms/Scalar/InstructionCombining.cpp
diff -u llvm/lib/Transforms/Scalar/InstructionCombining.cpp:1.456
llvm/lib/Transforms/Scalar/InstructionCombining.cpp:1.457
--- llvm/lib/Transforms/Scalar/InstructionCombining.cpp:1.456 Fri Mar 31
17:01:56 2006
+++ llvm/lib/Transforms/Scalar/InstructionCombining.cpp Sat Apr 1 02:03:55 2006
@@ -2508,6 +2508,30 @@
if (match(Op1, m_Or(m_Value(A), m_Value(B
if (A == Op0 || B == Op0)// A & (A | ?) --> A
return ReplaceInstUsesWith(I, Op0);
+
+if (Op0->hasOneUse() &&
+match(Op0, m_Xor(m_Value(A), m_Value(B {
+ if (A == Op1) {// (A^B)&A -> A&(A^B)
+I.swapOperands(); // Simplify below
+std::swap(Op0, Op1);
+ } else if (B == Op1) { // (A^B)&B -> B&(B^A)
+cast(Op0)->swapOperands();
+I.swapOperands(); // Simplify below
+std::swap(Op0, Op1);
+ }
+}
+if (Op1->hasOneUse() &&
+match(Op1, m_Xor(m_Value(A), m_Value(B {
+ if (B == Op0) {// B&(A^B) -> B&(B^A)
+cast(Op1)->swapOperands();
+std::swap(A, B);
+ }
+ if (A == Op0) {// A&(A^B) -> A & ~B
+Instruction *NotB = BinaryOperator::createNot(B, "tmp");
+InsertNewInstBefore(NotB, I);
+return BinaryOperator::createAnd(A, NotB);
+ }
+}
}
@@ -2943,14 +2967,14 @@
return ReplaceInstUsesWith(I,
ConstantIntegral::getAllOnesValue(I.getType()));
- if (Instruction *Op1I = dyn_cast(Op1))
+ if (BinaryOperator *Op1I = dyn_cast(Op1))
if (Op1I->getOpcode() == Instruction::Or) {
if (Op1I->getOperand(0) == Op0) { // B^(B|A) == (A|B)^B
-cast(Op1I)->swapOperands();
+Op1I->swapOperands();
I.swapOperands();
std::swap(Op0, Op1);
} else if (Op1I->getOperand(1) == Op0) { // B^(A|B) == (A|B)^B
-I.swapOperands();
+I.swapOperands(); // Simplified below.
std::swap(Op0, Op1);
}
} else if (Op1I->getOpcode() == Instruction::Xor) {
@@ -2958,15 +2982,22 @@
return ReplaceInstUsesWith(I, Op1I->getOperand(1));
else if (Op0 == Op1I->getOperand(1)) // A^(B^A) == B
return ReplaceInstUsesWith(I, Op1I->getOperand(0));
+} else if (Op1I->getOpcode() == Instruction::And && Op1I->hasOneUse()) {
+ if (Op1I->getOperand(0) == Op0) // A^(A&B) ->
A^(B&A)
+Op1I->swapOperands();
+ if (Op0 == Op1I->getOperand(1)) {// A^(B&A) ->
(B&A)^A
+I.swapOperands(); // Simplified below.
+std::swap(Op0, Op1);
+ }
}
- if (Instruction *Op0I = dyn_cast(Op0))
+ if (BinaryOperator *Op0I = dyn_cast(Op0))
if (Op0I->getOpcode() == Instruction::Or && Op0I->hasOneUse()) {
if (Op0I->getOperand(0) == Op1)// (B|A)^B == (A|B)^B
-cast(Op0I)->swapOperands();
+Op0I->swapOperands();
if (Op0I->getOperand(1) == Op1) { // (A|B)^B == A & ~B
-Value *NotB = InsertNewInstBefore(BinaryOperator::createNot(Op1,
- Op1->getName()+".not"),
I);
+Instruction *NotB = BinaryOperator::createNot(Op1, "tmp");
+InsertNewInstBefore(NotB, I);
return BinaryOperator::createAnd(Op0I->getOperand(0), NotB);
}
} else if (Op0I->getOpcode() == Instruction::Xor) {
@@ -2974,6 +3005,14 @@
return ReplaceInstUsesWith(I, Op0I->getOperand(1));
else if (Op1 == Op0I->getOperand(1)) // (B^A)^A == B
return ReplaceInstUsesWith(I, Op0I->getOperand(0));
+} else if (Op0I->getOpcode() == Instruction::And && Op0I->hasOneUse()) {
+ if (Op0I->getOperand(0) == Op1) // (A&B)^A ->
(B&A)^A
+Op0I->swapOperands();
+ if (Op0I->getOperand(1) == Op1) {// (B&A)^A == ~B & A
+Instruction *N = BinaryOperator::createNot(Op0I->getOperand(0), "tmp");
+InsertNewInstBefore(N, I);
+return BinaryOperator::createAnd(N, Op1);
+ }
}
// (setcc1 A, B) ^ (setcc2 A, B) --> (setcc3 A, B)
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[llvm-commits] CVS: llvm/test/Regression/Transforms/InstCombine/2006-04-01-InfLoop.ll
Changes in directory llvm/test/Regression/Transforms/InstCombine:
2006-04-01-InfLoop.ll added (r1.1)
---
Log message:
New testcase that caused instcombine to infinitely loop (with my recent
patch), distilled from Applications/JM/ldecod
---
Diffs of the changes: (+441 -0)
2006-04-01-InfLoop.ll | 441 ++
1 files changed, 441 insertions(+)
Index: llvm/test/Regression/Transforms/InstCombine/2006-04-01-InfLoop.ll
diff -c /dev/null
llvm/test/Regression/Transforms/InstCombine/2006-04-01-InfLoop.ll:1.1
*** /dev/null Sat Apr 1 16:04:50 2006
--- llvm/test/Regression/Transforms/InstCombine/2006-04-01-InfLoop.ll Sat Apr
1 16:04:40 2006
***
*** 0
--- 1,441
+ ; RUN: llvm-as < %s | opt -instcombine -disable-output
+
+ %struct.DecRefPicMarking_s = type { int, int, int, int, int,
%struct.DecRefPicMarking_s* }
+ %struct.datapartition = type { %typedef.Bitstream*,
%typedef.DecodingEnvironment, int (%struct.syntaxelement*, %struct.img_par*,
%struct.inp_par*, %struct.datapartition*)* }
+ %struct.img_par = type { int, uint, uint, int, int*, int, int, int,
int, int, int, int, int, int, int, int, int, int, int, int, int, int, int, int,
[16 x [16 x ushort]], [6 x [32 x int]], [16 x [16 x int]], [4 x [12 x [4 x [4 x
int, [16 x int], int**, int*, int***, int**, int, int, int, int,
%typedef.Slice*, %struct.macroblock*, int, int, int, int, int, int, int**,
%struct.DecRefPicMarking_s*, int, int, int, int, int, int, int, uint, int, int,
int, uint, uint, uint, uint, int, [3 x int], int, uint, int, uint, int, int,
int, uint, uint, int, int, int, int, uint, uint, int***, int***, int, int,
int, uint, int, int, int, int, uint, uint, uint, uint, uint, uint, uint, int,
int, int, int, int, int, int, int, int, int, int, uint, int, int, int, int,
int, int, int, int, int, int, int, int, int, int, int, %struct.timeb,
%struct.timeb, int, int, int, int, int, uint, int, int }
+ %struct.inp_par = type { [100 x sbyte], [100 x sbyte], [100 x sbyte],
int, int, int, int, int, int, int }
+ %struct.macroblock = type { int, int, int, %struct.macroblock*,
%struct.macroblock*, int, [2 x [4 x [4 x [2 x int, int, long, long, int,
int, [4 x int], [4 x int], int, int, int, int, int, int, int, int, int, int,
int, int, int, int, int, int, int }
+ %struct.pix_pos = type { int, int, int, int, int, int }
+ %struct.storable_picture = type { uint, int, int, int, int, [50 x [6 x
[33 x long]]], [50 x [6 x [33 x long]]], [50 x [6 x [33 x long]]], [50 x [6 x
[33 x long]]], uint, int, int, int, int, int, int, int, short, int, int, int,
int, int, int, int, uint, uint, ushort**, ushort***, ubyte*, short**, sbyte***,
long***, long***, short, ubyte**, ubyte**, %struct.storable_picture*,
%struct.storable_picture*, %struct.storable_picture*, int, int, int, int, int,
int, int, int, int, int, int, int, int, [2 x int], int,
%struct.DecRefPicMarking_s*, int }
+ %struct.syntaxelement = type { int, int, int, int, int, uint, int, int,
void (int, int, int*, int*)*, void (%struct.syntaxelement*, %struct.inp_par*,
%struct.img_par*, %typedef.DecodingEnvironment*)* }
+ %struct.timeb = type { int, ushort, short, short }
+ %typedef.BiContextType = type { ushort, ubyte }
+ %typedef.Bitstream = type { int, int, int, int, ubyte*, int }
+ %typedef.DecodingEnvironment = type { uint, uint, uint, uint, int,
ubyte*, int* }
+ %typedef.MotionInfoContexts = type { [4 x [11 x
%typedef.BiContextType]], [2 x [9 x %typedef.BiContextType]], [2 x [10 x
%typedef.BiContextType]], [2 x [6 x %typedef.BiContextType]], [4 x
%typedef.BiContextType], [4 x %typedef.BiContextType], [3 x
%typedef.BiContextType] }
+ %typedef.Slice = type { int, int, int, int, uint, int, int, int, int,
%struct.datapartition*, %typedef.MotionInfoContexts*,
%typedef.TextureInfoContexts*, int, int*, int*, int*, int, int*, int*, int*,
int (%struct.img_par*, %struct.inp_par*)*, int, int, int, int }
+ %typedef.TextureInfoContexts = type { [2 x %typedef.BiContextType], [4
x %typedef.BiContextType], [3 x [4 x %typedef.BiContextType]], [10 x [4 x
%typedef.BiContextType]], [10 x [15 x %typedef.BiContextType]], [10 x [15 x
%typedef.BiContextType]], [10 x [5 x %typedef.BiContextType]], [10 x [5 x
%typedef.BiContextType]], [10 x [15 x %typedef.BiContextType]], [10 x [15 x
%typedef.BiContextType]] }
+ %dec_picture = external global %struct.storable_picture* ;
<%struct.storable_picture**> [#uses=1]
+ %last_dquant = external global int; [#uses=1]
+
+ implementation ; Functions:
+
+ void %readCBP_CABAC(%struct.syntaxelement* %se, %struct.inp_par* %inp,
%struct.img_par* %img.1, %typedef.DecodingEnvironment* %dep_dp) {
+ entry:
+ %block_a = alloca %struct.pix_pos ; <%struct.pix_pos*>
[#uses=5]
+ %tmp.1 = getelementptr %struct.img_par* %img.1, int 0, uint 37
; <
[llvm-commits] CVS: llvm/lib/Transforms/Scalar/InstructionCombining.cpp
Changes in directory llvm/lib/Transforms/Scalar:
InstructionCombining.cpp updated: 1.457 -> 1.458
---
Log message:
Fix InstCombine/2006-04-01-InfLoop.ll
---
Diffs of the changes: (+2 -1)
InstructionCombining.cpp |3 ++-
1 files changed, 2 insertions(+), 1 deletion(-)
Index: llvm/lib/Transforms/Scalar/InstructionCombining.cpp
diff -u llvm/lib/Transforms/Scalar/InstructionCombining.cpp:1.457
llvm/lib/Transforms/Scalar/InstructionCombining.cpp:1.458
--- llvm/lib/Transforms/Scalar/InstructionCombining.cpp:1.457 Sat Apr 1
02:03:55 2006
+++ llvm/lib/Transforms/Scalar/InstructionCombining.cpp Sat Apr 1 16:05:01 2006
@@ -3008,7 +3008,8 @@
} else if (Op0I->getOpcode() == Instruction::And && Op0I->hasOneUse()) {
if (Op0I->getOperand(0) == Op1) // (A&B)^A ->
(B&A)^A
Op0I->swapOperands();
- if (Op0I->getOperand(1) == Op1) {// (B&A)^A == ~B & A
+ if (Op0I->getOperand(1) == Op1 &&// (B&A)^A == ~B & A
+ !isa(Op1)) { // Canonical form is (B&C)^C
Instruction *N = BinaryOperator::createNot(Op0I->getOperand(0), "tmp");
InsertNewInstBefore(N, I);
return BinaryOperator::createAnd(N, Op1);
___
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[llvm-commits] CVS: llvm/lib/Target/PowerPC/PPCInstrAltivec.td
Changes in directory llvm/lib/Target/PowerPC: PPCInstrAltivec.td updated: 1.29 -> 1.30 --- Log message: Implement vnot using VNOR instead of using 'vspltisb v0, -1' and vxor --- Diffs of the changes: (+4 -0) PPCInstrAltivec.td |4 1 files changed, 4 insertions(+) Index: llvm/lib/Target/PowerPC/PPCInstrAltivec.td diff -u llvm/lib/Target/PowerPC/PPCInstrAltivec.td:1.29 llvm/lib/Target/PowerPC/PPCInstrAltivec.td:1.30 --- llvm/lib/Target/PowerPC/PPCInstrAltivec.td:1.29 Fri Mar 31 16:41:56 2006 +++ llvm/lib/Target/PowerPC/PPCInstrAltivec.td Sat Apr 1 16:41:47 2006 @@ -445,6 +445,10 @@ def : Pat<(v4i32 vecspltisw:$invec), (v4i32 (VSPLTISW vecspltisw:$invec))>; // Logical Operations +def : Pat<(v16i8 (vnot VRRC:$vA)), (v16i8 (VNOR VRRC:$vA, VRRC:$vA))>; +def : Pat<(v8i16 (vnot VRRC:$vA)), (v8i16 (VNOR VRRC:$vA, VRRC:$vA))>; +def : Pat<(v4i32 (vnot VRRC:$vA)), (v4i32 (VNOR VRRC:$vA, VRRC:$vA))>; + def : Pat<(v16i8 (and VRRC:$A, VRRC:$B)), (v16i8 (VAND VRRC:$A, VRRC:$B))>; def : Pat<(v8i16 (and VRRC:$A, VRRC:$B)), (v8i16 (VAND VRRC:$A, VRRC:$B))>; def : Pat<(v16i8 (or VRRC:$A, VRRC:$B)), (v16i8 (VOR VRRC:$A, VRRC:$B))>; ___ llvm-commits mailing list llvm-commits@cs.uiuc.edu http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
[llvm-commits] CVS: llvm/lib/Transforms/Utils/ValueMapper.cpp
Changes in directory llvm/lib/Transforms/Utils:
ValueMapper.cpp updated: 1.22 -> 1.23
---
Log message:
add valuemapper support for inline asm
---
Diffs of the changes: (+1 -1)
ValueMapper.cpp |2 +-
1 files changed, 1 insertion(+), 1 deletion(-)
Index: llvm/lib/Transforms/Utils/ValueMapper.cpp
diff -u llvm/lib/Transforms/Utils/ValueMapper.cpp:1.22
llvm/lib/Transforms/Utils/ValueMapper.cpp:1.23
--- llvm/lib/Transforms/Utils/ValueMapper.cpp:1.22 Sun Mar 26 23:50:18 2006
+++ llvm/lib/Transforms/Utils/ValueMapper.cpp Sat Apr 1 17:17:11 2006
@@ -24,7 +24,7 @@
// Global values do not need to be seeded into the ValueMap if they are using
// the identity mapping.
- if (isa(V))
+ if (isa(V) || isa(V))
return VMSlot = const_cast(V);
if (Constant *C = const_cast(dyn_cast(V))) {
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[llvm-commits] CVS: llvm/test/Regression/CodeGen/PowerPC/2006-04-01-FloatDoubleExtend.ll
Changes in directory llvm/test/Regression/CodeGen/PowerPC:
2006-04-01-FloatDoubleExtend.ll added (r1.1)
---
Log message:
New testcase that crashes the compiler.
---
Diffs of the changes: (+7 -0)
2006-04-01-FloatDoubleExtend.ll |7 +++
1 files changed, 7 insertions(+)
Index: llvm/test/Regression/CodeGen/PowerPC/2006-04-01-FloatDoubleExtend.ll
diff -c /dev/null
llvm/test/Regression/CodeGen/PowerPC/2006-04-01-FloatDoubleExtend.ll:1.1
*** /dev/null Sat Apr 1 18:24:09 2006
--- llvm/test/Regression/CodeGen/PowerPC/2006-04-01-FloatDoubleExtend.ll
Sat Apr 1 18:23:59 2006
***
*** 0
--- 1,7
+ ; RUN: llvm-as < %s | llc -march=ppc32
+
+ double %CalcSpeed(float %tmp127) {
+ %tmp145 = cast float %tmp127 to double ; [#uses=1]
+ %tmp150 = call double asm "frsqrte $0,$1", "=f,f"( double %tmp145 )
; [#uses=0]
+ ret double %tmp150
+ }
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[llvm-commits] CVS: llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
Changes in directory llvm/lib/CodeGen/SelectionDAG:
SelectionDAGISel.cpp updated: 1.214 -> 1.215
---
Log message:
Prefer larger register classes over smaller ones when a register occurs in
multiple register classes. This fixes PowerPC/2006-04-01-FloatDoubleExtend.ll
---
Diffs of the changes: (+21 -7)
SelectionDAGISel.cpp | 28 +---
1 files changed, 21 insertions(+), 7 deletions(-)
Index: llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
diff -u llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp:1.214
llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp:1.215
--- llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp:1.214Thu Mar 30
20:12:18 2006
+++ llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp Sat Apr 1 18:24:45 2006
@@ -1663,21 +1663,30 @@
static const TargetRegisterClass *
isAllocatableRegister(unsigned Reg, MachineFunction &MF,
const TargetLowering &TLI, const MRegisterInfo *MRI) {
+ MVT::ValueType FoundVT = MVT::Other;
+ const TargetRegisterClass *FoundRC = 0;
for (MRegisterInfo::regclass_iterator RCI = MRI->regclass_begin(),
E = MRI->regclass_end(); RCI != E; ++RCI) {
+MVT::ValueType ThisVT = MVT::Other;
+
const TargetRegisterClass *RC = *RCI;
// If none of the the value types for this register class are valid, we
// can't use it. For example, 64-bit reg classes on 32-bit targets.
-bool isLegal = false;
for (TargetRegisterClass::vt_iterator I = RC->vt_begin(), E = RC->vt_end();
I != E; ++I) {
if (TLI.isTypeLegal(*I)) {
-isLegal = true;
-break;
+// If we have already found this register in a different register
class,
+// choose the one with the largest VT specified. For example, on
+// PowerPC, we favor f64 register classes over f32.
+if (FoundVT == MVT::Other ||
+MVT::getSizeInBits(FoundVT) < MVT::getSizeInBits(*I)) {
+ ThisVT = *I;
+ break;
+}
}
}
-if (!isLegal) continue;
+if (ThisVT == MVT::Other) continue;
// NOTE: This isn't ideal. In particular, this might allocate the
// frame pointer in functions that need it (due to them not being taken
@@ -1685,10 +1694,15 @@
// yet). This is a slight code pessimization, but should still work.
for (TargetRegisterClass::iterator I = RC->allocation_order_begin(MF),
E = RC->allocation_order_end(MF); I != E; ++I)
- if (*I == Reg)
-return RC;
+ if (*I == Reg) {
+// We found a matching register class. Keep looking at others in case
+// we find one with larger registers that this physreg is also in.
+FoundRC = RC;
+FoundVT = ThisVT;
+break;
+ }
}
- return 0;
+ return FoundRC;
}
RegsForValue SelectionDAGLowering::
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[llvm-commits] CVS: llvm/lib/Target/PowerPC/PPCISelLowering.cpp
Changes in directory llvm/lib/Target/PowerPC: PPCISelLowering.cpp updated: 1.124 -> 1.125 --- Log message: Custom lower all BUILD_VECTOR's so that we can compile vec_splat_u8(8) into "vspltisb v0, 8" instead of a constant pool load. --- Diffs of the changes: (+2 -0) PPCISelLowering.cpp |2 ++ 1 files changed, 2 insertions(+) Index: llvm/lib/Target/PowerPC/PPCISelLowering.cpp diff -u llvm/lib/Target/PowerPC/PPCISelLowering.cpp:1.124 llvm/lib/Target/PowerPC/PPCISelLowering.cpp:1.125 --- llvm/lib/Target/PowerPC/PPCISelLowering.cpp:1.124 Fri Mar 31 13:52:36 2006 +++ llvm/lib/Target/PowerPC/PPCISelLowering.cpp Sat Apr 1 18:43:36 2006 @@ -204,6 +204,8 @@ setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v4f32, Custom); setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v4i32, Custom); +setOperationAction(ISD::BUILD_VECTOR, MVT::v16i8, Custom); +setOperationAction(ISD::BUILD_VECTOR, MVT::v8i16, Custom); setOperationAction(ISD::BUILD_VECTOR, MVT::v4i32, Custom); setOperationAction(ISD::BUILD_VECTOR, MVT::v4f32, Custom); } ___ llvm-commits mailing list llvm-commits@cs.uiuc.edu http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
[llvm-commits] CVS: llvm/lib/VMCore/ConstantFolding.cpp
Changes in directory llvm/lib/VMCore:
ConstantFolding.cpp updated: 1.84 -> 1.85
---
Log message:
Constant fold casts from things like <4 x int> -> <4 x uint>, likewise int<->fp.
---
Diffs of the changes: (+108 -0)
ConstantFolding.cpp | 108
1 files changed, 108 insertions(+)
Index: llvm/lib/VMCore/ConstantFolding.cpp
diff -u llvm/lib/VMCore/ConstantFolding.cpp:1.84
llvm/lib/VMCore/ConstantFolding.cpp:1.85
--- llvm/lib/VMCore/ConstantFolding.cpp:1.84Fri Mar 31 12:31:40 2006
+++ llvm/lib/VMCore/ConstantFolding.cpp Sat Apr 1 19:38:28 2006
@@ -24,6 +24,7 @@
#include "llvm/DerivedTypes.h"
#include "llvm/Function.h"
#include "llvm/Support/GetElementPtrTypeIterator.h"
+#include "llvm/Support/MathExtras.h"
#include
#include
using namespace llvm;
@@ -621,6 +622,81 @@
return S ? S : 8; // Treat pointers at 8 bytes
}
+/// CastConstantPacked - Convert the specified ConstantPacked node to the
+/// specified packed type. At this point, we know that the elements of the
+/// input packed constant are all simple integer or FP values.
+static Constant *CastConstantPacked(ConstantPacked *CP,
+const PackedType *DstTy) {
+ unsigned SrcNumElts = CP->getType()->getNumElements();
+ unsigned DstNumElts = DstTy->getNumElements();
+ const Type *SrcEltTy = CP->getType()->getElementType();
+ const Type *DstEltTy = DstTy->getElementType();
+
+ // If both vectors have the same number of elements (thus, the elements
+ // are the same size), perform the conversion now.
+ if (SrcNumElts == DstNumElts) {
+std::vector Result;
+
+// If the src and dest elements are both integers, just cast each one
+// which will do the appropriate bit-convert.
+if (SrcEltTy->isIntegral() && DstEltTy->isIntegral()) {
+ for (unsigned i = 0; i != SrcNumElts; ++i)
+Result.push_back(ConstantExpr::getCast(CP->getOperand(i),
+ DstEltTy));
+ return ConstantPacked::get(Result);
+}
+
+if (SrcEltTy->isIntegral()) {
+ // Otherwise, this is an int-to-fp cast.
+ assert(DstEltTy->isFloatingPoint());
+ if (DstEltTy->getTypeID() == Type::DoubleTyID) {
+for (unsigned i = 0; i != SrcNumElts; ++i) {
+ double V =
+BitsToDouble(cast(CP->getOperand(i))->getRawValue());
+ Result.push_back(ConstantFP::get(Type::DoubleTy, V));
+}
+return ConstantPacked::get(Result);
+ }
+ assert(DstEltTy == Type::FloatTy && "Unknown fp type!");
+ for (unsigned i = 0; i != SrcNumElts; ++i) {
+float V =
+BitsToFloat(cast(CP->getOperand(i))->getRawValue());
+Result.push_back(ConstantFP::get(Type::FloatTy, V));
+ }
+ return ConstantPacked::get(Result);
+}
+
+// Otherwise, this is an fp-to-int cast.
+assert(SrcEltTy->isFloatingPoint() && DstEltTy->isIntegral());
+
+if (SrcEltTy->getTypeID() == Type::DoubleTyID) {
+ for (unsigned i = 0; i != SrcNumElts; ++i) {
+uint64_t V =
+ DoubleToBits(cast(CP->getOperand(i))->getValue());
+Constant *C = ConstantUInt::get(Type::ULongTy, V);
+Result.push_back(ConstantExpr::getCast(C, DstEltTy));
+ }
+ return ConstantPacked::get(Result);
+}
+
+assert(SrcEltTy->getTypeID() == Type::FloatTyID);
+for (unsigned i = 0; i != SrcNumElts; ++i) {
+ unsigned V =
FloatToBits(cast(CP->getOperand(i))->getValue());
+ Constant *C = ConstantUInt::get(Type::UIntTy, V);
+ Result.push_back(ConstantExpr::getCast(C, DstEltTy));
+}
+return ConstantPacked::get(Result);
+ }
+
+ // Otherwise, this is a cast that changes element count and size. Handle
+ // casts which shrink the elements here.
+
+ // FIXME: We need to know endianness to do this!
+
+ return 0;
+}
+
+
Constant *llvm::ConstantFoldCastInstruction(const Constant *V,
const Type *DestTy) {
if (V->getType() == DestTy) return (Constant*)V;
@@ -688,6 +764,38 @@
if (ElTy == DPTy->getElementType())
return
ConstantExpr::getGetElementPtr(const_cast(V),IdxList);
}
+
+ // Handle casts from one packed constant to another. We know that the src
and
+ // dest type have the same size.
+ if (const PackedType *DestPTy = dyn_cast(DestTy)) {
+if (const PackedType *SrcTy = dyn_cast(V->getType())) {
+ assert(DestPTy->getElementType()->getPrimitiveSizeInBits() *
+ DestPTy->getNumElements() ==
+ SrcTy->getElementType()->getPrimitiveSizeInBits() *
+ SrcTy->getNumElements() && "Not cast between same sized
vectors!");
+ if (isa(V))
+return Constant::getNullValue(DestTy);
+ if (isa(V))
+return UndefValue::get(DestTy);
+ if (const ConstantPacked *CP = dyn_cast(V)) {
+// This is a cast from a ConstantPacked of one type to a ConstantPacke
[llvm-commits] CVS: llvm/lib/Target/README.txt
Changes in directory llvm/lib/Target: README.txt updated: 1.27 -> 1.28 --- Log message: New note --- Diffs of the changes: (+6 -0) README.txt |6 ++ 1 files changed, 6 insertions(+) Index: llvm/lib/Target/README.txt diff -u llvm/lib/Target/README.txt:1.27 llvm/lib/Target/README.txt:1.28 --- llvm/lib/Target/README.txt:1.27 Fri Mar 31 22:08:29 2006 +++ llvm/lib/Target/README.txt Sat Apr 1 19:47:20 2006 @@ -166,3 +166,9 @@ //===-===// +We should constant fold packed type casts at the LLVM level, regardless of the +cast. Currently we cannot fold some casts because we don't have TargetData +information in the constant folder, so we don't know the endianness of the +target! + +//===-===// ___ llvm-commits mailing list llvm-commits@cs.uiuc.edu http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
[llvm-commits] CVS: llvm/include/llvm/CodeGen/SelectionDAGNodes.h
Changes in directory llvm/include/llvm/CodeGen:
SelectionDAGNodes.h updated: 1.125 -> 1.126
---
Log message:
simplify this method
---
Diffs of the changes: (+1 -3)
SelectionDAGNodes.h |4 +---
1 files changed, 1 insertion(+), 3 deletions(-)
Index: llvm/include/llvm/CodeGen/SelectionDAGNodes.h
diff -u llvm/include/llvm/CodeGen/SelectionDAGNodes.h:1.125
llvm/include/llvm/CodeGen/SelectionDAGNodes.h:1.126
--- llvm/include/llvm/CodeGen/SelectionDAGNodes.h:1.125 Tue Mar 28 13:54:11 2006
+++ llvm/include/llvm/CodeGen/SelectionDAGNodes.h Sat Apr 1 20:28:52 2006
@@ -1076,9 +1076,7 @@
bool isNullValue() const { return Value == 0; }
bool isAllOnesValue() const {
-int NumBits = MVT::getSizeInBits(getValueType(0));
-if (NumBits == 64) return Value+1 == 0;
-return Value == (1ULL << NumBits)-1;
+return Value == MVT::getIntVTBitMask(getValueType(0));
}
static bool classof(const ConstantSDNode *) { return true; }
___
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[llvm-commits] CVS: llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
Changes in directory llvm/lib/CodeGen/SelectionDAG: SelectionDAG.cpp updated: 1.293 -> 1.294 --- Log message: Add some missing node names --- Diffs of the changes: (+9 -0) SelectionDAG.cpp |9 + 1 files changed, 9 insertions(+) Index: llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp diff -u llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp:1.293 llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp:1.294 --- llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp:1.293Thu Mar 30 20:06:56 2006 +++ llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp Sat Apr 1 20:41:18 2006 @@ -2749,6 +2749,15 @@ case ISD::VADD: return "vadd"; case ISD::VSUB: return "vsub"; case ISD::VMUL: return "vmul"; + + case ISD::VADD: return "vadd"; + case ISD::VSUB: return "vsub"; + case ISD::VMUL: return "vmul"; + case ISD::VSDIV: return "vsdiv"; + case ISD::VUDIV: return "vudiv"; + case ISD::VAND: return "vand"; + case ISD::VOR:return "vor"; + case ISD::VXOR: return "vxor"; case ISD::SETCC: return "setcc"; case ISD::SELECT: return "select"; ___ llvm-commits mailing list llvm-commits@cs.uiuc.edu http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
[llvm-commits] CVS: llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
Changes in directory llvm/lib/CodeGen/SelectionDAG: SelectionDAG.cpp updated: 1.294 -> 1.295 --- Log message: These entries already exist --- Diffs of the changes: (+0 -4) SelectionDAG.cpp |4 1 files changed, 4 deletions(-) Index: llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp diff -u llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp:1.294 llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp:1.295 --- llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp:1.294Sat Apr 1 20:41:18 2006 +++ llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp Sat Apr 1 20:51:27 2006 @@ -2749,10 +2749,6 @@ case ISD::VADD: return "vadd"; case ISD::VSUB: return "vsub"; case ISD::VMUL: return "vmul"; - - case ISD::VADD: return "vadd"; - case ISD::VSUB: return "vsub"; - case ISD::VMUL: return "vmul"; case ISD::VSDIV: return "vsdiv"; case ISD::VUDIV: return "vudiv"; case ISD::VAND: return "vand"; ___ llvm-commits mailing list llvm-commits@cs.uiuc.edu http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
[llvm-commits] CVS: llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
Changes in directory llvm/lib/CodeGen/SelectionDAG:
DAGCombiner.cpp updated: 1.136 -> 1.137
---
Log message:
Implement constant folding of bit_convert of arbitrary constant vbuild_vector
nodes.
---
Diffs of the changes: (+139 -2)
DAGCombiner.cpp | 141 +++-
1 files changed, 139 insertions(+), 2 deletions(-)
Index: llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
diff -u llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp:1.136
llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp:1.137
--- llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp:1.136 Fri Mar 31 16:16:43 2006
+++ llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp Sat Apr 1 20:53:43 2006
@@ -190,6 +190,7 @@
SDOperand visitSIGN_EXTEND_INREG(SDNode *N);
SDOperand visitTRUNCATE(SDNode *N);
SDOperand visitBIT_CONVERT(SDNode *N);
+SDOperand visitVBIT_CONVERT(SDNode *N);
SDOperand visitFADD(SDNode *N);
SDOperand visitFSUB(SDNode *N);
SDOperand visitFMUL(SDNode *N);
@@ -224,7 +225,7 @@
SDOperand N3, ISD::CondCode CC);
SDOperand SimplifySetCC(MVT::ValueType VT, SDOperand N0, SDOperand N1,
ISD::CondCode Cond, bool foldBooleans = true);
-
+SDOperand ConstantFoldVBIT_CONVERTofVBUILD_VECTOR(SDNode *,
MVT::ValueType);
SDOperand BuildSDIV(SDNode *N);
SDOperand BuildUDIV(SDNode *N);
public:
@@ -627,6 +628,7 @@
case ISD::SIGN_EXTEND_INREG: return visitSIGN_EXTEND_INREG(N);
case ISD::TRUNCATE: return visitTRUNCATE(N);
case ISD::BIT_CONVERT:return visitBIT_CONVERT(N);
+ case ISD::VBIT_CONVERT: return visitVBIT_CONVERT(N);
case ISD::FADD: return visitFADD(N);
case ISD::FSUB: return visitFSUB(N);
case ISD::FMUL: return visitFMUL(N);
@@ -1940,7 +1942,7 @@
if (N0.getOpcode() == ISD::BIT_CONVERT) // conv(conv(x,t1),t2) -> conv(x,t2)
return DAG.getNode(ISD::BIT_CONVERT, VT, N0.getOperand(0));
-
+
// fold (conv (load x)) -> (load (conv*)x)
// FIXME: These xforms need to know that the resultant load doesn't need a
// higher alignment than the original!
@@ -1956,6 +1958,141 @@
return SDOperand();
}
+SDOperand DAGCombiner::visitVBIT_CONVERT(SDNode *N) {
+ SDOperand N0 = N->getOperand(0);
+ MVT::ValueType VT = N->getValueType(0);
+
+ // If the input is a VBUILD_VECTOR with all constant elements, fold this now.
+ // First check to see if this is all constant.
+ if (N0.getOpcode() == ISD::VBUILD_VECTOR && N0.Val->hasOneUse() &&
+ VT == MVT::Vector) {
+bool isSimple = true;
+for (unsigned i = 0, e = N0.getNumOperands()-2; i != e; ++i)
+ if (N0.getOperand(i).getOpcode() != ISD::UNDEF &&
+ N0.getOperand(i).getOpcode() != ISD::Constant &&
+ N0.getOperand(i).getOpcode() != ISD::ConstantFP) {
+isSimple = false;
+break;
+ }
+
+if (isSimple) {
+ MVT::ValueType DestEltVT = cast(N->getOperand(2))->getVT();
+ return ConstantFoldVBIT_CONVERTofVBUILD_VECTOR(N0.Val, DestEltVT);
+}
+ }
+
+ return SDOperand();
+}
+
+/// ConstantFoldVBIT_CONVERTofVBUILD_VECTOR - We know that BV is a
vbuild_vector
+/// node with Constant, ConstantFP or Undef operands. DstEltVT indicates the
+/// destination element value type.
+SDOperand DAGCombiner::
+ConstantFoldVBIT_CONVERTofVBUILD_VECTOR(SDNode *BV, MVT::ValueType DstEltVT) {
+ MVT::ValueType SrcEltVT = BV->getOperand(0).getValueType();
+
+ // If this is already the right type, we're done.
+ if (SrcEltVT == DstEltVT) return SDOperand(BV, 0);
+
+ unsigned SrcBitSize = MVT::getSizeInBits(SrcEltVT);
+ unsigned DstBitSize = MVT::getSizeInBits(DstEltVT);
+
+ // If this is a conversion of N elements of one type to N elements of another
+ // type, convert each element. This handles FP<->INT cases.
+ if (SrcBitSize == DstBitSize) {
+std::vector Ops;
+for (unsigned i = 0, e = BV->getNumOperands()-2; i != e; ++i)
+ Ops.push_back(DAG.getNode(ISD::BIT_CONVERT, DstEltVT,
BV->getOperand(i)));
+Ops.push_back(*(BV->op_end()-2)); // Add num elements.
+Ops.push_back(DAG.getValueType(DstEltVT));
+return DAG.getNode(ISD::VBUILD_VECTOR, MVT::Vector, Ops);
+ }
+
+ // Otherwise, we're growing or shrinking the elements. To avoid having to
+ // handle annoying details of growing/shrinking FP values, we convert them to
+ // int first.
+ if (MVT::isFloatingPoint(SrcEltVT)) {
+// Convert the input float vector to a int vector where the elements are
the
+// same sizes.
+assert((SrcEltVT == MVT::f32 || SrcEltVT == MVT::f64) && "Unknown FP VT!");
+MVT::ValueType IntVT = SrcEltVT == MVT::f32 ? MVT::i32 : MVT::i64;
+BV = ConstantFoldVBIT_CONVERTofVBUILD_VECTOR(BV, IntVT).Val;
+SrcEltVT = IntVT;
+ }
+
+ // Now we know the input is an integer vector. If the output is a FP type,
+ // convert to integer first, then to FP of the right size.
[llvm-commits] CVS: llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp SelectionDAGISel.cpp
Changes in directory llvm/lib/CodeGen/SelectionDAG:
LegalizeDAG.cpp updated: 1.348 -> 1.349
SelectionDAGISel.cpp updated: 1.215 -> 1.216
---
Log message:
Add a new -view-legalize-dags command line option
---
Diffs of the changes: (+13 -3)
LegalizeDAG.cpp | 13 -
SelectionDAGISel.cpp |3 +--
2 files changed, 13 insertions(+), 3 deletions(-)
Index: llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
diff -u llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp:1.348
llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp:1.349
--- llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp:1.348 Fri Mar 31 12:22:37 2006
+++ llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp Sat Apr 1 21:07:27 2006
@@ -14,16 +14,25 @@
#include "llvm/CodeGen/SelectionDAG.h"
#include "llvm/CodeGen/MachineFunction.h"
#include "llvm/CodeGen/MachineFrameInfo.h"
-#include "llvm/Support/MathExtras.h"
#include "llvm/Target/TargetLowering.h"
#include "llvm/Target/TargetData.h"
#include "llvm/Target/TargetOptions.h"
#include "llvm/CallingConv.h"
#include "llvm/Constants.h"
+#include "llvm/Support/MathExtras.h"
+#include "llvm/Support/CommandLine.h"
#include
#include
using namespace llvm;
+#ifndef NDEBUG
+static cl::opt
+ViewLegalizeDAGs("view-legalize-dags", cl::Hidden,
+ cl::desc("Pop up a window to show dags before legalize"));
+#else
+static const bool ViewLegalizeDAGs = 0;
+#endif
+
//===--===//
/// SelectionDAGLegalize - This takes an arbitrary SelectionDAG as input and
/// hacks on it until the target machine can handle it. This involves
@@ -4628,6 +4637,8 @@
// SelectionDAG::Legalize - This is the entry point for the file.
//
void SelectionDAG::Legalize() {
+ if (ViewLegalizeDAGs) viewGraph();
+
/// run - This is the main entry point to this class.
///
SelectionDAGLegalize(*this).LegalizeDAG();
Index: llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
diff -u llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp:1.215
llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp:1.216
--- llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp:1.215Sat Apr 1
18:24:45 2006
+++ llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp Sat Apr 1 21:07:27 2006
@@ -54,8 +54,7 @@
ViewSchedDAGs("view-sched-dags", cl::Hidden,
cl::desc("Pop up a window to show sched dags as they are
processed"));
#else
-static const bool ViewISelDAGs = 0;
-static const bool ViewSchedDAGs = 0;
+static const bool ViewISelDAGs = 0, ViewSchedDAGs = 0;
#endif
// Scheduling heuristics
___
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[llvm-commits] CVS: llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
Changes in directory llvm/lib/CodeGen/SelectionDAG:
DAGCombiner.cpp updated: 1.137 -> 1.138
---
Log message:
Constant fold all of the vector binops. This allows us to compile this:
"vector unsigned char mergeLowHigh = (vector unsigned char)
( 8, 9, 10, 11, 16, 17, 18, 19, 12, 13, 14, 15, 20, 21, 22, 23 );
vector unsigned char mergeHighLow = vec_xor( mergeLowHigh, vec_splat_u8(8));"
aka:
void %test2(<16 x sbyte>* %P) {
store <16 x sbyte> cast (<4 x int> xor (<4 x int> cast (<16 x ubyte> < ubyte
8, ubyte 9, ubyte 10, ubyte 11, ubyte 16, ubyte 17, ubyte 18, ubyte 19, ubyte
12, ubyte 13, ubyte 14, ubyte 15, ubyte 20, ubyte 21, ubyte 22, ubyte 23 > to
<4 x int>), <4 x int> cast (<16 x sbyte> < sbyte 8, sbyte 8, sbyte 8, sbyte 8,
sbyte 8, sbyte 8, sbyte 8, sbyte 8, sbyte 8, sbyte 8, sbyte 8, sbyte 8, sbyte
8, sbyte 8, sbyte 8, sbyte 8 > to <4 x int>)) to <16 x sbyte>), <16 x sbyte> *
%P
ret void
}
into this:
_test2:
mfspr r2, 256
oris r4, r2, 32768
mtspr 256: http://llvm.cs.uiuc.edu/PR256 , r4
li r4, lo16(LCPI2_0)
lis r5, ha16(LCPI2_0)
lvx v0, r5, r4
stvx v0, 0, r3
mtspr 256: http://llvm.cs.uiuc.edu/PR256 , r2
blr
instead of this:
_test2:
mfspr r2, 256
oris r4, r2, 49152
mtspr 256: http://llvm.cs.uiuc.edu/PR256 , r4
li r4, lo16(LCPI2_0)
lis r5, ha16(LCPI2_0)
vspltisb v0, 8
lvx v1, r5, r4
vxor v0, v1, v0
stvx v0, 0, r3
mtspr 256: http://llvm.cs.uiuc.edu/PR256 , r2
blr
... which occurs here:
http://developer.apple.com/hardware/ve/calcspeed.html
---
Diffs of the changes: (+49 -0)
DAGCombiner.cpp | 49 +
1 files changed, 49 insertions(+)
Index: llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
diff -u llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp:1.137
llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp:1.138
--- llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp:1.137 Sat Apr 1 20:53:43 2006
+++ llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp Sat Apr 1 21:25:57 2006
@@ -176,6 +176,7 @@
SDOperand visitAND(SDNode *N);
SDOperand visitOR(SDNode *N);
SDOperand visitXOR(SDNode *N);
+SDOperand visitVBinOp(SDNode *N, ISD::NodeType IntOp, ISD::NodeType FPOp);
SDOperand visitSHL(SDNode *N);
SDOperand visitSRA(SDNode *N);
SDOperand visitSRL(SDNode *N);
@@ -656,6 +657,14 @@
case ISD::VBUILD_VECTOR: return visitVBUILD_VECTOR(N);
case ISD::VECTOR_SHUFFLE: return visitVECTOR_SHUFFLE(N);
case ISD::VVECTOR_SHUFFLE:return visitVVECTOR_SHUFFLE(N);
+ case ISD::VADD: return visitVBinOp(N, ISD::ADD , ISD::FADD);
+ case ISD::VSUB: return visitVBinOp(N, ISD::SUB , ISD::FSUB);
+ case ISD::VMUL: return visitVBinOp(N, ISD::MUL , ISD::FMUL);
+ case ISD::VSDIV: return visitVBinOp(N, ISD::SDIV, ISD::FDIV);
+ case ISD::VUDIV: return visitVBinOp(N, ISD::UDIV, ISD::UDIV);
+ case ISD::VAND: return visitVBinOp(N, ISD::AND , ISD::AND);
+ case ISD::VOR:return visitVBinOp(N, ISD::OR , ISD::OR);
+ case ISD::VXOR: return visitVBinOp(N, ISD::XOR , ISD::XOR);
}
return SDOperand();
}
@@ -2682,6 +2691,46 @@
return SDOperand();
}
+/// visitVBinOp - Visit a binary vector operation, like VADD. IntOp indicates
+/// the scalar operation of the vop if it is operating on an integer vector
+/// (e.g. ADD) and FPOp indicates the FP version (e.g. FADD).
+SDOperand DAGCombiner::visitVBinOp(SDNode *N, ISD::NodeType IntOp,
+ ISD::NodeType FPOp) {
+ MVT::ValueType EltType = cast(*(N->op_end()-1))->getVT();
+ ISD::NodeType ScalarOp = MVT::isInteger(EltType) ? IntOp : FPOp;
+ SDOperand LHS = N->getOperand(0);
+ SDOperand RHS = N->getOperand(1);
+
+ // If the LHS and RHS are VBUILD_VECTOR nodes, see if we can constant fold
+ // this operation.
+ if (LHS.getOpcode() == ISD::VBUILD_VECTOR &&
+ RHS.getOpcode() == ISD::VBUILD_VECTOR) {
+std::vector Ops;
+for (unsigned i = 0, e = LHS.getNumOperands()-2; i != e; ++i) {
+ SDOperand LHSOp = LHS.getOperand(i);
+ SDOperand RHSOp = RHS.getOperand(i);
+ // If these two elements can't be folded, bail out.
+ if ((LHSOp.getOpcode() != ISD::UNDEF &&
+ LHSOp.getOpcode() != ISD::Constant &&
+ LHSOp.getOpcode() != ISD::ConstantFP) ||
+ (RHSOp.getOpcode() != ISD::UNDEF &&
+ RHSOp.getOpcode() != ISD::Constant &&
+ RHSOp.getOpcode() != ISD::ConstantFP))
+break;
+ Ops.push_back(DAG.getNode(ScalarOp, EltType, LHSOp, RHSOp));
+ assert((Ops.back().getOpcode() == ISD::UNDEF ||
+ Ops.back().getOpcode() == ISD::Constant ||
+ Ops.back().getOpcode() == ISD::ConstantFP) &&
+ "Scalar binop didn't fold!");
+}
+Ops.push_back(*(LHS.Val->op_end()-2));
+
[llvm-commits] CVS: llvm/utils/TableGen/IntrinsicEmitter.cpp
Changes in directory llvm/utils/TableGen:
IntrinsicEmitter.cpp updated: 1.19 -> 1.20
---
Log message:
Adjust the Intrinsics.gen interface a little bit
---
Diffs of the changes: (+2 -2)
IntrinsicEmitter.cpp |4 ++--
1 files changed, 2 insertions(+), 2 deletions(-)
Index: llvm/utils/TableGen/IntrinsicEmitter.cpp
diff -u llvm/utils/TableGen/IntrinsicEmitter.cpp:1.19
llvm/utils/TableGen/IntrinsicEmitter.cpp:1.20
--- llvm/utils/TableGen/IntrinsicEmitter.cpp:1.19 Thu Mar 30 22:48:26 2006
+++ llvm/utils/TableGen/IntrinsicEmitter.cppSat Apr 1 21:35:30 2006
@@ -214,9 +214,9 @@
void IntrinsicEmitter::
EmitSideEffectInfo(const std::vector &Ints, std::ostream
&OS){
- OS << "// isInstructionTriviallyDead code.\n";
+ OS << "// Return true if doesn't access or only reads memory.\n";
OS << "#ifdef GET_SIDE_EFFECT_INFO\n";
- OS << " switch (F->getIntrinsicID()) {\n";
+ OS << " switch (IntrinsicID) {\n";
OS << " default: break;\n";
for (unsigned i = 0, e = Ints.size(); i != e; ++i) {
switch (Ints[i].ModRef) {
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[llvm-commits] CVS: llvm/lib/Transforms/Utils/Local.cpp
Changes in directory llvm/lib/Transforms/Utils:
Local.cpp updated: 1.53 -> 1.54
---
Log message:
Adjust to change in Intrinsics.gen interface.
---
Diffs of the changes: (+1 -0)
Local.cpp |1 +
1 files changed, 1 insertion(+)
Index: llvm/lib/Transforms/Utils/Local.cpp
diff -u llvm/lib/Transforms/Utils/Local.cpp:1.53
llvm/lib/Transforms/Utils/Local.cpp:1.54
--- llvm/lib/Transforms/Utils/Local.cpp:1.53Thu Mar 9 16:38:10 2006
+++ llvm/lib/Transforms/Utils/Local.cpp Sat Apr 1 21:35:01 2006
@@ -308,6 +308,7 @@
if (CallInst *CI = dyn_cast(I))
if (Function *F = CI->getCalledFunction()) {
+ unsigned IntrinsicID = F->getIntrinsicID();
#define GET_SIDE_EFFECT_INFO
#include "llvm/Intrinsics.gen"
#undef GET_SIDE_EFFECT_INFO
___
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[llvm-commits] CVS: llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
Changes in directory llvm/lib/CodeGen/SelectionDAG:
SelectionDAGISel.cpp updated: 1.216 -> 1.217
---
Log message:
Intrinsics that just load from memory can be treated like loads: they don't
have to serialize against each other. This allows us to schedule lvx's
across each other, for example.
---
Diffs of the changes: (+25 -4)
SelectionDAGISel.cpp | 29 +
1 files changed, 25 insertions(+), 4 deletions(-)
Index: llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
diff -u llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp:1.216
llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp:1.217
--- llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp:1.216Sat Apr 1
21:07:27 2006
+++ llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp Sat Apr 1 21:41:14 2006
@@ -1236,16 +1236,32 @@
return false;
}
+// IntrinsicOnlyReadsMemory - Return true if the specified intrinsic doesn't
+// have any side-effects or if it only reads memory.
+static bool IntrinsicOnlyReadsMemory(unsigned IntrinsicID) {
+#define GET_SIDE_EFFECT_INFO
+#include "llvm/Intrinsics.gen"
+#undef GET_SIDE_EFFECT_INFO
+ return false;
+}
+
/// visitTargetIntrinsic - Lower a call of a target intrinsic to an INTRINSIC
/// node.
void SelectionDAGLowering::visitTargetIntrinsic(CallInst &I,
unsigned Intrinsic) {
bool HasChain = !IntrinsicCannotAccessMemory(Intrinsic);
+ bool OnlyLoad = HasChain && IntrinsicOnlyReadsMemory(Intrinsic);
// Build the operand list.
std::vector Ops;
- if (HasChain) // If this intrinsic has side-effects, chainify it.
-Ops.push_back(getRoot());
+ if (HasChain) { // If this intrinsic has side-effects, chainify it.
+if (OnlyLoad) {
+ // We don't need to serialize loads against other loads.
+ Ops.push_back(DAG.getRoot());
+} else {
+ Ops.push_back(getRoot());
+}
+ }
// Add the intrinsic ID as an integer operand.
Ops.push_back(DAG.getConstant(Intrinsic, TLI.getPointerTy()));
@@ -1295,8 +1311,13 @@
else
Result = DAG.getNode(ISD::INTRINSIC_VOID, VTs, Ops);
- if (HasChain)
-DAG.setRoot(Result.getValue(Result.Val->getNumValues()-1));
+ if (HasChain) {
+SDOperand Chain = Result.getValue(Result.Val->getNumValues()-1);
+if (OnlyLoad)
+ PendingLoads.push_back(Chain);
+else
+ DAG.setRoot(Chain);
+ }
if (I.getType() != Type::VoidTy) {
if (const PackedType *PTy = dyn_cast(I.getType())) {
MVT::ValueType EVT = TLI.getValueType(PTy->getElementType());
___
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[llvm-commits] CVS: llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
Changes in directory llvm/lib/CodeGen/SelectionDAG:
LegalizeDAG.cpp updated: 1.349 -> 1.350
---
Log message:
Implement the Expand action for binary vector operations to break the binop
into elements and operate on each piece. This allows generic vector integer
multiplies to work on PPC, though the generated code is horrible.
---
Diffs of the changes: (+18 -1)
LegalizeDAG.cpp | 19 ++-
1 files changed, 18 insertions(+), 1 deletion(-)
Index: llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
diff -u llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp:1.349
llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp:1.350
--- llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp:1.349 Sat Apr 1 21:07:27 2006
+++ llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp Sat Apr 1 21:57:31 2006
@@ -1916,12 +1916,29 @@
Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2);
switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) {
-default: assert(0 && "Operation not supported");
+default: assert(0 && "BinOp legalize operation not supported");
case TargetLowering::Legal: break;
case TargetLowering::Custom:
Tmp1 = TLI.LowerOperation(Result, DAG);
if (Tmp1.Val) Result = Tmp1;
break;
+case TargetLowering::Expand: {
+ assert(MVT::isVector(Node->getValueType(0)) &&
+ "Cannot expand this binary operator!");
+ // Expand the operation into a bunch of nasty scalar code.
+ std::vector Ops;
+ MVT::ValueType EltVT = MVT::getVectorBaseType(Node->getValueType(0));
+ MVT::ValueType PtrVT = TLI.getPointerTy();
+ for (unsigned i = 0, e =
MVT::getVectorNumElements(Node->getValueType(0));
+ i != e; ++i) {
+SDOperand Idx = DAG.getConstant(i, PtrVT);
+SDOperand LHS = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, EltVT, Tmp1, Idx);
+SDOperand RHS = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, EltVT, Tmp2, Idx);
+Ops.push_back(DAG.getNode(Node->getOpcode(), EltVT, LHS, RHS));
+ }
+ Result = DAG.getNode(ISD::BUILD_VECTOR, Node->getValueType(0), Ops);
+ break;
+}
}
break;
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[llvm-commits] CVS: llvm/lib/Target/PowerPC/README_ALTIVEC.txt
Changes in directory llvm/lib/Target/PowerPC:
README_ALTIVEC.txt updated: 1.9 -> 1.10
---
Log message:
add a note
---
Diffs of the changes: (+11 -0)
README_ALTIVEC.txt | 11 +++
1 files changed, 11 insertions(+)
Index: llvm/lib/Target/PowerPC/README_ALTIVEC.txt
diff -u llvm/lib/Target/PowerPC/README_ALTIVEC.txt:1.9
llvm/lib/Target/PowerPC/README_ALTIVEC.txt:1.10
--- llvm/lib/Target/PowerPC/README_ALTIVEC.txt:1.9 Fri Mar 31 13:00:22 2006
+++ llvm/lib/Target/PowerPC/README_ALTIVEC.txt Sat Apr 1 21:59:11 2006
@@ -137,3 +137,14 @@
Handle VECTOR_SHUFFLE nodes with the appropriate shuffle mask with vsldoi,
vpkuhum and vpkuwum.
+
+//===--===//
+
+Implement multiply for vector integer types, to avoid the horrible scalarized
+code produced by legalize.
+
+void test(vector int *X, vector int *Y) {
+ *X = *X * *Y;
+}
+
+//===--===//
___
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[llvm-commits] CVS: llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
Changes in directory llvm/lib/CodeGen/SelectionDAG:
LegalizeDAG.cpp updated: 1.350 -> 1.351
---
Log message:
Implement promotion for EXTRACT_VECTOR_ELT, allowing v16i8 multiplies to work
with PowerPC.
---
Diffs of the changes: (+27 -16)
LegalizeDAG.cpp | 43 +++
1 files changed, 27 insertions(+), 16 deletions(-)
Index: llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
diff -u llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp:1.350
llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp:1.351
--- llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp:1.350 Sat Apr 1 21:57:31 2006
+++ llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp Sat Apr 1 23:06:04 2006
@@ -194,6 +194,7 @@
SDOperand &Lo, SDOperand &Hi);
SDOperand LowerVEXTRACT_VECTOR_ELT(SDOperand Op);
+ SDOperand ExpandEXTRACT_VECTOR_ELT(SDOperand Op);
SDOperand getIntPtrConstant(uint64_t Val) {
return DAG.getConstant(Val, TLI.getPointerTy());
@@ -901,24 +902,10 @@
break;
}
// FALLTHROUGH
-case TargetLowering::Expand: {
- // If the target doesn't support this, store the value to a temporary
- // stack slot, then LOAD the scalar element back out.
- SDOperand StackPtr = CreateStackTemporary(Tmp1.getValueType());
- SDOperand Ch = DAG.getNode(ISD::STORE, MVT::Other, DAG.getEntryNode(),
- Tmp1, StackPtr, DAG.getSrcValue(NULL));
-
- // Add the offset to the index.
- unsigned EltSize = MVT::getSizeInBits(Result.getValueType())/8;
- Tmp2 = DAG.getNode(ISD::MUL, Tmp2.getValueType(), Tmp2,
- DAG.getConstant(EltSize, Tmp2.getValueType()));
- StackPtr = DAG.getNode(ISD::ADD, Tmp2.getValueType(), Tmp2, StackPtr);
-
- Result = DAG.getLoad(Result.getValueType(), Ch, StackPtr,
- DAG.getSrcValue(NULL));
+case TargetLowering::Expand:
+ Result = ExpandEXTRACT_VECTOR_ELT(Result);
break;
}
-}
break;
case ISD::VEXTRACT_VECTOR_ELT:
@@ -2990,6 +2977,9 @@
case ISD::VEXTRACT_VECTOR_ELT:
Result = PromoteOp(LowerVEXTRACT_VECTOR_ELT(Op));
break;
+ case ISD::EXTRACT_VECTOR_ELT:
+Result = PromoteOp(ExpandEXTRACT_VECTOR_ELT(Op));
+break;
}
assert(Result.Val && "Didn't set a result!");
@@ -3048,6 +3038,27 @@
}
}
+/// ExpandEXTRACT_VECTOR_ELT - Expand an EXTRACT_VECTOR_ELT operation into
+/// memory traffic.
+SDOperand SelectionDAGLegalize::ExpandEXTRACT_VECTOR_ELT(SDOperand Op) {
+ SDOperand Vector = Op.getOperand(0);
+ SDOperand Idx= Op.getOperand(1);
+
+ // If the target doesn't support this, store the value to a temporary
+ // stack slot, then LOAD the scalar element back out.
+ SDOperand StackPtr = CreateStackTemporary(Vector.getValueType());
+ SDOperand Ch = DAG.getNode(ISD::STORE, MVT::Other, DAG.getEntryNode(),
+ Vector, StackPtr, DAG.getSrcValue(NULL));
+
+ // Add the offset to the index.
+ unsigned EltSize = MVT::getSizeInBits(Op.getValueType())/8;
+ Idx = DAG.getNode(ISD::MUL, Idx.getValueType(), Idx,
+DAG.getConstant(EltSize, Idx.getValueType()));
+ StackPtr = DAG.getNode(ISD::ADD, Idx.getValueType(), Idx, StackPtr);
+
+ return DAG.getLoad(Op.getValueType(), Ch, StackPtr, DAG.getSrcValue(NULL));
+}
+
/// LegalizeSetCCOperands - Attempts to create a legal LHS and RHS for a SETCC
/// with condition CC on the current target. This usually involves legalizing
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[llvm-commits] CVS: llvm/win32/x86/x86.vcproj
Changes in directory llvm/win32/x86: x86.vcproj updated: 1.22 -> 1.23 --- Log message: Fix tablegen related dependencies in Visual Studio. --- Diffs of the changes: (+19 -2) x86.vcproj | 21 +++-- 1 files changed, 19 insertions(+), 2 deletions(-) Index: llvm/win32/x86/x86.vcproj diff -u llvm/win32/x86/x86.vcproj:1.22 llvm/win32/x86/x86.vcproj:1.23 --- llvm/win32/x86/x86.vcproj:1.22 Fri Mar 3 20:19:46 2006 +++ llvm/win32/x86/x86.vcproj Sat Apr 1 23:20:53 2006 @@ -124,7 +124,8 @@ ..\$(IntDir)\TableGen.exe -gen-asm-writer -I ..\..\lib\Target\X86 -I ..\..\include $(InputPath) -o X86GenAsmWriter.inc ..\$(IntDir)\TableGen.exe -gen-asm-writer -asmwriternum=1 -I ..\..\lib\Target\X86 -I ..\..\include $(InputPath) -o X86GenAsmWriter1.inc ..\$(IntDir)\TableGen.exe -gen-dag-isel -I ..\..\lib\Target\X86 -I ..\..\include $(InputPath) -o X86GenDAGISel.inc -..\$(IntDir)\TableGen.exe -gen-subtarget -I ..\..\lib\Target\X86 -I ..\..\include $(InputPath) -o X86GenSubtarget.inc" +..\$(IntDir)\TableGen.exe -gen-subtarget -I ..\..\lib\Target\X86 -I ..\..\include $(InputPath) -o X86GenSubtarget.inc +" AdditionalDependencies="$(InputDir)X86InstrInfo.td;$(InputDir)X86RegisterInfo.td;$(InputDir)..\Target.td;$(ProjectDir)..\$(IntDir)\TableGen.exe" Outputs="X86GenRegisterNames.inc;X86GenRegisterInfo.h.inc;X86GenRegisterInfo.inc;X86GenInstrNames.inc;X86GenInstrInfo.inc;X86GenAsmWriter.inc;X86GenAsmWriter1.inc;X86GenDAGISel.inc;X86GenSubtarget.inc"/> @@ -141,7 +142,8 @@ ..\$(IntDir)\TableGen.exe -gen-asm-writer -I ..\..\lib\Target\X86 -I ..\..\include $(InputPath) -o X86GenAsmWriter.inc ..\$(IntDir)\TableGen.exe -gen-asm-writer -asmwriternum=1 -I ..\..\lib\Target\X86 -I ..\..\include $(InputPath) -o X86GenAsmWriter1.inc ..\$(IntDir)\TableGen.exe -gen-dag-isel -I ..\..\lib\Target\X86 -I ..\..\include $(InputPath) -o X86GenDAGISel.inc -..\$(IntDir)\TableGen.exe -gen-subtarget -I ..\..\lib\Target\X86 -I ..\..\include $(InputPath) -o X86GenSubtarget.inc" +..\$(IntDir)\TableGen.exe -gen-subtarget -I ..\..\lib\Target\X86 -I ..\..\include $(InputPath) -o X86GenSubtarget.inc +" AdditionalDependencies="$(InputDir)X86InstrInfo.td;$(InputDir)X86RegisterInfo.td;$(InputDir)..\Target.td;$(ProjectDir)..\$(IntDir)\TableGen.exe" Outputs="X86GenRegisterNames.inc;X86GenRegisterInfo.h.inc;X86GenRegisterInfo.inc;X86GenInstrNames.inc;X86GenInstrInfo.inc;X86GenAsmWriter.inc;X86GenAsmWriter1.inc;X86GenDAGISel.inc;X86GenSubtarget.inc"/> @@ -194,6 +196,12 @@ RelativePath="..\..\lib\Target\Target.td"> + + + + + + + + + + http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
[llvm-commits] CVS: llvm/win32/VMCore/VMCore.vcproj
Changes in directory llvm/win32/VMCore: VMCore.vcproj updated: 1.19 -> 1.20 --- Log message: Fix tablegen related dependencies in Visual Studio. --- Diffs of the changes: (+8 -8) VMCore.vcproj | 16 1 files changed, 8 insertions(+), 8 deletions(-) Index: llvm/win32/VMCore/VMCore.vcproj diff -u llvm/win32/VMCore/VMCore.vcproj:1.19 llvm/win32/VMCore/VMCore.vcproj:1.20 --- llvm/win32/VMCore/VMCore.vcproj:1.19Mon Mar 27 22:01:27 2006 +++ llvm/win32/VMCore/VMCore.vcproj Sat Apr 1 23:20:52 2006 @@ -157,7 +157,7 @@ Description="Performing TableGen Step" CommandLine="..\$(IntDir)\TableGen.exe -gen-intrinsic -I ..\..\include $(InputPath) -o $(SolutionDir)llvm\intrinsics.gen " - AdditionalDependencies="$(ProjectDir)..\$(IntDir)\TableGen.exe $(InputDir)IntrinsicsX86.td $(InputDir)IntrinsicsPowerPC.td" + AdditionalDependencies="$(ProjectDir)..\$(IntDir)\TableGen.exe;$(InputDir)IntrinsicsX86.td;$(InputDir)IntrinsicsPowerPC.td" Outputs="$(SolutionDir)llvm\intrinsics.gen"/> - - - - + + + + http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
[llvm-commits] CVS: llvm/lib/Target/PowerPC/README_ALTIVEC.txt
Changes in directory llvm/lib/Target/PowerPC: README_ALTIVEC.txt updated: 1.10 -> 1.11 --- Log message: Remove done item --- Diffs of the changes: (+0 -5) README_ALTIVEC.txt |5 - 1 files changed, 5 deletions(-) Index: llvm/lib/Target/PowerPC/README_ALTIVEC.txt diff -u llvm/lib/Target/PowerPC/README_ALTIVEC.txt:1.10 llvm/lib/Target/PowerPC/README_ALTIVEC.txt:1.11 --- llvm/lib/Target/PowerPC/README_ALTIVEC.txt:1.10 Sat Apr 1 21:59:11 2006 +++ llvm/lib/Target/PowerPC/README_ALTIVEC.txt Sat Apr 1 23:28:54 2006 @@ -112,11 +112,6 @@ //===--===// -We should instcombine the lvx/stvx intrinsics into loads/stores if we know that -the loaded address is 16-byte aligned. - -//===--===// - Instead of writting a pattern for type-agnostic operations (e.g. gen-zero, load, store, and, ...) in every supported type, make legalize do the work. We should have a canonical type that we want operations changed to (e.g. v4i32 for ___ llvm-commits mailing list llvm-commits@cs.uiuc.edu http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
[llvm-commits] CVS: llvm/lib/Transforms/Scalar/InstructionCombining.cpp
Changes in directory llvm/lib/Transforms/Scalar:
InstructionCombining.cpp updated: 1.458 -> 1.459
---
Log message:
Turn altivec lvx/stvx intrinsics into loads and stores. This allows the
elimination of one load from this:
int AreSecondAndThirdElementsBothNegative( vector float *in ) {
#define QNaN 0x7FC0
const vector unsigned int testData = (vector unsigned int)( QNaN, 0, 0, QNaN );
vector float test = vec_ld( 0, (float*) &testData );
return ! vec_any_ge( test, *in );
}
Now generating:
_AreSecondAndThirdElementsBothNegative:
mfspr r2, 256
oris r4, r2, 49152
mtspr 256: http://llvm.cs.uiuc.edu/PR256 , r4
li r4, lo16(LCPI1_0)
lis r5, ha16(LCPI1_0)
addi r6, r1, -16
lvx v0, r5, r4
stvx v0, 0, r6
lvx v1, 0, r3
vcmpgefp. v0, v0, v1
mfcr r3, 2
rlwinm r3, r3, 27, 31, 31
xori r3, r3, 1
cntlzw r3, r3
srwi r3, r3, 5
mtspr 256: http://llvm.cs.uiuc.edu/PR256 , r2
blr
---
Diffs of the changes: (+22 -0)
InstructionCombining.cpp | 22 ++
1 files changed, 22 insertions(+)
Index: llvm/lib/Transforms/Scalar/InstructionCombining.cpp
diff -u llvm/lib/Transforms/Scalar/InstructionCombining.cpp:1.458
llvm/lib/Transforms/Scalar/InstructionCombining.cpp:1.459
--- llvm/lib/Transforms/Scalar/InstructionCombining.cpp:1.458 Sat Apr 1
16:05:01 2006
+++ llvm/lib/Transforms/Scalar/InstructionCombining.cpp Sat Apr 1 23:30:25 2006
@@ -5437,6 +5437,28 @@
} else {
switch (II->getIntrinsicID()) {
default: break;
+case Intrinsic::ppc_altivec_lvx:
+case Intrinsic::ppc_altivec_lvxl:
+ // Turn lvx -> load if the pointer is known aligned.
+ if (GetKnownAlignment(II->getOperand(1), TD) >= 16) {
+Instruction *Ptr = new CastInst(II->getOperand(1),
+PointerType::get(II->getType()),
"tmp");
+InsertNewInstBefore(Ptr, CI);
+return new LoadInst(Ptr);
+ }
+ break;
+case Intrinsic::ppc_altivec_stvx:
+case Intrinsic::ppc_altivec_stvxl:
+ // Turn stvx -> store if the pointer is known aligned.
+ if (GetKnownAlignment(II->getOperand(2), TD) >= 16) {
+const Type *OpTy = II->getOperand(1)->getType();
+Instruction *Ptr = new CastInst(II->getOperand(2),
+PointerType::get(OpTy), "tmp");
+InsertNewInstBefore(Ptr, CI);
+return new StoreInst(II->getOperand(1), Ptr);
+ }
+ break;
+
case Intrinsic::stackrestore: {
// If the save is right next to the restore, remove the restore. This
can
// happen when variable allocas are DCE'd.
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[llvm-commits] CVS: llvm/lib/Transforms/Scalar/InstructionCombining.cpp
Changes in directory llvm/lib/Transforms/Scalar:
InstructionCombining.cpp updated: 1.459 -> 1.460
---
Log message:
Allow transforming this:
%tmp = cast <4 x uint>* %testData to <4 x int>* ; <<4 x int>*>
[#uses=1]
%tmp = load <4 x int>* %tmp ; <<4 x int>> [#uses=1]
to this:
%tmp = load <4 x uint>* %testData ; <<4 x uint>> [#uses=1]
%tmp = cast <4 x uint> %tmp to <4 x int>; <<4 x int>>
[#uses=1]
---
Diffs of the changes: (+4 -2)
InstructionCombining.cpp |6 --
1 files changed, 4 insertions(+), 2 deletions(-)
Index: llvm/lib/Transforms/Scalar/InstructionCombining.cpp
diff -u llvm/lib/Transforms/Scalar/InstructionCombining.cpp:1.459
llvm/lib/Transforms/Scalar/InstructionCombining.cpp:1.460
--- llvm/lib/Transforms/Scalar/InstructionCombining.cpp:1.459 Sat Apr 1
23:30:25 2006
+++ llvm/lib/Transforms/Scalar/InstructionCombining.cpp Sat Apr 1 23:37:12 2006
@@ -6234,7 +6234,8 @@
if (const PointerType *SrcTy = dyn_cast(CastOp->getType())) {
const Type *SrcPTy = SrcTy->getElementType();
-if (DestPTy->isInteger() || isa(DestPTy)) {
+if (DestPTy->isInteger() || isa(DestPTy) ||
+isa(DestPTy)) {
// If the source is an array, the code below will not succeed. Check to
// see if a trivial 'gep P, 0, 0' will help matters. Only do this for
// constants.
@@ -6247,7 +6248,8 @@
SrcPTy = SrcTy->getElementType();
}
- if ((SrcPTy->isInteger() || isa(SrcPTy)) &&
+ if ((SrcPTy->isInteger() || isa(SrcPTy) ||
+ isa(SrcPTy)) &&
// Do not allow turning this into a load of an integer, which is then
// casted to a pointer, this pessimizes pointer analysis a lot.
(isa(SrcPTy) == isa(LI.getType())) &&
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[llvm-commits] CVS: llvm/lib/VMCore/Type.cpp
Changes in directory llvm/lib/VMCore:
Type.cpp updated: 1.137 -> 1.138
---
Log message:
vector casts never reinterpret bits
---
Diffs of the changes: (+5 -0)
Type.cpp |5 +
1 files changed, 5 insertions(+)
Index: llvm/lib/VMCore/Type.cpp
diff -u llvm/lib/VMCore/Type.cpp:1.137 llvm/lib/VMCore/Type.cpp:1.138
--- llvm/lib/VMCore/Type.cpp:1.137 Wed Nov 16 00:09:47 2005
+++ llvm/lib/VMCore/Type.cppSat Apr 1 23:40:28 2006
@@ -75,6 +75,11 @@
//
bool Type::isLosslesslyConvertibleTo(const Type *Ty) const {
if (this == Ty) return true;
+
+ // Packed type conversions are always bitwise.
+ if (isa(this) && isa(Ty))
+return true;
+
if ((!isPrimitiveType()&& !isa(this)) ||
(!isa(Ty) && !Ty->isPrimitiveType())) return false;
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[llvm-commits] CVS: llvm/lib/Transforms/Scalar/InstructionCombining.cpp
Changes in directory llvm/lib/Transforms/Scalar: InstructionCombining.cpp updated: 1.460 -> 1.461 --- Log message: vector casts of casts are eliminable. Transform this: %tmp = cast <4 x uint> %tmp to <4 x int>; <<4 x int>> [#uses=1] %tmp = cast <4 x int> %tmp to <4 x float> ; <<4 x float>> [#uses=1] into: %tmp = cast <4 x uint> %tmp to <4 x float> ; <<4 x float>> [#uses=1] --- Diffs of the changes: (+4 -0) InstructionCombining.cpp |4 1 files changed, 4 insertions(+) Index: llvm/lib/Transforms/Scalar/InstructionCombining.cpp diff -u llvm/lib/Transforms/Scalar/InstructionCombining.cpp:1.460 llvm/lib/Transforms/Scalar/InstructionCombining.cpp:1.461 --- llvm/lib/Transforms/Scalar/InstructionCombining.cpp:1.460 Sat Apr 1 23:37:12 2006 +++ llvm/lib/Transforms/Scalar/InstructionCombining.cpp Sat Apr 1 23:43:13 2006 @@ -4539,6 +4539,10 @@ SrcTy->getPrimitiveSize() < MidTy->getPrimitiveSize()) return true; + // Packed type conversions don't modify bits. + if (isa(SrcTy) && isa(MidTy) &&isa(DstTy)) +return true; + return false; } ___ llvm-commits mailing list llvm-commits@cs.uiuc.edu http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
[llvm-commits] CVS: llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
Changes in directory llvm/lib/CodeGen/SelectionDAG:
DAGCombiner.cpp updated: 1.138 -> 1.139
---
Log message:
Add a little dag combine to compile this:
int %AreSecondAndThirdElementsBothNegative(<4 x float>* %in) {
entry:
%tmp1 = load <4 x float>* %in ; <<4 x float>> [#uses=1]
%tmp = tail call int %llvm.ppc.altivec.vcmpgefp.p( int 1, <4 x float> <
float 0x7FF8, float 0.00e+00, float 0.00e+00, float
0x7FF8 >, <4 x float> %tmp1 ) ; [#uses=1]
%tmp = seteq int %tmp, 0; [#uses=1]
%tmp3 = cast bool %tmp to int ; [#uses=1]
ret int %tmp3
}
into this:
_AreSecondAndThirdElementsBothNegative:
mfspr r2, 256
oris r4, r2, 49152
mtspr 256: http://llvm.cs.uiuc.edu/PR256 , r4
li r4, lo16(LCPI1_0)
lis r5, ha16(LCPI1_0)
lvx v0, 0, r3
lvx v1, r5, r4
vcmpgefp. v0, v1, v0
mfcr r3, 2
rlwinm r3, r3, 27, 31, 31
mtspr 256: http://llvm.cs.uiuc.edu/PR256 , r2
blr
instead of this:
_AreSecondAndThirdElementsBothNegative:
mfspr r2, 256
oris r4, r2, 49152
mtspr 256: http://llvm.cs.uiuc.edu/PR256 , r4
li r4, lo16(LCPI1_0)
lis r5, ha16(LCPI1_0)
lvx v0, 0, r3
lvx v1, r5, r4
vcmpgefp. v0, v1, v0
mfcr r3, 2
rlwinm r3, r3, 27, 31, 31
xori r3, r3, 1
cntlzw r3, r3
srwi r3, r3, 5
mtspr 256: http://llvm.cs.uiuc.edu/PR256 , r2
blr
---
Diffs of the changes: (+33 -0)
DAGCombiner.cpp | 33 +
1 files changed, 33 insertions(+)
Index: llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
diff -u llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp:1.138
llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp:1.139
--- llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp:1.138 Sat Apr 1 21:25:57 2006
+++ llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp Sun Apr 2 00:11:11 2006
@@ -1601,6 +1601,39 @@
return DAG.getNode(ISD::SRL, VT, N0.getOperand(0),
DAG.getConstant(c1 + c2, N1.getValueType()));
}
+
+ // fold (srl (ctlz x), "5") -> x iff x has one bit set (the low bit).
+ if (N1C && N0.getOpcode() == ISD::CTLZ &&
+ N1C->getValue() == Log2_32(MVT::getSizeInBits(VT))) {
+uint64_t KnownZero, KnownOne, Mask = MVT::getIntVTBitMask(VT);
+TLI.ComputeMaskedBits(N0.getOperand(0), Mask, KnownZero, KnownOne);
+
+// If any of the input bits are KnownOne, then the input couldn't be all
+// zeros, thus the result of the srl will always be zero.
+if (KnownOne) return DAG.getConstant(0, VT);
+
+// If all of the bits input the to ctlz node are known to be zero, then
+// the result of the ctlz is "32" and the result of the shift is one.
+uint64_t UnknownBits = ~KnownZero & Mask;
+if (UnknownBits == 0) return DAG.getConstant(1, VT);
+
+// Otherwise, check to see if there is exactly one bit input to the ctlz.
+if ((UnknownBits & (UnknownBits-1)) == 0) {
+ // Okay, we know that only that the single bit specified by UnknownBits
+ // could be set on input to the CTLZ node. If this bit is set, the SRL
+ // will return 0, if it is clear, it returns 1. Change the CTLZ/SRL pair
+ // to an SRL,XOR pair, which is likely to simplify more.
+ unsigned ShAmt = CountTrailingZeros_64(UnknownBits);
+ SDOperand Op = N0.getOperand(0);
+ if (ShAmt) {
+Op = DAG.getNode(ISD::SRL, VT, Op,
+ DAG.getConstant(ShAmt, TLI.getShiftAmountTy()));
+AddToWorkList(Op.Val);
+ }
+ return DAG.getNode(ISD::XOR, VT, Op, DAG.getConstant(1, VT));
+}
+ }
+
return SDOperand();
}
___
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[llvm-commits] CVS: llvm/lib/Target/TargetLowering.cpp
Changes in directory llvm/lib/Target:
TargetLowering.cpp updated: 1.51 -> 1.52
---
Log message:
Allow targets to compute masked bits for intrinsics.
---
Diffs of the changes: (+9 -4)
TargetLowering.cpp | 13 +
1 files changed, 9 insertions(+), 4 deletions(-)
Index: llvm/lib/Target/TargetLowering.cpp
diff -u llvm/lib/Target/TargetLowering.cpp:1.51
llvm/lib/Target/TargetLowering.cpp:1.52
--- llvm/lib/Target/TargetLowering.cpp:1.51 Thu Mar 30 19:50:09 2006
+++ llvm/lib/Target/TargetLowering.cpp Sun Apr 2 00:15:09 2006
@@ -619,9 +619,10 @@
}
case ISD::ADD:
case ISD::SUB:
-// Just use ComputeMaskedBits to compute output bits, there are no
-// simplifications that can be done here, and sub always demands all input
-// bits.
+ case ISD::INTRINSIC_WO_CHAIN:
+ case ISD::INTRINSIC_W_CHAIN:
+ case ISD::INTRINSIC_VOID:
+// Just use ComputeMaskedBits to compute output bits.
ComputeMaskedBits(Op, DemandedMask, KnownZero, KnownOne, Depth);
break;
}
@@ -916,8 +917,12 @@
}
default:
// Allow the target to implement this method for its nodes.
-if (Op.getOpcode() >= ISD::BUILTIN_OP_END)
+if (Op.getOpcode() >= ISD::BUILTIN_OP_END) {
+ case ISD::INTRINSIC_WO_CHAIN:
+ case ISD::INTRINSIC_W_CHAIN:
+ case ISD::INTRINSIC_VOID:
computeMaskedBitsForTargetNode(Op, Mask, KnownZero, KnownOne);
+}
return;
}
}
___
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[llvm-commits] CVS: llvm/lib/Target/TargetLowering.cpp
Changes in directory llvm/lib/Target:
TargetLowering.cpp updated: 1.52 -> 1.53
---
Log message:
relax assertion
---
Diffs of the changes: (+4 -1)
TargetLowering.cpp |5 -
1 files changed, 4 insertions(+), 1 deletion(-)
Index: llvm/lib/Target/TargetLowering.cpp
diff -u llvm/lib/Target/TargetLowering.cpp:1.52
llvm/lib/Target/TargetLowering.cpp:1.53
--- llvm/lib/Target/TargetLowering.cpp:1.52 Sun Apr 2 00:15:09 2006
+++ llvm/lib/Target/TargetLowering.cpp Sun Apr 2 00:19:46 2006
@@ -935,7 +935,10 @@
uint64_t &KnownZero,
uint64_t &KnownOne,
unsigned Depth) const {
- assert(Op.getOpcode() >= ISD::BUILTIN_OP_END &&
+ assert((Op.getOpcode() >= ISD::BUILTIN_OP_END ||
+ Op.getOpcode() == ISD::INTRINSIC_WO_CHAIN ||
+ Op.getOpcode() == ISD::INTRINSIC_W_CHAIN ||
+ Op.getOpcode() == ISD::INTRINSIC_VOID) &&
"Should use MaskedValueIsZero if you don't know whether Op"
" is a target node!");
KnownZero = 0;
___
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[llvm-commits] CVS: llvm/lib/Target/PowerPC/PPCISelLowering.cpp PPCISelLowering.h
Changes in directory llvm/lib/Target/PowerPC:
PPCISelLowering.cpp updated: 1.125 -> 1.126
PPCISelLowering.h updated: 1.37 -> 1.38
---
Log message:
Inform the dag combiner that the predicate compares only return a low bit.
---
Diffs of the changes: (+39 -1)
PPCISelLowering.cpp | 35 ++-
PPCISelLowering.h |5 +
2 files changed, 39 insertions(+), 1 deletion(-)
Index: llvm/lib/Target/PowerPC/PPCISelLowering.cpp
diff -u llvm/lib/Target/PowerPC/PPCISelLowering.cpp:1.125
llvm/lib/Target/PowerPC/PPCISelLowering.cpp:1.126
--- llvm/lib/Target/PowerPC/PPCISelLowering.cpp:1.125 Sat Apr 1 18:43:36 2006
+++ llvm/lib/Target/PowerPC/PPCISelLowering.cpp Sun Apr 2 00:26:07 2006
@@ -760,7 +760,7 @@
return DAG.getNode(PPCISD::VPERM, V1.getValueType(), V1, V2, VPermMask);
}
case ISD::INTRINSIC_WO_CHAIN: {
-unsigned IntNo=cast(Op.getOperand(0))->getValue();
+unsigned IntNo = cast(Op.getOperand(0))->getValue();
// If this is a lowered altivec predicate compare, CompareOpc is set to the
// opcode number of the comparison.
@@ -1409,6 +1409,39 @@
return SDOperand();
}
+void PPCTargetLowering::computeMaskedBitsForTargetNode(const SDOperand Op,
+ uint64_t Mask,
+ uint64_t &KnownZero,
+ uint64_t &KnownOne,
+ unsigned Depth) const {
+ KnownZero = 0;
+ KnownOne = 0;
+ switch (Op.getOpcode()) {
+ default: break;
+ case ISD::INTRINSIC_WO_CHAIN: {
+switch (cast(Op.getOperand(0))->getValue()) {
+default: break;
+case Intrinsic::ppc_altivec_vcmpbfp_p:
+case Intrinsic::ppc_altivec_vcmpeqfp_p:
+case Intrinsic::ppc_altivec_vcmpequb_p:
+case Intrinsic::ppc_altivec_vcmpequh_p:
+case Intrinsic::ppc_altivec_vcmpequw_p:
+case Intrinsic::ppc_altivec_vcmpgefp_p:
+case Intrinsic::ppc_altivec_vcmpgtfp_p:
+case Intrinsic::ppc_altivec_vcmpgtsb_p:
+case Intrinsic::ppc_altivec_vcmpgtsh_p:
+case Intrinsic::ppc_altivec_vcmpgtsw_p:
+case Intrinsic::ppc_altivec_vcmpgtub_p:
+case Intrinsic::ppc_altivec_vcmpgtuh_p:
+case Intrinsic::ppc_altivec_vcmpgtuw_p:
+ KnownZero = ~1U; // All bits but the low one are known to be zero.
+ break;
+}
+ }
+ }
+}
+
+
/// getConstraintType - Given a constraint letter, return the type of
/// constraint it is for this target.
PPCTargetLowering::ConstraintType
Index: llvm/lib/Target/PowerPC/PPCISelLowering.h
diff -u llvm/lib/Target/PowerPC/PPCISelLowering.h:1.37
llvm/lib/Target/PowerPC/PPCISelLowering.h:1.38
--- llvm/lib/Target/PowerPC/PPCISelLowering.h:1.37 Thu Mar 30 23:13:27 2006
+++ llvm/lib/Target/PowerPC/PPCISelLowering.h Sun Apr 2 00:26:07 2006
@@ -133,6 +133,11 @@
virtual SDOperand PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const;
+virtual void computeMaskedBitsForTargetNode(const SDOperand Op,
+uint64_t Mask,
+uint64_t &KnownZero,
+uint64_t &KnownOne,
+unsigned Depth = 0) const;
/// LowerArguments - This hook must be implemented to indicate how we
should
/// lower the arguments for the specified function, into the specified DAG.
virtual std::vector
___
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[llvm-commits] CVS: llvm/lib/Target/PowerPC/README.txt
Changes in directory llvm/lib/Target/PowerPC: README.txt updated: 1.83 -> 1.84 --- Log message: add a note --- Diffs of the changes: (+9 -0) README.txt |9 + 1 files changed, 9 insertions(+) Index: llvm/lib/Target/PowerPC/README.txt diff -u llvm/lib/Target/PowerPC/README.txt:1.83 llvm/lib/Target/PowerPC/README.txt:1.84 --- llvm/lib/Target/PowerPC/README.txt:1.83 Mon Mar 27 01:04:16 2006 +++ llvm/lib/Target/PowerPC/README.txt Sun Apr 2 01:20:00 2006 @@ -551,3 +551,12 @@ ===-=== +extract_vector_elt of an arbitrary constant vector can be done with the +following instructions: + +vTemp = vec_splat(v0,2);// 2 is the element the src is in. +vec_ste(&destloc,0,vTemp); + +We can do an arbitrary non-constant value by using lvsr/perm/ste. + +===-=== ___ llvm-commits mailing list llvm-commits@cs.uiuc.edu http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
