[llvm-commits] CVS: llvm/utils/TableGen/DAGISelEmitter.cpp
Changes in directory llvm/utils/TableGen:
DAGISelEmitter.cpp updated: 1.178 -> 1.179
---
Log message:
It should be ok for a xform output type to be different from input type.
---
Diffs of the changes: (+17 -5)
DAGISelEmitter.cpp | 22 +-
1 files changed, 17 insertions(+), 5 deletions(-)
Index: llvm/utils/TableGen/DAGISelEmitter.cpp
diff -u llvm/utils/TableGen/DAGISelEmitter.cpp:1.178
llvm/utils/TableGen/DAGISelEmitter.cpp:1.179
--- llvm/utils/TableGen/DAGISelEmitter.cpp:1.178Mon Mar 20 00:04:09 2006
+++ llvm/utils/TableGen/DAGISelEmitter.cpp Mon Mar 20 02:09:17 2006
@@ -694,14 +694,26 @@
} else {
assert(getOperator()->isSubClassOf("SDNodeXForm") && "Unknown node type!");
-// Node transforms always take one operand, and take and return the same
-// type.
+// Node transforms always take one operand.
if (getNumChildren() != 1)
TP.error("Node transform '" + getOperator()->getName() +
"' requires one operand!");
-bool MadeChange = UpdateNodeType(getChild(0)->getExtTypes(), TP);
-MadeChange |= getChild(0)->UpdateNodeType(getExtTypes(), TP);
-return MadeChange;
+unsigned char ExtType0 = getExtTypeNum(0);
+unsigned char ChildExtType0 = getChild(0)->getExtTypeNum(0);
+if (ExtType0 == MVT::isInt ||
+ExtType0 == MVT::isFP ||
+ExtType0 == MVT::isUnknown ||
+ChildExtType0 == MVT::isInt ||
+ChildExtType0 == MVT::isFP ||
+ChildExtType0 == MVT::isUnknown) {
+ // If either the output or input of the xform does not have exact
+ // type info. We assume they must be the same. Otherwise, it is perfectly
+ // legal to transform from one type to a completely different type.
+ bool MadeChange = UpdateNodeType(getChild(0)->getExtTypes(), TP);
+ MadeChange |= getChild(0)->UpdateNodeType(getExtTypes(), TP);
+ return MadeChange;
+}
+return false;
}
}
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[llvm-commits] CVS: llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp PPCInstrInfo.td
Changes in directory llvm/lib/Target/PowerPC:
PPCISelDAGToDAG.cpp updated: 1.170 -> 1.171
PPCInstrInfo.td updated: 1.197 -> 1.198
---
Log message:
Use tblgen'd VECTOR_SHUFFLE selection code.
---
Diffs of the changes: (+2 -19)
PPCISelDAGToDAG.cpp | 16
PPCInstrInfo.td |5 ++---
2 files changed, 2 insertions(+), 19 deletions(-)
Index: llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp
diff -u llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp:1.170
llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp:1.171
--- llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp:1.170 Mon Mar 20 00:51:10 2006
+++ llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp Mon Mar 20 02:14:16 2006
@@ -927,22 +927,6 @@
switch (N->getOpcode()) {
default: break;
- case ISD::VECTOR_SHUFFLE:
-// FIXME: This should be autogenerated from the .td file, it is here for
now
-// due to bugs in tblgen.
-if (Op.getOperand(1).getOpcode() == ISD::UNDEF &&
-(Op.getValueType() == MVT::v4f32 || Op.getValueType() == MVT::v4i32) &&
-PPC::isSplatShuffleMask(Op.getOperand(2).Val)) {
- SDOperand N0;
- Select(N0, N->getOperand(0));
-
- Result = CodeGenMap[Op] =
-SDOperand(CurDAG->getTargetNode(PPC::VSPLTW, MVT::v4f32,
- getI32Imm(PPC::getVSPLTImmediate(Op.getOperand(2).Val)),
-N0), 0);
- return;
-}
-assert(0 && "ILLEGAL VECTOR_SHUFFLE!");
case ISD::SETCC:
Result = SelectSETCC(Op);
return;
Index: llvm/lib/Target/PowerPC/PPCInstrInfo.td
diff -u llvm/lib/Target/PowerPC/PPCInstrInfo.td:1.197
llvm/lib/Target/PowerPC/PPCInstrInfo.td:1.198
--- llvm/lib/Target/PowerPC/PPCInstrInfo.td:1.197 Mon Mar 20 00:51:10 2006
+++ llvm/lib/Target/PowerPC/PPCInstrInfo.td Mon Mar 20 02:14:16 2006
@@ -1034,9 +1034,8 @@
def VSPLTW : VXForm_1<652, (ops VRRC:$vD, u5imm:$UIMM, VRRC:$vB),
"vspltw $vD, $vB, $UIMM", VecPerm,
- [/*
- (set VRRC:$vD, (vector_shuffle (v4f32 VRRC:$vB),
(undef),
- VSPLT_shuffle_mask:$UIMM))*/]>;
+ [(set VRRC:$vD, (vector_shuffle (v4f32 VRRC:$vB),
(undef),
+ VSPLT_shuffle_mask:$UIMM))]>;
// FIXME: ALSO ADD SUPPORT FOR v4i32!
// VX-Form Pseudo Instructions
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[llvm-commits] CVS: llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp
Changes in directory llvm/lib/Target/PowerPC:
PPCISelDAGToDAG.cpp updated: 1.171 -> 1.172
---
Log message:
reenable this hack, the tblgen version isn't quite ready
---
Diffs of the changes: (+16 -0)
PPCISelDAGToDAG.cpp | 16
1 files changed, 16 insertions(+)
Index: llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp
diff -u llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp:1.171
llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp:1.172
--- llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp:1.171 Mon Mar 20 02:14:16 2006
+++ llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp Mon Mar 20 11:54:43 2006
@@ -927,6 +927,22 @@
switch (N->getOpcode()) {
default: break;
+ case ISD::VECTOR_SHUFFLE:
+// FIXME: This should be autogenerated from the .td file, it is here for
now
+// due to bugs in tblgen.
+if (Op.getOperand(1).getOpcode() == ISD::UNDEF &&
+(Op.getValueType() == MVT::v4f32 || Op.getValueType() == MVT::v4i32) &&
+PPC::isSplatShuffleMask(Op.getOperand(2).Val)) {
+ SDOperand N0;
+ Select(N0, N->getOperand(0));
+ Result = CodeGenMap[Op] =
+SDOperand(CurDAG->getTargetNode(PPC::VSPLTW, MVT::v4f32,
+
getI32Imm(PPC::getVSPLTImmediate(Op.getOperand(2).Val)),
+N0), 0);
+ return;
+}
+assert(0 && "ILLEGAL VECTOR_SHUFFLE!");
+
case ISD::SETCC:
Result = SelectSETCC(Op);
return;
___
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[llvm-commits] CVS: llvm/lib/Target/PowerPC/PPCInstrInfo.td
Changes in directory llvm/lib/Target/PowerPC: PPCInstrInfo.td updated: 1.198 -> 1.199 --- Log message: Fix the pattern for VADDUWM, add i32 splat --- Diffs of the changes: (+4 -1) PPCInstrInfo.td |5 - 1 files changed, 4 insertions(+), 1 deletion(-) Index: llvm/lib/Target/PowerPC/PPCInstrInfo.td diff -u llvm/lib/Target/PowerPC/PPCInstrInfo.td:1.198 llvm/lib/Target/PowerPC/PPCInstrInfo.td:1.199 --- llvm/lib/Target/PowerPC/PPCInstrInfo.td:1.198 Mon Mar 20 02:14:16 2006 +++ llvm/lib/Target/PowerPC/PPCInstrInfo.td Mon Mar 20 11:51:58 2006 @@ -972,7 +972,7 @@ [(set VRRC:$vD, (fadd VRRC:$vA, VRRC:$vB))]>; def VADDUWM : VXForm_1<128, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB), "vadduwm $vD, $vA, $vB", VecGeneral, - [(set VRRC:$vD, (add VRRC:$vA, VRRC:$vB))]>; + [(set VRRC:$vD, (add (v4i32 VRRC:$vA), VRRC:$vB))]>; def VCFSX : VXForm_1<842, (ops VRRC:$vD, u5imm:$UIMM, VRRC:$vB), "vcfsx $vD, $vB, $UIMM", VecFP, []>; @@ -1178,6 +1178,9 @@ (v16i8 (LVX xoaddr:$src))>; +def : Pat<(vector_shuffle (v4i32 VRRC:$vB), (undef), VSPLT_shuffle_mask:$UIMM), + (v4i32 (VSPLTW VSPLT_shuffle_mask:$UIMM, VRRC:$vB))>; + def : Pat<(PPCvperm (v4i32 VRRC:$vA), VRRC:$vB, VRRC:$vC), (v4i32 (VPERM VRRC:$vA, VRRC:$vB, VRRC:$vC))>; ___ llvm-commits mailing list llvm-commits@cs.uiuc.edu http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
[llvm-commits] CVS: llvm/test/Regression/CodeGen/X86/loop-strength-reduce.ll
Changes in directory llvm/test/Regression/CodeGen/X86:
loop-strength-reduce.ll updated: 1.1 -> 1.2
---
Log message:
Option -enable-x86-lsr has been removed
---
Diffs of the changes: (+1 -1)
loop-strength-reduce.ll |2 +-
1 files changed, 1 insertion(+), 1 deletion(-)
Index: llvm/test/Regression/CodeGen/X86/loop-strength-reduce.ll
diff -u llvm/test/Regression/CodeGen/X86/loop-strength-reduce.ll:1.1
llvm/test/Regression/CodeGen/X86/loop-strength-reduce.ll:1.2
--- llvm/test/Regression/CodeGen/X86/loop-strength-reduce.ll:1.1Fri Mar
17 13:45:54 2006
+++ llvm/test/Regression/CodeGen/X86/loop-strength-reduce.llMon Mar 20
12:26:11 2006
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -march=x86 -enable-x86-lsr | grep 'A(' | wc -l |
grep 1
+; RUN: llvm-as < %s | llc -march=x86 | grep 'A(' | wc -l | grep 1
;
; Make sure the common loop invariant _A(reg) is hoisted up to preheader.
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[llvm-commits] CVS: llvm/lib/Target/PowerPC/PPCISelLowering.cpp PPCInstrInfo.td
Changes in directory llvm/lib/Target/PowerPC: PPCISelLowering.cpp updated: 1.104 -> 1.105 PPCInstrInfo.td updated: 1.199 -> 1.200 --- Log message: Fix a couple of bugs in permute/splat generate, thanks to Nate for actually figuring these out! :) --- Diffs of the changes: (+1 -3) PPCISelLowering.cpp |2 -- PPCInstrInfo.td |2 +- 2 files changed, 1 insertion(+), 3 deletions(-) Index: llvm/lib/Target/PowerPC/PPCISelLowering.cpp diff -u llvm/lib/Target/PowerPC/PPCISelLowering.cpp:1.104 llvm/lib/Target/PowerPC/PPCISelLowering.cpp:1.105 --- llvm/lib/Target/PowerPC/PPCISelLowering.cpp:1.104 Mon Mar 20 00:51:10 2006 +++ llvm/lib/Target/PowerPC/PPCISelLowering.cpp Mon Mar 20 12:26:51 2006 @@ -599,8 +599,6 @@ // Store the input value into Value#0 of the stack slot. unsigned InSize = MVT::getSizeInBits(Op.getOperand(0).getValueType())/8; -FIdx = DAG.getNode(ISD::ADD, MVT::i32, FIdx, - DAG.getConstant(16-InSize, MVT::i32)); SDOperand Store = DAG.getNode(ISD::STORE, MVT::Other, DAG.getEntryNode(), Op.getOperand(0), FIdx,DAG.getSrcValue(NULL)); return DAG.getNode(PPCISD::LVE_X, Op.getValueType(), Store, FIdx, Index: llvm/lib/Target/PowerPC/PPCInstrInfo.td diff -u llvm/lib/Target/PowerPC/PPCInstrInfo.td:1.199 llvm/lib/Target/PowerPC/PPCInstrInfo.td:1.200 --- llvm/lib/Target/PowerPC/PPCInstrInfo.td:1.199 Mon Mar 20 11:51:58 2006 +++ llvm/lib/Target/PowerPC/PPCInstrInfo.td Mon Mar 20 12:26:51 2006 @@ -961,7 +961,7 @@ Requires<[FPContractions]>; def VPERM : VAForm_1<43, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB, VRRC:$vC), - "vperm $vD, $vA, $vC, $vB", VecPerm, + "vperm $vD, $vA, $vB, $vC", VecPerm, [(set VRRC:$vD, (PPCvperm (v4f32 VRRC:$vA), VRRC:$vB, VRRC:$vC))]>; ___ llvm-commits mailing list llvm-commits@cs.uiuc.edu http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
[llvm-commits] CVS: llvm/include/llvm/Analysis/PostDominators.h Dominators.h
Changes in directory llvm/include/llvm/Analysis:
PostDominators.h updated: 1.11 -> 1.12
Dominators.h updated: 1.53 -> 1.54
---
Log message:
Move some common data structures between dom and pdom into the base class
---
Diffs of the changes: (+16 -32)
Dominators.h | 32
PostDominators.h | 16
2 files changed, 16 insertions(+), 32 deletions(-)
Index: llvm/include/llvm/Analysis/PostDominators.h
diff -u llvm/include/llvm/Analysis/PostDominators.h:1.11
llvm/include/llvm/Analysis/PostDominators.h:1.12
--- llvm/include/llvm/Analysis/PostDominators.h:1.11Fri Mar 10 20:20:46 2006
+++ llvm/include/llvm/Analysis/PostDominators.h Mon Mar 20 13:32:48 2006
@@ -32,22 +32,6 @@
}
private:
-struct InfoRec {
- unsigned Semi;
- unsigned Size;
- BasicBlock *Label, *Parent, *Child, *Ancestor;
-
- std::vector Bucket;
-
- InfoRec() : Semi(0), Size(0), Label(0), Parent(0), Child(0),
Ancestor(0){}
-};
-
- // Vertex - Map the DFS number to the BasicBlock*
- std::vector Vertex;
-
- // Info - Collection of information used during the computation of idoms.
- std::map Info;
-
unsigned DFSPass(BasicBlock *V, InfoRec &VInfo, unsigned N);
void Compress(BasicBlock *V, InfoRec &VInfo);
BasicBlock *Eval(BasicBlock *v);
Index: llvm/include/llvm/Analysis/Dominators.h
diff -u llvm/include/llvm/Analysis/Dominators.h:1.53
llvm/include/llvm/Analysis/Dominators.h:1.54
--- llvm/include/llvm/Analysis/Dominators.h:1.53Sat Jan 14 14:55:08 2006
+++ llvm/include/llvm/Analysis/Dominators.h Mon Mar 20 13:32:48 2006
@@ -66,7 +66,23 @@
///
class ImmediateDominatorsBase : public DominatorBase {
protected:
+ struct InfoRec {
+unsigned Semi;
+unsigned Size;
+BasicBlock *Label, *Parent, *Child, *Ancestor;
+
+std::vector Bucket;
+
+InfoRec() : Semi(0), Size(0), Label(0), Parent(0), Child(0), Ancestor(0){}
+ };
+
std::map IDoms;
+
+ // Vertex - Map the DFS number to the BasicBlock*
+ std::vector Vertex;
+
+ // Info - Collection of information used during the computation of idoms.
+ std::map Info;
public:
ImmediateDominatorsBase(bool isPostDom) : DominatorBase(isPostDom) {}
@@ -139,22 +155,6 @@
}
private:
- struct InfoRec {
-unsigned Semi;
-unsigned Size;
-BasicBlock *Label, *Parent, *Child, *Ancestor;
-
-std::vector Bucket;
-
-InfoRec() : Semi(0), Size(0), Label(0), Parent(0), Child(0), Ancestor(0){}
- };
-
- // Vertex - Map the DFS number to the BasicBlock*
- std::vector Vertex;
-
- // Info - Collection of information used during the computation of idoms.
- std::map Info;
-
unsigned DFSPass(BasicBlock *V, InfoRec &VInfo, unsigned N);
void Compress(BasicBlock *V, InfoRec &VInfo);
BasicBlock *Eval(BasicBlock *v);
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[llvm-commits] CVS: llvm/test/Regression/CodeGen/PowerPC/load-constant-addr.ll
Changes in directory llvm/test/Regression/CodeGen/PowerPC:
load-constant-addr.ll added (r1.1)
---
Log message:
new testcase
---
Diffs of the changes: (+9 -0)
load-constant-addr.ll |9 +
1 files changed, 9 insertions(+)
Index: llvm/test/Regression/CodeGen/PowerPC/load-constant-addr.ll
diff -c /dev/null llvm/test/Regression/CodeGen/PowerPC/load-constant-addr.ll:1.1
*** /dev/null Mon Mar 20 16:37:15 2006
--- llvm/test/Regression/CodeGen/PowerPC/load-constant-addr.ll Mon Mar 20
16:37:05 2006
***
*** 0
--- 1,9
+ ; Should fold the ori into the lfs.
+ ; RUN: llvm-as < %s | llc -march=ppc32 | grep lfs &&
+ ; RUN: llvm-as < %s | llc -march=ppc32 | not grep ori
+
+ float %test() {
+ %tmp.i = load float* cast (uint 186018016 to float*)
+ ret float %tmp.i
+ }
+
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[llvm-commits] CVS: llvm/lib/Target/PowerPC/PPCISelLowering.cpp
Changes in directory llvm/lib/Target/PowerPC: PPCISelLowering.cpp updated: 1.105 -> 1.106 --- Log message: remove dead variable --- Diffs of the changes: (+1 -1) PPCISelLowering.cpp |2 +- 1 files changed, 1 insertion(+), 1 deletion(-) Index: llvm/lib/Target/PowerPC/PPCISelLowering.cpp diff -u llvm/lib/Target/PowerPC/PPCISelLowering.cpp:1.105 llvm/lib/Target/PowerPC/PPCISelLowering.cpp:1.106 --- llvm/lib/Target/PowerPC/PPCISelLowering.cpp:1.105 Mon Mar 20 12:26:51 2006 +++ llvm/lib/Target/PowerPC/PPCISelLowering.cpp Mon Mar 20 16:37:23 2006 @@ -598,9 +598,9 @@ SDOperand FIdx = DAG.getFrameIndex(FrameIdx, MVT::i32); // Store the input value into Value#0 of the stack slot. -unsigned InSize = MVT::getSizeInBits(Op.getOperand(0).getValueType())/8; SDOperand Store = DAG.getNode(ISD::STORE, MVT::Other, DAG.getEntryNode(), Op.getOperand(0), FIdx,DAG.getSrcValue(NULL)); +// LVE_X it out. return DAG.getNode(PPCISD::LVE_X, Op.getValueType(), Store, FIdx, DAG.getSrcValue(NULL)); } ___ llvm-commits mailing list llvm-commits@cs.uiuc.edu http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
[llvm-commits] CVS: llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp
Changes in directory llvm/lib/Target/PowerPC:
PPCISelDAGToDAG.cpp updated: 1.172 -> 1.173
---
Log message:
Handle constant addresses more efficiently, folding the low bits into the
disp field of the load/store if possible. This compiles
CodeGen/PowerPC/load-constant-addr.ll to:
_test:
lis r2, 2838
lfs f1, 26848(r2)
blr
instead of:
_test:
lis r2, 2838
ori r2, r2, 26848
lfs f1, 0(r2)
blr
---
Diffs of the changes: (+17 -0)
PPCISelDAGToDAG.cpp | 17 +
1 files changed, 17 insertions(+)
Index: llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp
diff -u llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp:1.172
llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp:1.173
--- llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp:1.172 Mon Mar 20 11:54:43 2006
+++ llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp Mon Mar 20 16:38:22 2006
@@ -535,7 +535,24 @@
return true;
}
}
+ } else if (ConstantSDNode *CN = dyn_cast(N)) {
+// Loading from a constant address.
+int Addr = (int)CN->getValue();
+
+// If this address fits entirely in a 16-bit sext immediate field, codegen
+// this as "d, 0"
+if (Addr == (short)Addr) {
+ Disp = getI32Imm(Addr);
+ Base = CurDAG->getRegister(PPC::R0, MVT::i32);
+ return true;
+}
+
+// Otherwise, break this down into an LIS + disp.
+Disp = getI32Imm((short)Addr);
+Base = CurDAG->getConstant(Addr - (signed short)Addr, MVT::i32);
+return true;
}
+
Disp = getI32Imm(0);
if (FrameIndexSDNode *FI = dyn_cast(N))
Base = CurDAG->getTargetFrameIndex(FI->getIndex(), MVT::i32);
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[llvm-commits] CVS: llvm/utils/TableGen/DAGISelEmitter.cpp
Changes in directory llvm/utils/TableGen:
DAGISelEmitter.cpp updated: 1.179 -> 1.180
---
Log message:
The node wrapped in PatLeaf<> should be treated as a leaf even if it isn't
one, i.e. don't select it.
---
Diffs of the changes: (+11 -4)
DAGISelEmitter.cpp | 15 +++
1 files changed, 11 insertions(+), 4 deletions(-)
Index: llvm/utils/TableGen/DAGISelEmitter.cpp
diff -u llvm/utils/TableGen/DAGISelEmitter.cpp:1.179
llvm/utils/TableGen/DAGISelEmitter.cpp:1.180
--- llvm/utils/TableGen/DAGISelEmitter.cpp:1.179Mon Mar 20 02:09:17 2006
+++ llvm/utils/TableGen/DAGISelEmitter.cpp Mon Mar 20 16:53:06 2006
@@ -2175,7 +2175,7 @@
/// EmitResultCode - Emit the action for a pattern. Now that it has matched
/// we actually have to build a DAG!
std::pair
- EmitResultCode(TreePatternNode *N, bool isRoot = false) {
+ EmitResultCode(TreePatternNode *N, bool LikeLeaf = false, bool isRoot =
false) {
// This is something selected from the pattern we matched.
if (!N->getName().empty()) {
assert(!isRoot && "Root of pattern cannot be a leaf!");
@@ -2257,7 +2257,12 @@
TmpNo = ResNo + NumRes;
} else {
emitDecl("Tmp" + utostr(ResNo));
-emitCode("Select(Tmp" + utostr(ResNo) + ", " + Val + ");");
+// This node, probably wrapped in a SDNodeXForms, behaves like a leaf
+// node even if it isn't one. Don't select it.
+if (LikeLeaf)
+ emitCode("Tmp" + utostr(ResNo) + " = " + Val + ";");
+else
+ emitCode("Select(Tmp" + utostr(ResNo) + ", " + Val + ");");
}
// Add Tmp to VariableMap, so that we don't multiply select this
// value if used multiple times by this pattern result.
@@ -2552,7 +2557,9 @@
return std::make_pair(1, ResNo);
} else if (Op->isSubClassOf("SDNodeXForm")) {
assert(N->getNumChildren() == 1 && "node xform should have one child!");
- unsigned OpVal = EmitResultCode(N->getChild(0)).second;
+ // PatLeaf node - the operand may or may not be a leaf node. But it
should
+ // behave like one.
+ unsigned OpVal = EmitResultCode(N->getChild(0), true).second;
unsigned ResNo = TmpNo++;
emitDecl("Tmp" + utostr(ResNo));
emitCode("Tmp" + utostr(ResNo) + " = Transform_" + Op->getName()
@@ -2748,7 +2755,7 @@
// otherwise we are done.
} while (Emitter.InsertOneTypeCheck(Pat, Pattern.getSrcPattern(), "N"));
- Emitter.EmitResultCode(Pattern.getDstPattern(), true /*the root*/);
+ Emitter.EmitResultCode(Pattern.getDstPattern(), false, true /*the root*/);
delete Pat;
}
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[llvm-commits] CVS: llvm/lib/Target/X86/X86RegisterInfo.td
Changes in directory llvm/lib/Target/X86: X86RegisterInfo.td updated: 1.30 -> 1.31 --- Log message: Junk unused vector register classes. --- Diffs of the changes: (+0 -25) X86RegisterInfo.td | 25 - 1 files changed, 25 deletions(-) Index: llvm/lib/Target/X86/X86RegisterInfo.td diff -u llvm/lib/Target/X86/X86RegisterInfo.td:1.30 llvm/lib/Target/X86/X86RegisterInfo.td:1.31 --- llvm/lib/Target/X86/X86RegisterInfo.td:1.30 Mon Feb 20 19:38:21 2006 +++ llvm/lib/Target/X86/X86RegisterInfo.td Mon Mar 20 18:30:59 2006 @@ -139,31 +139,6 @@ }]; } -// Vector integer registers: V8I8, the 8 x i8 class, V4I16, the 4 x i16 class, -// V2I32, the 2 x i32 class, V16I8, the 16 x i8 class, V8I16, the 8 x i16 class, -// V4I32, the 4 x i32 class, and V2I64, the 2 x i64 class. -def V8I8 : RegisterClass<"X86", [v8i8], 64, - [MM0, MM1, MM2, MM3, MM4, MM5, MM6, MM7]>; -def V4I16 : RegisterClass<"X86", [v4i16], 64, - [MM0, MM1, MM2, MM3, MM4, MM5, MM6, MM7]>; -def V2I32 : RegisterClass<"X86", [v2i32], 64, - [MM0, MM1, MM2, MM3, MM4, MM5, MM6, MM7]>; -def V16I8 : RegisterClass<"X86", [v16i8], 128, - [XMM0, XMM1, XMM2, XMM3, XMM4, XMM5, XMM6, XMM7]>; -def V8I16 : RegisterClass<"X86", [v8i16], 128, - [XMM0, XMM1, XMM2, XMM3, XMM4, XMM5, XMM6, XMM7]>; -def V4I32 : RegisterClass<"X86", [v4i32], 128, - [XMM0, XMM1, XMM2, XMM3, XMM4, XMM5, XMM6, XMM7]>; -def V2I64 : RegisterClass<"X86", [v2i64], 128, - [XMM0, XMM1, XMM2, XMM3, XMM4, XMM5, XMM6, XMM7]>; - -// Vector floating point registers: V4F4, the 4 x f32 class, and V2F8, -// the 2 x f64 class. -def V4F32 : RegisterClass<"X86", [v4f32], 128, - [XMM0, XMM1, XMM2, XMM3, XMM4, XMM5, XMM6, XMM7]>; -def V2F64 : RegisterClass<"X86", [v2f64], 128, - [XMM0, XMM1, XMM2, XMM3, XMM4, XMM5, XMM6, XMM7]>; - // Generic vector registers: VR64 and VR128. def VR64 : RegisterClass<"X86", [v8i8, v4i16, v2i32], 64, [MM0, MM1, MM2, MM3, MM4, MM5, MM6, MM7]>; ___ llvm-commits mailing list llvm-commits@cs.uiuc.edu http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
[llvm-commits] CVS: llvm/lib/Target/X86/X86InstrMMX.td X86InstrSSE.td
Changes in directory llvm/lib/Target/X86:
X86InstrMMX.td updated: 1.3 -> 1.4
X86InstrSSE.td updated: 1.9 -> 1.10
---
Log message:
x86 ISD::SCALAR_TO_VECTOR support.
---
Diffs of the changes: (+54 -0)
X86InstrMMX.td | 18 ++
X86InstrSSE.td | 36
2 files changed, 54 insertions(+)
Index: llvm/lib/Target/X86/X86InstrMMX.td
diff -u llvm/lib/Target/X86/X86InstrMMX.td:1.3
llvm/lib/Target/X86/X86InstrMMX.td:1.4
--- llvm/lib/Target/X86/X86InstrMMX.td:1.3 Mon Mar 20 00:04:52 2006
+++ llvm/lib/Target/X86/X86InstrMMX.td Mon Mar 20 18:33:35 2006
@@ -22,6 +22,24 @@
def : Pat<(v4i16 (undef)), (IMPLICIT_DEF_VR64)>, Requires<[HasMMX]>;
def : Pat<(v2i32 (undef)), (IMPLICIT_DEF_VR64)>, Requires<[HasMMX]>;
+def SCALAR_TO_VECTOR_V8I8 : I<0, Pseudo, (ops VR64:$dst, R8:$src),
+ "#SCALAR_TO_VECTOR $src",
+ [(set VR64:$dst,
+(v8i8 (scalar_to_vector R8:$src)))]>,
+Requires<[HasMMX]>;
+
+def SCALAR_TO_VECTOR_V4I16 : I<0, Pseudo, (ops VR64:$dst, R16:$src),
+ "#SCALAR_TO_VECTOR $src",
+ [(set VR64:$dst,
+ (v4i16 (scalar_to_vector R16:$src)))]>,
+ Requires<[HasMMX]>;
+
+def SCALAR_TO_VECTOR_V2I32 : I<0, Pseudo, (ops VR64:$dst, R32:$src),
+ "#SCALAR_TO_VECTOR $src",
+ [(set VR64:$dst,
+ (v2i32 (scalar_to_vector R32:$src)))]>,
+ Requires<[HasMMX]>;
+
// Move Instructions
def MOVD64rr : I<0x6E, MRMSrcReg, (ops VR64:$dst, R32:$src),
"movd {$src, $dst|$dst, $src}", []>, TB,
Index: llvm/lib/Target/X86/X86InstrSSE.td
diff -u llvm/lib/Target/X86/X86InstrSSE.td:1.9
llvm/lib/Target/X86/X86InstrSSE.td:1.10
--- llvm/lib/Target/X86/X86InstrSSE.td:1.9 Mon Mar 20 00:04:52 2006
+++ llvm/lib/Target/X86/X86InstrSSE.td Mon Mar 20 18:33:35 2006
@@ -353,6 +353,42 @@
def : Pat<(v4i32 (undef)), (IMPLICIT_DEF_VR128)>, Requires<[HasSSE2]>;
def : Pat<(v2i64 (undef)), (IMPLICIT_DEF_VR128)>, Requires<[HasSSE2]>;
+def SCALAR_TO_VECTOR_V4F32 : I<0, Pseudo, (ops VR128:$dst, FR32:$src),
+ "#SCALAR_TO_VECTOR $src",
+ [(set VR128:$dst,
+ (v4f32 (scalar_to_vector FR32:$src)))]>,
+ Requires<[HasSSE1]>;
+
+def SCALAR_TO_VECTOR_V2F64 : I<0, Pseudo, (ops VR128:$dst, FR64:$src),
+ "#SCALAR_TO_VECTOR $src",
+ [(set VR128:$dst,
+ (v2f64 (scalar_to_vector FR64:$src)))]>,
+ Requires<[HasSSE2]>;
+
+def SCALAR_TO_VECTOR_V16I8 : I<0, Pseudo, (ops VR128:$dst, R8:$src),
+ "#SCALAR_TO_VECTOR $src",
+ [(set VR128:$dst,
+ (v16i8 (scalar_to_vector R8:$src)))]>,
+ Requires<[HasSSE2]>;
+
+def SCALAR_TO_VECTOR_V8I16 : I<0, Pseudo, (ops VR128:$dst, R16:$src),
+ "#SCALAR_TO_VECTOR $src",
+ [(set VR128:$dst,
+ (v8i16 (scalar_to_vector R16:$src)))]>,
+ Requires<[HasSSE2]>;
+
+def SCALAR_TO_VECTOR_V4I32 : I<0, Pseudo, (ops VR128:$dst, R32:$src),
+ "#SCALAR_TO_VECTOR $src",
+ [(set VR128:$dst,
+ (v4i32 (scalar_to_vector R32:$src)))]>,
+ Requires<[HasSSE2]>;
+
+def SCALAR_TO_VECTOR_V2I64 : I<0, Pseudo, (ops VR128:$dst, VR64:$src),
+ "#SCALAR_TO_VECTOR $src",
+ [(set VR128:$dst,
+ (v2i64 (scalar_to_vector VR64:$src)))]>,
+ Requires<[HasSSE2]>;
+
// Move Instructions
def MOVAPSrr : PSI<0x28, MRMSrcReg, (ops VR128:$dst, VR128:$src),
"movaps {$src, $dst|$dst, $src}", []>;
___
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[llvm-commits] CVS: llvm/lib/Target/TargetSelectionDAG.td
Changes in directory llvm/lib/Target: TargetSelectionDAG.td updated: 1.54 -> 1.55 --- Log message: x86 ISD::SCALAR_TO_VECTOR support. --- Diffs of the changes: (+2 -0) TargetSelectionDAG.td |2 ++ 1 files changed, 2 insertions(+) Index: llvm/lib/Target/TargetSelectionDAG.td diff -u llvm/lib/Target/TargetSelectionDAG.td:1.54 llvm/lib/Target/TargetSelectionDAG.td:1.55 --- llvm/lib/Target/TargetSelectionDAG.td:1.54 Mon Mar 20 00:18:01 2006 +++ llvm/lib/Target/TargetSelectionDAG.td Mon Mar 20 18:33:35 2006 @@ -308,6 +308,8 @@ def vector_shuffle : SDNode<"ISD::VECTOR_SHUFFLE", SDTVecShuffle, []>; def build_vector : SDNode<"ISD::BUILD_VECTOR", SDTypeProfile<1, 0, []>, []>; +def scalar_to_vector : SDNode<"ISD::SCALAR_TO_VECTOR", SDTypeProfile<1, 1, []>, + []>; //===--===// // Selection DAG Condition Codes ___ llvm-commits mailing list llvm-commits@cs.uiuc.edu http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
[llvm-commits] CVS: llvm/lib/Target/PowerPC/README.txt
Changes in directory llvm/lib/Target/PowerPC: README.txt updated: 1.76 -> 1.77 --- Log message: minor note --- Diffs of the changes: (+3 -0) README.txt |3 +++ 1 files changed, 3 insertions(+) Index: llvm/lib/Target/PowerPC/README.txt diff -u llvm/lib/Target/PowerPC/README.txt:1.76 llvm/lib/Target/PowerPC/README.txt:1.77 --- llvm/lib/Target/PowerPC/README.txt:1.76 Sun Mar 19 16:08:08 2006 +++ llvm/lib/Target/PowerPC/README.txt Mon Mar 20 18:47:09 2006 @@ -519,6 +519,9 @@ We generate relatively atrocious code for this loop compared to gcc. +We could also strength reduce the rem and the div: +http://www.lcs.mit.edu/pubs/pdf/MIT-LCS-TM-600.pdf + ===-=== Altivec support. The first should be a single lvx from the constant pool, the ___ llvm-commits mailing list llvm-commits@cs.uiuc.edu http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
[llvm-commits] CVS: llvm/lib/Target/PowerPC/PPCInstrInfo.td
Changes in directory llvm/lib/Target/PowerPC: PPCInstrInfo.td updated: 1.200 -> 1.201 --- Log message: When codegen'ing vector MUL using VFMADD, *add* the 0, don't *mul* the 0. --- Diffs of the changes: (+1 -1) PPCInstrInfo.td |2 +- 1 files changed, 1 insertion(+), 1 deletion(-) Index: llvm/lib/Target/PowerPC/PPCInstrInfo.td diff -u llvm/lib/Target/PowerPC/PPCInstrInfo.td:1.200 llvm/lib/Target/PowerPC/PPCInstrInfo.td:1.201 --- llvm/lib/Target/PowerPC/PPCInstrInfo.td:1.200 Mon Mar 20 12:26:51 2006 +++ llvm/lib/Target/PowerPC/PPCInstrInfo.td Mon Mar 20 18:51:38 2006 @@ -1123,7 +1123,7 @@ (ADDIS GPRC:$in, tconstpool:$g)>; def : Pat<(fmul VRRC:$vA, VRRC:$vB), - (VMADDFP VRRC:$vA, (V_SET0), VRRC:$vB)>; + (VMADDFP VRRC:$vA, VRRC:$vB, (V_SET0))>; // Fused negative multiply subtract, alternate pattern def : Pat<(fsub F8RC:$B, (fmul F8RC:$A, F8RC:$C)), ___ llvm-commits mailing list llvm-commits@cs.uiuc.edu http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
[llvm-commits] CVS: llvm/Makefile.rules
Changes in directory llvm: Makefile.rules updated: 1.351 -> 1.352 --- Log message: Enable assertions to be enabled in release builds by building with make ENABLE_OPTIMIZED=1 ENABLE_ASSERTIONS=1 --- Diffs of the changes: (+21 -11) Makefile.rules | 32 +--- 1 files changed, 21 insertions(+), 11 deletions(-) Index: llvm/Makefile.rules diff -u llvm/Makefile.rules:1.351 llvm/Makefile.rules:1.352 --- llvm/Makefile.rules:1.351 Fri Mar 10 15:01:34 2006 +++ llvm/Makefile.rules Mon Mar 20 19:06:41 2006 @@ -198,12 +198,11 @@ # Variables derived from configuration we are building # - ifdef ENABLE_PROFILING BuildMode := Profile - CXX.Flags := -O3 -DNDEBUG -felide-constructors -finline-functions -pg - C.Flags := -O3 -DNDEBUG -pg - LD.Flags := -O3 -DNDEBUG -pg + CXX.Flags := -O3 -felide-constructors -finline-functions -pg + C.Flags := -O3 -pg + LD.Flags := -O3 -pg else ifdef ENABLE_OPTIMIZED BuildMode := Release @@ -211,19 +210,30 @@ ifneq ($(OS),FreeBSD) OmitFramePointer := -fomit-frame-pointer endif -CXX.Flags := -O3 -DNDEBUG -finline-functions -felide-constructors \ - $(OmitFramePointer) -C.Flags:= -O3 -DNDEBUG $(OmitFramePointer) -LD.Flags := -O3 -DNDEBUG +CXX.Flags := -O3 -finline-functions -felide-constructors $(OmitFramePointer) +C.Flags := -O3 $(OmitFramePointer) +LD.Flags := -O3 else BuildMode := Debug -CXX.Flags := -g -D_DEBUG -C.Flags := -g -D_DEBUG -LD.Flags := -g -D_DEBUG +CXX.Flags := -g +C.Flags := -g +LD.Flags := -g KEEP_SYMBOLS := 1 +# Assertions default to ON for debug builds. +ENABLE_ASSERTIONS := 1 endif endif +# If this is a debug build or if ENABLE_ASSERTIONS=1 is specified on the make +# command line, enable assertions. +ifdef ENABLE_ASSERTIONS + CXX.Flags += -D_DEBUG + C.Flags += -D_DEBUG +else + CXX.Flags += -DNDEBUG + C.Flags += -DNDEBUG +endif + CXX.Flags += $(CXXFLAGS) C.Flags += $(CFLAGS) CPP.Flags += $(CPPFLAGS) ___ llvm-commits mailing list llvm-commits@cs.uiuc.edu http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
[llvm-commits] CVS: llvm/docs/GettingStarted.html MakefileGuide.html
Changes in directory llvm/docs: GettingStarted.html updated: 1.126 -> 1.127 MakefileGuide.html updated: 1.28 -> 1.29 --- Log message: Document ENABLE_ASSERTIONS=1 --- Diffs of the changes: (+11 -2) GettingStarted.html |7 ++- MakefileGuide.html |6 +- 2 files changed, 11 insertions(+), 2 deletions(-) Index: llvm/docs/GettingStarted.html diff -u llvm/docs/GettingStarted.html:1.126 llvm/docs/GettingStarted.html:1.127 --- llvm/docs/GettingStarted.html:1.126 Mon Mar 13 23:39:39 2006 +++ llvm/docs/GettingStarted.html Mon Mar 20 19:10:57 2006 @@ -955,6 +955,11 @@ Perform a Release (Optimized) build. + gmake ENABLE_OPTIMIZED=1 ENABLE_ASSERTIONS=1 + + Perform a Release (Optimized) build with assertions enabled. + + gmake ENABLE_PROFILING=1 Perform a Profiling build. @@ -1546,7 +1551,7 @@ mailto:[EMAIL PROTECTED]">Chris Lattner http://llvm.x10sys.com/rspencer/";>Reid Spencer http://llvm.org";>The LLVM Compiler Infrastructure - Last modified: $Date: 2006/03/14 05:39:39 $ + Last modified: $Date: 2006/03/21 01:10:57 $ Index: llvm/docs/MakefileGuide.html diff -u llvm/docs/MakefileGuide.html:1.28 llvm/docs/MakefileGuide.html:1.29 --- llvm/docs/MakefileGuide.html:1.28 Mon Mar 13 23:39:39 2006 +++ llvm/docs/MakefileGuide.htmlMon Mar 20 19:10:57 2006 @@ -632,6 +632,10 @@ to the compilers and linkers to ensure that profile data can be collected from the tools built. Use the gprof tool to analyze the output from the profiled tools (gmon.out). +ENABLE_ASSERTIONS +If set to any value, causes the build to enable assertions, even if +building a release or profile build. This is slower than a release build but +far faster than a debug build. EXPERIMENTAL_DIRS Specify a set of directories that should be built, but if they fail, it should not cause the build to fail. Note that this should only be used @@ -991,7 +995,7 @@ mailto:[EMAIL PROTECTED]">Reid Spencer http://llvm.org";>The LLVM Compiler Infrastructure - Last modified: $Date: 2006/03/14 05:39:39 $ + Last modified: $Date: 2006/03/21 01:10:57 $ ___ llvm-commits mailing list llvm-commits@cs.uiuc.edu http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
[llvm-commits] CVS: llvm/utils/NightlyTestTemplate.html NightlyTest.pl
Changes in directory llvm/utils:
NightlyTestTemplate.html updated: 1.44 -> 1.45
NightlyTest.pl updated: 1.105 -> 1.106
---
Log message:
Cause the various warnings list to be generated via a list with
text enclosed in . This ensures that (a) the text is in a fixed width
font (to indicated generated text) and (b) the text wraps without causing
the page width to be extended. The main result of this is that the report
will wrap to conform to the window size in which it is displayed instead of
having a very wide length if a warning message is long.
---
Diffs of the changes: (+25 -9)
NightlyTest.pl | 24
NightlyTestTemplate.html | 10 +-
2 files changed, 25 insertions(+), 9 deletions(-)
Index: llvm/utils/NightlyTestTemplate.html
diff -u llvm/utils/NightlyTestTemplate.html:1.44
llvm/utils/NightlyTestTemplate.html:1.45
--- llvm/utils/NightlyTestTemplate.html:1.44Mon Mar 13 23:54:52 2006
+++ llvm/utils/NightlyTestTemplate.html Mon Mar 20 19:21:39 2006
@@ -77,7 +77,7 @@
Warnings during the build:
-$WarningsList
+$WarningsList
@@ -95,10 +95,10 @@
Changes to Warnings:
-
-Warnings Added: $WarningsAdded
-Warnings Removed: $WarningsRemoved
-
+Warnings Added:
+$WarningsAdded
+Warnings Removed:
+$WarningsRemoved
Changes in the test suite:
Index: llvm/utils/NightlyTest.pl
diff -u llvm/utils/NightlyTest.pl:1.105 llvm/utils/NightlyTest.pl:1.106
--- llvm/utils/NightlyTest.pl:1.105 Fri Mar 17 11:43:01 2006
+++ llvm/utils/NightlyTest.pl Mon Mar 20 19:21:39 2006
@@ -151,7 +151,21 @@
sub AddPreTag { # Add pre tags around nonempty list, or convert to "none"
$_ = shift;
- if (length) { return "$_"; } else { "none"; }
+ if (length) { return "$_"; } else { "none"; }
+}
+
+sub ArrayToList { # Add tags around nonempty list or convert to "none"
+ my $result = "";
+ if (scalar @_) {
+$result = "";
+foreach $item (@_) {
+ $result .= "$item";
+}
+$result .= "";
+ } else {
+$result = "none";
+ }
+ return $result;
}
sub ChangeDir { # directory, logical name
@@ -528,7 +542,7 @@
}
}
my $WarningsFile = join "\n", @Warnings;
-my $WarningsList = AddPreTag $WarningsFile;
+my $WarningsList = ArrayToList @Warnings;
$WarningsFile =~ s/:[0-9]+:/::/g;
# Emit the warnings file, so we can diff...
@@ -539,8 +553,10 @@
print "ADDED WARNINGS:\n$WarningsAdded\n\n" if (length $WarningsAdded);
print "REMOVED WARNINGS:\n$WarningsRemoved\n\n" if (length $WarningsRemoved);
-$WarningsAdded = AddPreTag $WarningsAdded;
-$WarningsRemoved = AddPreTag $WarningsRemoved;
+my @TmpWarningsAdded = split "\n", $WarningsAdded;
+my @TmpWarningsRemoved = split "\n", $WarningsRemoved;
+$WarningsAdded = ArrayToList @TmpWarningsAdded;
+$WarningsRemoved = ArrayToList @TmpWarningsRemoved;
#
# Get some statistics about CVS commits over the current day...
___
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[llvm-commits] CVS: llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp
Changes in directory llvm/lib/Target/PowerPC:
PPCISelDAGToDAG.cpp updated: 1.173 -> 1.174
---
Log message:
With Evan's latest tblgen patch, this code is obsolete, thanks Evan!
---
Diffs of the changes: (+0 -16)
PPCISelDAGToDAG.cpp | 16
1 files changed, 16 deletions(-)
Index: llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp
diff -u llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp:1.173
llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp:1.174
--- llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp:1.173 Mon Mar 20 16:38:22 2006
+++ llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp Tue Mar 21 00:37:40 2006
@@ -944,22 +944,6 @@
switch (N->getOpcode()) {
default: break;
- case ISD::VECTOR_SHUFFLE:
-// FIXME: This should be autogenerated from the .td file, it is here for
now
-// due to bugs in tblgen.
-if (Op.getOperand(1).getOpcode() == ISD::UNDEF &&
-(Op.getValueType() == MVT::v4f32 || Op.getValueType() == MVT::v4i32) &&
-PPC::isSplatShuffleMask(Op.getOperand(2).Val)) {
- SDOperand N0;
- Select(N0, N->getOperand(0));
- Result = CodeGenMap[Op] =
-SDOperand(CurDAG->getTargetNode(PPC::VSPLTW, MVT::v4f32,
-
getI32Imm(PPC::getVSPLTImmediate(Op.getOperand(2).Val)),
-N0), 0);
- return;
-}
-assert(0 && "ILLEGAL VECTOR_SHUFFLE!");
-
case ISD::SETCC:
Result = SelectSETCC(Op);
return;
___
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[llvm-commits] CVS: llvm/utils/TableGen/DAGISelEmitter.cpp
Changes in directory llvm/utils/TableGen:
DAGISelEmitter.cpp updated: 1.180 -> 1.181
---
Log message:
minor code simplification
---
Diffs of the changes: (+5 -11)
DAGISelEmitter.cpp | 16 +---
1 files changed, 5 insertions(+), 11 deletions(-)
Index: llvm/utils/TableGen/DAGISelEmitter.cpp
diff -u llvm/utils/TableGen/DAGISelEmitter.cpp:1.180
llvm/utils/TableGen/DAGISelEmitter.cpp:1.181
--- llvm/utils/TableGen/DAGISelEmitter.cpp:1.180Mon Mar 20 16:53:06 2006
+++ llvm/utils/TableGen/DAGISelEmitter.cpp Tue Mar 21 00:42:58 2006
@@ -698,17 +698,11 @@
if (getNumChildren() != 1)
TP.error("Node transform '" + getOperator()->getName() +
"' requires one operand!");
-unsigned char ExtType0 = getExtTypeNum(0);
-unsigned char ChildExtType0 = getChild(0)->getExtTypeNum(0);
-if (ExtType0 == MVT::isInt ||
-ExtType0 == MVT::isFP ||
-ExtType0 == MVT::isUnknown ||
-ChildExtType0 == MVT::isInt ||
-ChildExtType0 == MVT::isFP ||
-ChildExtType0 == MVT::isUnknown) {
- // If either the output or input of the xform does not have exact
- // type info. We assume they must be the same. Otherwise, it is perfectly
- // legal to transform from one type to a completely different type.
+
+// If either the output or input of the xform does not have exact
+// type info. We assume they must be the same. Otherwise, it is perfectly
+// legal to transform from one type to a completely different type.
+if (!hasTypeSet() || !getChild(0)->hasTypeSet()) {
bool MadeChange = UpdateNodeType(getChild(0)->getExtTypes(), TP);
MadeChange |= getChild(0)->UpdateNodeType(getExtTypes(), TP);
return MadeChange;
___
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[llvm-commits] CVS: llvm/lib/Target/X86/X86InstrInfo.cpp X86InstrMMX.td X86InstrSSE.td
Changes in directory llvm/lib/Target/X86:
X86InstrInfo.cpp updated: 1.45 -> 1.46
X86InstrMMX.td updated: 1.4 -> 1.5
X86InstrSSE.td updated: 1.10 -> 1.11
---
Log message:
- Remove scalar to vector pseudo ops. They are just wrong.
- Handle FR32 to VR128:v4f32 and FR64 to VR128:v2f64 with aliases of MOVAPS
and MOVAPD. Mark them as move instructions and *hope* they will be deleted.
---
Diffs of the changes: (+17 -56)
X86InstrInfo.cpp |3 ++-
X86InstrMMX.td | 19 ---
X86InstrSSE.td | 51 +++
3 files changed, 17 insertions(+), 56 deletions(-)
Index: llvm/lib/Target/X86/X86InstrInfo.cpp
diff -u llvm/lib/Target/X86/X86InstrInfo.cpp:1.45
llvm/lib/Target/X86/X86InstrInfo.cpp:1.46
--- llvm/lib/Target/X86/X86InstrInfo.cpp:1.45 Thu Feb 16 16:45:16 2006
+++ llvm/lib/Target/X86/X86InstrInfo.cppTue Mar 21 01:09:35 2006
@@ -30,7 +30,8 @@
if (oc == X86::MOV8rr || oc == X86::MOV16rr || oc == X86::MOV32rr ||
oc == X86::FpMOV || oc == X86::MOVSSrr || oc == X86::MOVSDrr ||
oc == X86::FsMOVAPSrr || oc == X86::FsMOVAPDrr ||
- oc == X86::MOVAPSrr || oc == X86::MOVAPDrr) {
+ oc == X86::MOVAPSrr || oc == X86::MOVAPDrr ||
+ oc == X86::FR32ToV4F32 || oc == X86::FR64ToV2F64) {
assert(MI.getNumOperands() == 2 &&
MI.getOperand(0).isRegister() &&
MI.getOperand(1).isRegister() &&
Index: llvm/lib/Target/X86/X86InstrMMX.td
diff -u llvm/lib/Target/X86/X86InstrMMX.td:1.4
llvm/lib/Target/X86/X86InstrMMX.td:1.5
--- llvm/lib/Target/X86/X86InstrMMX.td:1.4 Mon Mar 20 18:33:35 2006
+++ llvm/lib/Target/X86/X86InstrMMX.td Tue Mar 21 01:09:35 2006
@@ -22,24 +22,6 @@
def : Pat<(v4i16 (undef)), (IMPLICIT_DEF_VR64)>, Requires<[HasMMX]>;
def : Pat<(v2i32 (undef)), (IMPLICIT_DEF_VR64)>, Requires<[HasMMX]>;
-def SCALAR_TO_VECTOR_V8I8 : I<0, Pseudo, (ops VR64:$dst, R8:$src),
- "#SCALAR_TO_VECTOR $src",
- [(set VR64:$dst,
-(v8i8 (scalar_to_vector R8:$src)))]>,
-Requires<[HasMMX]>;
-
-def SCALAR_TO_VECTOR_V4I16 : I<0, Pseudo, (ops VR64:$dst, R16:$src),
- "#SCALAR_TO_VECTOR $src",
- [(set VR64:$dst,
- (v4i16 (scalar_to_vector R16:$src)))]>,
- Requires<[HasMMX]>;
-
-def SCALAR_TO_VECTOR_V2I32 : I<0, Pseudo, (ops VR64:$dst, R32:$src),
- "#SCALAR_TO_VECTOR $src",
- [(set VR64:$dst,
- (v2i32 (scalar_to_vector R32:$src)))]>,
- Requires<[HasMMX]>;
-
// Move Instructions
def MOVD64rr : I<0x6E, MRMSrcReg, (ops VR64:$dst, R32:$src),
"movd {$src, $dst|$dst, $src}", []>, TB,
@@ -60,4 +42,3 @@
def MOVQ64mr : I<0x7F, MRMDestMem, (ops i64mem:$dst, VR64:$src),
"movq {$src, $dst|$dst, $src}", []>, TB,
Requires<[HasMMX]>;
-
Index: llvm/lib/Target/X86/X86InstrSSE.td
diff -u llvm/lib/Target/X86/X86InstrSSE.td:1.10
llvm/lib/Target/X86/X86InstrSSE.td:1.11
--- llvm/lib/Target/X86/X86InstrSSE.td:1.10 Mon Mar 20 18:33:35 2006
+++ llvm/lib/Target/X86/X86InstrSSE.td Tue Mar 21 01:09:35 2006
@@ -353,42 +353,6 @@
def : Pat<(v4i32 (undef)), (IMPLICIT_DEF_VR128)>, Requires<[HasSSE2]>;
def : Pat<(v2i64 (undef)), (IMPLICIT_DEF_VR128)>, Requires<[HasSSE2]>;
-def SCALAR_TO_VECTOR_V4F32 : I<0, Pseudo, (ops VR128:$dst, FR32:$src),
- "#SCALAR_TO_VECTOR $src",
- [(set VR128:$dst,
- (v4f32 (scalar_to_vector FR32:$src)))]>,
- Requires<[HasSSE1]>;
-
-def SCALAR_TO_VECTOR_V2F64 : I<0, Pseudo, (ops VR128:$dst, FR64:$src),
- "#SCALAR_TO_VECTOR $src",
- [(set VR128:$dst,
- (v2f64 (scalar_to_vector FR64:$src)))]>,
- Requires<[HasSSE2]>;
-
-def SCALAR_TO_VECTOR_V16I8 : I<0, Pseudo, (ops VR128:$dst, R8:$src),
- "#SCALAR_TO_VECTOR $src",
- [(set VR128:$dst,
- (v16i8 (scalar_to_vector R8:$src)))]>,
- Requires<[HasSSE2]>;
-
-def SCALAR_TO_VECTOR_V8I16 : I<0, Pseudo, (ops VR128:$dst, R16:$src),
- "#SCALAR_TO_VECTOR $src",
- [(set VR128:$dst,
- (v8i16 (scalar_to_vector R16:$src)))]>,
- Requires<[HasSSE2]>;
-
-def SCALAR_TO_VECTOR_V4I32 : I<0, Pseudo, (ops VR128:$dst, R32:$src),
- "#SCALAR_TO_VECTOR $src",
- [(set VR128:$dst,
- (v4i32 (scalar_to_vector R32:$sr
[llvm-commits] CVS: llvm/lib/Target/X86/README.txt
Changes in directory llvm/lib/Target/X86: README.txt updated: 1.68 -> 1.69 --- Log message: Add a note about x86 register coallescing --- Diffs of the changes: (+2 -0) README.txt |2 ++ 1 files changed, 2 insertions(+) Index: llvm/lib/Target/X86/README.txt diff -u llvm/lib/Target/X86/README.txt:1.68 llvm/lib/Target/X86/README.txt:1.69 --- llvm/lib/Target/X86/README.txt:1.68 Sun Mar 19 16:27:41 2006 +++ llvm/lib/Target/X86/README.txt Tue Mar 21 01:12:57 2006 @@ -644,3 +644,5 @@ //===-===// +Teach the coallescer to coales vregs of different register classes. e.g. FR32 / +FR64 to VR128. ___ llvm-commits mailing list llvm-commits@cs.uiuc.edu http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
[llvm-commits] CVS: llvm/lib/Target/X86/README.txt
Changes in directory llvm/lib/Target/X86:
README.txt updated: 1.69 -> 1.70
---
Log message:
Combine 2 entries
---
Diffs of the changes: (+6 -8)
README.txt | 14 ++
1 files changed, 6 insertions(+), 8 deletions(-)
Index: llvm/lib/Target/X86/README.txt
diff -u llvm/lib/Target/X86/README.txt:1.69 llvm/lib/Target/X86/README.txt:1.70
--- llvm/lib/Target/X86/README.txt:1.69 Tue Mar 21 01:12:57 2006
+++ llvm/lib/Target/X86/README.txt Tue Mar 21 01:18:26 2006
@@ -485,6 +485,12 @@
//===-===//
+Should generate min/max for stuff like:
+
+void minf(float a, float b, float *X) {
+ *X = a <= b ? a : b;
+}
+
Make use of floating point min / max instructions. Perhaps introduce ISD::FMIN
and ISD::FMAX node types?
@@ -636,13 +642,5 @@
//===-===//
-Should generate min/max for stuff like:
-
-void minf(float a, float b, float *X) {
- *X = a <= b ? a : b;
-}
-
-//===-===//
-
Teach the coallescer to coales vregs of different register classes. e.g. FR32 /
FR64 to VR128.
___
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llvm-commits@cs.uiuc.edu
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