Changes in directory llvm/lib/Target/PowerPC:
PPCISelDAGToDAG.cpp updated: 1.171 -> 1.172
---
Log message:
reenable this hack, the tblgen version isn't quite ready
---
Diffs of the changes: (+16 -0)
PPCISelDAGToDAG.cpp | 16 ++++++++++++++++
1 files changed, 16 insertions(+)
Index: llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp
diff -u llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp:1.171
llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp:1.172
--- llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp:1.171 Mon Mar 20 02:14:16 2006
+++ llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp Mon Mar 20 11:54:43 2006
@@ -927,6 +927,22 @@
switch (N->getOpcode()) {
default: break;
+ case ISD::VECTOR_SHUFFLE:
+ // FIXME: This should be autogenerated from the .td file, it is here for
now
+ // due to bugs in tblgen.
+ if (Op.getOperand(1).getOpcode() == ISD::UNDEF &&
+ (Op.getValueType() == MVT::v4f32 || Op.getValueType() == MVT::v4i32) &&
+ PPC::isSplatShuffleMask(Op.getOperand(2).Val)) {
+ SDOperand N0;
+ Select(N0, N->getOperand(0));
+ Result = CodeGenMap[Op] =
+ SDOperand(CurDAG->getTargetNode(PPC::VSPLTW, MVT::v4f32,
+
getI32Imm(PPC::getVSPLTImmediate(Op.getOperand(2).Val)),
+ N0), 0);
+ return;
+ }
+ assert(0 && "ILLEGAL VECTOR_SHUFFLE!");
+
case ISD::SETCC:
Result = SelectSETCC(Op);
return;
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