[llvm-commits] CVS: llvm/lib/Target/Sparc/SparcInstrInfo.td
Changes in directory llvm/lib/Target/Sparc:
SparcInstrInfo.td updated: 1.122 -> 1.123
---
Log message:
The HasNoV9 hack isn't needed here, now that tblgen knows that
CustomDAGSchedInserter
instructions are expensive.
---
Diffs of the changes: (+2 -3)
SparcInstrInfo.td |5 ++---
1 files changed, 2 insertions(+), 3 deletions(-)
Index: llvm/lib/Target/Sparc/SparcInstrInfo.td
diff -u llvm/lib/Target/Sparc/SparcInstrInfo.td:1.122
llvm/lib/Target/Sparc/SparcInstrInfo.td:1.123
--- llvm/lib/Target/Sparc/SparcInstrInfo.td:1.122 Thu Feb 16 23:43:56 2006
+++ llvm/lib/Target/Sparc/SparcInstrInfo.td Tue Feb 21 12:04:32 2006
@@ -191,7 +191,7 @@
// FpMOVD/FpNEGD/FpABSD - These are lowered to single-precision ops by the
// fpmover pass.
-let Predicates = [HasNoV9] in { // Only emit these in SP mode.
+let Predicates = [HasNoV9] in { // Only emit these in V8 mode.
def FpMOVD : Pseudo<(ops DFPRegs:$dst, DFPRegs:$src),
"!FpMOVD $src, $dst", []>;
def FpNEGD : Pseudo<(ops DFPRegs:$dst, DFPRegs:$src),
@@ -205,8 +205,7 @@
// SELECT_CC_* - Used to implement the SELECT_CC DAG operation. Expanded by
the
// scheduler into a branch sequence. This has to handle all permutations of
// selection between i32/f32/f64 on ICC and FCC.
-let usesCustomDAGSchedInserter = 1,// Expanded by the scheduler.
-Predicates = [HasNoV9] in {// V9 has conditional moves
+let usesCustomDAGSchedInserter = 1 in { // Expanded by the scheduler.
def SELECT_CC_Int_ICC
: Pseudo<(ops IntRegs:$dst, IntRegs:$T, IntRegs:$F, i32imm:$Cond),
"; SELECT_CC_Int_ICC PSEUDO!",
___
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[llvm-commits] CVS: llvm/lib/Target/README.txt
Changes in directory llvm/lib/Target:
README.txt updated: 1.7 -> 1.8
---
Log message:
missed optzn
---
Diffs of the changes: (+11 -0)
README.txt | 11 +++
1 files changed, 11 insertions(+)
Index: llvm/lib/Target/README.txt
diff -u llvm/lib/Target/README.txt:1.7 llvm/lib/Target/README.txt:1.8
--- llvm/lib/Target/README.txt:1.7 Wed Feb 15 16:14:34 2006
+++ llvm/lib/Target/README.txt Tue Feb 21 12:29:44 2006
@@ -68,3 +68,14 @@
This sort of thing occurs in the alloca lowering code and other places that
are generating alignment of an already aligned value.
+//===-===//
+
+Turn this into a signed shift right in instcombine:
+
+int f(unsigned x) {
+ return x >> 31 ? -1 : 0;
+}
+
+http://gcc.gnu.org/bugzilla/show_bug.cgi?id=25600
+http://gcc.gnu.org/ml/gcc-patches/2006-02/msg01492.html
+
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[llvm-commits] CVS: llvm/lib/Target/X86/X86InstrFPStack.td X86InstrInfo.td X86InstrSSE.td
Changes in directory llvm/lib/Target/X86:
X86InstrFPStack.td updated: 1.1 -> 1.2
X86InstrInfo.td updated: 1.243 -> 1.244
X86InstrSSE.td updated: 1.1 -> 1.2
---
Log message:
Moving things to their proper places.
---
Diffs of the changes: (+303 -303)
X86InstrFPStack.td | 101 -
X86InstrInfo.td| 202 ---
X86InstrSSE.td | 303 +
3 files changed, 303 insertions(+), 303 deletions(-)
Index: llvm/lib/Target/X86/X86InstrFPStack.td
diff -u llvm/lib/Target/X86/X86InstrFPStack.td:1.1
llvm/lib/Target/X86/X86InstrFPStack.td:1.2
--- llvm/lib/Target/X86/X86InstrFPStack.td:1.1 Tue Feb 21 13:13:53 2006
+++ llvm/lib/Target/X86/X86InstrFPStack.td Tue Feb 21 13:26:52 2006
@@ -379,104 +379,3 @@
(ops i16mem:$dst), "fnstcw $dst", []>;
def FLDCW16m : I<0xD9, MRM5m, // X87 control world = [mem16]
(ops i16mem:$dst), "fldcw $dst", []>;
-
-
-//===--===//
-// Alias Instructions
-//===--===//
-
-// Alias instructions that map fld0 to pxor for sse.
-// FIXME: remove when we can teach regalloc that xor reg, reg is ok.
-def FsFLD0SS : I<0xEF, MRMInitReg, (ops FR32:$dst),
- "pxor $dst, $dst", [(set FR32:$dst, fp32imm0)]>,
- Requires<[HasSSE1]>, TB, OpSize;
-def FsFLD0SD : I<0xEF, MRMInitReg, (ops FR64:$dst),
- "pxor $dst, $dst", [(set FR64:$dst, fp64imm0)]>,
- Requires<[HasSSE2]>, TB, OpSize;
-
-// Alias instructions to do FR32 / FR64 reg-to-reg copy using movaps / movapd.
-// Upper bits are disregarded.
-def FsMOVAPSrr : I<0x28, MRMSrcReg, (ops V4F32:$dst, V4F32:$src),
- "movaps {$src, $dst|$dst, $src}", []>,
- Requires<[HasSSE1]>, TB;
-def FsMOVAPDrr : I<0x28, MRMSrcReg, (ops V2F64:$dst, V2F64:$src),
- "movapd {$src, $dst|$dst, $src}", []>,
- Requires<[HasSSE2]>, TB, OpSize;
-
-// Alias instructions to load FR32 / FR64 from f128mem using movaps / movapd.
-// Upper bits are disregarded.
-def FsMOVAPSrm : I<0x28, MRMSrcMem, (ops FR32:$dst, f128mem:$src),
- "movaps {$src, $dst|$dst, $src}",
- [(set FR32:$dst, (X86loadpf32 addr:$src))]>,
- Requires<[HasSSE1]>, TB;
-def FsMOVAPDrm : I<0x28, MRMSrcMem, (ops FR64:$dst, f128mem:$src),
- "movapd {$src, $dst|$dst, $src}",
- [(set FR64:$dst, (X86loadpf64 addr:$src))]>,
-Requires<[HasSSE2]>, TB, OpSize;
-
-// Alias bitwise logical operations using SSE logical ops on packed FP values.
-let isTwoAddress = 1 in {
-let isCommutable = 1 in {
-def FsANDPSrr : I<0x54, MRMSrcReg, (ops FR32:$dst, FR32:$src1, FR32:$src2),
- "andps {$src2, $dst|$dst, $src2}",
- [(set FR32:$dst, (X86fand FR32:$src1, FR32:$src2))]>,
-Requires<[HasSSE1]>, TB;
-def FsANDPDrr : I<0x54, MRMSrcReg, (ops FR64:$dst, FR64:$src1, FR64:$src2),
- "andpd {$src2, $dst|$dst, $src2}",
- [(set FR64:$dst, (X86fand FR64:$src1, FR64:$src2))]>,
-Requires<[HasSSE2]>, TB, OpSize;
-def FsORPSrr : I<0x56, MRMSrcReg, (ops FR32:$dst, FR32:$src1, FR32:$src2),
- "orps {$src2, $dst|$dst, $src2}", []>,
- Requires<[HasSSE1]>, TB;
-def FsORPDrr : I<0x56, MRMSrcReg, (ops FR64:$dst, FR64:$src1, FR64:$src2),
- "orpd {$src2, $dst|$dst, $src2}", []>,
- Requires<[HasSSE2]>, TB, OpSize;
-def FsXORPSrr : I<0x57, MRMSrcReg, (ops FR32:$dst, FR32:$src1, FR32:$src2),
- "xorps {$src2, $dst|$dst, $src2}",
- [(set FR32:$dst, (X86fxor FR32:$src1, FR32:$src2))]>,
-Requires<[HasSSE1]>, TB;
-def FsXORPDrr : I<0x57, MRMSrcReg, (ops FR64:$dst, FR64:$src1, FR64:$src2),
- "xorpd {$src2, $dst|$dst, $src2}",
- [(set FR64:$dst, (X86fxor FR64:$src1, FR64:$src2))]>,
-Requires<[HasSSE2]>, TB, OpSize;
-}
-def FsANDPSrm : I<0x54, MRMSrcMem, (ops FR32:$dst, FR32:$src1, f128mem:$src2),
- "andps {$src2, $dst|$dst, $src2}",
- [(set FR32:$dst, (X86fand FR32:$src1,
-(X86loadpf32 addr:$src2)))]>,
-Requires<[HasSSE1]>, TB;
-def FsANDPDrm : I<0x54, MRMSrcMem, (ops FR64:$dst, FR64:$src1, f128mem:$src2),
- "andpd {$src2, $dst|$dst, $src2}",
- [(set FR64:$dst, (X86fand FR64:$src1,
-(X86loadpf64 addr:$src2)))]>,
-Requires<[HasSSE2]>, TB, OpSize;
-def FsORPSrm : I<0x56, MRMSrcMem, (ops FR32:$dst, FR32:$src1, f128mem:$src2),
- "orps {$src2, $dst|$dst, $src2}", []>,
- Requires<[HasSSE1]>, TB;
-def FsORPDrm : I<0
[llvm-commits] CVS: llvm/lib/Target/X86/X86InstrInfo.td X86InstrSSE.td
Changes in directory llvm/lib/Target/X86:
X86InstrInfo.td updated: 1.244 -> 1.245
X86InstrSSE.td updated: 1.2 -> 1.3
---
Log message:
A big more cleaning up.
---
Diffs of the changes: (+18 -23)
X86InstrInfo.td | 37 ++---
X86InstrSSE.td |4
2 files changed, 18 insertions(+), 23 deletions(-)
Index: llvm/lib/Target/X86/X86InstrInfo.td
diff -u llvm/lib/Target/X86/X86InstrInfo.td:1.244
llvm/lib/Target/X86/X86InstrInfo.td:1.245
--- llvm/lib/Target/X86/X86InstrInfo.td:1.244 Tue Feb 21 13:26:52 2006
+++ llvm/lib/Target/X86/X86InstrInfo.td Tue Feb 21 13:30:30 2006
@@ -2367,31 +2367,12 @@
[(set R32:$dst, (zextloadi32i16 addr:$src))]>, TB;
//===--===//
-// Floating Point Stack Support
-//===--===//
-
-include "X86InstrFPStack.td"
-
-//===--===//
-// MMX and XMM Packed Integer support (requires MMX, SSE, and SSE2)
-//===--===//
-
-include "X86InstrMMX.td"
-
-//===--===//
-// XMM Packed Floating point support (requires SSE / SSE2)
-//===--===//
-
-include "X86InstrSSE.td"
-
-//===--===//
// Miscellaneous Instructions
//===--===//
def RDTSC : I<0x31, RawFrm, (ops), "rdtsc", [(X86rdtsc)]>,
TB, Imp<[],[EAX,EDX]>;
-
//===--===//
// Alias Instructions
//===--===//
@@ -2409,6 +2390,24 @@
[(set R32:$dst, 0)]>;
//===--===//
+// Floating Point Stack Support
+//===--===//
+
+include "X86InstrFPStack.td"
+
+//===--===//
+// MMX and XMM Packed Integer support (requires MMX, SSE, and SSE2)
+//===--===//
+
+include "X86InstrMMX.td"
+
+//===--===//
+// XMM Floating point support (requires SSE / SSE2)
+//===--===//
+
+include "X86InstrSSE.td"
+
+//===--===//
// Non-Instruction Patterns
//===--===//
Index: llvm/lib/Target/X86/X86InstrSSE.td
diff -u llvm/lib/Target/X86/X86InstrSSE.td:1.2
llvm/lib/Target/X86/X86InstrSSE.td:1.3
--- llvm/lib/Target/X86/X86InstrSSE.td:1.2 Tue Feb 21 13:26:52 2006
+++ llvm/lib/Target/X86/X86InstrSSE.td Tue Feb 21 13:30:30 2006
@@ -100,10 +100,6 @@
Requires<[HasSSE2]>, TB, OpSize;
}
-//===--===//
-// XMM Floating point support (requires SSE / SSE2)
-//===--===//
-
def MOVSSrr : I<0x10, MRMSrcReg, (ops FR32:$dst, FR32:$src),
"movss {$src, $dst|$dst, $src}", []>,
Requires<[HasSSE1]>, XS;
___
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[llvm-commits] CVS: llvm/lib/Target/X86/X86InstrFPStack.td X86InstrInfo.td X86InstrMMX.td X86InstrSSE.td
Changes in directory llvm/lib/Target/X86:
X86InstrFPStack.td updated: 1.2 -> 1.3
X86InstrInfo.td updated: 1.245 -> 1.246
X86InstrMMX.td updated: 1.1 -> 1.2
X86InstrSSE.td updated: 1.3 -> 1.4
---
Log message:
One more round of reorg so sabre doesn't freak out. :-)
---
Diffs of the changes: (+240 -222)
X86InstrFPStack.td | 39 ++
X86InstrInfo.td| 94 +++-
X86InstrMMX.td | 22 ---
X86InstrSSE.td | 307 +++--
4 files changed, 240 insertions(+), 222 deletions(-)
Index: llvm/lib/Target/X86/X86InstrFPStack.td
diff -u llvm/lib/Target/X86/X86InstrFPStack.td:1.2
llvm/lib/Target/X86/X86InstrFPStack.td:1.3
--- llvm/lib/Target/X86/X86InstrFPStack.td:1.2 Tue Feb 21 13:26:52 2006
+++ llvm/lib/Target/X86/X86InstrFPStack.td Tue Feb 21 14:00:20 2006
@@ -13,6 +13,26 @@
//
//===--===//
+// Some 'special' instructions
+let usesCustomDAGSchedInserter = 1 in { // Expanded by the scheduler.
+ def FP_TO_INT16_IN_MEM : I<0, Pseudo,
+(ops i16mem:$dst, RFP:$src),
+ "#FP_TO_INT16_IN_MEM PSEUDO!",
+ [(X86fp_to_i16mem RFP:$src, addr:$dst)]>;
+ def FP_TO_INT32_IN_MEM : I<0, Pseudo,
+(ops i32mem:$dst, RFP:$src),
+ "#FP_TO_INT32_IN_MEM PSEUDO!",
+ [(X86fp_to_i32mem RFP:$src, addr:$dst)]>;
+ def FP_TO_INT64_IN_MEM : I<0, Pseudo,
+(ops i64mem:$dst, RFP:$src),
+ "#FP_TO_INT64_IN_MEM PSEUDO!",
+ [(X86fp_to_i64mem RFP:$src, addr:$dst)]>;
+}
+
+let isTerminator = 1 in
+ let Defs = [FP0, FP1, FP2, FP3, FP4, FP5, FP6] in
+def FP_REG_KILL : I<0, Pseudo, (ops), "#FP_REG_KILL", []>;
+
// All FP Stack operations are represented with two instructions here. The
// first instruction, generated by the instruction selector, uses "RFP"
// registers: a traditional register file to reference floating point values.
@@ -379,3 +399,22 @@
(ops i16mem:$dst), "fnstcw $dst", []>;
def FLDCW16m : I<0xD9, MRM5m, // X87 control world = [mem16]
(ops i16mem:$dst), "fldcw $dst", []>;
+
+//===--===//
+// Non-Instruction Patterns
+//===--===//
+
+// Required for RET of f32 / f64 values.
+def : Pat<(X86fld addr:$src, f32), (FpLD32m addr:$src)>;
+def : Pat<(X86fld addr:$src, f64), (FpLD64m addr:$src)>;
+
+// Required for CALL which return f32 / f64 values.
+def : Pat<(X86fst RFP:$src, addr:$op, f32), (FpST32m addr:$op, RFP:$src)>;
+def : Pat<(X86fst RFP:$src, addr:$op, f64), (FpST64m addr:$op, RFP:$src)>;
+
+// Floating point constant -0.0 and -1.0
+def : Pat<(f64 fp64immneg0), (FpCHS (FpLD0))>, Requires<[FPStack]>;
+def : Pat<(f64 fp64immneg1), (FpCHS (FpLD1))>, Requires<[FPStack]>;
+
+// Used to conv. i64 to f64 since there isn't a SSE version.
+def : Pat<(X86fildflag addr:$src, i64), (FpILD64m addr:$src)>;
Index: llvm/lib/Target/X86/X86InstrInfo.td
diff -u llvm/lib/Target/X86/X86InstrInfo.td:1.245
llvm/lib/Target/X86/X86InstrInfo.td:1.246
--- llvm/lib/Target/X86/X86InstrInfo.td:1.245 Tue Feb 21 13:30:30 2006
+++ llvm/lib/Target/X86/X86InstrInfo.td Tue Feb 21 14:00:20 2006
@@ -403,47 +403,6 @@
def IMPLICIT_DEF_R32 : I<0, Pseudo, (ops R32:$dst),
"#IMPLICIT_DEF $dst",
[(set R32:$dst, (undef))]>;
-def IMPLICIT_DEF_FR32 : I<0, Pseudo, (ops FR32:$dst),
- "#IMPLICIT_DEF $dst",
- [(set FR32:$dst, (undef))]>, Requires<[HasSSE2]>;
-def IMPLICIT_DEF_FR64 : I<0, Pseudo, (ops FR64:$dst),
- "#IMPLICIT_DEF $dst",
- [(set FR64:$dst, (undef))]>, Requires<[HasSSE2]>;
-
-
-// CMOV* - Used to implement the SSE SELECT DAG operation. Expanded by the
-// scheduler into a branch sequence.
-let usesCustomDAGSchedInserter = 1 in { // Expanded by the scheduler.
- def CMOV_FR32 : I<0, Pseudo,
-(ops FR32:$dst, FR32:$t, FR32:$f, i8imm:$cond),
-"#CMOV_FR32 PSEUDO!",
-[(set FR32:$dst, (X86cmov FR32:$t, FR32:$f, imm:$cond))]>;
- def CMOV_FR64 : I<0, Pseudo,
-(ops FR64:$dst, FR64:$t, FR64:$f, i8imm:$cond),
-"#CMOV_FR64 PSEUDO!",
-[(set FR64:$dst, (X86cmov FR64:$t, FR64:$f, imm:$cond))]>;
-}
-
-let usesCustomDAGSchedInserter = 1 in { // Expanded by the scheduler.
- def FP_TO_INT16_IN_MEM : I<0, Pseudo,
-(ops i16mem:$dst, RFP:$src),
- "#FP_TO_INT16_IN_MEM PSEUDO!",
- [(X86fp_to_i16mem RFP:$src, addr:$dst)]>;
- def FP_TO_INT32_IN_MEM : I<0, Pseu
[llvm-commits] CVS: llvm/include/llvm/Target/TargetLowering.h
Changes in directory llvm/include/llvm/Target: TargetLowering.h updated: 1.51 -> 1.52 --- Log message: Pass in a value type to getRegForInlineAsmConstraint, allowing targets to select different sets of registers depending on the type requested. --- Diffs of the changes: (+2 -1) TargetLowering.h |3 ++- 1 files changed, 2 insertions(+), 1 deletion(-) Index: llvm/include/llvm/Target/TargetLowering.h diff -u llvm/include/llvm/Target/TargetLowering.h:1.51 llvm/include/llvm/Target/TargetLowering.h:1.52 --- llvm/include/llvm/Target/TargetLowering.h:1.51 Fri Feb 17 12:06:19 2006 +++ llvm/include/llvm/Target/TargetLowering.h Tue Feb 21 17:10:29 2006 @@ -496,7 +496,8 @@ /// satisfy the constraint. This should only be used for physregs and /// C_RegisterClass constraints. virtual std::vector - getRegForInlineAsmConstraint(const std::string &Constraint) const; + getRegForInlineAsmConstraint(const std::string &Constraint, + MVT::ValueType VT) const; /// isOperandValidForConstraint - Return true if the specified SDOperand is /// valid for the specified target constraint letter. ___ llvm-commits mailing list llvm-commits@cs.uiuc.edu http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
[llvm-commits] CVS: llvm/lib/Target/PowerPC/PPCISelLowering.cpp PPCISelLowering.h
Changes in directory llvm/lib/Target/PowerPC:
PPCISelLowering.cpp updated: 1.88 -> 1.89
PPCISelLowering.h updated: 1.21 -> 1.22
---
Log message:
Updates to match change of getRegForInlineAsmConstraint prototype
---
Diffs of the changes: (+5 -3)
PPCISelLowering.cpp |5 +++--
PPCISelLowering.h |3 ++-
2 files changed, 5 insertions(+), 3 deletions(-)
Index: llvm/lib/Target/PowerPC/PPCISelLowering.cpp
diff -u llvm/lib/Target/PowerPC/PPCISelLowering.cpp:1.88
llvm/lib/Target/PowerPC/PPCISelLowering.cpp:1.89
--- llvm/lib/Target/PowerPC/PPCISelLowering.cpp:1.88Fri Feb 17 18:08:58 2006
+++ llvm/lib/Target/PowerPC/PPCISelLowering.cpp Tue Feb 21 17:11:00 2006
@@ -999,7 +999,8 @@
std::vector PPCTargetLowering::
-getRegForInlineAsmConstraint(const std::string &Constraint) const {
+getRegForInlineAsmConstraint(const std::string &Constraint,
+ MVT::ValueType VT) const {
if (Constraint.size() == 1) {
switch (Constraint[0]) { // GCC RS6000 Constraint Letters
default: break; // Unknown constriant letter
@@ -1051,7 +1052,7 @@
}
// Handle explicit register names.
- return TargetLowering::getRegForInlineAsmConstraint(Constraint);
+ return TargetLowering::getRegForInlineAsmConstraint(Constraint, VT);
}
// isOperandValidForConstraint
Index: llvm/lib/Target/PowerPC/PPCISelLowering.h
diff -u llvm/lib/Target/PowerPC/PPCISelLowering.h:1.21
llvm/lib/Target/PowerPC/PPCISelLowering.h:1.22
--- llvm/lib/Target/PowerPC/PPCISelLowering.h:1.21 Tue Feb 7 14:16:30 2006
+++ llvm/lib/Target/PowerPC/PPCISelLowering.h Tue Feb 21 17:11:00 2006
@@ -99,7 +99,8 @@
ConstraintType getConstraintType(char ConstraintLetter) const;
std::vector
- getRegForInlineAsmConstraint(const std::string &Constraint) const;
+ getRegForInlineAsmConstraint(const std::string &Constraint,
+ MVT::ValueType VT) const;
bool isOperandValidForConstraint(SDOperand Op, char ConstraintLetter);
};
}
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[llvm-commits] CVS: llvm/lib/Target/TargetLowering.cpp
Changes in directory llvm/lib/Target:
TargetLowering.cpp updated: 1.33 -> 1.34
---
Log message:
Updates to match change of getRegForInlineAsmConstraint prototype
---
Diffs of the changes: (+2 -1)
TargetLowering.cpp |3 ++-
1 files changed, 2 insertions(+), 1 deletion(-)
Index: llvm/lib/Target/TargetLowering.cpp
diff -u llvm/lib/Target/TargetLowering.cpp:1.33
llvm/lib/Target/TargetLowering.cpp:1.34
--- llvm/lib/Target/TargetLowering.cpp:1.33 Fri Feb 17 20:43:25 2006
+++ llvm/lib/Target/TargetLowering.cpp Tue Feb 21 17:11:00 2006
@@ -745,7 +745,8 @@
std::vector TargetLowering::
-getRegForInlineAsmConstraint(const std::string &Constraint) const {
+getRegForInlineAsmConstraint(const std::string &Constraint,
+ MVT::ValueType VT) const {
// Not a physreg, must not be a register reference or something.
if (Constraint[0] != '{') return std::vector();
assert(*(Constraint.end()-1) == '}' && "Not a brace enclosed constraint?");
___
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[llvm-commits] CVS: llvm/lib/Target/X86/X86ISelLowering.cpp X86ISelLowering.h
Changes in directory llvm/lib/Target/X86:
X86ISelLowering.cpp updated: 1.90 -> 1.91
X86ISelLowering.h updated: 1.28 -> 1.29
---
Log message:
Updates to match change of getRegForInlineAsmConstraint prototype
---
Diffs of the changes: (+5 -3)
X86ISelLowering.cpp |5 +++--
X86ISelLowering.h |3 ++-
2 files changed, 5 insertions(+), 3 deletions(-)
Index: llvm/lib/Target/X86/X86ISelLowering.cpp
diff -u llvm/lib/Target/X86/X86ISelLowering.cpp:1.90
llvm/lib/Target/X86/X86ISelLowering.cpp:1.91
--- llvm/lib/Target/X86/X86ISelLowering.cpp:1.90Sat Feb 18 01:26:17 2006
+++ llvm/lib/Target/X86/X86ISelLowering.cpp Tue Feb 21 17:11:00 2006
@@ -1961,7 +1961,8 @@
}
std::vector X86TargetLowering::
-getRegForInlineAsmConstraint(const std::string &Constraint) const {
+getRegForInlineAsmConstraint(const std::string &Constraint,
+ MVT::ValueType VT) const {
if (Constraint.size() == 1) {
// FIXME: not handling fp-stack yet!
// FIXME: not handling MMX registers yet ('y' constraint).
@@ -1993,5 +1994,5 @@
}
// Handle explicit register names.
- return TargetLowering::getRegForInlineAsmConstraint(Constraint);
+ return TargetLowering::getRegForInlineAsmConstraint(Constraint, VT);
}
Index: llvm/lib/Target/X86/X86ISelLowering.h
diff -u llvm/lib/Target/X86/X86ISelLowering.h:1.28
llvm/lib/Target/X86/X86ISelLowering.h:1.29
--- llvm/lib/Target/X86/X86ISelLowering.h:1.28 Fri Feb 17 18:15:05 2006
+++ llvm/lib/Target/X86/X86ISelLowering.h Tue Feb 21 17:11:00 2006
@@ -224,7 +224,8 @@
SDOperand getReturnAddressFrameIndex(SelectionDAG &DAG);
std::vector
- getRegForInlineAsmConstraint(const std::string &Constraint) const;
+ getRegForInlineAsmConstraint(const std::string &Constraint,
+ MVT::ValueType VT) const;
private:
// C Calling Convention implementation.
std::vector LowerCCCArguments(Function &F, SelectionDAG &DAG);
___
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[llvm-commits] CVS: llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
Changes in directory llvm/lib/CodeGen/SelectionDAG:
SelectionDAGISel.cpp updated: 1.164 -> 1.165
---
Log message:
Adjust to changes in getRegForInlineAsmConstraint prototype
---
Diffs of the changes: (+18 -18)
SelectionDAGISel.cpp | 36 ++--
1 files changed, 18 insertions(+), 18 deletions(-)
Index: llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
diff -u llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp:1.164
llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp:1.165
--- llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp:1.164Thu Feb 16
17:11:42 2006
+++ llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp Tue Feb 21 17:12:12 2006
@@ -1198,13 +1198,6 @@
SDOperand Chain = getRoot();
SDOperand Flag;
- // Loop over all of the inputs, copying the operand values into the
- // appropriate registers and processing the output regs.
- unsigned RetValReg = 0;
- std::vector > IndirectStoresToEmit;
- unsigned OpNum = 1;
- bool FoundOutputConstraint = false;
-
// We fully assign registers here at isel time. This is not optimal, but
// should work. For register classes that correspond to LLVM classes, we
// could let the LLVM RA do its thing, but we currently don't. Do a prepass
@@ -1215,7 +1208,7 @@
std::string &ConstraintCode = Constraints[i].Codes[0];
std::vector Regs =
- TLI.getRegForInlineAsmConstraint(ConstraintCode);
+ TLI.getRegForInlineAsmConstraint(ConstraintCode, MVT::Other);
if (Regs.size() != 1) continue; // Not assigned a fixed reg.
unsigned TheReg = Regs[0];
@@ -1240,14 +1233,23 @@
}
}
+ // Loop over all of the inputs, copying the operand values into the
+ // appropriate registers and processing the output regs.
+ unsigned RetValReg = 0;
+ std::vector > IndirectStoresToEmit;
+ bool FoundOutputConstraint = false;
+ unsigned OpNum = 1;
+
for (unsigned i = 0, e = Constraints.size(); i != e; ++i) {
assert(Constraints[i].Codes.size() == 1 && "Only handles one code so
far!");
std::string &ConstraintCode = Constraints[i].Codes[0];
+Value *CallOperand = I.getOperand(OpNum);
+MVT::ValueType CallOpVT = TLI.getValueType(CallOperand->getType());
switch (Constraints[i].Type) {
case InlineAsm::isOutput: {
// Copy the output from the appropriate register.
std::vector Regs =
-TLI.getRegForInlineAsmConstraint(ConstraintCode);
+TLI.getRegForInlineAsmConstraint(ConstraintCode, CallOpVT);
// Find a regsister that we can use.
unsigned DestReg;
@@ -1276,9 +1278,8 @@
RetValReg = DestReg;
OpTy = I.getType();
} else {
-IndirectStoresToEmit.push_back(std::make_pair(DestReg,
- I.getOperand(OpNum)));
-OpTy = I.getOperand(OpNum)->getType();
+IndirectStoresToEmit.push_back(std::make_pair(DestReg, CallOperand));
+OpTy = CallOperand->getType();
OpTy = cast(OpTy)->getElementType();
OpNum++; // Consumes a call operand.
}
@@ -1292,21 +1293,20 @@
break;
}
case InlineAsm::isInput: {
- Value *Operand = I.getOperand(OpNum);
- const Type *OpTy = Operand->getType();
+ const Type *OpTy = CallOperand->getType();
OpNum++; // Consumes a call operand.
unsigned SrcReg;
SDOperand ResOp;
unsigned ResOpType;
- SDOperand InOperandVal = getValue(Operand);
+ SDOperand InOperandVal = getValue(CallOperand);
if (isdigit(ConstraintCode[0])) {// Matching constraint?
// If this is required to match an output register we have already set,
// just use its register.
unsigned OperandNo = atoi(ConstraintCode.c_str());
SrcReg =
cast(AsmNodeOperands[OperandNo*2+2])->getReg();
-ResOp = DAG.getRegister(SrcReg, TLI.getValueType(OpTy));
+ResOp = DAG.getRegister(SrcReg, CallOpVT);
ResOpType = 1;
Chain = DAG.getCopyToReg(Chain, SrcReg, InOperandVal, Flag);
@@ -1321,7 +1321,7 @@
case TargetLowering::C_RegisterClass: {
// Copy the input into the appropriate register.
std::vector Regs =
-TLI.getRegForInlineAsmConstraint(ConstraintCode);
+TLI.getRegForInlineAsmConstraint(ConstraintCode, CallOpVT);
if (Regs.size() == 1)
SrcReg = Regs[0];
else
@@ -1332,7 +1332,7 @@
Chain = DAG.getCopyToReg(Chain, SrcReg, InOperandVal, Flag);
Flag = Chain.getValue(1);
- ResOp = DAG.getRegister(SrcReg, TLI.getValueType(OpTy));
+ ResOp = DAG.getRegister(SrcReg, CallOpVT);
ResOpType = 1;
break;
}
___
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[llvm-commits] CVS: llvm/include/llvm/Target/MRegisterInfo.h
Changes in directory llvm/include/llvm/Target:
MRegisterInfo.h updated: 1.68 -> 1.69
---
Log message:
expose the set of values types holdable in a regclass to clients
---
Diffs of the changes: (+17 -1)
MRegisterInfo.h | 18 +-
1 files changed, 17 insertions(+), 1 deletion(-)
Index: llvm/include/llvm/Target/MRegisterInfo.h
diff -u llvm/include/llvm/Target/MRegisterInfo.h:1.68
llvm/include/llvm/Target/MRegisterInfo.h:1.69
--- llvm/include/llvm/Target/MRegisterInfo.h:1.68 Thu Feb 2 14:11:55 2006
+++ llvm/include/llvm/Target/MRegisterInfo.hTue Feb 21 17:51:58 2006
@@ -44,8 +44,9 @@
typedef const unsigned* iterator;
typedef const unsigned* const_iterator;
+ typedef const MVT::ValueType* vt_iterator;
private:
- const MVT::ValueType* VTs;
+ const vt_iterator VTs;
const unsigned RegSize, Alignment;// Size & Alignment of register in
bytes
const iterator RegsBegin, RegsEnd;
public:
@@ -84,6 +85,21 @@
return false;
}
+ /// vt_begin - Loop over all of the value types that can be represented by
+ /// values in this register class.
+ vt_iterator vt_begin() const {
+return VTs;
+ }
+
+ /// vt_begin - Loop over all of the value types that can be represented by
+ /// values in this register class.
+ vt_iterator vt_end() const {
+vt_iterator I = VTs;
+while (*I != MVT::Other) ++I;
+return I;
+ }
+
+
/// allocation_order_begin/end - These methods define a range of registers
/// which specify the registers in this class that are valid to register
/// allocate, and the preferred order to allocate them in. For example,
___
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[llvm-commits] CVS: llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
Changes in directory llvm/lib/CodeGen/SelectionDAG:
SelectionDAGISel.cpp updated: 1.165 -> 1.166
---
Log message:
split register class handling from explicit physreg handling.
---
Diffs of the changes: (+77 -34)
SelectionDAGISel.cpp | 111 +++
1 files changed, 77 insertions(+), 34 deletions(-)
Index: llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
diff -u llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp:1.165
llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp:1.166
--- llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp:1.165Tue Feb 21
17:12:12 2006
+++ llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp Tue Feb 21 18:56:12 2006
@@ -1187,6 +1187,7 @@
bool hasSideEffects = IA->hasSideEffects();
std::vector Constraints = IA->ParseConstraints();
+ std::vector ConstraintVTs;
/// AsmNodeOperands - A list of pairs. The first element is a register, the
/// second is a bitfield where bit #0 is set if it is a use and bit #1 is set
@@ -1203,14 +1204,43 @@
// could let the LLVM RA do its thing, but we currently don't. Do a prepass
// over the constraints, collecting fixed registers that we know we can't
use.
std::set OutputRegs, InputRegs;
+ unsigned OpNum = 1;
for (unsigned i = 0, e = Constraints.size(); i != e; ++i) {
assert(Constraints[i].Codes.size() == 1 && "Only handles one code so
far!");
std::string &ConstraintCode = Constraints[i].Codes[0];
-std::vector Regs =
- TLI.getRegForInlineAsmConstraint(ConstraintCode, MVT::Other);
-if (Regs.size() != 1) continue; // Not assigned a fixed reg.
-unsigned TheReg = Regs[0];
+MVT::ValueType OpVT;
+
+// Compute the value type for each operand and add it to ConstraintVTs.
+switch (Constraints[i].Type) {
+case InlineAsm::isOutput:
+ if (!Constraints[i].isIndirectOutput) {
+assert(I.getType() != Type::VoidTy && "Bad inline asm!");
+OpVT = TLI.getValueType(I.getType());
+ } else {
+Value *CallOperand = I.getOperand(OpNum);
+const Type *OpTy = CallOperand->getType();
+OpVT = TLI.getValueType(cast(OpTy)->getElementType());
+OpNum++; // Consumes a call operand.
+ }
+ break;
+case InlineAsm::isInput:
+ OpVT = TLI.getValueType(I.getOperand(OpNum)->getType());
+ OpNum++; // Consumes a call operand.
+ break;
+case InlineAsm::isClobber:
+ OpVT = MVT::Other;
+ break;
+}
+
+ConstraintVTs.push_back(OpVT);
+
+std::pair Reg =
+ TLI.getRegForInlineAsmConstraint(ConstraintCode, OpVT);
+if (Reg.first == 0) continue; // Not assigned a fixed reg.
+unsigned TheReg = Reg.first;
+
+// FIXME: Handle expanded physreg refs!
switch (Constraints[i].Type) {
case InlineAsm::isOutput:
@@ -1221,15 +1251,15 @@
if (Constraints[i].isEarlyClobber || Constraints[i].hasMatchingInput)
InputRegs.insert(TheReg);
break;
+case InlineAsm::isInput:
+ // We can't assign any other input to this register.
+ InputRegs.insert(TheReg);
+ break;
case InlineAsm::isClobber:
// Clobbered regs cannot be used as inputs or outputs.
InputRegs.insert(TheReg);
OutputRegs.insert(TheReg);
break;
-case InlineAsm::isInput:
- // We can't assign any other input to this register.
- InputRegs.insert(TheReg);
- break;
}
}
@@ -1238,28 +1268,32 @@
unsigned RetValReg = 0;
std::vector > IndirectStoresToEmit;
bool FoundOutputConstraint = false;
- unsigned OpNum = 1;
+ OpNum = 1;
for (unsigned i = 0, e = Constraints.size(); i != e; ++i) {
assert(Constraints[i].Codes.size() == 1 && "Only handles one code so
far!");
std::string &ConstraintCode = Constraints[i].Codes[0];
-Value *CallOperand = I.getOperand(OpNum);
-MVT::ValueType CallOpVT = TLI.getValueType(CallOperand->getType());
+
switch (Constraints[i].Type) {
case InlineAsm::isOutput: {
- // Copy the output from the appropriate register.
- std::vector Regs =
-TLI.getRegForInlineAsmConstraint(ConstraintCode, CallOpVT);
-
- // Find a regsister that we can use.
+ // Copy the output from the appropriate register. Find a regsister that
+ // we can use.
+
+ // Check to see if this is a physreg reference.
+ std::pair PhysReg =
+ TLI.getRegForInlineAsmConstraint(ConstraintCode, ConstraintVTs[i]);
unsigned DestReg;
- if (Regs.size() == 1)
-DestReg = Regs[0];
+ if (PhysReg.first)
+DestReg = PhysReg.first;
else {
-bool UsesInputRegister = false;
+std::vector Regs =
+ TLI.getRegClassForInlineAsmConstraint(ConstraintCode,
+ConstraintVTs[i]);
+
// If this is an early-clobber output, or if there is an input
// constraint that matches this, we need to reserve th
[llvm-commits] CVS: llvm/include/llvm/Target/TargetLowering.h
Changes in directory llvm/include/llvm/Target:
TargetLowering.h updated: 1.52 -> 1.53
---
Log message:
split register class handling from explicit physreg handling.
---
Diffs of the changes: (+16 -6)
TargetLowering.h | 22 --
1 files changed, 16 insertions(+), 6 deletions(-)
Index: llvm/include/llvm/Target/TargetLowering.h
diff -u llvm/include/llvm/Target/TargetLowering.h:1.52
llvm/include/llvm/Target/TargetLowering.h:1.53
--- llvm/include/llvm/Target/TargetLowering.h:1.52 Tue Feb 21 17:10:29 2006
+++ llvm/include/llvm/Target/TargetLowering.h Tue Feb 21 18:56:01 2006
@@ -481,6 +481,7 @@
//
enum ConstraintType {
+C_Register,// Constraint represents a single register.
C_RegisterClass, // Constraint represents one or more registers.
C_Other, // Something else.
C_Unknown // Unsupported constraint.
@@ -491,13 +492,22 @@
/// constraint it is for this target.
virtual ConstraintType getConstraintType(char ConstraintLetter) const;
- /// getRegForInlineAsmConstraint - Given a constraint letter or register
- /// name (e.g. "r" or "edx"), return a list of registers that can be used to
- /// satisfy the constraint. This should only be used for physregs and
- /// C_RegisterClass constraints.
+
+ /// getRegClassForInlineAsmConstraint - Given a constraint letter (e.g. "r"),
+ /// return a list of registers that can be used to satisfy the constraint.
+ /// This should only be used for C_RegisterClass constraints.
virtual std::vector
- getRegForInlineAsmConstraint(const std::string &Constraint,
- MVT::ValueType VT) const;
+ getRegClassForInlineAsmConstraint(const std::string &Constraint,
+MVT::ValueType VT) const;
+
+ /// getRegForInlineAsmConstraint - Given a physical register constraint (e.g.
+ /// {edx}), return the register number and the register class for the
+ /// register. This should only be used for C_Register constraints. On
error,
+ /// this returns a register number of 0.
+ virtual std::pair
+getRegForInlineAsmConstraint(const std::string &Constraint,
+ MVT::ValueType VT) const;
+
/// isOperandValidForConstraint - Return true if the specified SDOperand is
/// valid for the specified target constraint letter.
___
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[llvm-commits] CVS: llvm/lib/Target/TargetLowering.cpp
Changes in directory llvm/lib/Target:
TargetLowering.cpp updated: 1.34 -> 1.35
---
Log message:
split register class handling from explicit physreg handling.
---
Diffs of the changes: (+21 -11)
TargetLowering.cpp | 32 +---
1 files changed, 21 insertions(+), 11 deletions(-)
Index: llvm/lib/Target/TargetLowering.cpp
diff -u llvm/lib/Target/TargetLowering.cpp:1.34
llvm/lib/Target/TargetLowering.cpp:1.35
--- llvm/lib/Target/TargetLowering.cpp:1.34 Tue Feb 21 17:11:00 2006
+++ llvm/lib/Target/TargetLowering.cpp Tue Feb 21 18:56:38 2006
@@ -745,24 +745,34 @@
std::vector TargetLowering::
+getRegClassForInlineAsmConstraint(const std::string &Constraint,
+ MVT::ValueType VT) const {
+ return std::vector();
+}
+
+
+std::pair TargetLowering::
getRegForInlineAsmConstraint(const std::string &Constraint,
MVT::ValueType VT) const {
- // Not a physreg, must not be a register reference or something.
- if (Constraint[0] != '{') return std::vector();
+ if (Constraint[0] != '{')
+return std::pair(0, 0);
assert(*(Constraint.end()-1) == '}' && "Not a brace enclosed constraint?");
// Remove the braces from around the name.
std::string RegName(Constraint.begin()+1, Constraint.end()-1);
-
- // Scan to see if this constraint is a register name.
+
+ // Figure out which register class contains this reg.
const MRegisterInfo *RI = TM.getRegisterInfo();
- for (unsigned i = 1, e = RI->getNumRegs(); i != e; ++i) {
-if (const char *Name = RI->get(i).Name)
- if (StringsEqualNoCase(RegName, Name))
-return std::vector(1, i);
+ for (MRegisterInfo::regclass_iterator RCI = RI->regclass_begin(),
+ E = RI->regclass_end(); RCI != E; ++RCI) {
+const TargetRegisterClass *RC = *RCI;
+for (TargetRegisterClass::iterator I = RC->begin(), E = RC->end();
+ I != E; ++I) {
+ if (StringsEqualNoCase(RegName, RI->get(*I).Name)) {
+return std::make_pair(*I, RC);
+ }
+}
}
- // Unknown physreg.
- return std::vector();
+ return std::pair(0, 0);
}
-
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[llvm-commits] CVS: llvm/lib/Target/X86/X86ISelLowering.cpp X86ISelLowering.h
Changes in directory llvm/lib/Target/X86:
X86ISelLowering.cpp updated: 1.91 -> 1.92
X86ISelLowering.h updated: 1.29 -> 1.30
---
Log message:
split register class handling from explicit physreg handling.
---
Diffs of the changes: (+5 -6)
X86ISelLowering.cpp |7 +++
X86ISelLowering.h |4 ++--
2 files changed, 5 insertions(+), 6 deletions(-)
Index: llvm/lib/Target/X86/X86ISelLowering.cpp
diff -u llvm/lib/Target/X86/X86ISelLowering.cpp:1.91
llvm/lib/Target/X86/X86ISelLowering.cpp:1.92
--- llvm/lib/Target/X86/X86ISelLowering.cpp:1.91Tue Feb 21 17:11:00 2006
+++ llvm/lib/Target/X86/X86ISelLowering.cpp Tue Feb 21 18:56:39 2006
@@ -1961,8 +1961,8 @@
}
std::vector X86TargetLowering::
-getRegForInlineAsmConstraint(const std::string &Constraint,
- MVT::ValueType VT) const {
+getRegClassForInlineAsmConstraint(const std::string &Constraint,
+ MVT::ValueType VT) const {
if (Constraint.size() == 1) {
// FIXME: not handling fp-stack yet!
// FIXME: not handling MMX registers yet ('y' constraint).
@@ -1993,6 +1993,5 @@
}
}
- // Handle explicit register names.
- return TargetLowering::getRegForInlineAsmConstraint(Constraint, VT);
+ return std::vector();
}
Index: llvm/lib/Target/X86/X86ISelLowering.h
diff -u llvm/lib/Target/X86/X86ISelLowering.h:1.29
llvm/lib/Target/X86/X86ISelLowering.h:1.30
--- llvm/lib/Target/X86/X86ISelLowering.h:1.29 Tue Feb 21 17:11:00 2006
+++ llvm/lib/Target/X86/X86ISelLowering.h Tue Feb 21 18:56:39 2006
@@ -224,8 +224,8 @@
SDOperand getReturnAddressFrameIndex(SelectionDAG &DAG);
std::vector
- getRegForInlineAsmConstraint(const std::string &Constraint,
- MVT::ValueType VT) const;
+ getRegClassForInlineAsmConstraint(const std::string &Constraint,
+MVT::ValueType VT) const;
private:
// C Calling Convention implementation.
std::vector LowerCCCArguments(Function &F, SelectionDAG &DAG);
___
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[llvm-commits] CVS: llvm/tools/opt/Makefile
Changes in directory llvm/tools/opt: Makefile updated: 1.53 -> 1.54 --- Log message: reorder some libraries --- Diffs of the changes: (+1 -1) Makefile |2 +- 1 files changed, 1 insertion(+), 1 deletion(-) Index: llvm/tools/opt/Makefile diff -u llvm/tools/opt/Makefile:1.53 llvm/tools/opt/Makefile:1.54 --- llvm/tools/opt/Makefile:1.53Thu Oct 27 10:54:34 2005 +++ llvm/tools/opt/Makefile Tue Feb 21 18:59:06 2006 @@ -11,7 +11,7 @@ USEDLIBS = LLVMBCReader LLVMBCWriter LLVMInstrumentation.a \ LLVMScalarOpts.a LLVMipo.a LLVMipa.a LLVMDataStructure LLVMTransforms.a \ - LLVMTarget.a LLVMAnalysis.a LLVMTransformUtils.a LLVMCore LLVMSupport.a \ + LLVMTarget.a LLVMTransformUtils.a LLVMAnalysis.a LLVMCore LLVMSupport.a \ LLVMbzip2 LLVMSystem.a include $(LEVEL)/Makefile.common ___ llvm-commits mailing list llvm-commits@cs.uiuc.edu http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
[llvm-commits] CVS: llvm/lib/Target/PowerPC/PPCISelLowering.cpp PPCISelLowering.h
Changes in directory llvm/lib/Target/PowerPC:
PPCISelLowering.cpp updated: 1.89 -> 1.90
PPCISelLowering.h updated: 1.22 -> 1.23
---
Log message:
split register class handling from explicit physreg handling.
---
Diffs of the changes: (+5 -6)
PPCISelLowering.cpp |7 +++
PPCISelLowering.h |4 ++--
2 files changed, 5 insertions(+), 6 deletions(-)
Index: llvm/lib/Target/PowerPC/PPCISelLowering.cpp
diff -u llvm/lib/Target/PowerPC/PPCISelLowering.cpp:1.89
llvm/lib/Target/PowerPC/PPCISelLowering.cpp:1.90
--- llvm/lib/Target/PowerPC/PPCISelLowering.cpp:1.89Tue Feb 21 17:11:00 2006
+++ llvm/lib/Target/PowerPC/PPCISelLowering.cpp Tue Feb 21 18:56:38 2006
@@ -999,8 +999,8 @@
std::vector PPCTargetLowering::
-getRegForInlineAsmConstraint(const std::string &Constraint,
- MVT::ValueType VT) const {
+getRegClassForInlineAsmConstraint(const std::string &Constraint,
+ MVT::ValueType VT) const {
if (Constraint.size() == 1) {
switch (Constraint[0]) { // GCC RS6000 Constraint Letters
default: break; // Unknown constriant letter
@@ -1051,8 +1051,7 @@
}
}
- // Handle explicit register names.
- return TargetLowering::getRegForInlineAsmConstraint(Constraint, VT);
+ return std::vector();
}
// isOperandValidForConstraint
Index: llvm/lib/Target/PowerPC/PPCISelLowering.h
diff -u llvm/lib/Target/PowerPC/PPCISelLowering.h:1.22
llvm/lib/Target/PowerPC/PPCISelLowering.h:1.23
--- llvm/lib/Target/PowerPC/PPCISelLowering.h:1.22 Tue Feb 21 17:11:00 2006
+++ llvm/lib/Target/PowerPC/PPCISelLowering.h Tue Feb 21 18:56:38 2006
@@ -99,8 +99,8 @@
ConstraintType getConstraintType(char ConstraintLetter) const;
std::vector
- getRegForInlineAsmConstraint(const std::string &Constraint,
- MVT::ValueType VT) const;
+ getRegClassForInlineAsmConstraint(const std::string &Constraint,
+MVT::ValueType VT) const;
bool isOperandValidForConstraint(SDOperand Op, char ConstraintLetter);
};
}
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[llvm-commits] CVS: llvm/lib/Target/X86/X86ATTAsmPrinter.h X86ISelLowering.cpp X86InstrInfo.td X86InstrSSE.td X86IntelAsmPrinter.h
Changes in directory llvm/lib/Target/X86:
X86ATTAsmPrinter.h updated: 1.7 -> 1.8
X86ISelLowering.cpp updated: 1.92 -> 1.93
X86InstrInfo.td updated: 1.246 -> 1.247
X86InstrSSE.td updated: 1.4 -> 1.5
X86IntelAsmPrinter.h updated: 1.8 -> 1.9
---
Log message:
Added MMX, SSE1, and SSE2 vector instructions and some simple patterns.
Fixed some existing bugs (wrong predicates, prefixes) at the same time.
---
Diffs of the changes: (+542 -283)
X86ATTAsmPrinter.h |3
X86ISelLowering.cpp | 38 ++
X86InstrInfo.td |7
X86InstrSSE.td | 773 ---
X86IntelAsmPrinter.h |4
5 files changed, 542 insertions(+), 283 deletions(-)
Index: llvm/lib/Target/X86/X86ATTAsmPrinter.h
diff -u llvm/lib/Target/X86/X86ATTAsmPrinter.h:1.7
llvm/lib/Target/X86/X86ATTAsmPrinter.h:1.8
--- llvm/lib/Target/X86/X86ATTAsmPrinter.h:1.7 Fri Feb 17 18:15:05 2006
+++ llvm/lib/Target/X86/X86ATTAsmPrinter.h Tue Feb 21 20:26:30 2006
@@ -49,6 +49,9 @@
void printi64mem(const MachineInstr *MI, unsigned OpNo) {
printMemReference(MI, OpNo);
}
+ void printi128mem(const MachineInstr *MI, unsigned OpNo) {
+printMemReference(MI, OpNo);
+ }
void printf32mem(const MachineInstr *MI, unsigned OpNo) {
printMemReference(MI, OpNo);
}
Index: llvm/lib/Target/X86/X86ISelLowering.cpp
diff -u llvm/lib/Target/X86/X86ISelLowering.cpp:1.92
llvm/lib/Target/X86/X86ISelLowering.cpp:1.93
--- llvm/lib/Target/X86/X86ISelLowering.cpp:1.92Tue Feb 21 18:56:39 2006
+++ llvm/lib/Target/X86/X86ISelLowering.cpp Tue Feb 21 20:26:30 2006
@@ -236,6 +236,44 @@
addLegalFPImmediate(-0.0); // FLD0/FCHS
addLegalFPImmediate(-1.0); // FLD1/FCHS
}
+
+ if (TM.getSubtarget().hasMMX()) {
+addRegisterClass(MVT::v8i8, X86::VR64RegisterClass);
+addRegisterClass(MVT::v4i16, X86::VR64RegisterClass);
+addRegisterClass(MVT::v2i32, X86::VR64RegisterClass);
+
+// FIXME: We don't support any ConstantVec's yet. We should custom expand
+// the ones we do!
+setOperationAction(ISD::ConstantVec, MVT::v8i8, Expand);
+setOperationAction(ISD::ConstantVec, MVT::v4i16, Expand);
+setOperationAction(ISD::ConstantVec, MVT::v2i32, Expand);
+ }
+
+ if (TM.getSubtarget().hasSSE1()) {
+addRegisterClass(MVT::v4f32, X86::VR128RegisterClass);
+
+// FIXME: We don't support any ConstantVec's yet. We should custom expand
+// the ones we do!
+setOperationAction(ISD::ConstantVec, MVT::v4f32, Expand);
+ }
+
+ if (TM.getSubtarget().hasSSE2()) {
+addRegisterClass(MVT::v2f64, X86::VR128RegisterClass);
+addRegisterClass(MVT::v16i8, X86::VR128RegisterClass);
+addRegisterClass(MVT::v8i16, X86::VR128RegisterClass);
+addRegisterClass(MVT::v4i32, X86::VR128RegisterClass);
+addRegisterClass(MVT::v2i64, X86::VR128RegisterClass);
+
+
+// FIXME: We don't support any ConstantVec's yet. We should custom expand
+// the ones we do!
+setOperationAction(ISD::ConstantVec, MVT::v2f64, Expand);
+setOperationAction(ISD::ConstantVec, MVT::v16i8, Expand);
+setOperationAction(ISD::ConstantVec, MVT::v8i16, Expand);
+setOperationAction(ISD::ConstantVec, MVT::v4i32, Expand);
+setOperationAction(ISD::ConstantVec, MVT::v2i64, Expand);
+ }
+
computeRegisterProperties();
// FIXME: These should be based on subtarget info. Plus, the values should
Index: llvm/lib/Target/X86/X86InstrInfo.td
diff -u llvm/lib/Target/X86/X86InstrInfo.td:1.246
llvm/lib/Target/X86/X86InstrInfo.td:1.247
--- llvm/lib/Target/X86/X86InstrInfo.td:1.246 Tue Feb 21 14:00:20 2006
+++ llvm/lib/Target/X86/X86InstrInfo.td Tue Feb 21 20:26:30 2006
@@ -136,6 +136,7 @@
def i16mem : X86MemOperand<"printi16mem">;
def i32mem : X86MemOperand<"printi32mem">;
def i64mem : X86MemOperand<"printi64mem">;
+def i128mem : X86MemOperand<"printi128mem">;
def f32mem : X86MemOperand<"printf32mem">;
def f64mem : X86MemOperand<"printf64mem">;
def f128mem : X86MemOperand<"printf128mem">;
@@ -341,6 +342,9 @@
def loadf32 : PatFrag<(ops node:$ptr), (f32 (load node:$ptr))>;
def loadf64 : PatFrag<(ops node:$ptr), (f64 (load node:$ptr))>;
+def X86loadv4f32 : PatFrag<(ops node:$ptr), (v4f32 (load node:$ptr))>;
+def X86loadv2f64 : PatFrag<(ops node:$ptr), (v2f64 (load node:$ptr))>;
+
def sextloadi16i1 : PatFrag<(ops node:$ptr), (i16 (sextload node:$ptr, i1))>;
def sextloadi32i1 : PatFrag<(ops node:$ptr), (i32 (sextload node:$ptr, i1))>;
def sextloadi16i8 : PatFrag<(ops node:$ptr), (i16 (sextload node:$ptr, i8))>;
@@ -360,9 +364,6 @@
def X86loadpf32: PatFrag<(ops node:$ptr), (f32 (X86loadp node:$ptr))>;
def X86loadpf64: PatFrag<(ops node:$ptr), (f64 (X86loadp node:$ptr))>;
-def X86loadpv4f32 : PatFrag<(ops node:$ptr), (v4f32 (X86loadp node:$ptr))>;
-def X86loadpv2f64 : PatFrag<(ops node:$ptr), (v2f64 (X86loadp node:$ptr))>;
-
//===--===//
// Instruction templates...
[llvm-commits] CVS: llvm/lib/Transforms/Scalar/LoopUnswitch.cpp
Changes in directory llvm/lib/Transforms/Scalar:
LoopUnswitch.cpp updated: 1.33 -> 1.34
---
Log message:
Add some comments, simplify some code, and fix a bug that caused rewriting
to rewrite with the wrong value.
---
Diffs of the changes: (+26 -34)
LoopUnswitch.cpp | 60 +++
1 files changed, 26 insertions(+), 34 deletions(-)
Index: llvm/lib/Transforms/Scalar/LoopUnswitch.cpp
diff -u llvm/lib/Transforms/Scalar/LoopUnswitch.cpp:1.33
llvm/lib/Transforms/Scalar/LoopUnswitch.cpp:1.34
--- llvm/lib/Transforms/Scalar/LoopUnswitch.cpp:1.33Sat Feb 18 01:57:38 2006
+++ llvm/lib/Transforms/Scalar/LoopUnswitch.cpp Wed Feb 22 00:37:14 2006
@@ -88,7 +88,7 @@
bool UnswitchIfProfitable(Value *LoopCond, Constant *Val,Loop *L);
unsigned getLoopUnswitchCost(Loop *L, Value *LIC);
void UnswitchTrivialCondition(Loop *L, Value *Cond, Constant *Val,
- bool EntersWhenTrue, BasicBlock *ExitBlock);
+ BasicBlock *ExitBlock);
void UnswitchNontrivialCondition(Value *LIC, Constant *OnVal, Loop *L);
BasicBlock *SplitEdge(BasicBlock *From, BasicBlock *To);
BasicBlock *SplitBlock(BasicBlock *Old, Instruction *SplitPt);
@@ -282,16 +282,17 @@
/// code duplications (equivalently, it produces a simpler loop and a new empty
/// loop, which gets deleted).
///
-/// If this is a trivial condition, return ConstantBool::True if the loop body
-/// runs when the condition is true, False if the loop body executes when the
-/// condition is false. Otherwise, return null to indicate a complex
condition.
-static bool IsTrivialUnswitchCondition(Loop *L, Value *Cond,
- Constant **Val = 0,
- bool *EntersWhenTrue = 0,
+/// If this is a trivial condition, return true, otherwise return false. When
+/// returning true, this sets Cond and Val to the condition that controls the
+/// trivial condition: when Cond dynamically equals Val, the loop is known to
+/// exit. Finally, this sets LoopExit to the BB that the loop exits to when
+/// Cond == Val.
+///
+static bool IsTrivialUnswitchCondition(Loop *L, Value *Cond, Constant **Val =
0,
BasicBlock **LoopExit = 0) {
BasicBlock *Header = L->getHeader();
TerminatorInst *HeaderTerm = Header->getTerminator();
-
+
BasicBlock *LoopExitBB = 0;
if (BranchInst *BI = dyn_cast(HeaderTerm)) {
// If the header block doesn't end with a conditional branch on Cond, we
@@ -304,9 +305,9 @@
// side-effects. If so, determine the value of Cond that causes it to do
// this.
if ((LoopExitBB = isTrivialLoopExitBlock(L, BI->getSuccessor(0 {
- if (Val) *Val = ConstantBool::False;
-} else if ((LoopExitBB = isTrivialLoopExitBlock(L, BI->getSuccessor(1 {
if (Val) *Val = ConstantBool::True;
+} else if ((LoopExitBB = isTrivialLoopExitBlock(L, BI->getSuccessor(1 {
+ if (Val) *Val = ConstantBool::False;
}
} else if (SwitchInst *SI = dyn_cast(HeaderTerm)) {
// If this isn't a switch on Cond, we can't handle it.
@@ -320,7 +321,6 @@
if ((LoopExitBB = isTrivialLoopExitBlock(L, SI->getSuccessor(i {
// Okay, we found a trivial case, remember the value that is trivial.
if (Val) *Val = SI->getCaseValue(i);
-if (EntersWhenTrue) *EntersWhenTrue = false;
break;
}
}
@@ -395,11 +395,9 @@
// If this is a trivial condition to unswitch (which results in no code
// duplication), do it now.
Constant *CondVal;
- bool EntersWhenTrue = true;
BasicBlock *ExitBlock;
- if (IsTrivialUnswitchCondition(L, LoopCond, &CondVal,
- &EntersWhenTrue, &ExitBlock)) {
-UnswitchTrivialCondition(L, LoopCond, CondVal, EntersWhenTrue, ExitBlock);
+ if (IsTrivialUnswitchCondition(L, LoopCond, &CondVal, &ExitBlock)) {
+UnswitchTrivialCondition(L, LoopCond, CondVal, ExitBlock);
} else {
UnswitchNontrivialCondition(LoopCond, Val, L);
}
@@ -525,13 +523,12 @@
/// side-effects), unswitch it. This doesn't involve any code duplication,
just
/// moving the conditional branch outside of the loop and updating loop info.
void LoopUnswitch::UnswitchTrivialCondition(Loop *L, Value *Cond,
-Constant *Val, bool EntersWhenTrue,
+Constant *Val,
BasicBlock *ExitBlock) {
DEBUG(std::cerr << "loop-unswitch: Trivial-Unswitch loop %"
<< L->getHeader()->getName() << " [" << L->getBlocks().size()
<< " blocks] in Function " << L->getHeader()->getParent()->getName()
-<< " on cond: " << *Val << (EntersWhenTrue ? " == " : " != ") <<
-*Cond << "\n");
+<< " on cond: " << *Val << " == " << *Cond << "\n");
// First step, split the preheader, so that
[llvm-commits] CVS: llvm/tools/gccas/gccas.cpp
Changes in directory llvm/tools/gccas: gccas.cpp updated: 1.114 -> 1.115 --- Log message: Turn on loop unswitching tonight --- Diffs of the changes: (+1 -0) gccas.cpp |1 + 1 files changed, 1 insertion(+) Index: llvm/tools/gccas/gccas.cpp diff -u llvm/tools/gccas/gccas.cpp:1.114 llvm/tools/gccas/gccas.cpp:1.115 --- llvm/tools/gccas/gccas.cpp:1.114Sat May 7 17:45:35 2005 +++ llvm/tools/gccas/gccas.cpp Wed Feb 22 01:33:49 2006 @@ -109,6 +109,7 @@ addPass(PM, createCFGSimplificationPass());// Merge & remove BBs addPass(PM, createReassociatePass()); // Reassociate expressions addPass(PM, createLICMPass()); // Hoist loop invariants + addPass(PM, createLoopUnswitchPass()); // Unswitch loops. addPass(PM, createInstructionCombiningPass()); // Clean up after LICM/reassoc addPass(PM, createIndVarSimplifyPass()); // Canonicalize indvars addPass(PM, createLoopUnrollPass()); // Unroll small loops ___ llvm-commits mailing list llvm-commits@cs.uiuc.edu http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
