[llvm-commits] CVS: llvm-www/developers.txt
Changes in directory llvm-www: developers.txt updated: 1.5 -> 1.6 --- Log message: Added a link to my web page on the Developers list. --- Diffs of the changes: (+1 -1) developers.txt |2 +- 1 files changed, 1 insertion(+), 1 deletion(-) Index: llvm-www/developers.txt diff -u llvm-www/developers.txt:1.5 llvm-www/developers.txt:1.6 --- llvm-www/developers.txt:1.5 Sat Dec 17 00:49:45 2005 +++ llvm-www/developers.txt Fri Feb 17 11:57:35 2006 @@ -1,7 +1,7 @@ Vikram Advehref=http://www-sal.cs.uiuc.edu/~vadve/ img=PhotoVikram.jpg width=120 height=120 alt=vadve Henrik Bachhref=mailto:[EMAIL PROTECTED] img=PhotoHenrik.jpg width=156 height=178 alt=Henrik Nate Begeman href=http://sampo.lasthome.net/ img=PhotoNate.jpg width=160 height=130 alt=Sampo -RobBocchinoimg=PhotoRob.jpgwidth=140 height=187 alt=Rob +RobBocchino href=http://llvm.cs.uiuc.edu/~bocchino img=PhotoRob.jpg width=140 height=187 alt=Rob Misha Brukman href=http://misha.brukman.net/code/llvm/ img=PhotoMisha.png width=175 height=198 alt=Misha Evan Cheng href=mailto:[EMAIL PROTECTED] img=PhotoEvan.jpg width=152 height=198 alt=Grawp Jeff Cohen href=http://jolt-lang.org/ img=PhotoJeffCohen.jpg width=165 height=134 alt=jeffc ___ llvm-commits mailing list llvm-commits@cs.uiuc.edu http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
[llvm-commits] CVS: llvm/include/llvm/Target/TargetLowering.h
Changes in directory llvm/include/llvm/Target:
TargetLowering.h updated: 1.50 -> 1.51
---
Log message:
Fix a nit sabre noticed
---
Diffs of the changes: (+1 -1)
TargetLowering.h |2 +-
1 files changed, 1 insertion(+), 1 deletion(-)
Index: llvm/include/llvm/Target/TargetLowering.h
diff -u llvm/include/llvm/Target/TargetLowering.h:1.50
llvm/include/llvm/Target/TargetLowering.h:1.51
--- llvm/include/llvm/Target/TargetLowering.h:1.50 Thu Feb 16 15:11:51 2006
+++ llvm/include/llvm/Target/TargetLowering.h Fri Feb 17 12:06:19 2006
@@ -293,7 +293,7 @@
SDOperand Old;
SDOperand New;
-TargetLoweringOpt::TargetLoweringOpt(SelectionDAG &InDAG) : DAG(InDAG) {}
+TargetLoweringOpt(SelectionDAG &InDAG) : DAG(InDAG) {}
bool CombineTo(SDOperand O, SDOperand N) {
Old = O;
___
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[llvm-commits] CVS: llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
Changes in directory llvm/lib/CodeGen/SelectionDAG:
DAGCombiner.cpp updated: 1.105 -> 1.106
---
Log message:
Clean up DemandedBitsAreZero interface
Make more use of the new mask helpers in valuetypes.h
Combine (sra (srl x, c1), c1) -> sext_inreg if legal
---
Diffs of the changes: (+26 -22)
DAGCombiner.cpp | 48 ++--
1 files changed, 26 insertions(+), 22 deletions(-)
Index: llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
diff -u llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp:1.105
llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp:1.106
--- llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp:1.105 Fri Feb 17 01:26:20 2006
+++ llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp Fri Feb 17 13:54:08 2006
@@ -99,13 +99,12 @@
return SDOperand(N, 0);
}
-bool DemandedBitsAreZero(SDOperand Op, uint64_t DemandedMask,
- SDOperand &Old, SDOperand &New) const {
+bool DemandedBitsAreZero(SDOperand Op, uint64_t DemandedMask) {
TargetLowering::TargetLoweringOpt TLO(DAG);
uint64_t KnownZero, KnownOne;
if (TLI.SimplifyDemandedBits(Op, DemandedMask, KnownZero, KnownOne,
TLO)){
-Old = TLO.Old;
-New = TLO.New;
+WorkList.push_back(Op.Val);
+CombineTo(TLO.Old.Val, TLO.New);
return true;
}
return false;
@@ -732,7 +731,7 @@
TLI.MaskedValueIsZero(N0, SignBit))
return DAG.getNode(ISD::UDIV, N1.getValueType(), N0, N1);
// fold (sdiv X, pow2) -> simple ops after legalize
- if (N1C && N1C->getValue() && !TLI.isIntDivCheap() && AfterLegalize &&
+ if (N1C && N1C->getValue() && !TLI.isIntDivCheap() &&
(isPowerOf2_64(N1C->getSignExtended()) ||
isPowerOf2_64(-N1C->getSignExtended( {
// If dividing by powers of two is cheap, then don't perform the following
@@ -887,7 +886,7 @@
SDOperand DAGCombiner::visitAND(SDNode *N) {
SDOperand N0 = N->getOperand(0);
SDOperand N1 = N->getOperand(1);
- SDOperand LL, LR, RL, RR, CC0, CC1, Old, New;
+ SDOperand LL, LR, RL, RR, CC0, CC1;
ConstantSDNode *N0C = dyn_cast(N0);
ConstantSDNode *N1C = dyn_cast(N1);
MVT::ValueType VT = N1.getValueType();
@@ -986,12 +985,8 @@
}
// fold (and (sign_extend_inreg x, i16 to i32), 1) -> (and x, 1)
// fold (and (sra)) -> (and (srl)) when possible.
- if (DemandedBitsAreZero(SDOperand(N, 0), MVT::getIntVTBitMask(VT), Old,
- New)) {
-WorkList.push_back(N);
-CombineTo(Old.Val, New);
+ if (DemandedBitsAreZero(SDOperand(N, 0), MVT::getIntVTBitMask(VT)))
return SDOperand();
- }
// fold (zext_inreg (extload x)) -> (zextload x)
if (N0.getOpcode() == ISD::EXTLOAD) {
MVT::ValueType EVT = cast(N0.getOperand(3))->getVT();
@@ -1252,8 +1247,6 @@
SDOperand DAGCombiner::visitSHL(SDNode *N) {
SDOperand N0 = N->getOperand(0);
SDOperand N1 = N->getOperand(1);
- SDOperand Old = SDOperand();
- SDOperand New = SDOperand();
ConstantSDNode *N0C = dyn_cast(N0);
ConstantSDNode *N1C = dyn_cast(N1);
MVT::ValueType VT = N0.getValueType();
@@ -1272,14 +1265,10 @@
if (N1C && N1C->isNullValue())
return N0;
// if (shl x, c) is known to be zero, return 0
- if (N1C && TLI.MaskedValueIsZero(SDOperand(N, 0), ~0ULL >>
(64-OpSizeInBits)))
+ if (TLI.MaskedValueIsZero(SDOperand(N, 0), MVT::getIntVTBitMask(VT)))
return DAG.getConstant(0, VT);
- if (N1C && DemandedBitsAreZero(SDOperand(N,0), ~0ULL >> (64-OpSizeInBits),
- Old, New)) {
-WorkList.push_back(N);
-CombineTo(Old.Val, New);
+ if (DemandedBitsAreZero(SDOperand(N,0), MVT::getIntVTBitMask(VT)))
return SDOperand();
- }
// fold (shl (shl x, c1), c2) -> 0 or (shl x, c1+c2)
if (N1C && N0.getOpcode() == ISD::SHL &&
N0.getOperand(1).getOpcode() == ISD::Constant) {
@@ -1318,7 +1307,6 @@
ConstantSDNode *N0C = dyn_cast(N0);
ConstantSDNode *N1C = dyn_cast(N1);
MVT::ValueType VT = N0.getValueType();
- unsigned OpSizeInBits = MVT::getSizeInBits(VT);
// fold (sra c1, c2) -> c1>>c2
if (N0C && N1C)
@@ -1330,13 +1318,29 @@
if (N0C && N0C->isAllOnesValue())
return N0;
// fold (sra x, c >= size(x)) -> undef
- if (N1C && N1C->getValue() >= OpSizeInBits)
+ if (N1C && N1C->getValue() >= MVT::getSizeInBits(VT))
return DAG.getNode(ISD::UNDEF, VT);
// fold (sra x, 0) -> x
if (N1C && N1C->isNullValue())
return N0;
+ // fold (sra (shl x, c1), c1) -> sext_inreg for some c1 and target supports
+ // sext_inreg.
+ if (N1C && N0.getOpcode() == ISD::SHL && N1 == N0.getOperand(1)) {
+unsigned LowBits = MVT::getSizeInBits(VT) - (unsigned)N1C->getValue();
+MVT::ValueType EVT;
+switch (LowBits) {
+default: EVT = MVT::Other; break;
+case 1: EVT = MVT::i1;break;
+case 8: EVT = MVT::i8;break;
+case 16: EVT = MVT::i16; break;
+case 32: EVT = MVT::i32; break;
+}
+if (EVT > MVT::Other && TLI.isOperationLegal(IS
[llvm-commits] CVS: llvm/docs/LangRef.html
Changes in directory llvm/docs: LangRef.html updated: 1.134 -> 1.135 --- Log message: Added documentation for vset and vselect. --- Diffs of the changes: (+159 -5) LangRef.html | 164 +-- 1 files changed, 159 insertions(+), 5 deletions(-) Index: llvm/docs/LangRef.html diff -u llvm/docs/LangRef.html:1.134 llvm/docs/LangRef.html:1.135 --- llvm/docs/LangRef.html:1.134Wed Jan 25 17:47:57 2006 +++ llvm/docs/LangRef.html Fri Feb 17 15:18:08 2006 @@ -29,7 +29,7 @@ Type System - Primitive Types + Primitive Types Type Classifications @@ -96,9 +96,9 @@ 'malloc' Instruction 'free' Instruction 'alloca' Instruction -'load' Instruction -'store'Instruction -'getelementptr' Instruction + 'load' Instruction + 'store'Instruction + 'getelementptr' Instruction Other Operations @@ -106,6 +106,8 @@ 'phi' Instruction 'cast .. to' Instruction 'select' Instruction + 'vset' Instruction + 'vselect' Instruction 'extractelement' Instruction 'insertelement' Instruction 'call' Instruction @@ -1619,6 +1621,7 @@ Example:= rem int 4, %var ; yields {int}:result = 4 % %var + 'setcc' @@ -1664,6 +1667,7 @@ = setge sbyte 4, 5; yields {bool}:result = false + Bitwise Binary Operations @@ -2333,6 +2337,156 @@ + + 'vset' +Instruction + +Syntax: + = vset , > , ; yields + + +Overview: + +The 'vset' instruction returns a vector of boolean +values representing, at each position, the result of the comparison +between the values at that position in the two operands. + +Arguments: + +The arguments to a 'vset' instruction are a comparison +operation and two value arguments. The value arguments must be of packed type, and they must have identical types. +For value arguments of integral element type, the operation argument +must be one of eq, ne, lt, gt, +le, ge, ult, ugt, ule, +uge, true, and false. For value arguments +of floating point element type, the operation argument must be one of +eq, ne, lt, gt, le, +ge, oeq, one, olt, ogt, +ole, oge, ueq, une, ult, +ugt, ule, uge, o, u, +true, and false. The result is a packed +bool value with the same length as each operand. + +Semantics: + +The following table shows the semantics of 'vset' for +integral value arguments. For each position of the result, the +comparison is done on the corresponding positions of the two value +arguments. Note that the signedness of the comparison depends on the +comparison opcode and not on the signedness of the value +operands. E.g., vset lt <4 x unsigned> %x, %y does an +elementwise signed comparison of %x and +%y. + + + +OperationResult is true iffComparison is +eqvar1 == var2-- +nevar1 != var2-- +ltvar1 < var2signed +gtvar1 > var2signed +levar1 <= var2signed +gevar1 >= var2signed +ultvar1 < var2unsigned +ugtvar1 > var2unsigned +ulevar1 <= var2unsigned +ugevar1 >= var2unsigned +truealways-- +falsenever-- + + + +The following table shows the semantics of 'vset' for +floating point types. If either operand is a floating point Not a +Number (NaN) value, the operation is unordered, and the value in the +first column below is produced at that position. Otherwise, the +operation is ordered, and the value in the second column is +produced. + + + +OperationIf unorderedOtherwise true iff +equndefinedvar1 == var2 +neundefinedvar1 != var2 +ltundefinedvar1 < var2 +gtundefinedvar1 > var2 +leundefinedvar1 <= var2 +geundefinedvar1 >= var2 +oeqfalsevar1 == var2 +onefalsevar1 != var2 +oltfalsevar1 < var2 +ogtfalsevar1 > var2 +olefalsevar1 <= var2 +ogefalsevar1 >= var2 +ueqtruevar1 == var2 +unetruevar1 != var2 +ulttruevar1 < var2 +ugttruevar1 > var2 +uletruevar1 <= var2 +ugetruevar1 >= var2 +ofalsealways +utruenever +truetruealways +falsefalsenever + + + +Example: + = vset eq <2 x int> , ; yields {<2 x bool>}:result = false, false + = vset ne <2 x int> , ; yields {<2 x bool>}:result = true, true + = vset lt <2 x int> , ; yields {<2 x bool>}:result = true, false + = vset gt <2 x int> , ; yields {<2 x bool>}:result = false, true + = vset le <2 x int> , ; yields {<2 x bool>}:result = true, false + = vset ge <2 x int> , ; yields {<2 x bool>}:result = false, true + + + + + + 'vselect' Instruction + + + +
[llvm-commits] CVS: llvm/test/Regression/CodeGen/PowerPC/and_sext.ll and_sra.ll extsh.ll
Changes in directory llvm/test/Regression/CodeGen/PowerPC:
and_sext.ll added (r1.1)
and_sra.ll added (r1.1)
extsh.ll added (r1.1)
---
Log message:
New tests!
---
Diffs of the changes: (+34 -0)
and_sext.ll |9 +
and_sra.ll | 18 ++
extsh.ll|7 +++
3 files changed, 34 insertions(+)
Index: llvm/test/Regression/CodeGen/PowerPC/and_sext.ll
diff -c /dev/null llvm/test/Regression/CodeGen/PowerPC/and_sext.ll:1.1
*** /dev/null Fri Feb 17 15:22:18 2006
--- llvm/test/Regression/CodeGen/PowerPC/and_sext.llFri Feb 17 15:22:08 2006
***
*** 0
--- 1,9
+ ; This test should not contain a sign extend
+ ; RUN: llvm-as < %s | llc -march=ppc32 | not grep extsh
+
+ int %test(uint %mode.0.i.0) {
+ %tmp.79 = cast uint %mode.0.i.0 to short; [#uses=1]
+ %tmp.80 = cast short %tmp.79 to int ; [#uses=1]
+ %tmp.81 = and int %tmp.80, 24 ; [#uses=1]
+ ret int %tmp.81
+ }
Index: llvm/test/Regression/CodeGen/PowerPC/and_sra.ll
diff -c /dev/null llvm/test/Regression/CodeGen/PowerPC/and_sra.ll:1.1
*** /dev/null Fri Feb 17 15:22:20 2006
--- llvm/test/Regression/CodeGen/PowerPC/and_sra.ll Fri Feb 17 15:22:08 2006
***
*** 0
--- 1,18
+ ; Neither of these functions should contain algebraic right shifts
+ ; RUN: llvm-as < %s | llc -march=ppc32 | not grep srawi
+
+ int %test1(uint %mode.0.i.0) {
+ %tmp.79 = cast uint %mode.0.i.0 to int; [#uses=1]
+ %tmp.80 = shr int %tmp.79, ubyte 15 ; [#uses=1]
+ %tmp.81 = and int %tmp.80, 24 ; [#uses=1]
+ ret int %tmp.81
+ }
+
+ int %test2(uint %mode.0.i.0) {
+ %tmp.79 = cast uint %mode.0.i.0 to int; [#uses=1]
+ %tmp.80 = shr int %tmp.79, ubyte 15 ; [#uses=1]
+ %tmp.81 = shr uint %mode.0.i.0, ubyte 16
+ %tmp.82 = cast uint %tmp.81 to int
+ %tmp.83 = and int %tmp.80, %tmp.82 ; [#uses=1]
+ ret int %tmp.83
+ }
Index: llvm/test/Regression/CodeGen/PowerPC/extsh.ll
diff -c /dev/null llvm/test/Regression/CodeGen/PowerPC/extsh.ll:1.1
*** /dev/null Fri Feb 17 15:22:20 2006
--- llvm/test/Regression/CodeGen/PowerPC/extsh.ll Fri Feb 17 15:22:08 2006
***
*** 0
--- 1,7
+ ; This should turn into a single extsh
+ ; RUN: llvm-as < %s | llc -march=ppc32 | grep extsh | wc -l | grep 1
+ int %test(int %X) {
+ %tmp.81 = shl int %X, ubyte 16 ; [#uses=1]
+ %tmp.82 = shr int %tmp.81, ubyte 16 ; [#uses=1]
+ ret int %tmp.82
+ }
___
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[llvm-commits] CVS: llvm/test/Regression/CodeGen/PowerPC/shl_sext.ll
Changes in directory llvm/test/Regression/CodeGen/PowerPC:
shl_sext.ll added (r1.1)
---
Log message:
Yet another test
---
Diffs of the changes: (+9 -0)
shl_sext.ll |9 +
1 files changed, 9 insertions(+)
Index: llvm/test/Regression/CodeGen/PowerPC/shl_sext.ll
diff -c /dev/null llvm/test/Regression/CodeGen/PowerPC/shl_sext.ll:1.1
*** /dev/null Fri Feb 17 15:32:56 2006
--- llvm/test/Regression/CodeGen/PowerPC/shl_sext.llFri Feb 17 15:32:46 2006
***
*** 0
--- 1,9
+ ; This test should not contain a sign extend
+ ; RUN: llvm-as < %s | llc -march=ppc32 | not grep extsb
+
+ int %test(uint %mode.0.i.0) {
+ %tmp.79 = cast uint %mode.0.i.0 to sbyte; [#uses=1]
+ %tmp.80 = cast sbyte %tmp.79 to int ; [#uses=1]
+ %tmp.81 = shl int %tmp.80, ubyte 24 ; [#uses=1]
+ ret int %tmp.81
+ }
___
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[llvm-commits] CVS: llvm/test/Regression/CodeGen/PowerPC/and_sra.ll shl_sext.ll
Changes in directory llvm/test/Regression/CodeGen/PowerPC:
and_sra.ll updated: 1.1 -> 1.2
shl_sext.ll updated: 1.1 -> 1.2
---
Log message:
A few final (for now) tests
---
Diffs of the changes: (+16 -0)
and_sra.ll |8
shl_sext.ll |8
2 files changed, 16 insertions(+)
Index: llvm/test/Regression/CodeGen/PowerPC/and_sra.ll
diff -u llvm/test/Regression/CodeGen/PowerPC/and_sra.ll:1.1
llvm/test/Regression/CodeGen/PowerPC/and_sra.ll:1.2
--- llvm/test/Regression/CodeGen/PowerPC/and_sra.ll:1.1 Fri Feb 17 15:22:08 2006
+++ llvm/test/Regression/CodeGen/PowerPC/and_sra.ll Fri Feb 17 15:38:45 2006
@@ -16,3 +16,11 @@
%tmp.83 = and int %tmp.80, %tmp.82 ; [#uses=1]
ret int %tmp.83
}
+
+uint %test3(int %specbits.6.1) {
+%tmp.2540 = shr int %specbits.6.1, ubyte 11 ;
[#uses=1]
+%tmp.2541 = cast int %tmp.2540 to uint ; [#uses=1]
+%tmp.2542 = shl uint %tmp.2541, ubyte 13;
[#uses=1]
+%tmp.2543 = and uint %tmp.2542, 8192; [#uses=1]
+ret uint %tmp.2543
+}
Index: llvm/test/Regression/CodeGen/PowerPC/shl_sext.ll
diff -u llvm/test/Regression/CodeGen/PowerPC/shl_sext.ll:1.1
llvm/test/Regression/CodeGen/PowerPC/shl_sext.ll:1.2
--- llvm/test/Regression/CodeGen/PowerPC/shl_sext.ll:1.1Fri Feb 17
15:32:46 2006
+++ llvm/test/Regression/CodeGen/PowerPC/shl_sext.llFri Feb 17 15:38:45 2006
@@ -7,3 +7,11 @@
%tmp.81 = shl int %tmp.80, ubyte 24 ; [#uses=1]
ret int %tmp.81
}
+
+int %test2(uint %mode.0.i.0) {
+%tmp.79 = cast uint %mode.0.i.0 to sbyte; [#uses=1]
+%tmp.80 = cast sbyte %tmp.79 to int ; [#uses=1]
+%tmp.81 = shl int %tmp.80, ubyte 16 ; [#uses=1]
+%tmp.82 = and int %tmp.81, 16711680
+ret int %tmp.82
+}
___
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[llvm-commits] CVS: llvm/include/llvm/CodeGen/SelectionDAG.h
Changes in directory llvm/include/llvm/CodeGen: SelectionDAG.h updated: 1.98 -> 1.99 --- Log message: add a new method --- Diffs of the changes: (+7 -0) SelectionDAG.h |7 +++ 1 files changed, 7 insertions(+) Index: llvm/include/llvm/CodeGen/SelectionDAG.h diff -u llvm/include/llvm/CodeGen/SelectionDAG.h:1.98 llvm/include/llvm/CodeGen/SelectionDAG.h:1.99 --- llvm/include/llvm/CodeGen/SelectionDAG.h:1.98 Mon Feb 13 02:54:46 2006 +++ llvm/include/llvm/CodeGen/SelectionDAG.hFri Feb 17 15:57:00 2006 @@ -408,6 +408,13 @@ void ReplaceAllUsesWith(SDNode *From, const std::vector &To, std::vector *Deleted = 0); + /// ReplaceAllUsesOfValueWith - Replace any uses of From with To, leaving + /// uses of other values produced by From.Val alone. The Deleted vector is + /// handled the same was as for ReplaceAllUsesWith, but it is required for + /// this method. + void ReplaceAllUsesOfValueWith(SDOperand From, SDOperand To, + std::vector &Deleted); + /// DeleteNode - Remove the specified node from the system. This node must /// have no referrers. void DeleteNode(SDNode *N); ___ llvm-commits mailing list llvm-commits@cs.uiuc.edu http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
[llvm-commits] CVS: llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp SelectionDAG.cpp
Changes in directory llvm/lib/CodeGen/SelectionDAG:
DAGCombiner.cpp updated: 1.106 -> 1.107
SelectionDAG.cpp updated: 1.257 -> 1.258
---
Log message:
Fix a tricky issue in the SimplifyDemandedBits code where CombineTo wasn't
exactly the API we wanted to call into. This fixes the crash on crafty last
night.
---
Diffs of the changes: (+95 -9)
DAGCombiner.cpp | 43 ++
SelectionDAG.cpp | 61 +++
2 files changed, 95 insertions(+), 9 deletions(-)
Index: llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
diff -u llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp:1.106
llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp:1.107
--- llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp:1.106 Fri Feb 17 13:54:08 2006
+++ llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp Fri Feb 17 15:58:01 2006
@@ -99,15 +99,40 @@
return SDOperand(N, 0);
}
-bool DemandedBitsAreZero(SDOperand Op, uint64_t DemandedMask) {
+/// SimplifyDemandedBits - Check the specified integer node value to see if
+/// it can be simplified or if things is uses can be simplified by bit
+/// propagation. If so, return true.
+bool SimplifyDemandedBits(SDOperand Op) {
TargetLowering::TargetLoweringOpt TLO(DAG);
uint64_t KnownZero, KnownOne;
- if (TLI.SimplifyDemandedBits(Op, DemandedMask, KnownZero, KnownOne,
TLO)){
-WorkList.push_back(Op.Val);
-CombineTo(TLO.Old.Val, TLO.New);
-return true;
- }
- return false;
+ uint64_t Demanded = MVT::getIntVTBitMask(Op.getValueType());
+ if (!TLI.SimplifyDemandedBits(Op, Demanded, KnownZero, KnownOne, TLO))
+return false;
+
+ // Revisit the node.
+ WorkList.push_back(Op.Val);
+
+ // Replace the old value with the new one.
+ ++NodesCombined;
+ DEBUG(std::cerr << "\nReplacing "; TLO.Old.Val->dump();
+std::cerr << "\nWith: "; TLO.New.Val->dump());
+
+ std::vector NowDead;
+ DAG.ReplaceAllUsesOfValueWith(TLO.Old, TLO.New, NowDead);
+
+ // Push the new node and any (now) users onto the worklist.
+ WorkList.push_back(TLO.New.Val);
+ AddUsersToWorkList(TLO.New.Val);
+
+ // Nodes can end up on the worklist more than once. Make sure we do
+ // not process a node that has been replaced.
+ removeFromWorkList(TLO.Old.Val);
+ for (unsigned i = 0, e = NowDead.size(); i != e; ++i)
+removeFromWorkList(NowDead[i]);
+
+ // Finally, since the node is now dead, remove it from the graph.
+ DAG.DeleteNode(TLO.Old.Val);
+ return true;
}
SDOperand CombineTo(SDNode *N, SDOperand Res) {
@@ -985,7 +1010,7 @@
}
// fold (and (sign_extend_inreg x, i16 to i32), 1) -> (and x, 1)
// fold (and (sra)) -> (and (srl)) when possible.
- if (DemandedBitsAreZero(SDOperand(N, 0), MVT::getIntVTBitMask(VT)))
+ if (SimplifyDemandedBits(SDOperand(N, 0)))
return SDOperand();
// fold (zext_inreg (extload x)) -> (zextload x)
if (N0.getOpcode() == ISD::EXTLOAD) {
@@ -1267,7 +1292,7 @@
// if (shl x, c) is known to be zero, return 0
if (TLI.MaskedValueIsZero(SDOperand(N, 0), MVT::getIntVTBitMask(VT)))
return DAG.getConstant(0, VT);
- if (DemandedBitsAreZero(SDOperand(N,0), MVT::getIntVTBitMask(VT)))
+ if (SimplifyDemandedBits(SDOperand(N, 0)))
return SDOperand();
// fold (shl (shl x, c1), c2) -> 0 or (shl x, c1+c2)
if (N1C && N0.getOpcode() == ISD::SHL &&
Index: llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
diff -u llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp:1.257
llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp:1.258
--- llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp:1.257Thu Feb 16
23:43:56 2006
+++ llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp Fri Feb 17 15:58:01 2006
@@ -21,6 +21,7 @@
#include "llvm/Target/TargetLowering.h"
#include "llvm/Target/TargetInstrInfo.h"
#include "llvm/Target/TargetMachine.h"
+#include "llvm/ADT/SetVector.h"
#include "llvm/ADT/StringExtras.h"
#include
#include
@@ -2403,6 +2404,66 @@
}
}
+/// ReplaceAllUsesOfValueWith - Replace any uses of From with To, leaving
+/// uses of other values produced by From.Val alone. The Deleted vector is
+/// handled the same was as for ReplaceAllUsesWith.
+void SelectionDAG::ReplaceAllUsesOfValueWith(SDOperand From, SDOperand To,
+ std::vector &Deleted) {
+ assert(From != To && "Cannot replace a value with itself");
+ // Handle the simple, trivial, case efficiently.
+ if (From.Val->getNumValues() == 1 && To.Val->getNumValues() == 1) {
+ReplaceAllUsesWith(From, To, &Deleted);
+return;
+ }
+
+ // Get all of the users in a nice, deterministically ordered, uniqued set.
+ SetVector Users(From.Val->use_begin(), From.Val->use_end());
+
+ while (!Users.empty()) {
+// We know that this user uses some value of From. If it is the right
+//
[llvm-commits] CVS: llvm-test/MultiSource/Makefile.multisrc
Changes in directory llvm-test/MultiSource: Makefile.multisrc updated: 1.50 -> 1.51 --- Log message: Add -mdynamic-no-pic to native compiler (gcc) options for Darwin. --- Diffs of the changes: (+3 -3) Makefile.multisrc |6 +++--- 1 files changed, 3 insertions(+), 3 deletions(-) Index: llvm-test/MultiSource/Makefile.multisrc diff -u llvm-test/MultiSource/Makefile.multisrc:1.50 llvm-test/MultiSource/Makefile.multisrc:1.51 --- llvm-test/MultiSource/Makefile.multisrc:1.50Wed Feb 1 00:50:56 2006 +++ llvm-test/MultiSource/Makefile.multisrc Fri Feb 17 18:02:32 2006 @@ -29,13 +29,13 @@ .PRECIOUS: $(LObjects) $(NObjects) Output/%.linked.rll Output/%.o: %.c Output/.dir - -$(CC) $(CPPFLAGS) $(CFLAGS) -O2 -c $< -o $@ + -$(CC) $(CPPFLAGS) $(CFLAGS) -O2 $(TARGET_CFLAGS) -c $< -o $@ Output/%.o: %.cpp Output/.dir - -$(CC) $(CPPFLAGS) $(CXXFLAGS) -O2 -c $< -o $@ + -$(CC) $(CPPFLAGS) $(CXXFLAGS) -O2 $(TARGET_CFLAGS) -c $< -o $@ Output/%.o: %.cc Output/.dir - -$(CC) $(CPPFLAGS) $(CXXFLAGS) -O2 -c $< -o $@ + -$(CC) $(CPPFLAGS) $(CXXFLAGS) -O2 $(TARGET_CFLAGS) -c $< -o $@ bugpoint-gccas: Output/$(PROG).bugpoint-gccas bugpoint-gccld: Output/$(PROG).bugpoint-gccld ___ llvm-commits mailing list llvm-commits@cs.uiuc.edu http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
[llvm-commits] CVS: llvm-test/SingleSource/Makefile.singlesrc
Changes in directory llvm-test/SingleSource: Makefile.singlesrc updated: 1.28 -> 1.29 --- Log message: Add -mdynamic-no-pic to native compiler (gcc) options for Darwin. --- Diffs of the changes: (+2 -2) Makefile.singlesrc |4 ++-- 1 files changed, 2 insertions(+), 2 deletions(-) Index: llvm-test/SingleSource/Makefile.singlesrc diff -u llvm-test/SingleSource/Makefile.singlesrc:1.28 llvm-test/SingleSource/Makefile.singlesrc:1.29 --- llvm-test/SingleSource/Makefile.singlesrc:1.28 Sun May 15 14:46:42 2005 +++ llvm-test/SingleSource/Makefile.singlesrc Fri Feb 17 18:02:32 2006 @@ -35,6 +35,6 @@ # FIXME: LIBS should be specified, not hardcoded to -lm Output/%.native: $(SourceDir)/%.c Output/.dir - -$(CC) $(CFLAGS) -O2 $< -lm -o $@ $(LDFLAGS) + -$(CC) $(CFLAGS) -O2 $(TARGET_CFLAGS) $< -lm -o $@ $(LDFLAGS) Output/%.native: $(SourceDir)/%.cpp Output/.dir - -$(CXX) $(CXXFLAGS) -O2 $< -lm -o $@ $(LDFLAGS) + -$(CXX) $(CXXFLAGS) -O2 $(TARGET_CFLAGS) $< -lm -o $@ $(LDFLAGS) ___ llvm-commits mailing list llvm-commits@cs.uiuc.edu http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
[llvm-commits] CVS: llvm-test/Makefile.programs
Changes in directory llvm-test: Makefile.programs updated: 1.192 -> 1.193 --- Log message: Add -mdynamic-no-pic to native compiler (gcc) options for Darwin. --- Diffs of the changes: (+4 -0) Makefile.programs |4 1 files changed, 4 insertions(+) Index: llvm-test/Makefile.programs diff -u llvm-test/Makefile.programs:1.192 llvm-test/Makefile.programs:1.193 --- llvm-test/Makefile.programs:1.192 Tue Feb 14 02:09:05 2006 +++ llvm-test/Makefile.programs Fri Feb 17 18:02:32 2006 @@ -203,6 +203,10 @@ LLCBETAOPTION := -enable-sparc-v9-insts endif +ifeq ($(OS),Darwin) +TARGET_CFLAGS := -mdynamic-no-pic +endif + # Given a version of the entire program linked together into a single unit of # raw output from the C frontend, optimize it. $(PROGRAMS_TO_TEST:%=Output/%.linked.bc): \ ___ llvm-commits mailing list llvm-commits@cs.uiuc.edu http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
[llvm-commits] CVS: llvm/include/llvm/Target/TargetOptions.h
Changes in directory llvm/include/llvm/Target: TargetOptions.h updated: 1.6 -> 1.7 --- Log message: Move PICEnabled declaration here. --- Diffs of the changes: (+6 -0) TargetOptions.h |6 ++ 1 files changed, 6 insertions(+) Index: llvm/include/llvm/Target/TargetOptions.h diff -u llvm/include/llvm/Target/TargetOptions.h:1.6 llvm/include/llvm/Target/TargetOptions.h:1.7 --- llvm/include/llvm/Target/TargetOptions.h:1.6Thu Aug 18 18:53:15 2005 +++ llvm/include/llvm/Target/TargetOptions.hFri Feb 17 18:06:03 2006 @@ -40,6 +40,12 @@ /// produce results that are "less precise" than IEEE allows. This includes /// use of X86 instructions like FSIN and FCOS instead of libcalls. extern bool UnsafeFPMath; + + /// PICEnabled - This flag is enabled when the -enable-pic flag is specified + /// on the command line. When this flag is on, the code generator produces + /// position independant code. + extern bool PICEnabled; + } // End llvm namespace #endif ___ llvm-commits mailing list llvm-commits@cs.uiuc.edu http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
[llvm-commits] CVS: llvm/lib/Target/PowerPC/PPC.h PPCAsmPrinter.cpp PPCCodeEmitter.cpp PPCISelLowering.cpp
Changes in directory llvm/lib/Target/PowerPC: PPC.h updated: 1.25 -> 1.26 PPCAsmPrinter.cpp updated: 1.151 -> 1.152 PPCCodeEmitter.cpp updated: 1.45 -> 1.46 PPCISelLowering.cpp updated: 1.87 -> 1.88 --- Log message: Moved PICEnabled to include/llvm/Target/TargetOptions.h --- Diffs of the changes: (+3 -1) PPC.h |1 - PPCAsmPrinter.cpp |1 + PPCCodeEmitter.cpp |1 + PPCISelLowering.cpp |1 + 4 files changed, 3 insertions(+), 1 deletion(-) Index: llvm/lib/Target/PowerPC/PPC.h diff -u llvm/lib/Target/PowerPC/PPC.h:1.25 llvm/lib/Target/PowerPC/PPC.h:1.26 --- llvm/lib/Target/PowerPC/PPC.h:1.25 Wed Jan 11 19:46:07 2006 +++ llvm/lib/Target/PowerPC/PPC.h Fri Feb 17 18:08:58 2006 @@ -31,7 +31,6 @@ FunctionPass *createDarwinAsmPrinter(std::ostream &OS, TargetMachine &TM); FunctionPass *createAIXAsmPrinter(std::ostream &OS, TargetMachine &TM); -extern bool PICEnabled; extern bool PPCGenerateStaticCode; extern PPCTargetEnum PPCTarget; } // end namespace llvm; Index: llvm/lib/Target/PowerPC/PPCAsmPrinter.cpp diff -u llvm/lib/Target/PowerPC/PPCAsmPrinter.cpp:1.151 llvm/lib/Target/PowerPC/PPCAsmPrinter.cpp:1.152 --- llvm/lib/Target/PowerPC/PPCAsmPrinter.cpp:1.151 Tue Feb 14 16:18:23 2006 +++ llvm/lib/Target/PowerPC/PPCAsmPrinter.cpp Fri Feb 17 18:08:58 2006 @@ -35,6 +35,7 @@ #include "llvm/Support/Debug.h" #include "llvm/Target/MRegisterInfo.h" #include "llvm/Target/TargetInstrInfo.h" +#include "llvm/Target/TargetOptions.h" #include "llvm/ADT/Statistic.h" #include "llvm/ADT/StringExtras.h" #include Index: llvm/lib/Target/PowerPC/PPCCodeEmitter.cpp diff -u llvm/lib/Target/PowerPC/PPCCodeEmitter.cpp:1.45 llvm/lib/Target/PowerPC/PPCCodeEmitter.cpp:1.46 --- llvm/lib/Target/PowerPC/PPCCodeEmitter.cpp:1.45 Sun Jan 29 14:49:17 2006 +++ llvm/lib/Target/PowerPC/PPCCodeEmitter.cpp Fri Feb 17 18:08:58 2006 @@ -22,6 +22,7 @@ #include "llvm/CodeGen/MachineInstrBuilder.h" #include "llvm/CodeGen/Passes.h" #include "llvm/Support/Debug.h" +#include "llvm/Target/TargetOptions.h" #include using namespace llvm; Index: llvm/lib/Target/PowerPC/PPCISelLowering.cpp diff -u llvm/lib/Target/PowerPC/PPCISelLowering.cpp:1.87 llvm/lib/Target/PowerPC/PPCISelLowering.cpp:1.88 --- llvm/lib/Target/PowerPC/PPCISelLowering.cpp:1.87Mon Feb 13 02:55:29 2006 +++ llvm/lib/Target/PowerPC/PPCISelLowering.cpp Fri Feb 17 18:08:58 2006 @@ -22,6 +22,7 @@ #include "llvm/Constants.h" #include "llvm/Function.h" #include "llvm/Support/MathExtras.h" +#include "llvm/Target/TargetOptions.h" using namespace llvm; PPCTargetLowering::PPCTargetLowering(TargetMachine &TM) ___ llvm-commits mailing list llvm-commits@cs.uiuc.edu http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
[llvm-commits] CVS: llvm/lib/Target/X86/X86ATTAsmPrinter.cpp X86ATTAsmPrinter.h X86ISelDAGToDAG.cpp X86ISelLowering.cpp X86ISelLowering.h X86InstrInfo.td X86IntelAsmPrinter.cpp X86IntelAsmPrinter.h X8
Changes in directory llvm/lib/Target/X86:
X86ATTAsmPrinter.cpp updated: 1.22 -> 1.23
X86ATTAsmPrinter.h updated: 1.6 -> 1.7
X86ISelDAGToDAG.cpp updated: 1.49 -> 1.50
X86ISelLowering.cpp updated: 1.88 -> 1.89
X86ISelLowering.h updated: 1.27 -> 1.28
X86InstrInfo.td updated: 1.237 -> 1.238
X86IntelAsmPrinter.cpp updated: 1.16 -> 1.17
X86IntelAsmPrinter.h updated: 1.7 -> 1.8
X86Subtarget.cpp updated: 1.25 -> 1.26
X86Subtarget.h updated: 1.11 -> 1.12
---
Log message:
x86 / Darwin PIC support.
---
Diffs of the changes: (+143 -36)
X86ATTAsmPrinter.cpp | 23 +--
X86ATTAsmPrinter.h |1 +
X86ISelDAGToDAG.cpp| 39 +++
X86ISelLowering.cpp| 40
X86ISelLowering.h |4
X86InstrInfo.td|7 +++
X86IntelAsmPrinter.cpp | 47 +++
X86IntelAsmPrinter.h |1 +
X86Subtarget.cpp |5 +
X86Subtarget.h | 12 ++--
10 files changed, 143 insertions(+), 36 deletions(-)
Index: llvm/lib/Target/X86/X86ATTAsmPrinter.cpp
diff -u llvm/lib/Target/X86/X86ATTAsmPrinter.cpp:1.22
llvm/lib/Target/X86/X86ATTAsmPrinter.cpp:1.23
--- llvm/lib/Target/X86/X86ATTAsmPrinter.cpp:1.22 Tue Feb 7 02:38:37 2006
+++ llvm/lib/Target/X86/X86ATTAsmPrinter.cppFri Feb 17 18:15:05 2006
@@ -18,6 +18,7 @@
#include "X86TargetMachine.h"
#include "llvm/Module.h"
#include "llvm/Support/Mangler.h"
+#include "llvm/Target/TargetOptions.h"
#include
using namespace llvm;
using namespace x86;
@@ -116,9 +117,9 @@
case MachineOperand::MO_GlobalAddress: {
bool isCallOp = Modifier && !strcmp(Modifier, "call");
bool isMemOp = Modifier && !strcmp(Modifier, "mem");
+if (!isMemOp && !isCallOp) O << '$';
// Darwin block shameless ripped from PPCAsmPrinter.cpp
if (forDarwin) {
- if (!isMemOp && !isCallOp) O << '$';
GlobalValue *GV = MO.getGlobal();
std::string Name = Mang->getValueName(GV);
// Link-once, External, or Weakly-linked global variables need
@@ -132,19 +133,14 @@
} else {
GVStubs.insert(Name);
O << "L" << Name << "$non_lazy_ptr";
+ if (PICEnabled)
+O << "-\"L" << getFunctionNumber() << "$pb\"";
}
} else {
O << Mang->getValueName(GV);
}
- int Offset = MO.getOffset();
- if (Offset > 0)
-O << "+" << Offset;
- else if (Offset < 0)
-O << Offset;
- return;
-}
-if (!isMemOp && !isCallOp) O << '$';
-O << Mang->getValueName(MO.getGlobal());
+} else
+ O << Mang->getValueName(MO.getGlobal());
int Offset = MO.getOffset();
if (Offset > 0)
O << "+" << Offset;
@@ -202,6 +198,8 @@
} else if (BaseReg.isConstantPoolIndex()) {
O << PrivateGlobalPrefix << "CPI" << getFunctionNumber() << "_"
<< BaseReg.getConstantPoolIndex();
+if (forDarwin && PICEnabled)
+ O << "-\"L" << getFunctionNumber() << "$pb\"";
if (DispSpec.getImmedValue())
O << "+" << DispSpec.getImmedValue();
if (IndexReg.getReg()) {
@@ -238,6 +236,11 @@
}
}
+void X86ATTAsmPrinter::printPICLabel(const MachineInstr *MI, unsigned Op) {
+ O << "\"L" << getFunctionNumber() << "$pb\"\n";
+ O << "\"L" << getFunctionNumber() << "$pb\":";
+}
+
/// printMachineInstruction -- Print out a single X86 LLVM instruction
/// MI in Intel syntax to the current output stream.
///
Index: llvm/lib/Target/X86/X86ATTAsmPrinter.h
diff -u llvm/lib/Target/X86/X86ATTAsmPrinter.h:1.6
llvm/lib/Target/X86/X86ATTAsmPrinter.h:1.7
--- llvm/lib/Target/X86/X86ATTAsmPrinter.h:1.6 Mon Feb 6 17:41:19 2006
+++ llvm/lib/Target/X86/X86ATTAsmPrinter.h Fri Feb 17 18:15:05 2006
@@ -62,6 +62,7 @@
void printMachineInstruction(const MachineInstr *MI);
void printSSECC(const MachineInstr *MI, unsigned Op);
void printMemReference(const MachineInstr *MI, unsigned Op);
+ void printPICLabel(const MachineInstr *MI, unsigned Op);
bool runOnMachineFunction(MachineFunction &F);
};
Index: llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
diff -u llvm/lib/Target/X86/X86ISelDAGToDAG.cpp:1.49
llvm/lib/Target/X86/X86ISelDAGToDAG.cpp:1.50
--- llvm/lib/Target/X86/X86ISelDAGToDAG.cpp:1.49Fri Feb 10 20:05:36 2006
+++ llvm/lib/Target/X86/X86ISelDAGToDAG.cpp Fri Feb 17 18:15:05 2006
@@ -85,12 +85,20 @@
/// Subtarget - Keep a pointer to the X86Subtarget around so that we can
/// make the right decision when generating code for different targets.
const X86Subtarget *Subtarget;
+
+unsigned GlobalBaseReg;
public:
X86DAGToDAGISel(TargetMachine &TM)
: SelectionDAGISel(X86Lowering), X86Lowering(TM) {
Subtarget = &TM.getSubtarget();
}
+virtual bool runOnFunction(Function &Fn) {
+ // Make sure we re-emit a set of the global base reg if necessary
+ GlobalBaseReg = 0;
+ return SelectionDAGISel::runOnFunct
[llvm-commits] CVS: llvm/test/Regression/Transforms/SimplifyCFG/2006-02-17-InfiniteUnroll.ll
Changes in directory llvm/test/Regression/Transforms/SimplifyCFG:
2006-02-17-InfiniteUnroll.ll added (r1.1)
---
Log message:
new testcase that crashes simplifycfg
---
Diffs of the changes: (+35 -0)
2006-02-17-InfiniteUnroll.ll | 35 +++
1 files changed, 35 insertions(+)
Index: llvm/test/Regression/Transforms/SimplifyCFG/2006-02-17-InfiniteUnroll.ll
diff -c /dev/null
llvm/test/Regression/Transforms/SimplifyCFG/2006-02-17-InfiniteUnroll.ll:1.1
*** /dev/null Fri Feb 17 18:32:54 2006
--- llvm/test/Regression/Transforms/SimplifyCFG/2006-02-17-InfiniteUnroll.ll
Fri Feb 17 18:32:44 2006
***
*** 0
--- 1,35
+ ; RUN: llvm-as < %s | opt -simplifycfg -disable-output
+
+ void %polnel_() {
+ entry:
+ %tmp595 = setlt int 0, 0; [#uses=4]
+ br bool %tmp595, label %bb148.critedge, label %cond_true40
+
+ bb36: ; preds = %bb43
+ br bool %tmp595, label %bb43, label %cond_true40
+
+ cond_true40: ; preds = %bb46, %cond_true40, %bb36, %entry
+ %tmp397 = setgt int 0, 0; [#uses=1]
+ br bool %tmp397, label %bb43, label %cond_true40
+
+ bb43: ; preds = %cond_true40, %bb36
+ br bool false, label %bb53, label %bb36
+
+ bb46: ; preds = %bb53
+ br bool %tmp595, label %bb53, label %cond_true40
+
+ bb53: ; preds = %bb46, %bb43
+ br bool false, label %bb102, label %bb46
+
+ bb92.preheader: ; preds = %bb102
+ ret void
+
+ bb102:; preds = %bb53
+ br bool %tmp595, label %bb148, label %bb92.preheader
+
+ bb148.critedge: ; preds = %entry
+ ret void
+
+ bb148:; preds = %bb102
+ ret void
+ }
___
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[llvm-commits] CVS: llvm/lib/Transforms/Utils/SimplifyCFG.cpp
Changes in directory llvm/lib/Transforms/Utils:
SimplifyCFG.cpp updated: 1.94 -> 1.95
---
Log message:
Fix Transforms/SimplifyCFG/2006-02-17-InfiniteUnroll.ll
---
Diffs of the changes: (+8 -2)
SimplifyCFG.cpp | 10 --
1 files changed, 8 insertions(+), 2 deletions(-)
Index: llvm/lib/Transforms/Utils/SimplifyCFG.cpp
diff -u llvm/lib/Transforms/Utils/SimplifyCFG.cpp:1.94
llvm/lib/Transforms/Utils/SimplifyCFG.cpp:1.95
--- llvm/lib/Transforms/Utils/SimplifyCFG.cpp:1.94 Sun Jan 22 16:53:01 2006
+++ llvm/lib/Transforms/Utils/SimplifyCFG.cpp Fri Feb 17 18:33:17 2006
@@ -1426,8 +1426,8 @@
PBI->setSuccessor(1, OldTrue);
}
-if (PBI->getSuccessor(0) == TrueDest ||
-PBI->getSuccessor(1) == FalseDest) {
+if ((PBI->getSuccessor(0) == TrueDest && FalseDest != BB) ||
+(PBI->getSuccessor(1) == FalseDest && TrueDest != BB)) {
// Clone Cond into the predecessor basic block, and or/and
the
// two conditions together.
Instruction *New = Cond->clone();
@@ -1512,6 +1512,12 @@
PBIOp = BIOp = -1;
}
+ // Check to make sure that the other destination of this branch
+ // isn't BB itself. If so, this is an infinite loop that will
+ // keep getting unwound.
+ if (PBIOp != -1 && PBI->getSuccessor(PBIOp) == BB)
+PBIOp = BIOp = -1;
+
// Finally, if everything is ok, fold the branches to logical
ops.
if (PBIOp != -1) {
BasicBlock *CommonDest = PBI->getSuccessor(PBIOp);
___
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[llvm-commits] CVS: llvm-test/MultiSource/Applications/JM/ldecod/data/test.264 test_dec.yuv
Changes in directory llvm-test/MultiSource/Applications/JM/ldecod/data: test.264 updated: 1.1 -> 1.2 test_dec.yuv (r1.1) removed --- Log message: Replace the original test.264 with a larger CIF / 15 frame bitstream. --- Diffs of the changes: (+0 -0) test.264 |0 1 files changed Index: llvm-test/MultiSource/Applications/JM/ldecod/data/test.264 ___ llvm-commits mailing list llvm-commits@cs.uiuc.edu http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
[llvm-commits] CVS: llvm/lib/Transforms/Scalar/LoopUnswitch.cpp
Changes in directory llvm/lib/Transforms/Scalar:
LoopUnswitch.cpp updated: 1.28 -> 1.29
---
Log message:
When unswitching a loop, make sure to update loop info with exit blocks in
the right loop.
---
Diffs of the changes: (+4 -2)
LoopUnswitch.cpp |6 --
1 files changed, 4 insertions(+), 2 deletions(-)
Index: llvm/lib/Transforms/Scalar/LoopUnswitch.cpp
diff -u llvm/lib/Transforms/Scalar/LoopUnswitch.cpp:1.28
llvm/lib/Transforms/Scalar/LoopUnswitch.cpp:1.29
--- llvm/lib/Transforms/Scalar/LoopUnswitch.cpp:1.28Fri Feb 17 00:39:56 2006
+++ llvm/lib/Transforms/Scalar/LoopUnswitch.cpp Fri Feb 17 18:55:32 2006
@@ -590,6 +590,7 @@
// Split all of the edges from inside the loop to their exit blocks. This
// unswitching trivial: no phi nodes to update.
unsigned NumBlocks = L->getBlocks().size();
+
for (unsigned i = 0, e = ExitBlocks.size(); i != e; ++i) {
BasicBlock *ExitBlock = ExitBlocks[i];
std::vector Preds(pred_begin(ExitBlock), pred_end(ExitBlock));
@@ -639,8 +640,9 @@
for (unsigned i = 0, e = ExitBlocks.size(); i != e; ++i) {
BasicBlock *NewExit = cast(ValueMap[ExitBlocks[i]]);
-if (ParentLoop)
- ParentLoop->addBasicBlockToLoop(cast(NewExit), *LI);
+// The new exit block should be in the same loop as the old one.
+if (Loop *ExitBBLoop = LI->getLoopFor(ExitBlocks[i]))
+ ExitBBLoop->addBasicBlockToLoop(NewExit, *LI);
assert(NewExit->getTerminator()->getNumSuccessors() == 1 &&
"Exit block should have been split to have one successor!");
___
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[llvm-commits] CVS: llvm/lib/Target/X86/X86CodeEmitter.cpp
Changes in directory llvm/lib/Target/X86:
X86CodeEmitter.cpp updated: 1.89 -> 1.90
---
Log message:
Jit does not support PIC yet.
---
Diffs of the changes: (+2 -0)
X86CodeEmitter.cpp |2 ++
1 files changed, 2 insertions(+)
Index: llvm/lib/Target/X86/X86CodeEmitter.cpp
diff -u llvm/lib/Target/X86/X86CodeEmitter.cpp:1.89
llvm/lib/Target/X86/X86CodeEmitter.cpp:1.90
--- llvm/lib/Target/X86/X86CodeEmitter.cpp:1.89 Tue Feb 14 15:52:51 2006
+++ llvm/lib/Target/X86/X86CodeEmitter.cpp Fri Feb 17 18:57:10 2006
@@ -22,6 +22,7 @@
#include "llvm/CodeGen/Passes.h"
#include "llvm/Function.h"
#include "llvm/ADT/Statistic.h"
+#include "llvm/Target/TargetOptions.h"
#include
using namespace llvm;
@@ -96,6 +97,7 @@
}
void Emitter::emitBasicBlock(const MachineBasicBlock &MBB) {
+ assert(!PICEnabled && "CodeEmitter does not support PIC!");
if (uint64_t Addr = MCE.getCurrentPCValue())
BasicBlockAddrs[&MBB] = Addr;
___
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[llvm-commits] CVS: llvm/lib/Transforms/Scalar/LoopUnswitch.cpp
Changes in directory llvm/lib/Transforms/Scalar:
LoopUnswitch.cpp updated: 1.29 -> 1.30
---
Log message:
initial trivial support for folding branches that have now-constant
destinations.
---
Diffs of the changes: (+34 -3)
LoopUnswitch.cpp | 37 ++---
1 files changed, 34 insertions(+), 3 deletions(-)
Index: llvm/lib/Transforms/Scalar/LoopUnswitch.cpp
diff -u llvm/lib/Transforms/Scalar/LoopUnswitch.cpp:1.29
llvm/lib/Transforms/Scalar/LoopUnswitch.cpp:1.30
--- llvm/lib/Transforms/Scalar/LoopUnswitch.cpp:1.29Fri Feb 17 18:55:32 2006
+++ llvm/lib/Transforms/Scalar/LoopUnswitch.cpp Fri Feb 17 19:27:45 2006
@@ -76,12 +76,14 @@
unsigned getLoopUnswitchCost(Loop *L, Value *LIC);
void VersionLoop(Value *LIC, Constant *OnVal,
Loop *L, Loop *&Out1, Loop *&Out2);
+void UnswitchTrivialCondition(Loop *L, Value *Cond, Constant *Val,
+ bool EntersWhenTrue, BasicBlock *ExitBlock);
BasicBlock *SplitEdge(BasicBlock *From, BasicBlock *To);
BasicBlock *SplitBlock(BasicBlock *Old, Instruction *SplitPt);
void RewriteLoopBodyWithConditionConstant(Loop *L, Value *LIC,Constant
*Val,
bool isEqual);
-void UnswitchTrivialCondition(Loop *L, Value *Cond, Constant *Val,
- bool EntersWhenTrue, BasicBlock *ExitBlock);
+bool TryToRemoveEdge(TerminatorInst *TI, unsigned SuccNo,
+ std::vector &Worklist);
};
RegisterOpt X("loop-unswitch", "Unswitch loops");
}
@@ -717,7 +719,25 @@
++NumSimplify;
}
-
+/// TryToRemoveEdge - Determine whether this is a case where we're smart enough
+/// to remove the specified edge from the CFG and know how to update loop
+/// information. If it is, update SSA and the loop information for the future
+/// change, then return true. If not, return false.
+bool LoopUnswitch::TryToRemoveEdge(TerminatorInst *TI, unsigned DeadSuccNo,
+ std::vector &Worklist) {
+ BasicBlock *BB = TI->getParent(), *Succ = TI->getSuccessor(DeadSuccNo);
+ Loop *BBLoop = LI->getLoopFor(BB);
+ Loop *SuccLoop = LI->getLoopFor(Succ);
+
+ // If this edge is not in a loop, or if this edge is leaving a loop to a
+ // non-loop area, this is trivial.
+ if (SuccLoop == 0) {
+Succ->removePredecessor(BB, true);
+return true;
+ }
+
+ return false;
+}
// RewriteLoopBodyWithConditionConstant - We know either that the value LIC has
// the value specified by Val in the specified loop, or we know it does NOT
have
@@ -875,7 +895,18 @@
// Remove Succ from the loop tree.
LI->removeBlock(Succ);
Succ->eraseFromParent();
+++NumSimplify;
break;
+ } else if (ConstantBool *CB =
dyn_cast(BI->getCondition())){
+// Conditional branch.
+if (TryToRemoveEdge(BI, CB->getValue(), Worklist)) {
+ DEBUG(std::cerr << "Folded branch: " << *BI);
+ new BranchInst(BI->getSuccessor(!CB->getValue()), BI);
+ BI->eraseFromParent();
+ RemoveFromWorklist(BI, Worklist);
+ ++NumSimplify;
+ break;
+}
}
break;
}
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[llvm-commits] CVS: llvm/lib/Transforms/Scalar/LoopUnswitch.cpp
Changes in directory llvm/lib/Transforms/Scalar:
LoopUnswitch.cpp updated: 1.30 -> 1.31
---
Log message:
a previous patch completely disabled trivial unswitching, this fixees it.
Thanks to nate for pointing this out :)
---
Diffs of the changes: (+0 -1)
LoopUnswitch.cpp |1 -
1 files changed, 1 deletion(-)
Index: llvm/lib/Transforms/Scalar/LoopUnswitch.cpp
diff -u llvm/lib/Transforms/Scalar/LoopUnswitch.cpp:1.30
llvm/lib/Transforms/Scalar/LoopUnswitch.cpp:1.31
--- llvm/lib/Transforms/Scalar/LoopUnswitch.cpp:1.30Fri Feb 17 19:27:45 2006
+++ llvm/lib/Transforms/Scalar/LoopUnswitch.cpp Fri Feb 17 19:32:04 2006
@@ -168,7 +168,6 @@
static BasicBlock *isTrivialLoopExitBlock(Loop *L, BasicBlock *BB) {
std::set Visited;
Visited.insert(L->getHeader()); // Branches to header are ok.
- Visited.insert(BB); // Don't revisit BB after we do.
BasicBlock *ExitBB = 0;
if (isTrivialLoopExitBlockHelper(L, BB, ExitBB, Visited))
return ExitBB;
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[llvm-commits] CVS: llvm/lib/Target/X86/X86TargetMachine.cpp
Changes in directory llvm/lib/Target/X86:
X86TargetMachine.cpp updated: 1.103 -> 1.104
---
Log message:
Disable PIC for JIT.
---
Diffs of the changes: (+3 -0)
X86TargetMachine.cpp |3 +++
1 files changed, 3 insertions(+)
Index: llvm/lib/Target/X86/X86TargetMachine.cpp
diff -u llvm/lib/Target/X86/X86TargetMachine.cpp:1.103
llvm/lib/Target/X86/X86TargetMachine.cpp:1.104
--- llvm/lib/Target/X86/X86TargetMachine.cpp:1.103 Thu Feb 16 18:03:04 2006
+++ llvm/lib/Target/X86/X86TargetMachine.cppFri Feb 17 19:49:25 2006
@@ -149,6 +149,9 @@
/// not supported for this target.
///
void X86JITInfo::addPassesToJITCompile(FunctionPassManager &PM) {
+ // The JIT does not support or need PIC.
+ PICEnabled = false;
+
// FIXME: Implement efficient support for garbage collection intrinsics.
PM.add(createLowerGCPass());
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[llvm-commits] CVS: llvm/utils/TableGen/DAGISelEmitter.cpp
Changes in directory llvm/utils/TableGen:
DAGISelEmitter.cpp updated: 1.172 -> 1.173
---
Log message:
Bump up pattern cost if the resulting instruction is marked
usesCustomDAGSchedInserter.
---
Diffs of the changes: (+14 -7)
DAGISelEmitter.cpp | 21 ++---
1 files changed, 14 insertions(+), 7 deletions(-)
Index: llvm/utils/TableGen/DAGISelEmitter.cpp
diff -u llvm/utils/TableGen/DAGISelEmitter.cpp:1.172
llvm/utils/TableGen/DAGISelEmitter.cpp:1.173
--- llvm/utils/TableGen/DAGISelEmitter.cpp:1.172Thu Feb 9 16:12:27 2006
+++ llvm/utils/TableGen/DAGISelEmitter.cpp Fri Feb 17 20:33:09 2006
@@ -1749,12 +1749,19 @@
/// getResultPatternCost - Compute the number of instructions for this pattern.
/// This is a temporary hack. We should really include the instruction
/// latencies in this calculation.
-static unsigned getResultPatternCost(TreePatternNode *P) {
+static unsigned getResultPatternCost(TreePatternNode *P, DAGISelEmitter &ISE) {
if (P->isLeaf()) return 0;
- unsigned Cost = P->getOperator()->isSubClassOf("Instruction");
+ unsigned Cost = 0;
+ Record *Op = P->getOperator();
+ if (Op->isSubClassOf("Instruction")) {
+Cost++;
+CodeGenInstruction &II = ISE.getTargetInfo().getInstruction(Op->getName());
+if (II.usesCustomDAGSchedInserter)
+ Cost += 10;
+ }
for (unsigned i = 0, e = P->getNumChildren(); i != e; ++i)
-Cost += getResultPatternCost(P->getChild(i));
+Cost += getResultPatternCost(P->getChild(i), ISE);
return Cost;
}
@@ -1773,8 +1780,8 @@
if (LHSSize < RHSSize) return false;
// If the patterns have equal complexity, compare generated instruction
cost
-return getResultPatternCost(LHS->getDstPattern()) <
- getResultPatternCost(RHS->getDstPattern());
+return getResultPatternCost(LHS->getDstPattern(), ISE) <
+ getResultPatternCost(RHS->getDstPattern(), ISE);
}
};
@@ -2748,7 +2755,7 @@
OS << "\n";
OS << std::string(Indent, ' ') << "// Pattern complexity = "
<< getPatternSize(Pattern.getSrcPattern(), *this) << " cost = "
- << getResultPatternCost(Pattern.getDstPattern()) << "\n";
+ << getResultPatternCost(Pattern.getDstPattern(), *this) << "\n";
}
if (!FirstCodeLine.first) {
OS << std::string(Indent, ' ') << "{\n";
@@ -2769,7 +2776,7 @@
OS << "\n";
OS << std::string(Indent, ' ') << "// Pattern complexity = "
<< getPatternSize(Pattern.getSrcPattern(), *this) << " cost = "
- << getResultPatternCost(Pattern.getDstPattern()) << "\n";
+ << getResultPatternCost(Pattern.getDstPattern(), *this) << "\n";
}
EmitPatterns(Other, Indent, OS);
return;
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[llvm-commits] CVS: llvm/lib/Target/X86/X86FloatingPoint.cpp X86InstrInfo.td
Changes in directory llvm/lib/Target/X86:
X86FloatingPoint.cpp updated: 1.49 -> 1.50
X86InstrInfo.td updated: 1.238 -> 1.239
---
Log message:
Added fisttp for fp to int conversion.
---
Diffs of the changes: (+29 -3)
X86FloatingPoint.cpp | 17 ++---
X86InstrInfo.td | 15 +++
2 files changed, 29 insertions(+), 3 deletions(-)
Index: llvm/lib/Target/X86/X86FloatingPoint.cpp
diff -u llvm/lib/Target/X86/X86FloatingPoint.cpp:1.49
llvm/lib/Target/X86/X86FloatingPoint.cpp:1.50
--- llvm/lib/Target/X86/X86FloatingPoint.cpp:1.49 Thu Jan 26 14:41:32 2006
+++ llvm/lib/Target/X86/X86FloatingPoint.cppFri Feb 17 20:36:28 2006
@@ -357,6 +357,9 @@
{ X86::FpIST16m , X86::FIST16m },
{ X86::FpIST32m , X86::FIST32m },
{ X86::FpIST64m , X86::FISTP64m },
+ { X86::FpISTT16m , X86::FISTTP16m},
+ { X86::FpISTT32m , X86::FISTTP32m},
+ { X86::FpISTT64m , X86::FISTTP64m},
{ X86::FpISUB16m , X86::FISUB16m },
{ X86::FpISUB32m , X86::FISUB32m },
{ X86::FpISUBR16m, X86::FISUBR16m},
@@ -502,12 +505,17 @@
unsigned Reg = getFPReg(MI->getOperand(MI->getNumOperands()-1));
bool KillsSrc = LV->KillsRegister(MI, X86::FP0+Reg);
- // FISTP64r is strange because there isn't a non-popping versions.
+ // FISTP64m is strange because there isn't a non-popping versions.
// If we have one _and_ we don't want to pop the operand, duplicate the value
// on the stack instead of moving it. This ensure that popping the value is
// always ok.
+ // Ditto FISTTP16m, FISTTP32m, FISTTP64m.
//
- if (MI->getOpcode() == X86::FpIST64m && !KillsSrc) {
+ if (!KillsSrc &&
+ (MI->getOpcode() == X86::FpIST64m ||
+ MI->getOpcode() == X86::FpISTT16m ||
+ MI->getOpcode() == X86::FpISTT32m ||
+ MI->getOpcode() == X86::FpISTT64m)) {
duplicateToTop(Reg, 7 /*temp register*/, I);
} else {
moveToTop(Reg, I);// Move to the top of the stack...
@@ -517,7 +525,10 @@
MI->RemoveOperand(MI->getNumOperands()-1);// Remove explicit ST(0)
operand
MI->setOpcode(getConcreteOpcode(MI->getOpcode()));
- if (MI->getOpcode() == X86::FISTP64m) {
+ if (MI->getOpcode() == X86::FISTP64m ||
+ MI->getOpcode() == X86::FISTTP16m ||
+ MI->getOpcode() == X86::FISTTP32m ||
+ MI->getOpcode() == X86::FISTTP64m) {
assert(StackTop > 0 && "Stack empty??");
--StackTop;
} else if (KillsSrc) { // Last use of operand?
Index: llvm/lib/Target/X86/X86InstrInfo.td
diff -u llvm/lib/Target/X86/X86InstrInfo.td:1.238
llvm/lib/Target/X86/X86InstrInfo.td:1.239
--- llvm/lib/Target/X86/X86InstrInfo.td:1.238 Fri Feb 17 18:15:05 2006
+++ llvm/lib/Target/X86/X86InstrInfo.td Fri Feb 17 20:36:28 2006
@@ -2957,6 +2957,21 @@
def FISTP32m : FPI<0xDB, MRM3m, (ops i32mem:$dst), "fistp{l} $dst">;
def FISTP64m : FPI<0xDF, MRM7m, (ops i64mem:$dst), "fistp{ll} $dst">;
+// FISTTP requires SSE3 even though it's a FPStack op.
+def FpISTT16m : FpI_<(ops i16mem:$op, RFP:$src), OneArgFP,
+[(X86fp_to_i16mem RFP:$src, addr:$op)]>,
+Requires<[HasSSE3]>;
+def FpISTT32m : FpI_<(ops i32mem:$op, RFP:$src), OneArgFP,
+[(X86fp_to_i32mem RFP:$src, addr:$op)]>,
+Requires<[HasSSE3]>;
+def FpISTT64m : FpI_<(ops i64mem:$op, RFP:$src), OneArgFP,
+[(X86fp_to_i64mem RFP:$src, addr:$op)]>,
+Requires<[HasSSE3]>;
+
+def FISTTP16m : FPI<0xDF, MRM1m, (ops i16mem:$dst), "fisttp{s} $dst">;
+def FISTTP32m : FPI<0xDB, MRM1m, (ops i32mem:$dst), "fisttp{l} $dst">;
+def FISTTP64m : FPI<0xDD, MRM1m, (ops i64mem:$dst), "fisttp{ll} $dst">;
+
// FP Stack manipulation instructions.
def FLDrr : FPI<0xC0, AddRegFrm, (ops RST:$op), "fld $op">, D9;
def FSTrr : FPI<0xD0, AddRegFrm, (ops RST:$op), "fst $op">, DD;
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[llvm-commits] CVS: llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp SelectionDAG.cpp
Changes in directory llvm/lib/CodeGen/SelectionDAG:
DAGCombiner.cpp updated: 1.107 -> 1.108
SelectionDAG.cpp updated: 1.258 -> 1.259
---
Log message:
Add checks to make sure we don't create bogus extend nodes, and fix a bug
where we were doing exactly that which was causing failures on x86 and
alpha.
---
Diffs of the changes: (+14 -4)
DAGCombiner.cpp | 14 ++
SelectionDAG.cpp |4
2 files changed, 14 insertions(+), 4 deletions(-)
Index: llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
diff -u llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp:1.107
llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp:1.108
--- llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp:1.107 Fri Feb 17 15:58:01 2006
+++ llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp Fri Feb 17 20:40:58 2006
@@ -665,6 +665,9 @@
// fold (A+(B-A)) -> B
if (N1.getOpcode() == ISD::SUB && N0 == N1.getOperand(1))
return N1.getOperand(0);
+ //
+ if (SimplifyDemandedBits(SDOperand(N, 0)))
+return SDOperand();
return SDOperand();
}
@@ -2297,13 +2300,16 @@
// Get a SetCC of the condition
// FIXME: Should probably make sure that setcc is legal if we ever have a
// target where it isn't.
-SDOperand Temp, SCC = DAG.getSetCC(TLI.getSetCCResultTy(), N0, N1, CC);
-WorkList.push_back(SCC.Val);
+SDOperand Temp, SCC;
// cast from setcc result type to select result type
-if (AfterLegalize)
+if (AfterLegalize) {
+ SCC = DAG.getSetCC(TLI.getSetCCResultTy(), N0, N1, CC);
Temp = DAG.getZeroExtendInReg(SCC, N2.getValueType());
-else
+} else {
+ SCC = DAG.getSetCC(MVT::i1, N0, N1, CC);
Temp = DAG.getNode(ISD::ZERO_EXTEND, N2.getValueType(), SCC);
+}
+WorkList.push_back(SCC.Val);
WorkList.push_back(Temp.Val);
// shl setcc result by log2 n2c
return DAG.getNode(ISD::SHL, N2.getValueType(), Temp,
Index: llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
diff -u llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp:1.258
llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp:1.259
--- llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp:1.258Fri Feb 17
15:58:01 2006
+++ llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp Fri Feb 17 20:40:58 2006
@@ -1047,22 +1047,26 @@
return Operand; // Factor of one node? No factor.
case ISD::SIGN_EXTEND:
if (Operand.getValueType() == VT) return Operand; // noop extension
+assert(Operand.getValueType() < VT && "Invalid sext node, dst < src!");
if (OpOpcode == ISD::SIGN_EXTEND || OpOpcode == ISD::ZERO_EXTEND)
return getNode(OpOpcode, VT, Operand.Val->getOperand(0));
break;
case ISD::ZERO_EXTEND:
if (Operand.getValueType() == VT) return Operand; // noop extension
+assert(Operand.getValueType() < VT && "Invalid zext node, dst < src!");
if (OpOpcode == ISD::ZERO_EXTEND) // (zext (zext x)) -> (zext x)
return getNode(ISD::ZERO_EXTEND, VT, Operand.Val->getOperand(0));
break;
case ISD::ANY_EXTEND:
if (Operand.getValueType() == VT) return Operand; // noop extension
+assert(Operand.getValueType() < VT && "Invalid anyext node, dst < src!");
if (OpOpcode == ISD::ZERO_EXTEND || OpOpcode == ISD::SIGN_EXTEND)
// (ext (zext x)) -> (zext x) and (ext (sext x)) -> (sext x)
return getNode(OpOpcode, VT, Operand.Val->getOperand(0));
break;
case ISD::TRUNCATE:
if (Operand.getValueType() == VT) return Operand; // noop truncate
+assert(Operand.getValueType() > VT && "Invalid truncate node, src < dst!");
if (OpOpcode == ISD::TRUNCATE)
return getNode(ISD::TRUNCATE, VT, Operand.Val->getOperand(0));
else if (OpOpcode == ISD::ZERO_EXTEND || OpOpcode == ISD::SIGN_EXTEND ||
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[llvm-commits] CVS: llvm/lib/Transforms/Scalar/LoopUnswitch.cpp
Changes in directory llvm/lib/Transforms/Scalar:
LoopUnswitch.cpp updated: 1.31 -> 1.32
---
Log message:
Implement deletion of dead blocks, currently disabled.
---
Diffs of the changes: (+75 -28)
LoopUnswitch.cpp | 103 ---
1 files changed, 75 insertions(+), 28 deletions(-)
Index: llvm/lib/Transforms/Scalar/LoopUnswitch.cpp
diff -u llvm/lib/Transforms/Scalar/LoopUnswitch.cpp:1.31
llvm/lib/Transforms/Scalar/LoopUnswitch.cpp:1.32
--- llvm/lib/Transforms/Scalar/LoopUnswitch.cpp:1.31Fri Feb 17 19:32:04 2006
+++ llvm/lib/Transforms/Scalar/LoopUnswitch.cpp Fri Feb 17 20:42:34 2006
@@ -82,8 +82,8 @@
BasicBlock *SplitBlock(BasicBlock *Old, Instruction *SplitPt);
void RewriteLoopBodyWithConditionConstant(Loop *L, Value *LIC,Constant
*Val,
bool isEqual);
-bool TryToRemoveEdge(TerminatorInst *TI, unsigned SuccNo,
- std::vector &Worklist);
+void RemoveBlockIfDead(BasicBlock *BB,
+ std::vector &Worklist);
};
RegisterOpt X("loop-unswitch", "Unswitch loops");
}
@@ -718,24 +718,68 @@
++NumSimplify;
}
-/// TryToRemoveEdge - Determine whether this is a case where we're smart enough
-/// to remove the specified edge from the CFG and know how to update loop
-/// information. If it is, update SSA and the loop information for the future
-/// change, then return true. If not, return false.
-bool LoopUnswitch::TryToRemoveEdge(TerminatorInst *TI, unsigned DeadSuccNo,
- std::vector &Worklist) {
- BasicBlock *BB = TI->getParent(), *Succ = TI->getSuccessor(DeadSuccNo);
- Loop *BBLoop = LI->getLoopFor(BB);
- Loop *SuccLoop = LI->getLoopFor(Succ);
-
- // If this edge is not in a loop, or if this edge is leaving a loop to a
- // non-loop area, this is trivial.
- if (SuccLoop == 0) {
-Succ->removePredecessor(BB, true);
-return true;
+/// RemoveBlockIfDead - If the specified block is dead, remove it, update loop
+/// information, and remove any dead successors it has.
+///
+void LoopUnswitch::RemoveBlockIfDead(BasicBlock *BB,
+ std::vector &Worklist) {
+ if (pred_begin(BB) != pred_end(BB)) return; // not dead.
+
+ DEBUG(std::cerr << "Nuking dead block: " << *BB);
+
+ // Remove the instructions in the basic block from the worklist.
+ for (BasicBlock::iterator I = BB->begin(), E = BB->end(); I != E; ++I)
+RemoveFromWorklist(I, Worklist);
+
+ // If this is the header block for a loop, remove the loop and all subloops.
+ // We leave all of the blocks that used to be part of this loop in the parent
+ // loop if any.
+ if (Loop *BBLoop = LI->getLoopFor(BB)) {
+if (BBLoop->getHeader() == BB) {
+ if (Loop *ParentLoop = BBLoop->getParentLoop()) { // not a top-level
loop.
+for (Loop::iterator I = ParentLoop->begin(), E = ParentLoop->end();;
+ ++I) {
+ assert(I != E && "Couldn't find loop");
+ if (*I == BBLoop) {
+ParentLoop->removeChildLoop(I);
+break;
+ }
+}
+ } else {
+for (LoopInfo::iterator I = LI->begin(), E = LI->end();; ++I) {
+ assert(I != E && "Couldn't find loop");
+ if (*I == BBLoop) {
+LI->removeLoop(I);
+break;
+ }
+}
+ }
+ delete BBLoop;
+}
}
+
+ // Remove the block from the loop info, which removes it from any loops it
+ // was in.
+ LI->removeBlock(BB);
- return false;
+
+ // Remove phi node entries in successors for this block.
+ TerminatorInst *TI = BB->getTerminator();
+ std::vector Succs;
+ for (unsigned i = 0, e = TI->getNumSuccessors(); i != e; ++i) {
+Succs.push_back(TI->getSuccessor(i));
+TI->getSuccessor(i)->removePredecessor(BB);
+ }
+
+ // Unique the successors.
+ std::sort(Succs.begin(), Succs.end());
+ Succs.erase(std::unique(Succs.begin(), Succs.end()), Succs.end());
+
+ // Remove the basic block, including all of the instructions contained in it.
+ BB->eraseFromParent();
+
+ for (unsigned i = 0, e = Succs.size(); i != e; ++i)
+RemoveBlockIfDead(Succs[i], Worklist);
}
// RewriteLoopBodyWithConditionConstant - We know either that the value LIC has
@@ -895,17 +939,20 @@
LI->removeBlock(Succ);
Succ->eraseFromParent();
++NumSimplify;
-break;
} else if (ConstantBool *CB =
dyn_cast(BI->getCondition())){
-// Conditional branch.
-if (TryToRemoveEdge(BI, CB->getValue(), Worklist)) {
- DEBUG(std::cerr << "Folded branch: " << *BI);
- new BranchInst(BI->getSuccessor(!CB->getValue()), BI);
- BI->eraseFromParent();
- RemoveFromWorklist(BI, Worklist);
- ++NumSimplify;
- break;
-}
+break;// FIXME: disabled
+// Conditional branch. Turn it into an unconditional branch, then
+
[llvm-commits] CVS: llvm/lib/Target/TargetLowering.cpp
Changes in directory llvm/lib/Target:
TargetLowering.cpp updated: 1.32 -> 1.33
---
Log message:
Add a fold for add that exchanges it with a constant shift if possible, so
that the shift may be more easily folded into other operations.
---
Diffs of the changes: (+24 -6)
TargetLowering.cpp | 30 --
1 files changed, 24 insertions(+), 6 deletions(-)
Index: llvm/lib/Target/TargetLowering.cpp
diff -u llvm/lib/Target/TargetLowering.cpp:1.32
llvm/lib/Target/TargetLowering.cpp:1.33
--- llvm/lib/Target/TargetLowering.cpp:1.32 Thu Feb 16 20:12:18 2006
+++ llvm/lib/Target/TargetLowering.cpp Fri Feb 17 20:43:25 2006
@@ -459,6 +459,24 @@
CountTrailingZeros_64(~KnownZero2));
KnownZero = (1ULL << KnownZeroOut) - 1;
KnownOne = 0;
+
+ SDOperand SH = Op.getOperand(0);
+ // fold (add (shl x, c1), (shl c2, c1)) -> (shl (add x, c2), c1)
+ if (KnownZero && SH.getOpcode() == ISD::SHL && SH.Val->hasOneUse() &&
+ Op.Val->hasOneUse()) {
+if (ConstantSDNode *SA = dyn_cast(SH.getOperand(1))) {
+ MVT::ValueType VT = Op.getValueType();
+ unsigned ShiftAmt = SA->getValue();
+ uint64_t AddAmt = AA->getValue();
+ uint64_t AddShr = AddAmt >> ShiftAmt;
+ if (AddAmt == (AddShr << ShiftAmt)) {
+SDOperand ADD = TLO.DAG.getNode(ISD::ADD, VT, SH.getOperand(0),
+TLO.DAG.getConstant(AddShr, VT));
+SDOperand SHL = TLO.DAG.getNode(ISD::SHL, VT,
ADD,SH.getOperand(1));
+return TLO.CombineTo(Op, SHL);
+ }
+}
+ }
}
break;
case ISD::CTTZ:
@@ -577,7 +595,7 @@
KnownOne <<= SA->getValue();
KnownZero |= (1ULL << SA->getValue())-1; // low bits known zero.
}
-break;
+return;
case ISD::SRL:
// (ushr X, C1) & C2 == 0 iff (-1 >> C1) & C2 == 0
if (ConstantSDNode *SA = dyn_cast(Op.getOperand(1))) {
@@ -585,12 +603,12 @@
HighBits <<= MVT::getSizeInBits(Op.getValueType())-SA->getValue();
Mask <<= SA->getValue();
ComputeMaskedBits(Op.getOperand(0), Mask, KnownZero, KnownOne, Depth+1);
- assert((KnownZero & KnownOne) == 0&&"Bits known to be one AND zero?");
+ assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
KnownZero >>= SA->getValue();
KnownOne >>= SA->getValue();
KnownZero |= HighBits; // high bits known zero.
}
-break;
+return;
case ISD::SRA:
if (ConstantSDNode *SA = dyn_cast(Op.getOperand(1))) {
uint64_t HighBits = (1ULL << SA->getValue())-1;
@@ -611,7 +629,7 @@
KnownOne |= HighBits;
}
}
-break;
+return;
case ISD::CTTZ:
case ISD::CTLZ:
case ISD::CTPOP: {
@@ -666,12 +684,12 @@
// We know that the top bits of C-X are clear if X contains less bits
// than C (i.e. no wrap-around can happen). For example, 20-X is
// positive if we can prove that X is >= 0 and < 16.
-break;
+return;
default:
// Allow the target to implement this method for its nodes.
if (Op.getOpcode() >= ISD::BUILTIN_OP_END)
computeMaskedBitsForTargetNode(Op, Mask, KnownZero, KnownOne);
-break;
+return;
}
}
___
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[llvm-commits] CVS: llvm/utils/TableGen/Record.cpp
Changes in directory llvm/utils/TableGen:
Record.cpp updated: 1.50 -> 1.51
---
Log message:
Fix bugs identified by VC++.
---
Diffs of the changes: (+2 -2)
Record.cpp |4 ++--
1 files changed, 2 insertions(+), 2 deletions(-)
Index: llvm/utils/TableGen/Record.cpp
diff -u llvm/utils/TableGen/Record.cpp:1.50 llvm/utils/TableGen/Record.cpp:1.51
--- llvm/utils/TableGen/Record.cpp:1.50 Tue Jan 31 00:02:35 2006
+++ llvm/utils/TableGen/Record.cpp Fri Feb 17 21:20:33 2006
@@ -69,13 +69,13 @@
if (Value & ~((1LL << Size)-1))
return 0;
} else {
-if ((Value >> Size) != -1 || ((Value & (1 << (Size-1))) == 0))
+if ((Value >> Size) != -1 || ((Value & (1LL << (Size-1))) == 0))
return 0;
}
BitsInit *Ret = new BitsInit(Size);
for (unsigned i = 0; i != Size; ++i)
-Ret->setBit(i, new BitInit(Value & (1 << i)));
+Ret->setBit(i, new BitInit(Value & (1LL << i)));
return Ret;
}
___
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[llvm-commits] CVS: llvm/lib/Transforms/Scalar/InstructionCombining.cpp
Changes in directory llvm/lib/Transforms/Scalar: InstructionCombining.cpp updated: 1.436 -> 1.437 --- Log message: Fix bugs identified by VC++. --- Diffs of the changes: (+2 -2) InstructionCombining.cpp |4 ++-- 1 files changed, 2 insertions(+), 2 deletions(-) Index: llvm/lib/Transforms/Scalar/InstructionCombining.cpp diff -u llvm/lib/Transforms/Scalar/InstructionCombining.cpp:1.436 llvm/lib/Transforms/Scalar/InstructionCombining.cpp:1.437 --- llvm/lib/Transforms/Scalar/InstructionCombining.cpp:1.436 Thu Feb 16 15:11:51 2006 +++ llvm/lib/Transforms/Scalar/InstructionCombining.cpp Fri Feb 17 21:20:33 2006 @@ -757,9 +757,9 @@ // If all of the demanded bits are known zero on one side, return the other. // These bits cannot contribute to the result of the 'or'. -if ((DemandedMask & ~KnownOne2 & KnownZero) == DemandedMask & ~KnownOne2) +if ((DemandedMask & ~KnownOne2 & KnownZero) == (DemandedMask & ~KnownOne2)) return UpdateValueUsesWith(I, I->getOperand(0)); -if ((DemandedMask & ~KnownOne & KnownZero2) == DemandedMask & ~KnownOne) +if ((DemandedMask & ~KnownOne & KnownZero2) == (DemandedMask & ~KnownOne)) return UpdateValueUsesWith(I, I->getOperand(1)); // If all of the potentially set bits on one side are known to be set on ___ llvm-commits mailing list llvm-commits@cs.uiuc.edu http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
[llvm-commits] CVS: llvm/lib/Target/X86/X86ISelLowering.cpp
Changes in directory llvm/lib/Target/X86: X86ISelLowering.cpp updated: 1.89 -> 1.90 --- Log message: If SSE3 is available, promote FP_TO_UINT i32 to FP_TO_SINT i64 to take advantage of fisttpll. --- Diffs of the changes: (+2 -1) X86ISelLowering.cpp |3 ++- 1 files changed, 2 insertions(+), 1 deletion(-) Index: llvm/lib/Target/X86/X86ISelLowering.cpp diff -u llvm/lib/Target/X86/X86ISelLowering.cpp:1.89 llvm/lib/Target/X86/X86ISelLowering.cpp:1.90 --- llvm/lib/Target/X86/X86ISelLowering.cpp:1.89Fri Feb 17 18:15:05 2006 +++ llvm/lib/Target/X86/X86ISelLowering.cpp Sat Feb 18 01:26:17 2006 @@ -101,12 +101,13 @@ setOperationAction(ISD::FP_TO_UINT , MVT::i8 , Promote); setOperationAction(ISD::FP_TO_UINT , MVT::i16 , Promote); - if (X86ScalarSSE) + if (X86ScalarSSE && !Subtarget->hasSSE3()) // Expand FP_TO_UINT into a select. // FIXME: We would like to use a Custom expander here eventually to do // the optimal thing for SSE vs. the default expansion in the legalizer. setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Expand); else +// With SSE3 we can use fisttpll to convert to a signed i64. setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Promote); setOperationAction(ISD::BIT_CONVERT , MVT::f32 , Expand); ___ llvm-commits mailing list llvm-commits@cs.uiuc.edu http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
[llvm-commits] CVS: llvm/lib/Transforms/Scalar/LoopUnswitch.cpp
Changes in directory llvm/lib/Transforms/Scalar:
LoopUnswitch.cpp updated: 1.32 -> 1.33
---
Log message:
improved support for branch folding, still not enabled.
---
Diffs of the changes: (+269 -143)
LoopUnswitch.cpp | 412 +++
1 files changed, 269 insertions(+), 143 deletions(-)
Index: llvm/lib/Transforms/Scalar/LoopUnswitch.cpp
diff -u llvm/lib/Transforms/Scalar/LoopUnswitch.cpp:1.32
llvm/lib/Transforms/Scalar/LoopUnswitch.cpp:1.33
--- llvm/lib/Transforms/Scalar/LoopUnswitch.cpp:1.32Fri Feb 17 20:42:34 2006
+++ llvm/lib/Transforms/Scalar/LoopUnswitch.cpp Sat Feb 18 01:57:38 2006
@@ -36,6 +36,7 @@
#include "llvm/Transforms/Utils/Local.h"
#include "llvm/Transforms/Utils/BasicBlockUtils.h"
#include "llvm/ADT/Statistic.h"
+#include "llvm/ADT/PostOrderIterator.h"
#include "llvm/Support/Debug.h"
#include "llvm/Support/CommandLine.h"
#include
@@ -57,6 +58,9 @@
class LoopUnswitch : public FunctionPass {
LoopInfo *LI; // Loop information
+
+// LoopProcessWorklist - List of loops we need to process.
+std::vector LoopProcessWorklist;
public:
virtual bool runOnFunction(Function &F);
bool visitLoop(Loop *L);
@@ -72,18 +76,30 @@
}
private:
+/// RemoveLoopFromWorklist - If the specified loop is on the loop worklist,
+/// remove it.
+void RemoveLoopFromWorklist(Loop *L) {
+ std::vector::iterator I = std::find(LoopProcessWorklist.begin(),
+ LoopProcessWorklist.end(), L);
+ if (I != LoopProcessWorklist.end())
+LoopProcessWorklist.erase(I);
+}
+
bool UnswitchIfProfitable(Value *LoopCond, Constant *Val,Loop *L);
unsigned getLoopUnswitchCost(Loop *L, Value *LIC);
-void VersionLoop(Value *LIC, Constant *OnVal,
- Loop *L, Loop *&Out1, Loop *&Out2);
void UnswitchTrivialCondition(Loop *L, Value *Cond, Constant *Val,
bool EntersWhenTrue, BasicBlock *ExitBlock);
+void UnswitchNontrivialCondition(Value *LIC, Constant *OnVal, Loop *L);
BasicBlock *SplitEdge(BasicBlock *From, BasicBlock *To);
BasicBlock *SplitBlock(BasicBlock *Old, Instruction *SplitPt);
-void RewriteLoopBodyWithConditionConstant(Loop *L, Value *LIC,Constant
*Val,
- bool isEqual);
+
+void RewriteLoopBodyWithConditionConstant(Loop *L, Value *LIC,
+ Constant *Val, bool isEqual);
+
+void SimplifyCode(std::vector &Worklist);
void RemoveBlockIfDead(BasicBlock *BB,
std::vector &Worklist);
+void RemoveLoopFromHierarchy(Loop *L);
};
RegisterOpt X("loop-unswitch", "Unswitch loops");
}
@@ -94,12 +110,95 @@
bool Changed = false;
LI = &getAnalysis();
- // Transform all the top-level loops. Copy the loop list so that the child
- // can update the loop tree if it needs to delete the loop.
- std::vector SubLoops(LI->begin(), LI->end());
- for (unsigned i = 0, e = SubLoops.size(); i != e; ++i)
-Changed |= visitLoop(SubLoops[i]);
+ // Populate the worklist of loops to process in post-order.
+ for (LoopInfo::iterator I = LI->begin(), E = LI->end(); I != E; ++I)
+for (po_iterator LI = po_begin(*I), E = po_end(*I); LI != E; ++LI)
+ LoopProcessWorklist.push_back(*LI);
+
+ // Process the loops in worklist order, this is a post-order visitation of
+ // the loops. We use a worklist of loops so that loops can be removed at any
+ // time if they are deleted (e.g. the backedge of a loop is removed).
+ while (!LoopProcessWorklist.empty()) {
+Loop *L = LoopProcessWorklist.back();
+LoopProcessWorklist.pop_back();
+Changed |= visitLoop(L);
+ }
+
+ return Changed;
+}
+/// FindLIVLoopCondition - Cond is a condition that occurs in L. If it is
+/// invariant in the loop, or has an invariant piece, return the invariant.
+/// Otherwise, return null.
+static Value *FindLIVLoopCondition(Value *Cond, Loop *L, bool &Changed) {
+ // Constants should be folded, not unswitched on!
+ if (isa(Cond)) return false;
+
+ // TODO: Handle: br (VARIANT|INVARIANT).
+ // TODO: Hoist simple expressions out of loops.
+ if (L->isLoopInvariant(Cond)) return Cond;
+
+ if (BinaryOperator *BO = dyn_cast(Cond))
+if (BO->getOpcode() == Instruction::And ||
+BO->getOpcode() == Instruction::Or) {
+ // If either the left or right side is invariant, we can unswitch on
this,
+ // which will cause the branch to go away in one loop and the condition
to
+ // simplify in the other one.
+ if (Value *LHS = FindLIVLoopCondition(BO->getOperand(0), L, Changed))
+return LHS;
+ if (Value *RHS = FindLIVLoopCondition(BO->getOperand(1), L, Changed))
+return RHS;
+}
+
+ return 0;
+}
+
+bool LoopUnswitch::visitLoop(Loop *L) {
+ bool Changed = false;
+
+ // Loop over all of the b
