[llvm-commits] Re: llvm-commits Digest, Vol 18, Issue 8
> Message: 1
> Date: Wed, 7 Dec 2005 12:02:16 -0600
> From: "Chris Lattner" <[EMAIL PROTECTED]>
> Subject: [llvm-commits] CVS:
> llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
> To: llvm-commits@cs.uiuc.edu
> Message-ID: <[EMAIL PROTECTED]>
> Changes in directory llvm/lib/CodeGen/SelectionDAG:
>
> DAGCombiner.cpp updated: 1.63 -> 1.64
> ---
> Log message:
>
> Only transform (sext (truncate x)) -> (sextinreg x) if before legalize or
> if the target supports the resultant sextinreg
I think it is this change that breaks thing. This leads to i32 =
sign_extend_inreg hitting promoteOp, which cannot deal with it.
reduction for alpha:
;ModuleID = 'bugpoint-reduced-simplified.bc'
target endian = little
target pointersize = 64
%id.0__ = external global ushort
implementation ; Functions:
fastcc void %dxi_send() {
entry:
%tmp.233 = load ushort* %id.0__
%tmp.234 = cast ushort %tmp.233 to int
%tmp.235 = load short* null
%tmp.236 = cast short %tmp.235 to ushort
%tmp.244 = cast ushort %tmp.236 to int
%tmp.245 = shl int %tmp.244, ubyte 8
%tmp.247 = and int %tmp.245, 65280
%tmp.248 = or int 0, %tmp.247
%tmp.249 = cast int %tmp.248 to short
%tmp.250 = cast short %tmp.249 to int
%tmp.251 = seteq int %tmp.234, %tmp.250
br bool %tmp.251, label %endif.20, label %then.20
then.20:; preds = %entry
ret void
endif.20: ; preds = %entry
call void %llvm.memcpy( sbyte* null, sbyte* null, ulong 8, uint
1 )
unreachable
}
declare void %llvm.memcpy(sbyte*, sbyte*, ulong, uint)
>
> ---
> Diffs of the changes: (+3 -1)
>
> DAGCombiner.cpp |4 +++-
> 1 files changed, 3 insertions(+), 1 deletion(-)
>
>
> Index: llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
> diff -u llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp:1.63
> llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp:1.64
> --- llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp:1.63Wed Dec 7
> 01:11:03 2005
> +++ llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp Wed Dec 7 12:02:05 2005
> @@ -1547,7 +1547,9 @@
>if (N0.getOpcode() == ISD::SEXTLOAD && VT == N0.getValueType())
> return N0;
>// fold (sext (truncate x)) -> (sextinreg x) iff x size == sext size.
> - if (N0.getOpcode() == ISD::TRUNCATE && N0.getOperand(0).getValueType() ==
> VT)
> + if (N0.getOpcode() == ISD::TRUNCATE && N0.getOperand(0).getValueType() ==
> VT&&
> + (!AfterLegalize ||
> + TLI.isOperationLegal(ISD::SIGN_EXTEND_INREG, N0.getValueType(
> return DAG.getNode(ISD::SIGN_EXTEND_INREG, VT, N0.getOperand(0),
> DAG.getValueType(N0.getValueType()));
>// fold (sext (load x)) -> (sextload x)
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Re: [llvm-commits] Re: llvm-commits Digest, Vol 18, Issue 8
I think it is this change that breaks thing. This leads to i32 =
sign_extend_inreg hitting promoteOp, which cannot deal with it.
Fixed, thanks.
-Chris
Message: 1
Date: Wed, 7 Dec 2005 12:02:16 -0600
From: "Chris Lattner" <[EMAIL PROTECTED]>
Subject: [llvm-commits] CVS:
llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
To: llvm-commits@cs.uiuc.edu
Message-ID: <[EMAIL PROTECTED]>
Changes in directory llvm/lib/CodeGen/SelectionDAG:
DAGCombiner.cpp updated: 1.63 -> 1.64
---
Log message:
Only transform (sext (truncate x)) -> (sextinreg x) if before legalize or
if the target supports the resultant sextinreg
reduction for alpha:
;ModuleID = 'bugpoint-reduced-simplified.bc'
target endian = little
target pointersize = 64
%id.0__ = external global ushort
implementation ; Functions:
fastcc void %dxi_send() {
entry:
%tmp.233 = load ushort* %id.0__
%tmp.234 = cast ushort %tmp.233 to int
%tmp.235 = load short* null
%tmp.236 = cast short %tmp.235 to ushort
%tmp.244 = cast ushort %tmp.236 to int
%tmp.245 = shl int %tmp.244, ubyte 8
%tmp.247 = and int %tmp.245, 65280
%tmp.248 = or int 0, %tmp.247
%tmp.249 = cast int %tmp.248 to short
%tmp.250 = cast short %tmp.249 to int
%tmp.251 = seteq int %tmp.234, %tmp.250
br bool %tmp.251, label %endif.20, label %then.20
then.20:; preds = %entry
ret void
endif.20: ; preds = %entry
call void %llvm.memcpy( sbyte* null, sbyte* null, ulong 8, uint
1 )
unreachable
}
declare void %llvm.memcpy(sbyte*, sbyte*, ulong, uint)
---
Diffs of the changes: (+3 -1)
DAGCombiner.cpp |4 +++-
1 files changed, 3 insertions(+), 1 deletion(-)
Index: llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
diff -u llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp:1.63
llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp:1.64
--- llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp:1.63 Wed Dec 7 01:11:03 2005
+++ llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp Wed Dec 7 12:02:05 2005
@@ -1547,7 +1547,9 @@
if (N0.getOpcode() == ISD::SEXTLOAD && VT == N0.getValueType())
return N0;
// fold (sext (truncate x)) -> (sextinreg x) iff x size == sext size.
- if (N0.getOpcode() == ISD::TRUNCATE && N0.getOperand(0).getValueType() == VT)
+ if (N0.getOpcode() == ISD::TRUNCATE && N0.getOperand(0).getValueType() ==
VT&&
+ (!AfterLegalize ||
+ TLI.isOperationLegal(ISD::SIGN_EXTEND_INREG, N0.getValueType(
return DAG.getNode(ISD::SIGN_EXTEND_INREG, VT, N0.getOperand(0),
DAG.getValueType(N0.getValueType()));
// fold (sext (load x)) -> (sextload x)
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-Chris
--
http://nondot.org/sabre/
http://llvm.org/
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[llvm-commits] CVS: llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
Changes in directory llvm/lib/CodeGen/SelectionDAG:
LegalizeDAG.cpp updated: 1.224 -> 1.225
---
Log message:
Teach legalize how to promote sext_inreg to fix a problem Andrew pointed
out to me.
---
Diffs of the changes: (+5 -0)
LegalizeDAG.cpp |5 +
1 files changed, 5 insertions(+)
Index: llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
diff -u llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp:1.224
llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp:1.225
--- llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp:1.224 Wed Dec 7 13:48:11 2005
+++ llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp Fri Dec 9 11:32:47 2005
@@ -2404,6 +2404,11 @@
}
break;
+ case ISD::SIGN_EXTEND_INREG:
+Result = PromoteOp(Node->getOperand(0));
+Result = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Result,
+ Node->getOperand(1));
+break;
case ISD::FP_TO_SINT:
case ISD::FP_TO_UINT:
switch (getTypeAction(Node->getOperand(0).getValueType())) {
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[llvm-commits] CVS: llvm/lib/Target/PowerPC/PPCAsmPrinter.cpp
Changes in directory llvm/lib/Target/PowerPC:
PPCAsmPrinter.cpp updated: 1.122 -> 1.123
---
Log message:
Teach the PPC backend about the ctor and dtor list when not using __main and
linking the entire program into one bc file.
---
Diffs of the changes: (+34 -0)
PPCAsmPrinter.cpp | 34 ++
1 files changed, 34 insertions(+)
Index: llvm/lib/Target/PowerPC/PPCAsmPrinter.cpp
diff -u llvm/lib/Target/PowerPC/PPCAsmPrinter.cpp:1.122
llvm/lib/Target/PowerPC/PPCAsmPrinter.cpp:1.123
--- llvm/lib/Target/PowerPC/PPCAsmPrinter.cpp:1.122 Wed Nov 30 12:54:35 2005
+++ llvm/lib/Target/PowerPC/PPCAsmPrinter.cpp Fri Dec 9 12:24:29 2005
@@ -202,6 +202,8 @@
virtual const char *getPassName() const {
return "Darwin PPC Assembly Printer";
}
+
+void EmitXXStructorList(Constant *List);
bool runOnMachineFunction(MachineFunction &F);
bool doInitialization(Module &M);
@@ -412,6 +414,21 @@
return false;
}
+/// EmitXXStructorList - Emit the ctor or dtor list. On darwin, this just
+/// prints out the function pointers.
+void DarwinAsmPrinter::EmitXXStructorList(Constant *List) {
+ // Should be an array of '{ int, void ()* }' structs. The first value is the
+ // init priority, which we ignore.
+ if (!isa(List)) return;
+ ConstantArray *InitList = cast(List);
+ for (unsigned i = 0, e = InitList->getNumOperands(); i != e; ++i)
+if (ConstantStruct *CS =
dyn_cast(InitList->getOperand(i))){
+ if (CS->getNumOperands() != 2) return; // Not array of 2-element
structs.
+ // Emit the function pointer.
+ EmitGlobalConstant(CS->getOperand(1));
+}
+}
+
bool DarwinAsmPrinter::doFinalization(Module &M) {
const TargetData &TD = TM.getTargetData();
@@ -419,6 +436,23 @@
for (Module::const_global_iterator I = M.global_begin(), E = M.global_end();
I != E; ++I)
if (I->hasInitializer()) { // External global require no code
+ // Check to see if this is a special global used by LLVM.
+ if (I->hasAppendingLinkage()) {
+if (I->getName() == "llvm.used")
+ continue; // No need to emit this at all.
+if (I->getName() == "llvm.global_ctors") {
+ SwitchSection(".mod_init_func", 0);
+ EmitAlignment(2, 0);
+ EmitXXStructorList(I->getInitializer());
+ continue;
+} else if (I->getName() == "llvm.global_dtors") {
+ SwitchSection(".mod_term_func", 0);
+ EmitAlignment(2, 0);
+ EmitXXStructorList(I->getInitializer());
+ continue;
+}
+ }
+
O << '\n';
std::string name = Mang->getValueName(I);
Constant *C = I->getInitializer();
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[llvm-commits] CVS: llvm/lib/CodeGen/AsmPrinter.cpp
Changes in directory llvm/lib/CodeGen:
AsmPrinter.cpp updated: 1.30 -> 1.31
---
Log message:
Avoid emitting two tabs when switching to a named section
---
Diffs of the changes: (+2 -2)
AsmPrinter.cpp |4 ++--
1 files changed, 2 insertions(+), 2 deletions(-)
Index: llvm/lib/CodeGen/AsmPrinter.cpp
diff -u llvm/lib/CodeGen/AsmPrinter.cpp:1.30
llvm/lib/CodeGen/AsmPrinter.cpp:1.31
--- llvm/lib/CodeGen/AsmPrinter.cpp:1.30Tue Dec 6 00:18:55 2005
+++ llvm/lib/CodeGen/AsmPrinter.cpp Fri Dec 9 13:28:49 2005
@@ -30,12 +30,12 @@
if (GV && GV->hasSection())
NS = SwitchToSectionDirective + GV->getSection();
else
-NS = NewSection;
+NS = std::string("\t")+NewSection;
if (CurrentSection != NS) {
CurrentSection = NS;
if (!CurrentSection.empty())
- O << "\t" << CurrentSection << "\n";
+ O << CurrentSection << '\n';
}
}
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[llvm-commits] CVS: llvm/utils/TableGen/DAGISelEmitter.cpp DAGISelEmitter.h
Changes in directory llvm/utils/TableGen:
DAGISelEmitter.cpp updated: 1.89 -> 1.90
DAGISelEmitter.h updated: 1.42 -> 1.43
---
Log message:
* Do not allow nodes which produce chain results (e.g. loads) to be folded if
it has more than one real use (non-chain uses).
* Record folded chain producing node in CodeGenMap.
* Do not fold a chain producing node if it has already been selected as an
operand of a chain use.
---
Diffs of the changes: (+421 -427)
DAGISelEmitter.cpp | 835 ++---
DAGISelEmitter.h | 13
2 files changed, 421 insertions(+), 427 deletions(-)
Index: llvm/utils/TableGen/DAGISelEmitter.cpp
diff -u llvm/utils/TableGen/DAGISelEmitter.cpp:1.89
llvm/utils/TableGen/DAGISelEmitter.cpp:1.90
--- llvm/utils/TableGen/DAGISelEmitter.cpp:1.89 Fri Dec 9 00:06:08 2005
+++ llvm/utils/TableGen/DAGISelEmitter.cpp Fri Dec 9 16:45:35 2005
@@ -1686,446 +1686,458 @@
}
};
-/// EmitMatchForPattern - Emit a matcher for N, going to the label for
PatternNo
-/// if the match fails. At this point, we already know that the opcode for N
-/// matches, and the SDNode for the result has the RootName specified name.
-void DAGISelEmitter::EmitMatchForPattern(TreePatternNode *N,
- const std::string &RootName,
- std::map
&VarMap,
- unsigned PatternNo,
- std::ostream &OS,
- std::string &ChainName,
- bool &HasChain, bool &InFlag,
- bool isRoot) {
- if (N->isLeaf()) {
-if (IntInit *II = dynamic_cast(N->getLeafValue())) {
- OS << " if (cast(" << RootName
- << ")->getSignExtended() != " << II->getValue() << ")\n"
- << "goto P" << PatternNo << "Fail;\n";
- return;
-} else if (!NodeIsComplexPattern(N)) {
- assert(0 && "Cannot match this as a leaf value!");
- abort();
+/// getRegisterValueType - Look up and return the first ValueType of specified
+/// RegisterClass record
+static MVT::ValueType getRegisterValueType(Record *R, const CodeGenTarget &T) {
+ if (const CodeGenRegisterClass *RC = T.getRegisterClassForRegister(R))
+return RC->getValueTypeNum(0);
+ return MVT::Other;
+}
+
+
+/// RemoveAllTypes - A quick recursive walk over a pattern which removes all
+/// type information from it.
+static void RemoveAllTypes(TreePatternNode *N) {
+ N->setType(MVT::isUnknown);
+ if (!N->isLeaf())
+for (unsigned i = 0, e = N->getNumChildren(); i != e; ++i)
+ RemoveAllTypes(N->getChild(i));
+}
+
+Record *DAGISelEmitter::getSDNodeNamed(const std::string &Name) const {
+ Record *N = Records.getDef(Name);
+ assert(N && N->isSubClassOf("SDNode") && "Bad argument");
+ return N;
+}
+
+class PatternCodeEmitter {
+private:
+ DAGISelEmitter &ISE;
+
+ // LHS of the pattern being matched
+ TreePatternNode *LHS;
+ unsigned PatternNo;
+ std::ostream &OS;
+ // Node to name mapping
+ std::map VariableMap;
+ // Name of the inner most node which produces a chain.
+ std::string InnerChain;
+ // Names of all the folded nodes which produce chains.
+ std::vector FoldedChains;
+ bool InFlag;
+ unsigned TmpNo;
+
+public:
+ PatternCodeEmitter(DAGISelEmitter &ise, TreePatternNode *lhs,
+ unsigned PatNum, std::ostream &os) :
+ISE(ise), LHS(lhs), PatternNo(PatNum), OS(os),
+InFlag(false), TmpNo(0) {};
+
+ /// EmitMatchCode - Emit a matcher for N, going to the label for PatternNo
+ /// if the match fails. At this point, we already know that the opcode for N
+ /// matches, and the SDNode for the result has the RootName specified name.
+ void EmitMatchCode(TreePatternNode *N, const std::string &RootName,
+ bool isRoot = false) {
+if (N->isLeaf()) {
+ if (IntInit *II = dynamic_cast(N->getLeafValue())) {
+OS << " if (cast(" << RootName
+ << ")->getSignExtended() != " << II->getValue() << ")\n"
+ << "goto P" << PatternNo << "Fail;\n";
+return;
+ } else if (!NodeIsComplexPattern(N)) {
+assert(0 && "Cannot match this as a leaf value!");
+abort();
+ }
}
- }
- // If this node has a name associated with it, capture it in VarMap. If
- // we already saw this in the pattern, emit code to verify dagness.
- if (!N->getName().empty()) {
-std::string &VarMapEntry = VarMap[N->getName()];
-if (VarMapEntry.empty()) {
- VarMapEntry = RootName;
-} else {
- // If we get here, this is a second reference to a specific name. Since
- // we already have checked that the first reference is valid, we don't
- // have to recursively match it, just check that it's the same as the
- // previously named thing.
- OS << " if (" << VarMapEntry << " != " << RootName
-
[llvm-commits] CVS: llvm/lib/Target/X86/X86InstrInfo.td
Changes in directory llvm/lib/Target/X86:
X86InstrInfo.td updated: 1.150 -> 1.151
---
Log message:
Added patterns for ADD8rm, etc. These fold load operands. e.g. addb 4(%esp), %al
---
Diffs of the changes: (+6 -3)
X86InstrInfo.td |9 ++---
1 files changed, 6 insertions(+), 3 deletions(-)
Index: llvm/lib/Target/X86/X86InstrInfo.td
diff -u llvm/lib/Target/X86/X86InstrInfo.td:1.150
llvm/lib/Target/X86/X86InstrInfo.td:1.151
--- llvm/lib/Target/X86/X86InstrInfo.td:1.150 Wed Dec 7 20:15:07 2005
+++ llvm/lib/Target/X86/X86InstrInfo.td Fri Dec 9 16:48:48 2005
@@ -1165,11 +1165,14 @@
} // end isConvertibleToThreeAddress
} // end isCommutable
def ADD8rm : I<0x02, MRMSrcMem, (ops R8 :$dst, R8 :$src1, i8mem :$src2),
- "add{b} {$src2, $dst|$dst, $src2}", []>;
+ "add{b} {$src2, $dst|$dst, $src2}",
+ [(set R8:$dst, (add R8:$src1, (load addr:$src2)))]>;
def ADD16rm : I<0x03, MRMSrcMem, (ops R16:$dst, R16:$src1, i16mem:$src2),
- "add{w} {$src2, $dst|$dst, $src2}", []>, OpSize;
+ "add{w} {$src2, $dst|$dst, $src2}",
+ [(set R16:$dst, (add R16:$src1, (load addr:$src2)))]>, OpSize;
def ADD32rm : I<0x03, MRMSrcMem, (ops R32:$dst, R32:$src1, i32mem:$src2),
- "add{l} {$src2, $dst|$dst, $src2}", []>;
+ "add{l} {$src2, $dst|$dst, $src2}",
+ [(set R32:$dst, (add R32:$src1, (load addr:$src2)))]>;
def ADD8ri : Ii8<0x80, MRM0r, (ops R8:$dst, R8:$src1, i8imm:$src2),
"add{b} {$src2, $dst|$dst, $src2}",
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[llvm-commits] CVS: llvm/include/llvm/CodeGen/SelectionDAG.h
Changes in directory llvm/include/llvm/CodeGen:
SelectionDAG.h updated: 1.76 -> 1.77
---
Log message:
Added patterns for ADD8rm, etc. These fold load operands. e.g. addb 4(%esp), %al
---
Diffs of the changes: (+16 -0)
SelectionDAG.h | 16
1 files changed, 16 insertions(+)
Index: llvm/include/llvm/CodeGen/SelectionDAG.h
diff -u llvm/include/llvm/CodeGen/SelectionDAG.h:1.76
llvm/include/llvm/CodeGen/SelectionDAG.h:1.77
--- llvm/include/llvm/CodeGen/SelectionDAG.h:1.76 Wed Dec 7 20:00:35 2005
+++ llvm/include/llvm/CodeGen/SelectionDAG.hFri Dec 9 16:48:48 2005
@@ -394,6 +394,22 @@
Ops.push_back(Op5);
return getNode(ISD::BUILTIN_OP_END+Opcode, ResultTys, Ops);
}
+ SDOperand getTargetNode(unsigned Opcode, MVT::ValueType VT1,
+ MVT::ValueType VT2, SDOperand Op1, SDOperand Op2,
+ SDOperand Op3, SDOperand Op4, SDOperand Op5,
+ SDOperand Op6) {
+std::vector ResultTys;
+ResultTys.push_back(VT1);
+ResultTys.push_back(VT2);
+std::vector Ops;
+Ops.push_back(Op1);
+Ops.push_back(Op2);
+Ops.push_back(Op3);
+Ops.push_back(Op4);
+Ops.push_back(Op5);
+Ops.push_back(Op6);
+return getNode(ISD::BUILTIN_OP_END+Opcode, ResultTys, Ops);
+ }
SDOperand getTargetNode(unsigned Opcode, MVT::ValueType VT1,
MVT::ValueType VT2, std::vector &Ops) {
std::vector ResultTys;
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[llvm-commits] CVS: llvm/utils/TableGen/DAGISelEmitter.cpp DAGISelEmitter.h
Changes in directory llvm/utils/TableGen:
DAGISelEmitter.cpp updated: 1.90 -> 1.91
DAGISelEmitter.h updated: 1.43 -> 1.44
---
Log message:
Add a new SDTCisPtrTy constraint, which indicates that an operand must have
the same type as the pointer type for a target.
---
Diffs of the changes: (+8 -2)
DAGISelEmitter.cpp |6 ++
DAGISelEmitter.h |4 ++--
2 files changed, 8 insertions(+), 2 deletions(-)
Index: llvm/utils/TableGen/DAGISelEmitter.cpp
diff -u llvm/utils/TableGen/DAGISelEmitter.cpp:1.90
llvm/utils/TableGen/DAGISelEmitter.cpp:1.91
--- llvm/utils/TableGen/DAGISelEmitter.cpp:1.90 Fri Dec 9 16:45:35 2005
+++ llvm/utils/TableGen/DAGISelEmitter.cpp Fri Dec 9 16:57:42 2005
@@ -58,6 +58,8 @@
if (R->isSubClassOf("SDTCisVT")) {
ConstraintType = SDTCisVT;
x.SDTCisVT_Info.VT = getValueType(R->getValueAsDef("VT"));
+ } else if (R->isSubClassOf("SDTCisPtrTy")) {
+ConstraintType = SDTCisPtrTy;
} else if (R->isSubClassOf("SDTCisInt")) {
ConstraintType = SDTCisInt;
} else if (R->isSubClassOf("SDTCisFP")) {
@@ -120,6 +122,10 @@
case SDTCisVT:
// Operand must be a particular type.
return NodeToApply->UpdateNodeType(x.SDTCisVT_Info.VT, TP);
+ case SDTCisPtrTy: {
+// Operand must be same as target pointer type.
+return NodeToApply->UpdateNodeType(CGT.getPointerType(), TP);
+ }
case SDTCisInt: {
// If there is only one integer type supported, this must be it.
std::vector IntVTs =
Index: llvm/utils/TableGen/DAGISelEmitter.h
diff -u llvm/utils/TableGen/DAGISelEmitter.h:1.43
llvm/utils/TableGen/DAGISelEmitter.h:1.44
--- llvm/utils/TableGen/DAGISelEmitter.h:1.43 Fri Dec 9 16:45:35 2005
+++ llvm/utils/TableGen/DAGISelEmitter.hFri Dec 9 16:57:42 2005
@@ -45,8 +45,8 @@
unsigned OperandNo; // The operand # this constraint applies to.
enum {
- SDTCisVT, SDTCisInt, SDTCisFP, SDTCisSameAs, SDTCisVTSmallerThanOp,
- SDTCisOpSmallerThanOp
+ SDTCisVT, SDTCisPtrTy, SDTCisInt, SDTCisFP, SDTCisSameAs,
+ SDTCisVTSmallerThanOp, SDTCisOpSmallerThanOp
} ConstraintType;
union { // The discriminated union.
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[llvm-commits] CVS: llvm/lib/Target/TargetSelectionDAG.td
Changes in directory llvm/lib/Target:
TargetSelectionDAG.td updated: 1.13 -> 1.14
---
Log message:
Add SDTCisPtrTy and use it for loads, to indicate that the operand of a load
must be a pointer. This removes a type check out of the code generated by
tblgen for load matching.
---
Diffs of the changes: (+5 -3)
TargetSelectionDAG.td |8 +---
1 files changed, 5 insertions(+), 3 deletions(-)
Index: llvm/lib/Target/TargetSelectionDAG.td
diff -u llvm/lib/Target/TargetSelectionDAG.td:1.13
llvm/lib/Target/TargetSelectionDAG.td:1.14
--- llvm/lib/Target/TargetSelectionDAG.td:1.13 Wed Dec 7 22:28:48 2005
+++ llvm/lib/Target/TargetSelectionDAG.td Fri Dec 9 16:58:42 2005
@@ -24,15 +24,17 @@
}
// SDTCisVT - The specified operand has exactly this VT.
-class SDTCisVT : SDTypeConstraint {
+class SDTCisVT : SDTypeConstraint {
ValueType VT = vt;
}
+class SDTCisPtrTy : SDTypeConstraint;
+
// SDTCisInt - The specified operand is has integer type.
class SDTCisInt : SDTypeConstraint;
// SDTCisFP - The specified operand is has floating point type.
-class SDTCisFP : SDTypeConstraint;
+class SDTCisFP : SDTypeConstraint;
// SDTCisSameAs - The two specified operands have identical types.
class SDTCisSameAs : SDTypeConstraint {
@@ -132,7 +134,7 @@
]>;
def SDTLoad : SDTypeProfile<1, 1, [ // load
- SDTCisInt<1>
+ SDTCisPtrTy<1>
]>;
//===--===//
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[llvm-commits] CVS: llvm/lib/Target/PowerPC/PPCInstrFormats.td PPCInstrInfo.td
Changes in directory llvm/lib/Target/PowerPC:
PPCInstrFormats.td updated: 1.60 -> 1.61
PPCInstrInfo.td updated: 1.152 -> 1.153
---
Log message:
Add support patterns to many load and store instructions which will
hopefully use patterns in the near future.
---
Diffs of the changes: (+133 -76)
PPCInstrFormats.td | 69 +++---
PPCInstrInfo.td| 140 +++--
2 files changed, 133 insertions(+), 76 deletions(-)
Index: llvm/lib/Target/PowerPC/PPCInstrFormats.td
diff -u llvm/lib/Target/PowerPC/PPCInstrFormats.td:1.60
llvm/lib/Target/PowerPC/PPCInstrFormats.td:1.61
--- llvm/lib/Target/PowerPC/PPCInstrFormats.td:1.60 Sun Dec 4 12:42:54 2005
+++ llvm/lib/Target/PowerPC/PPCInstrFormats.td Fri Dec 9 17:54:17 2005
@@ -58,23 +58,27 @@
// 1.7.4 D-Form
class DForm_base opcode, dag OL, string asmstr, InstrItinClass itin,
- list pattern>
- : I {
- let Pattern = pattern;
+ list pattern>
+ : I {
bits<5> A;
bits<5> B;
bits<16> C;
+
+ let Pattern = pattern;
let Inst{6-10} = A;
let Inst{11-15} = B;
let Inst{16-31} = C;
}
-class DForm_1 opcode, dag OL, string asmstr, InstrItinClass itin>
- : I {
+class DForm_1 opcode, dag OL, string asmstr, InstrItinClass itin,
+ list pattern>
+ : I {
bits<5> A;
bits<16> C;
bits<5> B;
+
+ let Pattern = pattern;
let Inst{6-10} = A;
let Inst{11-15} = B;
@@ -99,12 +103,13 @@
}
// Currently we make the use/def reg distinction in ISel, not tablegen
-class DForm_3 opcode, dag OL, string asmstr, InstrItinClass itin>
- : DForm_1;
+class DForm_3 opcode, dag OL, string asmstr, InstrItinClass itin,
+ list pattern>
+ : DForm_1;
class DForm_4 opcode, dag OL, string asmstr, InstrItinClass itin,
list pattern>
- : I {
+ : I {
bits<5> B;
bits<5> A;
bits<16> C;
@@ -116,8 +121,9 @@
let Inst{16-31} = C;
}
-class DForm_4_zero opcode, dag OL, string asmstr, InstrItinClass itin>
- : DForm_1 {
+class DForm_4_zero opcode, dag OL, string asmstr, InstrItinClass itin,
+ list pattern>
+ : DForm_1 {
let A = 0;
let B = 0;
let C = 0;
@@ -150,22 +156,26 @@
let L = PPC64;
}
-class DForm_8 opcode, dag OL, string asmstr, InstrItinClass itin>
- : DForm_1 {
+class DForm_8 opcode, dag OL, string asmstr, InstrItinClass itin,
+ list pattern>
+ : DForm_1 {
}
-class DForm_9 opcode, dag OL, string asmstr, InstrItinClass itin>
- : DForm_1 {
+class DForm_9 opcode, dag OL, string asmstr, InstrItinClass itin,
+ list pattern>
+ : DForm_1 {
}
// 1.7.5 DS-Form
class DSForm_1 opcode, bits<2> xo, dag OL, string asmstr,
- InstrItinClass itin>
+ InstrItinClass itin, list pattern>
: I {
bits<5> RST;
bits<14> DS;
bits<5> RA;
+ let Pattern = pattern;
+
let Inst{6-10} = RST;
let Inst{11-15} = RA;
let Inst{16-29} = DS;
@@ -173,17 +183,19 @@
}
class DSForm_2 opcode, bits<2> xo, dag OL, string asmstr,
- InstrItinClass itin>
- : DSForm_1;
+ InstrItinClass itin, list pattern>
+ : DSForm_1;
// 1.7.6 X-Form
-class XForm_base_r3xo opcode, bits<10> xo,
- dag OL, string asmstr, InstrItinClass itin>
+class XForm_base_r3xo opcode, bits<10> xo, dag OL, string asmstr,
+ InstrItinClass itin, list pattern>
: I {
bits<5> RST;
bits<5> A;
bits<5> B;
+ let Pattern = pattern;
+
bit RC = 0;// set by isDOT
let Inst{6-10} = RST;
@@ -214,8 +226,8 @@
class XForm_1 opcode, bits<10> xo, dag OL, string asmstr,
- InstrItinClass itin>
- : XForm_base_r3xo;
+ InstrItinClass itin, list pattern>
+ : XForm_base_r3xo;
class XForm_6 opcode, bits<10> xo, dag OL, string asmstr,
InstrItinClass itin, list pattern>
@@ -224,8 +236,8 @@
}
class XForm_8 opcode, bits<10> xo, dag OL, string asmstr,
- InstrItinClass itin>
- : XForm_base_r3xo;
+ InstrItinClass itin, list pattern>
+ : XForm_base_r3xo;
class XForm_10 opcode, bits<10> xo, dag OL, string asmstr,
InstrItinClass itin, list pattern>
@@ -279,20 +291,19 @@
}
class XForm_25 opcode, bits<10> xo, dag OL, string asmstr,
- InstrItinClass itin>
- : XForm_base_r3xo {
+ InstrItinClass itin, list pattern>
+ : XForm_base_r3xo {
}
class XForm_26 opcode, bits<10> xo, dag OL, string asmstr,
InstrItinClass itin, list pattern>
- : XForm_base_r3xo {
+ : XForm_base_r3xo {
let A = 0;
- let Pattern = pattern;
}
class XForm_28 opcode, bits<10> xo, dag OL, string asmstr,
- InstrItinClass itin>
- : XForm_base_r3xo {
+ InstrItinClass itin, list pattern>
+ : XForm_base_r3xo {
}
// 1.7.7 XL-Form
Index: llvm/lib/Target/PowerPC/PPCInstrInfo.td
diff -u llvm/lib/T
[llvm-commits] CVS: llvm/utils/TableGen/DAGISelEmitter.cpp
Changes in directory llvm/utils/TableGen:
DAGISelEmitter.cpp updated: 1.91 -> 1.92
---
Log message:
For instructions which produce no result, e.g. store, chain's Resno == 0.
---
Diffs of the changes: (+6 -4)
DAGISelEmitter.cpp | 10 ++
1 files changed, 6 insertions(+), 4 deletions(-)
Index: llvm/utils/TableGen/DAGISelEmitter.cpp
diff -u llvm/utils/TableGen/DAGISelEmitter.cpp:1.91
llvm/utils/TableGen/DAGISelEmitter.cpp:1.92
--- llvm/utils/TableGen/DAGISelEmitter.cpp:1.91 Fri Dec 9 16:57:42 2005
+++ llvm/utils/TableGen/DAGISelEmitter.cpp Fri Dec 9 18:09:17 2005
@@ -1779,10 +1779,11 @@
if (NodeHasChain(N, ISE)) {
OpNo = 1;
if (!isRoot) {
+const SDNodeInfo &CInfo = ISE.getSDNodeInfo(N->getOperator());
OS << " if (!" << RootName << ".hasOneUse()) goto P"
<< PatternNo << "Fail; // Multiple uses of actual result?\n";
OS << " if (CodeGenMap.count(" << RootName
- << ".getValue(1))) goto P"
+ << ".getValue(" << CInfo.getNumResults() << "))) goto P"
<< PatternNo << "Fail; // Already selected for a chain use?\n";
}
if (InnerChain.empty()) {
@@ -2024,10 +2025,11 @@
}
OS << " Chain ";
if (NodeHasChain(LHS, ISE))
- OS << "= CodeGenMap[N.getValue(1)] ";
+ OS << "= CodeGenMap[N.getValue(" << NumResults << ")] ";
for (unsigned j = 0, e = FoldedChains.size(); j < e; j++)
- OS << "= CodeGenMap[" << FoldedChains[j] << ".getValue(1)] ";
-OS << "= Result.getValue(1);\n";
+ OS << "= CodeGenMap[" << FoldedChains[j] << ".getValue("
+ << NumResults << ")] ";
+OS << "= Result.getValue(" << NumResults << ");\n";
if (NumResults == 0)
OS << " return Chain;\n";
else
___
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[llvm-commits] CVS: llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
Changes in directory llvm/lib/CodeGen/SelectionDAG:
SelectionDAG.cpp updated: 1.223 -> 1.224
---
Log message:
Added new getNode and getTargetNode variants for X86 stores.
---
Diffs of the changes: (+73 -60)
SelectionDAG.cpp | 133 ++-
1 files changed, 73 insertions(+), 60 deletions(-)
Index: llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
diff -u llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp:1.223
llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp:1.224
--- llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp:1.223Tue Dec 6
00:18:55 2005
+++ llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp Fri Dec 9 18:37:58 2005
@@ -1088,66 +1088,6 @@
return SDOperand(N, 0);
}
-// setAdjCallChain - This method changes the token chain of an
-// CALLSEQ_START/END node to be the specified operand.
-void SDNode::setAdjCallChain(SDOperand N) {
- assert(N.getValueType() == MVT::Other);
- assert((getOpcode() == ISD::CALLSEQ_START ||
- getOpcode() == ISD::CALLSEQ_END) && "Cannot adjust this node!");
-
- OperandList[0].Val->removeUser(this);
- OperandList[0] = N;
- OperandList[0].Val->Uses.push_back(this);
-}
-
-
-
-SDOperand SelectionDAG::getLoad(MVT::ValueType VT,
-SDOperand Chain, SDOperand Ptr,
-SDOperand SV) {
- SDNode *&N = Loads[std::make_pair(Ptr, std::make_pair(Chain, VT))];
- if (N) return SDOperand(N, 0);
- N = new SDNode(ISD::LOAD, Chain, Ptr, SV);
-
- // Loads have a token chain.
- setNodeValueTypes(N, VT, MVT::Other);
- AllNodes.push_back(N);
- return SDOperand(N, 0);
-}
-
-SDOperand SelectionDAG::getVecLoad(unsigned Count, MVT::ValueType EVT,
- SDOperand Chain, SDOperand Ptr,
- SDOperand SV) {
- SDNode *&N = Loads[std::make_pair(Ptr, std::make_pair(Chain, EVT))];
- if (N) return SDOperand(N, 0);
- std::vector Ops;
- Ops.reserve(5);
- Ops.push_back(Chain);
- Ops.push_back(Ptr);
- Ops.push_back(getConstant(Count, MVT::i32));
- Ops.push_back(getValueType(EVT));
- Ops.push_back(SV);
- std::vector VTs;
- VTs.reserve(2);
- VTs.push_back(MVT::Vector); VTs.push_back(MVT::Other); // Add token chain.
- return getNode(ISD::VLOAD, VTs, Ops);
-}
-
-SDOperand SelectionDAG::getExtLoad(unsigned Opcode, MVT::ValueType VT,
- SDOperand Chain, SDOperand Ptr, SDOperand
SV,
- MVT::ValueType EVT) {
- std::vector Ops;
- Ops.reserve(4);
- Ops.push_back(Chain);
- Ops.push_back(Ptr);
- Ops.push_back(SV);
- Ops.push_back(getValueType(EVT));
- std::vector VTs;
- VTs.reserve(2);
- VTs.push_back(VT); VTs.push_back(MVT::Other); // Add token chain.
- return getNode(Opcode, VTs, Ops);
-}
-
SDOperand SelectionDAG::getNode(unsigned Opcode, MVT::ValueType VT,
SDOperand N1, SDOperand N2, SDOperand N3) {
// Perform various simplifications.
@@ -1224,6 +1164,79 @@
return getNode(Opcode, VT, Ops);
}
+SDOperand SelectionDAG::getNode(unsigned Opcode, MVT::ValueType VT,
+SDOperand N1, SDOperand N2, SDOperand N3,
+SDOperand N4, SDOperand N5, SDOperand N6) {
+ std::vector Ops;
+ Ops.reserve(6);
+ Ops.push_back(N1);
+ Ops.push_back(N2);
+ Ops.push_back(N3);
+ Ops.push_back(N4);
+ Ops.push_back(N5);
+ Ops.push_back(N6);
+ return getNode(Opcode, VT, Ops);
+}
+
+// setAdjCallChain - This method changes the token chain of an
+// CALLSEQ_START/END node to be the specified operand.
+void SDNode::setAdjCallChain(SDOperand N) {
+ assert(N.getValueType() == MVT::Other);
+ assert((getOpcode() == ISD::CALLSEQ_START ||
+ getOpcode() == ISD::CALLSEQ_END) && "Cannot adjust this node!");
+
+ OperandList[0].Val->removeUser(this);
+ OperandList[0] = N;
+ OperandList[0].Val->Uses.push_back(this);
+}
+
+
+
+SDOperand SelectionDAG::getLoad(MVT::ValueType VT,
+SDOperand Chain, SDOperand Ptr,
+SDOperand SV) {
+ SDNode *&N = Loads[std::make_pair(Ptr, std::make_pair(Chain, VT))];
+ if (N) return SDOperand(N, 0);
+ N = new SDNode(ISD::LOAD, Chain, Ptr, SV);
+
+ // Loads have a token chain.
+ setNodeValueTypes(N, VT, MVT::Other);
+ AllNodes.push_back(N);
+ return SDOperand(N, 0);
+}
+
+SDOperand SelectionDAG::getVecLoad(unsigned Count, MVT::ValueType EVT,
+ SDOperand Chain, SDOperand Ptr,
+ SDOperand SV) {
+ SDNode *&N = Loads[std::make_pair(Ptr, std::make_pair(Chain, EVT))];
+ if (N) return SDOperand(N, 0);
+ std::vector Ops;
+ Ops.reserve(5);
+ Ops.push_back(Chain);
+ Ops.push_back(Ptr);
+ Ops.push_back(getConstant(Count, MVT::i32));
+ Ops.push_back(getValueType(EVT));
+ Ops.push_back(SV);
+ std::vector VTs;
+ VTs.reserve(2);
+ VTs.push_back(MVT::Vector); VTs.push_back(MVT::Other); // Add token
[llvm-commits] CVS: llvm/include/llvm/CodeGen/SelectionDAG.h
Changes in directory llvm/include/llvm/CodeGen:
SelectionDAG.h updated: 1.77 -> 1.78
---
Log message:
Added new getNode and getTargetNode variants for X86 stores.
---
Diffs of the changes: (+8 -0)
SelectionDAG.h |8
1 files changed, 8 insertions(+)
Index: llvm/include/llvm/CodeGen/SelectionDAG.h
diff -u llvm/include/llvm/CodeGen/SelectionDAG.h:1.77
llvm/include/llvm/CodeGen/SelectionDAG.h:1.78
--- llvm/include/llvm/CodeGen/SelectionDAG.h:1.77 Fri Dec 9 16:48:48 2005
+++ llvm/include/llvm/CodeGen/SelectionDAG.hFri Dec 9 18:37:58 2005
@@ -233,6 +233,9 @@
SDOperand N1, SDOperand N2, SDOperand N3, SDOperand N4,
SDOperand N5);
SDOperand getNode(unsigned Opcode, MVT::ValueType VT,
+SDOperand N1, SDOperand N2, SDOperand N3, SDOperand N4,
+SDOperand N5, SDOperand N6);
+ SDOperand getNode(unsigned Opcode, MVT::ValueType VT,
std::vector &Children);
SDOperand getNode(unsigned Opcode, std::vector &ResultTys,
std::vector &Ops);
@@ -342,6 +345,11 @@
return getNode(ISD::BUILTIN_OP_END+Opcode, VT, Op1, Op2, Op3, Op4, Op5);
}
SDOperand getTargetNode(unsigned Opcode, MVT::ValueType VT,
+ SDOperand Op1, SDOperand Op2, SDOperand Op3,
+ SDOperand Op4, SDOperand Op5, SDOperand Op6) {
+return getNode(ISD::BUILTIN_OP_END+Opcode, VT, Op1, Op2, Op3, Op4, Op5,
Op6);
+ }
+ SDOperand getTargetNode(unsigned Opcode, MVT::ValueType VT,
std::vector &Ops) {
return getNode(ISD::BUILTIN_OP_END+Opcode, VT, Ops);
}
___
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[llvm-commits] CVS: llvm/lib/Target/X86/X86ISelDAGToDAG.cpp X86InstrInfo.td
Changes in directory llvm/lib/Target/X86:
X86ISelDAGToDAG.cpp updated: 1.7 -> 1.8
X86InstrInfo.td updated: 1.151 -> 1.152
---
Log message:
* Added X86 store patterns.
* Added X86 dec patterns.
---
Diffs of the changes: (+19 -43)
X86ISelDAGToDAG.cpp | 33 -
X86InstrInfo.td | 29 +++--
2 files changed, 19 insertions(+), 43 deletions(-)
Index: llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
diff -u llvm/lib/Target/X86/X86ISelDAGToDAG.cpp:1.7
llvm/lib/Target/X86/X86ISelDAGToDAG.cpp:1.8
--- llvm/lib/Target/X86/X86ISelDAGToDAG.cpp:1.7 Wed Dec 7 20:01:35 2005
+++ llvm/lib/Target/X86/X86ISelDAGToDAG.cpp Fri Dec 9 18:48:20 2005
@@ -387,39 +387,6 @@
getI16Imm(X86Lowering.getBytesToPopOnReturn()),
Chain);
}
-
-case ISD::STORE: {
- SDOperand Chain = Select(N->getOperand(0)); // Token chain.
- SDOperand Tmp1 = Select(N->getOperand(1));
- Opc = 0;
- if (ConstantSDNode *CN = dyn_cast(N->getOperand(1))) {
-switch (CN->getValueType(0)) {
- default: assert(0 && "Invalid type for operation!");
- case MVT::i1:
- case MVT::i8: Opc = X86::MOV8mi; break;
- case MVT::i16: Opc = X86::MOV16mi; break;
- case MVT::i32: Opc = X86::MOV32mi; break;
-}
- }
-
- if (!Opc) {
-switch (N->getOperand(1).getValueType()) {
- default: assert(0 && "Cannot store this type!");
- case MVT::i1:
- case MVT::i8: Opc = X86::MOV8mr; break;
- case MVT::i16: Opc = X86::MOV16mr; break;
- case MVT::i32: Opc = X86::MOV32mr; break;
- case MVT::f32: Opc = X86::MOVSSmr; break;
- case MVT::f64: Opc = X86::FST64m; break;
-}
- }
-
- SDOperand Base, Scale, Index, Disp;
- SelectAddr(N->getOperand(2), Base, Scale, Index, Disp);
- return CurDAG->SelectNodeTo(N, Opc, MVT::Other,
- Base, Scale, Index, Disp, Tmp1, Chain)
-.getValue(Op.ResNo);
-}
}
return SelectCode(Op);
Index: llvm/lib/Target/X86/X86InstrInfo.td
diff -u llvm/lib/Target/X86/X86InstrInfo.td:1.151
llvm/lib/Target/X86/X86InstrInfo.td:1.152
--- llvm/lib/Target/X86/X86InstrInfo.td:1.151 Fri Dec 9 16:48:48 2005
+++ llvm/lib/Target/X86/X86InstrInfo.td Fri Dec 9 18:48:20 2005
@@ -378,11 +378,14 @@
"mov{l} {$src, $dst|$dst, $src}",
[(set R32:$dst, imm:$src)]>;
def MOV8mi : Ii8 <0xC6, MRM0m, (ops i8mem :$dst, i8imm :$src),
- "mov{b} {$src, $dst|$dst, $src}", []>;
+ "mov{b} {$src, $dst|$dst, $src}",
+ [(store (i8 imm:$src), addr:$dst)]>;
def MOV16mi : Ii16<0xC7, MRM0m, (ops i16mem:$dst, i16imm:$src),
- "mov{w} {$src, $dst|$dst, $src}", []>, OpSize;
+ "mov{w} {$src, $dst|$dst, $src}",
+ [(store (i16 imm:$src), addr:$dst)]>, OpSize;
def MOV32mi : Ii32<0xC7, MRM0m, (ops i32mem:$dst, i32imm:$src),
- "mov{l} {$src, $dst|$dst, $src}", []>;
+ "mov{l} {$src, $dst|$dst, $src}",
+ [(store (i32 imm:$src), addr:$dst)]>;
def MOV8rm : I<0x8A, MRMSrcMem, (ops R8 :$dst, i8mem :$src),
"mov{b} {$src, $dst|$dst, $src}",
@@ -395,11 +398,14 @@
[(set R32:$dst, (load addr:$src))]>;
def MOV8mr : I<0x88, MRMDestMem, (ops i8mem :$dst, R8 :$src),
-"mov{b} {$src, $dst|$dst, $src}", []>;
+"mov{b} {$src, $dst|$dst, $src}",
+[(store R8:$src, addr:$dst)]>;
def MOV16mr : I<0x89, MRMDestMem, (ops i16mem:$dst, R16:$src),
-"mov{w} {$src, $dst|$dst, $src}", []>, OpSize;
+"mov{w} {$src, $dst|$dst, $src}",
+[(store R16:$src, addr:$dst)]>, OpSize;
def MOV32mr : I<0x89, MRMDestMem, (ops i32mem:$dst, R32:$src),
-"mov{l} {$src, $dst|$dst, $src}", []>;
+"mov{l} {$src, $dst|$dst, $src}",
+[(store R32:$src, addr:$dst)]>;
//===--===//
// Fixed-Register Multiplication and Division Instructions...
@@ -687,6 +693,7 @@
def NOT32m : I<0xF7, MRM2m, (ops i32mem:$dst), "not{l} $dst", []>;
}
+// TODO: inc/dec is slow for P4, but fast for Pentium-M.
def INC8r : I<0xFE, MRM0r, (ops R8 :$dst, R8 :$src), "inc{b} $dst",
[(set R8:$dst, (add R8:$src, 1))]>;
let isConvertibleToThreeAddress = 1 in { // Can transform into LEA.
@@ -701,11 +708,13 @@
def INC32m : I<0xFF, MRM0m, (ops i32mem:$dst), "inc{l} $dst", []>;
}
-def DEC8r : I<0xFE, MRM1r, (ops R8 :$dst, R8 :$src), "dec{b} $dst", []>;
+def DEC8r : I<0xFE, MRM1r, (ops R8 :$dst, R8 :$src), "dec{b} $dst",
+ [(set R8:$dst, (add R8:$src, -1))]>;
let isConvertibleToThreeAddress = 1 in { // Can transform int
[llvm-commits] CVS: llvm/lib/Target/TargetSelectionDAG.td
Changes in directory llvm/lib/Target: TargetSelectionDAG.td updated: 1.14 -> 1.15 --- Log message: * Added X86 store patterns. * Added X86 dec patterns. --- Diffs of the changes: (+5 -0) TargetSelectionDAG.td |5 + 1 files changed, 5 insertions(+) Index: llvm/lib/Target/TargetSelectionDAG.td diff -u llvm/lib/Target/TargetSelectionDAG.td:1.14 llvm/lib/Target/TargetSelectionDAG.td:1.15 --- llvm/lib/Target/TargetSelectionDAG.td:1.14 Fri Dec 9 16:58:42 2005 +++ llvm/lib/Target/TargetSelectionDAG.td Fri Dec 9 18:48:20 2005 @@ -137,6 +137,10 @@ SDTCisPtrTy<1> ]>; +def SDTStore : SDTypeProfile<0, 2, [ // store + SDTCisInt<1> +]>; + //===--===// // Selection DAG Node Properties. // @@ -227,6 +231,7 @@ def writeport : SDNode<"ISD::WRITEPORT" , SDTWritePort, [SDNPHasChain]>; def load : SDNode<"ISD::LOAD" , SDTLoad, [SDNPHasChain]>; +def store : SDNode<"ISD::STORE" , SDTStore, [SDNPHasChain]>; //===--===// // Selection DAG Condition Codes ___ llvm-commits mailing list llvm-commits@cs.uiuc.edu http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
[llvm-commits] CVS: llvm/utils/TableGen/DAGISelEmitter.cpp
Changes in directory llvm/utils/TableGen:
DAGISelEmitter.cpp updated: 1.92 -> 1.93
---
Log message:
Stop emitting a redudant type check for complex pattern node.
---
Diffs of the changes: (+0 -5)
DAGISelEmitter.cpp |5 -
1 files changed, 5 deletions(-)
Index: llvm/utils/TableGen/DAGISelEmitter.cpp
diff -u llvm/utils/TableGen/DAGISelEmitter.cpp:1.92
llvm/utils/TableGen/DAGISelEmitter.cpp:1.93
--- llvm/utils/TableGen/DAGISelEmitter.cpp:1.92 Fri Dec 9 18:09:17 2005
+++ llvm/utils/TableGen/DAGISelEmitter.cpp Fri Dec 9 19:57:33 2005
@@ -2091,11 +2091,6 @@
OS << " if (" << Prefix << ".Val->getValueType(0) != MVT::"
<< getName(Pat->getType()) << ") goto P" << PatternNo << "Fail;\n";
return true;
-} else if (Pat->isLeaf()) {
- if (NodeIsComplexPattern(Pat))
-OS << " if (" << Prefix << ".Val->getValueType(0) != MVT::"
- << getName(Pat->getType()) << ") goto P" << PatternNo << "Fail;\n";
- return false;
}
unsigned OpNo = (unsigned) NodeHasChain(Pat, ISE);
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[llvm-commits] CVS: llvm/lib/Target/TargetSelectionDAG.td
Changes in directory llvm/lib/Target: TargetSelectionDAG.td updated: 1.15 -> 1.16 --- Log message: Use SDTCisPtrTy type property for store address. --- Diffs of the changes: (+2 -2) TargetSelectionDAG.td |4 ++-- 1 files changed, 2 insertions(+), 2 deletions(-) Index: llvm/lib/Target/TargetSelectionDAG.td diff -u llvm/lib/Target/TargetSelectionDAG.td:1.15 llvm/lib/Target/TargetSelectionDAG.td:1.16 --- llvm/lib/Target/TargetSelectionDAG.td:1.15 Fri Dec 9 18:48:20 2005 +++ llvm/lib/Target/TargetSelectionDAG.td Fri Dec 9 19:59:36 2005 @@ -138,7 +138,7 @@ ]>; def SDTStore : SDTypeProfile<0, 2, [ // store - SDTCisInt<1> + SDTCisPtrTy<1> ]>; //===--===// @@ -230,7 +230,7 @@ def writeport : SDNode<"ISD::WRITEPORT" , SDTWritePort, [SDNPHasChain]>; -def load : SDNode<"ISD::LOAD" , SDTLoad, [SDNPHasChain]>; +def load : SDNode<"ISD::LOAD" , SDTLoad, [SDNPHasChain]>; def store : SDNode<"ISD::STORE" , SDTStore, [SDNPHasChain]>; //===--===// ___ llvm-commits mailing list llvm-commits@cs.uiuc.edu http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
[llvm-commits] CVS: llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp PPCISelLowering.cpp PPCInstrInfo.td
Changes in directory llvm/lib/Target/PowerPC:
PPCISelDAGToDAG.cpp updated: 1.139 -> 1.140
PPCISelLowering.cpp updated: 1.49 -> 1.50
PPCInstrInfo.td updated: 1.153 -> 1.154
---
Log message:
Add support for TargetConstantPool nodes to the dag isel emitter, and use
them in the PPC backend, to simplify some logic out of Select and
SelectAddr.
---
Diffs of the changes: (+40 -29)
PPCISelDAGToDAG.cpp | 29 +
PPCISelLowering.cpp | 35 +++
PPCInstrInfo.td |5 -
3 files changed, 40 insertions(+), 29 deletions(-)
Index: llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp
diff -u llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp:1.139
llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp:1.140
--- llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp:1.139 Tue Dec 6 14:56:18 2005
+++ llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp Fri Dec 9 20:36:00 2005
@@ -423,7 +423,8 @@
assert(!cast(Addr.getOperand(1).getOperand(1))->getValue()
&& "Cannot handle constant offsets yet!");
Op1 = Addr.getOperand(1).getOperand(0); // The global address.
- assert(Op1.getOpcode() == ISD::TargetGlobalAddress);
+ assert(Op1.getOpcode() == ISD::TargetGlobalAddress ||
+ Op1.getOpcode() == ISD::TargetConstantPool);
Op2 = Select(Addr.getOperand(0));
return false; // [&g+r]
} else {
@@ -433,20 +434,11 @@
}
}
- if (FrameIndexSDNode *FI = dyn_cast(Addr)) {
-Op1 = getI32Imm(0);
+ if (FrameIndexSDNode *FI = dyn_cast(Addr))
Op2 = CurDAG->getTargetFrameIndex(FI->getIndex(), MVT::i32);
-return false;
- } else if (ConstantPoolSDNode *CP = dyn_cast(Addr)) {
-Op1 = Addr;
-if (PICEnabled)
- Op2 = CurDAG->getTargetNode(PPC::ADDIS, MVT::i32,
getGlobalBaseReg(),Op1);
-else
- Op2 = CurDAG->getTargetNode(PPC::LIS, MVT::i32, Op1);
-return false;
- }
+ else
+Op2 = Select(Addr);
Op1 = getI32Imm(0);
- Op2 = Select(Addr);
return false;
}
@@ -893,17 +885,6 @@
CurDAG->getTargetFrameIndex(FI, MVT::i32),
getI32Imm(0));
}
- case ISD::ConstantPool: {
-Constant *C = cast(N)->get();
-SDOperand Tmp, CPI = CurDAG->getTargetConstantPool(C, MVT::i32);
-if (PICEnabled)
- Tmp = CurDAG->getTargetNode(PPC::ADDIS, MVT::i32,
getGlobalBaseReg(),CPI);
-else
- Tmp = CurDAG->getTargetNode(PPC::LIS, MVT::i32, CPI);
-if (N->hasOneUse())
- return CurDAG->SelectNodeTo(N, PPC::LA, MVT::i32, Tmp, CPI);
-return CodeGenMap[Op] = CurDAG->getTargetNode(PPC::LA, MVT::i32, Tmp, CPI);
- }
case ISD::FADD: {
MVT::ValueType Ty = N->getValueType(0);
if (!NoExcessFPPrecision) { // Match FMA ops
Index: llvm/lib/Target/PowerPC/PPCISelLowering.cpp
diff -u llvm/lib/Target/PowerPC/PPCISelLowering.cpp:1.49
llvm/lib/Target/PowerPC/PPCISelLowering.cpp:1.50
--- llvm/lib/Target/PowerPC/PPCISelLowering.cpp:1.49Mon Dec 5 20:10:38 2005
+++ llvm/lib/Target/PowerPC/PPCISelLowering.cpp Fri Dec 9 20:36:00 2005
@@ -94,9 +94,10 @@
// PowerPC doesn't have line number support yet.
setOperationAction(ISD::LOCATION, MVT::Other, Expand);
- // We want to legalize GlobalAddress into the appropriate instructions to
- // materialize the address.
+ // We want to legalize GlobalAddress and ConstantPool nodes into the
+ // appropriate instructions to materialize the address.
setOperationAction(ISD::GlobalAddress, MVT::i32, Custom);
+ setOperationAction(ISD::ConstantPool, MVT::i32, Custom);
if (TM.getSubtarget().is64Bit()) {
// They also have instructions for converting between i64 and fp.
@@ -341,14 +342,40 @@
Tmp4, Tmp6, ISD::SETLE);
return DAG.getNode(ISD::BUILD_PAIR, MVT::i64, OutLo, OutHi);
}
+ case ISD::ConstantPool: {
+Constant *C = cast(Op)->get();
+SDOperand CPI = DAG.getTargetConstantPool(C, MVT::i32);
+SDOperand Zero = DAG.getConstant(0, MVT::i32);
+
+if (PPCGenerateStaticCode) {
+ // Generate non-pic code that has direct accesses to the constant pool.
+ // The address of the global is just (hi(&g)+lo(&g)).
+ SDOperand Hi = DAG.getNode(PPCISD::Hi, MVT::i32, CPI, Zero);
+ SDOperand Lo = DAG.getNode(PPCISD::Lo, MVT::i32, CPI, Zero);
+ return DAG.getNode(ISD::ADD, MVT::i32, Hi, Lo);
+}
+
+// Only lower ConstantPool on Darwin.
+if (!getTargetMachine().getSubtarget().isDarwin()) break;
+SDOperand Hi = DAG.getNode(PPCISD::Hi, MVT::i32, CPI, Zero);
+if (PICEnabled) {
+ // With PIC, the first instruction is actually "GR+hi(&G)".
+ Hi = DAG.getNode(ISD::ADD, MVT::i32,
+ DAG.getNode(PPCISD::GlobalBaseReg, MVT::i32), Hi);
+}
+
+SDOperand Lo = DAG.getNode(PPCISD::Lo, MVT::i32, CPI, Zero);
+Lo = DAG.getNode(ISD::ADD, MVT::i32, Hi, Lo);
+return Lo;
+ }
case ISD::GlobalAddress: {
GlobalValue *GV = cast(Op)->getGlobal();
[llvm-commits] CVS: llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
Changes in directory llvm/lib/CodeGen/SelectionDAG:
LegalizeDAG.cpp updated: 1.225 -> 1.226
---
Log message:
Add support for TargetConstantPool nodes to the dag isel emitter, and use
them in the PPC backend, to simplify some logic out of Select and
SelectAddr.
---
Diffs of the changes: (+3 -1)
LegalizeDAG.cpp |4 +++-
1 files changed, 3 insertions(+), 1 deletion(-)
Index: llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
diff -u llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp:1.225
llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp:1.226
--- llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp:1.225 Fri Dec 9 11:32:47 2005
+++ llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp Fri Dec 9 20:36:00 2005
@@ -532,6 +532,7 @@
case ISD::TargetFrameIndex:
case ISD::Register:
case ISD::TargetConstant:
+ case ISD::TargetConstantPool:
case ISD::GlobalAddress:
case ISD::TargetGlobalAddress:
case ISD::ExternalSymbol:
@@ -679,7 +680,8 @@
Extend = true;
}
- SDOperand CPIdx = DAG.getConstantPool(LLVMC, TLI.getPointerTy());
+ SDOperand CPIdx =
+LegalizeOp(DAG.getConstantPool(LLVMC, TLI.getPointerTy()));
if (Extend) {
Result = DAG.getExtLoad(ISD::EXTLOAD, MVT::f64, DAG.getEntryNode(),
CPIdx, DAG.getSrcValue(NULL), MVT::f32);
___
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[llvm-commits] CVS: llvm/lib/Target/TargetSelectionDAG.td
Changes in directory llvm/lib/Target: TargetSelectionDAG.td updated: 1.16 -> 1.17 --- Log message: Add support for TargetConstantPool nodes to the dag isel emitter, and use them in the PPC backend, to simplify some logic out of Select and SelectAddr. --- Diffs of the changes: (+2 -0) TargetSelectionDAG.td |2 ++ 1 files changed, 2 insertions(+) Index: llvm/lib/Target/TargetSelectionDAG.td diff -u llvm/lib/Target/TargetSelectionDAG.td:1.16 llvm/lib/Target/TargetSelectionDAG.td:1.17 --- llvm/lib/Target/TargetSelectionDAG.td:1.16 Fri Dec 9 19:59:36 2005 +++ llvm/lib/Target/TargetSelectionDAG.td Fri Dec 9 20:36:00 2005 @@ -174,6 +174,8 @@ "GlobalAddressSDNode">; def tglobaladdr : SDNode<"ISD::TargetGlobalAddress", SDTImm, [], "GlobalAddressSDNode">; +def tconstpool : SDNode<"ISD::TargetConstantPool", SDTImm, [], +"ConstantPoolSDNode">; def add: SDNode<"ISD::ADD" , SDTIntBinOp , [SDNPCommutative, SDNPAssociative]>; def sub: SDNode<"ISD::SUB" , SDTIntBinOp>; ___ llvm-commits mailing list llvm-commits@cs.uiuc.edu http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
[llvm-commits] CVS: llvm/utils/TableGen/DAGISelEmitter.cpp
Changes in directory llvm/utils/TableGen:
DAGISelEmitter.cpp updated: 1.93 -> 1.94
---
Log message:
Add support for TargetConstantPool nodes to the dag isel emitter, and use
them in the PPC backend, to simplify some logic out of Select and
SelectAddr.
---
Diffs of the changes: (+2 -0)
DAGISelEmitter.cpp |2 ++
1 files changed, 2 insertions(+)
Index: llvm/utils/TableGen/DAGISelEmitter.cpp
diff -u llvm/utils/TableGen/DAGISelEmitter.cpp:1.93
llvm/utils/TableGen/DAGISelEmitter.cpp:1.94
--- llvm/utils/TableGen/DAGISelEmitter.cpp:1.93 Fri Dec 9 19:57:33 2005
+++ llvm/utils/TableGen/DAGISelEmitter.cpp Fri Dec 9 20:36:00 2005
@@ -1900,6 +1900,8 @@
<< ResNo << "C, MVT::" << getEnumName(N->getType()) << ");\n";
} else if (!N->isLeaf() && N->getOperator()->getName() == "tglobaladdr")
{
OS << " SDOperand Tmp" << ResNo << " = " << Val << ";\n";
+ } else if (!N->isLeaf() && N->getOperator()->getName() == "tconstpool") {
+OS << " SDOperand Tmp" << ResNo << " = " << Val << ";\n";
} else if (N->isLeaf() && (CP = NodeGetComplexPattern(N, ISE))) {
std::string Fn = CP->getSelectFunc();
NumRes = CP->getNumOperands();
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