[llvm-branch-commits] [clang] [llvm] Split fmv and extensions (PR #92882)
https://github.com/tmatheson-arm edited https://github.com/llvm/llvm-project/pull/92882 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [clang] [llvm] [AArch64] Add a check for invalid default features (#104435) (PR #104752)
https://github.com/tmatheson-arm created
https://github.com/llvm/llvm-project/pull/104752
This adds a check that all ExtensionWithMArch which are marked as implied
features for an architecture are also present in the list of default features.
It doesn't make sense to have something mandatory but not on by default.
There were a number of existing cases that violated this rule, and some changes
to which features are mandatory (indicated by the Implies field).
This resulted in a bug where if a feature was marked as `Implies` but was not
added to `DefaultExt`, then for `-march=base_arch+nofeat` the Driver would
consider `feat` to have never been added and therefore would do nothing to
disable it (no `-target-feature -feat` would be added, but the backend would
enable the feature by default because of `Implies`). See
clang/test/Driver/aarch64-negative-modifiers-for-default-features.c.
Note that the processor definitions do not respect the architecture
DefaultExts. These apply only when specifying `-march=`. So when a feature is moved from `Implies` to `DefaultExts` on the
Architecture definition, the feature needs to be added to all processor
definitions (that are based on that architecture) in order to preserve the
existing behaviour. I have checked the TRMs for many cases (see specific commit
messages) but in other cases I have just kept the current behaviour and not
tried to fix it.
>From b523150d05242d9e00dc2dcf1694a1cf7dde088f Mon Sep 17 00:00:00 2001
From: Tomas Matheson
Date: Sat, 17 Aug 2024 13:36:40 +0100
Subject: [PATCH] [AArch64] Add a check for invalid default features (#104435)
This adds a check that all ExtensionWithMArch which are marked as
implied features for an architecture are also present in the list of
default features. It doesn't make sense to have something mandatory but
not on by default.
There were a number of existing cases that violated this rule, and some
changes to which features are mandatory (indicated by the Implies
field).
This resulted in a bug where if a feature was marked as `Implies` but
was not added to `DefaultExt`, then for `-march=base_arch+nofeat` the
Driver would consider `feat` to have never been added and therefore
would do nothing to disable it (no `-target-feature -feat` would be
added, but the backend would enable the feature by default because of
`Implies`). See
clang/test/Driver/aarch64-negative-modifiers-for-default-features.c.
Note that the processor definitions do not respect the architecture
DefaultExts. These apply only when specifying `-march=`. So when a feature is moved from `Implies` to `DefaultExts` on
the Architecture definition, the feature needs to be added to all
processor definitions (that are based on that architecture) in order to
preserve the existing behaviour. I have checked the TRMs for many cases
(see specific commit messages) but in other cases I have just kept the
current behaviour and not tried to fix it.
---
clang/test/CodeGen/aarch64-targetattr.c | 12 +--
...-negative-modifiers-for-default-features.c | 12 +++
clang/test/Driver/arm-sb.c| 2 +-
.../aarch64-apple-a12.c | 1 -
.../aarch64-apple-a13.c | 1 -
.../aarch64-apple-a14.c | 1 -
.../aarch64-apple-a15.c | 1 -
.../aarch64-apple-a16.c | 1 -
.../aarch64-apple-a17.c | 1 -
.../aarch64-apple-m4.c| 2 -
.../aarch64-cortex-r82.c | 1 -
.../aarch64-cortex-r82ae.c| 1 -
llvm/lib/Target/AArch64/AArch64Features.td| 19 ++--
llvm/lib/Target/AArch64/AArch64Processors.td | 46 +++--
llvm/test/MC/AArch64/arm64-system-encoding.s | 2 +-
llvm/test/MC/AArch64/armv8.5a-ssbs-error.s| 2 +-
llvm/test/MC/AArch64/armv8.5a-ssbs.s | 2 +-
.../MC/Disassembler/AArch64/armv8.5a-ssbs.txt | 2 +-
.../AArch64/basic-a64-instructions.txt| 2 +-
.../TargetParser/TargetParserTest.cpp | 97 +++
llvm/utils/TableGen/ARMTargetDefEmitter.cpp | 32 +-
21 files changed, 156 insertions(+), 84 deletions(-)
create mode 100644
clang/test/Driver/aarch64-negative-modifiers-for-default-features.c
diff --git a/clang/test/CodeGen/aarch64-targetattr.c
b/clang/test/CodeGen/aarch64-targetattr.c
index 4f891f938b6186..d6227be2ebef83 100644
--- a/clang/test/CodeGen/aarch64-targetattr.c
+++ b/clang/test/CodeGen/aarch64-targetattr.c
@@ -195,19 +195,19 @@ void minusarch() {}
// CHECK: attributes #[[ATTR0]] = { noinline nounwind optnone
"no-trapping-math"="true" "stack-protector-buffer-size"="8"
"target-features"="+crc,+fp-armv8,+lse,+neon,+ras,+rdm,+v8.1a,+v8.2a,+v8a" }
// CHECK: attributes #[[ATTR1]] = { noinline nounwind optnone
"no-trapping-math"="true" "stack-protector-buffer-size"="8"
"target-features"="+crc,+fp-armv8,+fullfp16,+lse,+neon,+ras,+rdm,+sve,+v8.1a,+v8.2a,+v8a"
}
// CHECK: attributes #[[AT
[llvm-branch-commits] [clang] [llvm] [AArch64] Add a check for invalid default features (#104435) (PR #104752)
https://github.com/tmatheson-arm milestoned https://github.com/llvm/llvm-project/pull/104752 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [clang] [llvm] [AArch64] Add a check for invalid default features (#104435) (PR #104752)
https://github.com/tmatheson-arm edited https://github.com/llvm/llvm-project/pull/104752 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [clang] [llvm] [AArch64] Add a check for invalid default features (PR #104752)
https://github.com/tmatheson-arm edited https://github.com/llvm/llvm-project/pull/104752 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [clang] [llvm] [AArch64] Add a check for invalid default features (PR #104752)
https://github.com/tmatheson-arm edited https://github.com/llvm/llvm-project/pull/104752 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [clang] [llvm] [AArch64] Add a check for invalid default features (PR #104752)
tmatheson-arm wrote: Yes both of those are correct. https://github.com/llvm/llvm-project/pull/104752 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [clang] [llvm] [AArch64] Add a check for invalid default features (PR #104752)
https://github.com/tmatheson-arm edited https://github.com/llvm/llvm-project/pull/104752 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [clang] [llvm] [AArch64] Fix a bug where user could not disable certain architecture features (PR #104752)
https://github.com/tmatheson-arm edited https://github.com/llvm/llvm-project/pull/104752 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [clang] [llvm] [AArch64] Fix a bug where user could not disable certain architecture features (PR #104752)
https://github.com/tmatheson-arm updated
https://github.com/llvm/llvm-project/pull/104752
>From b523150d05242d9e00dc2dcf1694a1cf7dde088f Mon Sep 17 00:00:00 2001
From: Tomas Matheson
Date: Sat, 17 Aug 2024 13:36:40 +0100
Subject: [PATCH 1/2] [AArch64] Add a check for invalid default features
(#104435)
This adds a check that all ExtensionWithMArch which are marked as
implied features for an architecture are also present in the list of
default features. It doesn't make sense to have something mandatory but
not on by default.
There were a number of existing cases that violated this rule, and some
changes to which features are mandatory (indicated by the Implies
field).
This resulted in a bug where if a feature was marked as `Implies` but
was not added to `DefaultExt`, then for `-march=base_arch+nofeat` the
Driver would consider `feat` to have never been added and therefore
would do nothing to disable it (no `-target-feature -feat` would be
added, but the backend would enable the feature by default because of
`Implies`). See
clang/test/Driver/aarch64-negative-modifiers-for-default-features.c.
Note that the processor definitions do not respect the architecture
DefaultExts. These apply only when specifying `-march=`. So when a feature is moved from `Implies` to `DefaultExts` on
the Architecture definition, the feature needs to be added to all
processor definitions (that are based on that architecture) in order to
preserve the existing behaviour. I have checked the TRMs for many cases
(see specific commit messages) but in other cases I have just kept the
current behaviour and not tried to fix it.
---
clang/test/CodeGen/aarch64-targetattr.c | 12 +--
...-negative-modifiers-for-default-features.c | 12 +++
clang/test/Driver/arm-sb.c| 2 +-
.../aarch64-apple-a12.c | 1 -
.../aarch64-apple-a13.c | 1 -
.../aarch64-apple-a14.c | 1 -
.../aarch64-apple-a15.c | 1 -
.../aarch64-apple-a16.c | 1 -
.../aarch64-apple-a17.c | 1 -
.../aarch64-apple-m4.c| 2 -
.../aarch64-cortex-r82.c | 1 -
.../aarch64-cortex-r82ae.c| 1 -
llvm/lib/Target/AArch64/AArch64Features.td| 19 ++--
llvm/lib/Target/AArch64/AArch64Processors.td | 46 +++--
llvm/test/MC/AArch64/arm64-system-encoding.s | 2 +-
llvm/test/MC/AArch64/armv8.5a-ssbs-error.s| 2 +-
llvm/test/MC/AArch64/armv8.5a-ssbs.s | 2 +-
.../MC/Disassembler/AArch64/armv8.5a-ssbs.txt | 2 +-
.../AArch64/basic-a64-instructions.txt| 2 +-
.../TargetParser/TargetParserTest.cpp | 97 +++
llvm/utils/TableGen/ARMTargetDefEmitter.cpp | 32 +-
21 files changed, 156 insertions(+), 84 deletions(-)
create mode 100644
clang/test/Driver/aarch64-negative-modifiers-for-default-features.c
diff --git a/clang/test/CodeGen/aarch64-targetattr.c
b/clang/test/CodeGen/aarch64-targetattr.c
index 4f891f938b6186..d6227be2ebef83 100644
--- a/clang/test/CodeGen/aarch64-targetattr.c
+++ b/clang/test/CodeGen/aarch64-targetattr.c
@@ -195,19 +195,19 @@ void minusarch() {}
// CHECK: attributes #[[ATTR0]] = { noinline nounwind optnone
"no-trapping-math"="true" "stack-protector-buffer-size"="8"
"target-features"="+crc,+fp-armv8,+lse,+neon,+ras,+rdm,+v8.1a,+v8.2a,+v8a" }
// CHECK: attributes #[[ATTR1]] = { noinline nounwind optnone
"no-trapping-math"="true" "stack-protector-buffer-size"="8"
"target-features"="+crc,+fp-armv8,+fullfp16,+lse,+neon,+ras,+rdm,+sve,+v8.1a,+v8.2a,+v8a"
}
// CHECK: attributes #[[ATTR2]] = { noinline nounwind optnone
"no-trapping-math"="true" "stack-protector-buffer-size"="8"
"target-features"="+crc,+fp-armv8,+fullfp16,+lse,+neon,+ras,+rdm,+sve,+sve2,+v8.1a,+v8.2a,+v8a"
}
-// CHECK: attributes #[[ATTR3]] = { noinline nounwind optnone
"no-trapping-math"="true" "stack-protector-buffer-size"="8"
"target-features"="+bf16,+complxnum,+crc,+dotprod,+fp-armv8,+fp16fml,+fullfp16,+i8mm,+jsconv,+lse,+neon,+pauth,+ras,+rcpc,+rdm,+sve,+sve2,+v8.1a,+v8.2a,+v8.3a,+v8.4a,+v8.5a,+v8.6a,+v8a"
}
-// CHECK: attributes #[[ATTR4]] = { noinline nounwind optnone
"no-trapping-math"="true" "stack-protector-buffer-size"="8"
"target-cpu"="cortex-a710"
"target-features"="+bf16,+complxnum,+crc,+dotprod,+ete,+flagm,+fp-armv8,+fp16fml,+fullfp16,+i8mm,+jsconv,+lse,+mte,+neon,+pauth,+perfmon,+ras,+rcpc,+rdm,+sb,+sve,+sve2,+sve2-bitperm,+trbe,+v8.1a,+v8.2a,+v8.3a,+v8.4a,+v8.5a,+v8a,+v9a"
}
+// CHECK: attributes #[[ATTR3]] = { noinline nounwind optnone
"no-trapping-math"="true" "stack-protector-buffer-size"="8"
"target-features"="+bf16,+bti,+ccidx,+complxnum,+crc,+dit,+dotprod,+flagm,+fp-armv8,+fp16fml,+fullfp16,+i8mm,+jsconv,+lse,+neon,+pauth,+predres,+ras,+rcpc,+rdm,+sb,+ssbs,+sve,+sve2,+v8.1a,+v8.2a,+v8.3a,+v8.4a,+v8.5a,+v8.6a,+v8a"
}
+// CHECK: attributes #[[ATTR4]] = { noinline nounwind optnone
"no-
[llvm-branch-commits] [clang] [llvm] [AArch64] Fix a bug where user could not disable certain architecture features (PR #104752)
https://github.com/tmatheson-arm updated
https://github.com/llvm/llvm-project/pull/104752
>From b523150d05242d9e00dc2dcf1694a1cf7dde088f Mon Sep 17 00:00:00 2001
From: Tomas Matheson
Date: Sat, 17 Aug 2024 13:36:40 +0100
Subject: [PATCH 1/3] [AArch64] Add a check for invalid default features
(#104435)
This adds a check that all ExtensionWithMArch which are marked as
implied features for an architecture are also present in the list of
default features. It doesn't make sense to have something mandatory but
not on by default.
There were a number of existing cases that violated this rule, and some
changes to which features are mandatory (indicated by the Implies
field).
This resulted in a bug where if a feature was marked as `Implies` but
was not added to `DefaultExt`, then for `-march=base_arch+nofeat` the
Driver would consider `feat` to have never been added and therefore
would do nothing to disable it (no `-target-feature -feat` would be
added, but the backend would enable the feature by default because of
`Implies`). See
clang/test/Driver/aarch64-negative-modifiers-for-default-features.c.
Note that the processor definitions do not respect the architecture
DefaultExts. These apply only when specifying `-march=`. So when a feature is moved from `Implies` to `DefaultExts` on
the Architecture definition, the feature needs to be added to all
processor definitions (that are based on that architecture) in order to
preserve the existing behaviour. I have checked the TRMs for many cases
(see specific commit messages) but in other cases I have just kept the
current behaviour and not tried to fix it.
---
clang/test/CodeGen/aarch64-targetattr.c | 12 +--
...-negative-modifiers-for-default-features.c | 12 +++
clang/test/Driver/arm-sb.c| 2 +-
.../aarch64-apple-a12.c | 1 -
.../aarch64-apple-a13.c | 1 -
.../aarch64-apple-a14.c | 1 -
.../aarch64-apple-a15.c | 1 -
.../aarch64-apple-a16.c | 1 -
.../aarch64-apple-a17.c | 1 -
.../aarch64-apple-m4.c| 2 -
.../aarch64-cortex-r82.c | 1 -
.../aarch64-cortex-r82ae.c| 1 -
llvm/lib/Target/AArch64/AArch64Features.td| 19 ++--
llvm/lib/Target/AArch64/AArch64Processors.td | 46 +++--
llvm/test/MC/AArch64/arm64-system-encoding.s | 2 +-
llvm/test/MC/AArch64/armv8.5a-ssbs-error.s| 2 +-
llvm/test/MC/AArch64/armv8.5a-ssbs.s | 2 +-
.../MC/Disassembler/AArch64/armv8.5a-ssbs.txt | 2 +-
.../AArch64/basic-a64-instructions.txt| 2 +-
.../TargetParser/TargetParserTest.cpp | 97 +++
llvm/utils/TableGen/ARMTargetDefEmitter.cpp | 32 +-
21 files changed, 156 insertions(+), 84 deletions(-)
create mode 100644
clang/test/Driver/aarch64-negative-modifiers-for-default-features.c
diff --git a/clang/test/CodeGen/aarch64-targetattr.c
b/clang/test/CodeGen/aarch64-targetattr.c
index 4f891f938b6186..d6227be2ebef83 100644
--- a/clang/test/CodeGen/aarch64-targetattr.c
+++ b/clang/test/CodeGen/aarch64-targetattr.c
@@ -195,19 +195,19 @@ void minusarch() {}
// CHECK: attributes #[[ATTR0]] = { noinline nounwind optnone
"no-trapping-math"="true" "stack-protector-buffer-size"="8"
"target-features"="+crc,+fp-armv8,+lse,+neon,+ras,+rdm,+v8.1a,+v8.2a,+v8a" }
// CHECK: attributes #[[ATTR1]] = { noinline nounwind optnone
"no-trapping-math"="true" "stack-protector-buffer-size"="8"
"target-features"="+crc,+fp-armv8,+fullfp16,+lse,+neon,+ras,+rdm,+sve,+v8.1a,+v8.2a,+v8a"
}
// CHECK: attributes #[[ATTR2]] = { noinline nounwind optnone
"no-trapping-math"="true" "stack-protector-buffer-size"="8"
"target-features"="+crc,+fp-armv8,+fullfp16,+lse,+neon,+ras,+rdm,+sve,+sve2,+v8.1a,+v8.2a,+v8a"
}
-// CHECK: attributes #[[ATTR3]] = { noinline nounwind optnone
"no-trapping-math"="true" "stack-protector-buffer-size"="8"
"target-features"="+bf16,+complxnum,+crc,+dotprod,+fp-armv8,+fp16fml,+fullfp16,+i8mm,+jsconv,+lse,+neon,+pauth,+ras,+rcpc,+rdm,+sve,+sve2,+v8.1a,+v8.2a,+v8.3a,+v8.4a,+v8.5a,+v8.6a,+v8a"
}
-// CHECK: attributes #[[ATTR4]] = { noinline nounwind optnone
"no-trapping-math"="true" "stack-protector-buffer-size"="8"
"target-cpu"="cortex-a710"
"target-features"="+bf16,+complxnum,+crc,+dotprod,+ete,+flagm,+fp-armv8,+fp16fml,+fullfp16,+i8mm,+jsconv,+lse,+mte,+neon,+pauth,+perfmon,+ras,+rcpc,+rdm,+sb,+sve,+sve2,+sve2-bitperm,+trbe,+v8.1a,+v8.2a,+v8.3a,+v8.4a,+v8.5a,+v8a,+v9a"
}
+// CHECK: attributes #[[ATTR3]] = { noinline nounwind optnone
"no-trapping-math"="true" "stack-protector-buffer-size"="8"
"target-features"="+bf16,+bti,+ccidx,+complxnum,+crc,+dit,+dotprod,+flagm,+fp-armv8,+fp16fml,+fullfp16,+i8mm,+jsconv,+lse,+neon,+pauth,+predres,+ras,+rcpc,+rdm,+sb,+ssbs,+sve,+sve2,+v8.1a,+v8.2a,+v8.3a,+v8.4a,+v8.5a,+v8.6a,+v8a"
}
+// CHECK: attributes #[[ATTR4]] = { noinline nounwind optnone
"no-
[llvm-branch-commits] [clang] [llvm] [AArch64] Fix a bug where user could not disable certain architecture features (PR #104752)
tmatheson-arm wrote: @tru is there still time to merge this into 19.x, or is there anything else I should do? I'm not familiar with the new process. https://github.com/llvm/llvm-project/pull/104752 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [llvm] 643e3c9 - [AArch64] Add BRB IALL and BRB INJ instructions
Author: Tomas Matheson
Date: 2021-01-06T12:10:22Z
New Revision: 643e3c90761f30194a76671065d221d3cb71a199
URL:
https://github.com/llvm/llvm-project/commit/643e3c90761f30194a76671065d221d3cb71a199
DIFF:
https://github.com/llvm/llvm-project/commit/643e3c90761f30194a76671065d221d3cb71a199.diff
LOG: [AArch64] Add BRB IALL and BRB INJ instructions
BRB IALL: Invalidate the Branch Record Buffer
BRB INJ: Branch Record Injection into the Branch Record Buffer
Parser changes based on work by Simon Tatham.
These are two-word mnemonics. The assembly parser works by special-casing
the mnemonic in order to parse the second word as a plain identifier token.
Reviewed by: MarkMurrayARM
Differential Revision: https://reviews.llvm.org/D93899
Added:
Modified:
llvm/lib/Target/AArch64/AArch64InstrInfo.td
llvm/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp
llvm/test/MC/AArch64/brbe.s
Removed:
diff --git a/llvm/lib/Target/AArch64/AArch64InstrInfo.td
b/llvm/lib/Target/AArch64/AArch64InstrInfo.td
index 6209f51b1631..efc38292842c 100644
--- a/llvm/lib/Target/AArch64/AArch64InstrInfo.td
+++ b/llvm/lib/Target/AArch64/AArch64InstrInfo.td
@@ -813,7 +813,21 @@ def WFET : RegInputSystemI<0b, 0b000, "wfet">;
def WFIT : RegInputSystemI<0b, 0b001, "wfit">;
}
+// Branch Record Buffer two-word mnemonic instructions
+class BRBEI op2, string keyword>
+: SimpleSystemI<0, (ins), "brb", keyword>, Sched<[WriteSys]> {
+ let Inst{31-8} = 0b11010101100101110010;
+ let Inst{7-5} = op2;
+ let Predicates = [HasBRBE];
}
+def BRB_IALL: BRBEI<0b100, "\tiall">;
+def BRB_INJ: BRBEI<0b101, "\tinj">;
+
+}
+
+// Allow uppercase and lowercase keyword arguments for BRB IALL and BRB INJ
+def : TokenAlias<"INJ", "inj">;
+def : TokenAlias<"IALL", "iall">;
// ARMv8.2-A Dot Product
let Predicates = [HasDotProd] in {
diff --git a/llvm/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp
b/llvm/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp
index 26e093bf4ce7..0916cf92640b 100644
--- a/llvm/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp
+++ b/llvm/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp
@@ -159,6 +159,7 @@ class AArch64AsmParser : public MCTargetAsmParser {
bool parseSymbolicImmVal(const MCExpr *&ImmVal);
bool parseNeonVectorList(OperandVector &Operands);
bool parseOptionalMulOperand(OperandVector &Operands);
+ bool parseKeywordOperand(OperandVector &Operands);
bool parseOperand(OperandVector &Operands, bool isCondCode,
bool invertCondCode);
bool parseImmExpr(int64_t &Out);
@@ -3701,6 +3702,17 @@ bool
AArch64AsmParser::parseOptionalMulOperand(OperandVector &Operands) {
return Error(getLoc(), "expected 'vl' or '#'");
}
+bool AArch64AsmParser::parseKeywordOperand(OperandVector &Operands) {
+ MCAsmParser &Parser = getParser();
+ auto Tok = Parser.getTok();
+ if (Tok.isNot(AsmToken::Identifier))
+return true;
+ Operands.push_back(AArch64Operand::CreateToken(Tok.getString(), false,
+ Tok.getLoc(), getContext()));
+ Parser.Lex();
+ return false;
+}
+
/// parseOperand - Parse a arm instruction operand. For now this parses the
/// operand regardless of the mnemonic.
bool AArch64AsmParser::parseOperand(OperandVector &Operands, bool isCondCode,
@@ -3765,6 +3777,11 @@ bool AArch64AsmParser::parseOperand(OperandVector
&Operands, bool isCondCode,
if (GotShift != MatchOperand_NoMatch)
return GotShift;
+// If this is a two-word mnemonic, parse its special keyword
+// operand as an identifier.
+if (Mnemonic == "brb")
+ return parseKeywordOperand(Operands);
+
// This was not a register so parse other operands that start with an
// identifier (like labels) as expressions and create them as immediates.
const MCExpr *IdVal;
diff --git a/llvm/test/MC/AArch64/brbe.s b/llvm/test/MC/AArch64/brbe.s
index 7b0dfe4955ad..f02017dae8e5 100644
--- a/llvm/test/MC/AArch64/brbe.s
+++ b/llvm/test/MC/AArch64/brbe.s
@@ -133,3 +133,17 @@ mrs x5, BRBTGT31_EL1
// CHECK: mrs x5, BRBTGT31_EL1// encoding: [0xc5,0x8f,0x31,0xd5]
// ERROR-NO-BRBE: [[@LINE-4]]:5: error: expected writable system register
// ERROR-NO-BRBE: [[@LINE-4]]:9: error: expected readable system register
+
+brb iall
+brb inj
+// CHECK: brb iall // encoding: [0x9f,0x72,0x09,0xd5]
+// CHECK: brb inj // encoding: [0xbf,0x72,0x09,0xd5]
+// ERROR-NO-BRBE: [[@LINE-4]]:1: error: instruction requires: brbe
+// ERROR-NO-BRBE: [[@LINE-4]]:1: error: instruction requires: brbe
+
+brb IALL
+brb INJ
+// CHECK: brb iall // encoding: [0x9f,0x72,0x09,0xd5]
+// CHECK: brb inj // encoding: [0xbf,0x72,0x09,0xd5]
+// ERROR-NO-BRBE: [[@LINE-4]]:1: error: instruction requires: brbe
+// ERROR-NO-BRBE: [[@LINE-4]]:1: error: instruction requires: brbe
___
llvm-branch-commits mail
[llvm-branch-commits] [llvm] release/20.x: [AArch64] PAUTH_PROLOGUE should not be duplicated with PAuthLR (#124775) (PR #125230)
https://github.com/tmatheson-arm approved this pull request. https://github.com/llvm/llvm-project/pull/125230 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [llvm] [tablegen] Implement multiple outputs for patterns (PR #123775)
https://github.com/tmatheson-arm updated
https://github.com/llvm/llvm-project/pull/123775
>From 85c7ec7fee92ba634f3d2bec502eab94d4fbf18e Mon Sep 17 00:00:00 2001
From: Tomas Matheson
Date: Fri, 9 Feb 2024 15:56:02 +
Subject: [PATCH 1/5] Add TreePattern constructor that takes multiple patterns
---
llvm/utils/TableGen/Common/CodeGenDAGPatterns.cpp | 8
llvm/utils/TableGen/Common/CodeGenDAGPatterns.h | 4
2 files changed, 12 insertions(+)
diff --git a/llvm/utils/TableGen/Common/CodeGenDAGPatterns.cpp
b/llvm/utils/TableGen/Common/CodeGenDAGPatterns.cpp
index b95fe4eedda83e..5a9aec2ed7e5e5 100644
--- a/llvm/utils/TableGen/Common/CodeGenDAGPatterns.cpp
+++ b/llvm/utils/TableGen/Common/CodeGenDAGPatterns.cpp
@@ -2800,6 +2800,14 @@ TreePattern::TreePattern(const Record *TheRec,
TreePatternNodePtr Pat,
Trees.push_back(Pat);
}
+TreePattern::TreePattern(Record *TheRec,
+ const std::vector &Pats,
+ bool isInput, CodeGenDAGPatterns &cdp)
+: TheRecord(TheRec), CDP(cdp), isInputPattern(isInput), HasError(false),
+ Infer(*this) {
+ Trees = Pats;
+}
+
void TreePattern::error(const Twine &Msg) {
if (HasError)
return;
diff --git a/llvm/utils/TableGen/Common/CodeGenDAGPatterns.h
b/llvm/utils/TableGen/Common/CodeGenDAGPatterns.h
index f8c39172938256..d06623c743fe15 100644
--- a/llvm/utils/TableGen/Common/CodeGenDAGPatterns.h
+++ b/llvm/utils/TableGen/Common/CodeGenDAGPatterns.h
@@ -925,8 +925,12 @@ class TreePattern {
CodeGenDAGPatterns &ise);
TreePattern(const Record *TheRec, const DagInit *Pat, bool isInput,
CodeGenDAGPatterns &ise);
+ /// Construct from a single pattern
TreePattern(const Record *TheRec, TreePatternNodePtr Pat, bool isInput,
CodeGenDAGPatterns &ise);
+ /// Construct from multiple patterns
+ TreePattern(Record *TheRec, const std::vector &Pat,
+ bool isInput, CodeGenDAGPatterns &ise);
/// getTrees - Return the tree patterns which corresponds to this pattern.
///
>From daf6bcf1af8600eff9876e366c4c9334f30df100 Mon Sep 17 00:00:00 2001
From: Tomas Matheson
Date: Fri, 9 Feb 2024 15:57:38 +
Subject: [PATCH 2/5] Add TreePattern::hasProperTypeByHwMode
Change-Id: I3ac2e64b86233dd4c8b4f7f6effa50ed29759f25
---
llvm/utils/TableGen/Common/CodeGenDAGPatterns.cpp | 6 ++
llvm/utils/TableGen/Common/CodeGenDAGPatterns.h | 2 ++
2 files changed, 8 insertions(+)
diff --git a/llvm/utils/TableGen/Common/CodeGenDAGPatterns.cpp
b/llvm/utils/TableGen/Common/CodeGenDAGPatterns.cpp
index 5a9aec2ed7e5e5..96a98c2bac0250 100644
--- a/llvm/utils/TableGen/Common/CodeGenDAGPatterns.cpp
+++ b/llvm/utils/TableGen/Common/CodeGenDAGPatterns.cpp
@@ -2816,6 +2816,12 @@ void TreePattern::error(const Twine &Msg) {
HasError = true;
}
+bool TreePattern::hasProperTypeByHwMode() const {
+ return llvm::any_of(getTrees(),
+ [](auto &T) { return T->hasProperTypeByHwMode(); });
+}
+
+
void TreePattern::ComputeNamedNodes() {
for (TreePatternNodePtr &Tree : Trees)
ComputeNamedNodes(*Tree);
diff --git a/llvm/utils/TableGen/Common/CodeGenDAGPatterns.h
b/llvm/utils/TableGen/Common/CodeGenDAGPatterns.h
index d06623c743fe15..3fdb70a91544e1 100644
--- a/llvm/utils/TableGen/Common/CodeGenDAGPatterns.h
+++ b/llvm/utils/TableGen/Common/CodeGenDAGPatterns.h
@@ -988,6 +988,8 @@ class TreePattern {
TypeInfer &getInfer() { return Infer; }
+ bool hasProperTypeByHwMode() const;
+
void print(raw_ostream &OS) const;
void dump() const;
>From 0d2594fac0c3eb8b3bd3e43d62cd58ad4afb7c8c Mon Sep 17 00:00:00 2001
From: Tomas Matheson
Date: Sat, 10 Feb 2024 11:21:09 +
Subject: [PATCH 3/5] Implement multiple output patterns
See also D154945. It took me a while to track down the source of the
problems with the existing patterns.
Tablegen patterns for instrucion selection can generate multiple
instructions, but only if there is a data dependency between them so
that they can be expressed as a DAG. For example, something like:
(store (load %src), %dst)
For some patterns, we might want to generate a sequence of instructions
which do not have a data dependency. For example on AArch64 some atomic
instructions are implemented like this:
LDP %ptr
DMB ISH
Currently, sequences like this can not be selected with tablegen
patterns. To work around this we need to do custom selection, which has
several disadvantages compared to using patterns, such as needing
separate implementations for SelectionDAG and GlobalISel.
This patch adds basic support for tablegen Patterns which have a list
of output instructions. Pattern already has the ability to express this
but it looks like it was never implemented.
Multiple result instructions in an output pattern will be chained
together.
The GlobalISel pattern importer will skip these patterns for now. I
intend to implement this soon.
---
.../dag-isel-multiple-instructions.td | 204
[llvm-branch-commits] [llvm] [tablegen] Implement multiple outputs for patterns (PR #123775)
https://github.com/tmatheson-arm created
https://github.com/llvm/llvm-project/pull/123775
None
>From 85c7ec7fee92ba634f3d2bec502eab94d4fbf18e Mon Sep 17 00:00:00 2001
From: Tomas Matheson
Date: Fri, 9 Feb 2024 15:56:02 +
Subject: [PATCH 1/4] Add TreePattern constructor that takes multiple patterns
---
llvm/utils/TableGen/Common/CodeGenDAGPatterns.cpp | 8
llvm/utils/TableGen/Common/CodeGenDAGPatterns.h | 4
2 files changed, 12 insertions(+)
diff --git a/llvm/utils/TableGen/Common/CodeGenDAGPatterns.cpp
b/llvm/utils/TableGen/Common/CodeGenDAGPatterns.cpp
index b95fe4eedda83e..5a9aec2ed7e5e5 100644
--- a/llvm/utils/TableGen/Common/CodeGenDAGPatterns.cpp
+++ b/llvm/utils/TableGen/Common/CodeGenDAGPatterns.cpp
@@ -2800,6 +2800,14 @@ TreePattern::TreePattern(const Record *TheRec,
TreePatternNodePtr Pat,
Trees.push_back(Pat);
}
+TreePattern::TreePattern(Record *TheRec,
+ const std::vector &Pats,
+ bool isInput, CodeGenDAGPatterns &cdp)
+: TheRecord(TheRec), CDP(cdp), isInputPattern(isInput), HasError(false),
+ Infer(*this) {
+ Trees = Pats;
+}
+
void TreePattern::error(const Twine &Msg) {
if (HasError)
return;
diff --git a/llvm/utils/TableGen/Common/CodeGenDAGPatterns.h
b/llvm/utils/TableGen/Common/CodeGenDAGPatterns.h
index f8c39172938256..d06623c743fe15 100644
--- a/llvm/utils/TableGen/Common/CodeGenDAGPatterns.h
+++ b/llvm/utils/TableGen/Common/CodeGenDAGPatterns.h
@@ -925,8 +925,12 @@ class TreePattern {
CodeGenDAGPatterns &ise);
TreePattern(const Record *TheRec, const DagInit *Pat, bool isInput,
CodeGenDAGPatterns &ise);
+ /// Construct from a single pattern
TreePattern(const Record *TheRec, TreePatternNodePtr Pat, bool isInput,
CodeGenDAGPatterns &ise);
+ /// Construct from multiple patterns
+ TreePattern(Record *TheRec, const std::vector &Pat,
+ bool isInput, CodeGenDAGPatterns &ise);
/// getTrees - Return the tree patterns which corresponds to this pattern.
///
>From daf6bcf1af8600eff9876e366c4c9334f30df100 Mon Sep 17 00:00:00 2001
From: Tomas Matheson
Date: Fri, 9 Feb 2024 15:57:38 +
Subject: [PATCH 2/4] Add TreePattern::hasProperTypeByHwMode
Change-Id: I3ac2e64b86233dd4c8b4f7f6effa50ed29759f25
---
llvm/utils/TableGen/Common/CodeGenDAGPatterns.cpp | 6 ++
llvm/utils/TableGen/Common/CodeGenDAGPatterns.h | 2 ++
2 files changed, 8 insertions(+)
diff --git a/llvm/utils/TableGen/Common/CodeGenDAGPatterns.cpp
b/llvm/utils/TableGen/Common/CodeGenDAGPatterns.cpp
index 5a9aec2ed7e5e5..96a98c2bac0250 100644
--- a/llvm/utils/TableGen/Common/CodeGenDAGPatterns.cpp
+++ b/llvm/utils/TableGen/Common/CodeGenDAGPatterns.cpp
@@ -2816,6 +2816,12 @@ void TreePattern::error(const Twine &Msg) {
HasError = true;
}
+bool TreePattern::hasProperTypeByHwMode() const {
+ return llvm::any_of(getTrees(),
+ [](auto &T) { return T->hasProperTypeByHwMode(); });
+}
+
+
void TreePattern::ComputeNamedNodes() {
for (TreePatternNodePtr &Tree : Trees)
ComputeNamedNodes(*Tree);
diff --git a/llvm/utils/TableGen/Common/CodeGenDAGPatterns.h
b/llvm/utils/TableGen/Common/CodeGenDAGPatterns.h
index d06623c743fe15..3fdb70a91544e1 100644
--- a/llvm/utils/TableGen/Common/CodeGenDAGPatterns.h
+++ b/llvm/utils/TableGen/Common/CodeGenDAGPatterns.h
@@ -988,6 +988,8 @@ class TreePattern {
TypeInfer &getInfer() { return Infer; }
+ bool hasProperTypeByHwMode() const;
+
void print(raw_ostream &OS) const;
void dump() const;
>From 0d2594fac0c3eb8b3bd3e43d62cd58ad4afb7c8c Mon Sep 17 00:00:00 2001
From: Tomas Matheson
Date: Sat, 10 Feb 2024 11:21:09 +
Subject: [PATCH 3/4] Implement multiple output patterns
See also D154945. It took me a while to track down the source of the
problems with the existing patterns.
Tablegen patterns for instrucion selection can generate multiple
instructions, but only if there is a data dependency between them so
that they can be expressed as a DAG. For example, something like:
(store (load %src), %dst)
For some patterns, we might want to generate a sequence of instructions
which do not have a data dependency. For example on AArch64 some atomic
instructions are implemented like this:
LDP %ptr
DMB ISH
Currently, sequences like this can not be selected with tablegen
patterns. To work around this we need to do custom selection, which has
several disadvantages compared to using patterns, such as needing
separate implementations for SelectionDAG and GlobalISel.
This patch adds basic support for tablegen Patterns which have a list
of output instructions. Pattern already has the ability to express this
but it looks like it was never implemented.
Multiple result instructions in an output pattern will be chained
together.
The GlobalISel pattern importer will skip these patterns for now. I
intend to implement this soon.
---
.../dag-isel-multiple-instructions.td | 204 ++
[llvm-branch-commits] [llvm] [AArch64][llvm] Unify AArch64 tests into a single file (3/4) (NFC) (PR #146330)
@@ -1,592 +1,697 @@ -// RUN: not llvm-mc -triple aarch64-none-linux-gnu -show-encoding -mattr=+the -mattr=+d128 < %s | FileCheck %s -// RUN: not llvm-mc -triple aarch64-none-linux-gnu -show-encoding -mattr=+v8.9a -mattr=+the -mattr=+d128 < %s | FileCheck %s -// RUN: not llvm-mc -triple aarch64-none-linux-gnu -show-encoding -mattr=+v9.4a -mattr=+the -mattr=+d128 < %s | FileCheck %s +// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+the,+d128 < %s \ +// RUN:| FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST +// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+the,+d128,v8.9a < %s \ +// RUN:| FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST +// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+the,+d128,v9.4a < %s \ +// RUN:| FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST +// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \ +// RUN:| FileCheck %s --check-prefixes=CHECK-ERROR +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+the,+d128 < %s \ +// RUN:| llvm-objdump -d --mattr=+the,+d128 - | FileCheck %s --check-prefix=CHECK-INST +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+the,+d128 < %s \ +// RUN: | llvm-objdump -d --mattr=-the,-d128 - | FileCheck %s --check-prefix=CHECK-UNKNOWN +// Disassemble encoding and check the re-encoding (-show-encoding) matches. +// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+the,+d128 < %s \ +// RUN:| sed '/.text/d' | sed 's/.*encoding: //g' \ +// RUN:| llvm-mc -triple=aarch64 -mattr=+the,+d128 -disassemble -show-encoding \ +// RUN:| FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST -// RUN: not llvm-mc -triple aarch64-none-linux-gnu < %s 2>&1 | FileCheck --check-prefix=ERROR-NO-THE %s -// RUN: not llvm-mc -triple aarch64-none-linux-gnu -mattr=+v8.9a < %s 2>&1 | FileCheck --check-prefix=ERROR-NO-THE %s -// RUN: not llvm-mc -triple aarch64-none-linux-gnu -mattr=+v9.4a < %s 2>&1 | FileCheck --check-prefix=ERROR-NO-THE %s -// RUN: not llvm-mc -triple aarch64-none-linux-gnu -mattr=+the < %s 2>&1 | FileCheck --check-prefix=ERROR-NO-D128 %s -// RUN: not llvm-mc -triple aarch64-none-linux-gnu -mattr=+v8.9a -mattr=+the < %s 2>&1 | FileCheck --check-prefix=ERROR-NO-D128 %s -// RUN: not llvm-mc -triple aarch64-none-linux-gnu -mattr=+v9.4a -mattr=+the < %s 2>&1 | FileCheck --check-prefix=ERROR-NO-D128 %s +mrs x3, RCWMASK_EL1 +// CHECK-INST: mrs x3, RCWMASK_EL1 +// CHECK-ENCODING: encoding: [0xc3,0xd0,0x38,0xd5] +// CHECK-ERROR: error: expected readable system register +// CHECK-UNKNOWN: d538d0c3 mrs x3, S3_0_C13_C0_6 -// RUN: not llvm-mc -triple aarch64-none-linux-gnu -show-encoding -mattr=+the -mattr=+d128 < %s 2>&1 | FileCheck --check-prefix=ERROR-NO-ZXR %s +msr RCWMASK_EL1, x1 +// CHECK-INST: msr RCWMASK_EL1, x1 +// CHECK-ENCODING: encoding: [0xc1,0xd0,0x18,0xd5] +// CHECK-ERROR: error: expected writable system register or pstate +// CHECK-UNKNOWN: d518d0c1 msr S3_0_C13_C0_6, x1 -mrs x3, RCWMASK_EL1 -// CHECK: mrs x3, RCWMASK_EL1 // encoding: [0xc3,0xd0,0x38,0xd5] -// ERROR-NO-THE: [[@LINE-2]]:21: error: expected readable system register -msr RCWMASK_EL1, x1 -// CHECK: msr RCWMASK_EL1, x1 // encoding: [0xc1,0xd0,0x18,0xd5] -// ERROR-NO-THE: [[@LINE-2]]:17: error: expected writable system register or pstate -mrs x3, RCWSMASK_EL1 -// CHECK: mrs x3, RCWSMASK_EL1 // encoding: [0x63,0xd0,0x38,0xd5] -// ERROR-NO-THE: [[@LINE-2]]:21: error: expected readable system register -msr RCWSMASK_EL1, x1 -// CHECK: msr RCWSMASK_EL1, x1 // encoding: [0x61,0xd0,0x18,0xd5] -// ERROR-NO-THE: [[@LINE-2]]:17: error: expected writable system register or pstate +mrs x3, RCWSMASK_EL1 +// CHECK-INST: mrs x3, RCWSMASK_EL1 +// CHECK-ENCODING: encoding: [0x63,0xd0,0x38,0xd5] +// CHECK-ERROR: error: expected readable system register +// CHECK-UNKNOWN: d538d063 mrs x3, S3_0_C13_C0_3 +msr RCWSMASK_EL1, x1 +// CHECK-INST: msr RCWSMASK_EL1, x1 +// CHECK-ENCODING: encoding: [0x61,0xd0,0x18,0xd5] +// CHECK-ERROR: error: expected writable system register or pstate +// CHECK-UNKNOWN: d518d061 msr S3_0_C13_C0_3, x1 -rcwcas x0, x1, [x4] -// CHECK: rcwcas x0, x1, [x4] // encoding: [0x81,0x08,0x20,0x19] -// ERROR-NO-THE: [[@LINE-2]]:13: error: instruction requires: the -rcwcasa x0, x1, [x4] -// CHECK: rcwcasa x0, x1, [x4] // encoding: [0x81,0x08,0xa0,0x19] -// ERROR-NO-THE: [[@LINE-2]]:13: error: instruction requires: the -rcwcasal x0, x1, [x4] -// CHECK: rcwcasal x0, x1, [x4] // encoding: [0x81,0x08,0xe0,0x19] -// ERROR-NO-THE: [[@LINE-2]]:13: error: instruction requires: the -rcwcasl x0, x1, [x4] -// CHECK: rcwcasl x0, x1, [x4] // encoding: [0x81,0x08,0x60,0x19] -// ERROR-NO-THE: [[@LINE-2]]:13: error: instruction requires: the
[llvm-branch-commits] [llvm] [AArch64][llvm] Unify AArch64 tests into a single file (3/4) (NFC) (PR #146330)
@@ -16,28 +16,41 @@ // RUN: llvm-mc -show-encoding -triple aarch64-none-elf -mattr=+v9.3a,-clrbhb < %s | FileCheck %s --check-prefix=HINT_22 // Optional, off by default, manually enabled -// RUN: llvm-mc -show-encoding -triple aarch64-none-elf -mattr=+clrbhb < %s | FileCheck %s --check-prefix=CLRBHB -// RUN: llvm-mc -show-encoding -triple aarch64-none-elf -mattr=+v8a,+clrbhb < %s | FileCheck %s --check-prefix=CLRBHB -// RUN: llvm-mc -show-encoding -triple aarch64-none-elf -mattr=+v8.8a,+clrbhb < %s | FileCheck %s --check-prefix=CLRBHB -// RUN: llvm-mc -show-encoding -triple aarch64-none-elf -mattr=+v9a,+clrbhb < %s | FileCheck %s --check-prefix=CLRBHB -// RUN: llvm-mc -show-encoding -triple aarch64-none-elf -mattr=+v9.3a,+clrbhb < %s | FileCheck %s --check-prefix=CLRBHB +// RUN: llvm-mc -show-encoding -triple aarch64-none-elf -mattr=+clrbhb < %s | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST +// RUN: llvm-mc -show-encoding -triple aarch64-none-elf -mattr=+v8a,+clrbhb < %s | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST +// RUN: llvm-mc -show-encoding -triple aarch64-none-elf -mattr=+v8.8a,+clrbhb < %s | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST +// RUN: llvm-mc -show-encoding -triple aarch64-none-elf -mattr=+v9a,+clrbhb < %s | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST +// RUN: llvm-mc -show-encoding -triple aarch64-none-elf -mattr=+v9.3a,+clrbhb < %s | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST tmatheson-arm wrote: Why keeping a different test format for CLRBHB? https://github.com/llvm/llvm-project/pull/146330 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [llvm] [AArch64][llvm] Unify AArch64 tests into a single file (2/4) (NFC) (PR #146329)
@@ -1,55 +1,117 @@ -// RUN: llvm-mc -triple aarch64-none-linux-gnu -show-encoding -mattr=+mec < %s | FileCheck %s -// RUN: not llvm-mc -triple aarch64-none-linux-gnu < %s 2>&1 | FileCheck --check-prefix=CHECK-NO-MEC %s - - mrs x0, MECIDR_EL2 -// CHECK: mrs x0, MECIDR_EL2 // encoding: [0xe0,0xa8,0x3c,0xd5] -// CHECK-NO-MEC: [[@LINE-2]]:19: error: expected readable system register - mrs x0, MECID_P0_EL2 -// CHECK: mrs x0, MECID_P0_EL2 // encoding: [0x00,0xa8,0x3c,0xd5] -// CHECK-NO-MEC: [[@LINE-2]]:19: error: expected readable system register - mrs x0, MECID_A0_EL2 -// CHECK: mrs x0, MECID_A0_EL2 // encoding: [0x20,0xa8,0x3c,0xd5] -// CHECK-NO-MEC: [[@LINE-2]]:19: error: expected readable system register - mrs x0, MECID_P1_EL2 -// CHECK: mrs x0, MECID_P1_EL2 // encoding: [0x40,0xa8,0x3c,0xd5] -// CHECK-NO-MEC: [[@LINE-2]]:19: error: expected readable system register - mrs x0, MECID_A1_EL2 -// CHECK: mrs x0, MECID_A1_EL2 // encoding: [0x60,0xa8,0x3c,0xd5] -// CHECK-NO-MEC: [[@LINE-2]]:19: error: expected readable system register - mrs x0, VMECID_P_EL2 -// CHECK: mrs x0, VMECID_P_EL2 // encoding: [0x00,0xa9,0x3c,0xd5] -// CHECK-NO-MEC: [[@LINE-2]]:19: error: expected readable system register - mrs x0, VMECID_A_EL2 -// CHECK: mrs x0, VMECID_A_EL2 // encoding: [0x20,0xa9,0x3c,0xd5] -// CHECK-NO-MEC: [[@LINE-2]]:19: error: expected readable system register - mrs x0, MECID_RL_A_EL3 -// CHECK: mrs x0, MECID_RL_A_EL3 // encoding: [0x20,0xaa,0x3e,0xd5] -// CHECK-NO-MEC: [[@LINE-2]]:19: error: expected readable system register - msr MECID_P0_EL2,x0 -// CHECK: msr MECID_P0_EL2, x0 // encoding: [0x00,0xa8,0x1c,0xd5] -// CHECK-NO-MEC: [[@LINE-2]]:15: error: expected writable system register or pstate - msr MECID_A0_EL2,x0 -// CHECK: msr MECID_A0_EL2, x0 // encoding: [0x20,0xa8,0x1c,0xd5] -// CHECK-NO-MEC: [[@LINE-2]]:15: error: expected writable system register or pstate - msr MECID_P1_EL2,x0 -// CHECK: msr MECID_P1_EL2, x0 // encoding: [0x40,0xa8,0x1c,0xd5] -// CHECK-NO-MEC: [[@LINE-2]]:15: error: expected writable system register or pstate - msr MECID_A1_EL2,x0 -// CHECK: msr MECID_A1_EL2, x0 // encoding: [0x60,0xa8,0x1c,0xd5] -// CHECK-NO-MEC: [[@LINE-2]]:15: error: expected writable system register or pstate - msr VMECID_P_EL2, x0 -// CHECK: msr VMECID_P_EL2, x0 // encoding: [0x00,0xa9,0x1c,0xd5] -// CHECK-NO-MEC: [[@LINE-2]]:15: error: expected writable system register or pstate - msr VMECID_A_EL2, x0 -// CHECK: msr VMECID_A_EL2, x0 // encoding: [0x20,0xa9,0x1c,0xd5] -// CHECK-NO-MEC: [[@LINE-2]]:15: error: expected writable system register or pstate - msr MECID_RL_A_EL3, x0 -// CHECK: msr MECID_RL_A_EL3, x0 // encoding: [0x20,0xaa,0x1e,0xd5] -// CHECK-NO-MEC: [[@LINE-2]]:15: error: expected writable system register or pstate - - dc cigdpae, x0 -// CHECK: dc cigdpae, x0 // encoding: [0xe0,0x7e,0x0c,0xd5] -// CHECK-NO-MEC: [[@LINE-2]]:14: error: DC CIGDPAE requires: mec - dc cipae, x0 -// CHECK: dc cipae, x0 // encoding: [0x00,0x7e,0x0c,0xd5] -// CHECK-NO-MEC: [[@LINE-2]]:14: error: DC CIPAE requires: mec +// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+mec < %s \ +// RUN:| FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST +// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \ +// RUN:| FileCheck %s --check-prefixes=CHECK-ERROR +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+mec < %s \ +// RUN:| llvm-objdump -d --mattr=+mec --no-print-imm-hex - | FileCheck %s --check-prefix=CHECK-INST +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+mec < %s \ +// RUN: | llvm-objdump -d --mattr=-mec --no-print-imm-hex - | FileCheck %s --check-prefix=CHECK-UNKNOWN +// Disassemble encoding and check the re-encoding (-show-encoding) matches. +// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+mec < %s \ +// RUN:| sed '/.text/d' | sed 's/.*encoding: //g' \ +// RUN:| llvm-mc -triple=aarch64 -mattr=+mec -disassemble -show-encoding \ +// RUN:| FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST + + + +mrs x0, MECIDR_EL2 +// CHECK-INST: mrs x0, MECIDR_EL2 +// CHECK-ENCODING: encoding: [0xe0,0xa8,0x3c,0xd5] +// CHECK-ERROR: error: expected readable system register +// CHECK-UNKNOWN: d53ca8e0 mrs x0, S3_4_C10_C8_7 + +mrs x0, MECID_P0_EL2 +// CHECK-INST: mrs x0, MECID_P0_EL2 +// CHECK-ENCODING: encoding: [0x00,0xa8,0x3c,0xd5] +// CHECK-ERROR: error: expected readable system register +// CHECK-UNKNOWN: d53ca800 mrs x0, S3_4_C10_C8_0 + +mrs x0, MECID_A0_EL2 +// CHECK-INST: mrs x0, MECID_A0_EL2 +// CHECK-ENCODING: encoding: [0x20,0xa8,0x3c,0xd5] +// CHECK-ERROR: error: expected readable system register +// CHECK-UNKNOWN: d53ca820 mrs
[llvm-branch-commits] [llvm] [AArch64][llvm] Unify AArch64 tests into a single file (2/4) (NFC) (PR #146329)
@@ -1,115 +1,203 @@ -// RUN: llvm-mc -triple aarch64 -mattr +gcs -show-encoding %s | FileCheck %s -// RUN: not llvm-mc -triple aarch64 -show-encoding %s 2>%t | FileCheck %s --check-prefix=NO-GCS -// RUN: FileCheck --check-prefix=ERROR-NO-GCS %s < %t +// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+gcs < %s \ +// RUN:| FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST +// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \ +// RUN:| FileCheck %s --check-prefixes=CHECK-ERROR +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+gcs < %s \ +// RUN:| llvm-objdump -d --mattr=+gcs --no-print-imm-hex - | FileCheck %s --check-prefix=CHECK-INST +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+gcs < %s \ +// RUN: | llvm-objdump -d --mattr=-gcs --no-print-imm-hex - | FileCheck %s --check-prefix=CHECK-UNKNOWN +// Disassemble encoding and check the re-encoding (-show-encoding) matches. +// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+gcs < %s \ +// RUN:| sed '/.text/d' | sed 's/.*encoding: //g' \ +// RUN:| llvm-mc -triple=aarch64 -mattr=+gcs -disassemble -show-encoding \ +// RUN:| FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST + + msr GCSCR_EL1, x0 +// CHECK-INST: msr GCSCR_EL1, x0 +// CHECK-ENCODING: encoding: [0x00,0x25,0x18,0xd5] +// CHECK-UNKNOWN: d5182500 msr GCSCR_EL1, x0 + mrs x1, GCSCR_EL1 -// CHECK: msr GCSCR_EL1, x0 // encoding: [0x00,0x25,0x18,0xd5] -// CHECK: mrs x1, GCSCR_EL1 // encoding: [0x01,0x25,0x38,0xd5] +// CHECK-INST: mrs x1, GCSCR_EL1 +// CHECK-ENCODING: encoding: [0x01,0x25,0x38,0xd5] +// CHECK-UNKNOWN: d5382501 mrs x1, GCSCR_EL1 msr GCSPR_EL1, x2 +// CHECK-INST: msr GCSPR_EL1, x2 +// CHECK-ENCODING: encoding: [0x22,0x25,0x18,0xd5] +// CHECK-UNKNOWN: d5182522 msr GCSPR_EL1, x2 + mrs x3, GCSPR_EL1 -// CHECK: msr GCSPR_EL1, x2 // encoding: [0x22,0x25,0x18,0xd5] -// CHECK: mrs x3, GCSPR_EL1 // encoding: [0x23,0x25,0x38,0xd5] +// CHECK-INST: mrs x3, GCSPR_EL1 +// CHECK-ENCODING: encoding: [0x23,0x25,0x38,0xd5] +// CHECK-UNKNOWN: d5382523 mrs x3, GCSPR_EL1 msr GCSCRE0_EL1, x4 +// CHECK-INST: msr GCSCRE0_EL1, x4 +// CHECK-ENCODING: encoding: [0x44,0x25,0x18,0xd5] +// CHECK-UNKNOWN: d5182544 msr GCSCRE0_EL1, x4 + mrs x5, GCSCRE0_EL1 -// CHECK: msr GCSCRE0_EL1, x4 // encoding: [0x44,0x25,0x18,0xd5] -// CHECK: mrs x5, GCSCRE0_EL1 // encoding: [0x45,0x25,0x38,0xd5] +// CHECK-INST: mrs x5, GCSCRE0_EL1 +// CHECK-ENCODING: encoding: [0x45,0x25,0x38,0xd5] +// CHECK-UNKNOWN: d5382545 mrs x5, GCSCRE0_EL1 msr GCSPR_EL0, x6 +// CHECK-INST: msr GCSPR_EL0, x6 +// CHECK-ENCODING: encoding: [0x26,0x25,0x1b,0xd5] +// CHECK-UNKNOWN: d51b2526 msr GCSPR_EL0, x6 + mrs x7, GCSPR_EL0 -// CHECK: msr GCSPR_EL0, x6 // encoding: [0x26,0x25,0x1b,0xd5] -// CHECK: mrs x7, GCSPR_EL0 // encoding: [0x27,0x25,0x3b,0xd5] +// CHECK-INST: mrs x7, GCSPR_EL0 +// CHECK-ENCODING: encoding: [0x27,0x25,0x3b,0xd5] +// CHECK-UNKNOWN: d53b2527 mrs x7, GCSPR_EL0 msr GCSCR_EL2, x10 +// CHECK-INST: msr GCSCR_EL2, x10 +// CHECK-ENCODING: encoding: [0x0a,0x25,0x1c,0xd5] +// CHECK-UNKNOWN: d51c250a msr GCSCR_EL2, x10 + mrs x11, GCSCR_EL2 -// CHECK: msr GCSCR_EL2, x10 // encoding: [0x0a,0x25,0x1c,0xd5] -// CHECK: mrs x11, GCSCR_EL2 // encoding: [0x0b,0x25,0x3c,0xd5] +// CHECK-INST: mrs x11, GCSCR_EL2 +// CHECK-ENCODING: encoding: [0x0b,0x25,0x3c,0xd5] +// CHECK-UNKNOWN: d53c250b mrs x11, GCSCR_EL2 msr GCSPR_EL2, x12 +// CHECK-INST: msr GCSPR_EL2, x12 +// CHECK-ENCODING: encoding: [0x2c,0x25,0x1c,0xd5] +// CHECK-UNKNOWN: d51c252c msr GCSPR_EL2, x12 + mrs x13, GCSPR_EL2 -// CHECK: msr GCSPR_EL2, x12 // encoding: [0x2c,0x25,0x1c,0xd5] -// CHECK: mrs x13, GCSPR_EL2 // encoding: [0x2d,0x25,0x3c,0xd5] +// CHECK-INST: mrs x13, GCSPR_EL2 +// CHECK-ENCODING: encoding: [0x2d,0x25,0x3c,0xd5] +// CHECK-UNKNOWN: d53c252d mrs x13, GCSPR_EL2 msr GCSCR_EL12, x14 +// CHECK-INST: msr GCSCR_EL12, x14 +// CHECK-ENCODING: encoding: [0x0e,0x25,0x1d,0xd5] +// CHECK-UNKNOWN: d51d250e msr GCSCR_EL12, x14 + mrs x15, GCSCR_EL12 -// CHECK: msr GCSCR_EL12, x14 // encoding: [0x0e,0x25,0x1d,0xd5] -// CHECK: mrs x15, GCSCR_EL12 // encoding: [0x0f,0x25,0x3d,0xd5] +// CHECK-INST: mrs x15, GCSCR_EL12 +// CHECK-ENCODING: encoding: [0x0f,0x25,0x3d,0xd5] +// CHECK-UNKNOWN: d53d250f mrs x15, GCSCR_EL12 msr GCSPR_EL12, x16 +// CHECK-INST: msr GCSPR_EL12, x16 +// CHECK-ENCODING: encoding: [0x30,0x25,0x1d,0xd5] +// CHECK-UNKNOWN: d51d2530 msr GCSPR_EL12, x16 + mrs x17, GCSPR_EL12 -// CHECK: msr GCSPR_EL12, x16 // encoding: [0x30,0x25,0x1d,0xd5] -// CHECK: mrs x17, GCSPR_EL12 // encoding: [0
[llvm-branch-commits] [llvm] [AArch64][llvm] Unify AArch64 tests into a single file (2/4) (NFC) (PR #146329)
@@ -0,0 +1,138 @@ +// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+lse128 < %s \ +// RUN:| FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST +// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \ +// RUN:| FileCheck %s --check-prefixes=CHECK-ERROR +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+lse128 < %s \ +// RUN:| llvm-objdump -d --mattr=+lse128 - | FileCheck %s --check-prefix=CHECK-INST +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+lse128 < %s \ +// RUN: | llvm-objdump -d --mattr=-lse128 - | FileCheck %s --check-prefix=CHECK-UNKNOWN +// Disassemble encoding and check the re-encoding (-show-encoding) matches. +// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+lse128 < %s \ +// RUN:| sed '/.text/d' | sed 's/.*encoding: //g' \ +// RUN:| llvm-mc -triple=aarch64 -mattr=+lse128 -disassemble -show-encoding \ +// RUN:| FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST + + + +ldclrp x1, x2, [x11] +// CHECK-INST: ldclrp x1, x2, [x11] +// CHECK-ENCODING: encoding: [0x61,0x11,0x22,0x19] +// CHECK-ERROR: :[[@LINE-3]]:1: error: instruction requires: lse128 +// CHECK-UNKNOWN: 19221161 +ldclrp x21, x22, [sp] tmatheson-arm wrote: No spaces between cases? https://github.com/llvm/llvm-project/pull/146329 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
