Author: Tomas Matheson Date: 2021-01-06T12:10:22Z New Revision: 643e3c90761f30194a76671065d221d3cb71a199
URL: https://github.com/llvm/llvm-project/commit/643e3c90761f30194a76671065d221d3cb71a199 DIFF: https://github.com/llvm/llvm-project/commit/643e3c90761f30194a76671065d221d3cb71a199.diff LOG: [AArch64] Add BRB IALL and BRB INJ instructions BRB IALL: Invalidate the Branch Record Buffer BRB INJ: Branch Record Injection into the Branch Record Buffer Parser changes based on work by Simon Tatham. These are two-word mnemonics. The assembly parser works by special-casing the mnemonic in order to parse the second word as a plain identifier token. Reviewed by: MarkMurrayARM Differential Revision: https://reviews.llvm.org/D93899 Added: Modified: llvm/lib/Target/AArch64/AArch64InstrInfo.td llvm/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp llvm/test/MC/AArch64/brbe.s Removed: ################################################################################ diff --git a/llvm/lib/Target/AArch64/AArch64InstrInfo.td b/llvm/lib/Target/AArch64/AArch64InstrInfo.td index 6209f51b1631..efc38292842c 100644 --- a/llvm/lib/Target/AArch64/AArch64InstrInfo.td +++ b/llvm/lib/Target/AArch64/AArch64InstrInfo.td @@ -813,7 +813,21 @@ def WFET : RegInputSystemI<0b0000, 0b000, "wfet">; def WFIT : RegInputSystemI<0b0000, 0b001, "wfit">; } +// Branch Record Buffer two-word mnemonic instructions +class BRBEI<bits<3> op2, string keyword> + : SimpleSystemI<0, (ins), "brb", keyword>, Sched<[WriteSys]> { + let Inst{31-8} = 0b110101010000100101110010; + let Inst{7-5} = op2; + let Predicates = [HasBRBE]; } +def BRB_IALL: BRBEI<0b100, "\tiall">; +def BRB_INJ: BRBEI<0b101, "\tinj">; + +} + +// Allow uppercase and lowercase keyword arguments for BRB IALL and BRB INJ +def : TokenAlias<"INJ", "inj">; +def : TokenAlias<"IALL", "iall">; // ARMv8.2-A Dot Product let Predicates = [HasDotProd] in { diff --git a/llvm/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp b/llvm/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp index 26e093bf4ce7..0916cf92640b 100644 --- a/llvm/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp +++ b/llvm/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp @@ -159,6 +159,7 @@ class AArch64AsmParser : public MCTargetAsmParser { bool parseSymbolicImmVal(const MCExpr *&ImmVal); bool parseNeonVectorList(OperandVector &Operands); bool parseOptionalMulOperand(OperandVector &Operands); + bool parseKeywordOperand(OperandVector &Operands); bool parseOperand(OperandVector &Operands, bool isCondCode, bool invertCondCode); bool parseImmExpr(int64_t &Out); @@ -3701,6 +3702,17 @@ bool AArch64AsmParser::parseOptionalMulOperand(OperandVector &Operands) { return Error(getLoc(), "expected 'vl' or '#<imm>'"); } +bool AArch64AsmParser::parseKeywordOperand(OperandVector &Operands) { + MCAsmParser &Parser = getParser(); + auto Tok = Parser.getTok(); + if (Tok.isNot(AsmToken::Identifier)) + return true; + Operands.push_back(AArch64Operand::CreateToken(Tok.getString(), false, + Tok.getLoc(), getContext())); + Parser.Lex(); + return false; +} + /// parseOperand - Parse a arm instruction operand. For now this parses the /// operand regardless of the mnemonic. bool AArch64AsmParser::parseOperand(OperandVector &Operands, bool isCondCode, @@ -3765,6 +3777,11 @@ bool AArch64AsmParser::parseOperand(OperandVector &Operands, bool isCondCode, if (GotShift != MatchOperand_NoMatch) return GotShift; + // If this is a two-word mnemonic, parse its special keyword + // operand as an identifier. + if (Mnemonic == "brb") + return parseKeywordOperand(Operands); + // This was not a register so parse other operands that start with an // identifier (like labels) as expressions and create them as immediates. const MCExpr *IdVal; diff --git a/llvm/test/MC/AArch64/brbe.s b/llvm/test/MC/AArch64/brbe.s index 7b0dfe4955ad..f02017dae8e5 100644 --- a/llvm/test/MC/AArch64/brbe.s +++ b/llvm/test/MC/AArch64/brbe.s @@ -133,3 +133,17 @@ mrs x5, BRBTGT31_EL1 // CHECK: mrs x5, BRBTGT31_EL1 // encoding: [0xc5,0x8f,0x31,0xd5] // ERROR-NO-BRBE: [[@LINE-4]]:5: error: expected writable system register // ERROR-NO-BRBE: [[@LINE-4]]:9: error: expected readable system register + +brb iall +brb inj +// CHECK: brb iall // encoding: [0x9f,0x72,0x09,0xd5] +// CHECK: brb inj // encoding: [0xbf,0x72,0x09,0xd5] +// ERROR-NO-BRBE: [[@LINE-4]]:1: error: instruction requires: brbe +// ERROR-NO-BRBE: [[@LINE-4]]:1: error: instruction requires: brbe + +brb IALL +brb INJ +// CHECK: brb iall // encoding: [0x9f,0x72,0x09,0xd5] +// CHECK: brb inj // encoding: [0xbf,0x72,0x09,0xd5] +// ERROR-NO-BRBE: [[@LINE-4]]:1: error: instruction requires: brbe +// ERROR-NO-BRBE: [[@LINE-4]]:1: error: instruction requires: brbe _______________________________________________ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
