[llvm-branch-commits] [llvm] f344c02 - [AArch64] Add missing "pauth" feature to the .arch_extension directive.
Author: Mark Murray
Date: 2021-01-20T11:57:39Z
New Revision: f344c028dea34c1f1ec3b901d7a4c4d5d867384d
URL:
https://github.com/llvm/llvm-project/commit/f344c028dea34c1f1ec3b901d7a4c4d5d867384d
DIFF:
https://github.com/llvm/llvm-project/commit/f344c028dea34c1f1ec3b901d7a4c4d5d867384d.diff
LOG: [AArch64] Add missing "pauth" feature to the .arch_extension directive.
Differential Revision: https://reviews.llvm.org/D94970
Added:
llvm/test/MC/AArch64/armv8.3a-pauth.s
Modified:
llvm/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp
llvm/test/MC/AArch64/directive-arch_extension.s
Removed:
diff --git a/llvm/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp
b/llvm/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp
index 0916cf92640b..bcc5630b3ccd 100644
--- a/llvm/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp
+++ b/llvm/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp
@@ -2915,6 +2915,7 @@ static const struct Extension {
{"sve2-bitperm", {AArch64::FeatureSVE2BitPerm}},
{"ls64", {AArch64::FeatureLS64}},
{"xs", {AArch64::FeatureXS}},
+{"pauth", {AArch64::FeaturePAuth}},
// FIXME: Unsupported extensions
{"pan", {}},
{"lor", {}},
diff --git a/llvm/test/MC/AArch64/armv8.3a-pauth.s
b/llvm/test/MC/AArch64/armv8.3a-pauth.s
new file mode 100644
index ..153bf687fcc8
--- /dev/null
+++ b/llvm/test/MC/AArch64/armv8.3a-pauth.s
@@ -0,0 +1,6 @@
+// RUN: llvm-mc -triple aarch64-none-linux-gnu -show-encoding -mattr=+pauth
< %s | FileCheck %s
+
+paciasp
+
+// CHECK: .text
+// CHECK: paciasp // encoding: [0x3f,0x23,0x03,0xd5]
diff --git a/llvm/test/MC/AArch64/directive-arch_extension.s
b/llvm/test/MC/AArch64/directive-arch_extension.s
index a44b14ddeea2..7041f613c4c8 100644
--- a/llvm/test/MC/AArch64/directive-arch_extension.s
+++ b/llvm/test/MC/AArch64/directive-arch_extension.s
@@ -71,3 +71,7 @@ ldapr x0, [x1]
.arch_extension ls64
ld64b x0, [x13]
// CHECK: ld64b x0, [x13]
+
+.arch_extension pauth
+paciasp
+// CHECK: paciasp
___
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[llvm-branch-commits] [llvm] cab20f6 - [AArch64] Add missing "flagm" feature to the .arch_extension directive.
Author: Mark Murray
Date: 2021-01-20T11:57:39Z
New Revision: cab20f61057760e3f9d7e12a9b25f3934ebd1ea4
URL:
https://github.com/llvm/llvm-project/commit/cab20f61057760e3f9d7e12a9b25f3934ebd1ea4
DIFF:
https://github.com/llvm/llvm-project/commit/cab20f61057760e3f9d7e12a9b25f3934ebd1ea4.diff
LOG: [AArch64] Add missing "flagm" feature to the .arch_extension directive.
Depends on D94970
Differential Revision: https://reviews.llvm.org/D94971
Added:
llvm/test/MC/AArch64/armv8.4a-flagm.s
Modified:
llvm/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp
llvm/test/MC/AArch64/directive-arch_extension-negative.s
llvm/test/MC/AArch64/directive-arch_extension.s
Removed:
diff --git a/llvm/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp
b/llvm/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp
index bcc5630b3ccd..2df9a8050e66 100644
--- a/llvm/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp
+++ b/llvm/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp
@@ -2916,6 +2916,7 @@ static const struct Extension {
{"ls64", {AArch64::FeatureLS64}},
{"xs", {AArch64::FeatureXS}},
{"pauth", {AArch64::FeaturePAuth}},
+{"flagm", {AArch64::FeatureFlagM}},
// FIXME: Unsupported extensions
{"pan", {}},
{"lor", {}},
diff --git a/llvm/test/MC/AArch64/armv8.4a-flagm.s
b/llvm/test/MC/AArch64/armv8.4a-flagm.s
new file mode 100644
index ..2ed43b6cc874
--- /dev/null
+++ b/llvm/test/MC/AArch64/armv8.4a-flagm.s
@@ -0,0 +1,6 @@
+// RUN: llvm-mc -triple aarch64-none-linux-gnu -show-encoding -mattr=+flagm
< %s | FileCheck %s
+
+cfinv
+
+// CHECK: .text
+cfinv // encoding: [0x1f,0x40,0x00,0xd5]
diff --git a/llvm/test/MC/AArch64/directive-arch_extension-negative.s
b/llvm/test/MC/AArch64/directive-arch_extension-negative.s
index 29920d442a8a..797a303e3043 100644
--- a/llvm/test/MC/AArch64/directive-arch_extension-negative.s
+++ b/llvm/test/MC/AArch64/directive-arch_extension-negative.s
@@ -1,5 +1,5 @@
// RUN: not llvm-mc -triple aarch64 \
-// RUN:
-mattr=+crc,+sm4,+sha3,+sha2,+aes,+fp,+neon,+ras,+lse,+predres,+ccdp,+mte,+tlb-rmi,+pan-rwv,+ccpp,+rcpc,+ls64
\
+// RUN:
-mattr=+crc,+sm4,+sha3,+sha2,+aes,+fp,+neon,+ras,+lse,+predres,+ccdp,+mte,+tlb-rmi,+pan-rwv,+ccpp,+rcpc,+ls64,+flagm
\
// RUN: -filetype asm -o - %s 2>&1 | FileCheck %s
.arch_extension axp64
@@ -124,3 +124,10 @@ ld64b x0, [x13]
ld64b x0, [x13]
// CHECK: [[@LINE-1]]:1: error: instruction requires: ls64
// CHECK-NEXT: ld64b x0, [x13]
+
+cfinv
+// CHECK-NOT: [[@LINE-1]]:1: error: instruction requires: flagm
+.arch_extension noflagm
+cfinv
+// CHECK: [[@LINE-1]]:1: error: instruction requires: flagm
+// CHECK-NEXT: cfinv
diff --git a/llvm/test/MC/AArch64/directive-arch_extension.s
b/llvm/test/MC/AArch64/directive-arch_extension.s
index 7041f613c4c8..8cf2acd509b1 100644
--- a/llvm/test/MC/AArch64/directive-arch_extension.s
+++ b/llvm/test/MC/AArch64/directive-arch_extension.s
@@ -75,3 +75,7 @@ ld64b x0, [x13]
.arch_extension pauth
paciasp
// CHECK: paciasp
+
+.arch_extension flagm
+cfinv
+// CHECK: cfinv
___
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[llvm-branch-commits] [clang] 5abfecc - [ARM][AArch64] Add Cortex-A78C Support for Clang and LLVM
Author: Mark Murray
Date: 2020-12-29T10:18:59Z
New Revision: 5abfeccf10bcbc0d673ece21ddd8d4ac4a0e7594
URL:
https://github.com/llvm/llvm-project/commit/5abfeccf10bcbc0d673ece21ddd8d4ac4a0e7594
DIFF:
https://github.com/llvm/llvm-project/commit/5abfeccf10bcbc0d673ece21ddd8d4ac4a0e7594.diff
LOG: [ARM][AArch64] Add Cortex-A78C Support for Clang and LLVM
This patch upstreams support for the Armv8-a Cortex-A78C
processor for AArch64 and ARM.
In detail:
Adding cortex-a78c as cpu option for aarch64 and arm targets in clang
Adding Cortex-A78C CPU name and ProcessorModel in llvm
Details of the CPU can be found here:
https://www.arm.com/products/silicon-ip-cpu/cortex-a/cortex-a78c
Added:
Modified:
clang/test/Driver/aarch64-cpus.c
llvm/include/llvm/Support/AArch64TargetParser.def
llvm/include/llvm/Support/ARMTargetParser.def
llvm/lib/Target/AArch64/AArch64.td
llvm/lib/Target/AArch64/AArch64Subtarget.cpp
llvm/lib/Target/AArch64/AArch64Subtarget.h
llvm/lib/Target/ARM/ARM.td
llvm/lib/Target/ARM/ARMSubtarget.cpp
llvm/lib/Target/ARM/ARMSubtarget.h
llvm/unittests/Support/TargetParserTest.cpp
Removed:
diff --git a/clang/test/Driver/aarch64-cpus.c
b/clang/test/Driver/aarch64-cpus.c
index 283660b321b3..7ac2473915e8 100644
--- a/clang/test/Driver/aarch64-cpus.c
+++ b/clang/test/Driver/aarch64-cpus.c
@@ -183,6 +183,8 @@
// CORTEXX1: "-cc1"{{.*}} "-triple" "aarch64{{.*}}" "-target-cpu" "cortex-x1"
// RUN: %clang -target aarch64 -mcpu=cortex-a78 -### -c %s 2>&1 | FileCheck
-check-prefix=CORTEXA78 %s
// CORTEXA78: "-cc1"{{.*}} "-triple" "aarch64{{.*}}" "-target-cpu" "cortex-a78"
+// RUN: %clang -target aarch64 -mcpu=cortex-a78c -### -c %s 2>&1 | FileCheck
-check-prefix=CORTEX-A78C %s
+// CORTEX-A78C: "-cc1"{{.*}} "-triple" "aarch64{{.*}}" "-target-cpu"
"cortex-a78c"
// RUN: %clang -target aarch64 -mcpu=neoverse-v1 -### -c %s 2>&1 | FileCheck
-check-prefix=NEOVERSE-V1 %s
// NEOVERSE-V1: "-cc1"{{.*}} "-triple" "aarch64{{.*}}" "-target-cpu"
"neoverse-v1"
@@ -475,6 +477,12 @@
// MCPU-MTUNE-THUNDERX2T99: "-cc1"{{.*}} "-triple" "aarch64{{.*}}"
"-target-cpu" "thunderx2t99"
// MCPU-MTUNE-THUNDERX3T110: "-cc1"{{.*}} "-triple" "aarch64{{.*}}"
"-target-cpu" "thunderx3t110"
+// RUN: %clang -target armv8a-arm-none-eabi -mcpu=cortex-a78c -### -c %s 2>&1
| FileCheck -check-prefix=CHECK-CORTEX-A78C %s
+// RUN: %clang -target armv8a-arm-none-eabi -mcpu=cortex-a78c
-mfpu=crypto-neon-fp-armv8 -### -c %s 2>&1 | FileCheck
-check-prefix=CHECK-CORTEX-A78C-MFPU %s
+// CHECK-CORTEX-A78C: "-cc1"{{.*}} "-triple" "armv8.2a-{{.*}} "-target-cpu"
"cortex-a78c"
+// CHECK-CORTEX-A78C-MFPU: "-cc1"{{.*}} "-target-feature" "+fp-armv8"
+// CHECK-CORTEX-A78C-MFPU: "-target-feature" "+crypto"
+
// RUN: %clang -target aarch64 -march=armv8.1a -### -c %s 2>&1 | FileCheck
-check-prefix=GENERICV81A %s
// RUN: %clang -target aarch64 -march=armv8.1-a -### -c %s 2>&1 | FileCheck
-check-prefix=GENERICV81A %s
// RUN: %clang -target aarch64 -mlittle-endian -march=armv8.1a -### -c %s 2>&1
| FileCheck -check-prefix=GENERICV81A %s
diff --git a/llvm/include/llvm/Support/AArch64TargetParser.def
b/llvm/include/llvm/Support/AArch64TargetParser.def
index 97172730e364..f1a5bf734a13 100644
--- a/llvm/include/llvm/Support/AArch64TargetParser.def
+++ b/llvm/include/llvm/Support/AArch64TargetParser.def
@@ -147,6 +147,9 @@ AARCH64_CPU_NAME("cortex-a77", ARMV8_2A,
FK_CRYPTO_NEON_FP_ARMV8, false,
AARCH64_CPU_NAME("cortex-a78", ARMV8_2A, FK_CRYPTO_NEON_FP_ARMV8, false,
(AArch64::AEK_FP16 | AArch64::AEK_DOTPROD | AArch64::AEK_RCPC
|
AArch64::AEK_SSBS))
+AARCH64_CPU_NAME("cortex-a78c", ARMV8_2A, FK_CRYPTO_NEON_FP_ARMV8, false,
+ (AArch64::AEK_FP16 | AArch64::AEK_DOTPROD | AArch64::AEK_RCPC
|
+ AArch64::AEK_SSBS))
AARCH64_CPU_NAME("cortex-r82", ARMV8R, FK_CRYPTO_NEON_FP_ARMV8, false,
(AArch64::AEK_LSE))
AARCH64_CPU_NAME("cortex-x1", ARMV8_2A, FK_CRYPTO_NEON_FP_ARMV8, false,
diff --git a/llvm/include/llvm/Support/ARMTargetParser.def
b/llvm/include/llvm/Support/ARMTargetParser.def
index 76341a051dbf..37cf0a93bb04 100644
--- a/llvm/include/llvm/Support/ARMTargetParser.def
+++ b/llvm/include/llvm/Support/ARMTargetParser.def
@@ -300,8 +300,10 @@ ARM_CPU_NAME("cortex-a76ae", ARMV8_2A,
FK_CRYPTO_NEON_FP_ARMV8, false,
(ARM::AEK_FP16 | ARM::AEK_DOTPROD))
ARM_CPU_NAME("cortex-a77", ARMV8_2A, FK_CRYPTO_NEON_FP_ARMV8, false,
(ARM::AEK_FP16 | ARM::AEK_DOTPROD))
-ARM_CPU_NAME("cortex-a78",ARMV8_2A, FK_CRYPTO_NEON_FP_ARMV8, false,
+ARM_CPU_NAME("cortex-a78", ARMV8_2A, FK_CRYPTO_NEON_FP_ARMV8, false,
(ARM::AEK_FP16 | ARM::AEK_DOTPROD))
+ARM_CPU_NAME("cortex-a78c", ARMV8_2A, FK_CRYPTO_NEON_FP_ARMV8, false,
+ ARM::AEK_FP16 | ARM::AEK_DOTPROD)
ARM_CPU_NAME("cortex-x1", ARMV8_2A, FK_CRYPTO_NE
[llvm-branch-commits] [clang] af7cce2 - [AArch64] Add +pauth archictecture option, allowing the v8.3a pointer authentication extension.
Author: Mark Murray
Date: 2021-01-08T13:21:11Z
New Revision: af7cce2fa4d19c3cd09607e1d6ea2e0847cc55b7
URL:
https://github.com/llvm/llvm-project/commit/af7cce2fa4d19c3cd09607e1d6ea2e0847cc55b7
DIFF:
https://github.com/llvm/llvm-project/commit/af7cce2fa4d19c3cd09607e1d6ea2e0847cc55b7.diff
LOG: [AArch64] Add +pauth archictecture option, allowing the v8.3a pointer
authentication extension.
Differential Revision: https://reviews.llvm.org/D94083
Added:
Modified:
clang/lib/Basic/Targets/AArch64.cpp
clang/lib/Basic/Targets/AArch64.h
llvm/include/llvm/Support/AArch64TargetParser.def
llvm/include/llvm/Support/AArch64TargetParser.h
llvm/lib/Support/AArch64TargetParser.cpp
llvm/lib/Target/AArch64/AArch64.td
llvm/lib/Target/AArch64/AArch64FrameLowering.cpp
llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
llvm/lib/Target/AArch64/AArch64InstrInfo.cpp
llvm/lib/Target/AArch64/AArch64InstrInfo.td
llvm/lib/Target/AArch64/AArch64Subtarget.h
llvm/lib/Target/AArch64/AArch64SystemOperands.td
llvm/lib/Target/AArch64/GISel/AArch64InstructionSelector.cpp
llvm/unittests/Support/TargetParserTest.cpp
Removed:
diff --git a/clang/lib/Basic/Targets/AArch64.cpp
b/clang/lib/Basic/Targets/AArch64.cpp
index c1abe8e9f75b..d03bca9cfd90 100644
--- a/clang/lib/Basic/Targets/AArch64.cpp
+++ b/clang/lib/Basic/Targets/AArch64.cpp
@@ -510,6 +510,8 @@ bool
AArch64TargetInfo::handleTargetFeatures(std::vector &Features,
HasMTE = true;
if (Feature == "+tme")
HasTME = true;
+if (Feature == "+pauth")
+ HasPAuth = true;
if (Feature == "+i8mm")
HasMatMul = true;
if (Feature == "+bf16")
diff --git a/clang/lib/Basic/Targets/AArch64.h
b/clang/lib/Basic/Targets/AArch64.h
index bd576680077e..5f24ab6a4d61 100644
--- a/clang/lib/Basic/Targets/AArch64.h
+++ b/clang/lib/Basic/Targets/AArch64.h
@@ -36,6 +36,7 @@ class LLVM_LIBRARY_VISIBILITY AArch64TargetInfo : public
TargetInfo {
bool HasFP16FML;
bool HasMTE;
bool HasTME;
+ bool HasPAuth;
bool HasLS64;
bool HasMatMul;
bool HasSVE2;
diff --git a/llvm/include/llvm/Support/AArch64TargetParser.def
b/llvm/include/llvm/Support/AArch64TargetParser.def
index f1a5bf734a13..38cc2e753740 100644
--- a/llvm/include/llvm/Support/AArch64TargetParser.def
+++ b/llvm/include/llvm/Support/AArch64TargetParser.def
@@ -108,6 +108,7 @@ AARCH64_ARCH_EXT_NAME("f64mm",AArch64::AEK_F64MM,
"+f64mm", "-f64m
AARCH64_ARCH_EXT_NAME("tme", AArch64::AEK_TME, "+tme",
"-tme")
AARCH64_ARCH_EXT_NAME("ls64", AArch64::AEK_LS64,"+ls64",
"-ls64")
AARCH64_ARCH_EXT_NAME("brbe", AArch64::AEK_BRBE,"+brbe",
"-brbe")
+AARCH64_ARCH_EXT_NAME("pauth",AArch64::AEK_PAUTH, "+pauth",
"-pauth")
#undef AARCH64_ARCH_EXT_NAME
#ifndef AARCH64_CPU_NAME
diff --git a/llvm/include/llvm/Support/AArch64TargetParser.h
b/llvm/include/llvm/Support/AArch64TargetParser.h
index a3c9c6a30483..35827517d7fc 100644
--- a/llvm/include/llvm/Support/AArch64TargetParser.h
+++ b/llvm/include/llvm/Support/AArch64TargetParser.h
@@ -64,6 +64,7 @@ enum ArchExtKind : uint64_t {
AEK_F64MM = 1ULL << 32,
AEK_LS64 =1ULL << 33,
AEK_BRBE =1ULL << 34,
+ AEK_PAUTH = 1ULL << 35,
};
enum class ArchKind {
diff --git a/llvm/lib/Support/AArch64TargetParser.cpp
b/llvm/lib/Support/AArch64TargetParser.cpp
index 62761177c8c2..be595e83dbef 100644
--- a/llvm/lib/Support/AArch64TargetParser.cpp
+++ b/llvm/lib/Support/AArch64TargetParser.cpp
@@ -102,6 +102,8 @@ bool AArch64::getExtensionFeatures(uint64_t Extensions,
Features.push_back("+rcpc");
if (Extensions & AEK_BRBE)
Features.push_back("+brbe");
+ if (Extensions & AEK_PAUTH)
+Features.push_back("+pauth");
return true;
}
diff --git a/llvm/lib/Target/AArch64/AArch64.td
b/llvm/lib/Target/AArch64/AArch64.td
index 2be006bb647f..1f1bf0ac1657 100644
--- a/llvm/lib/Target/AArch64/AArch64.td
+++ b/llvm/lib/Target/AArch64/AArch64.td
@@ -261,8 +261,8 @@ def FeatureDotProd : SubtargetFeature<
"dotprod", "HasDotProd", "true",
"Enable dot product support">;
-def FeaturePA : SubtargetFeature<
-"pa", "HasPA", "true",
+def FeaturePAuth : SubtargetFeature<
+"pauth", "HasPAuth", "true",
"Enable v8.3-A Pointer Authentication extension">;
def FeatureJS : SubtargetFeature<
@@ -438,7 +438,7 @@ def HasV8_2aOps : SubtargetFeature<"v8.2a", "HasV8_2aOps",
"true",
FeaturePAN_RWV, FeatureRAS, FeatureCCPP]>;
def HasV8_3aOps : SubtargetFeature<"v8.3a", "HasV8_3aOps", "true",
- "Support ARM v8.3a instructions", [HasV8_2aOps, FeatureRCPC, FeaturePA,
+ "Support ARM v8.3a instructions", [HasV8_2aOps, FeatureRCPC, FeaturePAuth,
FeatureJS, FeatureCCIDX, FeatureComplxNum]>;
def HasV8_4aOps : SubtargetFeature<"v8.4a", "HasV8_4aOps", "true",
@@ -471,7 +471,7 @@ def Has
[llvm-branch-commits] [clang] 7d4a8bc - [AArch64] Add +flagm archictecture option, allowing the v8.4a flag modification extension.
Author: Mark Murray
Date: 2021-01-08T13:21:12Z
New Revision: 7d4a8bc417bf75b5e4034674a4255173d0089e68
URL:
https://github.com/llvm/llvm-project/commit/7d4a8bc417bf75b5e4034674a4255173d0089e68
DIFF:
https://github.com/llvm/llvm-project/commit/7d4a8bc417bf75b5e4034674a4255173d0089e68.diff
LOG: [AArch64] Add +flagm archictecture option, allowing the v8.4a flag
modification extension.
Differential Revision: https://reviews.llvm.org/D94081
Added:
Modified:
clang/lib/Basic/Targets/AArch64.cpp
clang/lib/Basic/Targets/AArch64.h
llvm/include/llvm/Support/AArch64TargetParser.def
llvm/include/llvm/Support/AArch64TargetParser.h
llvm/lib/Support/AArch64TargetParser.cpp
llvm/lib/Target/AArch64/AArch64.td
llvm/lib/Target/AArch64/AArch64InstrInfo.td
llvm/lib/Target/AArch64/AArch64Subtarget.h
llvm/test/MC/AArch64/armv8.4a-flag.s
llvm/unittests/Support/TargetParserTest.cpp
Removed:
diff --git a/clang/lib/Basic/Targets/AArch64.cpp
b/clang/lib/Basic/Targets/AArch64.cpp
index d03bca9cfd90..312c822ebb05 100644
--- a/clang/lib/Basic/Targets/AArch64.cpp
+++ b/clang/lib/Basic/Targets/AArch64.cpp
@@ -520,6 +520,8 @@ bool
AArch64TargetInfo::handleTargetFeatures(std::vector &Features,
HasLSE = true;
if (Feature == "+ls64")
HasLS64 = true;
+if (Feature == "+flagm")
+ HasFlagM = true;
}
setDataLayout();
diff --git a/clang/lib/Basic/Targets/AArch64.h
b/clang/lib/Basic/Targets/AArch64.h
index 5f24ab6a4d61..2809fbce9c88 100644
--- a/clang/lib/Basic/Targets/AArch64.h
+++ b/clang/lib/Basic/Targets/AArch64.h
@@ -47,6 +47,7 @@ class LLVM_LIBRARY_VISIBILITY AArch64TargetInfo : public
TargetInfo {
bool HasMatmulFP64;
bool HasMatmulFP32;
bool HasLSE;
+ bool HasFlagM;
llvm::AArch64::ArchKind ArchKind;
diff --git a/llvm/include/llvm/Support/AArch64TargetParser.def
b/llvm/include/llvm/Support/AArch64TargetParser.def
index 38cc2e753740..5f36b0eecff9 100644
--- a/llvm/include/llvm/Support/AArch64TargetParser.def
+++ b/llvm/include/llvm/Support/AArch64TargetParser.def
@@ -109,6 +109,7 @@ AARCH64_ARCH_EXT_NAME("tme", AArch64::AEK_TME,
"+tme", "-tme"
AARCH64_ARCH_EXT_NAME("ls64", AArch64::AEK_LS64,"+ls64",
"-ls64")
AARCH64_ARCH_EXT_NAME("brbe", AArch64::AEK_BRBE,"+brbe",
"-brbe")
AARCH64_ARCH_EXT_NAME("pauth",AArch64::AEK_PAUTH, "+pauth",
"-pauth")
+AARCH64_ARCH_EXT_NAME("flagm",AArch64::AEK_FLAGM, "+flagm",
"-flagm")
#undef AARCH64_ARCH_EXT_NAME
#ifndef AARCH64_CPU_NAME
diff --git a/llvm/include/llvm/Support/AArch64TargetParser.h
b/llvm/include/llvm/Support/AArch64TargetParser.h
index 35827517d7fc..7c9e245e3889 100644
--- a/llvm/include/llvm/Support/AArch64TargetParser.h
+++ b/llvm/include/llvm/Support/AArch64TargetParser.h
@@ -65,6 +65,7 @@ enum ArchExtKind : uint64_t {
AEK_LS64 =1ULL << 33,
AEK_BRBE =1ULL << 34,
AEK_PAUTH = 1ULL << 35,
+ AEK_FLAGM = 1ULL << 36,
};
enum class ArchKind {
diff --git a/llvm/lib/Support/AArch64TargetParser.cpp
b/llvm/lib/Support/AArch64TargetParser.cpp
index be595e83dbef..503a7bd49d15 100644
--- a/llvm/lib/Support/AArch64TargetParser.cpp
+++ b/llvm/lib/Support/AArch64TargetParser.cpp
@@ -104,6 +104,8 @@ bool AArch64::getExtensionFeatures(uint64_t Extensions,
Features.push_back("+brbe");
if (Extensions & AEK_PAUTH)
Features.push_back("+pauth");
+ if (Extensions & AEK_FLAGM)
+Features.push_back("+flagm");
return true;
}
diff --git a/llvm/lib/Target/AArch64/AArch64.td
b/llvm/lib/Target/AArch64/AArch64.td
index 1f1bf0ac1657..002efd700cc2 100644
--- a/llvm/lib/Target/AArch64/AArch64.td
+++ b/llvm/lib/Target/AArch64/AArch64.td
@@ -316,8 +316,8 @@ def FeatureTLB_RMI : SubtargetFeature<
"tlb-rmi", "HasTLB_RMI", "true",
"Enable v8.4-A TLB Range and Maintenance Instructions">;
-def FeatureFMI : SubtargetFeature<
-"fmi", "HasFMI", "true",
+def FeatureFlagM : SubtargetFeature<
+"flagm", "HasFlagM", "true",
"Enable v8.4-A Flag Manipulation Instructions">;
// 8.4 RCPC enchancements: LDAPR & STLR instructions with Immediate Offset
@@ -445,7 +445,7 @@ def HasV8_4aOps : SubtargetFeature<"v8.4a", "HasV8_4aOps",
"true",
"Support ARM v8.4a instructions", [HasV8_3aOps, FeatureDotProd,
FeatureNV, FeatureMPAM, FeatureDIT,
FeatureTRACEV8_4, FeatureAM, FeatureSEL2, FeaturePMU, FeatureTLB_RMI,
- FeatureFMI, FeatureRCPC_IMMO]>;
+ FeatureFlagM, FeatureRCPC_IMMO]>;
def HasV8_5aOps : SubtargetFeature<
"v8.5a", "HasV8_5aOps", "true", "Support ARM v8.5a instructions",
@@ -474,7 +474,7 @@ def HasV8_0rOps : SubtargetFeature<
FeaturePAuth, FeatureRCPC,
//v8.4
FeatureDotProd, FeatureFP16FML, FeatureTRACEV8_4,
- FeatureTLB_RMI, FeatureFMI, FeatureDIT, FeatureSEL2, FeatureRCPC_IMMO,
+ FeatureTLB_RMI, FeatureFlagM, FeatureDIT, Feature
[llvm-branch-commits] [clang] 2b66918 - [ARM][AArch64] Adding Neoverse N2 CPU support
Author: Mark Murray
Date: 2020-11-25T11:42:54Z
New Revision: 2b6691894ab671706051a6d7ef54571546c20d3b
URL:
https://github.com/llvm/llvm-project/commit/2b6691894ab671706051a6d7ef54571546c20d3b
DIFF:
https://github.com/llvm/llvm-project/commit/2b6691894ab671706051a6d7ef54571546c20d3b.diff
LOG: [ARM][AArch64] Adding Neoverse N2 CPU support
Add support for the Neoverse N2 CPU to the ARM and AArch64 backends.
Differential Revision: https://reviews.llvm.org/D91695
Added:
Modified:
clang/test/Driver/aarch64-cpus.c
clang/test/Driver/arm-cortex-cpus.c
llvm/include/llvm/Support/AArch64TargetParser.def
llvm/include/llvm/Support/ARMTargetParser.def
llvm/lib/Support/Host.cpp
llvm/lib/Target/AArch64/AArch64.td
llvm/lib/Target/AArch64/AArch64Subtarget.cpp
llvm/lib/Target/AArch64/AArch64Subtarget.h
llvm/lib/Target/ARM/ARM.td
llvm/lib/Target/ARM/ARMSubtarget.cpp
llvm/lib/Target/ARM/ARMSubtarget.h
llvm/test/CodeGen/AArch64/cpus.ll
llvm/test/CodeGen/AArch64/neon-dot-product.ll
llvm/test/CodeGen/AArch64/remat.ll
llvm/test/MC/AArch64/armv8.2a-dotprod.s
llvm/test/MC/AArch64/armv8.3a-rcpc.s
llvm/test/MC/AArch64/armv8.5a-ssbs.s
llvm/test/MC/ARM/armv8.2a-dotprod-a32.s
llvm/test/MC/ARM/armv8.2a-dotprod-t32.s
llvm/test/MC/Disassembler/AArch64/armv8.3a-rcpc.txt
llvm/unittests/Support/TargetParserTest.cpp
Removed:
diff --git a/clang/test/Driver/aarch64-cpus.c
b/clang/test/Driver/aarch64-cpus.c
index 139746823660..131a57940b4c 100644
--- a/clang/test/Driver/aarch64-cpus.c
+++ b/clang/test/Driver/aarch64-cpus.c
@@ -752,6 +752,9 @@
// RUN: %clang -target aarch64 -march=armv8-a+ras -### -c %s 2>&1 | FileCheck
-check-prefix=V8ARAS -check-prefix=GENERIC %s
// V8ARAS: "-target-feature" "+ras"
+// RUN: %clang -target aarch64 -mcpu=neoverse-n2 -### -c %s 2>&1 | FileCheck
-check-prefix=NEOVERSE-N2 %s
+// NEOVERSE-N2: "-cc1"{{.*}} "-triple" "aarch64{{.*}}" "-target-cpu"
"neoverse-n2"
+
// == Check whether -march accepts mixed-case values.
// RUN: %clang -target aarch64_be -march=ARMV8.1A -### -c %s 2>&1 | FileCheck
-check-prefix=GENERICV81A-BE %s
// RUN: %clang -target aarch64_be -march=ARMV8.1-A -### -c %s 2>&1 | FileCheck
-check-prefix=GENERICV81A-BE %s
diff --git a/clang/test/Driver/arm-cortex-cpus.c
b/clang/test/Driver/arm-cortex-cpus.c
index 5df872358a7a..a312ccfda5a1 100644
--- a/clang/test/Driver/arm-cortex-cpus.c
+++ b/clang/test/Driver/arm-cortex-cpus.c
@@ -879,6 +879,9 @@
// RUN: %clang -target arm -mcpu=cortex-m55 -### -c %s 2>&1 | FileCheck
-check-prefix=CHECK-CORTEX-M55 %s
// CHECK-CORTEX-M55: "-cc1"{{.*}} "-triple" "thumbv8.1m.main-{{.*}}
"-target-cpu" "cortex-m55"
+// RUN: %clang -target arm -mcpu=neoverse-n2 -### -c %s 2>&1 | FileCheck
-check-prefix=CHECK-NEOVERSE-N2 %s
+// CHECK-NEOVERSE-N2: "-cc1"{{.*}} "-triple" "armv8.5a-{{.*}}" "-target-cpu"
"neoverse-n2"
+
// == Check whether -mcpu accepts mixed-case values.
// RUN: %clang -target arm-linux-gnueabi -mcpu=Cortex-a5 -### -c %s 2>&1 |
FileCheck -check-prefix=CHECK-CASE-INSENSITIVE-CPUV7A %s
// RUN: %clang -target arm-linux-gnueabi -mcpu=cortex-A7 -### -c %s 2>&1 |
FileCheck -check-prefix=CHECK-CASE-INSENSITIVE-CPUV7A %s
diff --git a/llvm/include/llvm/Support/AArch64TargetParser.def
b/llvm/include/llvm/Support/AArch64TargetParser.def
index cbf0d5d079dd..7625f5a6f6ab 100644
--- a/llvm/include/llvm/Support/AArch64TargetParser.def
+++ b/llvm/include/llvm/Support/AArch64TargetParser.def
@@ -150,6 +150,11 @@ AARCH64_CPU_NAME("neoverse-n1", ARMV8_2A,
FK_CRYPTO_NEON_FP_ARMV8, false,
(AArch64::AEK_DOTPROD | AArch64::AEK_FP16 |
AArch64::AEK_PROFILE | AArch64::AEK_RAS | AArch64::AEK_RCPC |
AArch64::AEK_SSBS))
+AARCH64_CPU_NAME("neoverse-n2", ARMV8_5A, FK_CRYPTO_NEON_FP_ARMV8, false,
+ (AArch64::AEK_BF16 | AArch64::AEK_DOTPROD | AArch64::AEK_FP16
|
+ AArch64::AEK_I8MM | AArch64::AEK_MTE | AArch64::AEK_RAS |
+ AArch64::AEK_RCPC | AArch64::AEK_SB | AArch64::AEK_SSBS |
+ AArch64::AEK_SVE | AArch64::AEK_SVE2 |
AArch64::AEK_SVE2BITPERM))
AARCH64_CPU_NAME("neoverse-v1", ARMV8_4A, FK_CRYPTO_NEON_FP_ARMV8, false,
(AArch64::AEK_RAS | AArch64::AEK_SVE | AArch64::AEK_SSBS |
AArch64::AEK_RCPC | AArch64::AEK_FP16 | AArch64::AEK_BF16 |
diff --git a/llvm/include/llvm/Support/ARMTargetParser.def
b/llvm/include/llvm/Support/ARMTargetParser.def
index 35c94fd5bce0..75ab539762db 100644
--- a/llvm/include/llvm/Support/ARMTargetParser.def
+++ b/llvm/include/llvm/Support/ARMTargetParser.def
@@ -300,6 +300,9 @@ ARM_CPU_NAME("cortex-x1", ARMV8_2A,
FK_CRYPTO_NEON_FP_ARMV8, false,
(ARM::AEK_FP16 | ARM::AEK_DOTPROD))
ARM_CPU_NAME("neoverse-n1", ARMV8_2A, FK_CRYPTO_NEON_FP_ARMV8, false,
