Author: Mark Murray Date: 2020-12-29T10:18:59Z New Revision: 5abfeccf10bcbc0d673ece21ddd8d4ac4a0e7594
URL: https://github.com/llvm/llvm-project/commit/5abfeccf10bcbc0d673ece21ddd8d4ac4a0e7594 DIFF: https://github.com/llvm/llvm-project/commit/5abfeccf10bcbc0d673ece21ddd8d4ac4a0e7594.diff LOG: [ARM][AArch64] Add Cortex-A78C Support for Clang and LLVM This patch upstreams support for the Armv8-a Cortex-A78C processor for AArch64 and ARM. In detail: Adding cortex-a78c as cpu option for aarch64 and arm targets in clang Adding Cortex-A78C CPU name and ProcessorModel in llvm Details of the CPU can be found here: https://www.arm.com/products/silicon-ip-cpu/cortex-a/cortex-a78c Added: Modified: clang/test/Driver/aarch64-cpus.c llvm/include/llvm/Support/AArch64TargetParser.def llvm/include/llvm/Support/ARMTargetParser.def llvm/lib/Target/AArch64/AArch64.td llvm/lib/Target/AArch64/AArch64Subtarget.cpp llvm/lib/Target/AArch64/AArch64Subtarget.h llvm/lib/Target/ARM/ARM.td llvm/lib/Target/ARM/ARMSubtarget.cpp llvm/lib/Target/ARM/ARMSubtarget.h llvm/unittests/Support/TargetParserTest.cpp Removed: ################################################################################ diff --git a/clang/test/Driver/aarch64-cpus.c b/clang/test/Driver/aarch64-cpus.c index 283660b321b3..7ac2473915e8 100644 --- a/clang/test/Driver/aarch64-cpus.c +++ b/clang/test/Driver/aarch64-cpus.c @@ -183,6 +183,8 @@ // CORTEXX1: "-cc1"{{.*}} "-triple" "aarch64{{.*}}" "-target-cpu" "cortex-x1" // RUN: %clang -target aarch64 -mcpu=cortex-a78 -### -c %s 2>&1 | FileCheck -check-prefix=CORTEXA78 %s // CORTEXA78: "-cc1"{{.*}} "-triple" "aarch64{{.*}}" "-target-cpu" "cortex-a78" +// RUN: %clang -target aarch64 -mcpu=cortex-a78c -### -c %s 2>&1 | FileCheck -check-prefix=CORTEX-A78C %s +// CORTEX-A78C: "-cc1"{{.*}} "-triple" "aarch64{{.*}}" "-target-cpu" "cortex-a78c" // RUN: %clang -target aarch64 -mcpu=neoverse-v1 -### -c %s 2>&1 | FileCheck -check-prefix=NEOVERSE-V1 %s // NEOVERSE-V1: "-cc1"{{.*}} "-triple" "aarch64{{.*}}" "-target-cpu" "neoverse-v1" @@ -475,6 +477,12 @@ // MCPU-MTUNE-THUNDERX2T99: "-cc1"{{.*}} "-triple" "aarch64{{.*}}" "-target-cpu" "thunderx2t99" // MCPU-MTUNE-THUNDERX3T110: "-cc1"{{.*}} "-triple" "aarch64{{.*}}" "-target-cpu" "thunderx3t110" +// RUN: %clang -target armv8a-arm-none-eabi -mcpu=cortex-a78c -### -c %s 2>&1 | FileCheck -check-prefix=CHECK-CORTEX-A78C %s +// RUN: %clang -target armv8a-arm-none-eabi -mcpu=cortex-a78c -mfpu=crypto-neon-fp-armv8 -### -c %s 2>&1 | FileCheck -check-prefix=CHECK-CORTEX-A78C-MFPU %s +// CHECK-CORTEX-A78C: "-cc1"{{.*}} "-triple" "armv8.2a-{{.*}} "-target-cpu" "cortex-a78c" +// CHECK-CORTEX-A78C-MFPU: "-cc1"{{.*}} "-target-feature" "+fp-armv8" +// CHECK-CORTEX-A78C-MFPU: "-target-feature" "+crypto" + // RUN: %clang -target aarch64 -march=armv8.1a -### -c %s 2>&1 | FileCheck -check-prefix=GENERICV81A %s // RUN: %clang -target aarch64 -march=armv8.1-a -### -c %s 2>&1 | FileCheck -check-prefix=GENERICV81A %s // RUN: %clang -target aarch64 -mlittle-endian -march=armv8.1a -### -c %s 2>&1 | FileCheck -check-prefix=GENERICV81A %s diff --git a/llvm/include/llvm/Support/AArch64TargetParser.def b/llvm/include/llvm/Support/AArch64TargetParser.def index 97172730e364..f1a5bf734a13 100644 --- a/llvm/include/llvm/Support/AArch64TargetParser.def +++ b/llvm/include/llvm/Support/AArch64TargetParser.def @@ -147,6 +147,9 @@ AARCH64_CPU_NAME("cortex-a77", ARMV8_2A, FK_CRYPTO_NEON_FP_ARMV8, false, AARCH64_CPU_NAME("cortex-a78", ARMV8_2A, FK_CRYPTO_NEON_FP_ARMV8, false, (AArch64::AEK_FP16 | AArch64::AEK_DOTPROD | AArch64::AEK_RCPC | AArch64::AEK_SSBS)) +AARCH64_CPU_NAME("cortex-a78c", ARMV8_2A, FK_CRYPTO_NEON_FP_ARMV8, false, + (AArch64::AEK_FP16 | AArch64::AEK_DOTPROD | AArch64::AEK_RCPC | + AArch64::AEK_SSBS)) AARCH64_CPU_NAME("cortex-r82", ARMV8R, FK_CRYPTO_NEON_FP_ARMV8, false, (AArch64::AEK_LSE)) AARCH64_CPU_NAME("cortex-x1", ARMV8_2A, FK_CRYPTO_NEON_FP_ARMV8, false, diff --git a/llvm/include/llvm/Support/ARMTargetParser.def b/llvm/include/llvm/Support/ARMTargetParser.def index 76341a051dbf..37cf0a93bb04 100644 --- a/llvm/include/llvm/Support/ARMTargetParser.def +++ b/llvm/include/llvm/Support/ARMTargetParser.def @@ -300,8 +300,10 @@ ARM_CPU_NAME("cortex-a76ae", ARMV8_2A, FK_CRYPTO_NEON_FP_ARMV8, false, (ARM::AEK_FP16 | ARM::AEK_DOTPROD)) ARM_CPU_NAME("cortex-a77", ARMV8_2A, FK_CRYPTO_NEON_FP_ARMV8, false, (ARM::AEK_FP16 | ARM::AEK_DOTPROD)) -ARM_CPU_NAME("cortex-a78",ARMV8_2A, FK_CRYPTO_NEON_FP_ARMV8, false, +ARM_CPU_NAME("cortex-a78", ARMV8_2A, FK_CRYPTO_NEON_FP_ARMV8, false, (ARM::AEK_FP16 | ARM::AEK_DOTPROD)) +ARM_CPU_NAME("cortex-a78c", ARMV8_2A, FK_CRYPTO_NEON_FP_ARMV8, false, + ARM::AEK_FP16 | ARM::AEK_DOTPROD) ARM_CPU_NAME("cortex-x1", ARMV8_2A, FK_CRYPTO_NEON_FP_ARMV8, false, (ARM::AEK_FP16 | ARM::AEK_DOTPROD)) ARM_CPU_NAME("neoverse-n1", ARMV8_2A, FK_CRYPTO_NEON_FP_ARMV8, false, diff --git a/llvm/lib/Target/AArch64/AArch64.td b/llvm/lib/Target/AArch64/AArch64.td index 2df4e92e42cb..2be006bb647f 100644 --- a/llvm/lib/Target/AArch64/AArch64.td +++ b/llvm/lib/Target/AArch64/AArch64.td @@ -691,6 +691,25 @@ def ProcA78 : SubtargetFeature<"cortex-a78", "ARMProcFamily", FeatureSSBS, FeatureDotProd]>; +def ProcA78C : SubtargetFeature<"cortex-a78c", "ARMProcFamily", + "CortexA78C", + "Cortex-A78C ARM processors", [ + HasV8_2aOps, + FeatureCrypto, + FeatureDotProd, + FeatureFMI, + FeatureFP16FML, + FeatureFPARMv8, + FeatureFullFP16, + FeatureFuseAES, + FeatureNEON, + FeaturePA, + FeaturePerfMon, + FeaturePostRAScheduler, + FeatureRCPC, + FeatureSPE, + FeatureSSBS]>; + def ProcR82 : SubtargetFeature<"cortex-r82", "ARMProcFamily", "CortexR82", "Cortex-R82 ARM Processors", [ @@ -1089,6 +1108,7 @@ def : ProcessorModel<"cortex-a76", CortexA57Model, [ProcA76]>; def : ProcessorModel<"cortex-a76ae", CortexA57Model, [ProcA76]>; def : ProcessorModel<"cortex-a77", CortexA57Model, [ProcA77]>; def : ProcessorModel<"cortex-a78", CortexA57Model, [ProcA78]>; +def : ProcessorModel<"cortex-a78c", CortexA57Model, [ProcA78C]>; def : ProcessorModel<"cortex-r82", CortexA55Model, [ProcR82]>; def : ProcessorModel<"cortex-x1", CortexA57Model, [ProcX1]>; def : ProcessorModel<"neoverse-e1", CortexA53Model, [ProcNeoverseE1]>; diff --git a/llvm/lib/Target/AArch64/AArch64Subtarget.cpp b/llvm/lib/Target/AArch64/AArch64Subtarget.cpp index f3f9d662b600..cef9e9761e42 100644 --- a/llvm/lib/Target/AArch64/AArch64Subtarget.cpp +++ b/llvm/lib/Target/AArch64/AArch64Subtarget.cpp @@ -103,6 +103,7 @@ void AArch64Subtarget::initializeProperties() { case CortexA76: case CortexA77: case CortexA78: + case CortexA78C: case CortexR82: case CortexX1: PrefFunctionLogAlignment = 4; diff --git a/llvm/lib/Target/AArch64/AArch64Subtarget.h b/llvm/lib/Target/AArch64/AArch64Subtarget.h index 641450a6d776..ab44d0767dec 100644 --- a/llvm/lib/Target/AArch64/AArch64Subtarget.h +++ b/llvm/lib/Target/AArch64/AArch64Subtarget.h @@ -57,6 +57,7 @@ class AArch64Subtarget final : public AArch64GenSubtargetInfo { CortexA76, CortexA77, CortexA78, + CortexA78C, CortexR82, CortexX1, ExynosM3, diff --git a/llvm/lib/Target/ARM/ARM.td b/llvm/lib/Target/ARM/ARM.td index 5d626e7d8e5a..3d0a0bf7f8c3 100644 --- a/llvm/lib/Target/ARM/ARM.td +++ b/llvm/lib/Target/ARM/ARM.td @@ -616,6 +616,8 @@ def ProcA77 : SubtargetFeature<"a77", "ARMProcFamily", "CortexA77", "Cortex-A77 ARM processors", []>; def ProcA78 : SubtargetFeature<"cortex-a78", "ARMProcFamily", "CortexA78", "Cortex-A78 ARM processors", []>; +def ProcA78C : SubtargetFeature<"a78c", "ARMProcFamily", "CortexA78C", + "Cortex-A78C ARM processors", []>; def ProcX1 : SubtargetFeature<"cortex-x1", "ARMProcFamily", "CortexX1", "Cortex-X1 ARM processors", []>; @@ -1308,6 +1310,14 @@ def : ProcNoItin<"cortex-a78", [ARMv82a, ProcA78, FeatureFullFP16, FeatureDotProd]>; +def : ProcNoItin<"cortex-a78c", [ARMv82a, ProcA78C, + FeatureHWDivThumb, + FeatureHWDivARM, + FeatureCrypto, + FeatureCRC, + FeatureDotProd, + FeatureFullFP16]>; + def : ProcNoItin<"cortex-x1", [ARMv82a, ProcX1, FeatureHWDivThumb, FeatureHWDivARM, diff --git a/llvm/lib/Target/ARM/ARMSubtarget.cpp b/llvm/lib/Target/ARM/ARMSubtarget.cpp index e2a3d302b103..5cb608b74ace 100644 --- a/llvm/lib/Target/ARM/ARMSubtarget.cpp +++ b/llvm/lib/Target/ARM/ARMSubtarget.cpp @@ -294,6 +294,7 @@ void ARMSubtarget::initSubtargetFeatures(StringRef CPU, StringRef FS) { case CortexA76: case CortexA77: case CortexA78: + case CortexA78C: case CortexR4: case CortexR4F: case CortexR5: diff --git a/llvm/lib/Target/ARM/ARMSubtarget.h b/llvm/lib/Target/ARM/ARMSubtarget.h index ac7248ac29c9..fd9b94fdaa23 100644 --- a/llvm/lib/Target/ARM/ARMSubtarget.h +++ b/llvm/lib/Target/ARM/ARMSubtarget.h @@ -63,6 +63,7 @@ class ARMSubtarget : public ARMGenSubtargetInfo { CortexA76, CortexA77, CortexA78, + CortexA78C, CortexA8, CortexA9, CortexM3, diff --git a/llvm/unittests/Support/TargetParserTest.cpp b/llvm/unittests/Support/TargetParserTest.cpp index bc2fd6243aa5..c2721f3da505 100644 --- a/llvm/unittests/Support/TargetParserTest.cpp +++ b/llvm/unittests/Support/TargetParserTest.cpp @@ -308,6 +308,13 @@ INSTANTIATE_TEST_CASE_P( ARM::AEK_HWDIVTHUMB | ARM::AEK_DSP | ARM::AEK_FP16 | ARM::AEK_RAS | ARM::AEK_DOTPROD, "8.2-A"), + ARMCPUTestParams("cortex-a78c", "armv8.2-a", "crypto-neon-fp-armv8", + ARM::AEK_SEC | ARM::AEK_MP | + ARM::AEK_VIRT | ARM::AEK_HWDIVARM | + ARM::AEK_HWDIVTHUMB | ARM::AEK_DSP | + ARM::AEK_CRC | ARM::AEK_RAS | + ARM::AEK_FP16 | ARM::AEK_DOTPROD, + "8.2-A"), ARMCPUTestParams("cortex-a77", "armv8.2-a", "crypto-neon-fp-armv8", ARM::AEK_CRC | ARM::AEK_SEC | ARM::AEK_MP | ARM::AEK_VIRT | ARM::AEK_HWDIVARM | @@ -385,7 +392,7 @@ INSTANTIATE_TEST_CASE_P( ARM::AEK_HWDIVARM | ARM::AEK_HWDIVTHUMB | ARM::AEK_DSP, "7-S")), ); -static constexpr unsigned NumARMCPUArchs = 91; +static constexpr unsigned NumARMCPUArchs = 92; TEST(TargetParserTest, testARMCPUArchList) { SmallVector<StringRef, NumARMCPUArchs> List; @@ -962,6 +969,14 @@ INSTANTIATE_TEST_CASE_P( AArch64::AEK_DOTPROD | AArch64::AEK_RCPC | AArch64::AEK_SSBS, "8.2-A"), + ARMCPUTestParams("cortex-a78c", "armv8.2-a", "crypto-neon-fp-armv8", + AArch64::AEK_RAS | AArch64::AEK_CRC | + AArch64::AEK_CRYPTO | AArch64::AEK_FP | + AArch64::AEK_SIMD | AArch64::AEK_RAS | + AArch64::AEK_LSE | AArch64::AEK_RDM | + AArch64::AEK_FP16 | AArch64::AEK_DOTPROD | + AArch64::AEK_RCPC | AArch64::AEK_SSBS, + "8.2-A"), ARMCPUTestParams( "neoverse-v1", "armv8.4-a", "crypto-neon-fp-armv8", AArch64::AEK_RAS | AArch64::AEK_SVE | AArch64::AEK_SSBS | @@ -1151,7 +1166,7 @@ INSTANTIATE_TEST_CASE_P( AArch64::AEK_LSE | AArch64::AEK_RDM, "8.2-A")), ); -static constexpr unsigned NumAArch64CPUArchs = 45; +static constexpr unsigned NumAArch64CPUArchs = 46; TEST(TargetParserTest, testAArch64CPUArchList) { SmallVector<StringRef, NumAArch64CPUArchs> List; _______________________________________________ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
