[llvm-branch-commits] [clang] 2b1e25b - [AArch64] Adding ACLE intrinsics for the LS64 extension
Author: Lucas Prates
Date: 2021-01-14T09:43:58Z
New Revision: 2b1e25befefc20f012aa49011f46e11e8530ee21
URL:
https://github.com/llvm/llvm-project/commit/2b1e25befefc20f012aa49011f46e11e8530ee21
DIFF:
https://github.com/llvm/llvm-project/commit/2b1e25befefc20f012aa49011f46e11e8530ee21.diff
LOG: [AArch64] Adding ACLE intrinsics for the LS64 extension
This introduces the ARMv8.7-A LS64 extension's intrinsics for 64 bytes
atomic loads and stores: `__arm_ld64b`, `__arm_st64b`, `__arm_st64bv`,
and `__arm_st64bv0`. These are selected into the LS64 instructions
LD64B, ST64B, ST64BV and ST64BV0, respectively.
Based on patches written by Simon Tatham.
Reviewed By: tmatheson
Differential Revision: https://reviews.llvm.org/D93232
Added:
clang/test/CodeGen/aarch64-ls64.c
llvm/test/CodeGen/AArch64/ls64-intrinsics.ll
Modified:
clang/include/clang/Basic/BuiltinsAArch64.def
clang/lib/Basic/Targets/AArch64.cpp
clang/lib/CodeGen/CGBuiltin.cpp
clang/lib/Headers/arm_acle.h
clang/test/Preprocessor/aarch64-target-features.c
llvm/include/llvm/IR/IntrinsicsAArch64.td
llvm/lib/Target/AArch64/AArch64ISelDAGToDAG.cpp
llvm/lib/Target/AArch64/AArch64InstrInfo.td
Removed:
diff --git a/clang/include/clang/Basic/BuiltinsAArch64.def
b/clang/include/clang/Basic/BuiltinsAArch64.def
index c684105908de..b35510f8b691 100644
--- a/clang/include/clang/Basic/BuiltinsAArch64.def
+++ b/clang/include/clang/Basic/BuiltinsAArch64.def
@@ -99,6 +99,12 @@ BUILTIN(__builtin_arm_tcommit, "v", "n")
BUILTIN(__builtin_arm_tcancel, "vWUIi", "n")
BUILTIN(__builtin_arm_ttest, "WUi", "nc")
+// Armv8.7-A load/store 64-byte intrinsics
+BUILTIN(__builtin_arm_ld64b, "vvC*WUi*", "n")
+BUILTIN(__builtin_arm_st64b, "vv*WUiC*", "n")
+BUILTIN(__builtin_arm_st64bv, "WUiv*WUiC*", "n")
+BUILTIN(__builtin_arm_st64bv0, "WUiv*WUiC*", "n")
+
TARGET_HEADER_BUILTIN(_BitScanForward, "UcUNi*UNi", "nh", "intrin.h",
ALL_MS_LANGUAGES, "")
TARGET_HEADER_BUILTIN(_BitScanReverse, "UcUNi*UNi", "nh", "intrin.h",
ALL_MS_LANGUAGES, "")
TARGET_HEADER_BUILTIN(_BitScanForward64, "UcUNi*ULLi", "nh", "intrin.h",
ALL_MS_LANGUAGES, "")
diff --git a/clang/lib/Basic/Targets/AArch64.cpp
b/clang/lib/Basic/Targets/AArch64.cpp
index 312c822ebb05..f17134623b8b 100644
--- a/clang/lib/Basic/Targets/AArch64.cpp
+++ b/clang/lib/Basic/Targets/AArch64.cpp
@@ -356,6 +356,9 @@ void AArch64TargetInfo::getTargetDefines(const LangOptions
&Opts,
if (Opts.BranchTargetEnforcement)
Builder.defineMacro("__ARM_FEATURE_BTI_DEFAULT", "1");
+ if (HasLS64)
+Builder.defineMacro("__ARM_FEATURE_LS64", "1");
+
switch (ArchKind) {
default:
break;
diff --git a/clang/lib/CodeGen/CGBuiltin.cpp b/clang/lib/CodeGen/CGBuiltin.cpp
index cf84ad34e1ec..7fa4e4d270ad 100644
--- a/clang/lib/CodeGen/CGBuiltin.cpp
+++ b/clang/lib/CodeGen/CGBuiltin.cpp
@@ -8979,6 +8979,46 @@ Value *CodeGenFunction::EmitAArch64BuiltinExpr(unsigned
BuiltinID,
CGM.getIntrinsic(Intrinsic::aarch64_fjcvtzs), Arg);
}
+ if (BuiltinID == AArch64::BI__builtin_arm_ld64b ||
+ BuiltinID == AArch64::BI__builtin_arm_st64b ||
+ BuiltinID == AArch64::BI__builtin_arm_st64bv ||
+ BuiltinID == AArch64::BI__builtin_arm_st64bv0) {
+llvm::Value *MemAddr = EmitScalarExpr(E->getArg(0));
+llvm::Value *ValPtr = EmitScalarExpr(E->getArg(1));
+
+if (BuiltinID == AArch64::BI__builtin_arm_ld64b) {
+ // Load from the address via an LLVM intrinsic, receiving a
+ // tuple of 8 i64 words, and store each one to ValPtr.
+ Function *F = CGM.getIntrinsic(Intrinsic::aarch64_ld64b);
+ llvm::Value *Val = Builder.CreateCall(F, MemAddr);
+ llvm::Value *ToRet;
+ for (size_t i = 0; i < 8; i++) {
+llvm::Value *ValOffsetPtr = Builder.CreateGEP(ValPtr,
Builder.getInt32(i));
+Address Addr(ValOffsetPtr, CharUnits::fromQuantity(8));
+ToRet = Builder.CreateStore(Builder.CreateExtractValue(Val, i), Addr);
+ }
+ return ToRet;
+} else {
+ // Load 8 i64 words from ValPtr, and store them to the address
+ // via an LLVM intrinsic.
+ SmallVector Args;
+ Args.push_back(MemAddr);
+ for (size_t i = 0; i < 8; i++) {
+llvm::Value *ValOffsetPtr = Builder.CreateGEP(ValPtr,
Builder.getInt32(i));
+Address Addr(ValOffsetPtr, CharUnits::fromQuantity(8));
+Args.push_back(Builder.CreateLoad(Addr));
+ }
+
+ auto Intr = (BuiltinID == AArch64::BI__builtin_arm_st64b
+ ? Intrinsic::aarch64_st64b
+ : BuiltinID == AArch64::BI__builtin_arm_st64bv
+ ? Intrinsic::aarch64_st64bv
+ : Intrinsic::aarch64_st64bv0);
+ Function *F = CGM.getIntrinsic(Intr);
+ return Builder.CreateCall(F, Args);
+}
+ }
+
if (BuiltinID == AArch64::BI__clear_cache) {
assert(E->getNumArgs() == 2 && "__
[llvm-branch-commits] [clang] 59fce6b - [NFC] make clang/test/CodeGen/arm_neon_intrinsics.c resistent to function attribute id changes
Author: Jeroen Dobbelaere
Date: 2021-01-07T17:08:15Z
New Revision: 59fce6b0661647062918a47bdb1874950d3938d5
URL:
https://github.com/llvm/llvm-project/commit/59fce6b0661647062918a47bdb1874950d3938d5
DIFF:
https://github.com/llvm/llvm-project/commit/59fce6b0661647062918a47bdb1874950d3938d5.diff
LOG: [NFC] make clang/test/CodeGen/arm_neon_intrinsics.c resistent to function
attribute id changes
When introducing support for @llvm.experimental.noalias.scope.decl, this tests
started failing because it checks
(for no good reason) for a function attribute id of '#8' which now becomes '#9'
Reviewed By: pratlucas
Differential Revision: https://reviews.llvm.org/D94233
Added:
Modified:
clang/test/CodeGen/arm_neon_intrinsics.c
Removed:
diff --git a/clang/test/CodeGen/arm_neon_intrinsics.c
b/clang/test/CodeGen/arm_neon_intrinsics.c
index 9d3f35f48bb76..56e105a41962e 100644
--- a/clang/test/CodeGen/arm_neon_intrinsics.c
+++ b/clang/test/CodeGen/arm_neon_intrinsics.c
@@ -7114,7 +7114,7 @@ uint64x2_t test_vmlal_u32(uint64x2_t a, uint32x2_t b,
uint32x2_t c) {
// CHECK: [[LANE:%.*]] = shufflevector <4 x i16> [[TMP1]], <4 x i16>
[[TMP1]], <4 x i32>
// CHECK: [[TMP2:%.*]] = bitcast <4 x i16> [[B:%.*]] to <8 x i8>
// CHECK: [[TMP3:%.*]] = bitcast <4 x i16> [[LANE]] to <8 x i8>
-// CHECK: [[VMULL2_I:%.*]] = call <4 x i32> @llvm.arm.neon.vmulls.v4i32(<4 x
i16> [[B]], <4 x i16> [[LANE]]) #8
+// CHECK: [[VMULL2_I:%.*]] = call <4 x i32> @llvm.arm.neon.vmulls.v4i32(<4 x
i16> [[B]], <4 x i16> [[LANE]])
// CHECK: [[ADD:%.*]] = add <4 x i32> [[A:%.*]], [[VMULL2_I]]
// CHECK: ret <4 x i32> [[ADD]]
int32x4_t test_vmlal_lane_s16(int32x4_t a, int16x4_t b, int16x4_t c) {
@@ -7127,7 +7127,7 @@ int32x4_t test_vmlal_lane_s16(int32x4_t a, int16x4_t b,
int16x4_t c) {
// CHECK: [[LANE:%.*]] = shufflevector <2 x i32> [[TMP1]], <2 x i32>
[[TMP1]], <2 x i32>
// CHECK: [[TMP2:%.*]] = bitcast <2 x i32> [[B:%.*]] to <8 x i8>
// CHECK: [[TMP3:%.*]] = bitcast <2 x i32> [[LANE]] to <8 x i8>
-// CHECK: [[VMULL2_I:%.*]] = call <2 x i64> @llvm.arm.neon.vmulls.v2i64(<2 x
i32> [[B]], <2 x i32> [[LANE]]) #8
+// CHECK: [[VMULL2_I:%.*]] = call <2 x i64> @llvm.arm.neon.vmulls.v2i64(<2 x
i32> [[B]], <2 x i32> [[LANE]])
// CHECK: [[ADD:%.*]] = add <2 x i64> [[A:%.*]], [[VMULL2_I]]
// CHECK: ret <2 x i64> [[ADD]]
int64x2_t test_vmlal_lane_s32(int64x2_t a, int32x2_t b, int32x2_t c) {
@@ -7140,7 +7140,7 @@ int64x2_t test_vmlal_lane_s32(int64x2_t a, int32x2_t b,
int32x2_t c) {
// CHECK: [[LANE:%.*]] = shufflevector <4 x i16> [[TMP1]], <4 x i16>
[[TMP1]], <4 x i32>
// CHECK: [[TMP2:%.*]] = bitcast <4 x i16> [[B:%.*]] to <8 x i8>
// CHECK: [[TMP3:%.*]] = bitcast <4 x i16> [[LANE]] to <8 x i8>
-// CHECK: [[VMULL2_I:%.*]] = call <4 x i32> @llvm.arm.neon.vmullu.v4i32(<4 x
i16> [[B]], <4 x i16> [[LANE]]) #8
+// CHECK: [[VMULL2_I:%.*]] = call <4 x i32> @llvm.arm.neon.vmullu.v4i32(<4 x
i16> [[B]], <4 x i16> [[LANE]])
// CHECK: [[ADD:%.*]] = add <4 x i32> [[A:%.*]], [[VMULL2_I]]
// CHECK: ret <4 x i32> [[ADD]]
uint32x4_t test_vmlal_lane_u16(uint32x4_t a, uint16x4_t b, uint16x4_t c) {
@@ -7153,7 +7153,7 @@ uint32x4_t test_vmlal_lane_u16(uint32x4_t a, uint16x4_t
b, uint16x4_t c) {
// CHECK: [[LANE:%.*]] = shufflevector <2 x i32> [[TMP1]], <2 x i32>
[[TMP1]], <2 x i32>
// CHECK: [[TMP2:%.*]] = bitcast <2 x i32> [[B:%.*]] to <8 x i8>
// CHECK: [[TMP3:%.*]] = bitcast <2 x i32> [[LANE]] to <8 x i8>
-// CHECK: [[VMULL2_I:%.*]] = call <2 x i64> @llvm.arm.neon.vmullu.v2i64(<2 x
i32> [[B]], <2 x i32> [[LANE]]) #8
+// CHECK: [[VMULL2_I:%.*]] = call <2 x i64> @llvm.arm.neon.vmullu.v2i64(<2 x
i32> [[B]], <2 x i32> [[LANE]])
// CHECK: [[ADD:%.*]] = add <2 x i64> [[A:%.*]], [[VMULL2_I]]
// CHECK: ret <2 x i64> [[ADD]]
uint64x2_t test_vmlal_lane_u32(uint64x2_t a, uint32x2_t b, uint32x2_t c) {
@@ -7618,7 +7618,7 @@ uint64x2_t test_vmlsl_u32(uint64x2_t a, uint32x2_t b,
uint32x2_t c) {
// CHECK: [[LANE:%.*]] = shufflevector <4 x i16> [[TMP1]], <4 x i16>
[[TMP1]], <4 x i32>
// CHECK: [[TMP2:%.*]] = bitcast <4 x i16> [[B:%.*]] to <8 x i8>
// CHECK: [[TMP3:%.*]] = bitcast <4 x i16> [[LANE]] to <8 x i8>
-// CHECK: [[VMULL2_I:%.*]] = call <4 x i32> @llvm.arm.neon.vmulls.v4i32(<4 x
i16> [[B]], <4 x i16> [[LANE]]) #8
+// CHECK: [[VMULL2_I:%.*]] = call <4 x i32> @llvm.arm.neon.vmulls.v4i32(<4 x
i16> [[B]], <4 x i16> [[LANE]])
// CHECK: [[SUB:%.*]] = sub <4 x i32> [[A:%.*]], [[VMULL2_I]]
// CHECK: ret <4 x i32> [[SUB]]
int32x4_t test_vmlsl_lane_s16(int32x4_t a, int16x4_t b, int16x4_t c) {
@@ -7631,7 +7631,7 @@ int32x4_t test_vmlsl_lane_s16(int32x4_t a, int16x4_t b,
int16x4_t c) {
// CHECK: [[LANE:%.*]] = shufflevector <2 x i32> [[TMP1]], <2 x i32>
[[TMP1]], <2 x i32>
// CHECK: [[TMP2:%.*]] = bitcast <2 x i32> [[B:%.*]] to <8 x i8>
// CHECK: [[TMP3:%.*]] = bitca
[llvm-branch-commits] [llvm] b5bbb4b - [NFC][AArch64] Move AArch64 MSR/MRS into a new decoder namespace
Author: Lucas Prates
Date: 2020-12-17T13:40:10Z
New Revision: b5bbb4b2b75302d1d8080529ec7e9737a507ff1d
URL:
https://github.com/llvm/llvm-project/commit/b5bbb4b2b75302d1d8080529ec7e9737a507ff1d
DIFF:
https://github.com/llvm/llvm-project/commit/b5bbb4b2b75302d1d8080529ec7e9737a507ff1d.diff
LOG: [NFC][AArch64] Move AArch64 MSR/MRS into a new decoder namespace
This removes the general forms of the AArch64 MSR and MRS instructions
from the same decoding table that contains many more specific
instructions that supersede them. They're now in a separate decoding
table of their own, called "Fallback", which is only consulted in the
event of the main decoder table failing to produce an answer.
This should avoid decoding conflicts on future specialized instructions
in the MSR space.
Patch written by Simon Tatham.
Reviewed By: ostannard
Differential Revision: https://reviews.llvm.org/D91771
Added:
Modified:
llvm/lib/Target/AArch64/AArch64InstrFormats.td
llvm/lib/Target/AArch64/Disassembler/AArch64Disassembler.cpp
Removed:
diff --git a/llvm/lib/Target/AArch64/AArch64InstrFormats.td
b/llvm/lib/Target/AArch64/AArch64InstrFormats.td
index 2756e4dc8aa4..0f6ae93742bf 100644
--- a/llvm/lib/Target/AArch64/AArch64InstrFormats.td
+++ b/llvm/lib/Target/AArch64/AArch64InstrFormats.td
@@ -1447,6 +1447,7 @@ class MRSI : RtSystemI<1, (outs GPR64:$Rt), (ins
mrs_sysreg_op:$systemreg),
"mrs", "\t$Rt, $systemreg"> {
bits<16> systemreg;
let Inst{20-5} = systemreg;
+ let DecoderNamespace = "Fallback";
}
// FIXME: Some of these def NZCV, others don't. Best way to model that?
@@ -1456,6 +1457,7 @@ class MSRI : RtSystemI<0, (outs), (ins
msr_sysreg_op:$systemreg, GPR64:$Rt),
"msr", "\t$systemreg, $Rt"> {
bits<16> systemreg;
let Inst{20-5} = systemreg;
+ let DecoderNamespace = "Fallback";
}
def SystemPStateFieldWithImm0_15Operand : AsmOperandClass {
diff --git a/llvm/lib/Target/AArch64/Disassembler/AArch64Disassembler.cpp
b/llvm/lib/Target/AArch64/Disassembler/AArch64Disassembler.cpp
index 1ff4abb34054..e1a96ce8bdb1 100644
--- a/llvm/lib/Target/AArch64/Disassembler/AArch64Disassembler.cpp
+++ b/llvm/lib/Target/AArch64/Disassembler/AArch64Disassembler.cpp
@@ -267,8 +267,16 @@ DecodeStatus AArch64Disassembler::getInstruction(MCInst
&MI, uint64_t &Size,
uint32_t Insn =
(Bytes[3] << 24) | (Bytes[2] << 16) | (Bytes[1] << 8) | (Bytes[0] << 0);
- // Calling the auto-generated decoder function.
- return decodeInstruction(DecoderTable32, MI, Insn, Address, this, STI);
+ const uint8_t *Tables[] = {DecoderTable32, DecoderTableFallback32};
+
+ for (auto Table : Tables) {
+DecodeStatus Result =
+decodeInstruction(Table, MI, Insn, Address, this, STI);
+if (Result != MCDisassembler::Fail)
+ return Result;
+ }
+
+ return MCDisassembler::Fail;
}
static MCSymbolizer *
___
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[llvm-branch-commits] [llvm] 83ea17f - [NFC][AArch64] Capturing multiple feature requirements in AsmParser messages
Author: Lucas Prates
Date: 2020-12-17T13:44:17Z
New Revision: 83ea17fc5f742abb0ab0757ef9e667a4e2b39ea8
URL:
https://github.com/llvm/llvm-project/commit/83ea17fc5f742abb0ab0757ef9e667a4e2b39ea8
DIFF:
https://github.com/llvm/llvm-project/commit/83ea17fc5f742abb0ab0757ef9e667a4e2b39ea8.diff
LOG: [NFC][AArch64] Capturing multiple feature requirements in AsmParser
messages
This enables the capturing of multiple required features in the AArch64
AsmParser's SysAlias error messages.
Reviewed By: ostannard
Differential Revision: https://reviews.llvm.org/D92388
Added:
Modified:
llvm/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp
llvm/test/MC/AArch64/armv8.2a-at.s
llvm/test/MC/AArch64/armv8.2a-persistent-memory.s
llvm/test/MC/AArch64/armv8.4a-tlb.s
llvm/test/MC/AArch64/armv8.5a-mte.s
llvm/test/MC/AArch64/armv8.5a-persistent-memory.s
llvm/test/MC/AArch64/armv8.5a-predres.s
llvm/test/MC/AArch64/directive-arch_extension-negative.s
Removed:
diff --git a/llvm/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp
b/llvm/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp
index ae95d54b2d90..f3514f1d47f7 100644
--- a/llvm/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp
+++ b/llvm/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp
@@ -2907,14 +2907,13 @@ static void setRequiredFeatureString(FeatureBitset FBS,
std::string &Str) {
else if (FBS[AArch64::HasV8_6aOps])
Str += "ARMv8.6a";
else {
-auto ext = std::find_if(std::begin(ExtensionMap),
- std::end(ExtensionMap),
- [&](const Extension& e)
+SmallVector ExtMatches;
+for (const auto& Ext : ExtensionMap) {
// Use & in case multiple features are enabled
- { return (FBS & e.Features) != FeatureBitset(); }
-);
-
-Str += ext != std::end(ExtensionMap) ? ext->Name : "(unknown)";
+ if ((FBS & Ext.Features) != FeatureBitset())
+ExtMatches.push_back(Ext.Name);
+}
+Str += !ExtMatches.empty() ? llvm::join(ExtMatches, ", ") : "(unknown)";
}
}
@@ -2959,7 +2958,7 @@ bool AArch64AsmParser::parseSysAlias(StringRef Name,
SMLoc NameLoc,
if (!IC)
return TokError("invalid operand for IC instruction");
else if (!IC->haveFeatures(getSTI().getFeatureBits())) {
- std::string Str("IC " + std::string(IC->Name) + " requires ");
+ std::string Str("IC " + std::string(IC->Name) + " requires: ");
setRequiredFeatureString(IC->getRequiredFeatures(), Str);
return TokError(Str.c_str());
}
@@ -2969,7 +2968,7 @@ bool AArch64AsmParser::parseSysAlias(StringRef Name,
SMLoc NameLoc,
if (!DC)
return TokError("invalid operand for DC instruction");
else if (!DC->haveFeatures(getSTI().getFeatureBits())) {
- std::string Str("DC " + std::string(DC->Name) + " requires ");
+ std::string Str("DC " + std::string(DC->Name) + " requires: ");
setRequiredFeatureString(DC->getRequiredFeatures(), Str);
return TokError(Str.c_str());
}
@@ -2979,7 +2978,7 @@ bool AArch64AsmParser::parseSysAlias(StringRef Name,
SMLoc NameLoc,
if (!AT)
return TokError("invalid operand for AT instruction");
else if (!AT->haveFeatures(getSTI().getFeatureBits())) {
- std::string Str("AT " + std::string(AT->Name) + " requires ");
+ std::string Str("AT " + std::string(AT->Name) + " requires: ");
setRequiredFeatureString(AT->getRequiredFeatures(), Str);
return TokError(Str.c_str());
}
@@ -2989,7 +2988,7 @@ bool AArch64AsmParser::parseSysAlias(StringRef Name,
SMLoc NameLoc,
if (!TLBI)
return TokError("invalid operand for TLBI instruction");
else if (!TLBI->haveFeatures(getSTI().getFeatureBits())) {
- std::string Str("TLBI " + std::string(TLBI->Name) + " requires ");
+ std::string Str("TLBI " + std::string(TLBI->Name) + " requires: ");
setRequiredFeatureString(TLBI->getRequiredFeatures(), Str);
return TokError(Str.c_str());
}
@@ -3000,7 +2999,7 @@ bool AArch64AsmParser::parseSysAlias(StringRef Name,
SMLoc NameLoc,
return TokError("invalid operand for prediction restriction
instruction");
else if (!PRCTX->haveFeatures(getSTI().getFeatureBits())) {
std::string Str(
- Mnemonic.upper() + std::string(PRCTX->Name) + " requires ");
+ Mnemonic.upper() + std::string(PRCTX->Name) + " requires: ");
setRequiredFeatureString(PRCTX->getRequiredFeatures(), Str);
return TokError(Str.c_str());
}
diff --git a/llvm/test/MC/AArch64/armv8.2a-at.s
b/llvm/test/MC/AArch64/armv8.2a-at.s
index 3c26fb9ea3a1..1e8b4ca5a93d 100644
--- a/llvm/test/MC/AArch64/armv8.2a-at.s
+++ b/llvm/test/MC/AArch64/armv8.2a-at.s
@@ -7,5 +7,5 @@
at s1e1wp, x2
// CHECK: at s1e1rp, x1 // encoding: [0x01,0x79,0x08,0xd5]
// CHECK: at s1e1wp, x2 // encoding: [0x22,0x79,0x08,0xd5]
-// ERROR: error: AT S1E1RP requir
[llvm-branch-commits] [llvm] 42b92b3 - [ARM][AArch64] Adding basic support for the v8.7-A architecture
Author: Lucas Prates
Date: 2020-12-17T13:45:08Z
New Revision: 42b92b31b8b8ee9fdcd68adfe57db11561a5edcd
URL:
https://github.com/llvm/llvm-project/commit/42b92b31b8b8ee9fdcd68adfe57db11561a5edcd
DIFF:
https://github.com/llvm/llvm-project/commit/42b92b31b8b8ee9fdcd68adfe57db11561a5edcd.diff
LOG: [ARM][AArch64] Adding basic support for the v8.7-A architecture
This introduces support for the v8.7-A architecture through a new
subtarget feature called "v8.7a". It adds two new "WFET" and "WFIT"
instructions, the nXS limited-TLB-maintenance qualifier for DSB and TLBI
instructions, a new CPU id register, ID_AA64ISAR2_EL1, and the new
HCRX_EL2 system register.
Based on patches written by Simon Tatham and Victor Campos.
Reviewed By: ostannard
Differential Revision: https://reviews.llvm.org/D91772
Added:
llvm/test/MC/AArch64/armv8.7a-hcx.s
llvm/test/MC/AArch64/armv8.7a-wfxt.s
llvm/test/MC/AArch64/armv8.7a-xs.s
llvm/test/MC/Disassembler/AArch64/armv8.7a-hcx.txt
llvm/test/MC/Disassembler/AArch64/armv8.7a-wfxt.txt
llvm/test/MC/Disassembler/AArch64/armv8.7a-xs.txt
Modified:
llvm/lib/Target/AArch64/AArch64.td
llvm/lib/Target/AArch64/AArch64InstrFormats.td
llvm/lib/Target/AArch64/AArch64InstrInfo.td
llvm/lib/Target/AArch64/AArch64Subtarget.h
llvm/lib/Target/AArch64/AArch64SystemOperands.td
llvm/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp
llvm/lib/Target/AArch64/MCTargetDesc/AArch64InstPrinter.cpp
llvm/lib/Target/AArch64/MCTargetDesc/AArch64InstPrinter.h
llvm/lib/Target/AArch64/Utils/AArch64BaseInfo.cpp
llvm/lib/Target/AArch64/Utils/AArch64BaseInfo.h
llvm/lib/Target/ARM/ARMSubtarget.h
llvm/test/MC/AArch64/arm64-system-encoding.s
llvm/test/MC/AArch64/basic-a64-diagnostics.s
llvm/test/MC/Disassembler/AArch64/basic-a64-instructions.txt
Removed:
diff --git a/llvm/lib/Target/AArch64/AArch64.td
b/llvm/lib/Target/AArch64/AArch64.td
index 5bafe430a1b4..fd7894aa3fcb 100644
--- a/llvm/lib/Target/AArch64/AArch64.td
+++ b/llvm/lib/Target/AArch64/AArch64.td
@@ -400,6 +400,15 @@ def FeatureMatMulFP32 : SubtargetFeature<"f32mm",
"HasMatMulFP32",
def FeatureMatMulFP64 : SubtargetFeature<"f64mm", "HasMatMulFP64",
"true", "Enable Matrix Multiply FP64 Extension", [FeatureSVE]>;
+def FeatureXS : SubtargetFeature<"xs", "HasXS",
+"true", "Enable Armv8.7-A limited-TLB-maintenance instruction">;
+
+def FeatureWFxT : SubtargetFeature<"wfxt", "HasWFxT",
+"true", "Enable Armv8.7-A WFET and WFIT instruction">;
+
+def FeatureHCX : SubtargetFeature<
+"hcx", "HasHCX", "true", "Enable Armv8.7-A HCRX_EL2 system register">;
+
def FeatureFineGrainedTraps : SubtargetFeature<"fgt", "HasFineGrainedTraps",
"true", "Enable fine grained virtualization traps extension">;
@@ -440,6 +449,10 @@ def HasV8_6aOps : SubtargetFeature<
[HasV8_5aOps, FeatureAMVS, FeatureBF16, FeatureFineGrainedTraps,
FeatureEnhancedCounterVirtualization, FeatureMatMulInt8]>;
+def HasV8_7aOps : SubtargetFeature<
+ "v8.7a", "HasV8_7aOps", "true", "Support ARM v8.7a instructions",
+ [HasV8_6aOps, FeatureXS, FeatureWFxT, FeatureHCX]>;
+
def HasV8_0rOps : SubtargetFeature<
"v8r", "HasV8_0rOps", "true", "Support ARM v8r instructions",
[//v8.1
diff --git a/llvm/lib/Target/AArch64/AArch64InstrFormats.td
b/llvm/lib/Target/AArch64/AArch64InstrFormats.td
index 0f6ae93742bf..3c19a5bad573 100644
--- a/llvm/lib/Target/AArch64/AArch64InstrFormats.td
+++ b/llvm/lib/Target/AArch64/AArch64InstrFormats.td
@@ -1297,8 +1297,9 @@ class SimpleSystemI
-: BaseSystemI,
+class RtSystemI pattern = []>
+: BaseSystemI,
Sched<[WriteSys]> {
bits<5> Rt;
let Inst{4-0} = Rt;
@@ -1326,6 +1327,16 @@ class TMSystemI CRm, string asm, list
pattern>
let Inst{4-0} = Rt;
}
+// System instructions that pass a register argument
+// This class assumes the register is for input rather than output.
+class RegInputSystemI CRm, bits<3> Op2, string asm,
+ list pattern = []>
+: RtSystemI<0, (outs), (ins GPR64:$Rt), asm, "\t$Rt", pattern> {
+ let Inst{20-12} = 0b000110001;
+ let Inst{11-8} = CRm;
+ let Inst{7-5} = Op2;
+}
+
// System instructions for transactional memory - no operand
class TMSystemINoOperand CRm, string asm, list pattern>
: TMBaseSystemI<0b0, CRm, 0b011, (outs), (ins), asm, "", pattern> {
@@ -1366,6 +1377,14 @@ def barrier_op : Operand {
let PrintMethod = "printBarrierOption";
let ParserMatchClass = BarrierAsmOperand;
}
+def BarriernXSAsmOperand : AsmOperandClass {
+ let Name = "BarriernXS";
+ let ParserMethod = "tryParseBarriernXSOperand";
+}
+def barrier_nxs_op : Operand {
+ let PrintMethod = "printBarriernXSOption";
+ let ParserMatchClass = BarriernXSAsmOperand;
+}
class CRmSystemI opc, string asm,
list pattern = []>
: SimpleSystemI<0, (ins crmtype:$CRm), asm, "\t$CRm", pattern>,
diff --git
[llvm-branch-commits] [llvm] 97c006a - [AArch64] Add a GPR64x8 register class
Author: Lucas Prates
Date: 2020-12-17T13:45:46Z
New Revision: 97c006aabb6c831d68204bcb4aad8670af695618
URL:
https://github.com/llvm/llvm-project/commit/97c006aabb6c831d68204bcb4aad8670af695618
DIFF:
https://github.com/llvm/llvm-project/commit/97c006aabb6c831d68204bcb4aad8670af695618.diff
LOG: [AArch64] Add a GPR64x8 register class
This adds a GPR64x8 register class that will be needed as the data
operand to the LD64B/ST64B family of instructions in the v8.7-A
Accelerator Extension, which load or store a contiguous range of eight
x-regs. It has to be its own register class so that register allocation
will have visibility of the full set of registers actually read/written
by the instructions, which will be needed when we add intrinsics and/or
inline asm access to this piece of architecture.
Patch written by Simon Tatham.
Reviewed By: ostannard
Differential Revision: https://reviews.llvm.org/D91774
Added:
Modified:
llvm/lib/Target/AArch64/AArch64RegisterInfo.td
llvm/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp
llvm/lib/Target/AArch64/Disassembler/AArch64Disassembler.cpp
llvm/lib/Target/AArch64/MCTargetDesc/AArch64InstPrinter.cpp
llvm/lib/Target/AArch64/MCTargetDesc/AArch64InstPrinter.h
Removed:
diff --git a/llvm/lib/Target/AArch64/AArch64RegisterInfo.td
b/llvm/lib/Target/AArch64/AArch64RegisterInfo.td
index 54b351fda053..28d1988b8a5f 100644
--- a/llvm/lib/Target/AArch64/AArch64RegisterInfo.td
+++ b/llvm/lib/Target/AArch64/AArch64RegisterInfo.td
@@ -711,6 +711,32 @@ def XSeqPairClassOperand :
//===- END: v8.1a atomic CASP register operands
---===//
+//===--===//
+// Armv8.7a accelerator extension register operands: 8 consecutive GPRs
+// starting with an even one
+
+let Namespace = "AArch64" in {
+ foreach i = 0-7 in
+def "x8sub_"#i : SubRegIndex<64, !mul(64, i)>;
+}
+
+def Tuples8X : RegisterTuples<
+ !foreach(i, [0,1,2,3,4,5,6,7], !cast("x8sub_"#i)),
+ !foreach(i, [0,1,2,3,4,5,6,7], (trunc (decimate (rotl GPR64, i), 2), 12))>;
+
+def GPR64x8Class : RegisterClass<"AArch64", [i64], 64, (trunc Tuples8X, 12)>;
+def GPR64x8AsmOp : AsmOperandClass {
+ let Name = "GPR64x8";
+ let ParserMethod = "tryParseGPR64x8";
+ let RenderMethod = "addRegOperands";
+}
+def GPR64x8 : RegisterOperand {
+ let ParserMatchClass = GPR64x8AsmOp;
+ let PrintMethod = "printGPR64x8";
+}
+
+//===- END: v8.7a accelerator extension register operands
-===//
+
// SVE predicate registers
def P0: AArch64Reg<0, "p0">, DwarfRegNum<[48]>;
def P1: AArch64Reg<1, "p1">, DwarfRegNum<[49]>;
diff --git a/llvm/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp
b/llvm/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp
index 6a251f0d346c..10ab4830e9ee 100644
--- a/llvm/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp
+++ b/llvm/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp
@@ -257,6 +257,7 @@ class AArch64AsmParser : public MCTargetAsmParser {
OperandMatchResultTy tryParseVectorList(OperandVector &Operands,
bool ExpectMatch = false);
OperandMatchResultTy tryParseSVEPattern(OperandVector &Operands);
+ OperandMatchResultTy tryParseGPR64x8(OperandVector &Operands);
public:
enum AArch64MatchResultTy {
@@ -1170,6 +1171,12 @@ class AArch64Operand : public MCParsedAsmOperand {
AArch64MCRegisterClasses[AArch64::GPR32RegClassID].contains(Reg.RegNum);
}
+ bool isGPR64x8() const {
+return Kind == k_Register && Reg.Kind == RegKind::Scalar &&
+ AArch64MCRegisterClasses[AArch64::GPR64x8ClassRegClassID].contains(
+ Reg.RegNum);
+ }
+
bool isWSeqPair() const {
return Kind == k_Register && Reg.Kind == RegKind::Scalar &&
AArch64MCRegisterClasses[AArch64::WSeqPairsClassRegClassID].contains(
@@ -6291,3 +6298,26 @@ AArch64AsmParser::tryParseSVEPattern(OperandVector
&Operands) {
return MatchOperand_Success;
}
+
+OperandMatchResultTy
+AArch64AsmParser::tryParseGPR64x8(OperandVector &Operands) {
+ SMLoc SS = getLoc();
+
+ unsigned XReg;
+ if (tryParseScalarRegister(XReg) != MatchOperand_Success)
+return MatchOperand_NoMatch;
+
+ MCContext &ctx = getContext();
+ const MCRegisterInfo *RI = ctx.getRegisterInfo();
+ int X8Reg = RI->getMatchingSuperReg(
+ XReg, AArch64::x8sub_0,
+ &AArch64MCRegisterClasses[AArch64::GPR64x8ClassRegClassID]);
+ if (!X8Reg) {
+Error(SS, "expected an even-numbered x-register in the range [x0,x22]");
+return MatchOperand_ParseFail;
+ }
+
+ Operands.push_back(
+ AArch64Operand::CreateReg(X8Reg, RegKind::Scalar, SS, getLoc(), ctx));
+ return MatchOperand_Success;
+}
diff --git a/llvm/lib/Target/AArch64/Disassembler/AArch64Disassembler.cpp
b/llvm/lib/Target/AArch64/Disassembler/AArch64Disassembler.cpp
index e1a96ce8bdb1
[llvm-branch-commits] [llvm] 3138891 - [AArch64] Adding the v8.7-A LD64B/ST64B Accelerator extension
Author: Lucas Prates
Date: 2020-12-17T13:46:23Z
New Revision: 313889191ea14e978635b5cdf8838f3212d068a4
URL:
https://github.com/llvm/llvm-project/commit/313889191ea14e978635b5cdf8838f3212d068a4
DIFF:
https://github.com/llvm/llvm-project/commit/313889191ea14e978635b5cdf8838f3212d068a4.diff
LOG: [AArch64] Adding the v8.7-A LD64B/ST64B Accelerator extension
This adds support for the v8.7-A LD64B/ST64B Accelerator extension
through a subtarget feature called "ls64". It adds four 64-byte
load/store instructions with an operand in the new GPR64x8 register
class, and one system register that's part of the same extension.
Based on patches written by Simon Tatham.
Reviewed By: ostannard
Differential Revision: https://reviews.llvm.org/D91775
Added:
llvm/test/MC/AArch64/armv8.7a-ls64.s
llvm/test/MC/Disassembler/AArch64/armv8.7a-ls64.txt
Modified:
llvm/lib/Target/AArch64/AArch64.td
llvm/lib/Target/AArch64/AArch64InstrFormats.td
llvm/lib/Target/AArch64/AArch64InstrInfo.td
llvm/lib/Target/AArch64/AArch64Subtarget.h
llvm/lib/Target/AArch64/AArch64SystemOperands.td
llvm/lib/Target/AArch64/Disassembler/AArch64Disassembler.cpp
Removed:
diff --git a/llvm/lib/Target/AArch64/AArch64.td
b/llvm/lib/Target/AArch64/AArch64.td
index fd7894aa3fcb..69f2e31ecfb4 100644
--- a/llvm/lib/Target/AArch64/AArch64.td
+++ b/llvm/lib/Target/AArch64/AArch64.td
@@ -409,6 +409,9 @@ def FeatureWFxT : SubtargetFeature<"wfxt", "HasWFxT",
def FeatureHCX : SubtargetFeature<
"hcx", "HasHCX", "true", "Enable Armv8.7-A HCRX_EL2 system register">;
+def FeatureLS64 : SubtargetFeature<"ls64", "HasLS64",
+"true", "Enable Armv8.7-A LD64B/ST64B Accelerator Extension">;
+
def FeatureFineGrainedTraps : SubtargetFeature<"fgt", "HasFineGrainedTraps",
"true", "Enable fine grained virtualization traps extension">;
diff --git a/llvm/lib/Target/AArch64/AArch64InstrFormats.td
b/llvm/lib/Target/AArch64/AArch64InstrFormats.td
index 3c19a5bad573..3335071fe487 100644
--- a/llvm/lib/Target/AArch64/AArch64InstrFormats.td
+++ b/llvm/lib/Target/AArch64/AArch64InstrFormats.td
@@ -11255,6 +11255,35 @@ multiclass STOPregister {
!cast(instr # "X")>;
}
+class LoadStore64B_base opc, string asm_inst, string asm_ops,
+dag iops, dag oops, list pat>
+: I,
+ Sched<[]> /* FIXME: fill in scheduling details once known */ {
+ bits<5> Rt;
+ bits<5> Rn;
+ let Inst{31-21} = 0b101;
+ let Inst{15}= 1;
+ let Inst{14-12} = opc;
+ let Inst{11-10} = 0b00;
+ let Inst{9-5} = Rn;
+ let Inst{4-0} = Rt;
+
+ let Predicates = [HasV8_7a];
+}
+
+class LoadStore64B opc, string asm_inst, dag iops, dag oops,
+ list pat = []>
+: LoadStore64B_base {
+ let Inst{20-16} = 0b1;
+}
+
+class Store64BV opc, string asm_inst, list pat = []>
+: LoadStore64B_base {
+ bits<5> Rs;
+ let Inst{20-16} = Rs;
+}
+
//
// Allow the size specifier tokens to be upper case, not just lower.
def : TokenAlias<".4B", ".4b">; // Add dot product
diff --git a/llvm/lib/Target/AArch64/AArch64InstrInfo.td
b/llvm/lib/Target/AArch64/AArch64InstrInfo.td
index d366c3c4d04c..97b2ea3c345a 100644
--- a/llvm/lib/Target/AArch64/AArch64InstrInfo.td
+++ b/llvm/lib/Target/AArch64/AArch64InstrInfo.td
@@ -155,6 +155,8 @@ def HasXS: Predicate<"Subtarget->hasXS()">,
AssemblerPredicate<(all_of FeatureXS), "xs">;
def HasWFxT : Predicate<"Subtarget->hasWFxT()">,
AssemblerPredicate<(all_of FeatureWFxT), "wfxt">;
+def HasLS64 : Predicate<"Subtarget->hasLS64()">,
+ AssemblerPredicate<(all_of FeatureLS64), "ls64">;
def IsLE : Predicate<"Subtarget->isLittleEndian()">;
def IsBE : Predicate<"!Subtarget->isLittleEndian()">;
def IsWindows: Predicate<"Subtarget->isTargetWindows()">;
@@ -7745,6 +7747,15 @@ let AddedComplexity = 10 in {
// FIXME: add SVE dot-product patterns.
}
+let Predicates = [HasLS64] in {
+ def LD64B: LoadStore64B<0b101, "ld64b", (ins GPR64sp:$Rn),
+ (outs GPR64x8:$Rt)>;
+ def ST64B: LoadStore64B<0b001, "st64b", (ins GPR64sp:$Rn, GPR64x8:$Rt),
+ (outs)>;
+ def ST64BV: Store64BV<0b011, "st64bv">;
+ def ST64BV0: Store64BV<0b010, "st64bv0">;
+}
+
include "AArch64InstrAtomics.td"
include "AArch64SVEInstrInfo.td"
diff --git a/llvm/lib/Target/AArch64/AArch64Subtarget.h
b/llvm/lib/Target/AArch64/AArch64Subtarget.h
index 575542d1b6aa..2a9426cf8c30 100644
--- a/llvm/lib/Target/AArch64/AArch64Subtarget.h
+++ b/llvm/lib/Target/AArch64/AArch64Subtarget.h
@@ -172,6 +172,7 @@ class AArch64Subtarget final : public
AArch64GenSubtargetInfo {
bool HasXS = false;
bool HasWFxT = fal
[llvm-branch-commits] [llvm] c4d851b - [ARM][AAarch64] Initial command-line support for v8.7-A
Author: Lucas Prates
Date: 2020-12-17T13:47:28Z
New Revision: c4d851b079037e9b7dd3f8613dd1c8a4f3db99fa
URL:
https://github.com/llvm/llvm-project/commit/c4d851b079037e9b7dd3f8613dd1c8a4f3db99fa
DIFF:
https://github.com/llvm/llvm-project/commit/c4d851b079037e9b7dd3f8613dd1c8a4f3db99fa.diff
LOG: [ARM][AAarch64] Initial command-line support for v8.7-A
This introduces command-line support for the 'armv8.7-a' architecture name
(and an alias without the '-', as usual), and for the 'ls64' extension name.
Based on patches written by Simon Tatham.
Reviewed By: ostannard
Differential Revision: https://reviews.llvm.org/D91776
Added:
clang/test/Driver/aarch64-ls64.c
Modified:
clang/lib/Basic/Targets/AArch64.cpp
clang/lib/Basic/Targets/AArch64.h
clang/lib/Driver/ToolChains/Arch/AArch64.cpp
clang/test/Driver/aarch64-cpus.c
llvm/include/llvm/Support/AArch64TargetParser.def
llvm/include/llvm/Support/AArch64TargetParser.h
llvm/lib/Support/AArch64TargetParser.cpp
llvm/lib/Support/ARMTargetParser.cpp
llvm/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp
llvm/unittests/Support/TargetParserTest.cpp
Removed:
diff --git a/clang/lib/Basic/Targets/AArch64.cpp
b/clang/lib/Basic/Targets/AArch64.cpp
index c8162dd55220..c1abe8e9f75b 100644
--- a/clang/lib/Basic/Targets/AArch64.cpp
+++ b/clang/lib/Basic/Targets/AArch64.cpp
@@ -196,6 +196,12 @@ void AArch64TargetInfo::getTargetDefinesARMV86A(const
LangOptions &Opts,
getTargetDefinesARMV85A(Opts, Builder);
}
+void AArch64TargetInfo::getTargetDefinesARMV87A(const LangOptions &Opts,
+MacroBuilder &Builder) const {
+ // Also include the Armv8.6 defines
+ getTargetDefinesARMV86A(Opts, Builder);
+}
+
void AArch64TargetInfo::getTargetDefines(const LangOptions &Opts,
MacroBuilder &Builder) const {
// Target identification.
@@ -371,6 +377,9 @@ void AArch64TargetInfo::getTargetDefines(const LangOptions
&Opts,
case llvm::AArch64::ArchKind::ARMV8_6A:
getTargetDefinesARMV86A(Opts, Builder);
break;
+ case llvm::AArch64::ArchKind::ARMV8_7A:
+getTargetDefinesARMV87A(Opts, Builder);
+break;
}
// All of the __sync_(bool|val)_compare_and_swap_(1|2|4|8) builtins work.
@@ -411,6 +420,7 @@ bool
AArch64TargetInfo::handleTargetFeatures(std::vector &Features,
HasFP16FML = false;
HasMTE = false;
HasTME = false;
+ HasLS64 = false;
HasMatMul = false;
HasBFloat16 = false;
HasSVE2 = false;
@@ -486,6 +496,8 @@ bool
AArch64TargetInfo::handleTargetFeatures(std::vector &Features,
ArchKind = llvm::AArch64::ArchKind::ARMV8_5A;
if (Feature == "+v8.6a")
ArchKind = llvm::AArch64::ArchKind::ARMV8_6A;
+if (Feature == "+v8.7a")
+ ArchKind = llvm::AArch64::ArchKind::ARMV8_7A;
if (Feature == "+v8r")
ArchKind = llvm::AArch64::ArchKind::ARMV8R;
if (Feature == "+fullfp16")
@@ -504,6 +516,8 @@ bool
AArch64TargetInfo::handleTargetFeatures(std::vector &Features,
HasBFloat16 = true;
if (Feature == "+lse")
HasLSE = true;
+if (Feature == "+ls64")
+ HasLS64 = true;
}
setDataLayout();
diff --git a/clang/lib/Basic/Targets/AArch64.h
b/clang/lib/Basic/Targets/AArch64.h
index a70abb7bfd90..bd576680077e 100644
--- a/clang/lib/Basic/Targets/AArch64.h
+++ b/clang/lib/Basic/Targets/AArch64.h
@@ -36,6 +36,7 @@ class LLVM_LIBRARY_VISIBILITY AArch64TargetInfo : public
TargetInfo {
bool HasFP16FML;
bool HasMTE;
bool HasTME;
+ bool HasLS64;
bool HasMatMul;
bool HasSVE2;
bool HasSVE2AES;
@@ -81,6 +82,8 @@ class LLVM_LIBRARY_VISIBILITY AArch64TargetInfo : public
TargetInfo {
MacroBuilder &Builder) const;
void getTargetDefinesARMV86A(const LangOptions &Opts,
MacroBuilder &Builder) const;
+ void getTargetDefinesARMV87A(const LangOptions &Opts,
+ MacroBuilder &Builder) const;
void getTargetDefines(const LangOptions &Opts,
MacroBuilder &Builder) const override;
diff --git a/clang/lib/Driver/ToolChains/Arch/AArch64.cpp
b/clang/lib/Driver/ToolChains/Arch/AArch64.cpp
index 13e4cac292d0..a5e632fd8cdb 100644
--- a/clang/lib/Driver/ToolChains/Arch/AArch64.cpp
+++ b/clang/lib/Driver/ToolChains/Arch/AArch64.cpp
@@ -79,9 +79,10 @@ static bool DecodeAArch64Features(const Driver &D, StringRef
text,
else
return false;
-// +sve implies +f32mm if the base architecture is v8.6A
+// +sve implies +f32mm if the base architecture is v8.6A or v8.7A
// it isn't the case in general that sve implies both f64mm and f32mm
-if ((ArchKind == llvm::AArch64::ArchKind::ARMV8_6A) && Feature == "sve")
+if ((ArchKind == llvm::AArch64::ArchKind::ARMV8_6A ||
+ ArchKind == llvm::AArch64::ArchKind::ARMV8_7A) && Feature ==
[llvm-branch-commits] [llvm] c5046eb - [ARM] Adding v8.7-A command-line support for the ARM target
Author: Lucas Prates
Date: 2020-12-17T13:48:54Z
New Revision: c5046ebdf6e4be9300677c538ecaa61648c31248
URL:
https://github.com/llvm/llvm-project/commit/c5046ebdf6e4be9300677c538ecaa61648c31248
DIFF:
https://github.com/llvm/llvm-project/commit/c5046ebdf6e4be9300677c538ecaa61648c31248.diff
LOG: [ARM] Adding v8.7-A command-line support for the ARM target
This extends the command-line support for the 'armv8.7-a' architecture
name to the ARM target.
Based on a patch written by Momchil Velikov.
Reviewed By: ostannard
Differential Revision: https://reviews.llvm.org/D93231
Added:
Modified:
clang/lib/Basic/Targets/ARM.cpp
clang/test/Driver/arm-cortex-cpus.c
clang/test/Preprocessor/arm-target-features.c
llvm/include/llvm/ADT/Triple.h
llvm/include/llvm/Support/ARMTargetParser.def
llvm/lib/Support/ARMTargetParser.cpp
llvm/lib/Support/Triple.cpp
llvm/lib/Target/ARM/ARM.td
llvm/lib/Target/ARM/ARMPredicates.td
llvm/unittests/Support/TargetParserTest.cpp
Removed:
diff --git a/clang/lib/Basic/Targets/ARM.cpp b/clang/lib/Basic/Targets/ARM.cpp
index 21cfe0107bbb..a2c96ad12a76 100644
--- a/clang/lib/Basic/Targets/ARM.cpp
+++ b/clang/lib/Basic/Targets/ARM.cpp
@@ -208,6 +208,8 @@ StringRef ARMTargetInfo::getCPUAttr() const {
return "8_5A";
case llvm::ARM::ArchKind::ARMV8_6A:
return "8_6A";
+ case llvm::ARM::ArchKind::ARMV8_7A:
+return "8_7A";
case llvm::ARM::ArchKind::ARMV8MBaseline:
return "8M_BASE";
case llvm::ARM::ArchKind::ARMV8MMainline:
diff --git a/clang/test/Driver/arm-cortex-cpus.c
b/clang/test/Driver/arm-cortex-cpus.c
index a312ccfda5a1..f1ca801c4ddb 100644
--- a/clang/test/Driver/arm-cortex-cpus.c
+++ b/clang/test/Driver/arm-cortex-cpus.c
@@ -352,6 +352,23 @@
// RUN: %clang -target arm -march=armebv8.6-a -mbig-endian -### -c %s 2>&1 |
FileCheck -check-prefix=CHECK-BE-V86A %s
// CHECK-BE-V86A: "-cc1"{{.*}} "-triple" "armebv8.6{{.*}}" "-target-cpu"
"generic"
+// RUN: %clang -target armv8.7a -### -c %s 2>&1 | FileCheck
-check-prefix=CHECK-V87A %s
+// RUN: %clang -target arm -march=armv8.7a -### -c %s 2>&1 | FileCheck
-check-prefix=CHECK-V87A %s
+// RUN: %clang -target arm -march=armv8.7-a -### -c %s 2>&1 | FileCheck
-check-prefix=CHECK-V87A %s
+// RUN: %clang -target arm -march=armv8.7a -mlittle-endian -### -c %s 2>&1 |
FileCheck -check-prefix=CHECK-V87A %s
+// RUN: %clang -target armv8.7a -mlittle-endian -### -c %s 2>&1 | FileCheck
-check-prefix=CHECK-V87A %s
+// RUN: %clang -target arm -march=armv8.7a -mlittle-endian -### -c %s 2>&1 |
FileCheck -check-prefix=CHECK-V87A %s
+// RUN: %clang -target arm -mlittle-endian -march=armv8.7-a -mlittle-endian
-### -c %s 2>&1 | FileCheck -check-prefix=CHECK-V87A %s
+// CHECK-V87A: "-cc1"{{.*}} "-triple" "armv8.7{{.*}}" "-target-cpu" "generic"
+
+// RUN: %clang -target armebv8.7a -### -c %s 2>&1 | FileCheck
-check-prefix=CHECK-BE-V87A %s
+// RUN: %clang -target armv8.7a -mbig-endian -### -c %s 2>&1 | FileCheck
-check-prefix=CHECK-BE-V87A %s
+// RUN: %clang -target armeb -march=armebv8.7a -### -c %s 2>&1 | FileCheck
-check-prefix=CHECK-BE-V87A %s
+// RUN: %clang -target armeb -march=armebv8.7-a -### -c %s 2>&1 | FileCheck
-check-prefix=CHECK-BE-V87A %s
+// RUN: %clang -target arm -march=armebv8.7a -mbig-endian -### -c %s 2>&1 |
FileCheck -check-prefix=CHECK-BE-V87A %s
+// RUN: %clang -target arm -march=armebv8.7-a -mbig-endian -### -c %s 2>&1 |
FileCheck -check-prefix=CHECK-BE-V87A %s
+// CHECK-BE-V87A: "-cc1"{{.*}} "-triple" "armebv8.7{{.*}}" "-target-cpu"
"generic"
+
// Once we have CPUs with optional v8.2-A FP16, we will need a way to turn it
// on and off. Cortex-A53 is a placeholder for now.
// RUN: %clang -target armv8a-linux-eabi -mcpu=cortex-a53+fp16 -### -c %s 2>&1
| FileCheck --check-prefix CHECK-CORTEX-A53-FP16 %s
diff --git a/clang/test/Preprocessor/arm-target-features.c
b/clang/test/Preprocessor/arm-target-features.c
index 5eaffa1c372c..9f375162e6ab 100644
--- a/clang/test/Preprocessor/arm-target-features.c
+++ b/clang/test/Preprocessor/arm-target-features.c
@@ -849,6 +849,11 @@
// CHECK-V86A: #define __ARM_ARCH_8_6A__ 1
// CHECK-V86A: #define __ARM_ARCH_PROFILE 'A'
+// RUN: %clang -target armv8.7a-none-none-eabi -x c -E -dM %s -o - | FileCheck
-match-full-lines --check-prefix=CHECK-V87A %s
+// CHECK-V87A: #define __ARM_ARCH 8
+// CHECK-V87A: #define __ARM_ARCH_8_7A__ 1
+// CHECK-V87A: #define __ARM_ARCH_PROFILE 'A'
+
// RUN: %clang -target arm-none-none-eabi -march=armv7-m -mfpu=softvfp -x c -E
-dM %s -o - | FileCheck --check-prefix=CHECK-SOFTVFP %s
// CHECK-SOFTVFP-NOT: #define __ARM_FP 0x
diff --git a/llvm/include/llvm/ADT/Triple.h b/llvm/include/llvm/ADT/Triple.h
index 13a35857512a..6e2957f3c32b 100644
--- a/llvm/include/llvm/ADT/Triple.h
+++ b/llvm/include/llvm/ADT/Triple.h
@@ -104,6 +104,7 @@ class Triple {
enum SubArchType {
NoSubArch,
+
[llvm-branch-commits] [llvm] da21f7e - [AArch64] Add support for the Branch Record Buffer extension
Author: Lucas Prates
Date: 2020-12-18T11:11:06Z
New Revision: da21f7ec146e7e46a1622253f1cce8af3b290e23
URL:
https://github.com/llvm/llvm-project/commit/da21f7ec146e7e46a1622253f1cce8af3b290e23
DIFF:
https://github.com/llvm/llvm-project/commit/da21f7ec146e7e46a1622253f1cce8af3b290e23.diff
LOG: [AArch64] Add support for the Branch Record Buffer extension
This introduces asm support for the Branch Record Buffer extension, through
the new 'brbe' subtarget feature. It consists of a new set of system registers
that enable the handling of branch records.
Patch written by Simon Tatham.
Reviewed By: ostannard
Differential Revision: https://reviews.llvm.org/D92389
Added:
llvm/test/MC/AArch64/brbe.s
llvm/test/MC/Disassembler/AArch64/brbe.txt
Modified:
llvm/include/llvm/Support/AArch64TargetParser.def
llvm/include/llvm/Support/AArch64TargetParser.h
llvm/lib/Support/AArch64TargetParser.cpp
llvm/lib/Target/AArch64/AArch64.td
llvm/lib/Target/AArch64/AArch64InstrInfo.td
llvm/lib/Target/AArch64/AArch64Subtarget.h
llvm/lib/Target/AArch64/AArch64SystemOperands.td
Removed:
diff --git a/llvm/include/llvm/Support/AArch64TargetParser.def
b/llvm/include/llvm/Support/AArch64TargetParser.def
index 3683148427b8..97172730e364 100644
--- a/llvm/include/llvm/Support/AArch64TargetParser.def
+++ b/llvm/include/llvm/Support/AArch64TargetParser.def
@@ -107,6 +107,7 @@ AARCH64_ARCH_EXT_NAME("f32mm",AArch64::AEK_F32MM,
"+f32mm", "-f32m
AARCH64_ARCH_EXT_NAME("f64mm",AArch64::AEK_F64MM, "+f64mm",
"-f64mm")
AARCH64_ARCH_EXT_NAME("tme", AArch64::AEK_TME, "+tme",
"-tme")
AARCH64_ARCH_EXT_NAME("ls64", AArch64::AEK_LS64,"+ls64",
"-ls64")
+AARCH64_ARCH_EXT_NAME("brbe", AArch64::AEK_BRBE,"+brbe",
"-brbe")
#undef AARCH64_ARCH_EXT_NAME
#ifndef AARCH64_CPU_NAME
diff --git a/llvm/include/llvm/Support/AArch64TargetParser.h
b/llvm/include/llvm/Support/AArch64TargetParser.h
index aac9197b9c5d..a3c9c6a30483 100644
--- a/llvm/include/llvm/Support/AArch64TargetParser.h
+++ b/llvm/include/llvm/Support/AArch64TargetParser.h
@@ -63,6 +63,7 @@ enum ArchExtKind : uint64_t {
AEK_F32MM = 1ULL << 31,
AEK_F64MM = 1ULL << 32,
AEK_LS64 =1ULL << 33,
+ AEK_BRBE =1ULL << 34,
};
enum class ArchKind {
diff --git a/llvm/lib/Support/AArch64TargetParser.cpp
b/llvm/lib/Support/AArch64TargetParser.cpp
index ac8f5ac8ca01..62761177c8c2 100644
--- a/llvm/lib/Support/AArch64TargetParser.cpp
+++ b/llvm/lib/Support/AArch64TargetParser.cpp
@@ -100,6 +100,8 @@ bool AArch64::getExtensionFeatures(uint64_t Extensions,
Features.push_back("+sve2-bitperm");
if (Extensions & AEK_RCPC)
Features.push_back("+rcpc");
+ if (Extensions & AEK_BRBE)
+Features.push_back("+brbe");
return true;
}
diff --git a/llvm/lib/Target/AArch64/AArch64.td
b/llvm/lib/Target/AArch64/AArch64.td
index 69f2e31ecfb4..6457c86e926f 100644
--- a/llvm/lib/Target/AArch64/AArch64.td
+++ b/llvm/lib/Target/AArch64/AArch64.td
@@ -412,6 +412,9 @@ def FeatureHCX : SubtargetFeature<
def FeatureLS64 : SubtargetFeature<"ls64", "HasLS64",
"true", "Enable Armv8.7-A LD64B/ST64B Accelerator Extension">;
+def FeatureBRBE : SubtargetFeature<"brbe", "HasBRBE",
+"true", "Enable Branch Record Buffer Extension">;
+
def FeatureFineGrainedTraps : SubtargetFeature<"fgt", "HasFineGrainedTraps",
"true", "Enable fine grained virtualization traps extension">;
diff --git a/llvm/lib/Target/AArch64/AArch64InstrInfo.td
b/llvm/lib/Target/AArch64/AArch64InstrInfo.td
index 97b2ea3c345a..5c55dd9834a7 100644
--- a/llvm/lib/Target/AArch64/AArch64InstrInfo.td
+++ b/llvm/lib/Target/AArch64/AArch64InstrInfo.td
@@ -157,6 +157,8 @@ def HasWFxT : Predicate<"Subtarget->hasWFxT()">,
AssemblerPredicate<(all_of FeatureWFxT), "wfxt">;
def HasLS64 : Predicate<"Subtarget->hasLS64()">,
AssemblerPredicate<(all_of FeatureLS64), "ls64">;
+def HasBRBE : Predicate<"Subtarget->hasBRBE()">,
+ AssemblerPredicate<(all_of FeatureBRBE), "brbe">;
def IsLE : Predicate<"Subtarget->isLittleEndian()">;
def IsBE : Predicate<"!Subtarget->isLittleEndian()">;
def IsWindows: Predicate<"Subtarget->isTargetWindows()">;
diff --git a/llvm/lib/Target/AArch64/AArch64Subtarget.h
b/llvm/lib/Target/AArch64/AArch64Subtarget.h
index 2a9426cf8c30..169e8494f173 100644
--- a/llvm/lib/Target/AArch64/AArch64Subtarget.h
+++ b/llvm/lib/Target/AArch64/AArch64Subtarget.h
@@ -184,6 +184,7 @@ class AArch64Subtarget final : public
AArch64GenSubtargetInfo {
// Future architecture extensions.
bool HasETE = false;
bool HasTRBE = false;
+ bool HasBRBE = false;
// HasZeroCycleRegMove - Has zero-cycle register mov instructions.
bool HasZeroCycleRegM
[llvm-branch-commits] [llvm] 51fe17b - [AArch64] Add support for the SPE-EEF feature
Author: Lucas Prates
Date: 2020-12-18T11:11:56Z
New Revision: 51fe17b0471a2b0a27ce038426e6b996218061a2
URL:
https://github.com/llvm/llvm-project/commit/51fe17b0471a2b0a27ce038426e6b996218061a2
DIFF:
https://github.com/llvm/llvm-project/commit/51fe17b0471a2b0a27ce038426e6b996218061a2.diff
LOG: [AArch64] Add support for the SPE-EEF feature
This is an addition to the existing Statistical Profiling extension, which
introduces an extra system register that is enabled by the new 'spe-eef'
subtarget feature.
Patch written by Simon Tatham.
Reviewed By: ostannard
Differential Revision: https://reviews.llvm.org/D92391
Added:
llvm/test/MC/AArch64/spe.s
Modified:
llvm/lib/Target/AArch64/AArch64.td
llvm/lib/Target/AArch64/AArch64InstrInfo.td
llvm/lib/Target/AArch64/AArch64Subtarget.h
llvm/lib/Target/AArch64/AArch64SystemOperands.td
Removed:
diff --git a/llvm/lib/Target/AArch64/AArch64.td
b/llvm/lib/Target/AArch64/AArch64.td
index 6457c86e926f..2df4e92e42cb 100644
--- a/llvm/lib/Target/AArch64/AArch64.td
+++ b/llvm/lib/Target/AArch64/AArch64.td
@@ -415,6 +415,9 @@ def FeatureLS64 : SubtargetFeature<"ls64", "HasLS64",
def FeatureBRBE : SubtargetFeature<"brbe", "HasBRBE",
"true", "Enable Branch Record Buffer Extension">;
+def FeatureSPE_EEF : SubtargetFeature<"spe-eef", "HasSPE_EEF",
+"true", "Enable extra register in the Statistical Profiling Extension">;
+
def FeatureFineGrainedTraps : SubtargetFeature<"fgt", "HasFineGrainedTraps",
"true", "Enable fine grained virtualization traps extension">;
diff --git a/llvm/lib/Target/AArch64/AArch64InstrInfo.td
b/llvm/lib/Target/AArch64/AArch64InstrInfo.td
index 5c55dd9834a7..c1d8fd1aba3d 100644
--- a/llvm/lib/Target/AArch64/AArch64InstrInfo.td
+++ b/llvm/lib/Target/AArch64/AArch64InstrInfo.td
@@ -159,6 +159,8 @@ def HasLS64 : Predicate<"Subtarget->hasLS64()">,
AssemblerPredicate<(all_of FeatureLS64), "ls64">;
def HasBRBE : Predicate<"Subtarget->hasBRBE()">,
AssemblerPredicate<(all_of FeatureBRBE), "brbe">;
+def HasSPE_EEF : Predicate<"Subtarget->hasSPE_EEF()">,
+ AssemblerPredicate<(all_of FeatureSPE_EEF), "spe-eef">;
def IsLE : Predicate<"Subtarget->isLittleEndian()">;
def IsBE : Predicate<"!Subtarget->isLittleEndian()">;
def IsWindows: Predicate<"Subtarget->isTargetWindows()">;
diff --git a/llvm/lib/Target/AArch64/AArch64Subtarget.h
b/llvm/lib/Target/AArch64/AArch64Subtarget.h
index 169e8494f173..641450a6d776 100644
--- a/llvm/lib/Target/AArch64/AArch64Subtarget.h
+++ b/llvm/lib/Target/AArch64/AArch64Subtarget.h
@@ -185,6 +185,7 @@ class AArch64Subtarget final : public
AArch64GenSubtargetInfo {
bool HasETE = false;
bool HasTRBE = false;
bool HasBRBE = false;
+ bool HasSPE_EEF = false;
// HasZeroCycleRegMove - Has zero-cycle register mov instructions.
bool HasZeroCycleRegMove = false;
diff --git a/llvm/lib/Target/AArch64/AArch64SystemOperands.td
b/llvm/lib/Target/AArch64/AArch64SystemOperands.td
index a753b4d4fbc4..a69aa68405d4 100644
--- a/llvm/lib/Target/AArch64/AArch64SystemOperands.td
+++ b/llvm/lib/Target/AArch64/AArch64SystemOperands.td
@@ -1593,6 +1593,10 @@ foreach n = 0-31 in {
}
}
+// Statistical Profiling Extension system register
+let Requires = [{ {AArch64::FeatureSPE_EEF} }] in
+def : RWSysReg<"PMSNEVFR_EL1", 0b11, 0b000, 0b1001, 0b1001, 0b001>;
+
// Cyclone specific system registers
// Op0Op1 CRn CRmOp2
let Requires = [{ {AArch64::ProcAppleA7} }] in
diff --git a/llvm/test/MC/AArch64/spe.s b/llvm/test/MC/AArch64/spe.s
new file mode 100644
index ..a6fb46291dea
--- /dev/null
+++ b/llvm/test/MC/AArch64/spe.s
@@ -0,0 +1,6 @@
+// RUN: llvm-mc -triple aarch64 -mattr +spe-eef -show-encoding %s 2>%t |
FileCheck %s
+
+msr PMSNEVFR_EL1, x0
+mrs x1, PMSNEVFR_EL1
+// CHECK: msr PMSNEVFR_EL1, x0// encoding: [0x20,0x99,0x18,0xd5]
+// CHECK: mrs x1, PMSNEVFR_EL1// encoding: [0x21,0x99,0x38,0xd5]
___
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[llvm-branch-commits] [llvm] 1a9577b - [AArch64] Add support for ls64 to the .arch_extension asm directive
Author: Lucas Prates
Date: 2020-12-18T15:55:55Z
New Revision: 1a9577bde1dd3dc25eac2a78fb685f37351004cb
URL:
https://github.com/llvm/llvm-project/commit/1a9577bde1dd3dc25eac2a78fb685f37351004cb
DIFF:
https://github.com/llvm/llvm-project/commit/1a9577bde1dd3dc25eac2a78fb685f37351004cb.diff
LOG: [AArch64] Add support for ls64 to the .arch_extension asm directive
This adds support for the 'ls64' AArch64 extension to the `.arch_extension`
asm directive.
Reviewed By: ostannard
Differential Revision: https://reviews.llvm.org/D92574
Added:
Modified:
llvm/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp
llvm/test/MC/AArch64/directive-arch_extension-negative.s
llvm/test/MC/AArch64/directive-arch_extension.s
Removed:
diff --git a/llvm/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp
b/llvm/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp
index 069bb5e44f0e..26e093bf4ce7 100644
--- a/llvm/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp
+++ b/llvm/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp
@@ -2912,6 +2912,7 @@ static const struct Extension {
{"sve2-sm4", {AArch64::FeatureSVE2SM4}},
{"sve2-sha3", {AArch64::FeatureSVE2SHA3}},
{"sve2-bitperm", {AArch64::FeatureSVE2BitPerm}},
+{"ls64", {AArch64::FeatureLS64}},
{"xs", {AArch64::FeatureXS}},
// FIXME: Unsupported extensions
{"pan", {}},
diff --git a/llvm/test/MC/AArch64/directive-arch_extension-negative.s
b/llvm/test/MC/AArch64/directive-arch_extension-negative.s
index 8901247978a8..9d67abb80054 100644
--- a/llvm/test/MC/AArch64/directive-arch_extension-negative.s
+++ b/llvm/test/MC/AArch64/directive-arch_extension-negative.s
@@ -83,3 +83,8 @@ dc cvap, x7
ldapr x0, [x1]
// CHECK: error: instruction requires: rcpc
// CHECK-NEXT: ldapr x0, [x1]
+
+.arch_extension nols64
+ld64b x0, [x13]
+// CHECK: error: instruction requires: ls64
+// CHECK-NEXT: ld64b x0, [x13]
diff --git a/llvm/test/MC/AArch64/directive-arch_extension.s
b/llvm/test/MC/AArch64/directive-arch_extension.s
index 790bcf355475..a44b14ddeea2 100644
--- a/llvm/test/MC/AArch64/directive-arch_extension.s
+++ b/llvm/test/MC/AArch64/directive-arch_extension.s
@@ -67,3 +67,7 @@ dc cvap, x7
.arch_extension rcpc
ldapr x0, [x1]
// CHECK: ldapr x0, [x1]
+
+.arch_extension ls64
+ld64b x0, [x13]
+// CHECK: ld64b x0, [x13]
___
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[llvm-branch-commits] [llvm] 91593e4 - [AArch64] Updating .arch_extension negative tests
Author: Lucas Prates Date: 2020-12-18T15:57:11Z New Revision: 91593e461a24f355fa6138c2a7b136d1ec1d9d79 URL: https://github.com/llvm/llvm-project/commit/91593e461a24f355fa6138c2a7b136d1ec1d9d79 DIFF: https://github.com/llvm/llvm-project/commit/91593e461a24f355fa6138c2a7b136d1ec1d9d79.diff LOG: [AArch64] Updating .arch_extension negative tests This updates the test for the `.arch_extension` as directive negatives to properly enable the extensions being tested on the llvm-mc command line before validating that the directive correctly disables them. Reviewed By: ostannard Differential Revision: https://reviews.llvm.org/D93538 Added: Modified: llvm/test/MC/AArch64/directive-arch_extension-negative.s Removed: diff --git a/llvm/test/MC/AArch64/directive-arch_extension-negative.s b/llvm/test/MC/AArch64/directive-arch_extension-negative.s index 9d67abb80054..29920d442a8a 100644 --- a/llvm/test/MC/AArch64/directive-arch_extension-negative.s +++ b/llvm/test/MC/AArch64/directive-arch_extension-negative.s @@ -1,90 +1,126 @@ -// RUN: not llvm-mc -triple aarch64 -filetype asm -o - %s 2>&1 | FileCheck %s +// RUN: not llvm-mc -triple aarch64 \ +// RUN: -mattr=+crc,+sm4,+sha3,+sha2,+aes,+fp,+neon,+ras,+lse,+predres,+ccdp,+mte,+tlb-rmi,+pan-rwv,+ccpp,+rcpc,+ls64 \ +// RUN: -filetype asm -o - %s 2>&1 | FileCheck %s .arch_extension axp64 // CHECK: error: unknown architectural extension: axp64 // CHECK-NEXT: .arch_extension axp64 +crc32cx w0, w1, x3 +// CHECK-NOT: [[@LINE-1]]:1: error: instruction requires: crc .arch_extension nocrc crc32cx w0, w1, x3 -// CHECK: error: instruction requires: crc +// CHECK: [[@LINE-1]]:1: error: instruction requires: crc // CHECK-NEXT: crc32cx w0, w1, x3 +sm4e v2.4s, v15.4s +// CHECK-NOT: [[@LINE-1]]:1: error: instruction requires: sm4 .arch_extension nosm4 sm4e v2.4s, v15.4s -// CHECK: error: instruction requires: sm4 +// CHECK: [[@LINE-1]]:1: error: instruction requires: sm4 // CHECK-NEXT: sm4e v2.4s, v15.4s +sha512h q0, q1, v2.2d +// CHECK-NOT: [[@LINE-1]]:1: error: instruction requires: sha3 .arch_extension nosha3 sha512h q0, q1, v2.2d -// CHECK: error: instruction requires: sha3 +// CHECK: [[@LINE-1]]:1: error: instruction requires: sha3 // CHECK-NEXT: sha512h q0, q1, v2.2d +sha1h s0, s1 +// CHECK-NOT: [[@LINE-1]]:1: error: instruction requires: sha2 .arch_extension nosha2 sha1h s0, s1 -// CHECK: error: instruction requires: sha2 +// CHECK: [[@LINE-1]]:1: error: instruction requires: sha2 // CHECK-NEXT: sha1h s0, s1 +aese v0.16b, v1.16b +// CHECK-NOT: [[@LINE-1]]:1: error: instruction requires: aes .arch_extension noaes aese v0.16b, v1.16b -// CHECK: error: instruction requires: aes +// CHECK: [[@LINE-1]]:1: error: instruction requires: aes // CHECK-NEXT: aese v0.16b, v1.16b +fminnm d0, d0, d1 +// CHECK-NOT: [[@LINE-1]]:1: error: instruction requires: fp .arch_extension nofp fminnm d0, d0, d1 -// CHECK: error: instruction requires: fp +// CHECK: [[@LINE-1]]:1: error: instruction requires: fp // CHECK-NEXT: fminnm d0, d0, d1 +addp v0.4s, v0.4s, v0.4s +// CHECK-NOT: [[@LINE-1]]:1: error: instruction requires: neon .arch_extension nosimd addp v0.4s, v0.4s, v0.4s -// CHECK: error: instruction requires: neon +// CHECK: [[@LINE-1]]:1: error: instruction requires: neon // CHECK-NEXT: addp v0.4s, v0.4s, v0.4s +esb +// CHECK-NOT: [[@LINE-1]]:1: error: instruction requires: ras .arch_extension noras esb -// CHECK: error: instruction requires: ras +// CHECK: [[@LINE-1]]:1: error: instruction requires: ras // CHECK-NEXT: esb +casa w5, w7, [x20] +// CHECK-NOT: [[@LINE-1]]:1: error: instruction requires: lse .arch_extension nolse casa w5, w7, [x20] -// CHECK: error: instruction requires: lse +// CHECK: [[@LINE-1]]:1: error: instruction requires: lse // CHECK-NEXT: casa w5, w7, [x20] +cfp rctx, x0 +// CHECK-NOT: [[@LINE-1]]:5: error: CFPRCTX requires: predres .arch_extension nopredres cfp rctx, x0 -// CHECK: error: CFPRCTX requires: predres +// CHECK: [[@LINE-1]]:5: error: CFPRCTX requires: predres // CHECK-NEXT: cfp rctx, x0 +dc cvadp, x7 +// CHECK-NOT: [[@LINE-1]]:4: error: DC CVADP requires: ccdp .arch_extension noccdp dc cvadp, x7 -// CHECK: error: DC CVADP requires: ccdp +// CHECK: [[@LINE-1]]:4: error: DC CVADP requires: ccdp // CHECK-NEXT: dc cvadp, x7 +irg x0, x1 +// CHECK-NOT: [[@LINE-1]]:1: error: instruction requires: mte .arch_extension nomte irg x0, x1 -// CHECK: error: instruction requires: mte +// CHECK: [[@LINE-1]]:1: error: instruction requires: mte // CHECK-NEXT: irg x0, x1 +tlbi vmalle1os +// CHECK-NOT: [[@LINE-1]]:6: error: TLBI VMALLE1OS requires: tlb-rmi .arch_extension notlb-rmi tlbi vmalle1os -// CHECK: error: TLBI VMALLE1OS requires: tlb-rmi +// CHECK: [[@LINE-1]]:6: error: TLBI VMALLE1OS requires: tlb-rmi // CHECK-NEXT: tlbi vmalle1os +at s1e1wp, x2 +// CHECK-NOT: [[@LINE-1]]:4: error: AT S1E1WP r
[llvm-branch-commits] [clang] fdebc12 - [Clang][AArch64] Capturing proper pointer alignment for Neon vld1 intrinsicts
Author: Lucas Prates
Date: 2020-05-07T12:16:34+01:00
New Revision: fdebc127acffaae84c3768ae805f1f3e199f1fde
URL:
https://github.com/llvm/llvm-project/commit/fdebc127acffaae84c3768ae805f1f3e199f1fde
DIFF:
https://github.com/llvm/llvm-project/commit/fdebc127acffaae84c3768ae805f1f3e199f1fde.diff
LOG: [Clang][AArch64] Capturing proper pointer alignment for Neon vld1
intrinsicts
Added:
Modified:
clang/lib/CodeGen/CGBuiltin.cpp
Removed:
diff --git a/clang/lib/CodeGen/CGBuiltin.cpp b/clang/lib/CodeGen/CGBuiltin.cpp
index dbe8826454dc..8b33890098bd 100644
--- a/clang/lib/CodeGen/CGBuiltin.cpp
+++ b/clang/lib/CodeGen/CGBuiltin.cpp
@@ -10283,9 +10283,8 @@ Value *CodeGenFunction::EmitAArch64BuiltinExpr(unsigned
BuiltinID,
}
case NEON::BI__builtin_neon_vld1_v:
case NEON::BI__builtin_neon_vld1q_v: {
+auto Alignment = getNaturalPointeeTypeAlignment(E->getArg(0)->getType());
Ops[0] = Builder.CreateBitCast(Ops[0], llvm::PointerType::getUnqual(VTy));
-auto Alignment = CharUnits::fromQuantity(
-BuiltinID == NEON::BI__builtin_neon_vld1_v ? 8 : 16);
return Builder.CreateAlignedLoad(VTy, Ops[0], Alignment);
}
case NEON::BI__builtin_neon_vst1_v:
___
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