Author: Lucas Prates Date: 2020-12-17T13:40:10Z New Revision: b5bbb4b2b75302d1d8080529ec7e9737a507ff1d
URL: https://github.com/llvm/llvm-project/commit/b5bbb4b2b75302d1d8080529ec7e9737a507ff1d DIFF: https://github.com/llvm/llvm-project/commit/b5bbb4b2b75302d1d8080529ec7e9737a507ff1d.diff LOG: [NFC][AArch64] Move AArch64 MSR/MRS into a new decoder namespace This removes the general forms of the AArch64 MSR and MRS instructions from the same decoding table that contains many more specific instructions that supersede them. They're now in a separate decoding table of their own, called "Fallback", which is only consulted in the event of the main decoder table failing to produce an answer. This should avoid decoding conflicts on future specialized instructions in the MSR space. Patch written by Simon Tatham. Reviewed By: ostannard Differential Revision: https://reviews.llvm.org/D91771 Added: Modified: llvm/lib/Target/AArch64/AArch64InstrFormats.td llvm/lib/Target/AArch64/Disassembler/AArch64Disassembler.cpp Removed: ################################################################################ diff --git a/llvm/lib/Target/AArch64/AArch64InstrFormats.td b/llvm/lib/Target/AArch64/AArch64InstrFormats.td index 2756e4dc8aa4..0f6ae93742bf 100644 --- a/llvm/lib/Target/AArch64/AArch64InstrFormats.td +++ b/llvm/lib/Target/AArch64/AArch64InstrFormats.td @@ -1447,6 +1447,7 @@ class MRSI : RtSystemI<1, (outs GPR64:$Rt), (ins mrs_sysreg_op:$systemreg), "mrs", "\t$Rt, $systemreg"> { bits<16> systemreg; let Inst{20-5} = systemreg; + let DecoderNamespace = "Fallback"; } // FIXME: Some of these def NZCV, others don't. Best way to model that? @@ -1456,6 +1457,7 @@ class MSRI : RtSystemI<0, (outs), (ins msr_sysreg_op:$systemreg, GPR64:$Rt), "msr", "\t$systemreg, $Rt"> { bits<16> systemreg; let Inst{20-5} = systemreg; + let DecoderNamespace = "Fallback"; } def SystemPStateFieldWithImm0_15Operand : AsmOperandClass { diff --git a/llvm/lib/Target/AArch64/Disassembler/AArch64Disassembler.cpp b/llvm/lib/Target/AArch64/Disassembler/AArch64Disassembler.cpp index 1ff4abb34054..e1a96ce8bdb1 100644 --- a/llvm/lib/Target/AArch64/Disassembler/AArch64Disassembler.cpp +++ b/llvm/lib/Target/AArch64/Disassembler/AArch64Disassembler.cpp @@ -267,8 +267,16 @@ DecodeStatus AArch64Disassembler::getInstruction(MCInst &MI, uint64_t &Size, uint32_t Insn = (Bytes[3] << 24) | (Bytes[2] << 16) | (Bytes[1] << 8) | (Bytes[0] << 0); - // Calling the auto-generated decoder function. - return decodeInstruction(DecoderTable32, MI, Insn, Address, this, STI); + const uint8_t *Tables[] = {DecoderTable32, DecoderTableFallback32}; + + for (auto Table : Tables) { + DecodeStatus Result = + decodeInstruction(Table, MI, Insn, Address, this, STI); + if (Result != MCDisassembler::Fail) + return Result; + } + + return MCDisassembler::Fail; } static MCSymbolizer * _______________________________________________ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
