[llvm-branch-commits] [llvm] d53e260 - [AArch64] Allow .variant_pcs before the symbol is registered
Author: Fangrui Song
Date: 2022-04-06T11:58:31-07:00
New Revision: d53e2603383a1304c3ee081169b1bf8dac93f8e4
URL:
https://github.com/llvm/llvm-project/commit/d53e2603383a1304c3ee081169b1bf8dac93f8e4
DIFF:
https://github.com/llvm/llvm-project/commit/d53e2603383a1304c3ee081169b1bf8dac93f8e4.diff
LOG: [AArch64] Allow .variant_pcs before the symbol is registered
glibc sysdeps/aarch64/tst-vpcs-mod.S has something like:
```
.variant_pcsvpcs_call
.global vpcs_call
```
This is supported by GNU as but leads to an error in MC. Use getOrCreateSymbol
to support a not-yet-registered symbol: call `registerSymbol` to ensure the
symbol exists even if there is no binding directive/label, to match GNU as.
While here, improve tests to check (1) a local symbol can get
STO_AARCH64_VARIANT_PCS (2) undefined .variant_pcs (3) an alias does not
inherit STO_AARCH64_VARIANT_PCS.
Reviewed By: efriedma
Differential Revision: https://reviews.llvm.org/D122507
(cherry picked from commit cfbd5c8e4aa1ba3fc11fb408eeedbb05bd235956)
Added:
Modified:
llvm/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp
llvm/lib/Target/AArch64/MCTargetDesc/AArch64ELFStreamer.cpp
llvm/test/MC/AArch64/directive-variant_pcs-err.s
llvm/test/MC/AArch64/directive-variant_pcs.s
Removed:
diff --git a/llvm/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp
b/llvm/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp
index 33ed7ae9780e6..8f71eb3095cfe 100644
--- a/llvm/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp
+++ b/llvm/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp
@@ -6515,21 +6515,13 @@ bool AArch64AsmParser::parseDirectiveCFIBKeyFrame() {
/// parseDirectiveVariantPCS
/// ::= .variant_pcs symbolname
bool AArch64AsmParser::parseDirectiveVariantPCS(SMLoc L) {
- const AsmToken &Tok = getTok();
- if (Tok.isNot(AsmToken::Identifier))
+ StringRef Name;
+ if (getParser().parseIdentifier(Name))
return TokError("expected symbol name");
-
- StringRef SymbolName = Tok.getIdentifier();
-
- MCSymbol *Sym = getContext().lookupSymbol(SymbolName);
- if (!Sym)
-return TokError("unknown symbol");
-
- Lex(); // Eat the symbol
-
if (parseEOL())
return true;
- getTargetStreamer().emitDirectiveVariantPCS(Sym);
+ getTargetStreamer().emitDirectiveVariantPCS(
+ getContext().getOrCreateSymbol(Name));
return false;
}
diff --git a/llvm/lib/Target/AArch64/MCTargetDesc/AArch64ELFStreamer.cpp
b/llvm/lib/Target/AArch64/MCTargetDesc/AArch64ELFStreamer.cpp
index 78c0e90b13845..46edb12959d28 100644
--- a/llvm/lib/Target/AArch64/MCTargetDesc/AArch64ELFStreamer.cpp
+++ b/llvm/lib/Target/AArch64/MCTargetDesc/AArch64ELFStreamer.cpp
@@ -254,6 +254,7 @@ void AArch64TargetELFStreamer::emitInst(uint32_t Inst) {
}
void AArch64TargetELFStreamer::emitDirectiveVariantPCS(MCSymbol *Symbol) {
+ getStreamer().getAssembler().registerSymbol(*Symbol);
cast(Symbol)->setOther(ELF::STO_AARCH64_VARIANT_PCS);
}
diff --git a/llvm/test/MC/AArch64/directive-variant_pcs-err.s
b/llvm/test/MC/AArch64/directive-variant_pcs-err.s
index 70bb5451d3716..6aa63d8298776 100644
--- a/llvm/test/MC/AArch64/directive-variant_pcs-err.s
+++ b/llvm/test/MC/AArch64/directive-variant_pcs-err.s
@@ -3,9 +3,6 @@
// CHECK: [[#@LINE+1]]:13: error: expected symbol name
.variant_pcs
-// CHECK: [[#@LINE+1]]:14: error: unknown symbol
-.variant_pcs foo
-
.global foo
// CHECK: [[#@LINE+1]]:18: error: expected newline
.variant_pcs foo bar
diff --git a/llvm/test/MC/AArch64/directive-variant_pcs.s
b/llvm/test/MC/AArch64/directive-variant_pcs.s
index f6f9c9c272f78..26ed7aef90cce 100644
--- a/llvm/test/MC/AArch64/directive-variant_pcs.s
+++ b/llvm/test/MC/AArch64/directive-variant_pcs.s
@@ -1,11 +1,37 @@
-// RUN: llvm-mc -triple aarch64-elf -filetype asm -o - %s | FileCheck %s
-// RUN: llvm-mc -triple aarch64-elf -filetype obj -o - %s \
-// RUN: | llvm-readobj --symbols - | FileCheck %s
--check-prefix=CHECK-ST_OTHER
+// RUN: llvm-mc -triple aarch64-elf -filetype asm %s | FileCheck %s
--check-prefix=ASM
+// RUN: llvm-mc -triple aarch64-elf -filetype obj %s \
+// RUN: | llvm-readelf -s - | FileCheck %s --check-prefix=OBJ
+// ASM: .variant_pcs local
+// ASM-NEXT: local:
.text
-.global foo
-.variant_pcs foo
-// CHECK: .variant_pcs foo
+.variant_pcs local
+local:
-// CHECK-ST_OTHER: Name: foo
-// CHECK-ST_OTHER: Other [ (0x80)
+/// Binding directive before .variant_pcs.
+// ASM: .globl def1
+// ASM-NEXT: .variant_pcs def1
+// ASM-NEXT: def1:
+.global def1
+.variant_pcs def1
+def1:
+
+/// .variant_pcs before binding directive.
+// ASM: .variant_pcs def2
+// ASM-NEXT: .weak def2
+// ASM-NEXT: def2:
+.variant_pcs def2
+.weak def2
+def2:
+
+.globl alias_def1
+.set alias_def1, def1
+
+// ASM: .variant_pcs undef
+.variant_pcs undef
+
+// OBJ: NOTYPE LOCAL DEFAULT [VARIANT_PCS] [[#]] local
+// OBJ-NEXT: NOTYPE GLOBAL D
[llvm-branch-commits] [llvm] 67a2904 - [VectorCombine] Insert addrspacecast when crossing address space boundaries
Author: Fraser Cormack
Date: 2022-04-06T11:57:24-07:00
New Revision: 67a290460c374d5e0d18a06c798896cac0b19e59
URL:
https://github.com/llvm/llvm-project/commit/67a290460c374d5e0d18a06c798896cac0b19e59
DIFF:
https://github.com/llvm/llvm-project/commit/67a290460c374d5e0d18a06c798896cac0b19e59.diff
LOG: [VectorCombine] Insert addrspacecast when crossing address space boundaries
We can not bitcast pointers across different address spaces. This was
previously fixed in D89577 but then in D93229 an enhancement was added
which peeks further through the ponter operand, opening up the
possibility that address-space violations could be introduced.
Instead of bailing as the previous fix did, simply insert an
addrspacecast cast instruction.
Reviewed By: lebedev.ri
Differential Revision: https://reviews.llvm.org/D121787
(cherry picked from commit 2e44b7872bc638ed884ae4aa86e38b3b47e0b65a)
Added:
Modified:
llvm/lib/Transforms/Vectorize/VectorCombine.cpp
llvm/test/Transforms/VectorCombine/AMDGPU/as-transition-inseltpoison.ll
llvm/test/Transforms/VectorCombine/AMDGPU/as-transition.ll
llvm/test/Transforms/VectorCombine/X86/load-inseltpoison.ll
Removed:
diff --git a/llvm/lib/Transforms/Vectorize/VectorCombine.cpp
b/llvm/lib/Transforms/Vectorize/VectorCombine.cpp
index 620d388199e0f..258f6c67e54d5 100644
--- a/llvm/lib/Transforms/Vectorize/VectorCombine.cpp
+++ b/llvm/lib/Transforms/Vectorize/VectorCombine.cpp
@@ -152,12 +152,7 @@ bool VectorCombine::vectorizeLoadInsert(Instruction &I) {
Value *SrcPtr = Load->getPointerOperand()->stripPointerCasts();
assert(isa(SrcPtr->getType()) && "Expected a pointer type");
- // If original AS != Load's AS, we can't bitcast the original pointer and
have
- // to use Load's operand instead. Ideally we would want to strip pointer
casts
- // without changing AS, but there's no API to do that ATM.
unsigned AS = Load->getPointerAddressSpace();
- if (AS != SrcPtr->getType()->getPointerAddressSpace())
-SrcPtr = Load->getPointerOperand();
// We are potentially transforming byte-sized (8-bit) memory accesses, so
make
// sure we have all of our type-based constraints in place for this target.
@@ -245,7 +240,8 @@ bool VectorCombine::vectorizeLoadInsert(Instruction &I) {
// It is safe and potentially profitable to load a vector directly:
// inselt undef, load Scalar, 0 --> load VecPtr
IRBuilder<> Builder(Load);
- Value *CastedPtr = Builder.CreateBitCast(SrcPtr, MinVecTy->getPointerTo(AS));
+ Value *CastedPtr = Builder.CreatePointerBitCastOrAddrSpaceCast(
+ SrcPtr, MinVecTy->getPointerTo(AS));
Value *VecLd = Builder.CreateAlignedLoad(MinVecTy, CastedPtr, Alignment);
VecLd = Builder.CreateShuffleVector(VecLd, Mask);
diff --git
a/llvm/test/Transforms/VectorCombine/AMDGPU/as-transition-inseltpoison.ll
b/llvm/test/Transforms/VectorCombine/AMDGPU/as-transition-inseltpoison.ll
index 688e3c4cf6c7a..b493c2a4f8bb5 100644
--- a/llvm/test/Transforms/VectorCombine/AMDGPU/as-transition-inseltpoison.ll
+++ b/llvm/test/Transforms/VectorCombine/AMDGPU/as-transition-inseltpoison.ll
@@ -11,9 +11,7 @@ define protected amdgpu_kernel void @load_from_other_as(<4 x
float>* nocapture n
; CHECK-LABEL: @load_from_other_as(
; CHECK-NEXT: bb:
; CHECK-NEXT:[[A:%.*]] = alloca [[STRUCT_HOGE:%.*]], align 4, addrspace(5)
-; CHECK-NEXT:[[B:%.*]] = addrspacecast [[STRUCT_HOGE]] addrspace(5)* [[A]]
to %struct.hoge*
-; CHECK-NEXT:[[C:%.*]] = getelementptr inbounds [[STRUCT_HOGE]],
%struct.hoge* [[B]], i64 0, i32 0
-; CHECK-NEXT:[[TMP0:%.*]] = bitcast float* [[C]] to <1 x float>*
+; CHECK-NEXT:[[TMP0:%.*]] = addrspacecast [[STRUCT_HOGE]] addrspace(5)*
[[A]] to <1 x float>*
; CHECK-NEXT:[[TMP1:%.*]] = load <1 x float>, <1 x float>* [[TMP0]], align
4
; CHECK-NEXT:[[E:%.*]] = shufflevector <1 x float> [[TMP1]], <1 x float>
poison, <4 x i32>
; CHECK-NEXT:store <4 x float> [[E]], <4 x float>* [[RESULTPTR:%.*]],
align 16
diff --git a/llvm/test/Transforms/VectorCombine/AMDGPU/as-transition.ll
b/llvm/test/Transforms/VectorCombine/AMDGPU/as-transition.ll
index 3468cb540903e..8e36856714b24 100644
--- a/llvm/test/Transforms/VectorCombine/AMDGPU/as-transition.ll
+++ b/llvm/test/Transforms/VectorCombine/AMDGPU/as-transition.ll
@@ -11,9 +11,7 @@ define protected amdgpu_kernel void @load_from_other_as(<4 x
float>* nocapture n
; CHECK-LABEL: @load_from_other_as(
; CHECK-NEXT: bb:
; CHECK-NEXT:[[A:%.*]] = alloca [[STRUCT_HOGE:%.*]], align 4, addrspace(5)
-; CHECK-NEXT:[[B:%.*]] = addrspacecast [[STRUCT_HOGE]] addrspace(5)* [[A]]
to %struct.hoge*
-; CHECK-NEXT:[[C:%.*]] = getelementptr inbounds [[STRUCT_HOGE]],
%struct.hoge* [[B]], i64 0, i32 0
-; CHECK-NEXT:[[TMP0:%.*]] = bitcast float* [[C]] to <1 x float>*
+; CHECK-NEXT:[[TMP0:%.*]] = addrspacecast [[STRUCT_HOGE]] addrspace(5)*
[[A]] to <1 x float>*
[llvm-branch-commits] [llvm] fd98b0f - [SelectionDAG] Don't create illegally-typed nodes while constant folding
Author: Fraser Cormack
Date: 2022-04-06T12:00:08-07:00
New Revision: fd98b0f1a6a1c57bd368c78c7cf86fc9f527d452
URL:
https://github.com/llvm/llvm-project/commit/fd98b0f1a6a1c57bd368c78c7cf86fc9f527d452
DIFF:
https://github.com/llvm/llvm-project/commit/fd98b0f1a6a1c57bd368c78c7cf86fc9f527d452.diff
LOG: [SelectionDAG] Don't create illegally-typed nodes while constant folding
This patch fixes a (seemingly very rare) crash during vector constant
folding introduced in D113300.
Normally, during legalization, if we create an illegally-typed node during
a failed attempt at constant folding it's cleaned up before being
visited, due to it having no uses.
If, however, an illegally-typed node is created during one round of
legalization and isn't cleaned up, it's possible for a second round of
legalization to create new illegally-typed nodes which add extra uses to
the old illegal nodes. This means that we can end up visiting the old
nodes before they're known to be dead, at which point we crash.
I'm not happy about this fix. Creating illegal types at all seems like a
bad idea, but we all-too-often rely on illegal constants being
successfully folded and being fixed up afterwards. However, we can't
rely on constant folding actually happening, and we don't have a
foolproof way of peering into the future.
Perhaps the correct fix is to revisit the node-iteration order during
legalization, ensuring we visit all uses of nodes before the nodes
themselves. Or alternatively we could try and clean up dead nodes
immediately after failing constant folding.
Reviewed By: RKSimon
Differential Revision: https://reviews.llvm.org/D122382
(cherry picked from commit 43a91a8474f55241404199f6b8798ac6467c2687)
Added:
llvm/test/CodeGen/RISCV/rvv/constant-folding-crash.ll
Modified:
llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
Removed:
diff --git a/llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
b/llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
index d5998d166d255..40d861702e86c 100644
--- a/llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
@@ -5494,8 +5494,18 @@ SDValue SelectionDAG::FoldConstantArithmetic(unsigned
Opcode, const SDLoc &DL,
// Build vector (integer) scalar operands may need implicit
// truncation - do this before constant folding.
- if (ScalarVT.isInteger() && ScalarVT.bitsGT(InSVT))
+ if (ScalarVT.isInteger() && ScalarVT.bitsGT(InSVT)) {
+// Don't create illegally-typed nodes unless they're constants or undef
+// - if we fail to constant fold we can't guarantee the (dead) nodes
+// we're creating will be cleaned up before being visited for
+// legalization.
+if (NewNodesMustHaveLegalTypes && !ScalarOp.isUndef() &&
+!isa(ScalarOp) &&
+TLI->getTypeAction(*getContext(), InSVT) !=
+TargetLowering::TypeLegal)
+ return SDValue();
ScalarOp = getNode(ISD::TRUNCATE, DL, InSVT, ScalarOp);
+ }
ScalarOps.push_back(ScalarOp);
}
diff --git a/llvm/test/CodeGen/RISCV/rvv/constant-folding-crash.ll
b/llvm/test/CodeGen/RISCV/rvv/constant-folding-crash.ll
new file mode 100644
index 0..1fae357540b7e
--- /dev/null
+++ b/llvm/test/CodeGen/RISCV/rvv/constant-folding-crash.ll
@@ -0,0 +1,85 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -mtriple=riscv32 -mattr=+v -riscv-v-vector-bits-min=128
-verify-machineinstrs < %s \
+; RUN: | FileCheck %s --check-prefix RV32
+; RUN: llc -mtriple=riscv64 -mattr=+v -riscv-v-vector-bits-min=128
-verify-machineinstrs < %s \
+; RUN: | FileCheck %s --check-prefix RV64
+
+; This used to crash during type legalization, where lowering (v4i1 =
+; BUILD_VECTOR) created a (v4i1 = SETCC v4i8) which during constant-folding
+; created illegally-typed i8 nodes. Ultimately, constant-folding failed and so
+; the new illegal nodes had no uses. However, during a second round of
+; legalization, this same pattern was generated from another BUILD_VECTOR. This
+; meant one of the illegally-typed (i8 = Constant<0>) nodes now had two dead
+; uses. Because the Constant and one of the uses were from round 1, they were
+; further up in the node order than the new second use, so the constant was
+; visited while it wasn't "dead". At the point of visiting the constant, we
+; crashed.
+
+define void @constant_folding_crash(i8* %v54, <4 x <4 x i32>*> %lanes.a, <4 x
<4 x i32>*> %lanes.b, <4 x i1> %sel) {
+; RV32-LABEL: constant_folding_crash:
+; RV32: # %bb.0: # %entry
+; RV32-NEXT:lw a0, 8(a0)
+; RV32-NEXT:vmv1r.v v10, v0
+; RV32-NEXT:andi a0, a0, 1
+; RV32-NEXT:seqz a0, a0
+; RV32-NEXT:vsetivli zero, 4, e8, mf4, ta, mu
+; RV32-NEXT:vmv.v.x v11, a0
+; RV32-NEXT:vmsne.vi v0, v11, 0
+; RV32-NEXT:vsetvli zero, zero, e32, m1, ta, mu
+; RV32-N
[llvm-branch-commits] [clang] aaf0c92 - [clang-repl] Add an accessor to our underlying execution engine
Author: Vassil Vassilev
Date: 2022-04-06T22:20:02-07:00
New Revision: aaf0c921a54ac9f9d9bc0e74566f3153d25e0c00
URL:
https://github.com/llvm/llvm-project/commit/aaf0c921a54ac9f9d9bc0e74566f3153d25e0c00
DIFF:
https://github.com/llvm/llvm-project/commit/aaf0c921a54ac9f9d9bc0e74566f3153d25e0c00.diff
LOG: [clang-repl] Add an accessor to our underlying execution engine
This patch will allow better incremental adoption of these changes in downstream
cling and other users which want to experiment by customizing the execution
engine.
(cherry picked from commit 788e0f7f3e96a9d61c2412e452c4589e2693b79a)
Added:
Modified:
clang/include/clang/Interpreter/Interpreter.h
clang/lib/Interpreter/IncrementalExecutor.h
clang/lib/Interpreter/Interpreter.cpp
Removed:
diff --git a/clang/include/clang/Interpreter/Interpreter.h
b/clang/include/clang/Interpreter/Interpreter.h
index 721a649deb43b..f2fdb90f5ba48 100644
--- a/clang/include/clang/Interpreter/Interpreter.h
+++ b/clang/include/clang/Interpreter/Interpreter.h
@@ -26,6 +26,7 @@
namespace llvm {
namespace orc {
+class LLJIT;
class ThreadSafeContext;
}
} // namespace llvm
@@ -56,6 +57,7 @@ class Interpreter {
static llvm::Expected>
create(std::unique_ptr CI);
const CompilerInstance *getCompilerInstance() const;
+ const llvm::orc::LLJIT *getExecutionEngine() const;
llvm::Expected Parse(llvm::StringRef Code);
llvm::Error Execute(PartialTranslationUnit &T);
llvm::Error ParseAndExecute(llvm::StringRef Code) {
diff --git a/clang/lib/Interpreter/IncrementalExecutor.h
b/clang/lib/Interpreter/IncrementalExecutor.h
index 24447994d5f1d..51b4d83d10b1c 100644
--- a/clang/lib/Interpreter/IncrementalExecutor.h
+++ b/clang/lib/Interpreter/IncrementalExecutor.h
@@ -45,6 +45,7 @@ class IncrementalExecutor {
llvm::Error runCtors() const;
llvm::Expected
getSymbolAddress(llvm::StringRef Name, SymbolNameKind NameKind) const;
+ llvm::orc::LLJIT *getExecutionEngine() const { return Jit.get(); }
};
} // end namespace clang
diff --git a/clang/lib/Interpreter/Interpreter.cpp
b/clang/lib/Interpreter/Interpreter.cpp
index b2e7727be39a0..470c9c289a749 100644
--- a/clang/lib/Interpreter/Interpreter.cpp
+++ b/clang/lib/Interpreter/Interpreter.cpp
@@ -196,6 +196,12 @@ const CompilerInstance *Interpreter::getCompilerInstance()
const {
return IncrParser->getCI();
}
+const llvm::orc::LLJIT *Interpreter::getExecutionEngine() const {
+ if (IncrExecutor)
+return IncrExecutor->getExecutionEngine();
+ return nullptr;
+}
+
llvm::Expected
Interpreter::Parse(llvm::StringRef Code) {
return IncrParser->Parse(Code);
___
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[llvm-branch-commits] [llvm] d150523 - [AArch64] Use correct calling convention for each vararg
Author: Philippe Valembois
Date: 2022-04-06T22:13:04-07:00
New Revision: d150523f0776da96a1a6b694f800f15365318e20
URL:
https://github.com/llvm/llvm-project/commit/d150523f0776da96a1a6b694f800f15365318e20
DIFF:
https://github.com/llvm/llvm-project/commit/d150523f0776da96a1a6b694f800f15365318e20.diff
LOG: [AArch64] Use correct calling convention for each vararg
While checking is tail call optimization is possible, the calling
convention applied to fixed arguments is not the correct one.
This implies for DarwinPCS that all arguments of a vararg function will
go to the stack although fixed ones can go in registers.
This prevents non-virtual thunks to be tail optimized although they are
marked as musttail.
Differential Revision: https://reviews.llvm.org/D120622
(cherry picked from commit 26cd258420c774254cc48330b1f4d23d353baf05)
Added:
llvm/test/CodeGen/AArch64/darwinpcs-tail.ll
Modified:
llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
llvm/lib/Target/AArch64/AArch64ISelLowering.h
Removed:
diff --git a/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
b/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
index ac5e51e47ddf1..3008466159bb2 100644
--- a/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
+++ b/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
@@ -5843,14 +5843,62 @@ static bool mayTailCallThisCC(CallingConv::ID CC) {
}
}
+static void analyzeCallOperands(const AArch64TargetLowering &TLI,
+const AArch64Subtarget *Subtarget,
+const TargetLowering::CallLoweringInfo &CLI,
+CCState &CCInfo) {
+ const SelectionDAG &DAG = CLI.DAG;
+ CallingConv::ID CalleeCC = CLI.CallConv;
+ bool IsVarArg = CLI.IsVarArg;
+ const SmallVector &Outs = CLI.Outs;
+ bool IsCalleeWin64 = Subtarget->isCallingConvWin64(CalleeCC);
+
+ unsigned NumArgs = Outs.size();
+ for (unsigned i = 0; i != NumArgs; ++i) {
+MVT ArgVT = Outs[i].VT;
+ISD::ArgFlagsTy ArgFlags = Outs[i].Flags;
+
+bool UseVarArgCC = false;
+if (IsVarArg) {
+ // On Windows, the fixed arguments in a vararg call are passed in GPRs
+ // too, so use the vararg CC to force them to integer registers.
+ if (IsCalleeWin64) {
+UseVarArgCC = true;
+ } else {
+UseVarArgCC = !Outs[i].IsFixed;
+ }
+} else {
+ // Get type of the original argument.
+ EVT ActualVT =
+ TLI.getValueType(DAG.getDataLayout(),
CLI.Args[Outs[i].OrigArgIndex].Ty,
+ /*AllowUnknown*/ true);
+ MVT ActualMVT = ActualVT.isSimple() ? ActualVT.getSimpleVT() : ArgVT;
+ // If ActualMVT is i1/i8/i16, we should set LocVT to i8/i8/i16.
+ if (ActualMVT == MVT::i1 || ActualMVT == MVT::i8)
+ArgVT = MVT::i8;
+ else if (ActualMVT == MVT::i16)
+ArgVT = MVT::i16;
+}
+
+CCAssignFn *AssignFn = TLI.CCAssignFnForCall(CalleeCC, UseVarArgCC);
+bool Res = AssignFn(i, ArgVT, ArgVT, CCValAssign::Full, ArgFlags, CCInfo);
+assert(!Res && "Call operand has unhandled type");
+(void)Res;
+ }
+}
+
bool AArch64TargetLowering::isEligibleForTailCallOptimization(
-SDValue Callee, CallingConv::ID CalleeCC, bool isVarArg,
-const SmallVectorImpl &Outs,
-const SmallVectorImpl &OutVals,
-const SmallVectorImpl &Ins, SelectionDAG &DAG) const {
+const CallLoweringInfo &CLI) const {
+ CallingConv::ID CalleeCC = CLI.CallConv;
if (!mayTailCallThisCC(CalleeCC))
return false;
+ SDValue Callee = CLI.Callee;
+ bool IsVarArg = CLI.IsVarArg;
+ const SmallVector &Outs = CLI.Outs;
+ const SmallVector &OutVals = CLI.OutVals;
+ const SmallVector &Ins = CLI.Ins;
+ const SelectionDAG &DAG = CLI.DAG;
MachineFunction &MF = DAG.getMachineFunction();
const Function &CallerF = MF.getFunction();
CallingConv::ID CallerCC = CallerF.getCallingConv();
@@ -5915,30 +5963,14 @@ bool
AArch64TargetLowering::isEligibleForTailCallOptimization(
// I want anyone implementing a new calling convention to think long and hard
// about this assert.
- assert((!isVarArg || CalleeCC == CallingConv::C) &&
+ assert((!IsVarArg || CalleeCC == CallingConv::C) &&
"Unexpected variadic calling convention");
LLVMContext &C = *DAG.getContext();
- if (isVarArg && !Outs.empty()) {
-// At least two cases here: if caller is fastcc then we can't have any
-// memory arguments (we'd be expected to clean up the stack afterwards). If
-// caller is C then we could potentially use its argument area.
-
-// FIXME: for now we take the most conservative of these in both cases:
-// disallow all variadic memory operands.
-SmallVector ArgLocs;
-CCState CCInfo(CalleeCC, isVarArg, MF, ArgLocs, C);
-
-CCInfo.AnalyzeCallOperands(Outs, CCAssignFnForCall(CalleeCC, true));
-for (const CCValAssign &ArgLoc : ArgLocs)
- if (!ArgLoc.isRegLoc())
-
[llvm-branch-commits] [llvm] ec13fed - [X86] lowerV8I16Shuffle - use explicit SmallVector width to avoid MSVC AVX alignment bug
Author: Simon Pilgrim
Date: 2022-04-06T22:23:21-07:00
New Revision: ec13fed5867f674bb96ab5502629ec209ef5a73a
URL:
https://github.com/llvm/llvm-project/commit/ec13fed5867f674bb96ab5502629ec209ef5a73a
DIFF:
https://github.com/llvm/llvm-project/commit/ec13fed5867f674bb96ab5502629ec209ef5a73a.diff
LOG: [X86] lowerV8I16Shuffle - use explicit SmallVector width to
avoid MSVC AVX alignment bug
As discussed on Issue #54645 - building llc with /AVX can result in incorrectly
aligned structs
(cherry picked from commit cb5c4a5917889bd12c5662c8b550cde11924d570)
Added:
Modified:
llvm/lib/Target/X86/X86ISelLowering.cpp
Removed:
diff --git a/llvm/lib/Target/X86/X86ISelLowering.cpp
b/llvm/lib/Target/X86/X86ISelLowering.cpp
index 77c2e7d169907..600d146cb1245 100644
--- a/llvm/lib/Target/X86/X86ISelLowering.cpp
+++ b/llvm/lib/Target/X86/X86ISelLowering.cpp
@@ -15796,7 +15796,8 @@ static SDValue lowerV8I16Shuffle(const SDLoc &DL,
ArrayRef Mask,
V1 = extract128BitVector(V1V2, 0, DAG, DL);
V2 = extract128BitVector(V1V2, 4, DAG, DL);
} else {
- SmallVector DWordClearOps(4, DAG.getConstant(0, DL, MVT::i32));
+ SmallVector DWordClearOps(4,
+DAG.getConstant(0, DL, MVT::i32));
for (unsigned i = 0; i != 4; i += 1 << (NumEvenDrops - 1))
DWordClearOps[i] = DAG.getConstant(0x, DL, MVT::i32);
SDValue DWordClearMask =
___
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