Author: Simon Pilgrim Date: 2022-04-06T22:23:21-07:00 New Revision: ec13fed5867f674bb96ab5502629ec209ef5a73a
URL: https://github.com/llvm/llvm-project/commit/ec13fed5867f674bb96ab5502629ec209ef5a73a DIFF: https://github.com/llvm/llvm-project/commit/ec13fed5867f674bb96ab5502629ec209ef5a73a.diff LOG: [X86] lowerV8I16Shuffle - use explicit SmallVector<SDValue, 4> width to avoid MSVC AVX alignment bug As discussed on Issue #54645 - building llc with /AVX can result in incorrectly aligned structs (cherry picked from commit cb5c4a5917889bd12c5662c8b550cde11924d570) Added: Modified: llvm/lib/Target/X86/X86ISelLowering.cpp Removed: ################################################################################ diff --git a/llvm/lib/Target/X86/X86ISelLowering.cpp b/llvm/lib/Target/X86/X86ISelLowering.cpp index 77c2e7d169907..600d146cb1245 100644 --- a/llvm/lib/Target/X86/X86ISelLowering.cpp +++ b/llvm/lib/Target/X86/X86ISelLowering.cpp @@ -15796,7 +15796,8 @@ static SDValue lowerV8I16Shuffle(const SDLoc &DL, ArrayRef<int> Mask, V1 = extract128BitVector(V1V2, 0, DAG, DL); V2 = extract128BitVector(V1V2, 4, DAG, DL); } else { - SmallVector<SDValue> DWordClearOps(4, DAG.getConstant(0, DL, MVT::i32)); + SmallVector<SDValue, 4> DWordClearOps(4, + DAG.getConstant(0, DL, MVT::i32)); for (unsigned i = 0; i != 4; i += 1 << (NumEvenDrops - 1)) DWordClearOps[i] = DAG.getConstant(0xFFFF, DL, MVT::i32); SDValue DWordClearMask = _______________________________________________ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
