[llvm-branch-commits] [llvm-branch] r261334 - Merging r261306:
Author: hans
Date: Fri Feb 19 11:13:16 2016
New Revision: 261334
URL: http://llvm.org/viewvc/llvm-project?rev=261334&view=rev
Log:
Merging r261306:
r261306 | matze | 2016-02-18 20:44:19 -0800 (Thu, 18 Feb 2016) | 1 line
LegalizeDAG: Fix ExpandFCOPYSIGN assuming the same type on both inputs
Added:
llvm/branches/release_38/test/CodeGen/AArch64/fcopysign.ll
- copied unchanged from r261306,
llvm/trunk/test/CodeGen/AArch64/fcopysign.ll
Modified:
llvm/branches/release_38/ (props changed)
llvm/branches/release_38/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
Propchange: llvm/branches/release_38/
--
--- svn:mergeinfo (original)
+++ svn:mergeinfo Fri Feb 19 11:13:16 2016
@@ -1,3 +1,3 @@
/llvm/branches/Apple/Pertwee:110850,110961
/llvm/branches/type-system-rewrite:133420-134817
-/llvm/trunk:155241,257645,257648,257730,257775,257791,257864,257875,257886,257902,257905,257925,257929-257930,257940,257942,257977,257979,257997,258103,258112,258168,258184,258207,258221,258273,258325,258406,258416,258428,258436,258471,258609-258611,258616,258690,258729,258891,258971,259177-259178,259228,259236,259342,259346,259375,259381,259645,259649,259695-259696,259702,259740,259798,259835,259840,259886,259888,259958,260164,260390,260427,260587,260641,260703,260733,261033,261039,261258
+/llvm/trunk:155241,257645,257648,257730,257775,257791,257864,257875,257886,257902,257905,257925,257929-257930,257940,257942,257977,257979,257997,258103,258112,258168,258184,258207,258221,258273,258325,258406,258416,258428,258436,258471,258609-258611,258616,258690,258729,258891,258971,259177-259178,259228,259236,259342,259346,259375,259381,259645,259649,259695-259696,259702,259740,259798,259835,259840,259886,259888,259958,260164,260390,260427,260587,260641,260703,260733,261033,261039,261258,261306
Modified: llvm/branches/release_38/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
URL:
http://llvm.org/viewvc/llvm-project/llvm/branches/release_38/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp?rev=261334&r1=261333&r2=261334&view=diff
==
--- llvm/branches/release_38/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp (original)
+++ llvm/branches/release_38/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp Fri Feb
19 11:13:16 2016
@@ -1637,6 +1637,7 @@ struct FloatSignAsInt {
MachinePointerInfo FloatPointerInfo;
SDValue IntValue;
APInt SignMask;
+ uint8_t SignBit;
};
}
@@ -1653,6 +1654,7 @@ void SelectionDAGLegalize::getSignAsIntV
if (TLI.isTypeLegal(IVT)) {
State.IntValue = DAG.getNode(ISD::BITCAST, DL, IVT, Value);
State.SignMask = APInt::getSignBit(NumBits);
+State.SignBit = NumBits - 1;
return;
}
@@ -1689,6 +1691,7 @@ void SelectionDAGLegalize::getSignAsIntV
IntPtr, State.IntPointerInfo, MVT::i8,
false, false, false, 0);
State.SignMask = APInt::getOneBitSet(LoadTy.getSizeInBits(), 7);
+ State.SignBit = 7;
}
/// Replace the integer value produced by getSignAsIntValue() with a new value
@@ -1731,15 +1734,38 @@ SDValue SelectionDAGLegalize::ExpandFCOP
return DAG.getSelect(DL, FloatVT, Cond, NegValue, AbsValue);
}
- // Transform values to integer, copy the sign bit and transform back.
+ // Transform Mag value to integer, and clear the sign bit.
FloatSignAsInt MagAsInt;
getSignAsIntValue(MagAsInt, DL, Mag);
- assert(SignAsInt.SignMask == MagAsInt.SignMask);
- SDValue ClearSignMask = DAG.getConstant(~SignAsInt.SignMask, DL, IntVT);
- SDValue ClearedSign = DAG.getNode(ISD::AND, DL, IntVT, MagAsInt.IntValue,
+ EVT MagVT = MagAsInt.IntValue.getValueType();
+ SDValue ClearSignMask = DAG.getConstant(~MagAsInt.SignMask, DL, MagVT);
+ SDValue ClearedSign = DAG.getNode(ISD::AND, DL, MagVT, MagAsInt.IntValue,
ClearSignMask);
- SDValue CopiedSign = DAG.getNode(ISD::OR, DL, IntVT, ClearedSign, SignBit);
+ // Get the signbit at the right position for MagAsInt.
+ int ShiftAmount = SignAsInt.SignBit - MagAsInt.SignBit;
+ if (SignBit.getValueSizeInBits() > ClearedSign.getValueSizeInBits()) {
+if (ShiftAmount > 0) {
+ SDValue ShiftCnst = DAG.getConstant(ShiftAmount, DL, IntVT);
+ SignBit = DAG.getNode(ISD::SRL, DL, IntVT, SignBit, ShiftCnst);
+} else if (ShiftAmount < 0) {
+ SDValue ShiftCnst = DAG.getConstant(-ShiftAmount, DL, IntVT);
+ SignBit = DAG.getNode(ISD::SHL, DL, IntVT, SignBit, ShiftCnst);
+}
+SignBit = DAG.getNode(ISD::TRUNCATE, DL, MagVT, SignBit);
+ } else if (SignBit.getValueSizeInBits() < ClearedSign.getValueSizeInBits()) {
+SignBit = DAG.getNode(ISD::ZERO_EXTEND, DL, MagVT, SignBit);
+if (ShiftAmount > 0) {
+ SDValue ShiftCnst = DAG.getConstant(Sh
[llvm-branch-commits] [llvm-branch] r261341 - Merge r261331: avoid out of bounds loads for interleaved access vectorization
Author: rengolin
Date: Fri Feb 19 11:35:27 2016
New Revision: 261341
URL: http://llvm.org/viewvc/llvm-project?rev=261341&view=rev
Log:
Merge r261331: avoid out of bounds loads for interleaved access vectorization
Modified:
llvm/branches/release_38/lib/Transforms/Vectorize/LoopVectorize.cpp
llvm/branches/release_38/test/Transforms/LoopVectorize/PowerPC/stride-vectorization.ll
llvm/branches/release_38/test/Transforms/LoopVectorize/interleaved-accesses.ll
Modified: llvm/branches/release_38/lib/Transforms/Vectorize/LoopVectorize.cpp
URL:
http://llvm.org/viewvc/llvm-project/llvm/branches/release_38/lib/Transforms/Vectorize/LoopVectorize.cpp?rev=261341&r1=261340&r2=261341&view=diff
==
--- llvm/branches/release_38/lib/Transforms/Vectorize/LoopVectorize.cpp
(original)
+++ llvm/branches/release_38/lib/Transforms/Vectorize/LoopVectorize.cpp Fri Feb
19 11:35:27 2016
@@ -4636,6 +4636,8 @@ void InterleavedAccessInfo::analyzeInter
// Holds all interleaved store groups temporarily.
SmallSetVector StoreGroups;
+ // Holds all interleaved load groups temporarily.
+ SmallSetVector LoadGroups;
// Search the load-load/write-write pair B-A in bottom-up order and try to
// insert B into the interleave group of A according to 3 rules:
@@ -4663,6 +4665,8 @@ void InterleavedAccessInfo::analyzeInter
if (A->mayWriteToMemory())
StoreGroups.insert(Group);
+else
+ LoadGroups.insert(Group);
for (auto II = std::next(I); II != E; ++II) {
Instruction *B = II->first;
@@ -4710,6 +4714,12 @@ void InterleavedAccessInfo::analyzeInter
for (InterleaveGroup *Group : StoreGroups)
if (Group->getNumMembers() != Group->getFactor())
releaseGroup(Group);
+
+ // Remove interleaved load groups that don't have the first and last member.
+ // This guarantees that we won't do speculative out of bounds loads.
+ for (InterleaveGroup *Group : LoadGroups)
+if (!Group->getMember(0) || !Group->getMember(Group->getFactor() - 1))
+ releaseGroup(Group);
}
LoopVectorizationCostModel::VectorizationFactor
Modified:
llvm/branches/release_38/test/Transforms/LoopVectorize/PowerPC/stride-vectorization.ll
URL:
http://llvm.org/viewvc/llvm-project/llvm/branches/release_38/test/Transforms/LoopVectorize/PowerPC/stride-vectorization.ll?rev=261341&r1=261340&r2=261341&view=diff
==
---
llvm/branches/release_38/test/Transforms/LoopVectorize/PowerPC/stride-vectorization.ll
(original)
+++
llvm/branches/release_38/test/Transforms/LoopVectorize/PowerPC/stride-vectorization.ll
Fri Feb 19 11:35:27 2016
@@ -16,9 +16,15 @@ for.cond.cleanup:
for.body: ; preds = %for.body, %entry
%indvars.iv = phi i64 [ 0, %entry ], [ %indvars.iv.next, %for.body ]
%0 = shl nsw i64 %indvars.iv, 1
+ %odd.idx = add nsw i64 %0, 1
+
%arrayidx = getelementptr inbounds double, double* %b, i64 %0
+ %arrayidx.odd = getelementptr inbounds double, double* %b, i64 %odd.idx
+
%1 = load double, double* %arrayidx, align 8
- %add = fadd double %1, 1.00e+00
+ %2 = load double, double* %arrayidx.odd, align 8
+
+ %add = fadd double %1, %2
%arrayidx2 = getelementptr inbounds double, double* %a, i64 %indvars.iv
store double %add, double* %arrayidx2, align 8
%indvars.iv.next = add nuw nsw i64 %indvars.iv, 1
Modified:
llvm/branches/release_38/test/Transforms/LoopVectorize/interleaved-accesses.ll
URL:
http://llvm.org/viewvc/llvm-project/llvm/branches/release_38/test/Transforms/LoopVectorize/interleaved-accesses.ll?rev=261341&r1=261340&r2=261341&view=diff
==
---
llvm/branches/release_38/test/Transforms/LoopVectorize/interleaved-accesses.ll
(original)
+++
llvm/branches/release_38/test/Transforms/LoopVectorize/interleaved-accesses.ll
Fri Feb 19 11:35:27 2016
@@ -292,10 +292,8 @@ for.body:
; }
; CHECK-LABEL: @even_load(
-; CHECK: %wide.vec = load <8 x i32>, <8 x i32>* %{{.*}}, align 4
-; CHECK: %strided.vec = shufflevector <8 x i32> %wide.vec, <8 x i32> undef, <4
x i32>
-; CHECK-NOT: shufflevector <8 x i32> %wide.vec, <8 x i32> undef, <4 x i32>
-; CHECK: shl nsw <4 x i32> %strided.vec,
+; CHECK-NOT: %wide.vec = load <8 x i32>, <8 x i32>* %{{.*}}, align 4
+; CHECK-NOT: %strided.vec = shufflevector <8 x i32> %wide.vec, <8 x i32>
undef, <4 x i32>
define void @even_load(i32* noalias nocapture readonly %A, i32* noalias
nocapture %B) {
entry:
___
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[llvm-branch-commits] [cfe-branch] r261343 - Merge r261309: ARM: fix VFP asm constraints
Author: rengolin Date: Fri Feb 19 11:40:14 2016 New Revision: 261343 URL: http://llvm.org/viewvc/llvm-project?rev=261343&view=rev Log: Merge r261309: ARM: fix VFP asm constraints Modified: cfe/branches/release_38/lib/Basic/Targets.cpp Modified: cfe/branches/release_38/lib/Basic/Targets.cpp URL: http://llvm.org/viewvc/llvm-project/cfe/branches/release_38/lib/Basic/Targets.cpp?rev=261343&r1=261342&r2=261343&view=diff == --- cfe/branches/release_38/lib/Basic/Targets.cpp (original) +++ cfe/branches/release_38/lib/Basic/Targets.cpp Fri Feb 19 11:40:14 2016 @@ -4915,8 +4915,8 @@ public: default: break; case 'l': // r0-r7 case 'h': // r8-r15 -case 'w': // VFP Floating point register single precision -case 'P': // VFP Floating point register double precision +case 't': // VFP Floating point register single precision +case 'w': // VFP Floating point register double precision Info.setAllowsRegister(); return true; case 'I': ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org http://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [cfe-branch] r261357 - Merge r261310: Add test for ARM: fix VFP asm constraints
Author: rengolin
Date: Fri Feb 19 13:36:35 2016
New Revision: 261357
URL: http://llvm.org/viewvc/llvm-project?rev=261357&view=rev
Log:
Merge r261310: Add test for ARM: fix VFP asm constraints
Added:
cfe/branches/release_38/test/CodeGen/arm-vfp-asm-constraint.c
Added: cfe/branches/release_38/test/CodeGen/arm-vfp-asm-constraint.c
URL:
http://llvm.org/viewvc/llvm-project/cfe/branches/release_38/test/CodeGen/arm-vfp-asm-constraint.c?rev=261357&view=auto
==
--- cfe/branches/release_38/test/CodeGen/arm-vfp-asm-constraint.c (added)
+++ cfe/branches/release_38/test/CodeGen/arm-vfp-asm-constraint.c Fri Feb 19
13:36:35 2016
@@ -0,0 +1,36 @@
+// REQUIRES: arm-registered-target
+// RUN: %clang_cc1 -triple armv7-unknown-unknown -mfpmath vfp -emit-llvm -o -
%s | FileCheck %s
+
+// CHECK-NOT: error:
+
+double fabs(double x) { // CHECK-LABEL: @fabs(
+ // CHECK: call double asm "vabs.f64 ${0:P}, ${1:P}", "=w,w"(double
+ __asm__("vabs.f64 %P0, %P1"
+ : "=w"(x)
+ : "w"(x));
+ return x;
+}
+
+float fabsf(float x) { // CHECK-LABEL: @fabsf(
+ // CHECK: call float asm "vabs.f32 $0, $1", "=t,t"(float
+ __asm__("vabs.f32 %0, %1"
+ : "=t"(x)
+ : "t"(x));
+ return x;
+}
+
+double sqrt(double x) { // CHECK-LABEL: @sqrt(
+ // CHECK: call double asm "vsqrt.f64 ${0:P}, ${1:P}", "=w,w"(double
+ __asm__("vsqrt.f64 %P0, %P1"
+ : "=w"(x)
+ : "w"(x));
+ return x;
+}
+
+float sqrtf(float x) { // CHECK-LABEL: @sqrtf(
+ // CHECK: call float asm "vsqrt.f32 $0, $1", "=t,t"(float
+ __asm__("vsqrt.f32 %0, %1"
+ : "=t"(x)
+ : "t"(x));
+ return x;
+}
___
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Re: [llvm-branch-commits] [cfe-branch] r261343 - Merge r261309: ARM: fix VFP asm constraints
On 19 February 2016 at 19:13, Hans Wennborg wrote: > Thanks! Can you take r261310 too? Sure! r261357. Thanks! --renato ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org http://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [compiler-rt-branch] r261359 - Merging r261148:
Author: hans
Date: Fri Feb 19 13:43:25 2016
New Revision: 261359
URL: http://llvm.org/viewvc/llvm-project?rev=261359&view=rev
Log:
Merging r261148:
r261148 | samsonov | 2016-02-17 12:40:10 -0800 (Wed, 17 Feb 2016) | 1 line
[TSan] PR26609: Fix two test cases.
Modified:
compiler-rt/branches/release_38/ (props changed)
compiler-rt/branches/release_38/test/tsan/ignore_lib0.cc
compiler-rt/branches/release_38/test/tsan/printf-1.c
Propchange: compiler-rt/branches/release_38/
--
--- svn:mergeinfo (original)
+++ svn:mergeinfo Fri Feb 19 13:43:25 2016
@@ -1 +1 @@
-/compiler-rt/trunk:258916,259755,260669,260839,261073,261142,261193,261263
+/compiler-rt/trunk:258916,259755,260669,260839,261073,261142,261148,261193,261263
Modified: compiler-rt/branches/release_38/test/tsan/ignore_lib0.cc
URL:
http://llvm.org/viewvc/llvm-project/compiler-rt/branches/release_38/test/tsan/ignore_lib0.cc?rev=261359&r1=261358&r2=261359&view=diff
==
--- compiler-rt/branches/release_38/test/tsan/ignore_lib0.cc (original)
+++ compiler-rt/branches/release_38/test/tsan/ignore_lib0.cc Fri Feb 19
13:43:25 2016
@@ -1,9 +1,9 @@
// RUN: %clangxx_tsan -O1 %s -DLIB -fPIC -fno-sanitize=thread -shared -o
%T/libignore_lib0.so
// RUN: %clangxx_tsan -O1 %s -L%T -lignore_lib0 -o %t
// RUN: echo running w/o suppressions:
-// RUN: LD_LIBRARY_PATH=%T${LD_LIBRARY_PATH:+:$LD_LIBRARY_PATH} %deflake %run
%t | FileCheck %s --check-prefix=CHECK-NOSUPP
+// RUN: env LD_LIBRARY_PATH=%T${LD_LIBRARY_PATH:+:$LD_LIBRARY_PATH} %deflake
%run %t | FileCheck %s --check-prefix=CHECK-NOSUPP
// RUN: echo running with suppressions:
-// RUN: LD_LIBRARY_PATH=%T${LD_LIBRARY_PATH:+:$LD_LIBRARY_PATH}
%env_tsan_opts=suppressions='%s.supp' %run %t 2>&1 | FileCheck %s
--check-prefix=CHECK-WITHSUPP
+// RUN: env LD_LIBRARY_PATH=%T${LD_LIBRARY_PATH:+:$LD_LIBRARY_PATH}
%env_tsan_opts=suppressions='%s.supp' %run %t 2>&1 | FileCheck %s
--check-prefix=CHECK-WITHSUPP
// Tests that interceptors coming from a library specified in called_from_lib
// suppression are ignored.
Modified: compiler-rt/branches/release_38/test/tsan/printf-1.c
URL:
http://llvm.org/viewvc/llvm-project/compiler-rt/branches/release_38/test/tsan/printf-1.c?rev=261359&r1=261358&r2=261359&view=diff
==
--- compiler-rt/branches/release_38/test/tsan/printf-1.c (original)
+++ compiler-rt/branches/release_38/test/tsan/printf-1.c Fri Feb 19 13:43:25
2016
@@ -1,6 +1,6 @@
// RUN: %clang_tsan -O2 %s -o %t
-// RUN: ASAN_OPTIONS=check_printf=1 %run %t 2>&1 | FileCheck %s
-// RUN: ASAN_OPTIONS=check_printf=0 %run %t 2>&1 | FileCheck %s
+// RUN: %env_tsan_opts=check_printf=1 %run %t 2>&1 | FileCheck %s
+// RUN: %env_tsan_opts=check_printf=0 %run %t 2>&1 | FileCheck %s
// RUN: %run %t 2>&1 | FileCheck %s
#include
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[llvm-branch-commits] [llvm-branch] r261366 - Merging r261365:
Author: hans
Date: Fri Feb 19 15:28:08 2016
New Revision: 261366
URL: http://llvm.org/viewvc/llvm-project?rev=261366&view=rev
Log:
Merging r261365:
r261365 | hans | 2016-02-19 13:26:31 -0800 (Fri, 19 Feb 2016) | 3 lines
Revert r253557 "Alternative to long nops for X86 CPUs, by Andrey Turetsky"
Turns out the new nop sequences aren't actually nops on x86_64 (PR26554).
Modified:
llvm/branches/release_38/ (props changed)
llvm/branches/release_38/lib/Target/X86/MCTargetDesc/X86AsmBackend.cpp
llvm/branches/release_38/test/MC/X86/x86_nop.s
Propchange: llvm/branches/release_38/
--
--- svn:mergeinfo (original)
+++ svn:mergeinfo Fri Feb 19 15:28:08 2016
@@ -1,3 +1,3 @@
/llvm/branches/Apple/Pertwee:110850,110961
/llvm/branches/type-system-rewrite:133420-134817
-/llvm/trunk:155241,257645,257648,257730,257775,257791,257864,257875,257886,257902,257905,257925,257929-257930,257940,257942,257977,257979,257997,258103,258112,258168,258184,258207,258221,258273,258325,258406,258416,258428,258436,258471,258609-258611,258616,258690,258729,258891,258971,259177-259178,259228,259236,259342,259346,259375,259381,259645,259649,259695-259696,259702,259740,259798,259835,259840,259886,259888,259958,260164,260390,260427,260587,260641,260703,260733,261033,261039,261258,261306
+/llvm/trunk:155241,257645,257648,257730,257775,257791,257864,257875,257886,257902,257905,257925,257929-257930,257940,257942,257977,257979,257997,258103,258112,258168,258184,258207,258221,258273,258325,258406,258416,258428,258436,258471,258609-258611,258616,258690,258729,258891,258971,259177-259178,259228,259236,259342,259346,259375,259381,259645,259649,259695-259696,259702,259740,259798,259835,259840,259886,259888,259958,260164,260390,260427,260587,260641,260703,260733,261033,261039,261258,261306,261365
Modified: llvm/branches/release_38/lib/Target/X86/MCTargetDesc/X86AsmBackend.cpp
URL:
http://llvm.org/viewvc/llvm-project/llvm/branches/release_38/lib/Target/X86/MCTargetDesc/X86AsmBackend.cpp?rev=261366&r1=261365&r2=261366&view=diff
==
--- llvm/branches/release_38/lib/Target/X86/MCTargetDesc/X86AsmBackend.cpp
(original)
+++ llvm/branches/release_38/lib/Target/X86/MCTargetDesc/X86AsmBackend.cpp Fri
Feb 19 15:28:08 2016
@@ -69,19 +69,15 @@ public:
class X86AsmBackend : public MCAsmBackend {
const StringRef CPU;
bool HasNopl;
- uint64_t MaxNopLength;
+ const uint64_t MaxNopLength;
public:
- X86AsmBackend(const Target &T, StringRef CPU) : MCAsmBackend(), CPU(CPU) {
+ X86AsmBackend(const Target &T, StringRef CPU)
+ : MCAsmBackend(), CPU(CPU), MaxNopLength(CPU == "slm" ? 7 : 15) {
HasNopl = CPU != "generic" && CPU != "i386" && CPU != "i486" &&
CPU != "i586" && CPU != "pentium" && CPU != "pentium-mmx" &&
CPU != "i686" && CPU != "k6" && CPU != "k6-2" && CPU != "k6-3" &&
CPU != "geode" && CPU != "winchip-c6" && CPU != "winchip2" &&
CPU != "c3" && CPU != "c3-2";
-// Max length of true long nop instruction is 15 bytes.
-// Max length of long nop replacement instruction is 7 bytes.
-// Taking into account SilverMont architecture features max length of nops
-// is reduced for it to achieve better performance.
-MaxNopLength = (!HasNopl || CPU == "slm") ? 7 : 15;
}
unsigned getNumFixupKinds() const override {
@@ -299,7 +295,7 @@ void X86AsmBackend::relaxInstruction(con
/// bytes.
/// \return - true on success, false on failure
bool X86AsmBackend::writeNopData(uint64_t Count, MCObjectWriter *OW) const {
- static const uint8_t TrueNops[10][10] = {
+ static const uint8_t Nops[10][10] = {
// nop
{0x90},
// xchg %ax,%ax
@@ -322,31 +318,17 @@ bool X86AsmBackend::writeNopData(uint64_
{0x66, 0x2e, 0x0f, 0x1f, 0x84, 0x00, 0x00, 0x00, 0x00, 0x00},
};
- // Alternative nop instructions for CPUs which don't support long nops.
- static const uint8_t AltNops[7][10] = {
- // nop
- {0x90},
- // xchg %ax,%ax
- {0x66, 0x90},
- // lea 0x0(%esi),%esi
- {0x8d, 0x76, 0x00},
- // lea 0x0(%esi),%esi
- {0x8d, 0x74, 0x26, 0x00},
- // nop + lea 0x0(%esi),%esi
- {0x90, 0x8d, 0x74, 0x26, 0x00},
- // lea 0x0(%esi),%esi
- {0x8d, 0xb6, 0x00, 0x00, 0x00, 0x00 },
- // lea 0x0(%esi),%esi
- {0x8d, 0xb4, 0x26, 0x00, 0x00, 0x00, 0x00},
- };
-
- // Select the right NOP table.
- // FIXME: Can we get if CPU supports long nops from the subtarget somehow?
- const uint8_t (*Nops)[10] = HasNopl ? TrueNops : AltNops;
- assert(HasNopl || MaxNopLength <= 7);
+ // This CPU doesn't support long nops. If needed add more.
+ // FIXME: Can we get this from the subtarget somehow?
+ // FIXME: We could gen
[llvm-branch-commits] [llvm-branch] r261367 - Merging r261360:
Author: hans
Date: Fri Feb 19 15:35:00 2016
New Revision: 261367
URL: http://llvm.org/viewvc/llvm-project?rev=261367&view=rev
Log:
Merging r261360:
r261360 | dim | 2016-02-19 12:14:11 -0800 (Fri, 19 Feb 2016) | 19 lines
Fix incorrect selection of AVX512 sqrt when OptForSize is on
Summary:
When optimizing for size, sqrt calls can be incorrectly selected as
AVX512 VSQRT instructions. This is because X86InstrAVX512.td has a
`Requires<[OptForSize]>` in its `avx512_sqrt_scalar` multiclass
definition. Even if the target does not support AVX512, the class can
apparently still be chosen, leading to an incorrect selection of
`vsqrtss`.
In PR26625, this lead to an assertion: Reg >= X86::FP0 && Reg <=
X86::FP6 && "Expected FP register!", because the `vsqrtss` instruction
requires an XMM register, which is not available on i686 CPUs.
Reviewers: grosbach, resistor, joker.eph
Subscribers: spatel, emaste, llvm-commits
Differential Revision: http://reviews.llvm.org/D17414
Added:
llvm/branches/release_38/test/CodeGen/X86/pr26625.ll
- copied unchanged from r261360, llvm/trunk/test/CodeGen/X86/pr26625.ll
Modified:
llvm/branches/release_38/ (props changed)
llvm/branches/release_38/lib/Target/X86/X86InstrAVX512.td
Propchange: llvm/branches/release_38/
--
--- svn:mergeinfo (original)
+++ svn:mergeinfo Fri Feb 19 15:35:00 2016
@@ -1,3 +1,3 @@
/llvm/branches/Apple/Pertwee:110850,110961
/llvm/branches/type-system-rewrite:133420-134817
-/llvm/trunk:155241,257645,257648,257730,257775,257791,257864,257875,257886,257902,257905,257925,257929-257930,257940,257942,257977,257979,257997,258103,258112,258168,258184,258207,258221,258273,258325,258406,258416,258428,258436,258471,258609-258611,258616,258690,258729,258891,258971,259177-259178,259228,259236,259342,259346,259375,259381,259645,259649,259695-259696,259702,259740,259798,259835,259840,259886,259888,259958,260164,260390,260427,260587,260641,260703,260733,261033,261039,261258,261306,261365
+/llvm/trunk:155241,257645,257648,257730,257775,257791,257864,257875,257886,257902,257905,257925,257929-257930,257940,257942,257977,257979,257997,258103,258112,258168,258184,258207,258221,258273,258325,258406,258416,258428,258436,258471,258609-258611,258616,258690,258729,258891,258971,259177-259178,259228,259236,259342,259346,259375,259381,259645,259649,259695-259696,259702,259740,259798,259835,259840,259886,259888,259958,260164,260390,260427,260587,260641,260703,260733,261033,261039,261258,261306,261360,261365
Modified: llvm/branches/release_38/lib/Target/X86/X86InstrAVX512.td
URL:
http://llvm.org/viewvc/llvm-project/llvm/branches/release_38/lib/Target/X86/X86InstrAVX512.td?rev=261367&r1=261366&r2=261367&view=diff
==
--- llvm/branches/release_38/lib/Target/X86/X86InstrAVX512.td (original)
+++ llvm/branches/release_38/lib/Target/X86/X86InstrAVX512.td Fri Feb 19
15:35:00 2016
@@ -5896,7 +5896,7 @@ multiclass avx512_sqrt_scalar op
def : Pat<(_.EltVT (OpNode (load addr:$src))),
(!cast(NAME#SUFF#Zm)
-(_.EltVT (IMPLICIT_DEF)), addr:$src)>, Requires<[OptForSize]>;
+(_.EltVT (IMPLICIT_DEF)), addr:$src)>, Requires<[HasAVX512,
OptForSize]>;
}
multiclass avx512_sqrt_scalar_all opc, string OpcodeStr> {
___
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[llvm-branch-commits] [llvm-branch] r261369 - Merging r261368:
Author: hans
Date: Fri Feb 19 15:42:57 2016
New Revision: 261369
URL: http://llvm.org/viewvc/llvm-project?rev=261369&view=rev
Log:
Merging r261368:
r261368 | hans | 2016-02-19 13:40:12 -0800 (Fri, 19 Feb 2016) | 3 lines
Revert r255691 "[LoopVectorizer] Refine loop vectorizer's register usage
calculator by ignoring specific instructions."
It caused PR26509.
Removed:
llvm/branches/release_38/test/Transforms/LoopVectorize/X86/reg-usage.ll
Modified:
llvm/branches/release_38/ (props changed)
llvm/branches/release_38/lib/Transforms/Vectorize/LoopVectorize.cpp
llvm/branches/release_38/test/Transforms/LoopVectorize/X86/vector_max_bandwidth.ll
Propchange: llvm/branches/release_38/
--
--- svn:mergeinfo (original)
+++ svn:mergeinfo Fri Feb 19 15:42:57 2016
@@ -1,3 +1,3 @@
/llvm/branches/Apple/Pertwee:110850,110961
/llvm/branches/type-system-rewrite:133420-134817
-/llvm/trunk:155241,257645,257648,257730,257775,257791,257864,257875,257886,257902,257905,257925,257929-257930,257940,257942,257977,257979,257997,258103,258112,258168,258184,258207,258221,258273,258325,258406,258416,258428,258436,258471,258609-258611,258616,258690,258729,258891,258971,259177-259178,259228,259236,259342,259346,259375,259381,259645,259649,259695-259696,259702,259740,259798,259835,259840,259886,259888,259958,260164,260390,260427,260587,260641,260703,260733,261033,261039,261258,261306,261360,261365
+/llvm/trunk:155241,257645,257648,257730,257775,257791,257864,257875,257886,257902,257905,257925,257929-257930,257940,257942,257977,257979,257997,258103,258112,258168,258184,258207,258221,258273,258325,258406,258416,258428,258436,258471,258609-258611,258616,258690,258729,258891,258971,259177-259178,259228,259236,259342,259346,259375,259381,259645,259649,259695-259696,259702,259740,259798,259835,259840,259886,259888,259958,260164,260390,260427,260587,260641,260703,260733,261033,261039,261258,261306,261360,261365,261368
Modified: llvm/branches/release_38/lib/Transforms/Vectorize/LoopVectorize.cpp
URL:
http://llvm.org/viewvc/llvm-project/llvm/branches/release_38/lib/Transforms/Vectorize/LoopVectorize.cpp?rev=261369&r1=261368&r2=261369&view=diff
==
--- llvm/branches/release_38/lib/Transforms/Vectorize/LoopVectorize.cpp
(original)
+++ llvm/branches/release_38/lib/Transforms/Vectorize/LoopVectorize.cpp Fri Feb
19 15:42:57 2016
@@ -1409,14 +1409,15 @@ private:
/// different operations.
class LoopVectorizationCostModel {
public:
- LoopVectorizationCostModel(Loop *L, PredicatedScalarEvolution &PSE,
- LoopInfo *LI, LoopVectorizationLegality *Legal,
+ LoopVectorizationCostModel(Loop *L, ScalarEvolution *SE, LoopInfo *LI,
+ LoopVectorizationLegality *Legal,
const TargetTransformInfo &TTI,
const TargetLibraryInfo *TLI, DemandedBits *DB,
AssumptionCache *AC, const Function *F,
- const LoopVectorizeHints *Hints)
- : TheLoop(L), PSE(PSE), LI(LI), Legal(Legal), TTI(TTI), TLI(TLI), DB(DB),
-AC(AC), TheFunction(F), Hints(Hints) {}
+ const LoopVectorizeHints *Hints,
+ SmallPtrSetImpl &ValuesToIgnore)
+ : TheLoop(L), SE(SE), LI(LI), Legal(Legal), TTI(TTI), TLI(TLI), DB(DB),
+TheFunction(F), Hints(Hints), ValuesToIgnore(ValuesToIgnore) {}
/// Information about vectorization costs
struct VectorizationFactor {
@@ -1464,9 +1465,6 @@ public:
SmallVector
calculateRegisterUsage(const SmallVector &VFs);
- /// Collect values we want to ignore in the cost model.
- void collectValuesToIgnore();
-
private:
/// Returns the expected execution cost. The unit of the cost does
/// not matter because we use the 'cost' units to compare different
@@ -1498,8 +1496,8 @@ public:
/// The loop that we evaluate.
Loop *TheLoop;
- /// Predicated scalar evolution analysis.
- PredicatedScalarEvolution &PSE;
+ /// Scev analysis.
+ ScalarEvolution *SE;
/// Loop Info analysis.
LoopInfo *LI;
/// Vectorization legality.
@@ -1508,17 +1506,13 @@ public:
const TargetTransformInfo &TTI;
/// Target Library Info.
const TargetLibraryInfo *TLI;
- /// Demanded bits analysis.
+ /// Demanded bits analysis
DemandedBits *DB;
- /// Assumption cache.
- AssumptionCache *AC;
const Function *TheFunction;
- /// Loop Vectorize Hint.
+ // Loop Vectorize Hint.
const LoopVectorizeHints *Hints;
- /// Values to ignore in the cost model.
- SmallPtrSet ValuesToIgnore;
- /// Values to ignore in the cost model when VF > 1.
- SmallPtrSet VecValuesToIgnore;
+ // Values to ignore in the
