[Lldb-commits] [PATCH] D62732: [RISCV] Add SystemV ABI

[Luís Marques via Phabricator via lldb-commits]

luismarques added a comment.

In D62732#3157524 , @kasper81 wrote:

> Hi Luis, are you planning on adding plugin architecture support (in 
> `lldb/source/Plugins/Architecture`) as part of this work?

I commandeered this patch from Simon Cook, the original author, but I haven't 
been a good steward. For a while I seemed to always have something higher 
priority in my queue and eventually I kinda stopped thinking about it. So don't 
rely on my plans for this patch. Feel free to adopt it and continue this line 
of work. My apologies to the community.


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[Lldb-commits] [PATCH] D62732: [RISCV] Add SystemV ABI

[Luís Marques via Phabricator via lldb-commits]

luismarques added a comment.

In D62732#2789409 , @sven wrote:

> I have tried the patch with llvm12, test case is provide by 
> jade(https://gist.github.com/e2efac2f780ed820277dbaf608805f4e), but it didn't 
> worked for me.
> It seems that the unwind didn't succeed, can you figure out the problem?

That's surprising. I'll see if I can figure out what the issue might be. Thanks.


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[Lldb-commits] [PATCH] D62732: [RISCV] Add SystemV ABI

[Luís Marques via Phabricator via lldb-commits]

luismarques added a comment.

In D62732#2790028 , @luismarques wrote:

> That's surprising. I'll see if I can figure out what the issue might be. 
> Thanks.

Confirmed. Something must have broken since the last patch revision. I'll see 
if I can figure out / fix this soon.


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[Lldb-commits] [PATCH] D62732: [RISCV] Add SystemV ABI

[Luís Marques via Phabricator via lldb-commits]

luismarques added a comment.

In D62732#2875107 , @kasper81 wrote:

> Hi, I have my fingers crossed since this request was opened in 2019. It seems 
> like it compiles and usable to certain degree. Can this patch be merged and 
> included in llvm 13 as initial riscv64 support? We can then improve it 
> subsequently if bugs show up. Otherwise it will be one more year of waiting 
> for the consumers. Thank you for your effort!

I think the main blocker for merging was testing. If it helps, I now have the 
RISC-V server in my hands and I should be able to set up a buildbot soon.


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[Lldb-commits] [PATCH] D62732: [RISCV] Add SystemV ABI

[Luís Marques via Phabricator via lldb-commits]

luismarques added a comment.

In D62732#2707945 , @jade wrote:

> These files are also available as a gist, which can be grabbed with: `git 
> clone https://gist.github.com/e2efac2f780ed820277dbaf608805f4e 
> lldb-riscv-repro`

Thank you for the reproducer. I think I've isolated the issue. I'll see if I 
can provide a fix.


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[Lldb-commits] [PATCH] D62732: [RISCV] Add SystemV ABI

[Luís Marques via Phabricator via lldb-commits]

luismarques updated this revision to Diff 341153.
luismarques added a comment.

Rebase and fix the unwinding issue reported by @jade.


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Files:
  lldb/include/lldb/Utility/ArchSpec.h
  lldb/source/Plugins/ABI/CMakeLists.txt
  lldb/source/Plugins/ABI/RISCV/ABISysV_riscv.cpp
  lldb/source/Plugins/ABI/RISCV/ABISysV_riscv.h
  lldb/source/Plugins/ABI/RISCV/CMakeLists.txt
  lldb/source/Plugins/Disassembler/LLVMC/DisassemblerLLVMC.cpp
  lldb/source/Plugins/ObjectFile/ELF/ObjectFileELF.cpp
  lldb/source/Target/Platform.cpp

Index: lldb/source/Target/Platform.cpp
===
--- lldb/source/Target/Platform.cpp
+++ lldb/source/Target/Platform.cpp
@@ -1970,6 +1970,20 @@
 trap_opcode_size = sizeof(g_i386_opcode);
   } break;
 
+  case llvm::Triple::riscv32:
+  case llvm::Triple::riscv64: {
+static const uint8_t g_riscv_c_opcode[] = {0x02, 0x90}; // c_ebreak
+static const uint8_t g_riscv_opcode[] = {0x73, 0x00, 0x10, 0x00}; // ebreak
+if (arch.GetFlags() & ArchSpec::eRISCV_arch_c) {
+  trap_opcode = g_riscv_c_opcode;
+  trap_opcode_size = sizeof(g_riscv_c_opcode);
+} else {
+  trap_opcode = g_riscv_opcode;
+  trap_opcode_size = sizeof(g_riscv_opcode);
+}
+break;
+  }
+
   default:
 return 0;
   }
Index: lldb/source/Plugins/ObjectFile/ELF/ObjectFileELF.cpp
===
--- lldb/source/Plugins/ObjectFile/ELF/ObjectFileELF.cpp
+++ lldb/source/Plugins/ObjectFile/ELF/ObjectFileELF.cpp
@@ -1376,6 +1376,18 @@
   arch_spec.SetFlags(ArchSpec::eARM_abi_hard_float);
   }
 
+  if (arch_spec.GetMachine() == llvm::Triple::riscv32 ||
+  arch_spec.GetMachine() == llvm::Triple::riscv64) {
+if (header.e_flags & llvm::ELF::EF_RISCV_RVC)
+  arch_spec.SetFlags(ArchSpec::eRISCV_arch_c);
+if ((header.e_flags & llvm::ELF::EF_RISCV_FLOAT_ABI) ==
+llvm::ELF::EF_RISCV_FLOAT_ABI_SINGLE)
+  arch_spec.SetFlags(ArchSpec::eRISCV_abi_f);
+if ((header.e_flags & llvm::ELF::EF_RISCV_FLOAT_ABI) ==
+llvm::ELF::EF_RISCV_FLOAT_ABI_DOUBLE)
+  arch_spec.SetFlags(ArchSpec::eRISCV_abi_d);
+  }
+
   // If there are no section headers we are done.
   if (header.e_shnum == 0)
 return 0;
Index: lldb/source/Plugins/Disassembler/LLVMC/DisassemblerLLVMC.cpp
===
--- lldb/source/Plugins/Disassembler/LLVMC/DisassemblerLLVMC.cpp
+++ lldb/source/Plugins/Disassembler/LLVMC/DisassemblerLLVMC.cpp
@@ -1146,6 +1146,11 @@
   cpu = "apple-latest";
   }
 
+  // For RISC-V, enable all standard extensions so these can be disassembled.
+  if (triple.getArch() == llvm::Triple::riscv32 ||
+  triple.getArch() == llvm::Triple::riscv64)
+features_str += "+a,+c,+d,+f,+m";
+
   // We use m_disasm_up.get() to tell whether we are valid or not, so if this
   // isn't good for some reason, we won't be valid and FindPlugin will fail and
   // we won't get used.
Index: lldb/source/Plugins/ABI/RISCV/CMakeLists.txt
===
--- /dev/null
+++ lldb/source/Plugins/ABI/RISCV/CMakeLists.txt
@@ -0,0 +1,10 @@
+add_lldb_library(lldbPluginABISysV_riscv PLUGIN
+  ABISysV_riscv.cpp
+
+  LINK_LIBS
+lldbCore
+lldbSymbol
+lldbTarget
+  LINK_COMPONENTS
+Support
+  )
Index: lldb/source/Plugins/ABI/RISCV/ABISysV_riscv.h
===
--- /dev/null
+++ lldb/source/Plugins/ABI/RISCV/ABISysV_riscv.h
@@ -0,0 +1,119 @@
+//===-- ABISysV_riscv.h -*- C++ -*-===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===--===//
+
+#ifndef liblldb_ABISysV_riscv_h_
+#define liblldb_ABISysV_riscv_h_
+
+#include "lldb/Target/ABI.h"
+#include "lldb/lldb-private.h"
+
+class ABISysV_riscv : public lldb_private::MCBasedABI {
+  bool isRV64;
+
+public:
+  ~ABISysV_riscv() override = default;
+
+  size_t GetRedZoneSize() const override { return 0; }
+
+  bool PrepareTrivialCall(lldb_private::Thread &thread, lldb::addr_t sp,
+  lldb::addr_t functionAddress,
+  lldb::addr_t returnAddress,
+  llvm::ArrayRef args) const override {
+// TODO: Implement
+return false;
+  }
+
+  bool GetArgumentValues(lldb_private::Thread &thread,
+ lldb_private::ValueList &values) const override {
+// TODO: Implement
+return false;
+  }
+
+  lldb_private::Status
+  SetReturnValueObject(lldb::StackFrameSP &frame_sp,
+   lld

[Lldb-commits] [PATCH] D62732: [RISCV] Add SystemV ABI

[Luís Marques via Phabricator via lldb-commits]

luismarques added a comment.

In D62732#2724040 , @JDevlieghere 
wrote:

> Any update on the testing strategy yet? It seems like that this is actively 
> being used and worked on, so I'm generally supportive of landing this with 
> some elementary coverage.

A while ago I got a skeleton of lldb-server compiling for RISC-V, but it seemed 
like it would be quite a bit of work to flesh out that implementation. I can 
only allocate some amount of effort to that right now, so that part might take 
a while to get finished.

I was going to follow up on @labath's suggestions of further testing just this 
patch (the ObjectFileELF and the disassembler changes), but some other work got 
in the way. That bit should be easier to prioritize, especially if we agreed 
that such kind of testing would be enough to get this landed.


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[Lldb-commits] [PATCH] D62732: [RISCV] Add SystemV ABI

[Luís Marques via Phabricator via lldb-commits]

luismarques updated this revision to Diff 341471.
luismarques added a comment.

Address review feedback.


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Files:
  lldb/include/lldb/Utility/ArchSpec.h
  lldb/source/Plugins/ABI/CMakeLists.txt
  lldb/source/Plugins/ABI/RISCV/ABISysV_riscv.cpp
  lldb/source/Plugins/ABI/RISCV/ABISysV_riscv.h
  lldb/source/Plugins/ABI/RISCV/CMakeLists.txt
  lldb/source/Plugins/Disassembler/LLVMC/DisassemblerLLVMC.cpp
  lldb/source/Plugins/ObjectFile/ELF/ObjectFileELF.cpp
  lldb/source/Target/Platform.cpp

Index: lldb/source/Target/Platform.cpp
===
--- lldb/source/Target/Platform.cpp
+++ lldb/source/Target/Platform.cpp
@@ -1970,6 +1970,20 @@
 trap_opcode_size = sizeof(g_i386_opcode);
   } break;
 
+  case llvm::Triple::riscv32:
+  case llvm::Triple::riscv64: {
+static const uint8_t g_riscv_c_opcode[] = {0x02, 0x90}; // c_ebreak
+static const uint8_t g_riscv_opcode[] = {0x73, 0x00, 0x10, 0x00}; // ebreak
+if (arch.GetFlags() & ArchSpec::eRISCV_arch_c) {
+  trap_opcode = g_riscv_c_opcode;
+  trap_opcode_size = sizeof(g_riscv_c_opcode);
+} else {
+  trap_opcode = g_riscv_opcode;
+  trap_opcode_size = sizeof(g_riscv_opcode);
+}
+break;
+  }
+
   default:
 return 0;
   }
Index: lldb/source/Plugins/ObjectFile/ELF/ObjectFileELF.cpp
===
--- lldb/source/Plugins/ObjectFile/ELF/ObjectFileELF.cpp
+++ lldb/source/Plugins/ObjectFile/ELF/ObjectFileELF.cpp
@@ -1377,6 +1377,18 @@
   arch_spec.SetFlags(ArchSpec::eARM_abi_hard_float);
   }
 
+  if (arch_spec.GetMachine() == llvm::Triple::riscv32 ||
+  arch_spec.GetMachine() == llvm::Triple::riscv64) {
+if (header.e_flags & llvm::ELF::EF_RISCV_RVC)
+  arch_spec.SetFlags(ArchSpec::eRISCV_arch_c);
+if ((header.e_flags & llvm::ELF::EF_RISCV_FLOAT_ABI) ==
+llvm::ELF::EF_RISCV_FLOAT_ABI_SINGLE)
+  arch_spec.SetFlags(ArchSpec::eRISCV_abi_f);
+if ((header.e_flags & llvm::ELF::EF_RISCV_FLOAT_ABI) ==
+llvm::ELF::EF_RISCV_FLOAT_ABI_DOUBLE)
+  arch_spec.SetFlags(ArchSpec::eRISCV_abi_d);
+  }
+
   // If there are no section headers we are done.
   if (header.e_shnum == 0)
 return 0;
Index: lldb/source/Plugins/Disassembler/LLVMC/DisassemblerLLVMC.cpp
===
--- lldb/source/Plugins/Disassembler/LLVMC/DisassemblerLLVMC.cpp
+++ lldb/source/Plugins/Disassembler/LLVMC/DisassemblerLLVMC.cpp
@@ -1146,6 +1146,11 @@
   cpu = "apple-latest";
   }
 
+  // For RISC-V, enable all standard extensions so these can be disassembled.
+  if (triple.getArch() == llvm::Triple::riscv32 ||
+  triple.getArch() == llvm::Triple::riscv64)
+features_str += "+a,+c,+d,+f,+m";
+
   // We use m_disasm_up.get() to tell whether we are valid or not, so if this
   // isn't good for some reason, we won't be valid and FindPlugin will fail and
   // we won't get used.
Index: lldb/source/Plugins/ABI/RISCV/CMakeLists.txt
===
--- /dev/null
+++ lldb/source/Plugins/ABI/RISCV/CMakeLists.txt
@@ -0,0 +1,10 @@
+add_lldb_library(lldbPluginABISysV_riscv PLUGIN
+  ABISysV_riscv.cpp
+
+  LINK_LIBS
+lldbCore
+lldbSymbol
+lldbTarget
+  LINK_COMPONENTS
+Support
+  )
Index: lldb/source/Plugins/ABI/RISCV/ABISysV_riscv.h
===
--- /dev/null
+++ lldb/source/Plugins/ABI/RISCV/ABISysV_riscv.h
@@ -0,0 +1,119 @@
+//===-- ABISysV_riscv.h -*- C++ -*-===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===--===//
+
+#ifndef liblldb_ABISysV_riscv_h_
+#define liblldb_ABISysV_riscv_h_
+
+#include "lldb/Target/ABI.h"
+#include "lldb/lldb-private.h"
+
+class ABISysV_riscv : public lldb_private::MCBasedABI {
+  bool isRV64;
+
+public:
+  ~ABISysV_riscv() override = default;
+
+  size_t GetRedZoneSize() const override { return 0; }
+
+  bool PrepareTrivialCall(lldb_private::Thread &thread, lldb::addr_t sp,
+  lldb::addr_t functionAddress,
+  lldb::addr_t returnAddress,
+  llvm::ArrayRef args) const override {
+// TODO: Implement
+return false;
+  }
+
+  bool GetArgumentValues(lldb_private::Thread &thread,
+ lldb_private::ValueList &values) const override {
+// TODO: Implement
+return false;
+  }
+
+  lldb_private::Status
+  SetReturnValueObject(lldb::StackFrameSP &frame_sp,
+   lldb::ValueObjectSP &new_value) 

[Lldb-commits] [PATCH] D62732: [RISCV] Add SystemV ABI

[Luís Marques via Phabricator via lldb-commits]

luismarques added a comment.

In D62732#2038309 , @jrtc27 wrote:

> Yeah, I don't think we want to be merging code we can't test even in a 
> non-automated way. Even if this code is completely bug-free, the inability to 
> test it just means we risk having it bit-rot with nobody noticing.

We now have two open-source debug servers that we can use to test this patch: 
gdbserver and QEMU's gdbstub, both of which now have RISC-V support. I rebased 
this patch and tested it with both.
My initial tests were with QEMU/gdbstub, and I was quite pleased with the 
results. I could set breakpoints, continue execution, step line-by-line and 
instruction-by-instruction and print registers (GPRs and CSRs). The backtrace 
was only showing the current frame. Still, I would say that LLDB was in a good 
enough state to be useful. Next, I tested it against gdbserver (compiled from 
git main) running in a Fedora RISC-V machine. Setting a breakpoint would 
seemingly succeed (e.g. it reported success, with the correct code address), 
but the code doesn't actually trap. You can still break with Ctrl-C though, and 
print registers and so on. So there seem to be some additional issues, but I 
also had problems when connecting less recent versions of GDB to that debug 
server, so we might just need to do some adjustments to match the GDB changes.

It seems that, once rebased, this patch is in pretty good shape. lowRISC is 
keen to see LLDB get RISC-V support, and I'm now ramping up work to help with 
that. Given the great work that we already have in this patch, I think an 
important first step would be to land it. None of the issues I encountered were 
obviously due to the code in this patch (and the things still marked as TODO), 
so I don't see any major downside to merging it. I will do a more in-depth 
investigation of the issues I encountered, but that shouldn't be a blocker to 
this patch. Landing this contribution would make it easier for others to 
contribute the missing pieces, and fixes for the issues, without having to 
submit duplicate work.

If it helps, feel free to use this commit [1], it's pretty much just a rebase 
of this patch.
@simoncook please let me know if you plan to update this patch and get it 
approved and landed (LGTM, once rebased), or other ways in which it would make 
sense to coordinate our work.

[1] 
https://github.com/luismarques/llvm-project/commit/4a0cccb0cfa8cb5c59c8803077a76751498447ec


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[Lldb-commits] [PATCH] D62732: [RISCV] Add SystemV ABI

[Luís Marques via Phabricator via lldb-commits]

luismarques added a comment.

In D62732#2193729 , @simoncook wrote:

> As for next steps, if we're happy with the state then I think this should 
> land (assuming qemu is sufficient given it is public), and then we can flesh 
> out other bits which give a better experience. I'm not sure how to connect 
> this to any automated testing, or where to document any way of checking this 
> manually, the state of that isn't quite clear, so any clarity there helps.

Yeah, I think that after the rebase this is nearly ready to land. The only 
additional suggestions I have at this point are:

- We should probably follow the convention and put the registers in 
`Plugins/Process/Utility/RegisterInfos_riscv.h`, like is done for other archs. 
If that isn't trivial I guess it could be a follow-up patch.
- Review the list of callee-saved registers. Aren't `x25` and `x26` missing?
- Nit: there's a typo in this patch that I missed in my rebased commit and 
should be corrected: "poinrter".
- I had renamed the `RISCVflags` members, if you use my rebased commit please 
check if you agree with that alternative.

> I'm curious about your backtrace showing one frame, is that something without 
> debug information, since the example I was using when writing this did show a 
> backtrace back to main? It would be good to understand why that disn't 
> produce the expected output.

It is with debug information. I had been looking at other issues, but I'm going 
to look into this and I'll let you know what I find out.

> Beyond this I think the next stage is implementing the parts for calling 
> functions within a target, which if you could help with that would be great. 
> I see that as a follow up patch to this, I don't see the two necessarily 
> having to land together, since this part enables a useful debugging 
> experience already.

I agree, we can land this and provide follow-up patches. For my next steps I 
was looking into fixing the issues I was experiencing, if possible, and then 
implementing those TODOs. One of the issues I've diagnosed is that we need to 
add extra logic to handle RV32 vs RV64 based on the ELF header, like is done 
for MIPS, otherwise it incorrectly assumes RV32 when it should be RV64. I'll 
provide a follow-up patch.

Thanks for the feedback and the patch @simoncook!


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[Lldb-commits] [PATCH] D86292: [LLDB][RISCV] Distinguish between riscv32 and riscv64 based on ELF class

[Luís Marques via Phabricator via lldb-commits]

luismarques created this revision.
luismarques added reviewers: asb, lenary, clayborg, jasonmolenda, simoncook.
Herald added subscribers: lldb-commits, evandro, apazos, sameer.abuasal, 
pzheng, s.egerton, Jim, benna, psnobl, jocewei, PkmX, the_o, brucehoult, 
MartinMosbeck, rogfer01, atanasyan, edward-jones, zzheng, jrtc27, shiva0217, 
kito-cheng, niosHD, sabuasal, johnrusso, rbar, arichardson, sdardis, emaste.
Herald added a reviewer: espindola.
Herald added a project: LLDB.
luismarques requested review of this revision.
Herald added subscribers: JDevlieghere, MaskRay.

LLDB was detecting riscv64 ELF files as riscv32. This patch fixes that issue.

The patch follows the implementation approach previously used for MIPS. It 
defines RISC-V architecture subtypes and inspects the ELF header, namely the 
ELF class, to detect the right subtype. At the moment this is slightly silly, 
as the subtypes coincide with the architecture types (rv32 vs rv64), but given 
how the existing code was structured this seemed like a straightforward and 
future-proof solution.


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Files:
  lldb/include/lldb/Utility/ArchSpec.h
  lldb/source/Plugins/ObjectFile/ELF/ObjectFileELF.cpp
  lldb/source/Utility/ArchSpec.cpp
  lldb/test/Shell/ObjectFile/ELF/riscv64-arch.yaml


Index: lldb/test/Shell/ObjectFile/ELF/riscv64-arch.yaml
===
--- /dev/null
+++ lldb/test/Shell/ObjectFile/ELF/riscv64-arch.yaml
@@ -0,0 +1,11 @@
+# RUN: yaml2obj %s > %t
+# RUN: lldb-test object-file %t | FileCheck %s
+
+# CHECK: Architecture: riscv64--
+
+--- !ELF
+FileHeader:
+  Class:   ELFCLASS64
+  Data:ELFDATA2LSB
+  Type:ET_EXEC
+  Machine: EM_RISCV
Index: lldb/source/Utility/ArchSpec.cpp
===
--- lldb/source/Utility/ArchSpec.cpp
+++ lldb/source/Utility/ArchSpec.cpp
@@ -457,10 +457,10 @@
  0xu, 0xu}, // ARC
 {ArchSpec::eCore_avr, llvm::ELF::EM_AVR, LLDB_INVALID_CPUTYPE,
  0xu, 0xu}, // AVR
-{ArchSpec::eCore_riscv32, llvm::ELF::EM_RISCV, LLDB_INVALID_CPUTYPE,
- 0xu, 0xu}, // riscv32
-{ArchSpec::eCore_riscv64, llvm::ELF::EM_RISCV, LLDB_INVALID_CPUTYPE,
- 0xu, 0xu}, // riscv64
+{ArchSpec::eCore_riscv32, llvm::ELF::EM_RISCV,
+ ArchSpec::eRISCVSubType_riscv32, 0xu, 0xu}, // riscv32
+{ArchSpec::eCore_riscv64, llvm::ELF::EM_RISCV,
+ ArchSpec::eRISCVSubType_riscv64, 0xu, 0xu}, // riscv64
 };
 
 static const ArchDefinition g_elf_arch_def = {
Index: lldb/source/Plugins/ObjectFile/ELF/ObjectFileELF.cpp
===
--- lldb/source/Plugins/ObjectFile/ELF/ObjectFileELF.cpp
+++ lldb/source/Plugins/ObjectFile/ELF/ObjectFileELF.cpp
@@ -296,9 +296,23 @@
   return arch_variant;
 }
 
+static uint32_t riscvVariantFromElfFlags(const elf::ELFHeader &header) {
+  uint32_t fileclass = header.e_ident[EI_CLASS];
+  switch (fileclass) {
+  case llvm::ELF::ELFCLASS32:
+return ArchSpec::eRISCVSubType_riscv32;
+  case llvm::ELF::ELFCLASS64:
+return ArchSpec::eRISCVSubType_riscv64;
+  default:
+return ArchSpec::eRISCVSubType_unknown;
+  }
+}
+
 static uint32_t subTypeFromElfHeader(const elf::ELFHeader &header) {
   if (header.e_machine == llvm::ELF::EM_MIPS)
 return mipsVariantFromElfFlags(header);
+  else if (header.e_machine == llvm::ELF::EM_RISCV)
+return riscvVariantFromElfFlags(header);
 
   return LLDB_INVALID_CPUTYPE;
 }
Index: lldb/include/lldb/Utility/ArchSpec.h
===
--- lldb/include/lldb/Utility/ArchSpec.h
+++ lldb/include/lldb/Utility/ArchSpec.h
@@ -99,6 +99,12 @@
 eRISCV_abi_d = 0x0020
   };
 
+  enum RISCVSubType {
+eRISCVSubType_unknown,
+eRISCVSubType_riscv32,
+eRISCVSubType_riscv64,
+  };
+
   enum Core {
 eCore_arm_generic,
 eCore_arm_armv4,


Index: lldb/test/Shell/ObjectFile/ELF/riscv64-arch.yaml
===
--- /dev/null
+++ lldb/test/Shell/ObjectFile/ELF/riscv64-arch.yaml
@@ -0,0 +1,11 @@
+# RUN: yaml2obj %s > %t
+# RUN: lldb-test object-file %t | FileCheck %s
+
+# CHECK: Architecture: riscv64--
+
+--- !ELF
+FileHeader:
+  Class:   ELFCLASS64
+  Data:ELFDATA2LSB
+  Type:ET_EXEC
+  Machine: EM_RISCV
Index: lldb/source/Utility/ArchSpec.cpp
===
--- lldb/source/Utility/ArchSpec.cpp
+++ lldb/source/Utility/ArchSpec.cpp
@@ -457,10 +457,10 @@
  0xu, 0xu}, // ARC
 {ArchSpec::eCore_avr, llvm::ELF::EM_AVR, LLDB_INVALID_CPUTYPE,
  0xu, 0xu}, // AVR
-{ArchSpec::eCore_riscv32, llvm::ELF::EM_RISCV, LLDB_INVALID_CPUTYPE,
- 0xu, 0x

[Lldb-commits] [PATCH] D86292: [LLDB][RISCV] Distinguish between riscv32 and riscv64 based on ELF class

[Luís Marques via Phabricator via lldb-commits]

luismarques updated this revision to Diff 286994.
luismarques added a comment.

Add riscv32 test.


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Files:
  lldb/include/lldb/Utility/ArchSpec.h
  lldb/source/Plugins/ObjectFile/ELF/ObjectFileELF.cpp
  lldb/source/Utility/ArchSpec.cpp
  lldb/test/Shell/ObjectFile/ELF/riscv32-arch.yaml
  lldb/test/Shell/ObjectFile/ELF/riscv64-arch.yaml


Index: lldb/test/Shell/ObjectFile/ELF/riscv64-arch.yaml
===
--- /dev/null
+++ lldb/test/Shell/ObjectFile/ELF/riscv64-arch.yaml
@@ -0,0 +1,11 @@
+# RUN: yaml2obj %s > %t
+# RUN: lldb-test object-file %t | FileCheck %s
+
+# CHECK: Architecture: riscv64--
+
+--- !ELF
+FileHeader:
+  Class:   ELFCLASS64
+  Data:ELFDATA2LSB
+  Type:ET_EXEC
+  Machine: EM_RISCV
Index: lldb/test/Shell/ObjectFile/ELF/riscv32-arch.yaml
===
--- /dev/null
+++ lldb/test/Shell/ObjectFile/ELF/riscv32-arch.yaml
@@ -0,0 +1,11 @@
+# RUN: yaml2obj %s > %t
+# RUN: lldb-test object-file %t | FileCheck %s
+
+# CHECK: Architecture: riscv32--
+
+--- !ELF
+FileHeader:
+  Class:   ELFCLASS32
+  Data:ELFDATA2LSB
+  Type:ET_EXEC
+  Machine: EM_RISCV
Index: lldb/source/Utility/ArchSpec.cpp
===
--- lldb/source/Utility/ArchSpec.cpp
+++ lldb/source/Utility/ArchSpec.cpp
@@ -457,10 +457,10 @@
  0xu, 0xu}, // ARC
 {ArchSpec::eCore_avr, llvm::ELF::EM_AVR, LLDB_INVALID_CPUTYPE,
  0xu, 0xu}, // AVR
-{ArchSpec::eCore_riscv32, llvm::ELF::EM_RISCV, LLDB_INVALID_CPUTYPE,
- 0xu, 0xu}, // riscv32
-{ArchSpec::eCore_riscv64, llvm::ELF::EM_RISCV, LLDB_INVALID_CPUTYPE,
- 0xu, 0xu}, // riscv64
+{ArchSpec::eCore_riscv32, llvm::ELF::EM_RISCV,
+ ArchSpec::eRISCVSubType_riscv32, 0xu, 0xu}, // riscv32
+{ArchSpec::eCore_riscv64, llvm::ELF::EM_RISCV,
+ ArchSpec::eRISCVSubType_riscv64, 0xu, 0xu}, // riscv64
 };
 
 static const ArchDefinition g_elf_arch_def = {
Index: lldb/source/Plugins/ObjectFile/ELF/ObjectFileELF.cpp
===
--- lldb/source/Plugins/ObjectFile/ELF/ObjectFileELF.cpp
+++ lldb/source/Plugins/ObjectFile/ELF/ObjectFileELF.cpp
@@ -296,9 +296,23 @@
   return arch_variant;
 }
 
+static uint32_t riscvVariantFromElfFlags(const elf::ELFHeader &header) {
+  uint32_t fileclass = header.e_ident[EI_CLASS];
+  switch (fileclass) {
+  case llvm::ELF::ELFCLASS32:
+return ArchSpec::eRISCVSubType_riscv32;
+  case llvm::ELF::ELFCLASS64:
+return ArchSpec::eRISCVSubType_riscv64;
+  default:
+return ArchSpec::eRISCVSubType_unknown;
+  }
+}
+
 static uint32_t subTypeFromElfHeader(const elf::ELFHeader &header) {
   if (header.e_machine == llvm::ELF::EM_MIPS)
 return mipsVariantFromElfFlags(header);
+  else if (header.e_machine == llvm::ELF::EM_RISCV)
+return riscvVariantFromElfFlags(header);
 
   return LLDB_INVALID_CPUTYPE;
 }
Index: lldb/include/lldb/Utility/ArchSpec.h
===
--- lldb/include/lldb/Utility/ArchSpec.h
+++ lldb/include/lldb/Utility/ArchSpec.h
@@ -99,6 +99,12 @@
 eRISCV_abi_d = 0x0020
   };
 
+  enum RISCVSubType {
+eRISCVSubType_unknown,
+eRISCVSubType_riscv32,
+eRISCVSubType_riscv64,
+  };
+
   enum Core {
 eCore_arm_generic,
 eCore_arm_armv4,


Index: lldb/test/Shell/ObjectFile/ELF/riscv64-arch.yaml
===
--- /dev/null
+++ lldb/test/Shell/ObjectFile/ELF/riscv64-arch.yaml
@@ -0,0 +1,11 @@
+# RUN: yaml2obj %s > %t
+# RUN: lldb-test object-file %t | FileCheck %s
+
+# CHECK: Architecture: riscv64--
+
+--- !ELF
+FileHeader:
+  Class:   ELFCLASS64
+  Data:ELFDATA2LSB
+  Type:ET_EXEC
+  Machine: EM_RISCV
Index: lldb/test/Shell/ObjectFile/ELF/riscv32-arch.yaml
===
--- /dev/null
+++ lldb/test/Shell/ObjectFile/ELF/riscv32-arch.yaml
@@ -0,0 +1,11 @@
+# RUN: yaml2obj %s > %t
+# RUN: lldb-test object-file %t | FileCheck %s
+
+# CHECK: Architecture: riscv32--
+
+--- !ELF
+FileHeader:
+  Class:   ELFCLASS32
+  Data:ELFDATA2LSB
+  Type:ET_EXEC
+  Machine: EM_RISCV
Index: lldb/source/Utility/ArchSpec.cpp
===
--- lldb/source/Utility/ArchSpec.cpp
+++ lldb/source/Utility/ArchSpec.cpp
@@ -457,10 +457,10 @@
  0xu, 0xu}, // ARC
 {ArchSpec::eCore_avr, llvm::ELF::EM_AVR, LLDB_INVALID_CPUTYPE,
  0xu, 0xu}, // AVR
-{ArchSpec::eCore_riscv32, llv

[Lldb-commits] [PATCH] D86292: [LLDB][RISCV] Distinguish between riscv32 and riscv64 based on ELF class

[Luís Marques via Phabricator via lldb-commits]

luismarques added a comment.

In D86292#2237143 , @jrtc27 wrote:

> Not so silly; gdb (well, the names are inherited from bfd) has `set 
> architecture riscv:rv32`/`set architecture riscv:rv64` :)

Ha! We're in good company then. Thanks for sharing, Jessica.


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[Lldb-commits] [PATCH] D62732: [RISCV] Add SystemV ABI

[Luís Marques via Phabricator via lldb-commits]

luismarques updated this revision to Diff 289696.
luismarques added a comment.

- Fix list of callee saved registers;
- Fix typo;
- Fix trivial clang-format issue.


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Files:
  lldb/include/lldb/Utility/ArchSpec.h
  lldb/source/Plugins/ABI/CMakeLists.txt
  lldb/source/Plugins/ABI/RISCV/ABISysV_riscv.cpp
  lldb/source/Plugins/ABI/RISCV/ABISysV_riscv.h
  lldb/source/Plugins/ABI/RISCV/CMakeLists.txt
  lldb/source/Plugins/Disassembler/LLVMC/DisassemblerLLVMC.cpp
  lldb/source/Plugins/ObjectFile/ELF/ObjectFileELF.cpp
  lldb/source/Target/Platform.cpp
  lldb/source/Utility/ArchSpec.cpp

Index: lldb/source/Utility/ArchSpec.cpp
===
--- lldb/source/Utility/ArchSpec.cpp
+++ lldb/source/Utility/ArchSpec.cpp
@@ -212,6 +212,11 @@
 {eByteOrderLittle, 4, 4, 4, llvm::Triple::hexagon,
  ArchSpec::eCore_hexagon_hexagonv5, "hexagonv5"},
 
+{eByteOrderLittle, 4, 2, 4, llvm::Triple::riscv32, ArchSpec::eCore_riscv32,
+ "riscv32"},
+{eByteOrderLittle, 8, 2, 4, llvm::Triple::riscv64, ArchSpec::eCore_riscv64,
+ "riscv64"},
+
 {eByteOrderLittle, 4, 4, 4, llvm::Triple::UnknownArch,
  ArchSpec::eCore_uknownMach32, "unknown-mach-32"},
 {eByteOrderLittle, 8, 4, 4, llvm::Triple::UnknownArch,
@@ -452,6 +457,10 @@
  0xu, 0xu}, // ARC
 {ArchSpec::eCore_avr, llvm::ELF::EM_AVR, LLDB_INVALID_CPUTYPE,
  0xu, 0xu}, // AVR
+{ArchSpec::eCore_riscv32, llvm::ELF::EM_RISCV, LLDB_INVALID_CPUTYPE,
+ 0xu, 0xu}, // riscv32
+{ArchSpec::eCore_riscv64, llvm::ELF::EM_RISCV, LLDB_INVALID_CPUTYPE,
+ 0xu, 0xu}, // riscv64
 };
 
 static const ArchDefinition g_elf_arch_def = {
Index: lldb/source/Target/Platform.cpp
===
--- lldb/source/Target/Platform.cpp
+++ lldb/source/Target/Platform.cpp
@@ -1967,6 +1967,20 @@
 trap_opcode_size = sizeof(g_i386_opcode);
   } break;
 
+  case llvm::Triple::riscv32:
+  case llvm::Triple::riscv64: {
+static const uint8_t g_riscv_c_opcode[] = {0x02, 0x90}; // c_ebreak
+static const uint8_t g_riscv_opcode[] = {0x73, 0x00, 0x10, 0x00}; // ebreak
+if (arch.GetFlags() & ArchSpec::eRISCV_arch_c) {
+  trap_opcode = g_riscv_c_opcode;
+  trap_opcode_size = sizeof(g_riscv_c_opcode);
+} else {
+  trap_opcode = g_riscv_opcode;
+  trap_opcode_size = sizeof(g_riscv_opcode);
+}
+break;
+  }
+
   default:
 return 0;
   }
Index: lldb/source/Plugins/ObjectFile/ELF/ObjectFileELF.cpp
===
--- lldb/source/Plugins/ObjectFile/ELF/ObjectFileELF.cpp
+++ lldb/source/Plugins/ObjectFile/ELF/ObjectFileELF.cpp
@@ -1364,6 +1364,18 @@
   arch_spec.SetFlags(ArchSpec::eARM_abi_hard_float);
   }
 
+  if (arch_spec.GetMachine() == llvm::Triple::riscv32 ||
+  arch_spec.GetMachine() == llvm::Triple::riscv64) {
+if (header.e_flags & llvm::ELF::EF_RISCV_RVC)
+  arch_spec.SetFlags(ArchSpec::eRISCV_arch_c);
+if ((header.e_flags & llvm::ELF::EF_RISCV_FLOAT_ABI) ==
+llvm::ELF::EF_RISCV_FLOAT_ABI_SINGLE)
+  arch_spec.SetFlags(ArchSpec::eRISCV_abi_f);
+if ((header.e_flags & llvm::ELF::EF_RISCV_FLOAT_ABI) ==
+llvm::ELF::EF_RISCV_FLOAT_ABI_DOUBLE)
+  arch_spec.SetFlags(ArchSpec::eRISCV_abi_d);
+  }
+
   // If there are no section headers we are done.
   if (header.e_shnum == 0)
 return 0;
Index: lldb/source/Plugins/Disassembler/LLVMC/DisassemblerLLVMC.cpp
===
--- lldb/source/Plugins/Disassembler/LLVMC/DisassemblerLLVMC.cpp
+++ lldb/source/Plugins/Disassembler/LLVMC/DisassemblerLLVMC.cpp
@@ -1149,6 +1149,11 @@
 cpu = "apple-latest";
   }
 
+  // For RISC-V, enable all standard extensions so these can be disassembled.
+  if (triple.getArch() == llvm::Triple::riscv32 ||
+  triple.getArch() == llvm::Triple::riscv64)
+features_str += "+a,+c,+d,+f,+m";
+
   // We use m_disasm_up.get() to tell whether we are valid or not, so if this
   // isn't good for some reason, we won't be valid and FindPlugin will fail and
   // we won't get used.
Index: lldb/source/Plugins/ABI/RISCV/CMakeLists.txt
===
--- /dev/null
+++ lldb/source/Plugins/ABI/RISCV/CMakeLists.txt
@@ -0,0 +1,10 @@
+add_lldb_library(lldbPluginABISysV_riscv PLUGIN
+  ABISysV_riscv.cpp
+
+  LINK_LIBS
+lldbCore
+lldbSymbol
+lldbTarget
+  LINK_COMPONENTS
+Support
+  )
Index: lldb/source/Plugins/ABI/RISCV/ABISysV_riscv.h
===
--- /dev/null
+++ lldb/source/Plugins/ABI/RISCV/ABISysV_riscv.h
@@ -0,0 +1,116 @@
+//===-- ABISysV_riscv.h -*- C

[Lldb-commits] [PATCH] D62732: [RISCV] Add SystemV ABI

[Luís Marques via Phabricator via lldb-commits]

luismarques added a comment.

@labath @jrtc27 @clayborg Now that we have at least 3 open-source debug servers 
that we can use to test this with (OpenOCD, QEMU gdbstub, gdbserver) perhaps 
this can be merged? I had very good results using this patch with OpenOCD. This 
patch doesn't include automated tests, but I'm not sure what tests would be 
required for this patch, or that it makes sense to require them at this point. 
I'll be doing more work for LLDB RISC-V support, and I'll provide tests for 
specific fixes going forward.


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[Lldb-commits] [PATCH] D62732: [RISCV] Add SystemV ABI

[Luís Marques via Phabricator via lldb-commits]

luismarques commandeered this revision.
luismarques added a reviewer: simoncook.
luismarques added a comment.

Commandeering the patch, as discussed in the last RISC-V sync-up call. I'll 
update it with only minor changes; further development can be done in follow-up 
patches.


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[Lldb-commits] [PATCH] D62732: [RISCV] Add SystemV ABI

[Luís Marques via Phabricator via lldb-commits]

luismarques added a comment.

In D62732#2286332 , @wallace wrote:

> @luismarques , what's the recommended gdb-server implementation you recommend 
> for me to try this on a riscv machine?

I compiled mine from the mainline binutils-gdb git repository (running on 
Fedora riscv64). But I suggest that you used OpenOCD instead, as I think that 
RISC-V gdbserver had some issues. If I recall correctly, gdbserver wouldn't 
return from the `c` command even if it hit a breakpoint. GDB was using `vCont` 
instead so it didn't run into that problem. Anyway, that's in my TODO list to 
better reduce the issue and report bugs/send patches, but just to let you know.


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[Lldb-commits] [PATCH] D62732: [RISCV] Add SystemV ABI

[Luís Marques via Phabricator via lldb-commits]

luismarques added a comment.

In D62732#2288013 , @JDevlieghere 
wrote:

> Sounds reasonable to me. Maybe it's still to early for that but have you 
> tried running (part of) the test suite under QEMU yet? It should give you a 
> pretty good idea of the state of things and gives you a bunch of test 
> coverage for free. You'll probably want to consider setting up a bot for that 
> down the road anyway.

I haven't tried that yet. When I did try to build LLVM with LLDB support under 
a QEMU VM (Fedora RISC-V) it failed because 
`CreateHostNativeRegisterContextLinux` didn't yet have a RISC-V implementation. 
I imagine that it might be possible to run part of the tests without solving 
that issue, but I added that to my TODO list anyway. I'll be able to devote 
more time to LLDB work around the beginning of October.


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[Lldb-commits] [PATCH] D86292: [LLDB][RISCV] Add RISC-V ArchSpec and rv32/rv64 variant detection

[Luís Marques via Phabricator via lldb-commits]

luismarques updated this revision to Diff 302190.
luismarques retitled this revision from "[LLDB][RISCV] Distinguish between 
riscv32 and riscv64 based on ELF class" to "[LLDB][RISCV] Add RISC-V ArchSpec 
and rv32/rv64 variant detection".
luismarques edited the summary of this revision.
luismarques added a reviewer: labath.
luismarques added a subscriber: labath.
luismarques added a comment.

Moved some of the ArchSpec/core bits from D62732 
 to here, per @labath's suggestion.


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Files:
  lldb/include/lldb/Utility/ArchSpec.h
  lldb/source/Plugins/ObjectFile/ELF/ObjectFileELF.cpp
  lldb/source/Utility/ArchSpec.cpp
  lldb/test/Shell/ObjectFile/ELF/riscv32-arch.yaml
  lldb/test/Shell/ObjectFile/ELF/riscv64-arch.yaml

Index: lldb/test/Shell/ObjectFile/ELF/riscv64-arch.yaml
===
--- /dev/null
+++ lldb/test/Shell/ObjectFile/ELF/riscv64-arch.yaml
@@ -0,0 +1,11 @@
+# RUN: yaml2obj %s > %t
+# RUN: lldb-test object-file %t | FileCheck %s
+
+# CHECK: Architecture: riscv64--
+
+--- !ELF
+FileHeader:
+  Class:   ELFCLASS64
+  Data:ELFDATA2LSB
+  Type:ET_EXEC
+  Machine: EM_RISCV
Index: lldb/test/Shell/ObjectFile/ELF/riscv32-arch.yaml
===
--- /dev/null
+++ lldb/test/Shell/ObjectFile/ELF/riscv32-arch.yaml
@@ -0,0 +1,11 @@
+# RUN: yaml2obj %s > %t
+# RUN: lldb-test object-file %t | FileCheck %s
+
+# CHECK: Architecture: riscv32--
+
+--- !ELF
+FileHeader:
+  Class:   ELFCLASS32
+  Data:ELFDATA2LSB
+  Type:ET_EXEC
+  Machine: EM_RISCV
Index: lldb/source/Utility/ArchSpec.cpp
===
--- lldb/source/Utility/ArchSpec.cpp
+++ lldb/source/Utility/ArchSpec.cpp
@@ -212,6 +212,11 @@
 {eByteOrderLittle, 4, 4, 4, llvm::Triple::hexagon,
  ArchSpec::eCore_hexagon_hexagonv5, "hexagonv5"},
 
+{eByteOrderLittle, 4, 2, 4, llvm::Triple::riscv32,
+ ArchSpec::eCore_riscv32, "riscv32"},
+{eByteOrderLittle, 8, 2, 4, llvm::Triple::riscv64,
+ ArchSpec::eCore_riscv64, "riscv64"},
+
 {eByteOrderLittle, 4, 4, 4, llvm::Triple::UnknownArch,
  ArchSpec::eCore_uknownMach32, "unknown-mach-32"},
 {eByteOrderLittle, 8, 4, 4, llvm::Triple::UnknownArch,
@@ -452,6 +457,10 @@
  0xu, 0xu}, // ARC
 {ArchSpec::eCore_avr, llvm::ELF::EM_AVR, LLDB_INVALID_CPUTYPE,
  0xu, 0xu}, // AVR
+{ArchSpec::eCore_riscv32, llvm::ELF::EM_RISCV,
+ ArchSpec::eRISCVSubType_riscv32, 0xu, 0xu}, // riscv32
+{ArchSpec::eCore_riscv64, llvm::ELF::EM_RISCV,
+ ArchSpec::eRISCVSubType_riscv64, 0xu, 0xu}, // riscv64
 };
 
 static const ArchDefinition g_elf_arch_def = {
Index: lldb/source/Plugins/ObjectFile/ELF/ObjectFileELF.cpp
===
--- lldb/source/Plugins/ObjectFile/ELF/ObjectFileELF.cpp
+++ lldb/source/Plugins/ObjectFile/ELF/ObjectFileELF.cpp
@@ -296,9 +296,23 @@
   return arch_variant;
 }
 
+static uint32_t riscvVariantFromElfFlags(const elf::ELFHeader &header) {
+  uint32_t fileclass = header.e_ident[EI_CLASS];
+  switch (fileclass) {
+  case llvm::ELF::ELFCLASS32:
+return ArchSpec::eRISCVSubType_riscv32;
+  case llvm::ELF::ELFCLASS64:
+return ArchSpec::eRISCVSubType_riscv64;
+  default:
+return ArchSpec::eRISCVSubType_unknown;
+  }
+}
+
 static uint32_t subTypeFromElfHeader(const elf::ELFHeader &header) {
   if (header.e_machine == llvm::ELF::EM_MIPS)
 return mipsVariantFromElfFlags(header);
+  else if (header.e_machine == llvm::ELF::EM_RISCV)
+return riscvVariantFromElfFlags(header);
 
   return LLDB_INVALID_CPUTYPE;
 }
Index: lldb/include/lldb/Utility/ArchSpec.h
===
--- lldb/include/lldb/Utility/ArchSpec.h
+++ lldb/include/lldb/Utility/ArchSpec.h
@@ -99,6 +99,12 @@
 eRISCV_abi_d = 0x0020
   };
 
+  enum RISCVSubType {
+eRISCVSubType_unknown,
+eRISCVSubType_riscv32,
+eRISCVSubType_riscv64,
+  };
+
   enum Core {
 eCore_arm_generic,
 eCore_arm_armv4,
@@ -191,6 +197,9 @@
 eCore_hexagon_hexagonv4,
 eCore_hexagon_hexagonv5,
 
+eCore_riscv32,
+eCore_riscv64,
+
 eCore_uknownMach32,
 eCore_uknownMach64,
 
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[Lldb-commits] [PATCH] D62732: [RISCV] Add SystemV ABI

[Luís Marques via Phabricator via lldb-commits]

luismarques updated this revision to Diff 302182.
luismarques added a comment.
Herald added subscribers: frasercrmck, NickHung.

- Use MCBasedABI
- Remove ArchSpec core bits, to be moved to D86292 



Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D62732/new/

https://reviews.llvm.org/D62732

Files:
  lldb/include/lldb/Utility/ArchSpec.h
  lldb/source/Plugins/ABI/CMakeLists.txt
  lldb/source/Plugins/ABI/RISCV/ABISysV_riscv.cpp
  lldb/source/Plugins/ABI/RISCV/ABISysV_riscv.h
  lldb/source/Plugins/ABI/RISCV/CMakeLists.txt
  lldb/source/Plugins/Disassembler/LLVMC/DisassemblerLLVMC.cpp
  lldb/source/Plugins/ObjectFile/ELF/ObjectFileELF.cpp
  lldb/source/Target/Platform.cpp

Index: lldb/source/Target/Platform.cpp
===
--- lldb/source/Target/Platform.cpp
+++ lldb/source/Target/Platform.cpp
@@ -1973,6 +1973,20 @@
 trap_opcode_size = sizeof(g_i386_opcode);
   } break;
 
+  case llvm::Triple::riscv32:
+  case llvm::Triple::riscv64: {
+static const uint8_t g_riscv_c_opcode[] = {0x02, 0x90}; // c_ebreak
+static const uint8_t g_riscv_opcode[] = {0x73, 0x00, 0x10, 0x00}; // ebreak
+if (arch.GetFlags() & ArchSpec::eRISCV_arch_c) {
+  trap_opcode = g_riscv_c_opcode;
+  trap_opcode_size = sizeof(g_riscv_c_opcode);
+} else {
+  trap_opcode = g_riscv_opcode;
+  trap_opcode_size = sizeof(g_riscv_opcode);
+}
+break;
+  }
+
   default:
 return 0;
   }
Index: lldb/source/Plugins/ObjectFile/ELF/ObjectFileELF.cpp
===
--- lldb/source/Plugins/ObjectFile/ELF/ObjectFileELF.cpp
+++ lldb/source/Plugins/ObjectFile/ELF/ObjectFileELF.cpp
@@ -1364,6 +1364,18 @@
   arch_spec.SetFlags(ArchSpec::eARM_abi_hard_float);
   }
 
+  if (arch_spec.GetMachine() == llvm::Triple::riscv32 ||
+  arch_spec.GetMachine() == llvm::Triple::riscv64) {
+if (header.e_flags & llvm::ELF::EF_RISCV_RVC)
+  arch_spec.SetFlags(ArchSpec::eRISCV_arch_c);
+if ((header.e_flags & llvm::ELF::EF_RISCV_FLOAT_ABI) ==
+llvm::ELF::EF_RISCV_FLOAT_ABI_SINGLE)
+  arch_spec.SetFlags(ArchSpec::eRISCV_abi_f);
+if ((header.e_flags & llvm::ELF::EF_RISCV_FLOAT_ABI) ==
+llvm::ELF::EF_RISCV_FLOAT_ABI_DOUBLE)
+  arch_spec.SetFlags(ArchSpec::eRISCV_abi_d);
+  }
+
   // If there are no section headers we are done.
   if (header.e_shnum == 0)
 return 0;
Index: lldb/source/Plugins/Disassembler/LLVMC/DisassemblerLLVMC.cpp
===
--- lldb/source/Plugins/Disassembler/LLVMC/DisassemblerLLVMC.cpp
+++ lldb/source/Plugins/Disassembler/LLVMC/DisassemblerLLVMC.cpp
@@ -1149,6 +1149,11 @@
 cpu = "apple-latest";
   }
 
+  // For RISC-V, enable all standard extensions so these can be disassembled.
+  if (triple.getArch() == llvm::Triple::riscv32 ||
+  triple.getArch() == llvm::Triple::riscv64)
+features_str += "+a,+c,+d,+f,+m";
+
   // We use m_disasm_up.get() to tell whether we are valid or not, so if this
   // isn't good for some reason, we won't be valid and FindPlugin will fail and
   // we won't get used.
Index: lldb/source/Plugins/ABI/RISCV/CMakeLists.txt
===
--- /dev/null
+++ lldb/source/Plugins/ABI/RISCV/CMakeLists.txt
@@ -0,0 +1,10 @@
+add_lldb_library(lldbPluginABISysV_riscv PLUGIN
+  ABISysV_riscv.cpp
+
+  LINK_LIBS
+lldbCore
+lldbSymbol
+lldbTarget
+  LINK_COMPONENTS
+Support
+  )
Index: lldb/source/Plugins/ABI/RISCV/ABISysV_riscv.h
===
--- /dev/null
+++ lldb/source/Plugins/ABI/RISCV/ABISysV_riscv.h
@@ -0,0 +1,116 @@
+//===-- ABISysV_riscv.h -*- C++ -*-===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===--===//
+
+#ifndef liblldb_ABISysV_riscv_h_
+#define liblldb_ABISysV_riscv_h_
+
+#include "lldb/Target/ABI.h"
+#include "lldb/lldb-private.h"
+
+class ABISysV_riscv : public lldb_private::MCBasedABI {
+  bool isRV64;
+
+public:
+  ~ABISysV_riscv() override = default;
+
+  size_t GetRedZoneSize() const override { return 0; }
+
+  bool PrepareTrivialCall(lldb_private::Thread &thread, lldb::addr_t sp,
+  lldb::addr_t functionAddress,
+  lldb::addr_t returnAddress,
+  llvm::ArrayRef args) const override {
+// TODO: Implement
+return false;
+  }
+
+  bool GetArgumentValues(lldb_private::Thread &thread,
+ lldb_private::ValueList &values) const override {
+// TODO: Implement
+return false;
+  }
+
+  lldb_p

[Lldb-commits] [PATCH] D62732: [RISCV] Add SystemV ABI

[Luís Marques via Phabricator via lldb-commits]

luismarques added a comment.

In D62732#2306055 , @labath wrote:

> I'm not sure what's the state of risc-v hardware these days and how much 
> resources do you have available, but if it's at all possible, I'd definitely 
> recommend adding the lldb-server bits for risc-v and adding a builtbot for 
> testing this configuration.

That's on my TODO list. Still, if that would take, say, ~2 months, perhaps it 
would still make sense to merge this and D86292 
 before then? Please let me know if there's 
anything else that should be addressed in these patches themselves.


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[Lldb-commits] [PATCH] D86292: [LLDB][RISCV] Add RISC-V ArchSpec and rv32/rv64 variant detection

[Luís Marques via Phabricator via lldb-commits]

luismarques updated this revision to Diff 307360.
luismarques added a comment.

Merge tests, using `--docnum`.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D86292/new/

https://reviews.llvm.org/D86292

Files:
  lldb/include/lldb/Utility/ArchSpec.h
  lldb/source/Plugins/ObjectFile/ELF/ObjectFileELF.cpp
  lldb/source/Utility/ArchSpec.cpp
  lldb/test/Shell/ObjectFile/ELF/riscv-arch.yaml

Index: lldb/test/Shell/ObjectFile/ELF/riscv-arch.yaml
===
--- /dev/null
+++ lldb/test/Shell/ObjectFile/ELF/riscv-arch.yaml
@@ -0,0 +1,24 @@
+# RUN: yaml2obj --docnum=1 %s > %t32
+# RUN: yaml2obj --docnum=2 %s > %t64
+# RUN: lldb-test object-file %t32 | FileCheck --check-prefix=CHECK-RV32 %s
+# RUN: lldb-test object-file %t64 | FileCheck --check-prefix=CHECK-RV64 %s
+
+# CHECK-RV32: Architecture: riscv32--
+
+--- !ELF
+FileHeader:
+  Class:   ELFCLASS32
+  Data:ELFDATA2LSB
+  Type:ET_EXEC
+  Machine: EM_RISCV
+...
+
+# CHECK-RV64: Architecture: riscv64--
+
+--- !ELF
+FileHeader:
+  Class:   ELFCLASS64
+  Data:ELFDATA2LSB
+  Type:ET_EXEC
+  Machine: EM_RISCV
+...
Index: lldb/source/Utility/ArchSpec.cpp
===
--- lldb/source/Utility/ArchSpec.cpp
+++ lldb/source/Utility/ArchSpec.cpp
@@ -212,6 +212,11 @@
 {eByteOrderLittle, 4, 4, 4, llvm::Triple::hexagon,
  ArchSpec::eCore_hexagon_hexagonv5, "hexagonv5"},
 
+{eByteOrderLittle, 4, 2, 4, llvm::Triple::riscv32, ArchSpec::eCore_riscv32,
+ "riscv32"},
+{eByteOrderLittle, 8, 2, 4, llvm::Triple::riscv64, ArchSpec::eCore_riscv64,
+ "riscv64"},
+
 {eByteOrderLittle, 4, 4, 4, llvm::Triple::UnknownArch,
  ArchSpec::eCore_uknownMach32, "unknown-mach-32"},
 {eByteOrderLittle, 8, 4, 4, llvm::Triple::UnknownArch,
@@ -452,6 +457,10 @@
  0xu, 0xu}, // ARC
 {ArchSpec::eCore_avr, llvm::ELF::EM_AVR, LLDB_INVALID_CPUTYPE,
  0xu, 0xu}, // AVR
+{ArchSpec::eCore_riscv32, llvm::ELF::EM_RISCV,
+ ArchSpec::eRISCVSubType_riscv32, 0xu, 0xu}, // riscv32
+{ArchSpec::eCore_riscv64, llvm::ELF::EM_RISCV,
+ ArchSpec::eRISCVSubType_riscv64, 0xu, 0xu}, // riscv64
 };
 
 static const ArchDefinition g_elf_arch_def = {
Index: lldb/source/Plugins/ObjectFile/ELF/ObjectFileELF.cpp
===
--- lldb/source/Plugins/ObjectFile/ELF/ObjectFileELF.cpp
+++ lldb/source/Plugins/ObjectFile/ELF/ObjectFileELF.cpp
@@ -296,9 +296,23 @@
   return arch_variant;
 }
 
+static uint32_t riscvVariantFromElfFlags(const elf::ELFHeader &header) {
+  uint32_t fileclass = header.e_ident[EI_CLASS];
+  switch (fileclass) {
+  case llvm::ELF::ELFCLASS32:
+return ArchSpec::eRISCVSubType_riscv32;
+  case llvm::ELF::ELFCLASS64:
+return ArchSpec::eRISCVSubType_riscv64;
+  default:
+return ArchSpec::eRISCVSubType_unknown;
+  }
+}
+
 static uint32_t subTypeFromElfHeader(const elf::ELFHeader &header) {
   if (header.e_machine == llvm::ELF::EM_MIPS)
 return mipsVariantFromElfFlags(header);
+  else if (header.e_machine == llvm::ELF::EM_RISCV)
+return riscvVariantFromElfFlags(header);
 
   return LLDB_INVALID_CPUTYPE;
 }
Index: lldb/include/lldb/Utility/ArchSpec.h
===
--- lldb/include/lldb/Utility/ArchSpec.h
+++ lldb/include/lldb/Utility/ArchSpec.h
@@ -99,6 +99,12 @@
 eRISCV_abi_d = 0x0020
   };
 
+  enum RISCVSubType {
+eRISCVSubType_unknown,
+eRISCVSubType_riscv32,
+eRISCVSubType_riscv64,
+  };
+
   enum Core {
 eCore_arm_generic,
 eCore_arm_armv4,
@@ -191,6 +197,9 @@
 eCore_hexagon_hexagonv4,
 eCore_hexagon_hexagonv5,
 
+eCore_riscv32,
+eCore_riscv64,
+
 eCore_uknownMach32,
 eCore_uknownMach64,
 
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[Lldb-commits] [PATCH] D86292: [LLDB][RISCV] Add RISC-V ArchSpec and rv32/rv64 variant detection

[Luís Marques via Phabricator via lldb-commits]

This revision was landed with ongoing or failed builds.
This revision was automatically updated to reflect the committed changes.
Closed by commit rG15f597115068: [LLDB][RISCV] Add RISC-V ArchSpec and 
rv32/rv64 variant detection (authored by luismarques).

Changed prior to commit:
  https://reviews.llvm.org/D86292?vs=307360&id=315254#toc

Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D86292/new/

https://reviews.llvm.org/D86292

Files:
  lldb/include/lldb/Utility/ArchSpec.h
  lldb/source/Plugins/ObjectFile/ELF/ObjectFileELF.cpp
  lldb/source/Utility/ArchSpec.cpp
  lldb/test/Shell/ObjectFile/ELF/riscv-arch.yaml

Index: lldb/test/Shell/ObjectFile/ELF/riscv-arch.yaml
===
--- /dev/null
+++ lldb/test/Shell/ObjectFile/ELF/riscv-arch.yaml
@@ -0,0 +1,24 @@
+# RUN: yaml2obj --docnum=1 %s > %t32
+# RUN: yaml2obj --docnum=2 %s > %t64
+# RUN: lldb-test object-file %t32 | FileCheck --check-prefix=CHECK-RV32 %s
+# RUN: lldb-test object-file %t64 | FileCheck --check-prefix=CHECK-RV64 %s
+
+# CHECK-RV32: Architecture: riscv32--
+
+--- !ELF
+FileHeader:
+  Class:   ELFCLASS32
+  Data:ELFDATA2LSB
+  Type:ET_EXEC
+  Machine: EM_RISCV
+...
+
+# CHECK-RV64: Architecture: riscv64--
+
+--- !ELF
+FileHeader:
+  Class:   ELFCLASS64
+  Data:ELFDATA2LSB
+  Type:ET_EXEC
+  Machine: EM_RISCV
+...
Index: lldb/source/Utility/ArchSpec.cpp
===
--- lldb/source/Utility/ArchSpec.cpp
+++ lldb/source/Utility/ArchSpec.cpp
@@ -212,6 +212,11 @@
 {eByteOrderLittle, 4, 4, 4, llvm::Triple::hexagon,
  ArchSpec::eCore_hexagon_hexagonv5, "hexagonv5"},
 
+{eByteOrderLittle, 4, 2, 4, llvm::Triple::riscv32, ArchSpec::eCore_riscv32,
+ "riscv32"},
+{eByteOrderLittle, 8, 2, 4, llvm::Triple::riscv64, ArchSpec::eCore_riscv64,
+ "riscv64"},
+
 {eByteOrderLittle, 4, 4, 4, llvm::Triple::UnknownArch,
  ArchSpec::eCore_uknownMach32, "unknown-mach-32"},
 {eByteOrderLittle, 8, 4, 4, llvm::Triple::UnknownArch,
@@ -395,6 +400,10 @@
  0xu, 0xu}, // ARC
 {ArchSpec::eCore_avr, llvm::ELF::EM_AVR, LLDB_INVALID_CPUTYPE,
  0xu, 0xu}, // AVR
+{ArchSpec::eCore_riscv32, llvm::ELF::EM_RISCV,
+ ArchSpec::eRISCVSubType_riscv32, 0xu, 0xu}, // riscv32
+{ArchSpec::eCore_riscv64, llvm::ELF::EM_RISCV,
+ ArchSpec::eRISCVSubType_riscv64, 0xu, 0xu}, // riscv64
 };
 
 static const ArchDefinition g_elf_arch_def = {
Index: lldb/source/Plugins/ObjectFile/ELF/ObjectFileELF.cpp
===
--- lldb/source/Plugins/ObjectFile/ELF/ObjectFileELF.cpp
+++ lldb/source/Plugins/ObjectFile/ELF/ObjectFileELF.cpp
@@ -296,9 +296,23 @@
   return arch_variant;
 }
 
+static uint32_t riscvVariantFromElfFlags(const elf::ELFHeader &header) {
+  uint32_t fileclass = header.e_ident[EI_CLASS];
+  switch (fileclass) {
+  case llvm::ELF::ELFCLASS32:
+return ArchSpec::eRISCVSubType_riscv32;
+  case llvm::ELF::ELFCLASS64:
+return ArchSpec::eRISCVSubType_riscv64;
+  default:
+return ArchSpec::eRISCVSubType_unknown;
+  }
+}
+
 static uint32_t subTypeFromElfHeader(const elf::ELFHeader &header) {
   if (header.e_machine == llvm::ELF::EM_MIPS)
 return mipsVariantFromElfFlags(header);
+  else if (header.e_machine == llvm::ELF::EM_RISCV)
+return riscvVariantFromElfFlags(header);
 
   return LLDB_INVALID_CPUTYPE;
 }
Index: lldb/include/lldb/Utility/ArchSpec.h
===
--- lldb/include/lldb/Utility/ArchSpec.h
+++ lldb/include/lldb/Utility/ArchSpec.h
@@ -92,6 +92,12 @@
 eARM_abi_hard_float = 0x0400
   };
 
+  enum RISCVSubType {
+eRISCVSubType_unknown,
+eRISCVSubType_riscv32,
+eRISCVSubType_riscv64,
+  };
+
   enum Core {
 eCore_arm_generic,
 eCore_arm_armv4,
@@ -184,6 +190,9 @@
 eCore_hexagon_hexagonv4,
 eCore_hexagon_hexagonv5,
 
+eCore_riscv32,
+eCore_riscv64,
+
 eCore_uknownMach32,
 eCore_uknownMach64,
 
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