Re: [PATCH 11/11] k_clock:Remove the 32bit methods with timespec type
On Mon, Apr 20, 2015 at 01:57:39PM +0800, Baolin Wang wrote:
> @@ -911,18 +907,14 @@ retry:
> return -EINVAL;
>
> kc = clockid_to_kclock(timr->it_clock);
> - if (WARN_ON_ONCE(!kc || (!kc->timer_set && !kc->timer_set64))) {
> + if (WARN_ON_ONCE(!kc || !kc->timer_set64)) {
> error = -EINVAL;
> } else {
> - if (kc->timer_set64) {
> - new_spec64 = itimerspec_to_itimerspec64(new_spec);
> - error = kc->timer_set64(timr, flags, &new_spec64,
> - &old_spec64);
> - if (old_setting)
> - old_spec =
> itimerspec64_to_itimerspec(old_spec64);
> - } else {
> - error = kc->timer_set(timr, flags, &new_spec, rtn);
> - }
> + new_spec64 = itimerspec_to_itimerspec64(new_spec);
> + error = kc->timer_set64(timr, flags, &new_spec64,
> + &old_spec64);
This statement can fit on one line.
> + if (old_setting)
> + old_spec = itimerspec64_to_itimerspec(old_spec64);
> }
>
> unlock_timer(timr, flag);
> @@ -1057,14 +1045,13 @@ SYSCALL_DEFINE2(clock_gettime, const clockid_t,
> which_clock,
> if (!kc)
> return -EINVAL;
>
> - if (kc->clock_get64) {
> - error = kc->clock_get64(which_clock, &kernel_tp64);
> - kernel_tp = timespec64_to_timespec(kernel_tp64);
> - } else {
> - error = kc->clock_get(which_clock, &kernel_tp);
> - }
> + error = kc->clock_get64(which_clock, &kernel_tp64);
> + if (!error)
> + return error;
Wrong test, should be: if (error) ...
> +
> + kernel_tp = timespec64_to_timespec(kernel_tp64);
>
> - if (!error && copy_to_user(tp, &kernel_tp, sizeof (kernel_tp)))
The (!error && ...) was correct here!
> + if (copy_to_user(tp, &kernel_tp, sizeof (kernel_tp)))
> error = -EFAULT;
>
> return error;
You can simplify this like so:
return copy_to_user(tp, &kernel_tp, sizeof(kernel_tp)) ? -EFAULT : 0;
> @@ -1104,14 +1091,13 @@ SYSCALL_DEFINE2(clock_getres, const clockid_t,
> which_clock,
> if (!kc)
> return -EINVAL;
>
> - if (kc->clock_getres64) {
> - error = kc->clock_getres64(which_clock, &rtn_tp64);
> - rtn_tp = timespec64_to_timespec(rtn_tp64);
> - } else {
> - error = kc->clock_getres(which_clock, &rtn_tp);
> - }
> + error = kc->clock_getres64(which_clock, &rtn_tp64);
> + if (!error)
> + return error;
Also wrong.
> +
> + rtn_tp = timespec64_to_timespec(rtn_tp64);
>
> - if (!error && tp && copy_to_user(tp, &rtn_tp, sizeof (rtn_tp)))
> + if (tp && copy_to_user(tp, &rtn_tp, sizeof (rtn_tp)))
> error = -EFAULT;
>
> return error;
> --
> 1.7.9.5
>
Thanks,
Richard
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Re: [Y2038] [PATCH 04/11] posix timers:Introduce the 64bit methods with timespec64 type for k_clock structure
On Wed, Apr 22, 2015 at 10:45:23AM +0200, Thomas Gleixner wrote: > So we could save one translation step if we implement new syscalls > which have a scalar nsec interface instead of the timespec/timeval > cruft and let user space do the translation to whatever it wants. +1 > I personally would welcome such an interface as it makes user space > programming simpler. Just (re)arming a periodic nanosleep based on > absolute expiry time is horrible stupid today: Jup. > Thoughts? Current user space example: The linuxptp programs are doing ns64 to timespec conversions to call into the kernel, which then does timespec to ns64 to talk to the hardware. I would bet that most (all?) use cases are better served with 64 bit nanosecond system calls. Thanks, Richard ___ Linuxppc-dev mailing list Linuxppc-dev@lists.ozlabs.org https://lists.ozlabs.org/listinfo/linuxppc-dev
Re: [Y2038] [PATCH 04/11] posix timers:Introduce the 64bit methods with timespec64 type for k_clock structure
On Wed, Apr 22, 2015 at 03:50:45PM +0200, Arnd Bergmann wrote: > time, stime, gettimeofday, settimeofday, adjtimex, nanosleep, > getitimer, setitimer: > all deprecated => wontfix If adjtimex is deprecated, what will replace it? It is really important for ntp. Thanks, Richard ___ Linuxppc-dev mailing list Linuxppc-dev@lists.ozlabs.org https://lists.ozlabs.org/listinfo/linuxppc-dev
Re: [PATCH] powerpc/83xx: gianfar_ptp: select 1588 clock source through dts file
On Tue, Sep 24, 2013 at 11:39:57AM +0400, Aida Mynzhasova wrote: > Currently IEEE 1588 timer reference clock source is determined through > hard-coded value in gianfar_ptp driver. This patch allows to select ptp > clock source by means of device tree file node. > > For instance: > > fsl,cksel = <0>; > > for using external (TSEC_TMR_CLK input) high precision timer > reference clock. > > Other acceptable values: > > <1> : eTSEC system clock > <2> : eTSEC1 transmit clock > <3> : RTC clock input I think it would be useful to have this table in the binding document as well. Thanks, Richard ___ Linuxppc-dev mailing list Linuxppc-dev@lists.ozlabs.org https://lists.ozlabs.org/listinfo/linuxppc-dev
Re: [PATCH v2] powerpc/83xx: gianfar_ptp: select 1588 clock source through dts file
On Wed, Sep 25, 2013 at 11:24:23AM +0400, Aida Mynzhasova wrote: > Currently IEEE 1588 timer reference clock source is determined through > hard-coded value in gianfar_ptp driver. This patch allows to select ptp > clock source by means of device tree file node. Looks okay to me now. Acked-by: Richard Cochran ___ Linuxppc-dev mailing list Linuxppc-dev@lists.ozlabs.org https://lists.ozlabs.org/listinfo/linuxppc-dev
Re: [PATCH V3] tick/broadcast: Make movement of broadcast hrtimer robust against hotplug
On Wed, Jan 28, 2015 at 03:32:58PM +0530, Preeti U Murthy wrote: > Thomas ping. Would you be posting this patch? FYI, Thomas is temporarily out of action, in bed with the flu. Thanks, Richard ___ Linuxppc-dev mailing list Linuxppc-dev@lists.ozlabs.org https://lists.ozlabs.org/listinfo/linuxppc-dev
Re: [PATCH 09/10] dpaa_eth: add support for hardware timestamping
On Mon, Jun 04, 2018 at 03:08:36PM +0800, Yangbo Lu wrote:
> +if FSL_DPAA_ETH
> +config FSL_DPAA_ETH_TS
> + bool "DPAA hardware timestamping support"
> + select PTP_1588_CLOCK_QORIQ
> + default n
> + help
> + Enable DPAA hardware timestamping support.
> + This option is useful for applications to get
> + hardware time stamps on the Ethernet packets
> + using the SO_TIMESTAMPING API.
> +endif
You should drop this #ifdef. In general, if a MAC supports time
stamping and PHC, then the driver support should simply be compiled
in.
[ When time stamping incurs a large run time performance penalty to
non-PTP users, then it might make sense to have a Kconfig option to
disable it, but that doesn't appear to be the case here. ]
> @@ -1615,6 +1635,24 @@ static int dpaa_eth_refill_bpools(struct dpaa_priv
> *priv)
> skbh = (struct sk_buff **)phys_to_virt(addr);
> skb = *skbh;
>
> +#ifdef CONFIG_FSL_DPAA_ETH_TS
> + if (priv->tx_tstamp &&
> + skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP) {
This condition fits on one line easily.
> + struct skb_shared_hwtstamps shhwtstamps;
> + u64 ns;
Local variables belong at the top of the function.
> + memset(&shhwtstamps, 0, sizeof(shhwtstamps));
> +
> + if (!dpaa_get_tstamp_ns(priv->net_dev, &ns,
> + priv->mac_dev->port[TX],
> + (void *)skbh)) {
> + shhwtstamps.hwtstamp = ns_to_ktime(ns);
> + skb_tstamp_tx(skb, &shhwtstamps);
> + } else {
> + dev_warn(dev, "dpaa_get_tstamp_ns failed!\n");
> + }
> + }
> +#endif
> if (unlikely(qm_fd_get_format(fd) == qm_fd_sg)) {
> nr_frags = skb_shinfo(skb)->nr_frags;
> dma_unmap_single(dev, addr, qm_fd_get_offset(fd) +
> @@ -2086,6 +2124,14 @@ static int dpaa_start_xmit(struct sk_buff *skb, struct
> net_device *net_dev)
> if (unlikely(err < 0))
> goto skb_to_fd_failed;
>
> +#ifdef CONFIG_FSL_DPAA_ETH_TS
> + if (priv->tx_tstamp &&
> + skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP) {
One line please.
> + fd.cmd |= FM_FD_CMD_UPD;
> + skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS;
> + }
> +#endif
> +
> if (likely(dpaa_xmit(priv, percpu_stats, queue_mapping, &fd) == 0))
> return NETDEV_TX_OK;
>
Thanks,
Richard
Re: [PATCH 09/10] dpaa_eth: add support for hardware timestamping
On Tue, Jun 05, 2018 at 03:35:28AM +, Y.b. Lu wrote: > [Y.b. Lu] Actually these timestamping codes affected DPAA networking > performance in our previous performance test. > That's why we used ifdef for it. How much does time stamping hurt performance? If the time stamping is compiled in but not enabled at run time, does it still affect performace? Thanks, Richard
Re: [v3, 00/10] Support DPAA PTP clock and timestamping
On Thu, Jun 07, 2018 at 05:20:40PM +0800, Yangbo Lu wrote: > This patchset is to support DPAA FMAN PTP clock and HW timestamping. > It had been verified on both ARM platform and PPC platform. > - The patch #1 to patch #5 are to support DPAA FMAN 1588 timer in > ptp_qoriq driver. > - The patch #6 to patch #10 are to add HW timestamping support in > DPAA ethernet driver. Right now, net-next is closed for new stuff. You will have to post the series again after the merge window closes. You can check the status here: http://vger.kernel.org/~davem/net-next.html When you do re-post, you can add my: Acked-by: Richard Cochran
Re: [PATCH 3/3] ptp_qoriq: convert to use module parameters for initialization
On Mon, Jul 30, 2018 at 06:01:54PM +0800, Yangbo Lu wrote: > The ptp_qoriq driver initialized the 1588 timer with the > configurations provided by the properties of device tree > node. For example, > > fsl,tclk-period = <5>; > fsl,tmr-prsc= <2>; > fsl,tmr-add = <0xaaab>; > fsl,tmr-fiper1 = <5>; > fsl,tmr-fiper2 = <0>; > fsl,max-adj = <4>; > > These things actually were runtime configurations which > were not proper to be put into dts. That is debatable. While I agree that the dts isn't ideal for these, still it is the lesser of two or more evils. > This patch is to convert > to use module parameters for 1588 timer initialization, and > to support initial register values calculation. It is hard for me to understand how using module parameters improves the situation. > If the parameters are not provided, the driver will calculate > register values with a set of default parameters. With this > patch, those dts properties are no longer needed for new > platform to support 1588 timer, and many QorIQ DPAA platforms > (some P series and T series platforms of PowerPC, and some > LS series platforms of ARM64) could use this driver for their > fman ptp timer with default module parameters. However, this > patch didn't remove the dts method. Because there were still > many old platforms using the dts method. We need to clean up > their dts files, verify module parameters on them, and convert > them to the new method gradually in case of breaking any > function. In addition, like it or not, because the dts is an ABI, you must continue support of the dts values as a legacy option. Thanks, Richard
Re: [PATCH 3/3] ptp_qoriq: convert to use module parameters for initialization
On Wed, Aug 01, 2018 at 04:36:40AM +, Y.b. Lu wrote: > Could I add a function to calculate a set of default register values > to initialize ptp timer when dts method failed to get required > properties in driver? Yes, it would be ideal if the driver can pick correct values automatically. However, the frequency on the FIPER outputs can't be configured automatically, and we don't have an API for the user to choose this. > I think this will be useful. The ptp timer on new platforms (you may > see two dts patches in this patchset. Many platforms will be > affected.) will work without these dts properties. If user want > specific setting, they can set dts properties. Sure. Thanks, Richard
Re: [PATCH] gianfar: add missing include
On Tue, Apr 10, 2012 at 02:18:47PM +1000, Michael Neuling wrote: > This is because of a missing include file from: > 6663628 gianfar: Support the get_ts_info ethtool method. > > Signed-off-by: Michael Neuling I did a poor job testing the non-x86 stuff in this series. Thanks for the fix. Acked-by: Richard Cochran ___ Linuxppc-dev mailing list Linuxppc-dev@lists.ozlabs.org https://lists.ozlabs.org/listinfo/linuxppc-dev
Re: [PATCH 1/8] posix clocks: introduce a syscall for clock tuning.
On Thu, Sep 23, 2010 at 12:48:51PM -0700, john stultz wrote:
> On Thu, 2010-09-23 at 19:31 +0200, Richard Cochran wrote:
> > A new syscall is introduced that allows tuning of a POSIX clock. The
> > syscall is implemented for four architectures: arm, blackfin, powerpc,
> > and x86.
> >
> > The new syscall, clock_adjtime, takes two parameters, the clock ID,
> > and a pointer to a struct timex. The semantics of the timex struct
> > have been expanded by one additional mode flag, which allows an
> > absolute offset correction. When specificied, the clock offset is
> > immediately corrected by adding the given time value to the current
> > time value.
>
>
> So I'd still split this patch up a little bit more.
>
> 1) Patch that implements the ADJ_SETOFFSET (*and its implementation*)
> in do_adjtimex.
>
> 2) Patch that adds the new syscall and clock_id multiplexing.
>
> 3) Patches that wire it up to the rest of the architectures (there's
> still a bunch missing here).
I was not sure what the policy is about adding syscalls. Is it the
syscall author's responsibility to add it into every arch?
The last time (see a2e2725541fad7) the commit only added half of some
archs, and ignored others. In my patch, the syscall *really* works on
the archs that are present in the patch.
(Actually, I did not test blackfin, since I don't have one, but I
included it since I know they have a PTP hardware clock.)
> > +static inline int common_clock_adj(const clockid_t which_clock, struct
> > timex *t)
> > +{
> > + if (CLOCK_REALTIME == which_clock)
> > + return do_adjtimex(t);
> > + else
> > + return -EOPNOTSUPP;
> > +}
>
>
> Would it make sense to point to the do_adjtimex() in the k_clock
> definition for CLOCK_REALTIME rather then conditionalizing it here?
But what about CLOCK_MONOTONIC_RAW, for example?
Does it make sense to allow it to be adjusted?
Thanks,
Richard
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Re: [PATCH 1/8] posix clocks: introduce a syscall for clock tuning.
On Fri, Sep 24, 2010 at 08:03:43AM +1000, Benjamin Herrenschmidt wrote: > On Thu, 2010-09-23 at 19:31 +0200, Richard Cochran wrote: > > A new syscall is introduced that allows tuning of a POSIX clock. The > > syscall is implemented for four architectures: arm, blackfin, powerpc, > > and x86. > > > > The new syscall, clock_adjtime, takes two parameters, the clock ID, > > and a pointer to a struct timex. The semantics of the timex struct > > have been expanded by one additional mode flag, which allows an > > absolute offset correction. When specificied, the clock offset is > > immediately corrected by adding the given time value to the current > > time value. > > Any reason why you CC'ed device-tree discuss ? > > This list is getting way too much unrelated stuff, which I find > annoying, it would be nice if we were all a bit more careful here with > our CC lists. Sorry, I only added device-tree because some one asked me to do so. http://marc.info/?l=linux-netdev&m=127273157912358 I'll leave it off next time. Thanks, Richard ___ Linuxppc-dev mailing list Linuxppc-dev@lists.ozlabs.org https://lists.ozlabs.org/listinfo/linuxppc-dev
Re: [PATCH v6 0/8] ptp: IEEE 1588 hardware clock support
On Thu, Sep 23, 2010 at 12:53:20PM -0500, Christoph Lameter wrote: > On Thu, 23 Sep 2010, Richard Cochran wrote: > > 3.3 Synchronizing the Linux System Time > > > > > >One could offer a PHC as a combined clock source and clock event > >device. The advantage of this approach would be that it obviates > >the need for synchronization when the PHC is selected as the system > >timer. However, some PHCs, namely the PHY based clocks, cannot be > >used in this way. > > Why not? Do PHY based clock not at least provide a counter that increments > in synchronized intervals throughout the network? The counter in the PHY is accessed via the MDIO bus. One 16 bit read takes anywhere from 25 to 40 microseconds. Reading the 64 bit time value requires four reads, so we're talking about 100 to 160 microseconds, just for a single time reading. In addition to that, reading MDIO bus can sleep. So, we can't (in general) to offer PHCs as clock sources. > >Instead, the patch set provides a way to offer a Pulse Per Second > >(PPS) event from the PHC to the Linux PPS subsystem. A user space > >application can read the PPS events and tune the system clock, just > >like when using other external time sources like radio clocks or > >GPS. > > User space is subject to various latencies created by the OS etc. I would > that in order to have fine grained (read microsecond) accurary we would > have to run the portions that are relevant to obtaining the desired > accuracy in the kernel. The time-critical operations are all performed in hardware (packet timestamp), or in kernel space (input PPS timestamp). User space only runs the servo (using hardware or kernel timestamps as input) and performs the clock correction. With a sample rate of 1 PPS, the small user space induced delay (a few dozen microseconds) between sample time and clock correction is not an issue. Thanks, Richard ___ Linuxppc-dev mailing list Linuxppc-dev@lists.ozlabs.org https://lists.ozlabs.org/listinfo/linuxppc-dev
Re: [PATCH 6/8] ptp: Added a clock that uses the eTSEC found on the MPC85xx.
On Thu, Sep 23, 2010 at 02:17:36PM -0500, Christoph Lameter wrote: > On Thu, 23 Sep 2010, Richard Cochran wrote: > > + These properties set the operational parameters for the PTP > > + clock. You must choose these carefully for the clock to work right. > > + Here is how to figure good values: > > + > > + TimerOsc = system clock MHz > > + tclk_period = desired clock period nanoseconds > > + NominalFreq = 1000 / tclk_period MHz > > + FreqDivRatio = TimerOsc / NominalFreq (must be greater that 1.0) > > + tmr_add = ceil(2^32 / FreqDivRatio) > > + OutputClock = NominalFreq / tmr_prsc MHz > > + PulseWidth = 1 / OutputClockmicroseconds > > + FiperFreq1 = desired frequency in Hz > > + FiperDiv1= 100 * OutputClock / FiperFreq1 > > + tmr_fiper1 = tmr_prsc * tclk_period * FiperDiv1 - tclk_period > > + max_adj = 10 * (FreqDivRatio - 1.0) - 1 > > Great stuff for clock synchronization... > > > + The calculation for tmr_fiper2 is the same as for tmr_fiper1. The > > + driver expects that tmr_fiper1 will be correctly set to produce a 1 > > + Pulse Per Second (PPS) signal, since this will be offered to the PPS > > + subsystem to synchronize the Linux clock. > > Argh. And conceptually completely screwed up. Why go through the PPS > subsystem if you can directly tune the system clock based on a number of > the cool periodic clock features that you have above? See how the other > clocks do that easily? Look into drivers/clocksource. Add it there. > > Please do not introduce useless additional layers for clock sync. Load > these ptp clocks like the other regular clock modules and make them sync > system time like any other clock. > > Really guys: I want a PTP solution! Now! And not some idiotic additional > kernel layers that just pass bits around because its so much fun and > screws up clock accurary in due to the latency noise introduced while > having so much fun with the bits. (Sorry if this message comes twice. Mutt/Gmail flaked out again.) I think you misunderstood this particular patch. The device tree parameters are really just internal driver stuff. When you use the eTSEC, you must make some design choices at the same time as you plan your board. The proper values for some of the eTSEC registers are based on these design choices. Since the Freescale documentation is a bit thin on this, I added a few notes to help my fellow board designers. Because these values are closely related to the board itself, I think that it is nicer to configure them via the device tree than using either CONFIG_ variables or platform data. Richard ___ Linuxppc-dev mailing list Linuxppc-dev@lists.ozlabs.org https://lists.ozlabs.org/listinfo/linuxppc-dev
Re: [PATCH v6 0/8] ptp: IEEE 1588 hardware clock support
On Thu, Sep 23, 2010 at 09:36:54PM +0100, Alan Cox wrote: > Drop the clockid_t and swap it for a file handle like a proper Unix or > Linux interface. The rest is much the same > > fd = open /sys/class/timesource/[whatever] > > various queries you may want to do to check the name etc > > fclock_adjtime(fd, ...) Okay, but lets extend the story: clock_getttime(fd, ...); clock_settime(fd, ...); timer_create(fd, ...); Can you agree to that as well? (We would need to ensure that 'fd' avoids the range 0 to MAX_CLOCKS). Richard ___ Linuxppc-dev mailing list Linuxppc-dev@lists.ozlabs.org https://lists.ozlabs.org/listinfo/linuxppc-dev
Re: [PATCH v6 0/8] ptp: IEEE 1588 hardware clock support
On Thu, Sep 23, 2010 at 12:38:53PM -0700, john stultz wrote: > On Thu, 2010-09-23 at 19:30 +0200, Richard Cochran wrote: > > /sys/class/timesource//id > > /sys/class/ptp/ptp_clock_X/id > > > So yea, I'm not a fan of the "timesource" sysfs interface. One, I think > the name is poor (posix_clocks or something a little more specific would > be an improvement), and second, I don't like the dictionary interface, > where one looks up the clock by name. > > Instead, I think having the id hanging off the class driver is much > better, as it allows mapping the actual hardware to the id more clearly. > > So I'd drop the "timesource" listing. And maybe change "id" to > "clock_id" so its a little more clear what the id is for. Okay, I will drop /sys/class/timesource (hope Alan Cox agrees :) I threw it out there mostly for the sake of discussion. I imagined that there could be other properties in that directory, like time scale (TAI, UTC, etc). But it seems like we don't really need anything in that direction. > > 3.3 Synchronizing the Linux System Time > > > > > >One could offer a PHC as a combined clock source and clock event > >device. The advantage of this approach would be that it obviates > >the need for synchronization when the PHC is selected as the system > >timer. However, some PHCs, namely the PHY based clocks, cannot be > >used in this way. > > Again, I'd scratch this. Okay, I only wanted to preempt the question which people are asking all the time: why can't it work with the system clock transparently? > >Instead, the patch set provides a way to offer a Pulse Per Second > >(PPS) event from the PHC to the Linux PPS subsystem. A user space > >application can read the PPS events and tune the system clock, just > >like when using other external time sources like radio clocks or > >GPS. > > Forgive me for a bit of a tangent here: > So while I think this PPS method is a neat idea, I'm a little curious > how much of a difference the PPS method for syncing the clock would be > over just a simple reading of the two clocks and correcting the offset. > > It seems much of it depends on the read latency of the PTP hardware vs > the interrupt latency. Also the PTP clock granularity would effect the > read accuracy (like on the RTC, you don't really know how close to the > second boundary you are). > > Have you done any such measurements between the two methods? I have not yet tested how well the PPS method works, but I expect at least as good results as when using a GPS. > I just > wonder if it would actually be something noticeable, and if its not, how > much lighter this patch-set would be without the PPS connection. As you say, the problem with just reading two clocks at nearly the same time is that you have two uncertain operations. If you use a PPS, then there is only one clock to read, and that clock is the system clock, which hopefully is not too slow to read! In addition, PHY reads can sleep, and that surely won't work. Even with MAC PHCs, reading outside of interrupt context makes you vulnerable to other interrupts. > Again, this isn't super critical, just trying to make sure we don't end > up adding a bunch of code that doesn't end up being used. The PPS hooks are really only just a few lines of code. The great advantage of a PPS approach over and ad-hoc "read two clocks and compare", is that, with a steady, known sample rate, you can analyze and predict your control loop behavior. There is lots of literature available on how to do it. IMHO, that is the big weakness of the timecompare.c stuff used in the current IGB driver. > Also PPS > interrupts are awfully frequent, so systems concerned with power-saving > and deep idles probably would like something that could be done at a > more coarse interval. We could always make the pulse rate programmable, for power-saving applications. > > 4.1 Supported Hardware Clocks > > == > > > >+ Standard Linux system timer > > This driver exports the standard Linux timer as a PTP clock. > > Although this duplicates CLOCK_REALTIME, the code serves as a > > simple example for driver development and lets people who without > > special hardware try the new API. > > Still not a fan of this one, figure the app should handle the special > case where there are no PTP clocks and just use CLOCK_REALTIME rather > then funneling CLOCK_REALTIME through the PTP interface. It is really just as an example and for people who want to test driver the API. It can surely be removed before the final version... Thanks for your comments, Richard ___ Linuxppc-dev mailing list Linuxppc-dev@lists.ozlabs.org https://lists.ozlabs.org/listinfo/linuxppc-dev
Re: [PATCH v6 0/8] ptp: IEEE 1588 hardware clock support
On Mon, Sep 27, 2010 at 10:14:23AM -0600, M. Warner Losh wrote:
>
> This is a common error that I've seen repeated in this thread. The
> only reason that it has historically been important is because when
> you are doing timestamping in software based on an interrupt, that
> stuff does matter.
Yes, thanks for your helpful explanation.
To further illustrate how small the effect of running the servo in
user space is, consider the following.
It is true that delays and jitter in the time to process the received
packet negatively affect the clock servo loop. However, the effect in
our case will be quite small.
John Eidson's book [1] presents a rigorous servo model that includes
an analysis of the delay from the time the samples (timestamps) are
taken until the corrective action is performed by the PTP software.
For PTP, the sample time is at the sender (the remote host, the master
clock). The master sends *two* packets, where the second one (the so
called follow-up packet) contains the hardware time stamp of the first
one. So, the computational delay includes the time spent by the sender
in its PTP stack preparing the second packet, the time the packet
spends in transit, and the time in the receiver's PTP stack and servo.
According to Eidson's analysis, a delay of up to 10 milliseconds would
be acceptable, even with a sample rate of 10 Hz. Therefore, saving a
few dozen microseconds by placing the servo (and PTP stack) into the
kernel is not worth the effort.
Richard
[1] title = {Measurement, control, and communication using IEEE 1588},
author ={J. C. Eidson},
year = 2006,
publisher = {Springer-Verlag},
___
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Re: [PATCH v6 0/8] ptp: IEEE 1588 hardware clock support
On Mon, Sep 27, 2010 at 06:05:58PM +0100, Alan Cox wrote: > On Mon, 27 Sep 2010 10:56:09 -0500 (CDT) > Christoph Lameter wrote: > > > > > On Fri, 24 Sep 2010, Alan Cox wrote: > > > > > Whether you add new syscalls or do the fd passing using flags and hide > > > the ugly bits in glibc is another question. > > > > Use device specific ioctls instead of syscalls? > > Some of the ioctls are probably not device specific, the job of the OS in > part is to present a unified interface. We already have a mess of HPET > and RTC driver ioctls. Yes, and the whole point of introducing a PTP hardare clock API was to avoid each new clock driver introducing yet another ioctl interface. I had proposed a standard ioctl interface for PTP hardware clocks, but that interface was rightly criticized for duplicating the posix clock API. It does not make sense to have multiple interfaces with the exact same functionality. It is impossible to support every last feature of every possible hardware clock with a generic interface, so there will always need to be special ioctls for such features. However, some clock functions *are* completely generic and apply to every clock: - set time - get time - adjust the frequency by N ppb - shift the time by a given offset The first two are provided by the posix clock interface, the third by the NTP adjtimex call, which also can support (by a single mode extension) the last item. Richard ___ Linuxppc-dev mailing list Linuxppc-dev@lists.ozlabs.org https://lists.ozlabs.org/listinfo/linuxppc-dev
[PATCH V11 0/4] ptp: IEEE 1588 hardware clock support
This just might be the last round of review of the PTP hardware clock patch series. These patches apply on top of the timers/core branch in the tip tree. Patches 1 and 4 have changed since the last version. * Why all the CCs? - One driver is for PowerPC, and adds device tree stuff. - One driver is for the ARM Xscale IXP465. * Patch ChangeLog ** v11 - added more padding to the structures in the user space ABI - tweaked Kconfig to make dependencies more clear - fixed locking on time stamp event queue - added John Stultz's acks on patches 2 and 3. - now the phyter driver handles multiple PHYs Richard Cochran (4): ptp: Added a brand new class driver for ptp clocks. ptp: Added a clock that uses the eTSEC found on the MPC85xx. ptp: Added a clock driver for the IXP46x. ptp: Added a clock driver for the National Semiconductor PHYTER. Documentation/ABI/testing/sysfs-ptp| 98 ++ .../devicetree/bindings/net/fsl-tsec-phy.txt | 57 ++ Documentation/ptp/ptp.txt | 89 ++ Documentation/ptp/testptp.c| 352 +++ Documentation/ptp/testptp.mk | 33 + arch/arm/mach-ixp4xx/include/mach/ixp46x_ts.h | 78 ++ arch/powerpc/boot/dts/mpc8313erdb.dts | 14 + arch/powerpc/boot/dts/mpc8572ds.dts| 14 + arch/powerpc/boot/dts/p2020ds.dts | 14 + arch/powerpc/boot/dts/p2020rdb.dts | 14 + drivers/Kconfig|2 + drivers/Makefile |1 + drivers/net/Makefile |1 + drivers/net/arm/ixp4xx_eth.c | 192 - drivers/net/gianfar_ptp.c | 448 + drivers/net/gianfar_ptp_reg.h | 113 +++ drivers/net/phy/Makefile |1 + drivers/net/phy/dp83640.c | 1012 drivers/net/phy/dp83640_reg.h | 267 + drivers/ptp/Kconfig| 75 ++ drivers/ptp/Makefile |7 + drivers/ptp/ptp_chardev.c | 156 +++ drivers/ptp/ptp_clock.c| 320 ++ drivers/ptp/ptp_ixp46x.c | 332 +++ drivers/ptp/ptp_private.h | 86 ++ drivers/ptp/ptp_sysfs.c| 230 + include/linux/Kbuild |1 + include/linux/ptp_clock.h | 84 ++ include/linux/ptp_clock_kernel.h | 139 +++ 29 files changed, 4227 insertions(+), 3 deletions(-) create mode 100644 Documentation/ABI/testing/sysfs-ptp create mode 100644 Documentation/ptp/ptp.txt create mode 100644 Documentation/ptp/testptp.c create mode 100644 Documentation/ptp/testptp.mk create mode 100644 arch/arm/mach-ixp4xx/include/mach/ixp46x_ts.h create mode 100644 drivers/net/gianfar_ptp.c create mode 100644 drivers/net/gianfar_ptp_reg.h create mode 100644 drivers/net/phy/dp83640.c create mode 100644 drivers/net/phy/dp83640_reg.h create mode 100644 drivers/ptp/Kconfig create mode 100644 drivers/ptp/Makefile create mode 100644 drivers/ptp/ptp_chardev.c create mode 100644 drivers/ptp/ptp_clock.c create mode 100644 drivers/ptp/ptp_ixp46x.c create mode 100644 drivers/ptp/ptp_private.h create mode 100644 drivers/ptp/ptp_sysfs.c create mode 100644 include/linux/ptp_clock.h create mode 100644 include/linux/ptp_clock_kernel.h ___ Linuxppc-dev mailing list Linuxppc-dev@lists.ozlabs.org https://lists.ozlabs.org/listinfo/linuxppc-dev
[PATCH V11 1/4] ptp: Added a brand new class driver for ptp clocks.
This patch adds an infrastructure for hardware clocks that implement IEEE 1588, the Precision Time Protocol (PTP). A class driver offers a registration method to particular hardware clock drivers. Each clock is presented as a standard POSIX clock. The ancillary clock features are exposed in two different ways, via the sysfs and by a character device. Signed-off-by: Richard Cochran --- Documentation/ABI/testing/sysfs-ptp | 98 ++ Documentation/ptp/ptp.txt | 89 + Documentation/ptp/testptp.c | 352 +++ Documentation/ptp/testptp.mk| 33 drivers/Kconfig |2 + drivers/Makefile|1 + drivers/ptp/Kconfig | 30 +++ drivers/ptp/Makefile|6 + drivers/ptp/ptp_chardev.c | 156 drivers/ptp/ptp_clock.c | 320 +++ drivers/ptp/ptp_private.h | 86 + drivers/ptp/ptp_sysfs.c | 230 +++ include/linux/Kbuild|1 + include/linux/ptp_clock.h | 84 + include/linux/ptp_clock_kernel.h| 139 ++ 15 files changed, 1627 insertions(+), 0 deletions(-) create mode 100644 Documentation/ABI/testing/sysfs-ptp create mode 100644 Documentation/ptp/ptp.txt create mode 100644 Documentation/ptp/testptp.c create mode 100644 Documentation/ptp/testptp.mk create mode 100644 drivers/ptp/Kconfig create mode 100644 drivers/ptp/Makefile create mode 100644 drivers/ptp/ptp_chardev.c create mode 100644 drivers/ptp/ptp_clock.c create mode 100644 drivers/ptp/ptp_private.h create mode 100644 drivers/ptp/ptp_sysfs.c create mode 100644 include/linux/ptp_clock.h create mode 100644 include/linux/ptp_clock_kernel.h diff --git a/Documentation/ABI/testing/sysfs-ptp b/Documentation/ABI/testing/sysfs-ptp new file mode 100644 index 000..d40d2b5 --- /dev/null +++ b/Documentation/ABI/testing/sysfs-ptp @@ -0,0 +1,98 @@ +What: /sys/class/ptp/ +Date: September 2010 +Contact: Richard Cochran +Description: + This directory contains files and directories + providing a standardized interface to the ancillary + features of PTP hardware clocks. + +What: /sys/class/ptp/ptpN/ +Date: September 2010 +Contact: Richard Cochran +Description: + This directory contains the attributes of the Nth PTP + hardware clock registered into the PTP class driver + subsystem. + +What: /sys/class/ptp/ptpN/clock_name +Date: September 2010 +Contact: Richard Cochran +Description: + This file contains the name of the PTP hardware clock + as a human readable string. + +What: /sys/class/ptp/ptpN/max_adjustment +Date: September 2010 +Contact: Richard Cochran +Description: + This file contains the PTP hardware clock's maximum + frequency adjustment value (a positive integer) in + parts per billion. + +What: /sys/class/ptp/ptpN/n_alarms +Date: September 2010 +Contact: Richard Cochran +Description: + This file contains the number of periodic or one shot + alarms offer by the PTP hardware clock. + +What: /sys/class/ptp/ptpN/n_external_timestamps +Date: September 2010 +Contact: Richard Cochran +Description: + This file contains the number of external timestamp + channels offered by the PTP hardware clock. + +What: /sys/class/ptp/ptpN/n_periodic_outputs +Date: September 2010 +Contact: Richard Cochran +Description: + This file contains the number of programmable periodic + output channels offered by the PTP hardware clock. + +What: /sys/class/ptp/ptpN/pps_avaiable +Date: September 2010 +Contact: Richard Cochran +Description: + This file indicates whether the PTP hardware clock + supports a Pulse Per Second to the host CPU. Reading + "1" means that the PPS is supported, while "0" means + not supported. + +What: /sys/class/ptp/ptpN/extts_enable +Date: September 2010 +Contact: Richard Cochran +Description: + This write-only file enables or disables external + timestamps. To enable external timestamps, write the + channel index followed by a "1" into the file. + To disable external timestamps, write the channel + index followed by a "0" into the file. + +What: /sys/class/ptp/ptpN/fifo +Date: September 2010 +Contact: Richard Cochran +Description: + This file provides timestamps on external
[PATCH V11 2/4] ptp: Added a clock that uses the eTSEC found on the MPC85xx.
The eTSEC includes a PTP clock with quite a few features. This patch adds
support for the basic clock adjustment functions, plus two external time
stamps, one alarm, and the PPS callback.
Signed-off-by: Richard Cochran
Acked-by: John Stultz
---
.../devicetree/bindings/net/fsl-tsec-phy.txt | 57 +++
arch/powerpc/boot/dts/mpc8313erdb.dts | 14 +
arch/powerpc/boot/dts/mpc8572ds.dts| 14 +
arch/powerpc/boot/dts/p2020ds.dts | 14 +
arch/powerpc/boot/dts/p2020rdb.dts | 14 +
drivers/net/Makefile |1 +
drivers/net/gianfar_ptp.c | 448
drivers/net/gianfar_ptp_reg.h | 113 +
drivers/ptp/Kconfig| 13 +
9 files changed, 688 insertions(+), 0 deletions(-)
create mode 100644 drivers/net/gianfar_ptp.c
create mode 100644 drivers/net/gianfar_ptp_reg.h
diff --git a/Documentation/devicetree/bindings/net/fsl-tsec-phy.txt
b/Documentation/devicetree/bindings/net/fsl-tsec-phy.txt
index edb7ae1..f6edbb8 100644
--- a/Documentation/devicetree/bindings/net/fsl-tsec-phy.txt
+++ b/Documentation/devicetree/bindings/net/fsl-tsec-phy.txt
@@ -74,3 +74,60 @@ Example:
interrupt-parent = <&mpic>;
phy-handle = <&phy0>
};
+
+* Gianfar PTP clock nodes
+
+General Properties:
+
+ - compatible Should be "fsl,etsec-ptp"
+ - reg Offset and length of the register set for the device
+ - interrupts There should be at least two interrupts. Some devices
+ have as many as four PTP related interrupts.
+
+Clock Properties:
+
+ - tclk-period Timer reference clock period in nanoseconds.
+ - tmr-prsc Prescaler, divides the output clock.
+ - tmr-add Frequency compensation value.
+ - cksel0= external clock, 1= eTSEC system clock, 3= RTC clock input.
+ Currently the driver only supports choice "1".
+ - tmr-fiper1 Fixed interval period pulse generator.
+ - tmr-fiper2 Fixed interval period pulse generator.
+ - max-adj Maximum frequency adjustment in parts per billion.
+
+ These properties set the operational parameters for the PTP
+ clock. You must choose these carefully for the clock to work right.
+ Here is how to figure good values:
+
+ TimerOsc = system clock MHz
+ tclk_period = desired clock period nanoseconds
+ NominalFreq = 1000 / tclk_period MHz
+ FreqDivRatio = TimerOsc / NominalFreq (must be greater that 1.0)
+ tmr_add = ceil(2^32 / FreqDivRatio)
+ OutputClock = NominalFreq / tmr_prsc MHz
+ PulseWidth = 1 / OutputClockmicroseconds
+ FiperFreq1 = desired frequency in Hz
+ FiperDiv1= 100 * OutputClock / FiperFreq1
+ tmr_fiper1 = tmr_prsc * tclk_period * FiperDiv1 - tclk_period
+ max_adj = 10 * (FreqDivRatio - 1.0) - 1
+
+ The calculation for tmr_fiper2 is the same as for tmr_fiper1. The
+ driver expects that tmr_fiper1 will be correctly set to produce a 1
+ Pulse Per Second (PPS) signal, since this will be offered to the PPS
+ subsystem to synchronize the Linux clock.
+
+Example:
+
+ ptp_clock@24E00 {
+ compatible = "fsl,etsec-ptp";
+ reg = <0x24E00 0xB0>;
+ interrupts = <12 0x8 13 0x8>;
+ interrupt-parent = < &ipic >;
+ tclk-period = <10>;
+ tmr-prsc= <100>;
+ tmr-add = <0x99A4>;
+ cksel = <0x1>;
+ tmr-fiper1 = <0x3B9AC9F6>;
+ tmr-fiper2 = <0x00018696>;
+ max-adj = <65998>;
+ };
diff --git a/arch/powerpc/boot/dts/mpc8313erdb.dts
b/arch/powerpc/boot/dts/mpc8313erdb.dts
index 183f2aa..85a7eaa 100644
--- a/arch/powerpc/boot/dts/mpc8313erdb.dts
+++ b/arch/powerpc/boot/dts/mpc8313erdb.dts
@@ -208,6 +208,20 @@
sleep = <&pmc 0x0030>;
};
+ ptp_clock@24E00 {
+ compatible = "fsl,etsec-ptp";
+ reg = <0x24E00 0xB0>;
+ interrupts = <12 0x8 13 0x8>;
+ interrupt-parent = < &ipic >;
+ tclk-period = <10>;
+ tmr-prsc= <100>;
+ tmr-add = <0x99A4>;
+ cksel = <0x1>;
+ tmr-fiper1 = <0x3B9AC9F6>;
+ tmr-fiper2 = <0x00018696>;
+ max-adj = <65998>;
+ };
+
enet0: ethernet@24000 {
#address-cells = <1>;
#size-cells = <1>;
diff --gi
[PATCH V11 4/4] ptp: Added a clock driver for the National Semiconductor PHYTER.
This patch adds support for the PTP clock found on the DP83640.
The basic clock operations and one external time stamp have
been implemented.
Signed-off-by: Richard Cochran
---
drivers/net/phy/Makefile |1 +
drivers/net/phy/dp83640.c | 1012 +
drivers/net/phy/dp83640_reg.h | 267 +++
drivers/ptp/Kconfig | 19 +
4 files changed, 1299 insertions(+), 0 deletions(-)
create mode 100644 drivers/net/phy/dp83640.c
create mode 100644 drivers/net/phy/dp83640_reg.h
diff --git a/drivers/net/phy/Makefile b/drivers/net/phy/Makefile
index 13bebab..2333215 100644
--- a/drivers/net/phy/Makefile
+++ b/drivers/net/phy/Makefile
@@ -19,6 +19,7 @@ obj-$(CONFIG_FIXED_PHY) += fixed.o
obj-$(CONFIG_MDIO_BITBANG) += mdio-bitbang.o
obj-$(CONFIG_MDIO_GPIO)+= mdio-gpio.o
obj-$(CONFIG_NATIONAL_PHY) += national.o
+obj-$(CONFIG_DP83640_PHY) += dp83640.o
obj-$(CONFIG_STE10XP) += ste10Xp.o
obj-$(CONFIG_MICREL_PHY) += micrel.o
obj-$(CONFIG_MDIO_OCTEON) += mdio-octeon.o
diff --git a/drivers/net/phy/dp83640.c b/drivers/net/phy/dp83640.c
new file mode 100644
index 000..74f751e
--- /dev/null
+++ b/drivers/net/phy/dp83640.c
@@ -0,0 +1,1012 @@
+/*
+ * Driver for the National Semiconductor DP83640 PHYTER
+ *
+ * Copyright (C) 2010 OMICRON electronics GmbH
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
+ */
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+#include "dp83640_reg.h"
+
+#define DP83640_PHY_ID 0x20005ce1
+#define PAGESEL0x13
+#define LAYER4 0x02
+#define LAYER2 0x01
+#define MAX_RXTS 4
+#define MAX_TXTS 4
+#define N_EXT_TS 1
+#define PSF_PTPVER 2
+#define PSF_EVNT 0x4000
+#define PSF_RX 0x2000
+#define PSF_TX 0x1000
+#define EXT_EVENT 1
+#define EXT_GPIO 1
+#define CAL_EVENT 2
+#define CAL_GPIO 9
+#define CAL_TRIGGER2
+
+/* phyter seems to miss the mark by 16 ns */
+#define ADJTIME_FIX16
+
+#if defined(__BIG_ENDIAN)
+#define ENDIAN_FLAG0
+#elif defined(__LITTLE_ENDIAN)
+#define ENDIAN_FLAGPSF_ENDIAN
+#endif
+
+#define SKB_PTP_TYPE(__skb) (*(unsigned int *)((__skb)->cb))
+
+struct phy_rxts {
+ u16 ns_lo; /* ns[15:0] */
+ u16 ns_hi; /* overflow[1:0], ns[29:16] */
+ u16 sec_lo; /* sec[15:0] */
+ u16 sec_hi; /* sec[31:16] */
+ u16 seqid; /* sequenceId[15:0] */
+ u16 msgtype; /* messageType[3:0], hash[11:0] */
+};
+
+struct phy_txts {
+ u16 ns_lo; /* ns[15:0] */
+ u16 ns_hi; /* overflow[1:0], ns[29:16] */
+ u16 sec_lo; /* sec[15:0] */
+ u16 sec_hi; /* sec[31:16] */
+};
+
+struct rxts {
+ struct list_head list;
+ unsigned long tmo;
+ u64 ns;
+ u16 seqid;
+ u8 msgtype;
+ u16 hash;
+};
+
+struct dp83640_clock;
+
+struct dp83640_private {
+ struct list_head list;
+ struct dp83640_clock *clock;
+ struct phy_device *phydev;
+ struct work_struct ts_work;
+ int hwts_tx_en;
+ int hwts_rx_en;
+ int layer;
+ int version;
+ /* remember state of cfg0 during calibration */
+ int cfg0;
+ /* remember the last event time stamp */
+ struct phy_txts edata;
+ /* list of rx timestamps */
+ struct list_head rxts;
+ struct list_head rxpool;
+ struct rxts rx_pool_data[MAX_RXTS];
+ /* protects above three fields from concurrent access */
+ spinlock_t rx_lock;
+ /* queues of incoming and outgoing packets */
+ struct sk_buff_head rx_queue;
+ struct sk_buff_head tx_queue;
+};
+
+struct dp83640_clock {
+ /* protects extended registers from concurrent access */
+ struct mutex extreg_lock;
+ /* remembers which page was last selected */
+ int page;
+ /* our advertised capabilities */
+ struct ptp_clock_info caps;
+ /* the one phyter from which we shall read */
+ struct dp83640_private *chosen;
+ /* list of the other attached phyters, not chosen */
+ struct list_head phylist;
+ /* reference to our PTP hardware clock */
+ struct ptp_clock *ptp_clock;
+};
+
+/* globals
[PATCH V11 3/4] ptp: Added a clock driver for the IXP46x.
This patch adds a driver for the hardware time stamping unit found on the
IXP465. The basic clock operations and an external trigger are implemented.
Signed-off-by: Richard Cochran
Acked-by: John Stultz
---
arch/arm/mach-ixp4xx/include/mach/ixp46x_ts.h | 78 ++
drivers/net/arm/ixp4xx_eth.c | 192 ++-
drivers/ptp/Kconfig | 13 +
drivers/ptp/Makefile |1 +
drivers/ptp/ptp_ixp46x.c | 332 +
5 files changed, 613 insertions(+), 3 deletions(-)
create mode 100644 arch/arm/mach-ixp4xx/include/mach/ixp46x_ts.h
create mode 100644 drivers/ptp/ptp_ixp46x.c
diff --git a/arch/arm/mach-ixp4xx/include/mach/ixp46x_ts.h
b/arch/arm/mach-ixp4xx/include/mach/ixp46x_ts.h
new file mode 100644
index 000..292d55e
--- /dev/null
+++ b/arch/arm/mach-ixp4xx/include/mach/ixp46x_ts.h
@@ -0,0 +1,78 @@
+/*
+ * PTP 1588 clock using the IXP46X
+ *
+ * Copyright (C) 2010 OMICRON electronics GmbH
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
+ */
+
+#ifndef _IXP46X_TS_H_
+#define _IXP46X_TS_H_
+
+#define DEFAULT_ADDEND 0xF029
+#define TICKS_NS_SHIFT 4
+
+struct ixp46x_channel_ctl {
+ u32 ch_control; /* 0x40 Time Synchronization Channel Control */
+ u32 ch_event;/* 0x44 Time Synchronization Channel Event */
+ u32 tx_snap_lo; /* 0x48 Transmit Snapshot Low Register */
+ u32 tx_snap_hi; /* 0x4C Transmit Snapshot High Register */
+ u32 rx_snap_lo; /* 0x50 Receive Snapshot Low Register */
+ u32 rx_snap_hi; /* 0x54 Receive Snapshot High Register */
+ u32 src_uuid_lo; /* 0x58 Source UUID0 Low Register */
+ u32 src_uuid_hi; /* 0x5C Sequence Identifier/Source UUID0 High */
+};
+
+struct ixp46x_ts_regs {
+ u32 control; /* 0x00 Time Sync Control Register */
+ u32 event; /* 0x04 Time Sync Event Register */
+ u32 addend; /* 0x08 Time Sync Addend Register */
+ u32 accum; /* 0x0C Time Sync Accumulator Register */
+ u32 test;/* 0x10 Time Sync Test Register */
+ u32 unused; /* 0x14 */
+ u32 rsystime_lo; /* 0x18 RawSystemTime_Low Register */
+ u32 rsystime_hi; /* 0x1C RawSystemTime_High Register */
+ u32 systime_lo; /* 0x20 SystemTime_Low Register */
+ u32 systime_hi; /* 0x24 SystemTime_High Register */
+ u32 trgt_lo; /* 0x28 TargetTime_Low Register */
+ u32 trgt_hi; /* 0x2C TargetTime_High Register */
+ u32 asms_lo; /* 0x30 Auxiliary Slave Mode Snapshot Low */
+ u32 asms_hi; /* 0x34 Auxiliary Slave Mode Snapshot High */
+ u32 amms_lo; /* 0x38 Auxiliary Master Mode Snapshot Low */
+ u32 amms_hi; /* 0x3C Auxiliary Master Mode Snapshot High */
+
+ struct ixp46x_channel_ctl channel[3];
+};
+
+/* 0x00 Time Sync Control Register Bits */
+#define TSCR_AMM (1<<3)
+#define TSCR_ASM (1<<2)
+#define TSCR_TTM (1<<1)
+#define TSCR_RST (1<<0)
+
+/* 0x04 Time Sync Event Register Bits */
+#define TSER_SNM (1<<3)
+#define TSER_SNS (1<<2)
+#define TTIPEND (1<<1)
+
+/* 0x40 Time Synchronization Channel Control Register Bits */
+#define MASTER_MODE (1<<0)
+#define TIMESTAMP_ALL (1<<1)
+
+/* 0x44 Time Synchronization Channel Event Register Bits */
+#define TX_SNAPSHOT_LOCKED (1<<0)
+#define RX_SNAPSHOT_LOCKED (1<<1)
+
+#endif
diff --git a/drivers/net/arm/ixp4xx_eth.c b/drivers/net/arm/ixp4xx_eth.c
index 9eb9b98..fa08c17 100644
--- a/drivers/net/arm/ixp4xx_eth.c
+++ b/drivers/net/arm/ixp4xx_eth.c
@@ -30,9 +30,12 @@
#include
#include
#include
+#include
#include
#include
+#include
#include
+#include
#include
#include
@@ -67,6 +70,10 @@
#define RXFREE_QUEUE(port_id) (NPE_ID(port_id) + 26)
#define TXDONE_QUEUE 31
+#define PTP_SLAVE_MODE 1
+#define PTP_MASTER_MODE2
+#define PORT2CHANNEL(p)NPE_ID(p->id)
+
/* TX Control Registers */
#define TX_CNTRL0_TX_EN0x01
#define TX_CNTRL0_HALFDUPLEX 0x02
@@ -171,6 +178,8 @@ struct port {
int id; /* logical port ID */
int speed, duplex;
u8 firmware[4];
+ int hwts_tx_en;
+ int hwts_rx_en;
};
/*
Re: [PATCH V11 0/4] ptp: IEEE 1588 hardware clock support
* Previous Discussions This patch set previously appeared on the netdev list. Since V5 of the character device patch set, the discussion has moved to the lkml. - IEEE 1588 hardware clock support [V5] http://lkml.org/lkml/2010/8/16/90 - POSIX clock tuning syscall with static clock ids http://lkml.org/lkml/2010/8/23/49 - POSIX clock tuning syscall with dynamic clock ids http://lkml.org/lkml/2010/9/3/119 - IEEE 1588 hardware clock support [V6] http://lkml.org/lkml/2010/9/23/310 - Dynamic clock devices [RFC] http://lkml.org/lkml/2010/11/4/290 - IEEE 1588 hardware clock support [V7] http://lkml.org/lkml/2010/12/16/195 - IEEE 1588 hardware clock support [V8] http://lkml.org/lkml/2010/12/31/128 - IEEE 1588 hardware clock support [V9] http://lkml.org/lkml/2011/1/13/65 - IEEE 1588 hardware clock support [V10] http://lkml.org/lkml/2011/1/27/71 - Thomas Gleixner: Rework of the PTP support series core code http://lkml.org/lkml/2011/2/1/137 ___ Linuxppc-dev mailing list Linuxppc-dev@lists.ozlabs.org https://lists.ozlabs.org/listinfo/linuxppc-dev
Re: [PATCH V11 2/4] ptp: Added a clock that uses the eTSEC found on the MPC85xx.
On Wed, Feb 23, 2011 at 10:54:59AM -0700, Grant Likely wrote: > On Wed, Feb 23, 2011 at 11:26:12AM -0600, Scott Wood wrote: > > The eTSEC revision is probeable as well, but due the way PTP is described as > > a separate node, the driver doesn't have straightforward access to those > > registers. > > Ignorant question: Should the ptp be described as a separate node? Well, the PTP Hardware Clock function is logically separate from the MAC function. PHCs can be implemented in the MAC, in the PHY, or in between in an FPGA on MII bus. If the PHC is in the MAC, then it might be wise to implement one driver that offers both the MAC and the PHC. In the case of gianfar, it is not really necessary to combine the PHC into the gianfar driver, since the registers are pretty well separated. Also, given the size and complexity (and churn over time) of the gianfar driver, I decided to keep the PHC separate. Right now, the driver correctly handles all the clock revisions in the boards that I have (mpc8313, mpc8572, p2020ds, p2020rdb). If checking the revision becomes important, then we can always export a function from gianfar to provide this. Thanks, Richard ___ Linuxppc-dev mailing list Linuxppc-dev@lists.ozlabs.org https://lists.ozlabs.org/listinfo/linuxppc-dev
Re: [PATCH V11 2/4] ptp: Added a clock that uses the eTSEC found on the MPC85xx.
On Wed, Feb 23, 2011 at 01:24:44PM -0600, Scott Wood wrote:
> Whatever string is used should be written into a binding document.
>
> fsl,etsec-v1.6-ptp seems like it would be just as good for that purpose.
>
> Even just fsl,etsec-ptp will identify the binding, though it's lacking in
> identifying the hardware (in the absence of access to the eTSEC ID
> registers).
I read the conversation, and I don't mind admitting that I do not
understand what you both are arguing/discussing about.
How should I set the strings? Like this?
arch/powerpc/boot/dts/mpc8313erdb.dts:
ptp_clock@24E00 {
compatible = "fsl,mpc8313-etsec-ptp";
}
arch/powerpc/boot/dts/mpc8572ds.dts:
ptp_clock@24E00 {
compatible = "fsl,mpc8572-etsec-ptp";
}
arch/powerpc/boot/dts/p2020ds.dts:
ptp_clock@24E00 {
compatible = "fsl,p2020ds-etsec-ptp";
}
arch/powerpc/boot/dts/p2020rdb.dts:
ptp_clock@24E00 {
compatible = "fsl,p2020rdb-etsec-ptp";
}
drivers/net/gianfar_ptp.c:
static struct of_device_id match_table[] = {
{ .compatible = "fsl,mpc8313-etsec-ptp" },
{ .compatible = "fsl,mpc8572-etsec-ptp" },
{ .compatible = "fsl,p2020ds-etsec-ptp" },
{ .compatible = "fsl,p2020rdb-etsec-ptp" },
{},
};
Please let me know if this is what you meant.
Thanks,
Richard
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Re: [PATCH V11 2/4] ptp: Added a clock that uses the eTSEC found on the MPC85xx.
On Wed, Feb 23, 2011 at 09:50:58AM -0700, Grant Likely wrote:
> On Wed, Feb 23, 2011 at 11:38:17AM +0100, Richard Cochran wrote:
> > +Clock Properties:
> > +
> > + - tclk-period Timer reference clock period in nanoseconds.
> > + - tmr-prsc Prescaler, divides the output clock.
> > + - tmr-add Frequency compensation value.
> > + - cksel0= external clock, 1= eTSEC system clock, 3= RTC clock
> > input.
> > + Currently the driver only supports choice "1".
>
> I'd be hesitant about defining something that isn't actually
> implemented yet. You may find the binding to be insufficient at a
> later date.
Okay, I'll remove it.
We never got the external VCO working anyhow.
> > + - tmr-fiper1 Fixed interval period pulse generator.
> > + - tmr-fiper2 Fixed interval period pulse generator.
> > + - max-adj Maximum frequency adjustment in parts per billion.
>
> These are all custom properties (not part of any shared binding) so
> they should probably be prefixed with 'fsl,'.
Okay, fine.
> > + The calculation for tmr_fiper2 is the same as for tmr_fiper1. The
> > + driver expects that tmr_fiper1 will be correctly set to produce a 1
> > + Pulse Per Second (PPS) signal, since this will be offered to the PPS
> > + subsystem to synchronize the Linux clock.
>
> Good documentation, thanks. Question though, how many of these values
> will the end user (or board builder) be likely to want to change. It
> is risky encoding the calculation results into the device tree when
> they aren't the actually parameters that will be manipulated, or at
> least very user-unfriendly.
The whole thing is pretty opaque, and my explanation is (IMHO) way
better that Freescale's documentation of how the fipers work.
The board designer / system designer will want to set these carefully,
but never change them. Basically, for a given input clock, there is
only one optimal setting.
I think the device tree is the right place for that kind of setting.
The fiper1 signal should always be a 1 PPS. We could make fiper2 run
time programmable via PHC ioctls, but I think this can wait.
> > + etsects->irq = irq_of_parse_and_map(node, 0);
>
> Use platform_get_irq().
Okay.
> > + etsects->regs = of_iomap(node, 0);
>
> Use platform_get_resource(), and don't forget to request the
> resources.
Okay, but didn't you tell me before to do this way?
http://marc.info/?l=linux-netdev&m=127662247203659&w=4
> > +static struct of_platform_driver gianfar_ptp_driver = {
>
> Use a platform_driver instead. of_platform_driver is deprecated and
> being removed.
Ja, should have noticed that myself, sorry.
> > +++ b/drivers/net/gianfar_ptp_reg.h
>
> This data is only used by gianfar_ptp.c, so there is no need for a
> separate include file. Move the contents of gianfar_ptp_reg.h into
> gianfar_ptp.c
You are right, of course, since private #defines and declarations
should simply stay in their .c files. Some people think that all
#defines and declarations must go into a header file.
I am not one of those people, but in this case, I generated the file
from a little tool I wrote and so kept it separate.
Still, it is no trouble to combine the header into the driver .c file.
Thanks for your review,
Richard
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Re: [PATCH V11 2/4] ptp: Added a clock that uses the eTSEC found on the MPC85xx.
On Thu, Feb 24, 2011 at 11:27:31AM -0600, Scott Wood wrote: > My vote, if it goes in a separate node at all, is "fsl,etsec-ptp", So, that is what the patch does. > and let the driver use SVR. What is SVR? Thanks, Richard ___ Linuxppc-dev mailing list Linuxppc-dev@lists.ozlabs.org https://lists.ozlabs.org/listinfo/linuxppc-dev
[PATCH V12 0/4] ptp: IEEE 1588 hardware clock support
This really might be the last review of the PTP hardware clock patch series. These patches apply on top of the timers/core branch in the tip tree. * Why all the CCs? - One driver is for PowerPC, and adds device tree stuff. - One driver is for the ARM Xscale IXP465. * PHC Patch ChangeLog ** v12 *** gianfar_ptp - fixed up device tree - inlined the header file - use platform_ calls instead of deprecated of_ calls - removed static global single instance - removed John Stultz's ack from this patch * Previous Discussions - [V11] http://lkml.org/lkml/2011/2/23/107 - [V10] http://lkml.org/lkml/2011/1/27/71 - [V9] http://lkml.org/lkml/2011/1/13/65 - [V8] http://lkml.org/lkml/2010/12/31/128 - [V7] http://lkml.org/lkml/2010/12/16/195 - [V6] http://lkml.org/lkml/2010/9/23/310 - [V5] http://lkml.org/lkml/2010/8/16/90 - Thomas Gleixner: Rework of the PTP support series core code http://lkml.org/lkml/2011/2/1/137 - Dynamic clock devices [RFC] http://lkml.org/lkml/2010/11/4/290 - POSIX clock tuning syscall with dynamic clock ids http://lkml.org/lkml/2010/9/3/119 - POSIX clock tuning syscall with static clock ids http://lkml.org/lkml/2010/8/23/49 - Versions 1-4 appeared on the netdev list. Richard Cochran (4): ptp: Added a brand new class driver for ptp clocks. ptp: Added a clock that uses the eTSEC found on the MPC85xx. ptp: Added a clock driver for the IXP46x. ptp: Added a clock driver for the National Semiconductor PHYTER. Documentation/ABI/testing/sysfs-ptp| 98 ++ .../devicetree/bindings/net/fsl-tsec-phy.txt | 54 + Documentation/ptp/ptp.txt | 89 ++ Documentation/ptp/testptp.c| 352 +++ Documentation/ptp/testptp.mk | 33 + arch/arm/mach-ixp4xx/include/mach/ixp46x_ts.h | 78 ++ arch/powerpc/boot/dts/mpc8313erdb.dts | 13 + arch/powerpc/boot/dts/mpc8572ds.dts| 13 + arch/powerpc/boot/dts/p2020ds.dts | 13 + arch/powerpc/boot/dts/p2020rdb.dts | 13 + drivers/Kconfig|2 + drivers/Makefile |1 + drivers/net/Makefile |1 + drivers/net/arm/ixp4xx_eth.c | 192 - drivers/net/gianfar_ptp.c | 579 +++ drivers/net/phy/Makefile |1 + drivers/net/phy/dp83640.c | 1012 drivers/net/phy/dp83640_reg.h | 267 + drivers/ptp/Kconfig| 75 ++ drivers/ptp/Makefile |7 + drivers/ptp/ptp_chardev.c | 156 +++ drivers/ptp/ptp_clock.c| 320 ++ drivers/ptp/ptp_ixp46x.c | 332 +++ drivers/ptp/ptp_private.h | 86 ++ drivers/ptp/ptp_sysfs.c| 230 + include/linux/Kbuild |1 + include/linux/ptp_clock.h | 84 ++ include/linux/ptp_clock_kernel.h | 139 +++ 28 files changed, 4238 insertions(+), 3 deletions(-) create mode 100644 Documentation/ABI/testing/sysfs-ptp create mode 100644 Documentation/ptp/ptp.txt create mode 100644 Documentation/ptp/testptp.c create mode 100644 Documentation/ptp/testptp.mk create mode 100644 arch/arm/mach-ixp4xx/include/mach/ixp46x_ts.h create mode 100644 drivers/net/gianfar_ptp.c create mode 100644 drivers/net/phy/dp83640.c create mode 100644 drivers/net/phy/dp83640_reg.h create mode 100644 drivers/ptp/Kconfig create mode 100644 drivers/ptp/Makefile create mode 100644 drivers/ptp/ptp_chardev.c create mode 100644 drivers/ptp/ptp_clock.c create mode 100644 drivers/ptp/ptp_ixp46x.c create mode 100644 drivers/ptp/ptp_private.h create mode 100644 drivers/ptp/ptp_sysfs.c create mode 100644 include/linux/ptp_clock.h create mode 100644 include/linux/ptp_clock_kernel.h ___ Linuxppc-dev mailing list Linuxppc-dev@lists.ozlabs.org https://lists.ozlabs.org/listinfo/linuxppc-dev
[PATCH V12 1/4] ptp: Added a brand new class driver for ptp clocks.
This patch adds an infrastructure for hardware clocks that implement IEEE 1588, the Precision Time Protocol (PTP). A class driver offers a registration method to particular hardware clock drivers. Each clock is presented as a standard POSIX clock. The ancillary clock features are exposed in two different ways, via the sysfs and by a character device. Signed-off-by: Richard Cochran --- Documentation/ABI/testing/sysfs-ptp | 98 ++ Documentation/ptp/ptp.txt | 89 + Documentation/ptp/testptp.c | 352 +++ Documentation/ptp/testptp.mk| 33 drivers/Kconfig |2 + drivers/Makefile|1 + drivers/ptp/Kconfig | 30 +++ drivers/ptp/Makefile|6 + drivers/ptp/ptp_chardev.c | 156 drivers/ptp/ptp_clock.c | 320 +++ drivers/ptp/ptp_private.h | 86 + drivers/ptp/ptp_sysfs.c | 230 +++ include/linux/Kbuild|1 + include/linux/ptp_clock.h | 84 + include/linux/ptp_clock_kernel.h| 139 ++ 15 files changed, 1627 insertions(+), 0 deletions(-) create mode 100644 Documentation/ABI/testing/sysfs-ptp create mode 100644 Documentation/ptp/ptp.txt create mode 100644 Documentation/ptp/testptp.c create mode 100644 Documentation/ptp/testptp.mk create mode 100644 drivers/ptp/Kconfig create mode 100644 drivers/ptp/Makefile create mode 100644 drivers/ptp/ptp_chardev.c create mode 100644 drivers/ptp/ptp_clock.c create mode 100644 drivers/ptp/ptp_private.h create mode 100644 drivers/ptp/ptp_sysfs.c create mode 100644 include/linux/ptp_clock.h create mode 100644 include/linux/ptp_clock_kernel.h diff --git a/Documentation/ABI/testing/sysfs-ptp b/Documentation/ABI/testing/sysfs-ptp new file mode 100644 index 000..d40d2b5 --- /dev/null +++ b/Documentation/ABI/testing/sysfs-ptp @@ -0,0 +1,98 @@ +What: /sys/class/ptp/ +Date: September 2010 +Contact: Richard Cochran +Description: + This directory contains files and directories + providing a standardized interface to the ancillary + features of PTP hardware clocks. + +What: /sys/class/ptp/ptpN/ +Date: September 2010 +Contact: Richard Cochran +Description: + This directory contains the attributes of the Nth PTP + hardware clock registered into the PTP class driver + subsystem. + +What: /sys/class/ptp/ptpN/clock_name +Date: September 2010 +Contact: Richard Cochran +Description: + This file contains the name of the PTP hardware clock + as a human readable string. + +What: /sys/class/ptp/ptpN/max_adjustment +Date: September 2010 +Contact: Richard Cochran +Description: + This file contains the PTP hardware clock's maximum + frequency adjustment value (a positive integer) in + parts per billion. + +What: /sys/class/ptp/ptpN/n_alarms +Date: September 2010 +Contact: Richard Cochran +Description: + This file contains the number of periodic or one shot + alarms offer by the PTP hardware clock. + +What: /sys/class/ptp/ptpN/n_external_timestamps +Date: September 2010 +Contact: Richard Cochran +Description: + This file contains the number of external timestamp + channels offered by the PTP hardware clock. + +What: /sys/class/ptp/ptpN/n_periodic_outputs +Date: September 2010 +Contact: Richard Cochran +Description: + This file contains the number of programmable periodic + output channels offered by the PTP hardware clock. + +What: /sys/class/ptp/ptpN/pps_avaiable +Date: September 2010 +Contact: Richard Cochran +Description: + This file indicates whether the PTP hardware clock + supports a Pulse Per Second to the host CPU. Reading + "1" means that the PPS is supported, while "0" means + not supported. + +What: /sys/class/ptp/ptpN/extts_enable +Date: September 2010 +Contact: Richard Cochran +Description: + This write-only file enables or disables external + timestamps. To enable external timestamps, write the + channel index followed by a "1" into the file. + To disable external timestamps, write the channel + index followed by a "0" into the file. + +What: /sys/class/ptp/ptpN/fifo +Date: September 2010 +Contact: Richard Cochran +Description: + This file provides timestamps on external
[PATCH V12 2/4] ptp: Added a clock that uses the eTSEC found on the MPC85xx.
The eTSEC includes a PTP clock with quite a few features. This patch adds
support for the basic clock adjustment functions, plus two external time
stamps, one alarm, and the PPS callback.
Signed-off-by: Richard Cochran
---
.../devicetree/bindings/net/fsl-tsec-phy.txt | 54 ++
arch/powerpc/boot/dts/mpc8313erdb.dts | 13 +
arch/powerpc/boot/dts/mpc8572ds.dts| 13 +
arch/powerpc/boot/dts/p2020ds.dts | 13 +
arch/powerpc/boot/dts/p2020rdb.dts | 13 +
drivers/net/Makefile |1 +
drivers/net/gianfar_ptp.c | 579
drivers/ptp/Kconfig| 13 +
8 files changed, 699 insertions(+), 0 deletions(-)
create mode 100644 drivers/net/gianfar_ptp.c
diff --git a/Documentation/devicetree/bindings/net/fsl-tsec-phy.txt
b/Documentation/devicetree/bindings/net/fsl-tsec-phy.txt
index edb7ae1..2c6be03 100644
--- a/Documentation/devicetree/bindings/net/fsl-tsec-phy.txt
+++ b/Documentation/devicetree/bindings/net/fsl-tsec-phy.txt
@@ -74,3 +74,57 @@ Example:
interrupt-parent = <&mpic>;
phy-handle = <&phy0>
};
+
+* Gianfar PTP clock nodes
+
+General Properties:
+
+ - compatible Should be "fsl,etsec-ptp"
+ - reg Offset and length of the register set for the device
+ - interrupts There should be at least two interrupts. Some devices
+ have as many as four PTP related interrupts.
+
+Clock Properties:
+
+ - fsl,tclk-period Timer reference clock period in nanoseconds.
+ - fsl,tmr-prsc Prescaler, divides the output clock.
+ - fsl,tmr-add Frequency compensation value.
+ - fsl,tmr-fiper1 Fixed interval period pulse generator.
+ - fsl,tmr-fiper2 Fixed interval period pulse generator.
+ - fsl,max-adj Maximum frequency adjustment in parts per billion.
+
+ These properties set the operational parameters for the PTP
+ clock. You must choose these carefully for the clock to work right.
+ Here is how to figure good values:
+
+ TimerOsc = system clock MHz
+ tclk_period = desired clock period nanoseconds
+ NominalFreq = 1000 / tclk_period MHz
+ FreqDivRatio = TimerOsc / NominalFreq (must be greater that 1.0)
+ tmr_add = ceil(2^32 / FreqDivRatio)
+ OutputClock = NominalFreq / tmr_prsc MHz
+ PulseWidth = 1 / OutputClockmicroseconds
+ FiperFreq1 = desired frequency in Hz
+ FiperDiv1= 100 * OutputClock / FiperFreq1
+ tmr_fiper1 = tmr_prsc * tclk_period * FiperDiv1 - tclk_period
+ max_adj = 10 * (FreqDivRatio - 1.0) - 1
+
+ The calculation for tmr_fiper2 is the same as for tmr_fiper1. The
+ driver expects that tmr_fiper1 will be correctly set to produce a 1
+ Pulse Per Second (PPS) signal, since this will be offered to the PPS
+ subsystem to synchronize the Linux clock.
+
+Example:
+
+ ptp_clock@24E00 {
+ compatible = "fsl,etsec-ptp";
+ reg = <0x24E00 0xB0>;
+ interrupts = <12 0x8 13 0x8>;
+ interrupt-parent = < &ipic >;
+ fsl,tclk-period = <10>;
+ fsl,tmr-prsc= <100>;
+ fsl,tmr-add = <0x99A4>;
+ fsl,tmr-fiper1 = <0x3B9AC9F6>;
+ fsl,tmr-fiper2 = <0x00018696>;
+ fsl,max-adj = <65998>;
+ };
diff --git a/arch/powerpc/boot/dts/mpc8313erdb.dts
b/arch/powerpc/boot/dts/mpc8313erdb.dts
index 183f2aa..502e17c 100644
--- a/arch/powerpc/boot/dts/mpc8313erdb.dts
+++ b/arch/powerpc/boot/dts/mpc8313erdb.dts
@@ -208,6 +208,19 @@
sleep = <&pmc 0x0030>;
};
+ ptp_clock@24E00 {
+ compatible = "fsl,etsec-ptp";
+ reg = <0x24E00 0xB0>;
+ interrupts = <12 0x8 13 0x8>;
+ interrupt-parent = < &ipic >;
+ fsl,tclk-period = <10>;
+ fsl,tmr-prsc= <100>;
+ fsl,tmr-add = <0x99A4>;
+ fsl,tmr-fiper1 = <0x3B9AC9F6>;
+ fsl,tmr-fiper2 = <0x00018696>;
+ fsl,max-adj = <65998>;
+ };
+
enet0: ethernet@24000 {
#address-cells = <1>;
#size-cells = <1>;
diff --git a/arch/powerpc/boot/dts/mpc8572ds.dts
b/arch/powerpc/boot/dts/mpc8572ds.dts
index cafc128..f6c04d2 100644
--- a/arch/powerpc/boot/dts/mpc8572ds.dts
+++ b/arch/powerpc/boot/dts/mpc8572ds.dts
@@ -324,6 +324,19 @@
};
};
+ ptp_clock@24E00 {
+
[PATCH V12 3/4] ptp: Added a clock driver for the IXP46x.
This patch adds a driver for the hardware time stamping unit found on the
IXP465. The basic clock operations and an external trigger are implemented.
Signed-off-by: Richard Cochran
Acked-by: John Stultz
---
arch/arm/mach-ixp4xx/include/mach/ixp46x_ts.h | 78 ++
drivers/net/arm/ixp4xx_eth.c | 192 ++-
drivers/ptp/Kconfig | 13 +
drivers/ptp/Makefile |1 +
drivers/ptp/ptp_ixp46x.c | 332 +
5 files changed, 613 insertions(+), 3 deletions(-)
create mode 100644 arch/arm/mach-ixp4xx/include/mach/ixp46x_ts.h
create mode 100644 drivers/ptp/ptp_ixp46x.c
diff --git a/arch/arm/mach-ixp4xx/include/mach/ixp46x_ts.h
b/arch/arm/mach-ixp4xx/include/mach/ixp46x_ts.h
new file mode 100644
index 000..292d55e
--- /dev/null
+++ b/arch/arm/mach-ixp4xx/include/mach/ixp46x_ts.h
@@ -0,0 +1,78 @@
+/*
+ * PTP 1588 clock using the IXP46X
+ *
+ * Copyright (C) 2010 OMICRON electronics GmbH
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
+ */
+
+#ifndef _IXP46X_TS_H_
+#define _IXP46X_TS_H_
+
+#define DEFAULT_ADDEND 0xF029
+#define TICKS_NS_SHIFT 4
+
+struct ixp46x_channel_ctl {
+ u32 ch_control; /* 0x40 Time Synchronization Channel Control */
+ u32 ch_event;/* 0x44 Time Synchronization Channel Event */
+ u32 tx_snap_lo; /* 0x48 Transmit Snapshot Low Register */
+ u32 tx_snap_hi; /* 0x4C Transmit Snapshot High Register */
+ u32 rx_snap_lo; /* 0x50 Receive Snapshot Low Register */
+ u32 rx_snap_hi; /* 0x54 Receive Snapshot High Register */
+ u32 src_uuid_lo; /* 0x58 Source UUID0 Low Register */
+ u32 src_uuid_hi; /* 0x5C Sequence Identifier/Source UUID0 High */
+};
+
+struct ixp46x_ts_regs {
+ u32 control; /* 0x00 Time Sync Control Register */
+ u32 event; /* 0x04 Time Sync Event Register */
+ u32 addend; /* 0x08 Time Sync Addend Register */
+ u32 accum; /* 0x0C Time Sync Accumulator Register */
+ u32 test;/* 0x10 Time Sync Test Register */
+ u32 unused; /* 0x14 */
+ u32 rsystime_lo; /* 0x18 RawSystemTime_Low Register */
+ u32 rsystime_hi; /* 0x1C RawSystemTime_High Register */
+ u32 systime_lo; /* 0x20 SystemTime_Low Register */
+ u32 systime_hi; /* 0x24 SystemTime_High Register */
+ u32 trgt_lo; /* 0x28 TargetTime_Low Register */
+ u32 trgt_hi; /* 0x2C TargetTime_High Register */
+ u32 asms_lo; /* 0x30 Auxiliary Slave Mode Snapshot Low */
+ u32 asms_hi; /* 0x34 Auxiliary Slave Mode Snapshot High */
+ u32 amms_lo; /* 0x38 Auxiliary Master Mode Snapshot Low */
+ u32 amms_hi; /* 0x3C Auxiliary Master Mode Snapshot High */
+
+ struct ixp46x_channel_ctl channel[3];
+};
+
+/* 0x00 Time Sync Control Register Bits */
+#define TSCR_AMM (1<<3)
+#define TSCR_ASM (1<<2)
+#define TSCR_TTM (1<<1)
+#define TSCR_RST (1<<0)
+
+/* 0x04 Time Sync Event Register Bits */
+#define TSER_SNM (1<<3)
+#define TSER_SNS (1<<2)
+#define TTIPEND (1<<1)
+
+/* 0x40 Time Synchronization Channel Control Register Bits */
+#define MASTER_MODE (1<<0)
+#define TIMESTAMP_ALL (1<<1)
+
+/* 0x44 Time Synchronization Channel Event Register Bits */
+#define TX_SNAPSHOT_LOCKED (1<<0)
+#define RX_SNAPSHOT_LOCKED (1<<1)
+
+#endif
diff --git a/drivers/net/arm/ixp4xx_eth.c b/drivers/net/arm/ixp4xx_eth.c
index 9eb9b98..fa08c17 100644
--- a/drivers/net/arm/ixp4xx_eth.c
+++ b/drivers/net/arm/ixp4xx_eth.c
@@ -30,9 +30,12 @@
#include
#include
#include
+#include
#include
#include
+#include
#include
+#include
#include
#include
@@ -67,6 +70,10 @@
#define RXFREE_QUEUE(port_id) (NPE_ID(port_id) + 26)
#define TXDONE_QUEUE 31
+#define PTP_SLAVE_MODE 1
+#define PTP_MASTER_MODE2
+#define PORT2CHANNEL(p)NPE_ID(p->id)
+
/* TX Control Registers */
#define TX_CNTRL0_TX_EN0x01
#define TX_CNTRL0_HALFDUPLEX 0x02
@@ -171,6 +178,8 @@ struct port {
int id; /* logical port ID */
int speed, duplex;
u8 firmware[4];
+ int hwts_tx_en;
+ int hwts_rx_en;
};
/*
[PATCH V12 4/4] ptp: Added a clock driver for the National Semiconductor PHYTER.
This patch adds support for the PTP clock found on the DP83640.
The basic clock operations and one external time stamp have
been implemented.
Signed-off-by: Richard Cochran
---
drivers/net/phy/Makefile |1 +
drivers/net/phy/dp83640.c | 1012 +
drivers/net/phy/dp83640_reg.h | 267 +++
drivers/ptp/Kconfig | 19 +
4 files changed, 1299 insertions(+), 0 deletions(-)
create mode 100644 drivers/net/phy/dp83640.c
create mode 100644 drivers/net/phy/dp83640_reg.h
diff --git a/drivers/net/phy/Makefile b/drivers/net/phy/Makefile
index 13bebab..2333215 100644
--- a/drivers/net/phy/Makefile
+++ b/drivers/net/phy/Makefile
@@ -19,6 +19,7 @@ obj-$(CONFIG_FIXED_PHY) += fixed.o
obj-$(CONFIG_MDIO_BITBANG) += mdio-bitbang.o
obj-$(CONFIG_MDIO_GPIO)+= mdio-gpio.o
obj-$(CONFIG_NATIONAL_PHY) += national.o
+obj-$(CONFIG_DP83640_PHY) += dp83640.o
obj-$(CONFIG_STE10XP) += ste10Xp.o
obj-$(CONFIG_MICREL_PHY) += micrel.o
obj-$(CONFIG_MDIO_OCTEON) += mdio-octeon.o
diff --git a/drivers/net/phy/dp83640.c b/drivers/net/phy/dp83640.c
new file mode 100644
index 000..74f751e
--- /dev/null
+++ b/drivers/net/phy/dp83640.c
@@ -0,0 +1,1012 @@
+/*
+ * Driver for the National Semiconductor DP83640 PHYTER
+ *
+ * Copyright (C) 2010 OMICRON electronics GmbH
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
+ */
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+#include "dp83640_reg.h"
+
+#define DP83640_PHY_ID 0x20005ce1
+#define PAGESEL0x13
+#define LAYER4 0x02
+#define LAYER2 0x01
+#define MAX_RXTS 4
+#define MAX_TXTS 4
+#define N_EXT_TS 1
+#define PSF_PTPVER 2
+#define PSF_EVNT 0x4000
+#define PSF_RX 0x2000
+#define PSF_TX 0x1000
+#define EXT_EVENT 1
+#define EXT_GPIO 1
+#define CAL_EVENT 2
+#define CAL_GPIO 9
+#define CAL_TRIGGER2
+
+/* phyter seems to miss the mark by 16 ns */
+#define ADJTIME_FIX16
+
+#if defined(__BIG_ENDIAN)
+#define ENDIAN_FLAG0
+#elif defined(__LITTLE_ENDIAN)
+#define ENDIAN_FLAGPSF_ENDIAN
+#endif
+
+#define SKB_PTP_TYPE(__skb) (*(unsigned int *)((__skb)->cb))
+
+struct phy_rxts {
+ u16 ns_lo; /* ns[15:0] */
+ u16 ns_hi; /* overflow[1:0], ns[29:16] */
+ u16 sec_lo; /* sec[15:0] */
+ u16 sec_hi; /* sec[31:16] */
+ u16 seqid; /* sequenceId[15:0] */
+ u16 msgtype; /* messageType[3:0], hash[11:0] */
+};
+
+struct phy_txts {
+ u16 ns_lo; /* ns[15:0] */
+ u16 ns_hi; /* overflow[1:0], ns[29:16] */
+ u16 sec_lo; /* sec[15:0] */
+ u16 sec_hi; /* sec[31:16] */
+};
+
+struct rxts {
+ struct list_head list;
+ unsigned long tmo;
+ u64 ns;
+ u16 seqid;
+ u8 msgtype;
+ u16 hash;
+};
+
+struct dp83640_clock;
+
+struct dp83640_private {
+ struct list_head list;
+ struct dp83640_clock *clock;
+ struct phy_device *phydev;
+ struct work_struct ts_work;
+ int hwts_tx_en;
+ int hwts_rx_en;
+ int layer;
+ int version;
+ /* remember state of cfg0 during calibration */
+ int cfg0;
+ /* remember the last event time stamp */
+ struct phy_txts edata;
+ /* list of rx timestamps */
+ struct list_head rxts;
+ struct list_head rxpool;
+ struct rxts rx_pool_data[MAX_RXTS];
+ /* protects above three fields from concurrent access */
+ spinlock_t rx_lock;
+ /* queues of incoming and outgoing packets */
+ struct sk_buff_head rx_queue;
+ struct sk_buff_head tx_queue;
+};
+
+struct dp83640_clock {
+ /* protects extended registers from concurrent access */
+ struct mutex extreg_lock;
+ /* remembers which page was last selected */
+ int page;
+ /* our advertised capabilities */
+ struct ptp_clock_info caps;
+ /* the one phyter from which we shall read */
+ struct dp83640_private *chosen;
+ /* list of the other attached phyters, not chosen */
+ struct list_head phylist;
+ /* reference to our PTP hardware clock */
+ struct ptp_clock *ptp_clock;
+};
+
+/* globals
Re: [PATCH V12 0/4] ptp: IEEE 1588 hardware clock support
On Mon, Feb 28, 2011 at 08:57:03AM +0100, Richard Cochran wrote: > * PHC Patch ChangeLog > ** v12 > *** gianfar_ptp >- fixed up device tree >- inlined the header file >- use platform_ calls instead of deprecated of_ calls >- removed static global single instance >- removed John Stultz's ack from this patch @Thomas and John: Can I get your acks on the remaining patches? Can this be merged for 2.6.39? Thanks, Richard ___ Linuxppc-dev mailing list Linuxppc-dev@lists.ozlabs.org https://lists.ozlabs.org/listinfo/linuxppc-dev
Re: [PATCH V12 0/4] ptp: IEEE 1588 hardware clock support
For all those interested in the user space aspect, I have posted some patches to ptpd project showing how the API works. https://sourceforge.net/tracker/?group_id=139814&atid=744634 3225599 [PATCH 1/3] Convert to POSIX clock API. 3225603 [PATCH 2/3] Adapted to use the Linux PTP Hardware Clock API. 3225607 [PATCH 3/3] Adapted to use the newer SO_TIMESTAMPING Linux API. Enjoy, Richard ___ Linuxppc-dev mailing list Linuxppc-dev@lists.ozlabs.org https://lists.ozlabs.org/listinfo/linuxppc-dev
[PATCH] powerpc: add clock_adjtime for powerpc
This patch adds the clock_adjtime system call to the powerpc architecture. The call was introduced in f1f1d5ebd10ffa4242bce7a90a56a222d6b7bc77 Signed-off-by: Richard Cochran --- arch/powerpc/include/asm/systbl.h |1 + arch/powerpc/include/asm/unistd.h |3 ++- 2 files changed, 3 insertions(+), 1 deletions(-) diff --git a/arch/powerpc/include/asm/systbl.h b/arch/powerpc/include/asm/systbl.h index aa0f1eb..6a1152c 100644 --- a/arch/powerpc/include/asm/systbl.h +++ b/arch/powerpc/include/asm/systbl.h @@ -348,3 +348,4 @@ COMPAT_SYS_SPU(sendmsg) COMPAT_SYS_SPU(recvmsg) COMPAT_SYS_SPU(recvmmsg) SYSCALL_SPU(accept4) +COMPAT_SYS_SPU(clock_adjtime) diff --git a/arch/powerpc/include/asm/unistd.h b/arch/powerpc/include/asm/unistd.h index 6151937..386de07 100644 --- a/arch/powerpc/include/asm/unistd.h +++ b/arch/powerpc/include/asm/unistd.h @@ -367,10 +367,11 @@ #define __NR_recvmsg 342 #define __NR_recvmmsg 343 #define __NR_accept4 344 +#define __NR_clock_adjtime 345 #ifdef __KERNEL__ -#define __NR_syscalls 345 +#define __NR_syscalls 346 #define __NR__exit __NR_exit #define NR_syscalls__NR_syscalls -- 1.7.0.4 ___ Linuxppc-dev mailing list Linuxppc-dev@lists.ozlabs.org https://lists.ozlabs.org/listinfo/linuxppc-dev
Re: [PATCH] powerpc: add clock_adjtime for powerpc
On Thu, Mar 24, 2011 at 04:05:17PM +0100, Richard Cochran wrote: > This patch adds the clock_adjtime system call to the powerpc architecture. Never mind this patch. Stephen Rothwell already posted a patch on linuxppc-dev adding this syscall eariler today. Thanks, Richard ___ Linuxppc-dev mailing list Linuxppc-dev@lists.ozlabs.org https://lists.ozlabs.org/listinfo/linuxppc-dev
Re: [PATCH V12 1/4] ptp: Added a brand new class driver for ptp clocks.
On Wed, Mar 23, 2011 at 02:19:20PM -0700, John Stultz wrote:
> On Mon, 2011-02-28 at 08:57 +0100, Richard Cochran wrote:
> > +++ b/drivers/ptp/ptp_clock.c
> > @@ -0,0 +1,320 @@
> [snip]
> > +static void enqueue_external_timestamp(struct timestamp_event_queue *queue,
> > + struct ptp_clock_event *src)
> > +{
> > + struct ptp_extts_event *dst;
> > + unsigned long flags;
> > + u32 remainder;
> > +
> > + dst = &queue->buf[queue->tail];
>
> Doesn't the lock need to happen before you access the
> queue->buf[queue->tail] ?
>
> For example: What happens if two cpus enter the function at the same
> time, both get the same tail index, one overwrite the other's data, then
> both take turns bumping up the tail pointer?
Yes, thanks for that catch.
> > +struct timestamp_event_queue {
> > + struct ptp_extts_event buf[PTP_MAX_TIMESTAMPS];
> > + int head;
> > + int tail;
> > + spinlock_t lock;
> > +};
> > +
> > +struct ptp_clock {
> > + struct posix_clock clock;
> > + struct device *dev;
> > + struct ptp_clock_info *info;
> > + dev_t devid;
> > + int index; /* index into clocks.map */
> > + struct pps_device *pps_source;
> > + struct timestamp_event_queue tsevq; /* simple fifo for time stamps */
> > + struct mutex tsevq_mux; /* one process at a time reading the fifo */
> > + wait_queue_head_t tsev_wq;
> > +};
> > +
> > +static inline int queue_cnt(struct timestamp_event_queue *q)
> > +{
> > + int cnt = q->tail - q->head;
> > + return cnt < 0 ? PTP_MAX_TIMESTAMPS + cnt : cnt;
> > +}
>
> q->tail and head access probably need to happen only when locked.
>
> So probably need a comment that queue_cnt must be called only when
> holding the proper lock.
In this case, calling without a lock is allowed. However, I'll add
comment like the following.
* The function queue_cnt() is safe for readers to call without
* holding q->lock. Readers use this function to verify that the queue
* is nonempty before proceeding with a dequeue operation. The fact
* that a writer might concurrently increment the tail does not
* matter, since the queue remains nonempty nonetheless.
Thanks for your feedback,
Richard
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Re: [PATCH V12 2/4] ptp: Added a clock that uses the eTSEC found on the MPC85xx.
On Wed, Mar 23, 2011 at 02:30:04PM -0700, John Stultz wrote: > On Mon, 2011-02-28 at 08:57 +0100, Richard Cochran wrote: > > +/* > > + * Register access functions > > + */ > > So what are the locking rules on the functions below? I assume the > etsects->lock needs to be held prior to calling, so that should be made > explicit in a comment. Yes, you are right. I'll add comments. > > + gfar_write(&etsects->regs->tmr_ctrl, tmr_ctrl); > > + gfar_write(&etsects->regs->tmr_add,etsects->tmr_add); > > + gfar_write(&etsects->regs->tmr_prsc, etsects->tmr_prsc); > > + gfar_write(&etsects->regs->tmr_fiper1, etsects->tmr_fiper1); > > + gfar_write(&etsects->regs->tmr_fiper2, etsects->tmr_fiper2); > > + set_alarm(etsects); > > + gfar_write(&etsects->regs->tmr_ctrl, tmr_ctrl|FS|RTPE|TE); > > Does any of the above need a lock should an irq land in the middle of > the writes? Since these interrupts first must be enabled, I think it unlikely that an IRQ could occur. However, it can't hurt to add the lock, either. Thanks, Richard ___ Linuxppc-dev mailing list Linuxppc-dev@lists.ozlabs.org https://lists.ozlabs.org/listinfo/linuxppc-dev
Re: [PATCH V12 4/4] ptp: Added a clock driver for the National Semiconductor PHYTER.
On Wed, Mar 23, 2011 at 02:46:25PM -0700, John Stultz wrote:
> On Mon, 2011-02-28 at 08:58 +0100, Richard Cochran wrote:
> > +static int tdr_write(int bc, struct phy_device *dev,
> > +const struct timespec *ts, u16 cmd)
> > +{
> > + ext_write(bc, dev, PAGE4, PTP_TDR, ts->tv_nsec & 0x);/* ns[15:0] */
> > + ext_write(bc, dev, PAGE4, PTP_TDR, ts->tv_nsec >> 16); /* ns[31:16] */
> > + ext_write(bc, dev, PAGE4, PTP_TDR, ts->tv_sec & 0x); /* sec[15:0] */
> > + ext_write(bc, dev, PAGE4, PTP_TDR, ts->tv_sec >> 16);/* sec[31:16]*/
> > +
> > + ext_write(bc, dev, PAGE4, PTP_CTL, cmd);
> > +
> > + return 0;
> > +}
>
> The above needs to hold the extreg_lock, and should be commented as
> such.
Okay, will do.
> And again, the function names are sort of generic, and could use a
> dp83640_ prefix or something.
So, I will rename the IXP functions in the other driver to make them
more unique, but in this case I really prefer to keep the short names
for the sake of readability.
Just about every operation on this PHY requires four 16-bit writes,
where each write can really mean two writes, with the first one to set
a "page" register for the following write.
Keeping the tabular style (shown above) makes it much more clear what
is going on, IMHO. If the function names become longer, that would
force line breaks and spoil the nice formatting.
Also, these names are not in use anywhere else in the kernel's eight
million LOC.
Thanks,
Richard
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[PATCH V13 0/4] ptp: IEEE 1588 hardware clock support
* Introduction The aim of this patch set is to add support for PTP Hardware Clocks (PHCs) into the Linux kernel. The patch series builds upon the dynamic posix clock work appearing in kernel version 2.6.39. Support for obtaining timestamps from a PHC already exists via the SO_TIMESTAMPING socket option, integrated in kernel version 2.6.30. This patch set completes the picture by allow user space programs to adjust the PHC and to control its ancillary features. * Why all the CCs? - One driver is for PowerPC, and adds device tree stuff. - One driver is for the ARM Xscale IXP465. * PHC Patch ChangeLog ** v13 *** Incorporate v12 review from Andrew Morton - external timestamp read: mutex was held unnecessarily long - external timestamp read: require size to be multiple of sizeof(extts) - replaced 'uint' with 'unsigned int' in poll function - replaced empty release function with NULL function pointer *** Incorporate v12 review from John Stultz - added comment to explain the ppm to ppb conversion - commented the locking rules for the queue_cnt() function - commented the ppb to ppm conversion in the example program - fixed incomplete locking of external timestamp queue - gianfar, dp83640: comment on the locking rules - gianfar: fixed unlikely unprotected register access in probe() - ixp4xx: gave some private functions more unique names * Previous Discussions - [V12] http://lkml.org/lkml/2011/2/28/53 - [V11] http://lkml.org/lkml/2011/2/23/107 - [V10] http://lkml.org/lkml/2011/1/27/71 Richard Cochran (4): ptp: Added a brand new class driver for ptp clocks. ptp: Added a clock that uses the eTSEC found on the MPC85xx. ptp: Added a clock driver for the IXP46x. ptp: Added a clock driver for the National Semiconductor PHYTER. Documentation/ABI/testing/sysfs-ptp| 98 ++ .../devicetree/bindings/net/fsl-tsec-phy.txt | 54 + Documentation/ptp/ptp.txt | 89 ++ Documentation/ptp/testptp.c| 368 +++ Documentation/ptp/testptp.mk | 33 + arch/arm/mach-ixp4xx/include/mach/ixp46x_ts.h | 78 ++ arch/powerpc/boot/dts/mpc8313erdb.dts | 13 + arch/powerpc/boot/dts/mpc8572ds.dts| 13 + arch/powerpc/boot/dts/p2020ds.dts | 13 + arch/powerpc/boot/dts/p2020rdb.dts | 13 + drivers/Kconfig|2 + drivers/Makefile |1 + drivers/net/Makefile |1 + drivers/net/arm/ixp4xx_eth.c | 192 - drivers/net/gianfar_ptp.c | 588 +++ drivers/net/phy/Makefile |1 + drivers/net/phy/dp83640.c | 1015 drivers/net/phy/dp83640_reg.h | 267 + drivers/ptp/Kconfig| 75 ++ drivers/ptp/Makefile |7 + drivers/ptp/ptp_chardev.c | 155 +++ drivers/ptp/ptp_clock.c| 339 +++ drivers/ptp/ptp_ixp46x.c | 332 +++ drivers/ptp/ptp_private.h | 91 ++ drivers/ptp/ptp_sysfs.c| 230 + include/linux/Kbuild |1 + include/linux/ptp_clock.h | 84 ++ include/linux/ptp_clock_kernel.h | 139 +++ 28 files changed, 4289 insertions(+), 3 deletions(-) create mode 100644 Documentation/ABI/testing/sysfs-ptp create mode 100644 Documentation/ptp/ptp.txt create mode 100644 Documentation/ptp/testptp.c create mode 100644 Documentation/ptp/testptp.mk create mode 100644 arch/arm/mach-ixp4xx/include/mach/ixp46x_ts.h create mode 100644 drivers/net/gianfar_ptp.c create mode 100644 drivers/net/phy/dp83640.c create mode 100644 drivers/net/phy/dp83640_reg.h create mode 100644 drivers/ptp/Kconfig create mode 100644 drivers/ptp/Makefile create mode 100644 drivers/ptp/ptp_chardev.c create mode 100644 drivers/ptp/ptp_clock.c create mode 100644 drivers/ptp/ptp_ixp46x.c create mode 100644 drivers/ptp/ptp_private.h create mode 100644 drivers/ptp/ptp_sysfs.c create mode 100644 include/linux/ptp_clock.h create mode 100644 include/linux/ptp_clock_kernel.h ___ Linuxppc-dev mailing list Linuxppc-dev@lists.ozlabs.org https://lists.ozlabs.org/listinfo/linuxppc-dev
[PATCH V13 1/4] ptp: Added a brand new class driver for ptp clocks.
This patch adds an infrastructure for hardware clocks that implement IEEE 1588, the Precision Time Protocol (PTP). A class driver offers a registration method to particular hardware clock drivers. Each clock is presented as a standard POSIX clock. The ancillary clock features are exposed in two different ways, via the sysfs and by a character device. Signed-off-by: Richard Cochran --- Documentation/ABI/testing/sysfs-ptp | 98 + Documentation/ptp/ptp.txt | 89 + Documentation/ptp/testptp.c | 368 +++ Documentation/ptp/testptp.mk| 33 +++ drivers/Kconfig |2 + drivers/Makefile|1 + drivers/ptp/Kconfig | 30 +++ drivers/ptp/Makefile|6 + drivers/ptp/ptp_chardev.c | 155 +++ drivers/ptp/ptp_clock.c | 339 drivers/ptp/ptp_private.h | 91 + drivers/ptp/ptp_sysfs.c | 230 ++ include/linux/Kbuild|1 + include/linux/ptp_clock.h | 84 include/linux/ptp_clock_kernel.h| 139 + 15 files changed, 1666 insertions(+), 0 deletions(-) create mode 100644 Documentation/ABI/testing/sysfs-ptp create mode 100644 Documentation/ptp/ptp.txt create mode 100644 Documentation/ptp/testptp.c create mode 100644 Documentation/ptp/testptp.mk create mode 100644 drivers/ptp/Kconfig create mode 100644 drivers/ptp/Makefile create mode 100644 drivers/ptp/ptp_chardev.c create mode 100644 drivers/ptp/ptp_clock.c create mode 100644 drivers/ptp/ptp_private.h create mode 100644 drivers/ptp/ptp_sysfs.c create mode 100644 include/linux/ptp_clock.h create mode 100644 include/linux/ptp_clock_kernel.h diff --git a/Documentation/ABI/testing/sysfs-ptp b/Documentation/ABI/testing/sysfs-ptp new file mode 100644 index 000..d40d2b5 --- /dev/null +++ b/Documentation/ABI/testing/sysfs-ptp @@ -0,0 +1,98 @@ +What: /sys/class/ptp/ +Date: September 2010 +Contact: Richard Cochran +Description: + This directory contains files and directories + providing a standardized interface to the ancillary + features of PTP hardware clocks. + +What: /sys/class/ptp/ptpN/ +Date: September 2010 +Contact: Richard Cochran +Description: + This directory contains the attributes of the Nth PTP + hardware clock registered into the PTP class driver + subsystem. + +What: /sys/class/ptp/ptpN/clock_name +Date: September 2010 +Contact: Richard Cochran +Description: + This file contains the name of the PTP hardware clock + as a human readable string. + +What: /sys/class/ptp/ptpN/max_adjustment +Date: September 2010 +Contact: Richard Cochran +Description: + This file contains the PTP hardware clock's maximum + frequency adjustment value (a positive integer) in + parts per billion. + +What: /sys/class/ptp/ptpN/n_alarms +Date: September 2010 +Contact: Richard Cochran +Description: + This file contains the number of periodic or one shot + alarms offer by the PTP hardware clock. + +What: /sys/class/ptp/ptpN/n_external_timestamps +Date: September 2010 +Contact: Richard Cochran +Description: + This file contains the number of external timestamp + channels offered by the PTP hardware clock. + +What: /sys/class/ptp/ptpN/n_periodic_outputs +Date: September 2010 +Contact: Richard Cochran +Description: + This file contains the number of programmable periodic + output channels offered by the PTP hardware clock. + +What: /sys/class/ptp/ptpN/pps_avaiable +Date: September 2010 +Contact: Richard Cochran +Description: + This file indicates whether the PTP hardware clock + supports a Pulse Per Second to the host CPU. Reading + "1" means that the PPS is supported, while "0" means + not supported. + +What: /sys/class/ptp/ptpN/extts_enable +Date: September 2010 +Contact: Richard Cochran +Description: + This write-only file enables or disables external + timestamps. To enable external timestamps, write the + channel index followed by a "1" into the file. + To disable external timestamps, write the channel + index followed by a "0" into the file. + +What: /sys/class/ptp/ptpN/fifo +Date: September 2010 +Contact: Richard Cochran +Description: + This file provides timestamps on external events,
[PATCH V13 2/4] ptp: Added a clock that uses the eTSEC found on the MPC85xx.
The eTSEC includes a PTP clock with quite a few features. This patch adds
support for the basic clock adjustment functions, plus two external time
stamps, one alarm, and the PPS callback.
Signed-off-by: Richard Cochran
---
.../devicetree/bindings/net/fsl-tsec-phy.txt | 54 ++
arch/powerpc/boot/dts/mpc8313erdb.dts | 13 +
arch/powerpc/boot/dts/mpc8572ds.dts| 13 +
arch/powerpc/boot/dts/p2020ds.dts | 13 +
arch/powerpc/boot/dts/p2020rdb.dts | 13 +
drivers/net/Makefile |1 +
drivers/net/gianfar_ptp.c | 588
drivers/ptp/Kconfig| 13 +
8 files changed, 708 insertions(+), 0 deletions(-)
create mode 100644 drivers/net/gianfar_ptp.c
diff --git a/Documentation/devicetree/bindings/net/fsl-tsec-phy.txt
b/Documentation/devicetree/bindings/net/fsl-tsec-phy.txt
index edb7ae1..2c6be03 100644
--- a/Documentation/devicetree/bindings/net/fsl-tsec-phy.txt
+++ b/Documentation/devicetree/bindings/net/fsl-tsec-phy.txt
@@ -74,3 +74,57 @@ Example:
interrupt-parent = <&mpic>;
phy-handle = <&phy0>
};
+
+* Gianfar PTP clock nodes
+
+General Properties:
+
+ - compatible Should be "fsl,etsec-ptp"
+ - reg Offset and length of the register set for the device
+ - interrupts There should be at least two interrupts. Some devices
+ have as many as four PTP related interrupts.
+
+Clock Properties:
+
+ - fsl,tclk-period Timer reference clock period in nanoseconds.
+ - fsl,tmr-prsc Prescaler, divides the output clock.
+ - fsl,tmr-add Frequency compensation value.
+ - fsl,tmr-fiper1 Fixed interval period pulse generator.
+ - fsl,tmr-fiper2 Fixed interval period pulse generator.
+ - fsl,max-adj Maximum frequency adjustment in parts per billion.
+
+ These properties set the operational parameters for the PTP
+ clock. You must choose these carefully for the clock to work right.
+ Here is how to figure good values:
+
+ TimerOsc = system clock MHz
+ tclk_period = desired clock period nanoseconds
+ NominalFreq = 1000 / tclk_period MHz
+ FreqDivRatio = TimerOsc / NominalFreq (must be greater that 1.0)
+ tmr_add = ceil(2^32 / FreqDivRatio)
+ OutputClock = NominalFreq / tmr_prsc MHz
+ PulseWidth = 1 / OutputClockmicroseconds
+ FiperFreq1 = desired frequency in Hz
+ FiperDiv1= 100 * OutputClock / FiperFreq1
+ tmr_fiper1 = tmr_prsc * tclk_period * FiperDiv1 - tclk_period
+ max_adj = 10 * (FreqDivRatio - 1.0) - 1
+
+ The calculation for tmr_fiper2 is the same as for tmr_fiper1. The
+ driver expects that tmr_fiper1 will be correctly set to produce a 1
+ Pulse Per Second (PPS) signal, since this will be offered to the PPS
+ subsystem to synchronize the Linux clock.
+
+Example:
+
+ ptp_clock@24E00 {
+ compatible = "fsl,etsec-ptp";
+ reg = <0x24E00 0xB0>;
+ interrupts = <12 0x8 13 0x8>;
+ interrupt-parent = < &ipic >;
+ fsl,tclk-period = <10>;
+ fsl,tmr-prsc= <100>;
+ fsl,tmr-add = <0x99A4>;
+ fsl,tmr-fiper1 = <0x3B9AC9F6>;
+ fsl,tmr-fiper2 = <0x00018696>;
+ fsl,max-adj = <65998>;
+ };
diff --git a/arch/powerpc/boot/dts/mpc8313erdb.dts
b/arch/powerpc/boot/dts/mpc8313erdb.dts
index 183f2aa..502e17c 100644
--- a/arch/powerpc/boot/dts/mpc8313erdb.dts
+++ b/arch/powerpc/boot/dts/mpc8313erdb.dts
@@ -208,6 +208,19 @@
sleep = <&pmc 0x0030>;
};
+ ptp_clock@24E00 {
+ compatible = "fsl,etsec-ptp";
+ reg = <0x24E00 0xB0>;
+ interrupts = <12 0x8 13 0x8>;
+ interrupt-parent = < &ipic >;
+ fsl,tclk-period = <10>;
+ fsl,tmr-prsc= <100>;
+ fsl,tmr-add = <0x99A4>;
+ fsl,tmr-fiper1 = <0x3B9AC9F6>;
+ fsl,tmr-fiper2 = <0x00018696>;
+ fsl,max-adj = <65998>;
+ };
+
enet0: ethernet@24000 {
#address-cells = <1>;
#size-cells = <1>;
diff --git a/arch/powerpc/boot/dts/mpc8572ds.dts
b/arch/powerpc/boot/dts/mpc8572ds.dts
index cafc128..f6c04d2 100644
--- a/arch/powerpc/boot/dts/mpc8572ds.dts
+++ b/arch/powerpc/boot/dts/mpc8572ds.dts
@@ -324,6 +324,19 @@
};
};
+ ptp_clock@24E00 {
+
[PATCH V13 3/4] ptp: Added a clock driver for the IXP46x.
This patch adds a driver for the hardware time stamping unit found on the
IXP465. The basic clock operations and an external trigger are implemented.
Signed-off-by: Richard Cochran
Acked-by: John Stultz
---
arch/arm/mach-ixp4xx/include/mach/ixp46x_ts.h | 78 ++
drivers/net/arm/ixp4xx_eth.c | 192 ++-
drivers/ptp/Kconfig | 13 +
drivers/ptp/Makefile |1 +
drivers/ptp/ptp_ixp46x.c | 332 +
5 files changed, 613 insertions(+), 3 deletions(-)
create mode 100644 arch/arm/mach-ixp4xx/include/mach/ixp46x_ts.h
create mode 100644 drivers/ptp/ptp_ixp46x.c
diff --git a/arch/arm/mach-ixp4xx/include/mach/ixp46x_ts.h
b/arch/arm/mach-ixp4xx/include/mach/ixp46x_ts.h
new file mode 100644
index 000..292d55e
--- /dev/null
+++ b/arch/arm/mach-ixp4xx/include/mach/ixp46x_ts.h
@@ -0,0 +1,78 @@
+/*
+ * PTP 1588 clock using the IXP46X
+ *
+ * Copyright (C) 2010 OMICRON electronics GmbH
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
+ */
+
+#ifndef _IXP46X_TS_H_
+#define _IXP46X_TS_H_
+
+#define DEFAULT_ADDEND 0xF029
+#define TICKS_NS_SHIFT 4
+
+struct ixp46x_channel_ctl {
+ u32 ch_control; /* 0x40 Time Synchronization Channel Control */
+ u32 ch_event;/* 0x44 Time Synchronization Channel Event */
+ u32 tx_snap_lo; /* 0x48 Transmit Snapshot Low Register */
+ u32 tx_snap_hi; /* 0x4C Transmit Snapshot High Register */
+ u32 rx_snap_lo; /* 0x50 Receive Snapshot Low Register */
+ u32 rx_snap_hi; /* 0x54 Receive Snapshot High Register */
+ u32 src_uuid_lo; /* 0x58 Source UUID0 Low Register */
+ u32 src_uuid_hi; /* 0x5C Sequence Identifier/Source UUID0 High */
+};
+
+struct ixp46x_ts_regs {
+ u32 control; /* 0x00 Time Sync Control Register */
+ u32 event; /* 0x04 Time Sync Event Register */
+ u32 addend; /* 0x08 Time Sync Addend Register */
+ u32 accum; /* 0x0C Time Sync Accumulator Register */
+ u32 test;/* 0x10 Time Sync Test Register */
+ u32 unused; /* 0x14 */
+ u32 rsystime_lo; /* 0x18 RawSystemTime_Low Register */
+ u32 rsystime_hi; /* 0x1C RawSystemTime_High Register */
+ u32 systime_lo; /* 0x20 SystemTime_Low Register */
+ u32 systime_hi; /* 0x24 SystemTime_High Register */
+ u32 trgt_lo; /* 0x28 TargetTime_Low Register */
+ u32 trgt_hi; /* 0x2C TargetTime_High Register */
+ u32 asms_lo; /* 0x30 Auxiliary Slave Mode Snapshot Low */
+ u32 asms_hi; /* 0x34 Auxiliary Slave Mode Snapshot High */
+ u32 amms_lo; /* 0x38 Auxiliary Master Mode Snapshot Low */
+ u32 amms_hi; /* 0x3C Auxiliary Master Mode Snapshot High */
+
+ struct ixp46x_channel_ctl channel[3];
+};
+
+/* 0x00 Time Sync Control Register Bits */
+#define TSCR_AMM (1<<3)
+#define TSCR_ASM (1<<2)
+#define TSCR_TTM (1<<1)
+#define TSCR_RST (1<<0)
+
+/* 0x04 Time Sync Event Register Bits */
+#define TSER_SNM (1<<3)
+#define TSER_SNS (1<<2)
+#define TTIPEND (1<<1)
+
+/* 0x40 Time Synchronization Channel Control Register Bits */
+#define MASTER_MODE (1<<0)
+#define TIMESTAMP_ALL (1<<1)
+
+/* 0x44 Time Synchronization Channel Event Register Bits */
+#define TX_SNAPSHOT_LOCKED (1<<0)
+#define RX_SNAPSHOT_LOCKED (1<<1)
+
+#endif
diff --git a/drivers/net/arm/ixp4xx_eth.c b/drivers/net/arm/ixp4xx_eth.c
index 9eb9b98..c56fcb6 100644
--- a/drivers/net/arm/ixp4xx_eth.c
+++ b/drivers/net/arm/ixp4xx_eth.c
@@ -30,9 +30,12 @@
#include
#include
#include
+#include
#include
#include
+#include
#include
+#include
#include
#include
@@ -67,6 +70,10 @@
#define RXFREE_QUEUE(port_id) (NPE_ID(port_id) + 26)
#define TXDONE_QUEUE 31
+#define PTP_SLAVE_MODE 1
+#define PTP_MASTER_MODE2
+#define PORT2CHANNEL(p)NPE_ID(p->id)
+
/* TX Control Registers */
#define TX_CNTRL0_TX_EN0x01
#define TX_CNTRL0_HALFDUPLEX 0x02
@@ -171,6 +178,8 @@ struct port {
int id; /* logical port ID */
int speed, duplex;
u8 firmware[4];
+ int hwts_tx_en;
+ int hwts_rx_en;
};
/*
[PATCH V13 4/4] ptp: Added a clock driver for the National Semiconductor PHYTER.
This patch adds support for the PTP clock found on the DP83640.
The basic clock operations and one external time stamp have
been implemented.
Signed-off-by: Richard Cochran
---
drivers/net/phy/Makefile |1 +
drivers/net/phy/dp83640.c | 1015 +
drivers/net/phy/dp83640_reg.h | 267 +++
drivers/ptp/Kconfig | 19 +
4 files changed, 1302 insertions(+), 0 deletions(-)
create mode 100644 drivers/net/phy/dp83640.c
create mode 100644 drivers/net/phy/dp83640_reg.h
diff --git a/drivers/net/phy/Makefile b/drivers/net/phy/Makefile
index 13bebab..2333215 100644
--- a/drivers/net/phy/Makefile
+++ b/drivers/net/phy/Makefile
@@ -19,6 +19,7 @@ obj-$(CONFIG_FIXED_PHY) += fixed.o
obj-$(CONFIG_MDIO_BITBANG) += mdio-bitbang.o
obj-$(CONFIG_MDIO_GPIO)+= mdio-gpio.o
obj-$(CONFIG_NATIONAL_PHY) += national.o
+obj-$(CONFIG_DP83640_PHY) += dp83640.o
obj-$(CONFIG_STE10XP) += ste10Xp.o
obj-$(CONFIG_MICREL_PHY) += micrel.o
obj-$(CONFIG_MDIO_OCTEON) += mdio-octeon.o
diff --git a/drivers/net/phy/dp83640.c b/drivers/net/phy/dp83640.c
new file mode 100644
index 000..61d682d
--- /dev/null
+++ b/drivers/net/phy/dp83640.c
@@ -0,0 +1,1015 @@
+/*
+ * Driver for the National Semiconductor DP83640 PHYTER
+ *
+ * Copyright (C) 2010 OMICRON electronics GmbH
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
+ */
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+#include "dp83640_reg.h"
+
+#define DP83640_PHY_ID 0x20005ce1
+#define PAGESEL0x13
+#define LAYER4 0x02
+#define LAYER2 0x01
+#define MAX_RXTS 4
+#define MAX_TXTS 4
+#define N_EXT_TS 1
+#define PSF_PTPVER 2
+#define PSF_EVNT 0x4000
+#define PSF_RX 0x2000
+#define PSF_TX 0x1000
+#define EXT_EVENT 1
+#define EXT_GPIO 1
+#define CAL_EVENT 2
+#define CAL_GPIO 9
+#define CAL_TRIGGER2
+
+/* phyter seems to miss the mark by 16 ns */
+#define ADJTIME_FIX16
+
+#if defined(__BIG_ENDIAN)
+#define ENDIAN_FLAG0
+#elif defined(__LITTLE_ENDIAN)
+#define ENDIAN_FLAGPSF_ENDIAN
+#endif
+
+#define SKB_PTP_TYPE(__skb) (*(unsigned int *)((__skb)->cb))
+
+struct phy_rxts {
+ u16 ns_lo; /* ns[15:0] */
+ u16 ns_hi; /* overflow[1:0], ns[29:16] */
+ u16 sec_lo; /* sec[15:0] */
+ u16 sec_hi; /* sec[31:16] */
+ u16 seqid; /* sequenceId[15:0] */
+ u16 msgtype; /* messageType[3:0], hash[11:0] */
+};
+
+struct phy_txts {
+ u16 ns_lo; /* ns[15:0] */
+ u16 ns_hi; /* overflow[1:0], ns[29:16] */
+ u16 sec_lo; /* sec[15:0] */
+ u16 sec_hi; /* sec[31:16] */
+};
+
+struct rxts {
+ struct list_head list;
+ unsigned long tmo;
+ u64 ns;
+ u16 seqid;
+ u8 msgtype;
+ u16 hash;
+};
+
+struct dp83640_clock;
+
+struct dp83640_private {
+ struct list_head list;
+ struct dp83640_clock *clock;
+ struct phy_device *phydev;
+ struct work_struct ts_work;
+ int hwts_tx_en;
+ int hwts_rx_en;
+ int layer;
+ int version;
+ /* remember state of cfg0 during calibration */
+ int cfg0;
+ /* remember the last event time stamp */
+ struct phy_txts edata;
+ /* list of rx timestamps */
+ struct list_head rxts;
+ struct list_head rxpool;
+ struct rxts rx_pool_data[MAX_RXTS];
+ /* protects above three fields from concurrent access */
+ spinlock_t rx_lock;
+ /* queues of incoming and outgoing packets */
+ struct sk_buff_head rx_queue;
+ struct sk_buff_head tx_queue;
+};
+
+struct dp83640_clock {
+ /* protects extended registers from concurrent access */
+ struct mutex extreg_lock;
+ /* remembers which page was last selected */
+ int page;
+ /* our advertised capabilities */
+ struct ptp_clock_info caps;
+ /* the one phyter from which we shall read */
+ struct dp83640_private *chosen;
+ /* list of the other attached phyters, not chosen */
+ struct list_head phylist;
+ /* reference to our PTP hardware clock */
+ struct ptp_clock *ptp_clock;
+};
+
+/* globals
[PATCH] powerpc: rename get_irq_desc_data and get_irq_desc_chip
These two functions disappeared in commit
0c6f8a8b917ad361319c8ace3e9f28e69bfdb4c1
"genirq: Remove compat code"
but they still exist in qe_ic.h.
This patch renames the function to their new names.
Signed-off-by: Richard Cochran
---
arch/powerpc/include/asm/qe_ic.h | 16
1 files changed, 8 insertions(+), 8 deletions(-)
diff --git a/arch/powerpc/include/asm/qe_ic.h b/arch/powerpc/include/asm/qe_ic.h
index 9e2cb20..f706164 100644
--- a/arch/powerpc/include/asm/qe_ic.h
+++ b/arch/powerpc/include/asm/qe_ic.h
@@ -81,7 +81,7 @@ int qe_ic_set_high_priority(unsigned int virq, unsigned int
priority, int high);
static inline void qe_ic_cascade_low_ipic(unsigned int irq,
struct irq_desc *desc)
{
- struct qe_ic *qe_ic = get_irq_desc_data(desc);
+ struct qe_ic *qe_ic = irq_desc_get_handler_data(desc);
unsigned int cascade_irq = qe_ic_get_low_irq(qe_ic);
if (cascade_irq != NO_IRQ)
@@ -91,7 +91,7 @@ static inline void qe_ic_cascade_low_ipic(unsigned int irq,
static inline void qe_ic_cascade_high_ipic(unsigned int irq,
struct irq_desc *desc)
{
- struct qe_ic *qe_ic = get_irq_desc_data(desc);
+ struct qe_ic *qe_ic = irq_desc_get_handler_data(desc);
unsigned int cascade_irq = qe_ic_get_high_irq(qe_ic);
if (cascade_irq != NO_IRQ)
@@ -101,9 +101,9 @@ static inline void qe_ic_cascade_high_ipic(unsigned int irq,
static inline void qe_ic_cascade_low_mpic(unsigned int irq,
struct irq_desc *desc)
{
- struct qe_ic *qe_ic = get_irq_desc_data(desc);
+ struct qe_ic *qe_ic = irq_desc_get_handler_data(desc);
unsigned int cascade_irq = qe_ic_get_low_irq(qe_ic);
- struct irq_chip *chip = get_irq_desc_chip(desc);
+ struct irq_chip *chip = irq_desc_get_chip(desc);
if (cascade_irq != NO_IRQ)
generic_handle_irq(cascade_irq);
@@ -114,9 +114,9 @@ static inline void qe_ic_cascade_low_mpic(unsigned int irq,
static inline void qe_ic_cascade_high_mpic(unsigned int irq,
struct irq_desc *desc)
{
- struct qe_ic *qe_ic = get_irq_desc_data(desc);
+ struct qe_ic *qe_ic = irq_desc_get_handler_data(desc);
unsigned int cascade_irq = qe_ic_get_high_irq(qe_ic);
- struct irq_chip *chip = get_irq_desc_chip(desc);
+ struct irq_chip *chip = irq_desc_get_chip(desc);
if (cascade_irq != NO_IRQ)
generic_handle_irq(cascade_irq);
@@ -127,9 +127,9 @@ static inline void qe_ic_cascade_high_mpic(unsigned int irq,
static inline void qe_ic_cascade_muxed_mpic(unsigned int irq,
struct irq_desc *desc)
{
- struct qe_ic *qe_ic = get_irq_desc_data(desc);
+ struct qe_ic *qe_ic = irq_desc_get_handler_data(desc);
unsigned int cascade_irq;
- struct irq_chip *chip = get_irq_desc_chip(desc);
+ struct irq_chip *chip = irq_desc_get_chip(desc);
cascade_irq = qe_ic_get_high_irq(qe_ic);
if (cascade_irq == NO_IRQ)
--
1.7.0.4
___
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Linuxppc-dev@lists.ozlabs.org
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RE: [PATCH] * mpc8313erdb.dts: Fixed eTSEC interrupt assignment.
>-Original Message- >From: linuxppc-dev-bounces On Behalf Of Scott Wood >Sent: Wednesday, September 09, 2009 8:22 PM >To: Roland Lezuo >Cc: linuxppc-dev@lists.ozlabs.org >Subject: Re: [PATCH] * mpc8313erdb.dts: Fixed eTSEC interrupt assignment. > >On Fri, Sep 04, 2009 at 12:31:25PM +0200, Roland Lezuo wrote: >> The following patch is needed to correctly assign the IRQs for the >> gianfar driver on the MPC8313ERDB-revc boards. ERR and TX are swapped >> as well as the interrupt lines for the two devices. > >And it will incorrectly assign them on older revisions of the chip. > >We really should have a u-boot fixup based on SVR. Why not just offer different dts files, one for each board revision? Something like: mpc8313erdb-revA.dts mpc8313erdb-revB.dts mpc8313erdb-revC.dts Richard ___ Linuxppc-dev mailing list Linuxppc-dev@lists.ozlabs.org https://lists.ozlabs.org/listinfo/linuxppc-dev
RE: [PATCH] * mpc8313erdb.dts: Fixed eTSEC interrupt assignment.
>-Original Message- From: Scott Wood [mailto:scottw...@freescale.com] >Because that would be three times the device trees to maintain, and a >source of user confusion. I wonder which is more confusing for the user: 1. Choosing one of three dts files. 2. Having only one dts for his board, but Ethernet doesn't work. Richard ___ Linuxppc-dev mailing list Linuxppc-dev@lists.ozlabs.org https://lists.ozlabs.org/listinfo/linuxppc-dev
RE: [PATCH] * mpc8313erdb.dts: Fixed eTSEC interrupt assignment.
> -Original Message- > From: Scott Wood [mailto:scottw...@freescale.com] > Subject: Re: [PATCH] * mpc8313erdb.dts: Fixed eTSEC interrupt assignment. > > On Thu, Oct 15, 2009 at 02:19:30PM +0200, Richard Cochran wrote: > > 2. Having only one dts for his board, but Ethernet doesn't work. > > The point is to fix u-boot so that it *does* work with only one dts. If > people not upgrading u-boot is your concern, we could put the fixup in the > Linux platform code instead. Yes, I was thinking that upgrading u-boot can be problematic for people who don't have a JTAG flash tool, in case things go wrong. The whole kernel-uboot-dts triangle is a constant source of confusion, IMHO. But I thought the whole point of the device tree was, that it is easy to produce a dts that exactly matches a particular physical board design. If MPC8313-ERDB REVC has a different IRQ routing, then doesn't it deserve its own dts? Or do only *some* of the REVC boards have this routing? > And feel free to ask through official Freescale support channels why the > U-Boot that shipped on these boards does not have such a fixup (or why they > decided it was better to make late-rev 8313's interrupt assignments match > other 83xx than for all revs of the same part number to have the same > interrupt assignments). It sounds like you are not overly satisfied with Freescale's handling of their BSPs ;) To be fair, I am happy that Freescale appears to take Linux support seriously, but I do think they drop the ball once a BSP is published. For example, the MPC8313-ERDB ships with kernel 2.6.23 (with the old style dts) and a fair number of non-mainstream patches. It is not so easy to get a recent kernel booting on that board. I have the LITE5200B, MPC8313-ERDB, MPC8572DS, and the P2020DS in house, and it is really the same, sad story with each of them. Wouldn't it be grand if the development boards would boot "out of the box" when compiling the most recent kernel with default config? Maybe that's only wishful thinking, but I am happy to contribute what I can... Richard ___ Linuxppc-dev mailing list Linuxppc-dev@lists.ozlabs.org https://lists.ozlabs.org/listinfo/linuxppc-dev
RE: [PATCH] * mpc8313erdb.dts: Fixed eTSEC interrupt assignment.
> -Original Message- > From: Scott Wood [mailto:scottw...@freescale.com] > > What problems have you been having with upstream kernels on mpc8313erdb, > other than this IRQ issue? It should work, though the BSP may have extra > features that haven't been pushed upstream. I have been working from kernel 2.6.30 (although the very latest kernel is just the same WRT these problems, AFAICT). I had to patch in order to sovle the following three problems: 1. The flash layout in the DTS does not match the default partitioning from Freescale. In the current dts, the NAND partitioning is wrong, and there is no partitioning for the NOR flash given. 2. The eTSEC interrupt issue that started this thread. 3. The PTP IO signals are not configured in a vanilla linux. For this, you need parts of a Freescale patch. [1] Their PTP implementation gianfar driver is horrible, but still, the IO configuration in these two files in the patch is necessary to get any external signals from the PTP clock: arch/powerpc/platforms/83xx/mpc8313_rdb.c arch/powerpc/platforms/83xx/mpc83xx.h It may be that point 1 is not so important, since the flash layout is perhaps a very personal thing, but I would still expect the default dts to match the default partitioning from Freescale. Point 2 is obviously essential, and if you buy the mpc8313 for its PTP capabilities, as I did, then point 3 is a show stopper, as well. > I just booted 2.6.32-rc4 straight from Linus on an mpc8572ds yesterday. > I've booted various upstream kernels on mpc8313erdb (typically an older rev, > though). Okay, you are right, the mpc8572ds does seem to work pretty well. Perhaps we can fix up the above three issues? Richard [1] http://www.bitshrine.org/gpp_info/linux-fsl-2.6.23-MPC8313ERDB-IEEE-1588.patch.html ___ Linuxppc-dev mailing list Linuxppc-dev@lists.ozlabs.org https://lists.ozlabs.org/listinfo/linuxppc-dev
Re: [PATCH 3/3] ptp: Added a clock that uses the eTSEC found on the MPC85xx.
On Sat, May 01, 2010 at 11:36:12AM -0500, Kumar Gala wrote: > Is there a binding document that describes this node you are adding? No, but I will add one to Documentation/powerpc/dts-bindings. Thanks, Richard ___ Linuxppc-dev mailing list Linuxppc-dev@lists.ozlabs.org https://lists.ozlabs.org/listinfo/linuxppc-dev
regression: 2.6.39-rc2,3 compile failure on p2020
When compiling mpc85xx_smp_defconfig, the kernel fails to link with: arch/powerpc/kernel/built-in.o: In function `cpu_die': arch/powerpc/kernel/smp.c:702: undefined reference to `start_secondary_resume' I suspect: commit fa3f82c8bb7acbe049ea71f258b3ae0a33d9d40b powerpc/smp: soft-replugged CPUs must go back to start_secondary The symbol start_secondary_resume is provided by head_32.S, but it is not present in head_fsl_booke.S. I don't now how to fix this and would appreciate any help. Thanks, Richard ___ Linuxppc-dev mailing list Linuxppc-dev@lists.ozlabs.org https://lists.ozlabs.org/listinfo/linuxppc-dev
regression: 2.6.39-rc2,3 compile failure on p2020 (repost)
When compiling mpc85xx_smp_defconfig, the kernel fails to link with: arch/powerpc/kernel/built-in.o: In function `cpu_die': arch/powerpc/kernel/smp.c:702: undefined reference to `start_secondary_resume' I suspect: commit fa3f82c8bb7acbe049ea71f258b3ae0a33d9d40b powerpc/smp: soft-replugged CPUs must go back to start_secondary The symbol start_secondary_resume is provided by head_32.S, but it is not present in head_fsl_booke.S. I don't now how to fix this and would appreciate any help. Thanks, Richard ___ Linuxppc-dev mailing list Linuxppc-dev@lists.ozlabs.org https://lists.ozlabs.org/listinfo/linuxppc-dev
[PATCH V14 0/4] ptp: IEEE 1588 hardware clock support
* Introduction The aim of this patch set is to add support for PTP Hardware Clocks (PHCs) into the Linux kernel. The patch series builds upon the dynamic posix clock work appearing in kernel version 2.6.39. Support for obtaining timestamps from a PHC already exists via the SO_TIMESTAMPING socket option, integrated in kernel version 2.6.30. This patch set completes the picture by allow user space programs to adjust the PHC and to control its ancillary features. * Patches for ptpd on sf.net https://sourceforge.net/tracker/?group_id=139814&atid=744634 3225599 [PATCH 1/3] Convert to POSIX clock API. 3225603 [PATCH 2/3] Adapted to use the Linux PTP Hardware Clock API. 3225607 [PATCH 3/3] Adapted to use the newer SO_TIMESTAMPING Linux API. * PHC Patch ChangeLog ** v14 *** general - fixed unregister method to allow a clean module removal - blocked fifo readers no longer prohibit module removal - export skb_clone_tx_timestamp for module use *** phyter - allow mutiple clock/mdio bus instances - fix endian bug in packet matching code for LE host - fix module related null pointer dereference - warn rather than BUG when MAC driver is missing * Why all the CCs? - One driver is for PowerPC, and adds device tree stuff. - One driver is for the ARM Xscale IXP465. * Previous Discussions - [V13] http://lkml.org/lkml/2011/3/27/2 - [V12] http://lkml.org/lkml/2011/2/28/53 - [V11] http://lkml.org/lkml/2011/2/23/107 - [V10] http://lkml.org/lkml/2011/1/27/71 - [V9] http://lkml.org/lkml/2011/1/13/65 - [V8] http://lkml.org/lkml/2010/12/31/128 - [V7] http://lkml.org/lkml/2010/12/16/195 - [V6] http://lkml.org/lkml/2010/9/23/310 - [V5] http://lkml.org/lkml/2010/8/16/90 - Thomas Gleixner: Rework of the PTP support series core code http://lkml.org/lkml/2011/2/1/137 - Dynamic clock devices [RFC] http://lkml.org/lkml/2010/11/4/290 - POSIX clock tuning syscall with dynamic clock ids http://lkml.org/lkml/2010/9/3/119 - POSIX clock tuning syscall with static clock ids http://lkml.org/lkml/2010/8/23/49 - Versions 1-4 appeared on the netdev list. Richard Cochran (4): ptp: Added a brand new class driver for ptp clocks. ptp: Added a clock that uses the eTSEC found on the MPC85xx. ptp: Added a clock driver for the IXP46x. ptp: Added a clock driver for the National Semiconductor PHYTER. Documentation/ABI/testing/sysfs-ptp| 98 ++ .../devicetree/bindings/net/fsl-tsec-phy.txt | 54 + Documentation/ptp/ptp.txt | 89 ++ Documentation/ptp/testptp.c| 368 +++ Documentation/ptp/testptp.mk | 33 + arch/arm/mach-ixp4xx/include/mach/ixp46x_ts.h | 78 ++ arch/powerpc/boot/dts/mpc8313erdb.dts | 13 + arch/powerpc/boot/dts/mpc8572ds.dts| 13 + arch/powerpc/boot/dts/p2020ds.dts | 13 + arch/powerpc/boot/dts/p2020rdb.dts | 13 + drivers/Kconfig|2 + drivers/Makefile |1 + drivers/net/Makefile |1 + drivers/net/arm/ixp4xx_eth.c | 192 - drivers/net/gianfar_ptp.c | 588 +++ drivers/net/phy/Makefile |1 + drivers/net/phy/dp83640.c | 1100 drivers/net/phy/dp83640_reg.h | 267 + drivers/ptp/Kconfig| 75 ++ drivers/ptp/Makefile |7 + drivers/ptp/ptp_chardev.c | 159 +++ drivers/ptp/ptp_clock.c| 343 ++ drivers/ptp/ptp_ixp46x.c | 332 ++ drivers/ptp/ptp_private.h | 92 ++ drivers/ptp/ptp_sysfs.c| 230 include/linux/Kbuild |1 + include/linux/ptp_clock.h | 84 ++ include/linux/ptp_clock_kernel.h | 139 +++ 28 files changed, 4383 insertions(+), 3 deletions(-) create mode 100644 Documentation/ABI/testing/sysfs-ptp create mode 100644 Documentation/ptp/ptp.txt create mode 100644 Documentation/ptp/testptp.c create mode 100644 Documentation/ptp/testptp.mk create mode 100644 arch/arm/mach-ixp4xx/include/mach/ixp46x_ts.h create mode 100644 drivers/net/gianfar_ptp.c create mode 100644 drivers/net/phy/dp83640.c create mode 100644 drivers/net/phy/dp83640_reg.h create mode 100644 drivers/ptp/Kconfig create mode 100644 drivers/ptp/Makefile create mode 100644 drivers/ptp/ptp_chardev.c create mode 100644 drivers/ptp/ptp_clock.c create mode 100644 drivers/ptp/ptp_ixp46x.c create mode 100644 drivers/ptp/ptp_private.h create mode 100644 drivers/ptp/ptp_sysfs.c create mode 100644 include/linux/ptp_clo
[PATCH V14 1/4] ptp: Added a brand new class driver for ptp clocks.
This patch adds an infrastructure for hardware clocks that implement IEEE 1588, the Precision Time Protocol (PTP). A class driver offers a registration method to particular hardware clock drivers. Each clock is presented as a standard POSIX clock. The ancillary clock features are exposed in two different ways, via the sysfs and by a character device. Signed-off-by: Richard Cochran --- Documentation/ABI/testing/sysfs-ptp | 98 + Documentation/ptp/ptp.txt | 89 + Documentation/ptp/testptp.c | 368 +++ Documentation/ptp/testptp.mk| 33 +++ drivers/Kconfig |2 + drivers/Makefile|1 + drivers/ptp/Kconfig | 30 +++ drivers/ptp/Makefile|6 + drivers/ptp/ptp_chardev.c | 159 +++ drivers/ptp/ptp_clock.c | 343 drivers/ptp/ptp_private.h | 92 + drivers/ptp/ptp_sysfs.c | 230 ++ include/linux/Kbuild|1 + include/linux/ptp_clock.h | 84 include/linux/ptp_clock_kernel.h| 139 + 15 files changed, 1675 insertions(+), 0 deletions(-) create mode 100644 Documentation/ABI/testing/sysfs-ptp create mode 100644 Documentation/ptp/ptp.txt create mode 100644 Documentation/ptp/testptp.c create mode 100644 Documentation/ptp/testptp.mk create mode 100644 drivers/ptp/Kconfig create mode 100644 drivers/ptp/Makefile create mode 100644 drivers/ptp/ptp_chardev.c create mode 100644 drivers/ptp/ptp_clock.c create mode 100644 drivers/ptp/ptp_private.h create mode 100644 drivers/ptp/ptp_sysfs.c create mode 100644 include/linux/ptp_clock.h create mode 100644 include/linux/ptp_clock_kernel.h diff --git a/Documentation/ABI/testing/sysfs-ptp b/Documentation/ABI/testing/sysfs-ptp new file mode 100644 index 000..d40d2b5 --- /dev/null +++ b/Documentation/ABI/testing/sysfs-ptp @@ -0,0 +1,98 @@ +What: /sys/class/ptp/ +Date: September 2010 +Contact: Richard Cochran +Description: + This directory contains files and directories + providing a standardized interface to the ancillary + features of PTP hardware clocks. + +What: /sys/class/ptp/ptpN/ +Date: September 2010 +Contact: Richard Cochran +Description: + This directory contains the attributes of the Nth PTP + hardware clock registered into the PTP class driver + subsystem. + +What: /sys/class/ptp/ptpN/clock_name +Date: September 2010 +Contact: Richard Cochran +Description: + This file contains the name of the PTP hardware clock + as a human readable string. + +What: /sys/class/ptp/ptpN/max_adjustment +Date: September 2010 +Contact: Richard Cochran +Description: + This file contains the PTP hardware clock's maximum + frequency adjustment value (a positive integer) in + parts per billion. + +What: /sys/class/ptp/ptpN/n_alarms +Date: September 2010 +Contact: Richard Cochran +Description: + This file contains the number of periodic or one shot + alarms offer by the PTP hardware clock. + +What: /sys/class/ptp/ptpN/n_external_timestamps +Date: September 2010 +Contact: Richard Cochran +Description: + This file contains the number of external timestamp + channels offered by the PTP hardware clock. + +What: /sys/class/ptp/ptpN/n_periodic_outputs +Date: September 2010 +Contact: Richard Cochran +Description: + This file contains the number of programmable periodic + output channels offered by the PTP hardware clock. + +What: /sys/class/ptp/ptpN/pps_avaiable +Date: September 2010 +Contact: Richard Cochran +Description: + This file indicates whether the PTP hardware clock + supports a Pulse Per Second to the host CPU. Reading + "1" means that the PPS is supported, while "0" means + not supported. + +What: /sys/class/ptp/ptpN/extts_enable +Date: September 2010 +Contact: Richard Cochran +Description: + This write-only file enables or disables external + timestamps. To enable external timestamps, write the + channel index followed by a "1" into the file. + To disable external timestamps, write the channel + index followed by a "0" into the file. + +What: /sys/class/ptp/ptpN/fifo +Date: September 2010 +Contact: Richard Cochran +Description: + This file provides timestamps on external events,
[PATCH V14 2/4] ptp: Added a clock that uses the eTSEC found on the MPC85xx.
The eTSEC includes a PTP clock with quite a few features. This patch adds
support for the basic clock adjustment functions, plus two external time
stamps, one alarm, and the PPS callback.
Signed-off-by: Richard Cochran
Acked-by: John Stultz
---
.../devicetree/bindings/net/fsl-tsec-phy.txt | 54 ++
arch/powerpc/boot/dts/mpc8313erdb.dts | 13 +
arch/powerpc/boot/dts/mpc8572ds.dts| 13 +
arch/powerpc/boot/dts/p2020ds.dts | 13 +
arch/powerpc/boot/dts/p2020rdb.dts | 13 +
drivers/net/Makefile |1 +
drivers/net/gianfar_ptp.c | 588
drivers/ptp/Kconfig| 13 +
8 files changed, 708 insertions(+), 0 deletions(-)
create mode 100644 drivers/net/gianfar_ptp.c
diff --git a/Documentation/devicetree/bindings/net/fsl-tsec-phy.txt
b/Documentation/devicetree/bindings/net/fsl-tsec-phy.txt
index edb7ae1..2c6be03 100644
--- a/Documentation/devicetree/bindings/net/fsl-tsec-phy.txt
+++ b/Documentation/devicetree/bindings/net/fsl-tsec-phy.txt
@@ -74,3 +74,57 @@ Example:
interrupt-parent = <&mpic>;
phy-handle = <&phy0>
};
+
+* Gianfar PTP clock nodes
+
+General Properties:
+
+ - compatible Should be "fsl,etsec-ptp"
+ - reg Offset and length of the register set for the device
+ - interrupts There should be at least two interrupts. Some devices
+ have as many as four PTP related interrupts.
+
+Clock Properties:
+
+ - fsl,tclk-period Timer reference clock period in nanoseconds.
+ - fsl,tmr-prsc Prescaler, divides the output clock.
+ - fsl,tmr-add Frequency compensation value.
+ - fsl,tmr-fiper1 Fixed interval period pulse generator.
+ - fsl,tmr-fiper2 Fixed interval period pulse generator.
+ - fsl,max-adj Maximum frequency adjustment in parts per billion.
+
+ These properties set the operational parameters for the PTP
+ clock. You must choose these carefully for the clock to work right.
+ Here is how to figure good values:
+
+ TimerOsc = system clock MHz
+ tclk_period = desired clock period nanoseconds
+ NominalFreq = 1000 / tclk_period MHz
+ FreqDivRatio = TimerOsc / NominalFreq (must be greater that 1.0)
+ tmr_add = ceil(2^32 / FreqDivRatio)
+ OutputClock = NominalFreq / tmr_prsc MHz
+ PulseWidth = 1 / OutputClockmicroseconds
+ FiperFreq1 = desired frequency in Hz
+ FiperDiv1= 100 * OutputClock / FiperFreq1
+ tmr_fiper1 = tmr_prsc * tclk_period * FiperDiv1 - tclk_period
+ max_adj = 10 * (FreqDivRatio - 1.0) - 1
+
+ The calculation for tmr_fiper2 is the same as for tmr_fiper1. The
+ driver expects that tmr_fiper1 will be correctly set to produce a 1
+ Pulse Per Second (PPS) signal, since this will be offered to the PPS
+ subsystem to synchronize the Linux clock.
+
+Example:
+
+ ptp_clock@24E00 {
+ compatible = "fsl,etsec-ptp";
+ reg = <0x24E00 0xB0>;
+ interrupts = <12 0x8 13 0x8>;
+ interrupt-parent = < &ipic >;
+ fsl,tclk-period = <10>;
+ fsl,tmr-prsc= <100>;
+ fsl,tmr-add = <0x99A4>;
+ fsl,tmr-fiper1 = <0x3B9AC9F6>;
+ fsl,tmr-fiper2 = <0x00018696>;
+ fsl,max-adj = <65998>;
+ };
diff --git a/arch/powerpc/boot/dts/mpc8313erdb.dts
b/arch/powerpc/boot/dts/mpc8313erdb.dts
index 183f2aa..502e17c 100644
--- a/arch/powerpc/boot/dts/mpc8313erdb.dts
+++ b/arch/powerpc/boot/dts/mpc8313erdb.dts
@@ -208,6 +208,19 @@
sleep = <&pmc 0x0030>;
};
+ ptp_clock@24E00 {
+ compatible = "fsl,etsec-ptp";
+ reg = <0x24E00 0xB0>;
+ interrupts = <12 0x8 13 0x8>;
+ interrupt-parent = < &ipic >;
+ fsl,tclk-period = <10>;
+ fsl,tmr-prsc= <100>;
+ fsl,tmr-add = <0x99A4>;
+ fsl,tmr-fiper1 = <0x3B9AC9F6>;
+ fsl,tmr-fiper2 = <0x00018696>;
+ fsl,max-adj = <65998>;
+ };
+
enet0: ethernet@24000 {
#address-cells = <1>;
#size-cells = <1>;
diff --git a/arch/powerpc/boot/dts/mpc8572ds.dts
b/arch/powerpc/boot/dts/mpc8572ds.dts
index cafc128..f6c04d2 100644
--- a/arch/powerpc/boot/dts/mpc8572ds.dts
+++ b/arch/powerpc/boot/dts/mpc8572ds.dts
@@ -324,6 +324,19 @@
};
};
+ ptp_clock@24E00 {
+
[PATCH V14 3/4] ptp: Added a clock driver for the IXP46x.
This patch adds a driver for the hardware time stamping unit found on the
IXP465. The basic clock operations and an external trigger are implemented.
Signed-off-by: Richard Cochran
Acked-by: John Stultz
---
arch/arm/mach-ixp4xx/include/mach/ixp46x_ts.h | 78 ++
drivers/net/arm/ixp4xx_eth.c | 192 ++-
drivers/ptp/Kconfig | 13 +
drivers/ptp/Makefile |1 +
drivers/ptp/ptp_ixp46x.c | 332 +
5 files changed, 613 insertions(+), 3 deletions(-)
create mode 100644 arch/arm/mach-ixp4xx/include/mach/ixp46x_ts.h
create mode 100644 drivers/ptp/ptp_ixp46x.c
diff --git a/arch/arm/mach-ixp4xx/include/mach/ixp46x_ts.h
b/arch/arm/mach-ixp4xx/include/mach/ixp46x_ts.h
new file mode 100644
index 000..292d55e
--- /dev/null
+++ b/arch/arm/mach-ixp4xx/include/mach/ixp46x_ts.h
@@ -0,0 +1,78 @@
+/*
+ * PTP 1588 clock using the IXP46X
+ *
+ * Copyright (C) 2010 OMICRON electronics GmbH
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
+ */
+
+#ifndef _IXP46X_TS_H_
+#define _IXP46X_TS_H_
+
+#define DEFAULT_ADDEND 0xF029
+#define TICKS_NS_SHIFT 4
+
+struct ixp46x_channel_ctl {
+ u32 ch_control; /* 0x40 Time Synchronization Channel Control */
+ u32 ch_event;/* 0x44 Time Synchronization Channel Event */
+ u32 tx_snap_lo; /* 0x48 Transmit Snapshot Low Register */
+ u32 tx_snap_hi; /* 0x4C Transmit Snapshot High Register */
+ u32 rx_snap_lo; /* 0x50 Receive Snapshot Low Register */
+ u32 rx_snap_hi; /* 0x54 Receive Snapshot High Register */
+ u32 src_uuid_lo; /* 0x58 Source UUID0 Low Register */
+ u32 src_uuid_hi; /* 0x5C Sequence Identifier/Source UUID0 High */
+};
+
+struct ixp46x_ts_regs {
+ u32 control; /* 0x00 Time Sync Control Register */
+ u32 event; /* 0x04 Time Sync Event Register */
+ u32 addend; /* 0x08 Time Sync Addend Register */
+ u32 accum; /* 0x0C Time Sync Accumulator Register */
+ u32 test;/* 0x10 Time Sync Test Register */
+ u32 unused; /* 0x14 */
+ u32 rsystime_lo; /* 0x18 RawSystemTime_Low Register */
+ u32 rsystime_hi; /* 0x1C RawSystemTime_High Register */
+ u32 systime_lo; /* 0x20 SystemTime_Low Register */
+ u32 systime_hi; /* 0x24 SystemTime_High Register */
+ u32 trgt_lo; /* 0x28 TargetTime_Low Register */
+ u32 trgt_hi; /* 0x2C TargetTime_High Register */
+ u32 asms_lo; /* 0x30 Auxiliary Slave Mode Snapshot Low */
+ u32 asms_hi; /* 0x34 Auxiliary Slave Mode Snapshot High */
+ u32 amms_lo; /* 0x38 Auxiliary Master Mode Snapshot Low */
+ u32 amms_hi; /* 0x3C Auxiliary Master Mode Snapshot High */
+
+ struct ixp46x_channel_ctl channel[3];
+};
+
+/* 0x00 Time Sync Control Register Bits */
+#define TSCR_AMM (1<<3)
+#define TSCR_ASM (1<<2)
+#define TSCR_TTM (1<<1)
+#define TSCR_RST (1<<0)
+
+/* 0x04 Time Sync Event Register Bits */
+#define TSER_SNM (1<<3)
+#define TSER_SNS (1<<2)
+#define TTIPEND (1<<1)
+
+/* 0x40 Time Synchronization Channel Control Register Bits */
+#define MASTER_MODE (1<<0)
+#define TIMESTAMP_ALL (1<<1)
+
+/* 0x44 Time Synchronization Channel Event Register Bits */
+#define TX_SNAPSHOT_LOCKED (1<<0)
+#define RX_SNAPSHOT_LOCKED (1<<1)
+
+#endif
diff --git a/drivers/net/arm/ixp4xx_eth.c b/drivers/net/arm/ixp4xx_eth.c
index 9eb9b98..c56fcb6 100644
--- a/drivers/net/arm/ixp4xx_eth.c
+++ b/drivers/net/arm/ixp4xx_eth.c
@@ -30,9 +30,12 @@
#include
#include
#include
+#include
#include
#include
+#include
#include
+#include
#include
#include
@@ -67,6 +70,10 @@
#define RXFREE_QUEUE(port_id) (NPE_ID(port_id) + 26)
#define TXDONE_QUEUE 31
+#define PTP_SLAVE_MODE 1
+#define PTP_MASTER_MODE2
+#define PORT2CHANNEL(p)NPE_ID(p->id)
+
/* TX Control Registers */
#define TX_CNTRL0_TX_EN0x01
#define TX_CNTRL0_HALFDUPLEX 0x02
@@ -171,6 +178,8 @@ struct port {
int id; /* logical port ID */
int speed, duplex;
u8 firmware[4];
+ int hwts_tx_en;
+ int hwts_rx_en;
};
/*
[PATCH V14 4/4] ptp: Added a clock driver for the National Semiconductor PHYTER.
This patch adds support for the PTP clock found on the DP83640.
The basic clock operations and one external time stamp have
been implemented.
Signed-off-by: Richard Cochran
---
drivers/net/phy/Makefile |1 +
drivers/net/phy/dp83640.c | 1100 +
drivers/net/phy/dp83640_reg.h | 267 ++
drivers/ptp/Kconfig | 19 +
4 files changed, 1387 insertions(+), 0 deletions(-)
create mode 100644 drivers/net/phy/dp83640.c
create mode 100644 drivers/net/phy/dp83640_reg.h
diff --git a/drivers/net/phy/Makefile b/drivers/net/phy/Makefile
index 13bebab..2333215 100644
--- a/drivers/net/phy/Makefile
+++ b/drivers/net/phy/Makefile
@@ -19,6 +19,7 @@ obj-$(CONFIG_FIXED_PHY) += fixed.o
obj-$(CONFIG_MDIO_BITBANG) += mdio-bitbang.o
obj-$(CONFIG_MDIO_GPIO)+= mdio-gpio.o
obj-$(CONFIG_NATIONAL_PHY) += national.o
+obj-$(CONFIG_DP83640_PHY) += dp83640.o
obj-$(CONFIG_STE10XP) += ste10Xp.o
obj-$(CONFIG_MICREL_PHY) += micrel.o
obj-$(CONFIG_MDIO_OCTEON) += mdio-octeon.o
diff --git a/drivers/net/phy/dp83640.c b/drivers/net/phy/dp83640.c
new file mode 100644
index 000..11c7e2d
--- /dev/null
+++ b/drivers/net/phy/dp83640.c
@@ -0,0 +1,1100 @@
+/*
+ * Driver for the National Semiconductor DP83640 PHYTER
+ *
+ * Copyright (C) 2010 OMICRON electronics GmbH
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
+ */
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+#include "dp83640_reg.h"
+
+#define DP83640_PHY_ID 0x20005ce1
+#define PAGESEL0x13
+#define LAYER4 0x02
+#define LAYER2 0x01
+#define MAX_RXTS 4
+#define MAX_TXTS 4
+#define N_EXT_TS 1
+#define PSF_PTPVER 2
+#define PSF_EVNT 0x4000
+#define PSF_RX 0x2000
+#define PSF_TX 0x1000
+#define EXT_EVENT 1
+#define EXT_GPIO 1
+#define CAL_EVENT 2
+#define CAL_GPIO 9
+#define CAL_TRIGGER2
+
+/* phyter seems to miss the mark by 16 ns */
+#define ADJTIME_FIX16
+
+#if defined(__BIG_ENDIAN)
+#define ENDIAN_FLAG0
+#elif defined(__LITTLE_ENDIAN)
+#define ENDIAN_FLAGPSF_ENDIAN
+#endif
+
+#define SKB_PTP_TYPE(__skb) (*(unsigned int *)((__skb)->cb))
+
+struct phy_rxts {
+ u16 ns_lo; /* ns[15:0] */
+ u16 ns_hi; /* overflow[1:0], ns[29:16] */
+ u16 sec_lo; /* sec[15:0] */
+ u16 sec_hi; /* sec[31:16] */
+ u16 seqid; /* sequenceId[15:0] */
+ u16 msgtype; /* messageType[3:0], hash[11:0] */
+};
+
+struct phy_txts {
+ u16 ns_lo; /* ns[15:0] */
+ u16 ns_hi; /* overflow[1:0], ns[29:16] */
+ u16 sec_lo; /* sec[15:0] */
+ u16 sec_hi; /* sec[31:16] */
+};
+
+struct rxts {
+ struct list_head list;
+ unsigned long tmo;
+ u64 ns;
+ u16 seqid;
+ u8 msgtype;
+ u16 hash;
+};
+
+struct dp83640_clock;
+
+struct dp83640_private {
+ struct list_head list;
+ struct dp83640_clock *clock;
+ struct phy_device *phydev;
+ struct work_struct ts_work;
+ int hwts_tx_en;
+ int hwts_rx_en;
+ int layer;
+ int version;
+ /* remember state of cfg0 during calibration */
+ int cfg0;
+ /* remember the last event time stamp */
+ struct phy_txts edata;
+ /* list of rx timestamps */
+ struct list_head rxts;
+ struct list_head rxpool;
+ struct rxts rx_pool_data[MAX_RXTS];
+ /* protects above three fields from concurrent access */
+ spinlock_t rx_lock;
+ /* queues of incoming and outgoing packets */
+ struct sk_buff_head rx_queue;
+ struct sk_buff_head tx_queue;
+};
+
+struct dp83640_clock {
+ /* keeps the instance in the 'phyter_clocks' list */
+ struct list_head list;
+ /* we create one clock instance per MII bus */
+ struct mii_bus *bus;
+ /* protects extended registers from concurrent access */
+ struct mutex extreg_lock;
+ /* remembers which page was last selected */
+ int page;
+ /* our advertised capabilities */
+ struct ptp_clock_info caps;
+ /* protects the three fields below from concurrent access */
+ struct mutex clock_lock;
+
Re: [PATCH V14 3/4] ptp: Added a clock driver for the IXP46x.
On Mon, Apr 18, 2011 at 08:56:03AM +0200, Arnd Bergmann wrote: > On Monday 18 April 2011, Richard Cochran wrote: > > + > > + lo = __raw_readl(®s->channel[ch].src_uuid_lo); > > + hi = __raw_readl(®s->channel[ch].src_uuid_hi); > > + > > I guess you should use readl(), not __raw_readl() here. The __raw_* functions > are not meant for device drivers. Krzysztof had a different opinion about this. https://lkml.org/lkml/2011/1/8/67 Anyway, it is his driver, and I just followed what he does elsewhere in the driver. It make sense to me to keep the driver consistent. Maybe we should make the change throughout? Thanks, Richard ___ Linuxppc-dev mailing list Linuxppc-dev@lists.ozlabs.org https://lists.ozlabs.org/listinfo/linuxppc-dev
Re: [PATCH V14 3/4] ptp: Added a clock driver for the IXP46x.
Also, I forgot to add Krzysztof's ack to the commit message, but he did ack V12. Thanks, Richard ___ Linuxppc-dev mailing list Linuxppc-dev@lists.ozlabs.org https://lists.ozlabs.org/listinfo/linuxppc-dev
Re: [PATCH V14 4/4] ptp: Added a clock driver for the National Semiconductor PHYTER.
On Mon, Apr 18, 2011 at 09:57:25PM +0100, Ben Hutchings wrote: > Would be better without the magic numbers. Yes, of course, you are right, and also about patch #3. Please take a look at v15 and see if it improves things. Thanks, Richard ___ Linuxppc-dev mailing list Linuxppc-dev@lists.ozlabs.org https://lists.ozlabs.org/listinfo/linuxppc-dev
[PATCH V15 0/4] ptp: IEEE 1588 hardware clock support
Here is V15 of the PHC patch series. I had been a bit lazy in adding the acks that have accumulated since V13, and so now I have added them into the commit message, unless the particular patch changed substantially since the ack. * Introduction The aim of this patch set is to add support for PTP Hardware Clocks (PHCs) into the Linux kernel. The patch series builds upon the dynamic posix clock work appearing in kernel version 2.6.39. Support for obtaining timestamps from a PHC already exists via the SO_TIMESTAMPING socket option, integrated in kernel version 2.6.30. This patch set completes the picture by allow user space programs to adjust the PHC and to control its ancillary features. * Patches for ptpd on sf.net https://sourceforge.net/tracker/?group_id=139814&atid=744634 3225599 [PATCH 1/3] Convert to POSIX clock API. 3225603 [PATCH 2/3] Adapted to use the Linux PTP Hardware Clock API. 3225607 [PATCH 3/3] Adapted to use the newer SO_TIMESTAMPING Linux API. * PHC Patch ChangeLog ** v15 *** general - allow test program to set system time from PTP HW clock *** ixp46x and phyter packet matching - check packet bounds - handle variable ipv4 header length - replace magic numbers with macros * Why all the CCs? - One driver is for PowerPC, and adds device tree stuff. - One driver is for the ARM Xscale IXP465. * Previous Discussions - [V14] http://lkml.org/lkml/2011/4/18/16 - [V13] http://lkml.org/lkml/2011/3/27/2 - [V12] http://lkml.org/lkml/2011/2/28/53 - [V11] http://lkml.org/lkml/2011/2/23/107 - [V10] http://lkml.org/lkml/2011/1/27/71 - [V9] http://lkml.org/lkml/2011/1/13/65 - [V8] http://lkml.org/lkml/2010/12/31/128 - [V7] http://lkml.org/lkml/2010/12/16/195 - [V6] http://lkml.org/lkml/2010/9/23/310 - [V5] http://lkml.org/lkml/2010/8/16/90 - Thomas Gleixner: Rework of the PTP support series core code http://lkml.org/lkml/2011/2/1/137 - Dynamic clock devices [RFC] http://lkml.org/lkml/2010/11/4/290 - POSIX clock tuning syscall with dynamic clock ids http://lkml.org/lkml/2010/9/3/119 - POSIX clock tuning syscall with static clock ids http://lkml.org/lkml/2010/8/23/49 - Versions 1-4 appeared on the netdev list. Richard Cochran (4): ptp: Added a brand new class driver for ptp clocks. ptp: Added a clock that uses the eTSEC found on the MPC85xx. ptp: Added a clock driver for the IXP46x. ptp: Added a clock driver for the National Semiconductor PHYTER. Documentation/ABI/testing/sysfs-ptp| 98 ++ .../devicetree/bindings/net/fsl-tsec-phy.txt | 54 + Documentation/ptp/ptp.txt | 89 ++ Documentation/ptp/testptp.c| 381 +++ Documentation/ptp/testptp.mk | 33 + arch/arm/mach-ixp4xx/include/mach/ixp46x_ts.h | 78 ++ arch/powerpc/boot/dts/mpc8313erdb.dts | 13 + arch/powerpc/boot/dts/mpc8572ds.dts| 13 + arch/powerpc/boot/dts/p2020ds.dts | 13 + arch/powerpc/boot/dts/p2020rdb.dts | 13 + drivers/Kconfig|2 + drivers/Makefile |1 + drivers/net/Makefile |1 + drivers/net/arm/ixp4xx_eth.c | 195 - drivers/net/gianfar_ptp.c | 588 +++ drivers/net/phy/Makefile |1 + drivers/net/phy/dp83640.c | 1100 drivers/net/phy/dp83640_reg.h | 267 + drivers/ptp/Kconfig| 75 ++ drivers/ptp/Makefile |7 + drivers/ptp/ptp_chardev.c | 159 +++ drivers/ptp/ptp_clock.c| 343 ++ drivers/ptp/ptp_ixp46x.c | 332 ++ drivers/ptp/ptp_private.h | 92 ++ drivers/ptp/ptp_sysfs.c| 230 include/linux/Kbuild |1 + include/linux/ptp_classify.h |7 + include/linux/ptp_clock.h | 84 ++ include/linux/ptp_clock_kernel.h | 139 +++ 29 files changed, 4406 insertions(+), 3 deletions(-) create mode 100644 Documentation/ABI/testing/sysfs-ptp create mode 100644 Documentation/ptp/ptp.txt create mode 100644 Documentation/ptp/testptp.c create mode 100644 Documentation/ptp/testptp.mk create mode 100644 arch/arm/mach-ixp4xx/include/mach/ixp46x_ts.h create mode 100644 drivers/net/gianfar_ptp.c create mode 100644 drivers/net/phy/dp83640.c create mode 100644 drivers/net/phy/dp83640_reg.h create mode 100644 drivers/ptp/Kconfig create mode 100644 drivers/ptp/Makefile create mode 100644 drivers/ptp/ptp_chardev.c create mode 100644 drivers/ptp/ptp_clock.c create mode 100644 drivers
[PATCH V15 1/4] ptp: Added a brand new class driver for ptp clocks.
This patch adds an infrastructure for hardware clocks that implement IEEE 1588, the Precision Time Protocol (PTP). A class driver offers a registration method to particular hardware clock drivers. Each clock is presented as a standard POSIX clock. The ancillary clock features are exposed in two different ways, via the sysfs and by a character device. Signed-off-by: Richard Cochran Acked-by: Arnd Bergmann Acked-by: David S. Miller --- Documentation/ABI/testing/sysfs-ptp | 98 + Documentation/ptp/ptp.txt | 89 Documentation/ptp/testptp.c | 381 +++ Documentation/ptp/testptp.mk| 33 +++ drivers/Kconfig |2 + drivers/Makefile|1 + drivers/ptp/Kconfig | 30 +++ drivers/ptp/Makefile|6 + drivers/ptp/ptp_chardev.c | 159 +++ drivers/ptp/ptp_clock.c | 343 +++ drivers/ptp/ptp_private.h | 92 + drivers/ptp/ptp_sysfs.c | 230 + include/linux/Kbuild|1 + include/linux/ptp_classify.h|7 + include/linux/ptp_clock.h | 84 include/linux/ptp_clock_kernel.h| 139 + 16 files changed, 1695 insertions(+), 0 deletions(-) create mode 100644 Documentation/ABI/testing/sysfs-ptp create mode 100644 Documentation/ptp/ptp.txt create mode 100644 Documentation/ptp/testptp.c create mode 100644 Documentation/ptp/testptp.mk create mode 100644 drivers/ptp/Kconfig create mode 100644 drivers/ptp/Makefile create mode 100644 drivers/ptp/ptp_chardev.c create mode 100644 drivers/ptp/ptp_clock.c create mode 100644 drivers/ptp/ptp_private.h create mode 100644 drivers/ptp/ptp_sysfs.c create mode 100644 include/linux/ptp_clock.h create mode 100644 include/linux/ptp_clock_kernel.h diff --git a/Documentation/ABI/testing/sysfs-ptp b/Documentation/ABI/testing/sysfs-ptp new file mode 100644 index 000..d40d2b5 --- /dev/null +++ b/Documentation/ABI/testing/sysfs-ptp @@ -0,0 +1,98 @@ +What: /sys/class/ptp/ +Date: September 2010 +Contact: Richard Cochran +Description: + This directory contains files and directories + providing a standardized interface to the ancillary + features of PTP hardware clocks. + +What: /sys/class/ptp/ptpN/ +Date: September 2010 +Contact: Richard Cochran +Description: + This directory contains the attributes of the Nth PTP + hardware clock registered into the PTP class driver + subsystem. + +What: /sys/class/ptp/ptpN/clock_name +Date: September 2010 +Contact: Richard Cochran +Description: + This file contains the name of the PTP hardware clock + as a human readable string. + +What: /sys/class/ptp/ptpN/max_adjustment +Date: September 2010 +Contact: Richard Cochran +Description: + This file contains the PTP hardware clock's maximum + frequency adjustment value (a positive integer) in + parts per billion. + +What: /sys/class/ptp/ptpN/n_alarms +Date: September 2010 +Contact: Richard Cochran +Description: + This file contains the number of periodic or one shot + alarms offer by the PTP hardware clock. + +What: /sys/class/ptp/ptpN/n_external_timestamps +Date: September 2010 +Contact: Richard Cochran +Description: + This file contains the number of external timestamp + channels offered by the PTP hardware clock. + +What: /sys/class/ptp/ptpN/n_periodic_outputs +Date: September 2010 +Contact: Richard Cochran +Description: + This file contains the number of programmable periodic + output channels offered by the PTP hardware clock. + +What: /sys/class/ptp/ptpN/pps_avaiable +Date: September 2010 +Contact: Richard Cochran +Description: + This file indicates whether the PTP hardware clock + supports a Pulse Per Second to the host CPU. Reading + "1" means that the PPS is supported, while "0" means + not supported. + +What: /sys/class/ptp/ptpN/extts_enable +Date: September 2010 +Contact: Richard Cochran +Description: + This write-only file enables or disables external + timestamps. To enable external timestamps, write the + channel index followed by a "1" into the file. + To disable external timestamps, write the channel + index followed by a "0" into the file. + +What: /sys/class/ptp/ptpN/fifo +Date: September 2010
[PATCH V15 2/4] ptp: Added a clock that uses the eTSEC found on the MPC85xx.
The eTSEC includes a PTP clock with quite a few features. This patch adds
support for the basic clock adjustment functions, plus two external time
stamps, one alarm, and the PPS callback.
Signed-off-by: Richard Cochran
Acked-by: David S. Miller
Acked-by: John Stultz
---
.../devicetree/bindings/net/fsl-tsec-phy.txt | 54 ++
arch/powerpc/boot/dts/mpc8313erdb.dts | 13 +
arch/powerpc/boot/dts/mpc8572ds.dts| 13 +
arch/powerpc/boot/dts/p2020ds.dts | 13 +
arch/powerpc/boot/dts/p2020rdb.dts | 13 +
drivers/net/Makefile |1 +
drivers/net/gianfar_ptp.c | 588
drivers/ptp/Kconfig| 13 +
8 files changed, 708 insertions(+), 0 deletions(-)
create mode 100644 drivers/net/gianfar_ptp.c
diff --git a/Documentation/devicetree/bindings/net/fsl-tsec-phy.txt
b/Documentation/devicetree/bindings/net/fsl-tsec-phy.txt
index edb7ae1..2c6be03 100644
--- a/Documentation/devicetree/bindings/net/fsl-tsec-phy.txt
+++ b/Documentation/devicetree/bindings/net/fsl-tsec-phy.txt
@@ -74,3 +74,57 @@ Example:
interrupt-parent = <&mpic>;
phy-handle = <&phy0>
};
+
+* Gianfar PTP clock nodes
+
+General Properties:
+
+ - compatible Should be "fsl,etsec-ptp"
+ - reg Offset and length of the register set for the device
+ - interrupts There should be at least two interrupts. Some devices
+ have as many as four PTP related interrupts.
+
+Clock Properties:
+
+ - fsl,tclk-period Timer reference clock period in nanoseconds.
+ - fsl,tmr-prsc Prescaler, divides the output clock.
+ - fsl,tmr-add Frequency compensation value.
+ - fsl,tmr-fiper1 Fixed interval period pulse generator.
+ - fsl,tmr-fiper2 Fixed interval period pulse generator.
+ - fsl,max-adj Maximum frequency adjustment in parts per billion.
+
+ These properties set the operational parameters for the PTP
+ clock. You must choose these carefully for the clock to work right.
+ Here is how to figure good values:
+
+ TimerOsc = system clock MHz
+ tclk_period = desired clock period nanoseconds
+ NominalFreq = 1000 / tclk_period MHz
+ FreqDivRatio = TimerOsc / NominalFreq (must be greater that 1.0)
+ tmr_add = ceil(2^32 / FreqDivRatio)
+ OutputClock = NominalFreq / tmr_prsc MHz
+ PulseWidth = 1 / OutputClockmicroseconds
+ FiperFreq1 = desired frequency in Hz
+ FiperDiv1= 100 * OutputClock / FiperFreq1
+ tmr_fiper1 = tmr_prsc * tclk_period * FiperDiv1 - tclk_period
+ max_adj = 10 * (FreqDivRatio - 1.0) - 1
+
+ The calculation for tmr_fiper2 is the same as for tmr_fiper1. The
+ driver expects that tmr_fiper1 will be correctly set to produce a 1
+ Pulse Per Second (PPS) signal, since this will be offered to the PPS
+ subsystem to synchronize the Linux clock.
+
+Example:
+
+ ptp_clock@24E00 {
+ compatible = "fsl,etsec-ptp";
+ reg = <0x24E00 0xB0>;
+ interrupts = <12 0x8 13 0x8>;
+ interrupt-parent = < &ipic >;
+ fsl,tclk-period = <10>;
+ fsl,tmr-prsc= <100>;
+ fsl,tmr-add = <0x99A4>;
+ fsl,tmr-fiper1 = <0x3B9AC9F6>;
+ fsl,tmr-fiper2 = <0x00018696>;
+ fsl,max-adj = <65998>;
+ };
diff --git a/arch/powerpc/boot/dts/mpc8313erdb.dts
b/arch/powerpc/boot/dts/mpc8313erdb.dts
index 183f2aa..502e17c 100644
--- a/arch/powerpc/boot/dts/mpc8313erdb.dts
+++ b/arch/powerpc/boot/dts/mpc8313erdb.dts
@@ -208,6 +208,19 @@
sleep = <&pmc 0x0030>;
};
+ ptp_clock@24E00 {
+ compatible = "fsl,etsec-ptp";
+ reg = <0x24E00 0xB0>;
+ interrupts = <12 0x8 13 0x8>;
+ interrupt-parent = < &ipic >;
+ fsl,tclk-period = <10>;
+ fsl,tmr-prsc= <100>;
+ fsl,tmr-add = <0x99A4>;
+ fsl,tmr-fiper1 = <0x3B9AC9F6>;
+ fsl,tmr-fiper2 = <0x00018696>;
+ fsl,max-adj = <65998>;
+ };
+
enet0: ethernet@24000 {
#address-cells = <1>;
#size-cells = <1>;
diff --git a/arch/powerpc/boot/dts/mpc8572ds.dts
b/arch/powerpc/boot/dts/mpc8572ds.dts
index cafc128..f6c04d2 100644
--- a/arch/powerpc/boot/dts/mpc8572ds.dts
+++ b/arch/powerpc/boot/dts/mpc8572ds.dts
@@ -324,6 +324,19 @@
};
};
+
[PATCH V15 3/4] ptp: Added a clock driver for the IXP46x.
This patch adds a driver for the hardware time stamping unit found on the
IXP465. The basic clock operations and an external trigger are implemented.
Signed-off-by: Richard Cochran
Acked-by: Arnd Bergmann
Acked-by: David S. Miller
Acked-by: John Stultz
Acked-by: Krzysztof Halasa
---
arch/arm/mach-ixp4xx/include/mach/ixp46x_ts.h | 78 ++
drivers/net/arm/ixp4xx_eth.c | 195 ++-
drivers/ptp/Kconfig | 13 +
drivers/ptp/Makefile |1 +
drivers/ptp/ptp_ixp46x.c | 332 +
5 files changed, 616 insertions(+), 3 deletions(-)
create mode 100644 arch/arm/mach-ixp4xx/include/mach/ixp46x_ts.h
create mode 100644 drivers/ptp/ptp_ixp46x.c
diff --git a/arch/arm/mach-ixp4xx/include/mach/ixp46x_ts.h
b/arch/arm/mach-ixp4xx/include/mach/ixp46x_ts.h
new file mode 100644
index 000..292d55e
--- /dev/null
+++ b/arch/arm/mach-ixp4xx/include/mach/ixp46x_ts.h
@@ -0,0 +1,78 @@
+/*
+ * PTP 1588 clock using the IXP46X
+ *
+ * Copyright (C) 2010 OMICRON electronics GmbH
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
+ */
+
+#ifndef _IXP46X_TS_H_
+#define _IXP46X_TS_H_
+
+#define DEFAULT_ADDEND 0xF029
+#define TICKS_NS_SHIFT 4
+
+struct ixp46x_channel_ctl {
+ u32 ch_control; /* 0x40 Time Synchronization Channel Control */
+ u32 ch_event;/* 0x44 Time Synchronization Channel Event */
+ u32 tx_snap_lo; /* 0x48 Transmit Snapshot Low Register */
+ u32 tx_snap_hi; /* 0x4C Transmit Snapshot High Register */
+ u32 rx_snap_lo; /* 0x50 Receive Snapshot Low Register */
+ u32 rx_snap_hi; /* 0x54 Receive Snapshot High Register */
+ u32 src_uuid_lo; /* 0x58 Source UUID0 Low Register */
+ u32 src_uuid_hi; /* 0x5C Sequence Identifier/Source UUID0 High */
+};
+
+struct ixp46x_ts_regs {
+ u32 control; /* 0x00 Time Sync Control Register */
+ u32 event; /* 0x04 Time Sync Event Register */
+ u32 addend; /* 0x08 Time Sync Addend Register */
+ u32 accum; /* 0x0C Time Sync Accumulator Register */
+ u32 test;/* 0x10 Time Sync Test Register */
+ u32 unused; /* 0x14 */
+ u32 rsystime_lo; /* 0x18 RawSystemTime_Low Register */
+ u32 rsystime_hi; /* 0x1C RawSystemTime_High Register */
+ u32 systime_lo; /* 0x20 SystemTime_Low Register */
+ u32 systime_hi; /* 0x24 SystemTime_High Register */
+ u32 trgt_lo; /* 0x28 TargetTime_Low Register */
+ u32 trgt_hi; /* 0x2C TargetTime_High Register */
+ u32 asms_lo; /* 0x30 Auxiliary Slave Mode Snapshot Low */
+ u32 asms_hi; /* 0x34 Auxiliary Slave Mode Snapshot High */
+ u32 amms_lo; /* 0x38 Auxiliary Master Mode Snapshot Low */
+ u32 amms_hi; /* 0x3C Auxiliary Master Mode Snapshot High */
+
+ struct ixp46x_channel_ctl channel[3];
+};
+
+/* 0x00 Time Sync Control Register Bits */
+#define TSCR_AMM (1<<3)
+#define TSCR_ASM (1<<2)
+#define TSCR_TTM (1<<1)
+#define TSCR_RST (1<<0)
+
+/* 0x04 Time Sync Event Register Bits */
+#define TSER_SNM (1<<3)
+#define TSER_SNS (1<<2)
+#define TTIPEND (1<<1)
+
+/* 0x40 Time Synchronization Channel Control Register Bits */
+#define MASTER_MODE (1<<0)
+#define TIMESTAMP_ALL (1<<1)
+
+/* 0x44 Time Synchronization Channel Event Register Bits */
+#define TX_SNAPSHOT_LOCKED (1<<0)
+#define RX_SNAPSHOT_LOCKED (1<<1)
+
+#endif
diff --git a/drivers/net/arm/ixp4xx_eth.c b/drivers/net/arm/ixp4xx_eth.c
index 9eb9b98..de51e84 100644
--- a/drivers/net/arm/ixp4xx_eth.c
+++ b/drivers/net/arm/ixp4xx_eth.c
@@ -30,9 +30,12 @@
#include
#include
#include
+#include
#include
#include
+#include
#include
+#include
#include
#include
@@ -67,6 +70,10 @@
#define RXFREE_QUEUE(port_id) (NPE_ID(port_id) + 26)
#define TXDONE_QUEUE 31
+#define PTP_SLAVE_MODE 1
+#define PTP_MASTER_MODE2
+#define PORT2CHANNEL(p)NPE_ID(p->id)
+
/* TX Control Registers */
#define TX_CNTRL0_TX_EN0x01
#define TX_CNTRL0_HALFDUPLEX 0x02
@@ -171,6 +178,8 @@ struct port {
int id; /* logical port ID */
int speed, duplex;
[PATCH V15 4/4] ptp: Added a clock driver for the National Semiconductor PHYTER.
This patch adds support for the PTP clock found on the DP83640.
The basic clock operations and one external time stamp have
been implemented.
Signed-off-by: Richard Cochran
---
drivers/net/phy/Makefile |1 +
drivers/net/phy/dp83640.c | 1100 +
drivers/net/phy/dp83640_reg.h | 267 ++
drivers/ptp/Kconfig | 19 +
4 files changed, 1387 insertions(+), 0 deletions(-)
create mode 100644 drivers/net/phy/dp83640.c
create mode 100644 drivers/net/phy/dp83640_reg.h
diff --git a/drivers/net/phy/Makefile b/drivers/net/phy/Makefile
index 13bebab..2333215 100644
--- a/drivers/net/phy/Makefile
+++ b/drivers/net/phy/Makefile
@@ -19,6 +19,7 @@ obj-$(CONFIG_FIXED_PHY) += fixed.o
obj-$(CONFIG_MDIO_BITBANG) += mdio-bitbang.o
obj-$(CONFIG_MDIO_GPIO)+= mdio-gpio.o
obj-$(CONFIG_NATIONAL_PHY) += national.o
+obj-$(CONFIG_DP83640_PHY) += dp83640.o
obj-$(CONFIG_STE10XP) += ste10Xp.o
obj-$(CONFIG_MICREL_PHY) += micrel.o
obj-$(CONFIG_MDIO_OCTEON) += mdio-octeon.o
diff --git a/drivers/net/phy/dp83640.c b/drivers/net/phy/dp83640.c
new file mode 100644
index 000..d463b8a
--- /dev/null
+++ b/drivers/net/phy/dp83640.c
@@ -0,0 +1,1100 @@
+/*
+ * Driver for the National Semiconductor DP83640 PHYTER
+ *
+ * Copyright (C) 2010 OMICRON electronics GmbH
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
+ */
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+#include "dp83640_reg.h"
+
+#define DP83640_PHY_ID 0x20005ce1
+#define PAGESEL0x13
+#define LAYER4 0x02
+#define LAYER2 0x01
+#define MAX_RXTS 4
+#define MAX_TXTS 4
+#define N_EXT_TS 1
+#define PSF_PTPVER 2
+#define PSF_EVNT 0x4000
+#define PSF_RX 0x2000
+#define PSF_TX 0x1000
+#define EXT_EVENT 1
+#define EXT_GPIO 1
+#define CAL_EVENT 2
+#define CAL_GPIO 9
+#define CAL_TRIGGER2
+
+/* phyter seems to miss the mark by 16 ns */
+#define ADJTIME_FIX16
+
+#if defined(__BIG_ENDIAN)
+#define ENDIAN_FLAG0
+#elif defined(__LITTLE_ENDIAN)
+#define ENDIAN_FLAGPSF_ENDIAN
+#endif
+
+#define SKB_PTP_TYPE(__skb) (*(unsigned int *)((__skb)->cb))
+
+struct phy_rxts {
+ u16 ns_lo; /* ns[15:0] */
+ u16 ns_hi; /* overflow[1:0], ns[29:16] */
+ u16 sec_lo; /* sec[15:0] */
+ u16 sec_hi; /* sec[31:16] */
+ u16 seqid; /* sequenceId[15:0] */
+ u16 msgtype; /* messageType[3:0], hash[11:0] */
+};
+
+struct phy_txts {
+ u16 ns_lo; /* ns[15:0] */
+ u16 ns_hi; /* overflow[1:0], ns[29:16] */
+ u16 sec_lo; /* sec[15:0] */
+ u16 sec_hi; /* sec[31:16] */
+};
+
+struct rxts {
+ struct list_head list;
+ unsigned long tmo;
+ u64 ns;
+ u16 seqid;
+ u8 msgtype;
+ u16 hash;
+};
+
+struct dp83640_clock;
+
+struct dp83640_private {
+ struct list_head list;
+ struct dp83640_clock *clock;
+ struct phy_device *phydev;
+ struct work_struct ts_work;
+ int hwts_tx_en;
+ int hwts_rx_en;
+ int layer;
+ int version;
+ /* remember state of cfg0 during calibration */
+ int cfg0;
+ /* remember the last event time stamp */
+ struct phy_txts edata;
+ /* list of rx timestamps */
+ struct list_head rxts;
+ struct list_head rxpool;
+ struct rxts rx_pool_data[MAX_RXTS];
+ /* protects above three fields from concurrent access */
+ spinlock_t rx_lock;
+ /* queues of incoming and outgoing packets */
+ struct sk_buff_head rx_queue;
+ struct sk_buff_head tx_queue;
+};
+
+struct dp83640_clock {
+ /* keeps the instance in the 'phyter_clocks' list */
+ struct list_head list;
+ /* we create one clock instance per MII bus */
+ struct mii_bus *bus;
+ /* protects extended registers from concurrent access */
+ struct mutex extreg_lock;
+ /* remembers which page was last selected */
+ int page;
+ /* our advertised capabilities */
+ struct ptp_clock_info caps;
+ /* protects the three fields below from concurrent access */
+ struct mutex clock_lock;
+
powerpc: mpc85xx regression since 2.6.39-rc2, one cpu core lame
Ben, Recent 2.6.39-rc kernels behave strangely on the Freescale dual core mpc8572 and p2020. There is a long pause (like 2 seconds) in the boot sequence after "mpic: requesting IPIs..." When the system comes up, only one core shows in /proc/cpuinfo. Later on, lots of messages appear like the following: INFO: task ksoftirqd/1:9 blocked for more than 120 seconds. I bisected [1] the problem to: commit c56e58537d504706954a06570b4034c04e5b7500 Author: Benjamin Herrenschmidt Date: Tue Mar 8 14:40:04 2011 +1100 powerpc/smp: Create idle threads on demand and properly reset them I don't see from that commit what had gone wrong. Perhaps you can help resolve this? Thanks, Richard 1. I had to patch commit e5462d16 by hand when bisecting, which is a fixup for commit fa3f82c8 and not yet merged in c56e5853. ___ Linuxppc-dev mailing list Linuxppc-dev@lists.ozlabs.org https://lists.ozlabs.org/listinfo/linuxppc-dev
Re: powerpc: mpc85xx regression since 2.6.39-rc2, one cpu core lame
On Wed, May 18, 2011 at 07:40:16AM +1000, Benjamin Herrenschmidt wrote: > On Tue, 2011-05-17 at 18:28 +0200, Richard Cochran wrote: > > Ben, > > > > Recent 2.6.39-rc kernels behave strangely on the Freescale dual core > > mpc8572 and p2020. There is a long pause (like 2 seconds) in the boot > > sequence after "mpic: requesting IPIs..." > > > > When the system comes up, only one core shows in /proc/cpuinfo. Later > > on, lots of messages appear like the following: > > > >INFO: task ksoftirqd/1:9 blocked for more than 120 seconds. > > > > I bisected [1] the problem to: > > > >commit c56e58537d504706954a06570b4034c04e5b7500 > >Author: Benjamin Herrenschmidt > >Date: Tue Mar 8 14:40:04 2011 +1100 > > > >powerpc/smp: Create idle threads on demand and properly reset them > > > > I don't see from that commit what had gone wrong. Perhaps you can > > help resolve this? > > Hrm, odd. Kumar, care to have a look ? That's what happens when you > don't get me HW to test with :-) (I get the feeling that I am the only one testing recent kernels with the mpc85xx.) Anyhow, I see that this commit was one of a series. For my own use, can I simply revert this one commit independently? Thanks, Richard ___ Linuxppc-dev mailing list Linuxppc-dev@lists.ozlabs.org https://lists.ozlabs.org/listinfo/linuxppc-dev
Re: [git pull] Please pull powerpc.git merge branch
On Thu, May 19, 2011 at 02:06:18PM +1000, Benjamin Herrenschmidt wrote:
> are available in the git repository at:
>
> git://git.kernel.org/pub/scm/linux/kernel/git/benh/powerpc.git merge
When I try to build 'next' (now at 208b3a4c), it does not compile due
to a change from the following commit.
> Benjamin Herrenschmidt (1):
> powerpc/smp: Make start_secondary_resume available to all CPU variants
I would appreciate your help in getting this fixed...
Thanks,
Richard
PS the error looks like this:
AS arch/powerpc/kernel/misc_32.o
arch/powerpc/kernel/misc_32.S: Assembler messages:
arch/powerpc/kernel/misc_32.S:703: Error: Unrecognized opcode: `std'
make[2]: *** [arch/powerpc/kernel/misc_32.o] Error 1
make[1]: *** [arch/powerpc/kernel] Error 2
> ${CROSS_COMPILE}gcc -v
Using built-in specs.
Target: powerpc-none-linux-gnuspe
Configured with: ../gcc-4.3.2/configure --target=powerpc-none-linux-gnuspe
--host=i686-pc-linux-gnu
--prefix=/opt/freescale/usr/local/gcc-4.3.74-eglibc-2.8.74-dp-2/powerpc-none-linux-gnuspe
--with-sysroot=/opt/freescale/usr/local/gcc-4.3.74-eglibc-2.8.74-dp-2/powerpc-none-linux-gnuspe/powerpc-none-linux-gnuspe/libc
--disable-libssp --disable-libmudflap --disable-libstdcxx-pch --enable-libgomp
--enable-shared --enable-threads --enable-languages=c,c++
--with-gmp=/usr/src/redhat/BUILD/csl-tc-4.3.74/host-libs/usr
--with-mpfr=/usr/src/redhat/BUILD/csl-tc-4.3.74/host-libs/usr --with-cpu=8548
--with-gnu-as --with-gnu-ld --enable-symvers=gnu --enable-__cxa_atexit
--enable-cxx-flags=-mcpu=8548 --disable-multilib --with-long-double-128
--disable-nls --enable-e500_double
Thread model: posix
gcc version 4.3.2 (GCC)
___
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Re: [git pull] Please pull powerpc.git merge branch
On Fri, May 20, 2011 at 09:58:45AM -0400, Josh Boyer wrote: > On Fri, May 20, 2011 at 03:23:29PM +0200, Richard Cochran wrote: > >When I try to build 'next' (now at 208b3a4c), it does not compile due > >to a change from the following commit. > > > >> Benjamin Herrenschmidt (1): > >> powerpc/smp: Make start_secondary_resume available to all CPU > >> variants > > > >I would appreciate your help in getting this fixed... > > Could you try the patch below? Yes, and it both compiles and boots. Thanks, Richard > > Commit 69e3cea8d5fd526 introduced start_secondary_resume to misc_32.S, > however it uses a 64-bit instruction which is not valid on 32-bit > platforms. Use 'stw' instead. > > Reported-by: Richard Cochran > Signed-off-by: Josh Boyer > > --- > > diff --git a/arch/powerpc/kernel/misc_32.S > b/arch/powerpc/kernel/misc_32.S > index 402560e..998a100 100644 > --- a/arch/powerpc/kernel/misc_32.S > +++ b/arch/powerpc/kernel/misc_32.S > @@ -700,7 +700,7 @@ _GLOBAL(start_secondary_resume) > rlwinm r1,r1,0,0,(31-THREAD_SHIFT) /* current_thread_info() */ > addir1,r1,THREAD_SIZE-STACK_FRAME_OVERHEAD > li r3,0 > - std r3,0(r1)/* Zero the stack frame pointer */ > + stw r3,0(r1)/* Zero the stack frame pointer */ > bl start_secondary > b . > #endif /* CONFIG_SMP */ > ___ Linuxppc-dev mailing list Linuxppc-dev@lists.ozlabs.org https://lists.ozlabs.org/listinfo/linuxppc-dev
[PATCH v3 0/3] ptp: IEEE 1588 clock support
Now and again there has been talk on this list of adding PTP support into Linux. One part of the picture is already in place, the SO_TIMESTAMPING API for hardware time stamping. This patch set offers the missing second part needed for complete IEEE 1588 support. The only feature still to be implemented is the hook into the PPS subsystem, to synchronize the Linux clock to the PTP clock. Enjoy, Richard * Patch ChangeLog ** v3 *** general - Added documentation on writing clock drivers. - Added the ioctls for the ancillary clock features. - Changed wrong subsys_initcall() to module_init() in clock drivers. - Removed the (too coarse) character device mutex. - Setting the clock now requires CAP_SYS_TIME. *** gianfar - Added alarm feature. - Added device tree node binding description. - Added fine grain locking of the clock registers. - Added the external time stamp feature. - Added white space for better style. - Coverted base+offset to structure pointers for register access. - When removing the driver, we now disable all PTP functions. ** v2 - Changed clock list from a static array into a dynamic list. Also, use a bitmap to manage the clock's minor numbers. - Replaced character device semaphore with a mutex. - Drop .ko from module names in Kbuild help. - Replace deprecated unifdef-y with header-y for user space header file. - Added links to both of the ptpd patches on sourceforge. - Gianfar driver now gets parameters from device tree. - Added API documentation to Documentation/ptp/ptp.txt Richard Cochran (3): ptp: Added a brand new class driver for ptp clocks. ptp: Added a clock that uses the Linux system time. ptp: Added a clock that uses the eTSEC found on the MPC85xx. Documentation/powerpc/dts-bindings/fsl/tsec.txt | 56 +++ Documentation/ptp/ptp.txt | 95 Documentation/ptp/testptp.c | 245 +++ Documentation/ptp/testptp.mk| 33 ++ arch/powerpc/boot/dts/mpc8313erdb.dts | 14 + arch/powerpc/boot/dts/p2020ds.dts | 14 + arch/powerpc/boot/dts/p2020rdb.dts | 14 + drivers/Kconfig |2 + drivers/Makefile|1 + drivers/net/Makefile|1 + drivers/net/gianfar_ptp.c | 521 +++ drivers/net/gianfar_ptp_reg.h | 113 + drivers/ptp/Kconfig | 51 +++ drivers/ptp/Makefile|6 + drivers/ptp/ptp_clock.c | 512 ++ drivers/ptp/ptp_linux.c | 136 ++ include/linux/Kbuild|1 + include/linux/ptp_clock.h | 79 include/linux/ptp_clock_kernel.h| 137 ++ kernel/time/ntp.c |2 + 20 files changed, 2033 insertions(+), 0 deletions(-) create mode 100644 Documentation/ptp/ptp.txt create mode 100644 Documentation/ptp/testptp.c create mode 100644 Documentation/ptp/testptp.mk create mode 100644 drivers/net/gianfar_ptp.c create mode 100644 drivers/net/gianfar_ptp_reg.h create mode 100644 drivers/ptp/Kconfig create mode 100644 drivers/ptp/Makefile create mode 100644 drivers/ptp/ptp_clock.c create mode 100644 drivers/ptp/ptp_linux.c create mode 100644 include/linux/ptp_clock.h create mode 100644 include/linux/ptp_clock_kernel.h ___ Linuxppc-dev mailing list Linuxppc-dev@lists.ozlabs.org https://lists.ozlabs.org/listinfo/linuxppc-dev
[PATCH v3 1/3] ptp: Added a brand new class driver for ptp clocks.
This patch adds an infrastructure for hardware clocks that implement IEEE 1588, the Precision Time Protocol (PTP). A class driver offers a registration method to particular hardware clock drivers. Each clock is exposed to user space as a character device with ioctls that allow tuning of the PTP clock. Signed-off-by: Richard Cochran --- Documentation/ptp/ptp.txt| 95 +++ Documentation/ptp/testptp.c | 245 ++ Documentation/ptp/testptp.mk | 33 +++ drivers/Kconfig |2 + drivers/Makefile |1 + drivers/ptp/Kconfig | 26 ++ drivers/ptp/Makefile |5 + drivers/ptp/ptp_clock.c | 512 ++ include/linux/Kbuild |1 + include/linux/ptp_clock.h| 79 ++ include/linux/ptp_clock_kernel.h | 137 ++ 11 files changed, 1136 insertions(+), 0 deletions(-) create mode 100644 Documentation/ptp/ptp.txt create mode 100644 Documentation/ptp/testptp.c create mode 100644 Documentation/ptp/testptp.mk create mode 100644 drivers/ptp/Kconfig create mode 100644 drivers/ptp/Makefile create mode 100644 drivers/ptp/ptp_clock.c create mode 100644 include/linux/ptp_clock.h create mode 100644 include/linux/ptp_clock_kernel.h diff --git a/Documentation/ptp/ptp.txt b/Documentation/ptp/ptp.txt new file mode 100644 index 000..46858b3 --- /dev/null +++ b/Documentation/ptp/ptp.txt @@ -0,0 +1,95 @@ + +* PTP infrastructure for Linux + + This patch set introduces support for IEEE 1588 PTP clocks in + Linux. Together with the SO_TIMESTAMPING socket options, this + presents a standardized method for developing PTP user space + programs, synchronizing Linux with external clocks, and using the + ancillary features of PTP hardware clocks. + + A new class driver exports a kernel interface for specific clock + drivers and a user space interface. The infrastructure supports a + complete set of PTP functionality. + + + Basic clock operations +- Set time +- Get time +- Shift the clock by a given offset atomically +- Adjust clock frequency + + + Ancillary clock features +- One short or periodic alarms, with signal delivery to user program +- Time stamp external events +- Period output signals configurable from user space +- Synchronization of the Linux system time via the PPS subsystem + +** PTP kernel API + + A PTP clock driver registers itself with the class driver. The + class driver handles all of the dealings with user space. The + author of a clock driver need only implement the details of + programming the clock hardware. The clock driver notifies the class + driver of asynchronous events (alarms and external time stamps) via + a simple message passing interface. + + The class driver supports multiple PTP clock drivers. In normal use + cases, only one PTP clock is needed. However, for testing and + development, it can be useful to have more than one clock in a + single system, in order to allow performance comparisons. + +** PTP user space API + + The class driver creates a character device for each registered PTP + clock. User space programs may control the clock using standardized + ioctls. A program may query, enable, configure, and disable the + ancillary clock features. User space can receive time stamped + events via blocking read() and poll(). One shot and periodic + signals may be configured via an ioctl API with semantics similar + to the POSIX timer_settime() system call. + + As an real life example, the following two patches for ptpd version + 1.0.0 demonstrate how the API works. + + https://sourceforge.net/tracker/?func=detail&aid=2992845&group_id=139814&atid=744634 + + https://sourceforge.net/tracker/?func=detail&aid=2992847&group_id=139814&atid=744634 + +** Writing clock drivers + + Clock drivers include include/linux/ptp_clock_kernel.h and register + themselves by presenting a 'struct ptp_clock_info' to the + registration method. Clock drivers must implement all of the + functions in the interface. If a clock does not offer a particular + ancillary feature, then the driver should just return -EOPNOTSUPP + from those functions. + + Drivers must ensure that all of the methods in interface are + reentrant. Since most hardware implementations treat the time value + as a 64 bit integer accessed as two 32 bit registers, drivers + should use spin_lock_irqsave/spin_unlock_irqrestore to protect + against concurrent access. This locking cannot be accomplished in + class driver, since the lock may also be needed by the clock + driver's interrupt service routine. + +** Supported hardware + + + Standard Linux system timer + - No special PTP features + - For use with software time stamping + + + Freescale eTSEC gianfar + - 2 Time stamp external triggers, programmable polarity (op
[PATCH v3 2/3] ptp: Added a clock that uses the Linux system time.
This PTP clock simply uses the NTP time adjustment system calls. The
driver can be used in systems that lack a special hardware PTP clock.
Signed-off-by: Richard Cochran
---
drivers/ptp/Kconfig | 12
drivers/ptp/Makefile|1 +
drivers/ptp/ptp_linux.c | 136 +++
kernel/time/ntp.c |2 +
4 files changed, 151 insertions(+), 0 deletions(-)
create mode 100644 drivers/ptp/ptp_linux.c
diff --git a/drivers/ptp/Kconfig b/drivers/ptp/Kconfig
index c80a25b..9390d44 100644
--- a/drivers/ptp/Kconfig
+++ b/drivers/ptp/Kconfig
@@ -23,4 +23,16 @@ config PTP_1588_CLOCK
To compile this driver as a module, choose M here: the module
will be called ptp_clock.
+config PTP_1588_CLOCK_LINUX
+ tristate "Linux system timer as PTP clock"
+ depends on PTP_1588_CLOCK
+ help
+ This driver adds support for using the standard Linux time
+ source as a PTP clock. This clock is only useful if your PTP
+ programs are using software time stamps for the PTP Ethernet
+ packets.
+
+ To compile this driver as a module, choose M here: the module
+ will be called ptp_linux.
+
endmenu
diff --git a/drivers/ptp/Makefile b/drivers/ptp/Makefile
index b86695c..1651d52 100644
--- a/drivers/ptp/Makefile
+++ b/drivers/ptp/Makefile
@@ -3,3 +3,4 @@
#
obj-$(CONFIG_PTP_1588_CLOCK) += ptp_clock.o
+obj-$(CONFIG_PTP_1588_CLOCK_LINUX) += ptp_linux.o
diff --git a/drivers/ptp/ptp_linux.c b/drivers/ptp/ptp_linux.c
new file mode 100644
index 000..f0dbfc6
--- /dev/null
+++ b/drivers/ptp/ptp_linux.c
@@ -0,0 +1,136 @@
+/*
+ * PTP 1588 clock using the Linux system clock
+ *
+ * Copyright (C) 2010 OMICRON electronics GmbH
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
+ */
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+#include
+
+static struct ptp_clock *linux_clock;
+
+DEFINE_SPINLOCK(adjtime_lock);
+
+static int ptp_linux_adjfreq(void *priv, s32 delta)
+{
+ struct timex txc;
+ s64 tmp = delta;
+ int err;
+ txc.freq = div_s64(tmp<<16, 1000);
+ txc.modes = ADJ_FREQUENCY;
+ err = do_adjtimex(&txc);
+ return err < 0 ? err : 0;
+}
+
+static int ptp_linux_adjtime(void *priv, struct timespec *ts)
+{
+ s64 delta;
+ ktime_t now;
+ struct timespec t2;
+ unsigned long flags;
+ int err;
+
+ delta = 10LL * ts->tv_sec + ts->tv_nsec;
+
+ spin_lock_irqsave(&adjtime_lock, flags);
+
+ now = ktime_get_real();
+
+ now = delta < 0 ? ktime_sub_ns(now,-delta) : ktime_add_ns(now,delta);
+
+ t2 = ktime_to_timespec(now);
+
+ err = do_settimeofday(&t2);
+
+ spin_unlock_irqrestore(&adjtime_lock, flags);
+
+ return err;
+}
+
+static int ptp_linux_gettime(void *priv, struct timespec *ts)
+{
+ getnstimeofday(ts);
+ return 0;
+}
+
+static int ptp_linux_settime(void *priv, struct timespec *ts)
+{
+ return do_settimeofday(ts);
+}
+
+static int ptp_linux_gettimer(void *priv, int index, struct itimerspec *ts)
+{
+ /* We do not offer any ancillary features at all. */
+ return -EOPNOTSUPP;
+}
+
+static int ptp_linux_settimer(void *p, int i, int abs, struct itimerspec *ts)
+{
+ /* We do not offer any ancillary features at all. */
+ return -EOPNOTSUPP;
+}
+
+static int ptp_linux_enable(void *priv, struct ptp_clock_request *rq, int on)
+{
+ /* We do not offer any ancillary features at all. */
+ return -EOPNOTSUPP;
+}
+
+static struct ptp_clock_info ptp_linux_caps = {
+ .owner = THIS_MODULE,
+ .name = "Linux timer",
+ .max_adj= 512000,
+ .n_alarm= 0,
+ .n_ext_ts = 0,
+ .n_per_out = 0,
+ .pps= 0,
+ .priv = NULL,
+ .adjfreq= ptp_linux_adjfreq,
+ .adjtime= ptp_linux_adjtime,
+ .gettime= ptp_linux_gettime,
+ .settime= ptp_linux_settime,
+ .gettimer = ptp_linux_gettimer,
+ .settimer = ptp_linux_settimer,
+ .enable = ptp_linux_enable,
+};
+
+/* module operations */
+
+static void __exit ptp_linux_
[PATCH v3 3/3] ptp: Added a clock that uses the eTSEC found on the MPC85xx.
The eTSEC includes a PTP clock with quite a few features. This patch adds
support for the basic clock adjustment functions, plus two external time
stamps and one alarm.
Signed-off-by: Richard Cochran
---
Documentation/powerpc/dts-bindings/fsl/tsec.txt | 56 +++
arch/powerpc/boot/dts/mpc8313erdb.dts | 14 +
arch/powerpc/boot/dts/p2020ds.dts | 14 +
arch/powerpc/boot/dts/p2020rdb.dts | 14 +
drivers/net/Makefile|1 +
drivers/net/gianfar_ptp.c | 521 +++
drivers/net/gianfar_ptp_reg.h | 113 +
drivers/ptp/Kconfig | 13 +
8 files changed, 746 insertions(+), 0 deletions(-)
create mode 100644 drivers/net/gianfar_ptp.c
create mode 100644 drivers/net/gianfar_ptp_reg.h
diff --git a/Documentation/powerpc/dts-bindings/fsl/tsec.txt
b/Documentation/powerpc/dts-bindings/fsl/tsec.txt
index edb7ae1..b09ba66 100644
--- a/Documentation/powerpc/dts-bindings/fsl/tsec.txt
+++ b/Documentation/powerpc/dts-bindings/fsl/tsec.txt
@@ -74,3 +74,59 @@ Example:
interrupt-parent = <&mpic>;
phy-handle = <&phy0>
};
+
+* Gianfar PTP clock nodes
+
+General Properties:
+
+ - device_type Should be "ptp_clock"
+ - modelModel of the device. Must be "eTSEC"
+ - reg Offset and length of the register set for the device
+ - interrupts There should be at least two and as many as four
+ PTP related interrupts
+
+Clock Properties:
+
+ - tclk_period Timer reference clock period in nanoseconds.
+ - tmr_prsc Prescaler, divides the output clock.
+ - tmr_add Frequency compensation value.
+ - cksel0= external clock, 1= eTSEC system clock, 3= RTC clock input.
+ Currently the driver only supports choice "1".
+ - tmr_fiper1 Fixed interval period pulse generator.
+ - tmr_fiper2 Fixed interval period pulse generator.
+
+ These properties set the operational parameters for the PTP
+ clock. You must choose these carefully for the clock to work right.
+ Here is how to figure good values:
+
+ TimerOsc = system clock MHz
+ tclk_period = desired clock period nanoseconds
+ NominalFreq = 1000 / tclk_period MHz
+ FreqDivRatio = TimerOsc / NominalFreq (must be greater that 1.0)
+ tmr_add = ceil(2^32 / FreqDivRatio)
+ OutputClock = NominalFreq / tmr_prsc MHz
+ PulseWidth = 1 / OutputClockmicroseconds
+ FiperFreq1 = desired frequency in Hz
+ FiperDiv1= 100 * OutputClock / FiperFreq1
+ tmr_fiper1 = tmr_prsc * tclk_period * FiperDiv1 - tclk_period
+
+ The calculation for tmr_fiper2 is the same as for tmr_fiper1. The
+ driver expects that tmr_fiper1 will be correctly set to produce a 1
+ Pulse Per Second (PPS) signal, since this will be offered to the PPS
+ subsystem to synchronize the Linux clock.
+
+Example:
+
+ ptp_cl...@24e00 {
+ device_type = "ptp_clock";
+ model = "eTSEC";
+ reg = <0x24E00 0xB0>;
+ interrupts = <12 0x8 13 0x8>;
+ interrupt-parent = < &ipic >;
+ tclk_period = <10>;
+ tmr_prsc= <100>;
+ tmr_add = <0x99A4>;
+ cksel = <0x1>;
+ tmr_fiper1 = <0x3B9AC9F6>;
+ tmr_fiper2 = <0x00018696>;
+ };
diff --git a/arch/powerpc/boot/dts/mpc8313erdb.dts
b/arch/powerpc/boot/dts/mpc8313erdb.dts
index 183f2aa..6be6b16 100644
--- a/arch/powerpc/boot/dts/mpc8313erdb.dts
+++ b/arch/powerpc/boot/dts/mpc8313erdb.dts
@@ -208,6 +208,20 @@
sleep = <&pmc 0x0030>;
};
+ ptp_cl...@24e00 {
+ device_type = "ptp_clock";
+ model = "eTSEC";
+ reg = <0x24E00 0xB0>;
+ interrupts = <12 0x8 13 0x8>;
+ interrupt-parent = < &ipic >;
+ tclk_period = <10>;
+ tmr_prsc= <100>;
+ tmr_add = <0x99A4>;
+ cksel = <0x1>;
+ tmr_fiper1 = <0x3B9AC9F6>;
+ tmr_fiper2 = <0x00018696>;
+ };
+
enet0: ether...@24000 {
#address-cells = <1>;
#size-cells = <1>;
diff --git a/arch/powerpc/boot/dts/p2020ds.dts
b/arch/powerpc/boot/dts/p2020ds.dts
index 1101914..f72353a 100644
--- a/arch/powerpc/boot/dts/p2020ds.dts
+++ b/arch/powerpc/boot/dts/p2020ds.dts
@@ -336,6 +336,20 @@
phy_type = "ulpi";
Re: [PATCH v3 3/3] ptp: Added a clock that uses the eTSEC found on the MPC85xx.
On Fri, May 14, 2010 at 12:46:57PM -0500, Scott Wood wrote:
> On 05/14/2010 11:46 AM, Richard Cochran wrote:
> >diff --git a/Documentation/powerpc/dts-bindings/fsl/tsec.txt
> >b/Documentation/powerpc/dts-bindings/fsl/tsec.txt
>
> Get rid of both device_type and model, and specify a compatible
> string instead (e.g. "fsl,etsec-ptp").
Okay, will do. I really am at a loss at understanding all the rules in
the whole device tree world. I just tried to follow
Documentation/powerpc and what is already present in the kernel.
> Or perhaps this should just be some additional properties on the
> existing gianfar nodes, rather than presenting it as a separate
> device? How do you associate a given ptp block with the
> corresponding gianfar node?
There only one PTP clock. Its registers repeat in each port's memory
space, but you are only supposed to touch the first set of PTP
registers. If you consider how PTP works, there can never be per port
clocks, since this would make it impossible to make a boundary clock,
for example.
The whole idea of this PTP clock framework is to keep the clock
drivers separate from the MAC drivers, even when they use the same
hardware. The functionality is logically divided into two parts. The
MAC provides time stamps, and the clock provides a way to control its
offset and frequency.
Up until this point, people have simply hacked new private ioctls into
the driver for each MAC that supports PTP. That is not a good long
term solution for PTP support in Linux.
In general, I think it will not be hard to keep the MAC and the clock
drivers from stepping on each other's toes. The eTSEC hardware is
certainly able to be used in this way.
> If there are differences in ptp implementation between different
> versions of etsec, can the ptp driver see the etsec version
> register?
There are no differences (that I know of) in how the PTP clocks
work. I have in house the mpc8313, the mpc8572, and the p2020. The
mpc8572 appears to lack some of the TMR_CTRL bits, but this is
probably a documentation bug. I will check it.
> >+ - tclk_period Timer reference clock period in nanoseconds.
> >+ - tmr_prsc Prescaler, divides the output clock.
> >+ - tmr_add Frequency compensation value.
> >+ - cksel0= external clock, 1= eTSEC system clock, 3= RTC clock
> >input.
> >+ Currently the driver only supports choice "1".
> >+ - tmr_fiper1 Fixed interval period pulse generator.
> >+ - tmr_fiper2 Fixed interval period pulse generator.
>
> Dashes are more typical in OF names than underscores, and it's
> generally better to be a little more verbose -- these aren't local
> loop iterators.
The names come from the register mnemonics from the documentation. I
prefer to use the same names as is found in the manuals. That way, a
person working with docu in hand will have an easier job.
> They should probably have an "fsl,ptp-" prefix as well.
Okay, but must I then change the following code in order to find them?
Does adding the prefix just mean that I also add it to my search
strings, or is it preprocessed (stripped) somehow?
static int get_of_u32(struct device_node *node, char *str, u32 *val)
{
int plen;
const u32 *prop = of_get_property(node, str, &plen);
if (!prop || plen != sizeof(*prop))
return -1;
*val = *prop;
return 0;
}
...
if (get_of_u32(node, "tclk_period",&etsects->tclk_period) ||
get_of_u32(node, "tmr_prsc",&etsects->tmr_prsc) ||
get_of_u32(node, "tmr_add",&etsects->tmr_add) ||
get_of_u32(node, "cksel",&etsects->cksel) ||
get_of_u32(node, "tmr_fiper1",&etsects->tmr_fiper1) ||
get_of_u32(node, "tmr_fiper2",&etsects->tmr_fiper2))
return -ENODEV;
> >+ These properties set the operational parameters for the PTP
> >+ clock. You must choose these carefully for the clock to work right.
>
> Do these values describe the way the hardware is, or how it's been
> configured by firmware, or a set of values that are clearly optimal
> for this particular board? If it's just configuration for the Linux
> driver, that could reasonably differ based on what a given user or
> OS will want, the device tree probably isn't the right place for it.
The values are related to the board. One important parameter is the
input clock, and the rest reflect some engineering decisions/tradeoffs
related to the signals to and from the PTP clock. There is not just
one "optimal" choice, so I wanted to let the designer set the
values. In any case, the parameters are definitely related to the
board (not to the cpu or to linux), so I think t
Re: [PATCH v3 3/3] ptp: Added a clock that uses the eTSEC found on the MPC85xx.
On Mon, May 17, 2010 at 01:05:54PM -0500, Scott Wood wrote: > >>> >+ - tmr_fiper1 Fixed interval period pulse generator. > >>> >+ - tmr_fiper2 Fixed interval period pulse generator. > >> > > MPC8572 and P2020 have fiper3 as well. I doubt they really have a third fiper. First of all, this signal is not routed anywhere on the boards. Also, according to the documentation, it has no bit in the TMR_CTRL or the TMR_TEMASK registers. Unless there is a bit in TMR_TEMASK, you cannot get an interrupt from it. If you cannot use the signal externally (in the "real" world) and you cannot get an interrupt, what good is it to have such a periodic signal? Polling the bit in the TMR_TEVENT to see when a pulse occurs seems pointless. Scott, you have connections, right? Can you clarify this for me? Thanks, Richard ___ Linuxppc-dev mailing list Linuxppc-dev@lists.ozlabs.org https://lists.ozlabs.org/listinfo/linuxppc-dev
Re: [PATCH] gianfar: Revive the driver for eTSEC devices (disable timestamping)
On Wed, Jun 09, 2010 at 11:32:19PM +0400, Anton Vorontsov wrote:
> Since commit cc772ab7cdcaa24d1fae332d92a1602788644f7a ("gianfar: Add
> hardware RX timestamping support"), the driver no longer works on
> at least MPC8313ERDB and MPC8568EMDS boards (and possibly much more
> boards as well).
What do you mean by, "no longer works?" The driver works fine for us,
even without TMR_CTRL[TE] set. We tested the driver on two MPC8313ERDB
REV C boards, one P2020DS, and one P2020RDB.
> That's how MPC8313 Reference Manual describes RCTRL_TS_ENABLE bit:
>
> Timestamp incoming packets as padding bytes. PAL field is set
> to 8 if the PAL field is programmed to less than 8. Must be set
> to zero if TMR_CTRL[TE]=0.
>
> I see that the commit above sets this bit, but it doesn't handle
> TMR_CTRL. Manfred probably had this bit set by the firmware for
> his boards. But obviously this isn't true for all boards in the
> wild.
No, we did not set TMR_CTRL[TE].
For the Rx timestamps, we simply enabled them unconditionally. The
effect of not setting TMR_CTRL[TE] was that the timestamps were
invalid, but that should not matter if user space has not configured
the PTP clock. We left the TMR_CTRL[TE] bit for the PTP clock driver
(recently submitted and discussed on netdev). Actually, I copy the PTP
clock driver to the target via 'scp' during development, and I never
had any trouble.
> Also, I recall that Freescale BSPs were explicitly disabling the
> timestamping because of a performance drop.
The BSPs that we have, for the MPC8313ERDB and the P2020RBD both
include a (hacky) PTP timestmaping driver. Can you be more specific
about where and when Freescale is disabling timestamping?
> For now, the best way to deal with this is just disable the
> timestamping, and later we can discuss proper device tree bindings
> and implement enabling this feature via some property.
Okay, but now we want to identify what exactly works and what not. As
mentioned, we tested this driver on four different boards and did not
see any problems.
Thanks,
Richard
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Re: [PATCH] gianfar: Revive the driver for eTSEC devices (disable timestamping)
On Thu, Jun 10, 2010 at 01:31:59PM +0400, Anton Vorontsov wrote: > > No, we did not set TMR_CTRL[TE]. > > So, you deliberately violate the spec and expect it to work > everywhere? :-) Sometimes one must read the manual with a grain of salt ;) > > > Also, I recall that Freescale BSPs were explicitly disabling the > > > timestamping because of a performance drop. > > > > The BSPs that we have, for the MPC8313ERDB and the P2020RBD both > > include a (hacky) PTP timestmaping driver. Can you be more specific > > about where and when Freescale is disabling timestamping? > > Well, bitshrine site no longer allows[1] to list patches at > http://www.bitshrine.org/gpp/ , but there was a patch for sure. > > I'll try to find it in a bunch of .iso files that I have on disk > tho. Thanks, that will help to track the problem down. > U-Boot 1.1.6 (Oct 9 2007 - 20:42:39) MPC83XX ... > CPU: MPC8313E, Rev: 10 at 333.333 MHz We have a newer CPU revision: U-Boot 1.3.0 (Dec 23 2008 - 13:38:14) MPC83XX CPU: e300c3, MPC8313E, Rev: 21 at 333.333 MHz, CSB: 166 MHz Perhaps a bug was fixed between revision 10 and 21... You mentioned having trouble on the MPC8568EMDS. Was it the same problem? Thanks, Richard ___ Linuxppc-dev mailing list Linuxppc-dev@lists.ozlabs.org https://lists.ozlabs.org/listinfo/linuxppc-dev
[PATCH] powerpc: fix obsolete device tree code for the UPM NAND driver.
Commit 58f9b0b02414062eaff46716bc04b47d7e79add5 removed of_device->node.
This driver was apparently overlooked in the processes.
Signed-off-by: Richard Cochran
---
drivers/mtd/nand/fsl_upm.c | 18 ++
1 files changed, 10 insertions(+), 8 deletions(-)
diff --git a/drivers/mtd/nand/fsl_upm.c b/drivers/mtd/nand/fsl_upm.c
index 00aea6f..81ec87a 100644
--- a/drivers/mtd/nand/fsl_upm.c
+++ b/drivers/mtd/nand/fsl_upm.c
@@ -232,7 +232,7 @@ static int __devinit fun_probe(struct of_device *ofdev,
if (!fun)
return -ENOMEM;
- ret = of_address_to_resource(ofdev->node, 0, &io_res);
+ ret = of_address_to_resource(ofdev->dev.of_node, 0, &io_res);
if (ret) {
dev_err(&ofdev->dev, "can't get IO base\n");
goto err1;
@@ -244,7 +244,8 @@ static int __devinit fun_probe(struct of_device *ofdev,
goto err1;
}
- prop = of_get_property(ofdev->node, "fsl,upm-addr-offset", &size);
+ prop = of_get_property(ofdev->dev.of_node,
+ "fsl,upm-addr-offset", &size);
if (!prop || size != sizeof(uint32_t)) {
dev_err(&ofdev->dev, "can't get UPM address offset\n");
ret = -EINVAL;
@@ -252,7 +253,8 @@ static int __devinit fun_probe(struct of_device *ofdev,
}
fun->upm_addr_offset = *prop;
- prop = of_get_property(ofdev->node, "fsl,upm-cmd-offset", &size);
+ prop = of_get_property(ofdev->dev.of_node,
+ "fsl,upm-cmd-offset", &size);
if (!prop || size != sizeof(uint32_t)) {
dev_err(&ofdev->dev, "can't get UPM command offset\n");
ret = -EINVAL;
@@ -260,7 +262,7 @@ static int __devinit fun_probe(struct of_device *ofdev,
}
fun->upm_cmd_offset = *prop;
- prop = of_get_property(ofdev->node,
+ prop = of_get_property(ofdev->dev.of_node,
"fsl,upm-addr-line-cs-offsets", &size);
if (prop && (size / sizeof(uint32_t)) > 0) {
fun->mchip_count = size / sizeof(uint32_t);
@@ -276,7 +278,7 @@ static int __devinit fun_probe(struct of_device *ofdev,
for (i = 0; i < fun->mchip_count; i++) {
fun->rnb_gpio[i] = -1;
- rnb_gpio = of_get_gpio(ofdev->node, i);
+ rnb_gpio = of_get_gpio(ofdev->dev.of_node, i);
if (rnb_gpio >= 0) {
ret = gpio_request(rnb_gpio, dev_name(&ofdev->dev));
if (ret) {
@@ -292,13 +294,13 @@ static int __devinit fun_probe(struct of_device *ofdev,
}
}
- prop = of_get_property(ofdev->node, "chip-delay", NULL);
+ prop = of_get_property(ofdev->dev.of_node, "chip-delay", NULL);
if (prop)
fun->chip_delay = *prop;
else
fun->chip_delay = 50;
- prop = of_get_property(ofdev->node, "fsl,upm-wait-flags", &size);
+ prop = of_get_property(ofdev->dev.of_node, "fsl,upm-wait-flags", &size);
if (prop && size == sizeof(uint32_t))
fun->wait_flags = *prop;
else
@@ -315,7 +317,7 @@ static int __devinit fun_probe(struct of_device *ofdev,
fun->dev = &ofdev->dev;
fun->last_ctrl = NAND_CLE;
- ret = fun_chip_init(fun, ofdev->node, &io_res);
+ ret = fun_chip_init(fun, ofdev->dev.of_node, &io_res);
if (ret)
goto err2;
--
1.6.3.3
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[PATCH v4 00/12] ptp: IEEE 1588 clock support
Now and again there has been talk on the netdev list of adding PTP
support into Linux. One part of the picture is already in place, the
SO_TIMESTAMPING API for hardware time stamping. This patch set offers
the missing second part needed for complete IEEE 1588 support.
The only feature still to be implemented is the hook into the PPS
subsystem, to synchronize the Linux clock to the PTP clock.
The first seven patches concern phylib. A new generation of PHYs with
timestamping capabilities is appearing on the market. In order to
support hardware timestamping on these devices in Linux, a number of
adjustments will have to be made in the PHY subsystem. The reasons for
the changes are explained inline at the top of the patches.
The last five patches provide the PTP subsystem itself.
* Why all the CCs?
1. The patches probably should go through netdev.
2. One driver is for PowerPC, and adds device tree stuff.
3. One driver is for the ARM Xscale IXP465
* Open Issues:
** DP83640
In order to make this work, three lines must be added into the MAC
driver. Since this PHY can be connected to almost any MAC, I did
not do anything about that. If you have the DP83640 and want to try
the driver, you need to add three lines to your MAC driver.
1. Before mdio_register, add
bus->locktype = MDIOBUS_ATOMIC_RW;
2. In the .ndo_start_xmit function, add
skb_tx_timestamp()
3. In the NAPI poll function, add
skb_rx_timestamp()
** IXP465
I do not know how to correctly choose the timestamp "channel" based
on the port identifier:
#define PORT2CHANNEL(p) 1
/*
* PHYSICAL_ID(p->id) ?
* TODO - Figure out correct mapping.
*/
* Patch ChangeLog
** v4
*** general
- Added a clock driver for the National Semiconductor PHYTER.
- Added a clock driver for the Intel IXP465.
- Made more stylish according to checkstyle.pl.
*** gianfar
- Replace device_type and model with compatible string ("fsl,etsec-ptp")
- Register only one interrupt, since others are superfluous.
- Combine ptp clock instance with private variable structure.
- ISR now returns NONE or HANDLED properly.
- Print error message if something is missing from the device nodes.
** v3
*** general
- Added documentation on writing clock drivers.
- Added the ioctls for the ancillary clock features.
- Changed wrong subsys_initcall() to module_init() in clock drivers.
- Removed the (too coarse) character device mutex.
- Setting the clock now requires CAP_SYS_TIME.
*** gianfar
- Added alarm feature.
- Added device tree node binding description.
- Added fine grain locking of the clock registers.
- Added the external time stamp feature.
- Added white space for better style.
- Coverted base+offset to structure pointers for register access.
- When removing the driver, we now disable all PTP functions.
** v2
- Changed clock list from a static array into a dynamic list. Also,
use a bitmap to manage the clock's minor numbers.
- Replaced character device semaphore with a mutex.
- Drop .ko from module names in Kbuild help.
- Replace deprecated unifdef-y with header-y for user space header file.
- Added links to both of the ptpd patches on sourceforge.
- Gianfar driver now gets parameters from device tree.
- Added API documentation to Documentation/ptp/ptp.txt
Looking forward to your feedback,
Richard
Richard Cochran (12):
phylib: preserve ifreq parameter when calling generic phy_mii_ioctl()
phylib: do not filter phy_mii_ioctl()
phylib: add a driver method for the SIOCSHWTSTAMP ioctl.
phylib: add a way to make PHY time stamps possible.
phylib: Allow reading and writing a mii bus from atomic context.
ptp: add a BPF to help drivers detect PTP packets.
phylib: support the National Semiconductor DP83640 PHY.
ptp: Added a brand new class driver for ptp clocks.
ptp: Added a clock that uses the Linux system time.
ptp: Added a clock that uses the eTSEC found on the MPC85xx.
ptp: Added a clock driver for the IXP46x.
ptp: Added a clock driver for the National Semiconductor PHYTER.
Documentation/powerpc/dts-bindings/fsl/tsec.txt | 54 ++
Documentation/ptp/ptp.txt | 95
Documentation/ptp/testptp.c | 269 ++
Documentation/ptp/testptp.mk| 33 ++
arch/arm/mach-ixp4xx/include/mach/ixp46x_ts.h | 67 +++
arch/powerpc/boot/dts/mpc8313erdb.dts | 13 +
arch/powerpc/boot/dts/p2020ds.dts | 13 +
arch/powerpc/boot/dts/p2020rdb.dts | 13 +
drivers/Kconfig |2 +
drivers/Makefile|1 +
drivers/net/Makefile|1 +
drivers/net/arm/ixp4xx_eth.c| 197 -
drivers/net/au1000_eth.c
[PATCH 01/12] phylib: preserve ifreq parameter when calling generic phy_mii_ioctl()
The phy_mii_ioctl() function unnecessarily throws away the original ifreq.
We need access to the ifreq in order to support PHYs that can perform
hardware time stamping.
Signed-off-by: Richard Cochran
---
drivers/net/arm/ixp4xx_eth.c |3 ++-
drivers/net/au1000_eth.c |2 +-
drivers/net/bcm63xx_enet.c |2 +-
drivers/net/cpmac.c|2 +-
drivers/net/dnet.c |2 +-
drivers/net/ethoc.c|2 +-
drivers/net/fec.c |2 +-
drivers/net/fec_mpc52xx.c |2 +-
drivers/net/fs_enet/fs_enet-main.c |3 +--
drivers/net/gianfar.c |2 +-
drivers/net/macb.c |2 +-
drivers/net/mv643xx_eth.c |2 +-
drivers/net/octeon/octeon_mgmt.c |2 +-
drivers/net/phy/phy.c |3 ++-
drivers/net/sb1250-mac.c |2 +-
drivers/net/sh_eth.c |2 +-
drivers/net/smsc911x.c |2 +-
drivers/net/smsc9420.c |2 +-
drivers/net/stmmac/stmmac_main.c |2 +-
drivers/net/tc35815.c |2 +-
drivers/net/tg3.c |2 +-
drivers/staging/octeon/ethernet-mdio.c |2 +-
include/linux/phy.h|2 +-
net/dsa/slave.c|3 +--
24 files changed, 26 insertions(+), 26 deletions(-)
diff --git a/drivers/net/arm/ixp4xx_eth.c b/drivers/net/arm/ixp4xx_eth.c
index ee2f842..4f1cc71 100644
--- a/drivers/net/arm/ixp4xx_eth.c
+++ b/drivers/net/arm/ixp4xx_eth.c
@@ -782,7 +782,8 @@ static int eth_ioctl(struct net_device *dev, struct ifreq
*req, int cmd)
if (!netif_running(dev))
return -EINVAL;
- return phy_mii_ioctl(port->phydev, if_mii(req), cmd);
+
+ return phy_mii_ioctl(port->phydev, req, cmd);
}
/* ethtool support */
diff --git a/drivers/net/au1000_eth.c b/drivers/net/au1000_eth.c
index ece6128..386d4fe 100644
--- a/drivers/net/au1000_eth.c
+++ b/drivers/net/au1000_eth.c
@@ -978,7 +978,7 @@ static int au1000_ioctl(struct net_device *dev, struct
ifreq *rq, int cmd)
if (!aup->phy_dev)
return -EINVAL; /* PHY not controllable */
- return phy_mii_ioctl(aup->phy_dev, if_mii(rq), cmd);
+ return phy_mii_ioctl(aup->phy_dev, rq, cmd);
}
static const struct net_device_ops au1000_netdev_ops = {
diff --git a/drivers/net/bcm63xx_enet.c b/drivers/net/bcm63xx_enet.c
index faf5add..0d2c5da 100644
--- a/drivers/net/bcm63xx_enet.c
+++ b/drivers/net/bcm63xx_enet.c
@@ -1496,7 +1496,7 @@ static int bcm_enet_ioctl(struct net_device *dev, struct
ifreq *rq, int cmd)
if (priv->has_phy) {
if (!priv->phydev)
return -ENODEV;
- return phy_mii_ioctl(priv->phydev, if_mii(rq), cmd);
+ return phy_mii_ioctl(priv->phydev, rq, cmd);
} else {
struct mii_if_info mii;
diff --git a/drivers/net/cpmac.c b/drivers/net/cpmac.c
index 3c58db5..d4c5ca4 100644
--- a/drivers/net/cpmac.c
+++ b/drivers/net/cpmac.c
@@ -848,7 +848,7 @@ static int cpmac_ioctl(struct net_device *dev, struct ifreq
*ifr, int cmd)
return -EINVAL;
if ((cmd == SIOCGMIIPHY) || (cmd == SIOCGMIIREG) ||
(cmd == SIOCSMIIREG))
- return phy_mii_ioctl(priv->phy, if_mii(ifr), cmd);
+ return phy_mii_ioctl(priv->phy, ifr, cmd);
return -EOPNOTSUPP;
}
diff --git a/drivers/net/dnet.c b/drivers/net/dnet.c
index 8b0f50b..4ea7141 100644
--- a/drivers/net/dnet.c
+++ b/drivers/net/dnet.c
@@ -797,7 +797,7 @@ static int dnet_ioctl(struct net_device *dev, struct ifreq
*rq, int cmd)
if (!phydev)
return -ENODEV;
- return phy_mii_ioctl(phydev, if_mii(rq), cmd);
+ return phy_mii_ioctl(phydev, rq, cmd);
}
static void dnet_get_drvinfo(struct net_device *dev,
diff --git a/drivers/net/ethoc.c b/drivers/net/ethoc.c
index 6ed2df1..8102f01 100644
--- a/drivers/net/ethoc.c
+++ b/drivers/net/ethoc.c
@@ -734,7 +734,7 @@ static int ethoc_ioctl(struct net_device *dev, struct ifreq
*ifr, int cmd)
phy = priv->phy;
}
- return phy_mii_ioctl(phy, mdio, cmd);
+ return phy_mii_ioctl(phy, ifr, cmd);
}
static int ethoc_config(struct net_device *dev, struct ifmap *map)
diff --git a/drivers/net/fec.c b/drivers/net/fec.c
index a3cae4e..f24f49e 100644
--- a/drivers/net/fec.c
+++ b/drivers/net/fec.c
@@ -828,7 +828,7 @@ static int fec_enet_ioctl(struct net_device *dev, struct
ifreq *rq, int cmd)
if (!phydev)
return -ENODEV;
- return phy_mii_ioctl(phydev, if_mii(rq), cmd);
+ return phy_mii_ioctl(phydev, rq, cmd);
}
static void fec_enet_free_buffers(struct net_device *dev)
diff --git a/drivers/net/fec_mpc52xx.c b/drivers/net/fec_mpc52xx.c
index 25e6c
[PATCH 02/12] phylib: do not filter phy_mii_ioctl()
Two maverick drivers filter the ioctl commands passed to phy_mii_ioctl().
This is unnecessary since phylib will check the command in any case.
Signed-off-by: Richard Cochran
---
drivers/net/cpmac.c |5 +
drivers/net/stmmac/stmmac_main.c | 22 --
2 files changed, 9 insertions(+), 18 deletions(-)
diff --git a/drivers/net/cpmac.c b/drivers/net/cpmac.c
index d4c5ca4..0e47ca1 100644
--- a/drivers/net/cpmac.c
+++ b/drivers/net/cpmac.c
@@ -846,11 +846,8 @@ static int cpmac_ioctl(struct net_device *dev, struct
ifreq *ifr, int cmd)
return -EINVAL;
if (!priv->phy)
return -EINVAL;
- if ((cmd == SIOCGMIIPHY) || (cmd == SIOCGMIIREG) ||
- (cmd == SIOCSMIIREG))
- return phy_mii_ioctl(priv->phy, ifr, cmd);
- return -EOPNOTSUPP;
+ return phy_mii_ioctl(priv->phy, ifr, cmd);
}
static int cpmac_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
diff --git a/drivers/net/stmmac/stmmac_main.c b/drivers/net/stmmac/stmmac_main.c
index 6af7471..acf0616 100644
--- a/drivers/net/stmmac/stmmac_main.c
+++ b/drivers/net/stmmac/stmmac_main.c
@@ -1437,24 +1437,18 @@ static void stmmac_poll_controller(struct net_device
*dev)
static int stmmac_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
{
struct stmmac_priv *priv = netdev_priv(dev);
- int ret = -EOPNOTSUPP;
+ int ret;
if (!netif_running(dev))
return -EINVAL;
- switch (cmd) {
- case SIOCGMIIPHY:
- case SIOCGMIIREG:
- case SIOCSMIIREG:
- if (!priv->phydev)
- return -EINVAL;
-
- spin_lock(&priv->lock);
- ret = phy_mii_ioctl(priv->phydev, rq, cmd);
- spin_unlock(&priv->lock);
- default:
- break;
- }
+ if (!priv->phydev)
+ return -EINVAL;
+
+ spin_lock(&priv->lock);
+ ret = phy_mii_ioctl(priv->phydev, rq, cmd);
+ spin_unlock(&priv->lock);
+
return ret;
}
--
1.6.3.3
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[PATCH 03/12] phylib: add a driver method for the SIOCSHWTSTAMP ioctl.
This patch adds a phy driver method for configuring hardware time stamping.
Drivers may optionally implement this function.
Signed-off-by: Richard Cochran
---
drivers/net/phy/phy.c |5 +
include/linux/phy.h |3 +++
2 files changed, 8 insertions(+), 0 deletions(-)
diff --git a/drivers/net/phy/phy.c b/drivers/net/phy/phy.c
index bd88d81..5130db8 100644
--- a/drivers/net/phy/phy.c
+++ b/drivers/net/phy/phy.c
@@ -361,6 +361,11 @@ int phy_mii_ioctl(struct phy_device *phydev,
}
break;
+ case SIOCSHWTSTAMP:
+ if (phydev->drv->hwtstamp)
+ return phydev->drv->hwtstamp(phydev, ifr);
+ /* fall through */
+
default:
return -EOPNOTSUPP;
}
diff --git a/include/linux/phy.h b/include/linux/phy.h
index d63736a..a5e9df1 100644
--- a/include/linux/phy.h
+++ b/include/linux/phy.h
@@ -402,6 +402,9 @@ struct phy_driver {
/* Clears up any memory if needed */
void (*remove)(struct phy_device *phydev);
+ /* Handles SIOCSHWTSTAMP ioctl for hardware time stamping. */
+ int (*hwtstamp)(struct phy_device *phydev, struct ifreq *ifr);
+
struct device_driver driver;
};
#define to_phy_driver(d) container_of(d, struct phy_driver, driver)
--
1.6.3.3
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[PATCH 04/12] phylib: add a way to make PHY time stamps possible.
This patch adds a new networking option to allow hardware time stamps
from PHY devices. Using PHY time stamps will still require adding two
inline function calls to each MAC driver. The CONFIG option makes these
calls safe to add, since the calls become NOOPs when the option is
disabled.
Signed-off-by: Richard Cochran
---
include/linux/phy.h|4
include/linux/skbuff.h | 32
net/Kconfig| 11 +++
3 files changed, 47 insertions(+), 0 deletions(-)
diff --git a/include/linux/phy.h b/include/linux/phy.h
index a5e9df1..7a8caac 100644
--- a/include/linux/phy.h
+++ b/include/linux/phy.h
@@ -234,6 +234,8 @@ enum phy_state {
PHY_RESUMING
};
+struct sk_buff;
+
/* phy_device: An instance of a PHY
*
* drv: Pointer to the driver for this PHY instance
@@ -404,6 +406,8 @@ struct phy_driver {
/* Handles SIOCSHWTSTAMP ioctl for hardware time stamping. */
int (*hwtstamp)(struct phy_device *phydev, struct ifreq *ifr);
+ int (*rxtstamp)(struct phy_device *phydev, struct sk_buff *skb);
+ int (*txtstamp)(struct phy_device *phydev, struct sk_buff *skb);
struct device_driver driver;
};
diff --git a/include/linux/skbuff.h b/include/linux/skbuff.h
index 645e78d..7b650d4 100644
--- a/include/linux/skbuff.h
+++ b/include/linux/skbuff.h
@@ -29,6 +29,7 @@
#include
#include
#include
+#include
/* Don't change this without changing skb_csum_unnecessary! */
#define CHECKSUM_NONE 0
@@ -1942,6 +1943,37 @@ static inline ktime_t net_invalid_timestamp(void)
extern void skb_tstamp_tx(struct sk_buff *orig_skb,
struct skb_shared_hwtstamps *hwtstamps);
+#ifdef CONFIG_NETWORK_PHY_TIMESTAMPING
+
+static inline void skb_tx_timetamp(struct phy_device *phy, struct sk_buff *skb)
+{
+ union skb_shared_tx *shtx = skb_tx(skb);
+
+ if (shtx->hardware && phy && phy->drv->txtstamp)
+ phy->drv->txtstamp(phy, skb);
+
+ if (shtx->software && !shtx->in_progress)
+ skb_tstamp_tx(skb, NULL);
+}
+
+static inline void skb_rx_timetamp(struct phy_device *phy, struct sk_buff *skb)
+{
+ if (phy && phy->drv->rxtstamp)
+ phy->drv->rxtstamp(phy, skb);
+}
+
+#else /* CONFIG_NETWORK_PHY_TIMESTAMPING */
+
+static inline void skb_tx_timetamp(struct phy_device *phy, struct sk_buff *skb)
+{
+}
+
+static inline void skb_rx_timetamp(struct phy_device *phy, struct sk_buff *skb)
+{
+}
+
+#endif /* !CONFIG_NETWORK_PHY_TIMESTAMPING */
+
extern __sum16 __skb_checksum_complete_head(struct sk_buff *skb, int len);
extern __sum16 __skb_checksum_complete(struct sk_buff *skb);
diff --git a/net/Kconfig b/net/Kconfig
index 0d68b40..3fa7ae3 100644
--- a/net/Kconfig
+++ b/net/Kconfig
@@ -86,6 +86,17 @@ config NETWORK_SECMARK
to nfmark, but designated for security purposes.
If you are unsure how to answer this question, answer N.
+config NETWORK_PHY_TIMESTAMPING
+ bool "Timestamping in PHY devices"
+ depends on EXPERIMENTAL
+ help
+ This allows timestamping of network packets by PHYs with
+ hardware timestamping capabilities. This option adds some
+ overhead in the transmit and receive paths. Note that this
+ option also requires support in the MAC driver.
+
+ If you are unsure how to answer this question, answer N.
+
menuconfig NETFILTER
bool "Network packet filtering framework (Netfilter)"
---help---
--
1.6.3.3
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[PATCH 05/12] phylib: Allow reading and writing a mii bus from atomic context.
In order to support hardware time stamping from a PHY, it is necessary to
read from the PHY while running in_interrupt(). This patch allows a mii
bus to operate in an atomic context. An mii_bus driver may declare itself
capable for this mode. Drivers which do not do this will remain with the
default that bus operations may sleep.
Signed-off-by: Richard Cochran
---
drivers/net/phy/mdio_bus.c | 35 ---
include/linux/phy.h| 13 +++--
2 files changed, 39 insertions(+), 9 deletions(-)
diff --git a/drivers/net/phy/mdio_bus.c b/drivers/net/phy/mdio_bus.c
index 6a6b819..441be7d 100644
--- a/drivers/net/phy/mdio_bus.c
+++ b/drivers/net/phy/mdio_bus.c
@@ -36,6 +36,22 @@
#include
#include
+static inline void mdiobus_lock(struct mii_bus *bus)
+{
+ if (MDIOBUS_SLEEPS_RW == bus->locktype)
+ mutex_lock(&bus->mdio_lock.m);
+ else
+ spin_lock(&bus->mdio_lock.s);
+}
+
+static inline void mdiobus_unlock(struct mii_bus *bus)
+{
+ if (MDIOBUS_SLEEPS_RW == bus->locktype)
+ mutex_unlock(&bus->mdio_lock.m);
+ else
+ spin_unlock(&bus->mdio_lock.s);
+}
+
/**
* mdiobus_alloc - allocate a mii_bus structure
*
@@ -107,7 +123,10 @@ int mdiobus_register(struct mii_bus *bus)
return -EINVAL;
}
- mutex_init(&bus->mdio_lock);
+ if (MDIOBUS_SLEEPS_RW == bus->locktype)
+ mutex_init(&bus->mdio_lock.m);
+ else
+ spin_lock_init(&bus->mdio_lock.s);
if (bus->reset)
bus->reset(bus);
@@ -212,11 +231,12 @@ int mdiobus_read(struct mii_bus *bus, int addr, u32
regnum)
{
int retval;
- BUG_ON(in_interrupt());
+ if (MDIOBUS_SLEEPS_RW == bus->locktype)
+ BUG_ON(in_interrupt());
- mutex_lock(&bus->mdio_lock);
+ mdiobus_lock(bus);
retval = bus->read(bus, addr, regnum);
- mutex_unlock(&bus->mdio_lock);
+ mdiobus_unlock(bus);
return retval;
}
@@ -237,11 +257,12 @@ int mdiobus_write(struct mii_bus *bus, int addr, u32
regnum, u16 val)
{
int err;
- BUG_ON(in_interrupt());
+ if (MDIOBUS_SLEEPS_RW == bus->locktype)
+ BUG_ON(in_interrupt());
- mutex_lock(&bus->mdio_lock);
+ mdiobus_lock(bus);
err = bus->write(bus, addr, regnum, val);
- mutex_unlock(&bus->mdio_lock);
+ mdiobus_unlock(bus);
return err;
}
diff --git a/include/linux/phy.h b/include/linux/phy.h
index 7a8caac..352b030 100644
--- a/include/linux/phy.h
+++ b/include/linux/phy.h
@@ -98,11 +98,20 @@ struct mii_bus {
int (*write)(struct mii_bus *bus, int phy_id, int regnum, u16 val);
int (*reset)(struct mii_bus *bus);
+ /* Indicates whether bus may be used from an atomic context. */
+ enum {
+ MDIOBUS_SLEEPS_RW,
+ MDIOBUS_ATOMIC_RW
+ } locktype;
+
/*
-* A lock to ensure that only one thing can read/write
+* A lock or mutex to ensure that only one thing can read/write
* the MDIO bus at a time
*/
- struct mutex mdio_lock;
+ union {
+ struct mutex m;
+ spinlock_t s;
+ } mdio_lock;
struct device *parent;
enum {
--
1.6.3.3
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[PATCH 06/12] ptp: add a BPF to help drivers detect PTP packets.
Certain kinds of hardware time stamping units in both MACs and PHYs have
the limitation that they can only time stamp PTP packets. Drivers for such
hardware are left with the task of correctly matching skbs to time stamps.
This patch adds a BPF that drivers can use to classify PTP packets when
needed.
Signed-off-by: Richard Cochran
---
include/linux/ptp_classify.h | 118 ++
1 files changed, 118 insertions(+), 0 deletions(-)
create mode 100644 include/linux/ptp_classify.h
diff --git a/include/linux/ptp_classify.h b/include/linux/ptp_classify.h
new file mode 100644
index 000..e68efc3
--- /dev/null
+++ b/include/linux/ptp_classify.h
@@ -0,0 +1,118 @@
+/*
+ * PTP 1588 support
+ *
+ * This file implements a BPF that recognizes PTP event messages.
+ *
+ * Copyright (C) 2010 OMICRON electronics GmbH
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
+ */
+
+#ifndef _PTP_CLASSIFY_H_
+#define _PTP_CLASSIFY_H_
+
+#include
+#include
+#include
+#ifdef __KERNEL__
+#include
+#else
+#include
+#endif
+
+#define PTP_CLASS_NONE 0x00 /* not a PTP event message */
+#define PTP_CLASS_V10x01 /* protocol version 1 */
+#define PTP_CLASS_V20x02 /* protocol version 2 */
+#define PTP_CLASS_VMASK 0x0f /* max protocol version is 15 */
+#define PTP_CLASS_IPV4 0x10 /* event in an IPV4 UDP packet */
+#define PTP_CLASS_IPV6 0x20 /* event in an IPV6 UDP packet */
+#define PTP_CLASS_L20x30 /* event in a L2 packet */
+#define PTP_CLASS_VLAN 0x40 /* event in a VLAN tagged L2 packet */
+#define PTP_CLASS_PMASK 0xf0 /* mask for the packet type field */
+
+#define PTP_CLASS_V1_IPV4 (PTP_CLASS_V1 | PTP_CLASS_IPV4)
+#define PTP_CLASS_V1_IPV6 (PTP_CLASS_V1 | PTP_CLASS_IPV6) /*probably DNE*/
+#define PTP_CLASS_V2_IPV4 (PTP_CLASS_V2 | PTP_CLASS_IPV4)
+#define PTP_CLASS_V2_IPV6 (PTP_CLASS_V2 | PTP_CLASS_IPV6)
+#define PTP_CLASS_V2_L2 (PTP_CLASS_V2 | PTP_CLASS_L2)
+#define PTP_CLASS_V2_VLAN (PTP_CLASS_V2 | PTP_CLASS_VLAN)
+
+#define PTP_EV_PORT 319
+
+#define OFF_ETYPE 12
+#define OFF_IHL14
+#define OFF_FRAG 20
+#define OFF_PROTO4 23
+#define OFF_NEXT 6
+#define OFF_UDP_DST2
+
+#define IP6_HLEN 40
+#define UDP_HLEN 8
+
+#define RELOFF_DST4(ETH_HLEN + OFF_UDP_DST)
+#define OFF_DST6 (ETH_HLEN + IP6_HLEN + OFF_UDP_DST)
+#define OFF_PTP6 (ETH_HLEN + IP6_HLEN + UDP_HLEN)
+
+#define OP_AND (BPF_ALU | BPF_AND | BPF_K)
+#define OP_JEQ (BPF_JMP | BPF_JEQ | BPF_K)
+#define OP_JSET(BPF_JMP | BPF_JSET | BPF_K)
+#define OP_LDB (BPF_LD | BPF_B| BPF_ABS)
+#define OP_LDH (BPF_LD | BPF_H| BPF_ABS)
+#define OP_LDHI(BPF_LD | BPF_H| BPF_IND)
+#define OP_LDX (BPF_LDX | BPF_B| BPF_MSH)
+#define OP_OR (BPF_ALU | BPF_OR | BPF_K)
+#define OP_RETA(BPF_RET | BPF_A)
+#define OP_RETK(BPF_RET | BPF_K)
+
+#define PTP_FILTER \
+ {OP_LDH,0, 0, OFF_ETYPE }, /* */ \
+ {OP_JEQ,0, 12, ETH_P_IP}, /* f goto L20 */ \
+ {OP_LDB,0, 0, OFF_PROTO4 }, /* */ \
+ {OP_JEQ,0, 9, IPPROTO_UDP }, /* f goto L10 */ \
+ {OP_LDH,0, 0, OFF_FRAG}, /* */ \
+ {OP_JSET, 7, 0, 0x1fff }, /* t goto L11 */ \
+ {OP_LDX,0, 0, OFF_IHL }, /* */ \
+ {OP_LDHI, 0, 0, RELOFF_DST4 }, /* */ \
+ {OP_JEQ,0, 4, PTP_EV_PORT }, /* f goto L12 */ \
+ {OP_LDHI, 0, 0, ETH_HLEN + UDP_HLEN }, /* */ \
+ {OP_AND,0, 0, PTP_CLASS_VMASK }, /* */ \
+ {OP_OR, 0, 0, PTP_CLASS_IPV4 }, /* */ \
+ {OP_RETA, 0, 0, 0 }, /* */ \
+/*L1x*/{OP_RETK, 0, 0, PTP_CLASS_NONE }, /*
*/ \
+/*L20*/{OP_JEQ,0, 9, ETH_P_IPV6 }, /* f goto
L40 */ \
+ {OP_LDB,0, 0, ETH_HLEN + OFF_NEXT }, /* */ \
+ {OP_JEQ,0, 6, IPPROTO_UDP }, /* f goto L30 */ \
+ {OP_LDH,0, 0, OFF_DST6
[PATCH 07/12] phylib: support the National Semiconductor DP83640 PHY.
This patch adds a driver for the DP83640. This device is one of a new
generation of PHYs able to time stamp PTP packets.
Signed-off-by: Richard Cochran
---
drivers/net/phy/Kconfig |5 +
drivers/net/phy/Makefile |1 +
drivers/net/phy/dp83640.c | 439 +
drivers/net/phy/dp83640_reg.h | 237 ++
4 files changed, 682 insertions(+), 0 deletions(-)
create mode 100644 drivers/net/phy/dp83640.c
create mode 100644 drivers/net/phy/dp83640_reg.h
diff --git a/drivers/net/phy/Kconfig b/drivers/net/phy/Kconfig
index a527e37..430cab1 100644
--- a/drivers/net/phy/Kconfig
+++ b/drivers/net/phy/Kconfig
@@ -77,6 +77,11 @@ config NATIONAL_PHY
---help---
Currently supports the DP83865 PHY.
+config DP83640_PHY
+ tristate "Driver for the National Semiconductor DP83640 PHYTER"
+ ---help---
+ Supports the DP83640 PHYTER with IEEE 1588 features.
+
config STE10XP
depends on PHYLIB
tristate "Driver for STMicroelectronics STe10Xp PHYs"
diff --git a/drivers/net/phy/Makefile b/drivers/net/phy/Makefile
index 13bebab..2333215 100644
--- a/drivers/net/phy/Makefile
+++ b/drivers/net/phy/Makefile
@@ -19,6 +19,7 @@ obj-$(CONFIG_FIXED_PHY) += fixed.o
obj-$(CONFIG_MDIO_BITBANG) += mdio-bitbang.o
obj-$(CONFIG_MDIO_GPIO)+= mdio-gpio.o
obj-$(CONFIG_NATIONAL_PHY) += national.o
+obj-$(CONFIG_DP83640_PHY) += dp83640.o
obj-$(CONFIG_STE10XP) += ste10Xp.o
obj-$(CONFIG_MICREL_PHY) += micrel.o
obj-$(CONFIG_MDIO_OCTEON) += mdio-octeon.o
diff --git a/drivers/net/phy/dp83640.c b/drivers/net/phy/dp83640.c
new file mode 100644
index 000..a3217ea
--- /dev/null
+++ b/drivers/net/phy/dp83640.c
@@ -0,0 +1,439 @@
+/*
+ * Driver for the National Semiconductor DP83640 PHYTER
+ *
+ * Copyright (C) 2010 OMICRON electronics GmbH
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
+ */
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+#include "dp83640_reg.h"
+
+#define DP83640_PHY_ID 0x20005ce1
+#define PAGESEL0x13
+#define LAYER4 0x02
+#define LAYER2 0x01
+#define MAX_RXTS 8
+
+struct rxts {
+ struct list_head list;
+ u64 ns;
+ unsigned long tmo;
+ u16 seqid;
+ u8 msgtype;
+ u16 hash;
+};
+
+struct dp83640_private {
+ int hwts_tx_en;
+ int hwts_rx_en;
+ int layer;
+ int version;
+ /* protects extended registers from concurrent access */
+ spinlock_t extreg_lock;
+ int page;
+ /* list of rx timestamps */
+ struct list_head rxts;
+ struct list_head pool;
+ struct rxts pool_data[MAX_RXTS];
+};
+
+/* globals */
+
+static struct sock_filter ptp_filter[] = {
+ PTP_FILTER
+};
+
+/* extended register access functions */
+
+static int ext_read(struct phy_device *phydev, int page, u32 regnum)
+{
+ struct dp83640_private *dp83640 = phydev->priv;
+ int val;
+
+ spin_lock(&dp83640->extreg_lock);
+
+ if (dp83640->page != page) {
+ phy_write(phydev, PAGESEL, page);
+ dp83640->page = page;
+ }
+ val = phy_read(phydev, regnum);
+
+ spin_unlock(&dp83640->extreg_lock);
+
+ return val;
+}
+
+static void ext_write(struct phy_device *phydev, int page, u32 regnum, u16 val)
+{
+ struct dp83640_private *dp83640 = phydev->priv;
+
+ spin_lock(&dp83640->extreg_lock);
+
+ if (dp83640->page != page) {
+ phy_write(phydev, PAGESEL, page);
+ dp83640->page = page;
+ }
+ phy_write(phydev, regnum, val);
+
+ spin_unlock(&dp83640->extreg_lock);
+}
+
+static int expired(struct rxts *rxts)
+{
+ return time_after(jiffies, rxts->tmo);
+}
+
+static int match(struct sk_buff *skb, unsigned int type, struct rxts *rxts)
+{
+ u16 *seqid;
+ u8 *msgtype, *data = skb->data;
+
+ switch (type) {
+ case PTP_CLASS_V1_IPV4:
+ msgtype = data + 42 + 32;
+ seqid = (u16 *)(data + 42 + 30);
+ break;
+ case PTP_CLASS_V1_IPV6:
+ msgtype = data
[PATCH 08/12] ptp: Added a brand new class driver for ptp clocks.
This patch adds an infrastructure for hardware clocks that implement IEEE 1588, the Precision Time Protocol (PTP). A class driver offers a registration method to particular hardware clock drivers. Each clock is exposed to user space as a character device with ioctls that allow tuning of the PTP clock. Signed-off-by: Richard Cochran --- Documentation/ptp/ptp.txt| 95 +++ Documentation/ptp/testptp.c | 269 Documentation/ptp/testptp.mk | 33 +++ drivers/Kconfig |2 + drivers/Makefile |1 + drivers/ptp/Kconfig | 26 ++ drivers/ptp/Makefile |5 + drivers/ptp/ptp_clock.c | 514 ++ include/linux/Kbuild |1 + include/linux/ptp_clock.h| 79 ++ include/linux/ptp_clock_kernel.h | 137 ++ 11 files changed, 1162 insertions(+), 0 deletions(-) create mode 100644 Documentation/ptp/ptp.txt create mode 100644 Documentation/ptp/testptp.c create mode 100644 Documentation/ptp/testptp.mk create mode 100644 drivers/ptp/Kconfig create mode 100644 drivers/ptp/Makefile create mode 100644 drivers/ptp/ptp_clock.c create mode 100644 include/linux/ptp_clock.h create mode 100644 include/linux/ptp_clock_kernel.h diff --git a/Documentation/ptp/ptp.txt b/Documentation/ptp/ptp.txt new file mode 100644 index 000..46858b3 --- /dev/null +++ b/Documentation/ptp/ptp.txt @@ -0,0 +1,95 @@ + +* PTP infrastructure for Linux + + This patch set introduces support for IEEE 1588 PTP clocks in + Linux. Together with the SO_TIMESTAMPING socket options, this + presents a standardized method for developing PTP user space + programs, synchronizing Linux with external clocks, and using the + ancillary features of PTP hardware clocks. + + A new class driver exports a kernel interface for specific clock + drivers and a user space interface. The infrastructure supports a + complete set of PTP functionality. + + + Basic clock operations +- Set time +- Get time +- Shift the clock by a given offset atomically +- Adjust clock frequency + + + Ancillary clock features +- One short or periodic alarms, with signal delivery to user program +- Time stamp external events +- Period output signals configurable from user space +- Synchronization of the Linux system time via the PPS subsystem + +** PTP kernel API + + A PTP clock driver registers itself with the class driver. The + class driver handles all of the dealings with user space. The + author of a clock driver need only implement the details of + programming the clock hardware. The clock driver notifies the class + driver of asynchronous events (alarms and external time stamps) via + a simple message passing interface. + + The class driver supports multiple PTP clock drivers. In normal use + cases, only one PTP clock is needed. However, for testing and + development, it can be useful to have more than one clock in a + single system, in order to allow performance comparisons. + +** PTP user space API + + The class driver creates a character device for each registered PTP + clock. User space programs may control the clock using standardized + ioctls. A program may query, enable, configure, and disable the + ancillary clock features. User space can receive time stamped + events via blocking read() and poll(). One shot and periodic + signals may be configured via an ioctl API with semantics similar + to the POSIX timer_settime() system call. + + As an real life example, the following two patches for ptpd version + 1.0.0 demonstrate how the API works. + + https://sourceforge.net/tracker/?func=detail&aid=2992845&group_id=139814&atid=744634 + + https://sourceforge.net/tracker/?func=detail&aid=2992847&group_id=139814&atid=744634 + +** Writing clock drivers + + Clock drivers include include/linux/ptp_clock_kernel.h and register + themselves by presenting a 'struct ptp_clock_info' to the + registration method. Clock drivers must implement all of the + functions in the interface. If a clock does not offer a particular + ancillary feature, then the driver should just return -EOPNOTSUPP + from those functions. + + Drivers must ensure that all of the methods in interface are + reentrant. Since most hardware implementations treat the time value + as a 64 bit integer accessed as two 32 bit registers, drivers + should use spin_lock_irqsave/spin_unlock_irqrestore to protect + against concurrent access. This locking cannot be accomplished in + class driver, since the lock may also be needed by the clock + driver's interrupt service routine. + +** Supported hardware + + + Standard Linux system timer + - No special PTP features + - For use with software time stamping + + + Freescale eTSEC gianfar + - 2 Time stamp external triggers, programmable polarity (op
[PATCH 09/12] ptp: Added a clock that uses the Linux system time.
This PTP clock simply uses the NTP time adjustment system calls. The
driver can be used in systems that lack a special hardware PTP clock.
Signed-off-by: Richard Cochran
---
drivers/ptp/Kconfig | 12
drivers/ptp/Makefile|1 +
drivers/ptp/ptp_linux.c | 136 +++
kernel/time/ntp.c |2 +
4 files changed, 151 insertions(+), 0 deletions(-)
create mode 100644 drivers/ptp/ptp_linux.c
diff --git a/drivers/ptp/Kconfig b/drivers/ptp/Kconfig
index c80a25b..9390d44 100644
--- a/drivers/ptp/Kconfig
+++ b/drivers/ptp/Kconfig
@@ -23,4 +23,16 @@ config PTP_1588_CLOCK
To compile this driver as a module, choose M here: the module
will be called ptp_clock.
+config PTP_1588_CLOCK_LINUX
+ tristate "Linux system timer as PTP clock"
+ depends on PTP_1588_CLOCK
+ help
+ This driver adds support for using the standard Linux time
+ source as a PTP clock. This clock is only useful if your PTP
+ programs are using software time stamps for the PTP Ethernet
+ packets.
+
+ To compile this driver as a module, choose M here: the module
+ will be called ptp_linux.
+
endmenu
diff --git a/drivers/ptp/Makefile b/drivers/ptp/Makefile
index b86695c..1651d52 100644
--- a/drivers/ptp/Makefile
+++ b/drivers/ptp/Makefile
@@ -3,3 +3,4 @@
#
obj-$(CONFIG_PTP_1588_CLOCK) += ptp_clock.o
+obj-$(CONFIG_PTP_1588_CLOCK_LINUX) += ptp_linux.o
diff --git a/drivers/ptp/ptp_linux.c b/drivers/ptp/ptp_linux.c
new file mode 100644
index 000..f93ae0c
--- /dev/null
+++ b/drivers/ptp/ptp_linux.c
@@ -0,0 +1,136 @@
+/*
+ * PTP 1588 clock using the Linux system clock
+ *
+ * Copyright (C) 2010 OMICRON electronics GmbH
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
+ */
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+#include
+
+static struct ptp_clock *linux_clock;
+
+DEFINE_SPINLOCK(adjtime_lock);
+
+static int ptp_linux_adjfreq(void *priv, s32 delta)
+{
+ struct timex txc;
+ s64 tmp = delta;
+ int err;
+ txc.freq = div_s64(tmp<<16, 1000);
+ txc.modes = ADJ_FREQUENCY;
+ err = do_adjtimex(&txc);
+ return err < 0 ? err : 0;
+}
+
+static int ptp_linux_adjtime(void *priv, struct timespec *ts)
+{
+ s64 delta;
+ ktime_t now;
+ struct timespec t2;
+ unsigned long flags;
+ int err;
+
+ delta = 10LL * ts->tv_sec + ts->tv_nsec;
+
+ spin_lock_irqsave(&adjtime_lock, flags);
+
+ now = ktime_get_real();
+
+ now = delta < 0 ? ktime_sub_ns(now, -delta) : ktime_add_ns(now, delta);
+
+ t2 = ktime_to_timespec(now);
+
+ err = do_settimeofday(&t2);
+
+ spin_unlock_irqrestore(&adjtime_lock, flags);
+
+ return err;
+}
+
+static int ptp_linux_gettime(void *priv, struct timespec *ts)
+{
+ getnstimeofday(ts);
+ return 0;
+}
+
+static int ptp_linux_settime(void *priv, struct timespec *ts)
+{
+ return do_settimeofday(ts);
+}
+
+static int ptp_linux_gettimer(void *priv, int index, struct itimerspec *ts)
+{
+ /* We do not offer any ancillary features at all. */
+ return -EOPNOTSUPP;
+}
+
+static int ptp_linux_settimer(void *p, int i, int abs, struct itimerspec *ts)
+{
+ /* We do not offer any ancillary features at all. */
+ return -EOPNOTSUPP;
+}
+
+static int ptp_linux_enable(void *priv, struct ptp_clock_request *rq, int on)
+{
+ /* We do not offer any ancillary features at all. */
+ return -EOPNOTSUPP;
+}
+
+static struct ptp_clock_info ptp_linux_caps = {
+ .owner = THIS_MODULE,
+ .name = "Linux timer",
+ .max_adj= 512000,
+ .n_alarm= 0,
+ .n_ext_ts = 0,
+ .n_per_out = 0,
+ .pps= 0,
+ .priv = NULL,
+ .adjfreq= ptp_linux_adjfreq,
+ .adjtime= ptp_linux_adjtime,
+ .gettime= ptp_linux_gettime,
+ .settime= ptp_linux_settime,
+ .gettimer = ptp_linux_gettimer,
+ .settimer = ptp_linux_settimer,
+ .enable = ptp_linux_enable,
+};
+
+/* module operations */
+
+static void __exi
[PATCH 10/12] ptp: Added a clock that uses the eTSEC found on the MPC85xx.
The eTSEC includes a PTP clock with quite a few features. This patch adds
support for the basic clock adjustment functions, plus two external time
stamps and one alarm.
Signed-off-by: Richard Cochran
---
Documentation/powerpc/dts-bindings/fsl/tsec.txt | 54 +++
arch/powerpc/boot/dts/mpc8313erdb.dts | 13 +
arch/powerpc/boot/dts/p2020ds.dts | 13 +
arch/powerpc/boot/dts/p2020rdb.dts | 13 +
drivers/net/Makefile|1 +
drivers/net/gianfar_ptp.c | 518 +++
drivers/net/gianfar_ptp_reg.h | 113 +
drivers/ptp/Kconfig | 13 +
8 files changed, 738 insertions(+), 0 deletions(-)
create mode 100644 drivers/net/gianfar_ptp.c
create mode 100644 drivers/net/gianfar_ptp_reg.h
diff --git a/Documentation/powerpc/dts-bindings/fsl/tsec.txt
b/Documentation/powerpc/dts-bindings/fsl/tsec.txt
index edb7ae1..14577e9 100644
--- a/Documentation/powerpc/dts-bindings/fsl/tsec.txt
+++ b/Documentation/powerpc/dts-bindings/fsl/tsec.txt
@@ -74,3 +74,57 @@ Example:
interrupt-parent = <&mpic>;
phy-handle = <&phy0>
};
+
+* Gianfar PTP clock nodes
+
+General Properties:
+
+ - compatible Should be "fsl,etsec-ptp"
+ - reg Offset and length of the register set for the device
+ - interrupts There should be at least two interrupts. Some devices
+ have as many as four PTP related interrupts.
+
+Clock Properties:
+
+ - tclk_period Timer reference clock period in nanoseconds.
+ - tmr_prsc Prescaler, divides the output clock.
+ - tmr_add Frequency compensation value.
+ - cksel0= external clock, 1= eTSEC system clock, 3= RTC clock input.
+ Currently the driver only supports choice "1".
+ - tmr_fiper1 Fixed interval period pulse generator.
+ - tmr_fiper2 Fixed interval period pulse generator.
+
+ These properties set the operational parameters for the PTP
+ clock. You must choose these carefully for the clock to work right.
+ Here is how to figure good values:
+
+ TimerOsc = system clock MHz
+ tclk_period = desired clock period nanoseconds
+ NominalFreq = 1000 / tclk_period MHz
+ FreqDivRatio = TimerOsc / NominalFreq (must be greater that 1.0)
+ tmr_add = ceil(2^32 / FreqDivRatio)
+ OutputClock = NominalFreq / tmr_prsc MHz
+ PulseWidth = 1 / OutputClockmicroseconds
+ FiperFreq1 = desired frequency in Hz
+ FiperDiv1= 100 * OutputClock / FiperFreq1
+ tmr_fiper1 = tmr_prsc * tclk_period * FiperDiv1 - tclk_period
+
+ The calculation for tmr_fiper2 is the same as for tmr_fiper1. The
+ driver expects that tmr_fiper1 will be correctly set to produce a 1
+ Pulse Per Second (PPS) signal, since this will be offered to the PPS
+ subsystem to synchronize the Linux clock.
+
+Example:
+
+ ptp_cl...@24e00 {
+ compatible = "fsl,etsec-ptp";
+ reg = <0x24E00 0xB0>;
+ interrupts = <12 0x8 13 0x8>;
+ interrupt-parent = < &ipic >;
+ tclk_period = <10>;
+ tmr_prsc= <100>;
+ tmr_add = <0x99A4>;
+ cksel = <0x1>;
+ tmr_fiper1 = <0x3B9AC9F6>;
+ tmr_fiper2 = <0x00018696>;
+ };
diff --git a/arch/powerpc/boot/dts/mpc8313erdb.dts
b/arch/powerpc/boot/dts/mpc8313erdb.dts
index 183f2aa..0526384 100644
--- a/arch/powerpc/boot/dts/mpc8313erdb.dts
+++ b/arch/powerpc/boot/dts/mpc8313erdb.dts
@@ -208,6 +208,19 @@
sleep = <&pmc 0x0030>;
};
+ ptp_cl...@24e00 {
+ compatible = "fsl,etsec-ptp";
+ reg = <0x24E00 0xB0>;
+ interrupts = <12 0x8 13 0x8>;
+ interrupt-parent = < &ipic >;
+ tclk_period = <10>;
+ tmr_prsc= <100>;
+ tmr_add = <0x99A4>;
+ cksel = <0x1>;
+ tmr_fiper1 = <0x3B9AC9F6>;
+ tmr_fiper2 = <0x00018696>;
+ };
+
enet0: ether...@24000 {
#address-cells = <1>;
#size-cells = <1>;
diff --git a/arch/powerpc/boot/dts/p2020ds.dts
b/arch/powerpc/boot/dts/p2020ds.dts
index 1101914..ae5dc4d 100644
--- a/arch/powerpc/boot/dts/p2020ds.dts
+++ b/arch/powerpc/boot/dts/p2020ds.dts
@@ -336,6 +336,19 @@
phy_type = "ulpi";
};
+ ptp_cl...@24e00 {
+ compatible = "fsl,etsec-ptp";
+
[PATCH 11/12] ptp: Added a clock driver for the IXP46x.
This patch adds a driver for the hardware time stamping unit found on the
IXP465. Only the basic clock operations are implemented.
Signed-off-by: Richard Cochran
---
arch/arm/mach-ixp4xx/include/mach/ixp46x_ts.h | 67 +++
drivers/net/arm/ixp4xx_eth.c | 194 +
drivers/ptp/Kconfig | 13 ++
drivers/ptp/Makefile |1 +
drivers/ptp/ptp_ixp46x.c | 231 +
5 files changed, 506 insertions(+), 0 deletions(-)
create mode 100644 arch/arm/mach-ixp4xx/include/mach/ixp46x_ts.h
create mode 100644 drivers/ptp/ptp_ixp46x.c
diff --git a/arch/arm/mach-ixp4xx/include/mach/ixp46x_ts.h
b/arch/arm/mach-ixp4xx/include/mach/ixp46x_ts.h
new file mode 100644
index 000..7fb02b6
--- /dev/null
+++ b/arch/arm/mach-ixp4xx/include/mach/ixp46x_ts.h
@@ -0,0 +1,67 @@
+/*
+ * PTP 1588 clock using the IXP46X
+ *
+ * Copyright (C) 2010 OMICRON electronics GmbH
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
+ */
+
+#ifndef _IXP46X_TS_H_
+#define _IXP46X_TS_H_
+
+#define DEFAULT_ADDEND 0xF029
+#define TICKS_NS_SHIFT 4
+
+struct ixp46x_channel_ctl {
+ u32 Ch_Control; /* 0x40 Time Synchronization Channel Control */
+ u32 Ch_Event; /* 0x44 Time Synchronization Channel Event */
+ u32 TxSnapLo; /* 0x48 Transmit Snapshot Low Register */
+ u32 TxSnapHi; /* 0x4C Transmit Snapshot High Register */
+ u32 RxSnapLo; /* 0x50 Receive Snapshot Low Register */
+ u32 RxSnapHi; /* 0x54 Receive Snapshot High Register */
+ u32 SrcUUIDLo; /* 0x58 Source UUID0 Low Register */
+ u32 SrcUUIDHi; /* 0x5C Sequence Identifier/Source UUID0 High */
+};
+
+struct ixp46x_ts_regs {
+ u32 Control; /* 0x00 Time Sync Control Register */
+ u32 Event; /* 0x04 Time Sync Event Register */
+ u32 Addend; /* 0x08 Time Sync Addend Register */
+ u32 Accum; /* 0x0C Time Sync Accumulator Register */
+ u32 Test;/* 0x10 Time Sync Test Register */
+ u32 Unused; /* 0x14 */
+ u32 RSysTime_Lo; /* 0x18 RawSystemTime_Low Register */
+ u32 RSysTimeHi; /* 0x1C RawSystemTime_High Register */
+ u32 SysTimeLo; /* 0x20 SystemTime_Low Register */
+ u32 SysTimeHi; /* 0x24 SystemTime_High Register */
+ u32 TrgtLo; /* 0x28 TargetTime_Low Register */
+ u32 TrgtHi; /* 0x2C TargetTime_High Register */
+ u32 ASMSLo; /* 0x30 Auxiliary Slave Mode Snapshot Low */
+ u32 ASMSHi; /* 0x34 Auxiliary Slave Mode Snapshot High */
+ u32 AMMSLo; /* 0x38 Auxiliary Master Mode Snapshot Low */
+ u32 AMMSHi; /* 0x3C Auxiliary Master Mode Snapshot High */
+
+ struct ixp46x_channel_ctl channel[3];
+};
+
+/* 0x40 Time Synchronization Channel Control Register Bits */
+#define MASTER_MODE (1<<0)
+#define TIMESTAMP_ALL (1<<1)
+
+/* 0x44 Time Synchronization Channel Event Register Bits */
+#define TX_SNAPSHOT_LOCKED (1<<0)
+#define RX_SNAPSHOT_LOCKED (1<<1)
+
+#endif
diff --git a/drivers/net/arm/ixp4xx_eth.c b/drivers/net/arm/ixp4xx_eth.c
index 4f1cc71..2201960 100644
--- a/drivers/net/arm/ixp4xx_eth.c
+++ b/drivers/net/arm/ixp4xx_eth.c
@@ -30,9 +30,12 @@
#include
#include
#include
+#include
#include
#include
+#include
#include
+#include
#include
#include
@@ -67,6 +70,14 @@
#define RXFREE_QUEUE(port_id) (NPE_ID(port_id) + 26)
#define TXDONE_QUEUE 31
+#define PTP_SLAVE_MODE 1
+#define PTP_MASTER_MODE2
+#define PORT2CHANNEL(p)1
+/*
+ * PHYSICAL_ID(p->id) ?
+ * TODO - Figure out correct mapping.
+ */
+
/* TX Control Registers */
#define TX_CNTRL0_TX_EN0x01
#define TX_CNTRL0_HALFDUPLEX 0x02
@@ -171,6 +182,8 @@ struct port {
int id; /* logical port ID */
int speed, duplex;
u8 firmware[4];
+ int hwts_tx_en;
+ int hwts_rx_en;
};
/* NPE message structure */
@@ -246,6 +259,170 @@ static int ports_open;
static struct port *npe_port_tab[MAX_NPES];
static struct dma_pool *dma_pool;
+static struct sock_filter ptp_filter[] = {
+ PTP_FILTER
+};
+
+static int match(struct sk_buff *skb, u16 uid_hi, u32 uid_lo, u16 s
[PATCH 12/12] ptp: Added a clock driver for the National Semiconductor PHYTER.
This patch adds support for the PTP clock found on the DP83640. Only the
basic clock operations have been implemented.
Signed-off-by: Richard Cochran
---
drivers/net/phy/Kconfig | 11 +++
drivers/net/phy/dp83640.c | 158 -
2 files changed, 168 insertions(+), 1 deletions(-)
diff --git a/drivers/net/phy/Kconfig b/drivers/net/phy/Kconfig
index 430cab1..507c68a 100644
--- a/drivers/net/phy/Kconfig
+++ b/drivers/net/phy/Kconfig
@@ -79,9 +79,20 @@ config NATIONAL_PHY
config DP83640_PHY
tristate "Driver for the National Semiconductor DP83640 PHYTER"
+ depends on PTP_1588_CLOCK
+ depends on NETWORK_PHY_TIMESTAMPING
---help---
Supports the DP83640 PHYTER with IEEE 1588 features.
+ This driver adds support for using the DP83640 as a PTP
+ clock. This clock is only useful if your PTP programs are
+ getting hardware time stamps on the PTP Ethernet packets
+ using the SO_TIMESTAMPING API.
+
+ In order for this to work, your MAC driver must also
+ implement the the skb_tx_timetamp() and skb_rx_timetamp()
+ functions.
+
config STE10XP
depends on PHYLIB
tristate "Driver for STMicroelectronics STe10Xp PHYs"
diff --git a/drivers/net/phy/dp83640.c b/drivers/net/phy/dp83640.c
index a3217ea..21eadc3 100644
--- a/drivers/net/phy/dp83640.c
+++ b/drivers/net/phy/dp83640.c
@@ -26,6 +26,7 @@
#include
#include
#include
+#include
#include "dp83640_reg.h"
@@ -45,10 +46,13 @@ struct rxts {
};
struct dp83640_private {
+ struct phy_device *phydev;
int hwts_tx_en;
int hwts_rx_en;
int layer;
int version;
+ /* protects PTP_TDR register from concurrent access */
+ spinlock_t ptp_tdr_lock;
/* protects extended registers from concurrent access */
spinlock_t extreg_lock;
int page;
@@ -60,6 +64,9 @@ struct dp83640_private {
/* globals */
+static struct ptp_clock *dp83640_clock;
+DEFINE_SPINLOCK(clock_lock); /* protects the one and only dp83640_clock */
+
static struct sock_filter ptp_filter[] = {
PTP_FILTER
};
@@ -99,6 +106,129 @@ static void ext_write(struct phy_device *phydev, int page,
u32 regnum, u16 val)
spin_unlock(&dp83640->extreg_lock);
}
+static int tdr_write(struct dp83640_private *dp83640,
+struct timespec *ts, u16 cmd)
+{
+ struct phy_device *phydev = dp83640->phydev;
+
+ spin_lock(&dp83640->ptp_tdr_lock);
+
+ ext_write(phydev, PAGE4, PTP_TDR, ts->tv_nsec & 0x);/* ns[15:0] */
+ ext_write(phydev, PAGE4, PTP_TDR, ts->tv_nsec >> 16); /* ns[31:16] */
+ ext_write(phydev, PAGE4, PTP_TDR, ts->tv_sec & 0x); /* sec[15:0] */
+ ext_write(phydev, PAGE4, PTP_TDR, ts->tv_sec >> 16);/* sec[31:16] */
+
+ ext_write(phydev, PAGE4, PTP_CTL, cmd);
+
+ spin_unlock(&dp83640->ptp_tdr_lock);
+
+ return 0;
+}
+
+/* ptp clock methods */
+
+static int ptp_dp83640_adjfreq(void *priv, s32 ppb)
+{
+ struct dp83640_private *dp83640 = priv;
+ struct phy_device *phydev = dp83640->phydev;
+ u64 rate;
+ int neg_adj = 0;
+ u16 hi, lo;
+
+ if (!ppb)
+ return 0;
+
+ if (ppb < 0) {
+ neg_adj = 1;
+ ppb = -ppb;
+ }
+ rate = ppb;
+ rate <<= 26;
+ rate = div_u64(rate, 1953125);
+
+ hi = (rate >> 16) & PTP_RATE_HI_MASK;
+ if (neg_adj)
+ hi |= PTP_RATE_DIR;
+
+ lo = rate & 0x;
+
+ ext_write(phydev, PAGE4, PTP_RATEH, hi);
+ ext_write(phydev, PAGE4, PTP_RATEL, lo);
+
+ return 0;
+}
+
+static int ptp_dp83640_adjtime(void *priv, struct timespec *ts)
+{
+ return tdr_write(priv, ts, PTP_STEP_CLK);
+}
+
+static int ptp_dp83640_gettime(void *priv, struct timespec *ts)
+{
+ struct dp83640_private *dp83640 = priv;
+ struct phy_device *phydev = dp83640->phydev;
+ unsigned int val[4];
+
+ spin_lock(&dp83640->ptp_tdr_lock);
+
+ ext_write(phydev, PAGE4, PTP_CTL, PTP_RD_CLK);
+
+ val[0] = ext_read(phydev, PAGE4, PTP_TDR); /* ns[15:0] */
+ val[1] = ext_read(phydev, PAGE4, PTP_TDR); /* ns[31:16] */
+ val[2] = ext_read(phydev, PAGE4, PTP_TDR); /* sec[15:0] */
+ val[3] = ext_read(phydev, PAGE4, PTP_TDR); /* sec[31:16] */
+
+ spin_unlock(&dp83640->ptp_tdr_lock);
+
+ ts->tv_nsec = val[0] | (val[1] << 16);
+ ts->tv_sec = val[2] | (val[3] << 16);
+
+ return 0;
+}
+
+static int ptp_dp83640_settime(void *priv, struct timespec *ts)
+{
+ return tdr_write(priv, ts, PTP_LOAD_CLK);
+}
+
+static int ptp_dp83640_gettimer(void *priv, int index, struct itimerspec *ts)
+{
+ /* We do not (yet) offer any ancillary features. */
+ return -
Re: [PATCH 03/12] phylib: add a driver method for the SIOCSHWTSTAMP ioctl.
On Tue, Jun 15, 2010 at 10:27:59AM -0600, Grant Likely wrote: > On Tue, Jun 15, 2010 at 10:08 AM, Richard Cochran > wrote: > > This patch adds a phy driver method for configuring hardware time stamping. > > Drivers may optionally implement this function. > > > > Signed-off-by: Richard Cochran > > Adding an ioctl to the userspace ABI. Make sure you cc: linux-kernel > on the next spin of this series. Not sure what you mean. SIOCSHWTSTAMP is a standard socket option as of 2.6.30. The patch just makes it possible for PHY drivers to implement this option. Richard ___ Linuxppc-dev mailing list Linuxppc-dev@lists.ozlabs.org https://lists.ozlabs.org/listinfo/linuxppc-dev
Re: [PATCH 05/12] phylib: Allow reading and writing a mii bus from atomic context.
On Tue, Jun 15, 2010 at 10:43:08AM -0600, Grant Likely wrote: > On Tue, Jun 15, 2010 at 10:08 AM, Richard Cochran > wrote: > > In order to support hardware time stamping from a PHY, it is necessary to > > read from the PHY while running in_interrupt(). This patch allows a mii > > bus to operate in an atomic context. An mii_bus driver may declare itself > > capable for this mode. Drivers which do not do this will remain with the > > default that bus operations may sleep. > > > > Signed-off-by: Richard Cochran > > Last I checked, the MDIO bus is very slow. Is this really a good > idea? How much latency does MDIO access have on the hardware you are > working with? Yes, MDIO access is slow, and it can vary (eg bit banging implementations). It clear that getting PHY timestamps is costly, but for applications that want PTP synchronization, one is willing to pay the price. > I also don't like the idea of taking a spin lock during MDIO > operations, and the dual locking mode in the core code. Originally, the phylib used a spinlock for this. It was replaced with a mutex in 35b5f6b1a82b5c586e0b24c711dc6ba944e88ef1 in order to accommodate mdio busses that may need to sleep. So, keeping the option to use a spinlock is similar to the previous implementation. > I'd rather see separate atomic context hooks that doesn't obtain the > mutex under the assumption that the caller has already done so. If > the bus doesn't support atomic access, then it won't implement the > hooks and the core code should return an error. > > I've cc'd Thomas Gleixner. He might have a better idea about how to > implement what you're trying to do. Okay, I'm open to suggestions... Thanks, Richard ___ Linuxppc-dev mailing list Linuxppc-dev@lists.ozlabs.org https://lists.ozlabs.org/listinfo/linuxppc-dev
Re: [PATCH 04/12] phylib: add a way to make PHY time stamps possible.
On Tue, Jun 15, 2010 at 10:33:51AM -0600, Grant Likely wrote: > > +config NETWORK_PHY_TIMESTAMPING > Some overhead? At a brief glance of the series it looks like it could > add a lot of overhead, but I'm not fully clear on what the full > process is. Can you describe how the hardware timestamping works? I > could use an overview of what the kernel has to do. First of all, I want to emphasize that this network stack option is purely voluntary. Only those people who know that they have a PTP capable PHY and really want the timestamps will (or should) enable this option. When it is not enabled, it has no effect at all. Hardware timestamping is described in Documentation/networking/timestamping.txt Documentation/networking/timestamping/timestamping.c The PTP subsystem is described in Documentation/ptp/ptp.txt There really is more to say about the issue than appears in those documents, but they are a good starting place for discussion. BTW I am submitting a conference paper on the design on the PTP subsystem. If you would like to have it, just ask me off-list. Richard ___ Linuxppc-dev mailing list Linuxppc-dev@lists.ozlabs.org https://lists.ozlabs.org/listinfo/linuxppc-dev
Re: [PATCH 05/12] phylib: Allow reading and writing a mii bus from atomic context.
> That's right, and I fully agree with that change. To me, going back > to allowing spin locks is a regression because it adds a new source of > scheduling latency. I think that the change was not about reducing scheduling latency. Rather, the idea was simply to allow mdio bus drivers that sleep. Here is the change log message: commit 35b5f6b1a82b5c586e0b24c711dc6ba944e88ef1 PHYLIB: Locking fixes for PHY I/O potentially sleeping PHY read/write functions can potentially sleep (e.g., a PHY accessed via I2C). The following changes were made to account for this: * Change spin locks to mutex locks * Add a BUG_ON() to phy_read() phy_write() to warn against calling them from an interrupt context. * Use work queue for PHY state machine handling since it can potentially sleep * Change phydev lock from spinlock to mutex The fundamental issue is this: Fro the SO_TIMESTAMPING API, receive timestamps must appear in a control message along with the packet data. Only the MAC driver (or the PHY driver) knows how to get the timestamp. The stack calls the MAC driver via its napi poll function. During the call, the driver must provide the skb with Rx timestamp. The only reasonable way to do this is to have the driver fetch the timestamp durng the napi poll function. For MAC drivers with fast register access, the performance penalty is small. For PHY drivers with must go via the MDIO bus, the performance penalty is obviously larger, and the user must be willing to live with it. You might suggest the alternate that the driver would defer the netif_receive_skb() callback until a work queue completes, providing the Rx timestamp. The driver would then call netif_receive_skb() at some later time. However, there are a number of problems with this idea: 1. It is really icky for the drivers to be creating new skb queues for this purpose. MAC drivers would have to maintain such queues on behalf of the PHY drivers, but only when the PHYs support timestamping. Yuck. 2. There is a (soft) real time constraint on the delivery of the PTP packets to the user space application. Basicly, delays and jitter in the time to receive the packet negatively affect the clock servo loop. 3. It cannot work for many kinds of PTP timestamping hardware. Some of hardware only timestamps PTP packets. That means that not every received packet will have a timestamp. Such hardware provides some key data from the packet (like PTP UUID and sequence number) with the timestamp. Software must match this information to a particular packet. In order to defer a skb, the driver must first obtain the timestamp information. This is a catch-22. Having said all that, I am still open to suggestions... Richard ___ Linuxppc-dev mailing list Linuxppc-dev@lists.ozlabs.org https://lists.ozlabs.org/listinfo/linuxppc-dev
Re: [PATCH 04/12] phylib: add a way to make PHY time stamps possible.
On Tue, Jun 15, 2010 at 06:08:20PM +0200, Richard Cochran wrote:
> +static inline void skb_tx_timetamp(struct phy_device *phy, struct sk_buff
> *skb)
> +{
> + union skb_shared_tx *shtx = skb_tx(skb);
> +
> + if (shtx->hardware && phy && phy->drv->txtstamp)
> + phy->drv->txtstamp(phy, skb);
> +
> + if (shtx->software && !shtx->in_progress)
> + skb_tstamp_tx(skb, NULL);
> +}
I forgot to mention this patch also provides a way to fix the broken
software timestamp fallback mode of the SO_TIMESTAMPING API.
We would have to add this inline call to every MAC driver in an
appropriate spot within the hard_xmit function. It is not too pretty,
but providing this as a compile time option will promote
standardization of the SO_TIMESTAMPING API for applications.
Richard
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Re: [PATCH 10/12] ptp: Added a clock that uses the eTSEC found on the MPC85xx.
On Tue, Jun 15, 2010 at 11:20:41AM -0600, Grant Likely wrote:
>
> Is this header file used by anything other than gianfar_ptp.c? If
> not, then roll the two files together.
I anticipate that it might be necessary to share the header's contents
with gianfar.c one day.
> Use dash ('-') not underscore ('_') in property names.
Okay, can do.
> If you encode this value as a string, then it will be friendly for humans too.
Okay.
> I could use more explication here. Is this a divider value?
> Computers are good at making calculations, and the driver can obtain
> the clock frequency supplied to the device. It may be more useful to
> specify here the desired frequency rather than the divider. Certainly
> more human-friendly too.
It is not that simple. The basic algorithm is described in the text,
and anyone wanting to use the eTSEC for PTP will have to consider the
issue themselves, since it is a design issue with a few tradeoffs
related to the board layout. It is really too thorny to do in the
driver automatically.
I can post a tcltk calculator script for finding appropriate values,
in anyone would like to see it.
> > +static struct etsects the_clock;
>
> Will there ever be multiple instances of this device?
No, never. If you consider how PTP works, there can only be one clock
per system.
> Consider of_iomap(), it will simplify the code a bit.
> Move ptp_gianfar_exit() definition here so it is immediately before
> the module_exit() line.
Okay.
Thanks for the review,
Richard
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