Re: [PATCH -mm 18/43] powerpc compat_binfmt_elf

[Roland McGrath]

> On Thu, Dec 20, 2007 at 03:58:16AM -0800, Roland McGrath wrote:
> > +obj-$(CONFIG_PPC64)+= ../../../fs/compat_binfmt_elf.o
> 
> Building files from another directory is nasty.  Please add a
> CONFIG_BINFMT_COMPAT_ELF so we can simply build it in fs/

If that's better, please post the precise Kconfig magic you have in mind to
have it set when it should be.


Thanks,
Roland
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[PATCH 2/3] (Resend part #1) Add the RapidIO support to powerpc architecture with memory mapping support.

[Zhang Wei]

The patch adds the RapidIO support to powerpc with of-device support.
New Serial RapidIO of new Freescale processor, such as MPC8548, MPC8568,
is also added.

Signed-off-by: Zhang Wei <[EMAIL PROTECTED]>
---
 arch/powerpc/Kconfig|   12 +
 arch/powerpc/platforms/85xx/Kconfig |1 +
 arch/powerpc/platforms/86xx/Kconfig |1 +
 arch/powerpc/sysdev/Makefile|1 +
 arch/powerpc/sysdev/fsl_rio.c   | 1130 ++-
 5 files changed, 861 insertions(+), 284 deletions(-)

diff --git a/arch/powerpc/Kconfig b/arch/powerpc/Kconfig
index 18f397c..ee27b77 100644
--- a/arch/powerpc/Kconfig
+++ b/arch/powerpc/Kconfig
@@ -523,6 +523,18 @@ source "drivers/pci/Kconfig"
 
 source "drivers/pcmcia/Kconfig"
 
+config FSL_RAPIDIO
+   bool
+   default n
+
+config RAPIDIO
+   bool "RapidIO support" if FSL_RAPIDIO
+   help
+ If you say Y here, the kernel will include drivers and
+ infrastructure code to support RapidIO interconnect devices.
+
+source "drivers/rapidio/Kconfig"
+
 source "drivers/pci/hotplug/Kconfig"
 
 endmenu
diff --git a/arch/powerpc/platforms/85xx/Kconfig 
b/arch/powerpc/platforms/85xx/Kconfig
index 7748a3a..09c522d 100644
--- a/arch/powerpc/platforms/85xx/Kconfig
+++ b/arch/powerpc/platforms/85xx/Kconfig
@@ -56,6 +56,7 @@ config MPC85xx
select PPC_UDBG_16550
select PPC_INDIRECT_PCI if PCI
select MPIC
+   select FSL_RAPIDIO
select FSL_PCI if PCI
select SERIAL_8250_SHARE_IRQ if SERIAL_8250
default y if MPC8540_ADS || MPC85xx_CDS || MPC8560_ADS \
diff --git a/arch/powerpc/platforms/86xx/Kconfig 
b/arch/powerpc/platforms/86xx/Kconfig
index 21d1135..a6a6593 100644
--- a/arch/powerpc/platforms/86xx/Kconfig
+++ b/arch/powerpc/platforms/86xx/Kconfig
@@ -24,6 +24,7 @@ config MPC8641
select FSL_PCI if PCI
select PPC_UDBG_16550
select MPIC
+   select FSL_RAPIDIO
default y if MPC8641_HPCN
 
 config MPC8610
diff --git a/arch/powerpc/sysdev/Makefile b/arch/powerpc/sysdev/Makefile
index 99a77d7..073d197 100644
--- a/arch/powerpc/sysdev/Makefile
+++ b/arch/powerpc/sysdev/Makefile
@@ -12,6 +12,7 @@ obj-$(CONFIG_U3_DART) += dart_iommu.o
 obj-$(CONFIG_MMIO_NVRAM)   += mmio_nvram.o
 obj-$(CONFIG_FSL_SOC)  += fsl_soc.o
 obj-$(CONFIG_FSL_PCI)  += fsl_pci.o
+obj-$(CONFIG_FSL_RAPIDIO)  += fsl_rio.o
 obj-$(CONFIG_TSI108_BRIDGE)+= tsi108_pci.o tsi108_dev.o
 obj-$(CONFIG_QUICC_ENGINE) += qe_lib/
 obj-$(CONFIG_PPC_BESTCOMM) += bestcomm/
diff --git a/arch/powerpc/sysdev/fsl_rio.c b/arch/powerpc/sysdev/fsl_rio.c
index af2425e..525066c 100644
--- a/arch/powerpc/sysdev/fsl_rio.c
+++ b/arch/powerpc/sysdev/fsl_rio.c
@@ -1,5 +1,8 @@
 /*
- * MPC85xx RapidIO support
+ * Freescale PowerPC RapidIO support
+ *
+ * Copyright (C) 2007 Freescale Semiconductor, Inc. All rights reserved.
+ * Zhang Wei <[EMAIL PROTECTED]>, Jun 2007
  *
  * Copyright 2005 MontaVista Software, Inc.
  * Matt Porter <[EMAIL PROTECTED]>
@@ -8,6 +11,13 @@
  * under  the terms of  the GNU General  Public License as published by the
  * Free Software Foundation;  either version 2 of the  License, or (at your
  * option) any later version.
+ *
+ * Changelog:
+ * Jun 2007 Zhang Wei <[EMAIL PROTECTED]>
+ * - This file is moved from arch/ppc/ppc85xx_rio.c. And the OF-tree support
+ *   is added. New silicons such as MPC8548, MPC8641 are all supported.
+ *   Memory driver hardware operations are added.
+ *
  */
 
 #include 
@@ -17,14 +27,41 @@
 #include 
 #include 
 #include 
+#include 
+#include 
 
 #include 
+#include 
+#include "fsl_soc.h"
+
+/* RapidIO definition irq, which read from OF-tree */
+#define IRQ_RIO_BELL(m)(((struct rio_priv 
*)(m->priv))->bellirq)
+#define IRQ_RIO_TX(m)  (((struct rio_priv *)(m->priv))->txirq)
+#define IRQ_RIO_RX(m)  (((struct rio_priv *)(m->priv))->rxirq)
+
+#define ERR(fmt, arg...) \
+   printk(KERN_ERR "RIO %s: " fmt, __FUNCTION__, ## arg)
+#define INFO(fmt...) printk(KERN_INFO "RIO: " fmt)
+#define IS_64BIT_RES ((sizeof(resource_size_t) == 8) ? 1 : 0)
 
-#define RIO_REGS_BASE  (CCSRBAR + 0xc)
 #define RIO_ATMU_REGS_OFFSET   0x10c00
-#define RIO_MSG_REGS_OFFSET0x11000
+#define RIO_P_MSG_REGS_OFFSET  0x11000
+#define RIO_S_MSG_REGS_OFFSET  0x13000
+#define RIO_ESCSR  0x158
+#define RIO_CCSR   0x15c
+#define RIO_ISR_AACR   0x10120
+#define RIO_ISR_AACR_AA0x1 /* Accept All ID */
 #define RIO_MAINT_WIN_SIZE 0x40
 #define RIO_DBELL_WIN_SIZE 0x1000
+#define RIO_MAX_INB_ATMU   4
+#define RIO_MAX_OUTB_ATMU  8
+#define RIO_INB_ATMU_REGS_OFFSET   0x10de0
+#define RIO_ATMU_EN_MASK   0x8000
+
+#define RIO_NREAD  0x4
+#define RIO_NWRITE 0x4
+#define RIO_NWRITE_R   0x5
+#define RIO_NREAD_R0x5
 
 #define RIO_MSG_OMR_MUI0x0002
 #define RIO_MSG_OSR_TE  

[PATCH 2/3] (Resend part #2) Add RapidIO memory mapping API and simple Bitmap allocation.

[Zhang Wei]

Add RapidIO memory mapping API and simple Bitmap allocation with fixed size.
Some bugs are fixed.

Signed-off-by: Zhang Wei <[EMAIL PROTECTED]>
---
 drivers/rapidio/Kconfig |   18 +-
 drivers/rapidio/Makefile|1 +
 drivers/rapidio/rio-access.c|   10 +-
 drivers/rapidio/rio-scan.c  |   53 +++--
 drivers/rapidio/rio-sysfs.c |3 +-
 drivers/rapidio/rio.c   |  486 ++-
 drivers/rapidio/rio.h   |9 +-
 drivers/rapidio/sallocator/Kconfig  |9 +
 drivers/rapidio/sallocator/Makefile |   12 +
 drivers/rapidio/sallocator/bitmap.c |  383 +++
 10 files changed, 944 insertions(+), 40 deletions(-)
 create mode 100644 drivers/rapidio/sallocator/Kconfig
 create mode 100644 drivers/rapidio/sallocator/Makefile
 create mode 100644 drivers/rapidio/sallocator/bitmap.c

diff --git a/drivers/rapidio/Kconfig b/drivers/rapidio/Kconfig
index 4142115..f669108 100644
--- a/drivers/rapidio/Kconfig
+++ b/drivers/rapidio/Kconfig
@@ -1,14 +1,6 @@
 #
 # RapidIO configuration
 #
-config RAPIDIO_8_BIT_TRANSPORT
-   bool "8-bit transport addressing"
-   depends on RAPIDIO
-   ---help---
- By default, the kernel assumes a 16-bit addressed RapidIO
- network. By selecting this option, the kernel will support
- an 8-bit addressed network.
-
 config RAPIDIO_DISC_TIMEOUT
int "Discovery timeout duration (seconds)"
depends on RAPIDIO
@@ -16,3 +8,13 @@ config RAPIDIO_DISC_TIMEOUT
---help---
  Amount of time a discovery node waits for a host to complete
  enumeration before giving up.
+
+config RAPIDIO_PROC_FS
+   bool "I/O and Memory resource debug"
+   depends on RAPIDIO && PROC_FS
+   default y
+   ---help---
+ Enable this option, it will create a /proc/riores node for
+ monitoring the RapidIO I/O and Memory resource.
+
+source "drivers/rapidio/sallocator/Kconfig"
diff --git a/drivers/rapidio/Makefile b/drivers/rapidio/Makefile
index 7c0e181..e5b2f11 100644
--- a/drivers/rapidio/Makefile
+++ b/drivers/rapidio/Makefile
@@ -4,3 +4,4 @@
 obj-y += rio.o rio-access.o rio-driver.o rio-scan.o rio-sysfs.o
 
 obj-$(CONFIG_RAPIDIO)  += switches/
+obj-$(CONFIG_RAPIDIO)  += sallocator/
diff --git a/drivers/rapidio/rio-access.c b/drivers/rapidio/rio-access.c
index 8b56bbd..a3824ba 100644
--- a/drivers/rapidio/rio-access.c
+++ b/drivers/rapidio/rio-access.c
@@ -48,7 +48,7 @@ int __rio_local_read_config_##size \
u32 data = 0;   \
if (RIO_##size##_BAD) return RIO_BAD_SIZE;  \
spin_lock_irqsave(&rio_config_lock, flags); \
-   res = mport->ops->lcread(mport->id, offset, len, &data);\
+   res = mport->ops->lcread(mport, mport->id, offset, len, &data); \
*value = (type)data;\
spin_unlock_irqrestore(&rio_config_lock, flags);\
return res; \
@@ -71,7 +71,7 @@ int __rio_local_write_config_##size \
unsigned long flags;\
if (RIO_##size##_BAD) return RIO_BAD_SIZE;  \
spin_lock_irqsave(&rio_config_lock, flags); \
-   res = mport->ops->lcwrite(mport->id, offset, len, value);   \
+   res = mport->ops->lcwrite(mport, mport->id, offset, len, value);\
spin_unlock_irqrestore(&rio_config_lock, flags);\
return res; \
 }
@@ -108,7 +108,7 @@ int rio_mport_read_config_##size \
u32 data = 0;   \
if (RIO_##size##_BAD) return RIO_BAD_SIZE;  \
spin_lock_irqsave(&rio_config_lock, flags); \
-   res = mport->ops->cread(mport->id, destid, hopcount, offset, len, 
&data); \
+   res = mport->ops->cread(mport, mport->id, destid, hopcount, offset, 
len, &data); \
*value = (type)data;\
spin_unlock_irqrestore(&rio_config_lock, flags);\
return res; \
@@ -131,7 +131,7 @@ int rio_mport_write_config_##size \
unsigned long flags;\
if (RIO_##size##_BAD) return RIO_BAD_SIZE;  \
spin_lock_irqsave(&rio_config_lock, flags); \
-   res = mport->ops->cwrite(mport->id, destid, hopcount, offset, len, 
value); \
+   res = mport->ops->cwrite(mport, mport->id, destid, hopcount, offset, 
len, value); \
spin_unlock_irqrestore(&rio_config_lock, flags);\
return res; 

Bug#457294: [powerpc] System time not updated after sleep cycle

[Michel Dänzer]

Package: linux-2.6
Version: 2.6.23-1
Severity: important

-BEGIN PGP SIGNED MESSAGE-
Hash: SHA1


After wakeup from sleep, the system time is still the same as it was when going
to sleep. I have to restart ntp to get it updated.

This problem didn't occur with previous kernels. It persists in
2.6.23-2~snapshot.9949 but is fixed in
2.6.24~rc5-1~experimental.1~snapshot.9974 . I'm CC'ing the linuxppc-dev list on
this report in the hope that someone there remembers how this was fixed post
2.6.23 upstream and that the fix can hopefully be backported.


- -- System Information:
Debian Release: lenny/sid
  APT prefers unstable
  APT policy: (500, 'unstable'), (500, 'stable'), (102, 'experimental')
Architecture: powerpc (ppc)

Kernel: Linux 2.6.24-rc5-powerpc
Locale: LANG=de_CH.UTF-8, LC_CTYPE=de_CH.UTF-8 (charmap=UTF-8)
Shell: /bin/sh linked to /bin/bash

-BEGIN PGP SIGNATURE-
Version: GnuPG v1.4.6 (GNU/Linux)

iD8DBQFHa5O1WoGvjmrbsgARAjGpAJ0TaORdhlrDU1kYPDF7dpAvNK0s0ACfU4mX
erietOhcqZUjsxn+803CxXo=
=I/Op
-END PGP SIGNATURE-


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Re: [PATCH 20/21] [POWERPC] pci32: 4xx embedded platforms want to reassign all PCI resources

[Josh Boyer]

On Fri, 21 Dec 2007 15:39:37 +1100
Benjamin Herrenschmidt <[EMAIL PROTECTED]> wrote:

> Index: linux-merge/arch/powerpc/platforms/44x/sequoia.c
> ===
> --- linux-merge.orig/arch/powerpc/platforms/44x/sequoia.c 2007-12-14 
> 15:48:53.0 +1100
> +++ linux-merge/arch/powerpc/platforms/44x/sequoia.c  2007-12-14 
> 15:49:52.0 +1100
> @@ -21,7 +21,8 @@
>  #include 
>  #include 
>  #include 
> -#include "44x.h"
> +#include 
> +

This is still broken because you removed the 44x.h include.  I'll fix
it on my commit.

josh
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Re: [PATCH 18/21] [POWERPC] bamboo: remove bogus "ranges" property in EBC node

[Josh Boyer]

On Fri, 21 Dec 2007 15:39:35 +1100
Benjamin Herrenschmidt <[EMAIL PROTECTED]> wrote:

> This removes a bogus empty "ranges" property in the EBC device node
> of the Bamboo board device-tree.
> 
> The "ranges" property will be created by the boot wrapper, there is
> no need to have an empty property there, and that causes recent
> dtc to complain.

The wrapper doesn't do anything with EBC for bamboo because the EBC
stuff is a nightmare on this board.  The patch can stand, but I'll
fixup the comments in the changelog.

josh
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Yet more patches added to for-2.6.25/master branches

[Paul Mackerras]

Aegis Lin (1):
  [POWERPC] spufs: Use separate timer for /proc/spu_loadavg calculation

Andre Detsch (1):
  [POWERPC] spufs: DMA Restart after SIGSEGV

Arnd Bergmann (1):
  [POWERPC] spufs: block fault handlers in spu_acquire_runnable

Benjamin Herrenschmidt (2):
  [POWERPC] Fix for via-pmu based backlight control
  [POWERPC] Fix possible NULL deref in ppc32 PCI

Christoph Hellwig (2):
  [POWERPC] spufs: add enchanced simple attr macros
  [POWERPC] spufs: make state_mutex interruptible

Emil Medve (1):
  [POWERPC] Optimize counting distinct entries in the relocation sections

Jeremy Kerr (5):
  [POWERPC] spufs: move fault, lscsa_alloc and switch code to spufs module
  [POWERPC] spufs: fix incorrect interrupt status clearing in backing mbox 
stat poll
  [POWERPC] spufs: use #defines for SPU class [012] exception status
  [POWERPC] spufs: rework class 0 and 1 interrupt handling
  [POWERPC] spufs: Don't leak kernel stack through an empty {i,m}box_info 
read

Julio M. Merino Vidal (1):
  [POWERPC] spufs: fix typos in sched.c comments

Luke Browning (4):
  [POWERPC] spufs: add backing ops for privcntl register
  [POWERPC] spufs: reorganize spu_run_init
  [POWERPC] spufs: spu_find_victim may choose wrong victim
  [POWERPC] spufs: decouple spu scheduler from spufs_spu_run (asynchronous 
scheduling)

Masato Noguchi (2):
  [POWERPC] cell: wrap master run control bit
  [POWERPC] spufs: don't set reserved bits in spu interrupt status

Scott Wood (1):
  [POWERPC] Implement arch disable/enable irq hooks.

Stephen Rothwell (5):
  [POWERPC] Add EHEA and EHCA as modules in the ppc64_defconfig
  [POWERPC] The builtin matches for ibmebus.c can be __initdata
  [POWERPC] Constify the of_device_id passed to of_platform_bus_probe
  [POWERPC] Pointers marked as __iomem do not need to be volatile
  [POWERPC] Make non-PCI build work again

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Time for cell code reshuffle?

[Arnd Bergmann]

We've been discussing in the past a few times where we should best put
the spufs code, and when to do it. Since Jeremy and I now have all the
current patches in powerpc.git, maybe we should do it now.

To the question, where what it should go, I'd leave the decision to
Jeremy, but my current idea would be:

arch/powerpc/platforms/cell/spufs -> arch/powerpc/spufs
arch/powerpc/platforms/cell/spu_{callbacks,base,syscalls,fault,notify}.[co]
 -> arch/powerpc/spufs/{callbacks,base,syscalls,fault,notify}.[co]

If we do it in git now, that should result in a minimal breakage of patches.

A related question is what to do about the location of the other cell
related files. platforms/ps3 is already pretty self-contained once we have
spufs outside of platforms/cell, but there is still some code shared between
platforms/cell and platforms/celleb, and each of these directories also contains
code that is only relevant for a subset of the platforms.

My position on these files is that while I find the current state a little
bit confusing, I don't have an idea how to do it better either, and I think
we should just leave the platform files where they are.

Arnd <><
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Re: Yet more patches added to for-2.6.25/master branches

[Marian Balakowicz]

Any changes to add new 52xx targets:

http://patchwork.ozlabs.org/linuxppc/patch?person=988&id=14661
http://patchwork.ozlabs.org/linuxppc/patch?person=988&id=14662
http://patchwork.ozlabs.org/linuxppc/patch?person=988&id=14663
http://patchwork.ozlabs.org/linuxppc/patch?person=988&id=14743
http://patchwork.ozlabs.org/linuxppc/patch?person=988&id=14665
http://patchwork.ozlabs.org/linuxppc/patch?person=988&id=14666
http://patchwork.ozlabs.org/linuxppc/patch?person=988&id=14667
http://patchwork.ozlabs.org/linuxppc/patch?person=988&id=14668
http://patchwork.ozlabs.org/linuxppc/patch?person=988&id=14669
http://patchwork.ozlabs.org/linuxppc/patch?person=988&id=14670
http://patchwork.ozlabs.org/linuxppc/patch?person=988&id=14671
http://patchwork.ozlabs.org/linuxppc/patch?person=988&id=14672
http://patchwork.ozlabs.org/linuxppc/patch?person=988&id=14673

Those did not make it to 2.6.24, Grant Likely suggested to wait until
2.6.25 window opens.

Thanks,
Marian
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Re: [PATCH 1/21] [POWERPC] Reworking machine check handling and Fix 440/440A

[Josh Boyer]

On Fri, 21 Dec 2007 15:39:21 +1100
Benjamin Herrenschmidt <[EMAIL PROTECTED]> wrote:


> Index: linux-merge/include/asm-ppc/reg_booke.h
> ===
> --- linux-merge.orig/include/asm-ppc/reg_booke.h  2007-09-28 
> 11:42:10.0 +1000
> +++ linux-merge/include/asm-ppc/reg_booke.h   2007-12-20 11:35:40.0 
> +1100
> @@ -207,7 +207,7 @@
>  #define  CCR1_TCS0x0080 /* Timer Clock Select */
> 
>  /* Bit definitions for the MCSR. */
> -#ifdef CONFIG_440A
> +#ifdef CONFIG_44x

Should be #ifdef CONFIG_4xx as I pointed out last time.  I'll fix it
when I commit.

josh
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Re: Yet more patches added to for-2.6.25/master branches

[Arnd Bergmann]

Thanks for adding the patches I submitted for 2.6.25.

What's your position on this one:

  http://patchwork.ozlabs.org/linuxppc/patch?id=15600
  OProfile: remove dependency on spufs module

Jeremy agreed that we should merge it in 2.6.24, but if you think
it's too late for that, please add it to your 2.6.25 queue.

Arnd <><
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Re: [PATCH 2/3] sbc8548: Add device tree source for Wind River SBC8548 board

[Kumar Gala]

On Dec 21, 2007, at 12:43 AM, Paul Gortmaker wrote:

> This adds the device tree source for the Wind River SBC8548 board.   
> The
> biggest difference between this and the MPC8548CDS reference platform
> is the absence of the CDS's Arcadia peripherals and physical access  
> to PCI#2.
>
> Signed-off-by: Paul Gortmaker <[EMAIL PROTECTED]>
> ---
> arch/powerpc/boot/dts/sbc8548.dts |  242  
> +
> 1 files changed, 242 insertions(+), 0 deletions(-)
>
> diff --git a/arch/powerpc/boot/dts/sbc8548.dts b/arch/powerpc/boot/ 
> dts/sbc8548.dts
> new file mode 100644
> index 000..e63ed20
> --- /dev/null
> +++ b/arch/powerpc/boot/dts/sbc8548.dts
> @@ -0,0 +1,242 @@
> +/*
> + * SBC8548 Device Tree Source
> + *
> + * Copyright 2007 Wind River Systems Inc.
> + *
> + * Paul Gortmaker (see MAINTAINERS for contact information)
> + *
> + * This program is free software; you can redistribute  it and/or  
> modify it
> + * under  the terms of  the GNU General  Public License as  
> published by the
> + * Free Software Foundation;  either version 2 of the  License, or  
> (at your
> + * option) any later version.
> + */
> +
> +
> +/ {
> + model = "SBC8548";
> + compatible = "SBC8548";
> + #address-cells = <1>;
> + #size-cells = <1>;

mind looking at converting this to a dts-v1 format?

- k
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Re: [PATCH 1/4] sbc8560: add basic support for Wind River SBC8560 as powerpc

[Paul Gortmaker]

In message: Re: [PATCH 1/4] sbc8560: add basic support for Wind River SBC8560 
as powerpc
on 21/12/2007 Stephen Rothwell wrote:

> Hi Paul,
> 
> Just a couple of comments.

[...]

> The braces are unnecessary.
> 

[...]

> We often say "if (!np)" and leave out the blank line above.
> 
> > +   if(of_address_to_resource(np, 0, &r)) {
>   ^
> Put a space here.

[...]

> Need an of_node_pit(np) - cpm2_pic_init() does its own of_node_get.
> 
> > +static struct cpm_pin sbc8560_pins[] = {
> 
> const?
> 

Sounds reasonable to me.  I've integrated these into sbc8560.c (still
looking at how to handle the duart/dts based on feedback).  Since I'd
inerited the things you'd requested fixes on from mpc85xx_ads.c, it
probably makes sense to fix them there too I would imagine.  I'll send
that under its own subject in a minute.

Paul.
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Re: Yet more patches added to for-2.6.25/master branches

[Kumar Gala]

On Dec 21, 2007, at 8:13 AM, Marian Balakowicz wrote:

>
> Any changes to add new 52xx targets:
>
> http://patchwork.ozlabs.org/linuxppc/patch?person=988&id=14661
> http://patchwork.ozlabs.org/linuxppc/patch?person=988&id=14662
> http://patchwork.ozlabs.org/linuxppc/patch?person=988&id=14663
> http://patchwork.ozlabs.org/linuxppc/patch?person=988&id=14743
> http://patchwork.ozlabs.org/linuxppc/patch?person=988&id=14665
> http://patchwork.ozlabs.org/linuxppc/patch?person=988&id=14666
> http://patchwork.ozlabs.org/linuxppc/patch?person=988&id=14667
> http://patchwork.ozlabs.org/linuxppc/patch?person=988&id=14668
> http://patchwork.ozlabs.org/linuxppc/patch?person=988&id=14669
> http://patchwork.ozlabs.org/linuxppc/patch?person=988&id=14670
> http://patchwork.ozlabs.org/linuxppc/patch?person=988&id=14671
> http://patchwork.ozlabs.org/linuxppc/patch?person=988&id=14672
> http://patchwork.ozlabs.org/linuxppc/patch?person=988&id=14673
>
> Those did not make it to 2.6.24, Grant Likely suggested to wait until
> 2.6.25 window opens.

A few of these patches may need to get updated do to other changes.   
For example the i2c nodes in .dts.

- k
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Re: [PATCH 1/3] sbc8548: Add basic support for Wind River SBC8548 as powerpc

[Kumar Gala]

On Dec 21, 2007, at 12:43 AM, Paul Gortmaker wrote:

> This adds the basic support for the Wind River SBC8548 board,  
> implemented
> as powerpc.  It closely follows the implementation of the MPC8548CDS.
>
> Signed-off-by: Paul Gortmaker <[EMAIL PROTECTED]>
> ---
> arch/powerpc/platforms/85xx/Kconfig   |   10 ++-
> arch/powerpc/platforms/85xx/Makefile  |1 +
> arch/powerpc/platforms/85xx/sbc8548.c |  182  
> +
> 3 files changed, 191 insertions(+), 2 deletions(-)
>
> diff --git a/arch/powerpc/platforms/85xx/Kconfig b/arch/powerpc/ 
> platforms/85xx/Kconfig
> index 33d3bea..8407f43 100644
> --- a/arch/powerpc/platforms/85xx/Kconfig
> +++ b/arch/powerpc/platforms/85xx/Kconfig
> @@ -39,6 +39,12 @@ config MPC85xx_DS
>   help
> This option enables support for the MPC85xx DS (MPC8544 DS) board
>
> +config SBC8548
> + bool "Wind River SBC8548"
> + select DEFAULT_UIMAGE
> + help
> +   This option enables support for the Wind River SBC8548 board
> +
> config SBC8560
>   bool "Wind River SBC8560"
>   select DEFAULT_UIMAGE
> @@ -52,7 +58,7 @@ config MPC8540
>   bool
>   select PPC_UDBG_16550
>   select PPC_INDIRECT_PCI
> - default y if MPC8540_ADS || MPC85xx_CDS
> + default y if MPC8540_ADS || MPC85xx_CDS || SBC8548
>
> config MPC8560
>   bool
> @@ -66,4 +72,4 @@ config MPC85xx
>   select FSL_PCI if PCI
>   select SERIAL_8250_SHARE_IRQ if SERIAL_8250
>   default y if MPC8540_ADS || MPC85xx_CDS || MPC8560_ADS \
> - || MPC85xx_MDS || MPC85xx_DS || SBC8560
> + || MPC85xx_MDS || MPC85xx_DS || SBC8560 || SBC8548
> diff --git a/arch/powerpc/platforms/85xx/Makefile b/arch/powerpc/ 
> platforms/85xx/Makefile
> index c3f4d01..3a47b7a 100644
> --- a/arch/powerpc/platforms/85xx/Makefile
> +++ b/arch/powerpc/platforms/85xx/Makefile
> @@ -6,4 +6,5 @@ obj-$(CONFIG_MPC8560_ADS) += mpc85xx_ads.o
> obj-$(CONFIG_MPC85xx_CDS) += mpc85xx_cds.o
> obj-$(CONFIG_MPC85xx_DS)  += mpc85xx_ds.o
> obj-$(CONFIG_MPC85xx_MDS) += mpc85xx_mds.o
> +obj-$(CONFIG_SBC8548) += sbc8548.o
> obj-$(CONFIG_SBC8560) += sbc8560.o
> diff --git a/arch/powerpc/platforms/85xx/sbc8548.c b/arch/powerpc/ 
> platforms/85xx/sbc8548.c
> new file mode 100644
> index 000..f3ab271
> --- /dev/null
> +++ b/arch/powerpc/platforms/85xx/sbc8548.c
> @@ -0,0 +1,182 @@
> +/*
> + * Wind River SBC8548 setup and early boot code.
> + *
> + * Copyright 2007 Wind River Systems Inc.
> + *
> + * By Paul Gortmaker (see MAINTAINERS for contact information)
> + *
> + * Based largely on the MPC8548CDS support - Copyright 2005  
> Freescale Inc.
> + *
> + *
> + * This program is free software; you can redistribute  it and/or  
> modify it
> + * under  the terms of  the GNU General  Public License as  
> published by the
> + * Free Software Foundation;  either version 2 of the  License, or  
> (at your
> + * option) any later version.
> + */
> +
> +#include 
> +#include 
> +#include 
> +#include 
> +#include 
> +#include 
> +#include 
> +#include 
> +#include 
> +#include 
> +#include 
> +#include 
> +#include 
> +#include 
> +#include 
> +#include 
> +
> +#include 
> +#include 
> +#include 
> +#include 
> +#include 
> +#include 
> +#include 
> +#include 
> +#include 
> +#include 
> +#include 
> +#include 
> +#include 
> +#include 
> +
> +#include 
> +#include 
> +
> +#ifdef CONFIG_PCI
> +static int sbc8548_exclude_device(struct pci_controller *hose,
> +   u_char bus, u_char devfn)
> +{
> + if (bus == 0 && PCI_SLOT(devfn) == 0)
> + return PCIBIOS_DEVICE_NOT_FOUND;
> + else
> + return PCIBIOS_SUCCESSFUL;
> +}
> +#endif

see comment on the 8560 support, but I don't think you need to exclude  
the PHBs anymore.  I've fixed this so we have a general quick for FSL  
PHBs.

>
- k
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[PATCH] mpc85xx_ads: add in missing of_node_put()

[Paul Gortmaker]

cpm2_pic_init() does its own of_node_get() so we should do an of_node_put()
before calling it. This and other coding style cleanups as suggested by
Stephen Rothwell.

Signed-off-by: Paul Gortmaker <[EMAIL PROTECTED]>
---
 arch/powerpc/platforms/85xx/mpc85xx_ads.c |   12 ++--
 1 files changed, 6 insertions(+), 6 deletions(-)

diff --git a/arch/powerpc/platforms/85xx/mpc85xx_ads.c 
b/arch/powerpc/platforms/85xx/mpc85xx_ads.c
index bccdc25..ea4886f 100644
--- a/arch/powerpc/platforms/85xx/mpc85xx_ads.c
+++ b/arch/powerpc/platforms/85xx/mpc85xx_ads.c
@@ -52,9 +52,9 @@ static void cpm2_cascade(unsigned int irq, struct irq_desc 
*desc)
 {
int cascade_irq;
 
-   while ((cascade_irq = cpm2_get_irq()) >= 0) {
+   while ((cascade_irq = cpm2_get_irq()) >= 0)
generic_handle_irq(cascade_irq);
-   }
+
desc->chip->eoi(irq);
 }
 
@@ -70,13 +70,12 @@ static void __init mpc85xx_ads_pic_init(void)
 #endif
 
np = of_find_node_by_type(np, "open-pic");
-
-   if (np == NULL) {
+   if (!np) {
printk(KERN_ERR "Could not find open-pic node\n");
return;
}
 
-   if(of_address_to_resource(np, 0, &r)) {
+   if (of_address_to_resource(np, 0, &r)) {
printk(KERN_ERR "Could not map mpic register space\n");
of_node_put(np);
return;
@@ -98,6 +97,7 @@ static void __init mpc85xx_ads_pic_init(void)
return;
}
irq = irq_of_parse_and_map(np, 0);
+   of_node_put(np);
 
cpm2_pic_init(np);
set_irq_chained_handler(irq, cpm2_cascade);
@@ -112,7 +112,7 @@ struct cpm_pin {
int port, pin, flags;
 };
 
-static struct cpm_pin mpc8560_ads_pins[] = {
+static const struct cpm_pin mpc8560_ads_pins[] = {
/* SCC1 */
{3, 29, CPM_PIN_OUTPUT | CPM_PIN_PRIMARY},
{3, 30, CPM_PIN_OUTPUT | CPM_PIN_SECONDARY},
-- 
1.5.0.rc1.gf4b6c

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[PATCH 0/4] PowerPC: more Sequoia/Rainier updates for 2.6.25

[Valentine Barshak]

This patch series has a couple of PowerPC 440EPx/GRx fixes and
adds PCI to Sequoia/Rainier DTS.

Thanks,
Valentine.
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[PATCH 1/4] PowerPC: Correct 440GRx machine_check callback

[Valentine Barshak]

Correct the PowerPC 440GRx machine check callback.

Signed-off-by: Valentine Barshak <[EMAIL PROTECTED]>
---
 arch/powerpc/kernel/cputable.c |2 +-
 1 files changed, 1 insertion(+), 1 deletion(-)

diff -pruN linux-2.6.orig/arch/powerpc/kernel/cputable.c 
linux-2.6/arch/powerpc/kernel/cputable.c
--- linux-2.6.orig/arch/powerpc/kernel/cputable.c   2007-12-21 
17:14:17.0 +0300
+++ linux-2.6/arch/powerpc/kernel/cputable.c2007-12-21 18:05:08.0 
+0300
@@ -1247,7 +1247,7 @@ static struct cpu_spec __initdata cpu_sp
.icache_bsize   = 32,
.dcache_bsize   = 32,
.cpu_setup  = __setup_cpu_440grx,
-   .machine_check  = machine_check_4xx,
+   .machine_check  = machine_check_440A,
.platform   = "ppc440",
},
{ /* Use logical PVR for 440EPx (logical pvr = pvr | 0x8) */
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[PATCH 2/4] PowerPC: update 440EP(x)/440GR(x) identical PVR issue workaround

[Valentine Barshak]

Commit 3ee133269861dc449ad5be761aa8570b1b05571f introduced
a CPU "model" property and thus broke PowerPC 440EP(x)/440GR(x)
identical PVR workaround. The patch updates it to use the new
model property for CPU identification.

Signed-off-by: Valentine Barshak <[EMAIL PROTECTED]>
---
 arch/powerpc/kernel/prom.c |   37 +
 1 files changed, 25 insertions(+), 12 deletions(-)

diff -pruN linux-2.6.orig/arch/powerpc/kernel/prom.c 
linux-2.6/arch/powerpc/kernel/prom.c
--- linux-2.6.orig/arch/powerpc/kernel/prom.c   2007-12-21 17:14:17.0 
+0300
+++ linux-2.6/arch/powerpc/kernel/prom.c2007-12-21 18:42:09.0 
+0300
@@ -614,6 +614,29 @@ static struct feature_property {
 #endif /* CONFIG_PPC64 */
 };
 
+#if defined(CONFIG_44x) && defined(CONFIG_PPC_FPU)
+static inline void identical_pvr_fixup(unsigned long node)
+{
+   unsigned int pvr;
+   char *model = of_get_flat_dt_prop(node, "model", NULL);
+
+   /*
+* Since 440GR(x)/440EP(x) processors have the same pvr,
+* we check the node path and set bit 28 in the cur_cpu_spec
+* pvr for EP(x) processor version. This bit is always 0 in
+* the "real" pvr. Then we call identify_cpu again with
+* the new logical pvr to enable FPU support.
+*/
+   if (model && strstr(model, "440EP")) {
+   pvr = cur_cpu_spec->pvr_value | 0x8;
+   identify_cpu(0, pvr);
+   DBG("Using logical pvr %x for %s\n", pvr, model);
+   }
+}
+#else
+#define identical_pvr_fixup(node) do { } while(0)
+#endif
+
 static void __init check_cpu_feature_properties(unsigned long node)
 {
unsigned long i;
@@ -711,18 +734,8 @@ static int __init early_init_dt_scan_cpu
prop = of_get_flat_dt_prop(node, "cpu-version", NULL);
if (prop && (*prop & 0xff00) == 0x0f00)
identify_cpu(0, *prop);
-#if defined(CONFIG_44x) && defined(CONFIG_PPC_FPU)
-   /*
-* Since 440GR(x)/440EP(x) processors have the same pvr,
-* we check the node path and set bit 28 in the cur_cpu_spec
-* pvr for EP(x) processor version. This bit is always 0 in
-* the "real" pvr. Then we call identify_cpu again with
-* the new logical pvr to enable FPU support.
-*/
-   if (strstr(uname, "440EP")) {
-   identify_cpu(0, cur_cpu_spec->pvr_value | 0x8);
-   }
-#endif
+
+   identical_pvr_fixup(node);
}
 
check_cpu_feature_properties(node);
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Re: [PATCH 2/4] PowerPC: update 440EP(x)/440GR(x) identical PVR issue workaround

[Josh Boyer]

On Fri, 21 Dec 2007 19:24:02 +0300
Valentine Barshak <[EMAIL PROTECTED]> wrote:

> Commit 3ee133269861dc449ad5be761aa8570b1b05571f introduced
> a CPU "model" property and thus broke PowerPC 440EP(x)/440GR(x)
> identical PVR workaround. The patch updates it to use the new
> model property for CPU identification.

Good catch.  I'll have to look more closely to see if anything else
would be broken by changing the cpu node name from "PowerPC,[EMAIL PROTECTED]" 
to
"[EMAIL PROTECTED]".

josh
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[PATCH 3/4] PowerPC: Add PCI entry to 440EPx Sequoia DTS.

[Valentine Barshak]

This adds PCI entry to PowerPC 440EPx Sequoia DTS.

Signed-off-by: Valentine Barshak <[EMAIL PROTECTED]>
---
 arch/powerpc/boot/dts/sequoia.dts |   27 +++
 1 files changed, 27 insertions(+)

--- linux-2.6.orig/arch/powerpc/boot/dts/sequoia.dts2007-12-21 
17:14:17.0 +0300
+++ linux-2.6/arch/powerpc/boot/dts/sequoia.dts 2007-12-21 17:18:32.0 
+0300
@@ -324,6 +324,33 @@
has-new-stacr-staopc;
};
};
+
+   PCI0: [EMAIL PROTECTED] {
+   device_type = "pci";
+   #interrupt-cells = <1>;
+   #size-cells = <2>;
+   #address-cells = <3>;
+   compatible = "ibm,plb440epx-pci", "ibm,plb-pci";
+   primary;
+   reg = <1 eec0 8 /* Config space access */
+  1 eed0 4 /* IACK */
+  1 eed0 4 /* Special cycle */
+  1 ef40 40>;  /* Internal registers */
+
+   /* Outbound ranges, one memory and one IO,
+* later cannot be changed. Chip supports a second
+* IO range but we don't use it for now
+*/
+   ranges = <0200 0 8000 1 8000 0 1000
+   0100 0  1 e800 0 0010>;
+
+   /* Inbound 2GB range starting at 0 */
+   dma-ranges = <4200 0 0 0 0 0 8000>;
+
+   /* All PCI interrupts are routed to IRQ 67 */
+   interrupt-map-mask = < 0 0 0>;
+   interrupt-map = <  0 0 0 &UIC2 3 8 >;
+   };
};
 
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Re: [RESEND DTC PATCH 2/2] Add support for binary includes.

[Scott Wood]

On Fri, Dec 21, 2007 at 11:29:22AM +1100, David Gibson wrote:
> On Thu, Dec 20, 2007 at 01:52:59PM -0600, Scott Wood wrote:
> > A property's data can be populated with a file's contents
> > as follows:
> > 
> > node {
> > prop = /bin-include/ "path/to/data";
> > };
> 
> I'd be inclined to use /incbin/ rather than /bin-include/.  It's only
> slightly less obvious, but it's then the same as the gas pseudo-op as
> well as being a little briefer.

OK.

> > Search paths are not yet implemented; non-absolute lookups are relative to
> > the directory from which dtc was invoked.
> 
> Hrm.  I think that's a bit too bogus.  Although it's rather more work
> to implement, I think we have to make relative paths relative to the
> location of the dts file until search paths are implemented.

OK.  I was being lazy. :-P

> > +   | propdataprefix DT_BININCLUDE DT_STRING
> > +   {
> > +   struct stat st;
> > +   FILE *f;
> > +   int fd;
> > +   
> > +   f = fopen($3.val, "rb");
> > +   if (!f) {
> > +   yyerrorf("Cannot open file \"%s\": %s",
> > +$3.val, strerror(errno));
> > +   YYERROR;
> 
> Hrm.  I'm not sure that being unable to open the file should cause a
> *parse* error which is what YYERROR will do.  Probably better to print
> an error message, but let the parsing continue, with the property
> value being as though the file were empty.

Yeah, I wanted something that would cause dtc to return an error code,
and it doesn't seem that calling yyerror(f) will do that at present.  I
guess I should fix that rather than overload YYERROR.

> 
> > +   }
> > +
> > +   fd = fileno(f);
> > +   if (fstat(fd, &st) < 0) {
> > +   yyerrorf("Cannot stat file \"%s\": %s",
> > +$3.val, strerror(errno));
> > +   YYERROR;
> > +   }
> 
> I'm also not sure that stat()ing the file is a good way to get the
> size.  This requires that the included file be a regular file with a
> sane st_size value, and I can imagine cases where it might be useful
> to incbin from a /dev node or other special file.  Obviosuly
> implementing that will require work to data_copy_file().

Hmm...  do you have a use case in mind?

> Actually, I think the way to go here would be to have two variants of
> the incbin directive:  one which takes just a filename and includes
> the whole file contents, another which takes a filename and a number
> and includes just the first N bytes of the file.

Maybe.  /incbinrange/ "path/name" start len?

> > diff --git a/dtc.h b/dtc.h
> > index 9b89689..87b5bb1 100644
> > --- a/dtc.h
> > +++ b/dtc.h
> > @@ -138,6 +138,7 @@ struct data data_grow_for(struct data d, int xlen);
> >  struct data data_copy_mem(const char *mem, int len);
> >  struct data data_copy_escape_string(const char *s, int len);
> >  struct data data_copy_file(FILE *f, size_t len);
> > +struct data data_bin_include(const char *filename);
> 
> This looks like a hangover from an earlier version.

Oops, yes.

-Scott
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[PATCH 4/4] PowerPC: Add PCI node to 440GRx Rainier DTS.

[Valentine Barshak]

This adds PCI entry to PowerPC 440GRx Rainier DTS.

Signed-off-by: Valentine Barshak <[EMAIL PROTECTED]>
---
 arch/powerpc/boot/dts/rainier.dts |   27 +++
 1 files changed, 27 insertions(+)

--- linux-2.6.orig/arch/powerpc/boot/dts/rainier.dts2007-12-19 
16:00:01.0 +0300
+++ linux-2.6/arch/powerpc/boot/dts/rainier.dts 2007-12-20 21:59:42.0 
+0300
@@ -317,6 +317,33 @@
has-new-stacr-staopc;
};
};
+
+   PCI0: [EMAIL PROTECTED] {
+   device_type = "pci";
+   #interrupt-cells = <1>;
+   #size-cells = <2>;
+   #address-cells = <3>;
+   compatible = "ibm,plb440grx-pci", "ibm,plb-pci";
+   primary;
+   reg = <1 eec0 8 /* Config space access */
+  1 eed8 4 /* IACK */
+  1 eed8 4 /* Special cycle */
+  1 ef40 40>;  /* Internal registers */
+
+   /* Outbound ranges, one memory and one IO,
+* later cannot be changed. Chip supports a second
+* IO range but we don't use it for now
+*/
+   ranges = <0200 0 8000 1 8000 0 1000
+   0100 0  1 e800 0 0010>;
+
+   /* Inbound 2GB range starting at 0 */
+   dma-ranges = <4200 0 0 0 0 0 8000>;
+
+   /* All PCI interrupts are routed to IRQ 67 */
+   interrupt-map-mask = < 0 0 0>;
+   interrupt-map = <  0 0 0 &UIC2 3 8 >;
+   };
};
 
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OProfile callgraph support not working correctly on PPC processors

[Bob Nelson]

I have been investigating why I have not been able to get callgraph code for 
OProfile on Cell to work correctly and I am pretty sure that I have run into 
a problem that is common across all the Power platforms.  (At least the other 
ones I have looked at.)  I have a simple test program that is attached 
below.  It has a main, that calls function1, which calls function2.  Each of 
the functions has some type of loop in it so that I can catch it spending 
some CPU time with OProfile.  I have also attached the objdump -d output for 
the program cut down to the three pertinent functions that shows what is 
happening.  In a nutshell when a terminal function (calls no other function) 
is called the compiler is making an optimization that seems to break the ABI 
convention as far as I can tell.  It does not store the Link Register on the 
stack like any other function.  It just leaves the return address in LR, 
knowing that nothing should change it.  (You can see at the top of both main 
and function1 the first thing it does is "mflr  r0" to copy the link register 
to R0 to be saved. It does not do that in function2.)   When OProfile takes 
an interrupt and needs to gather the callgraph information it does so by 
grabbing the process' stack pointer (R1) and follows the chain back up the 
stack to gather all the caller's addresses.  This works for most functions, 
except for terminal functions for the reason noted above.

Looking at the assembly listing I drew myself a diagram of the stack while 
function2 is active to convince myself of what was wrong and here is what I 
see it as...  When the interrupt is handled OProfile grabs a copy of R1, it 
ignores the first frame on the stack because there should be no address 
stored.  In the second frame it expects to find function2's caller but since 
function2 doesn't store it, it grabs some random data and proceeds. The stack 
chain is all ok so it doesn't go off into neverland trying to follow a bad 
chain, but it grabs an invalid address for the caller.  And that is why 
OProfile thinks terminal functions have no callers on PPC...

Any suggestions on how this can be fixed?  I am guessing that changing the 
compiler and recompiling every program is probably not the answer.  I assume 
the link register has to be saved in the interrupt routine when it runs, or 
else it couldn't call anything else without crashing the program that was 
interrupted.  Is there a safe place to find it?

Thanks, Bob Nelson


top of stack   --
               |       .                    |
               |       .                    | <--
               |       .                    |   |
               ||           |
               |    R0 (link register)      |  --> main's caller    |
               ||           |
               |    flags (unused)          |               |
               ||           |
               |    R1 (previous frame) |>---
R1 main     -> || 0 (Offset from R1   <--
   (entry)     |    R31 save                |    at entry to main)      |
               || -8                    |
               |       .                    |               |
               |       .                    |               | 
               |       .                    |           |
               ||           |
               |    R0 (link register)      |  -->function1's caller (main) |
               ||           |
               |    flags (not stored)      |           |
               ||               |
               |    R1 (previous frame) |>---
R1 function1-->|| -144 <-
   (entry)     |    R31 save                |               |
               ||           |
               |       .                    |               |
               |       .                    |               |
               |       .                    |               |
               ||           |
               |    nothing stored          | (should be function2's caller |
               ||  function1)               |
               |    flags (not stored)      |               |
               ||               |

Re: [PATCH 2/3] sbc8548: Add device tree source for Wind River SBC8548 board

[Paul Gortmaker]

In message: Re: [PATCH 2/3] sbc8548: Add device tree source for Wind River 
SBC8548 board
on 21/12/2007 Kumar Gala wrote:

>
> On Dec 21, 2007, at 12:43 AM, Paul Gortmaker wrote:
>
>> This adds the device tree source for the Wind River SBC8548 board. 

[...]

> mind looking at converting this to a dts-v1 format?
>
> - k

I figured there might be value in having it as a separate commit, seeing
as there aren't that many other dts-v1 as a reference (yet).  Not sure
if I've got all the v1 type changes in that you had in mind, but I fed
it through the latest dtc from git and fed it to the board and it still
seems happy with it.

I'll probably be away from e-mail after this afternoon for the holiday
period -- so thanks (everyone) for the feedback and whatever I don't
get to today, or any additional recommended changes I'll pick up in Jan.

P.

---

>From: Paul Gortmaker <[EMAIL PROTECTED]>
>Date: Fri, 21 Dec 2007 12:11:17 -0500
>Subject: [PATCH] sbc8548: Convert device tree to be dts-v1 compatible

This converts the sbc8548 dts to be dts-v1 compatible.  Tested with the
latest git pull of dtc (Dec 21/07).

Signed-off-by: Paul Gortmaker <[EMAIL PROTECTED]>
---
 arch/powerpc/boot/dts/sbc8548.dts |  122 +++--
 1 files changed, 62 insertions(+), 60 deletions(-)

diff --git a/arch/powerpc/boot/dts/sbc8548.dts 
b/arch/powerpc/boot/dts/sbc8548.dts
index e63ed20..14be38a 100644
--- a/arch/powerpc/boot/dts/sbc8548.dts
+++ b/arch/powerpc/boot/dts/sbc8548.dts
@@ -12,6 +12,8 @@
  */
 
 
+/dts-v1/;
+
 / {
model = "SBC8548";
compatible = "SBC8548";
@@ -35,10 +37,10 @@
PowerPC,[EMAIL PROTECTED] {
device_type = "cpu";
reg = <0>;
-   d-cache-line-size = <20>;   // 32 bytes
-   i-cache-line-size = <20>;   // 32 bytes
-   d-cache-size = <8000>;  // L1, 32K
-   i-cache-size = <8000>;  // L1, 32K
+   d-cache-line-size = <0x20>; // 32 bytes
+   i-cache-line-size = <0x20>; // 32 bytes
+   d-cache-size = <0x8000>;// L1, 32K
+   i-cache-size = <0x8000>;// L1, 32K
timebase-frequency = <0>;   // From uboot
bus-frequency = <0>;
clock-frequency = <0>;
@@ -47,31 +49,31 @@
 
memory {
device_type = "memory";
-   reg = < 1000>;
+   reg = <0x 0x1000>;
};
 
[EMAIL PROTECTED] {
#address-cells = <1>;
#size-cells = <1>;
device_type = "soc";
-   ranges = < e000 0010>;
-   reg = ;  // CCSRBAR
+   ranges = <0x 0xe000 0x0010>;
+   reg = <0xe000 0x1000>;  // CCSRBAR
bus-frequency = <0>;
 
[EMAIL PROTECTED] {
compatible = "fsl,8548-memory-controller";
-   reg = <2000 1000>;
+   reg = <0x2000 0x1000>;
interrupt-parent = <&mpic>;
-   interrupts = <12 2>;
+   interrupts = <0x12 0x2>;
};
 
[EMAIL PROTECTED] {
compatible = "fsl,8548-l2-cache-controller";
-   reg = <2 1000>;
-   cache-line-size = <20>; // 32 bytes
-   cache-size = <8>;   // L2, 512K
+   reg = <0x2 0x1000>;
+   cache-line-size = <0x20>;   // 32 bytes
+   cache-size = <0x8>; // L2, 512K
interrupt-parent = <&mpic>;
-   interrupts = <10 2>;
+   interrupts = <0x10 0x2>;
};
 
[EMAIL PROTECTED] {
@@ -79,8 +81,8 @@
#size-cells = <0>;
cell-index = <0>;
compatible = "fsl-i2c";
-   reg = <3000 100>;
-   interrupts = <2b 2>;
+   reg = <0x3000 0x100>;
+   interrupts = <0x2b 0x2>;
interrupt-parent = <&mpic>;
dfsrr;
};
@@ -90,8 +92,8 @@
#size-cells = <0>;
cell-index = <1>;
compatible = "fsl-i2c";
-   reg = <3100 100>;
-   interrupts = <2b 2>;
+   reg = <0x3100 0x100>;
+   interrupts = <0x2b 0x2>;
interrupt-parent = <&mpic>;
dfsrr;
};
@@ -100,18 +102,18 @@
#address-cells = <1>;
#size-c

Re: [PATCH 4/4] PowerPC: Add PCI node to 440GRx Rainier DTS.

[Valentine Barshak]

> + reg = <1 eec0 8 /* Config space access */
> +1 eed8 4 /* IACK */
> +1 eed8 4 /* Special cycle */

Please, discard this one, since it contains the typos pasted from 
previous bamboo dts, which have been fixed :).

I'll send the corrected patch right away.
Thanks,
Valentine.
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Re: [PATCH 3/4] sbc8560: Add device tree source for Wind River SBC8560 board

[Scott Wood]

On Fri, Dec 21, 2007 at 10:57:24AM +1100, David Gibson wrote:
> > +   mpic: [EMAIL PROTECTED] {
> > +   clock-frequency = <0>;
> 
> The mpic has a clock-frequency??

Yes, there's a timer on the PIC.

> > +   interrupt-controller;
> > +   #address-cells = <0>;
> 
> Should have #size-cells = <0> too.

This is debatable. :-)

-Scott
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Re: Yet more patches added to for-2.6.25/master branches

[Grant Likely]

On 12/21/07, Marian Balakowicz <[EMAIL PROTECTED]> wrote:
>
>
> Any changes to add new 52xx targets:
>
> http://patchwork.ozlabs.org/linuxppc/patch?person=988&id=14661
> http://patchwork.ozlabs.org/linuxppc/patch?person=988&id=14662
> http://patchwork.ozlabs.org/linuxppc/patch?person=988&id=14663
> http://patchwork.ozlabs.org/linuxppc/patch?person=988&id=14743
> http://patchwork.ozlabs.org/linuxppc/patch?person=988&id=14665
> http://patchwork.ozlabs.org/linuxppc/patch?person=988&id=14666
> http://patchwork.ozlabs.org/linuxppc/patch?person=988&id=14667
> http://patchwork.ozlabs.org/linuxppc/patch?person=988&id=14668
> http://patchwork.ozlabs.org/linuxppc/patch?person=988&id=14669
> http://patchwork.ozlabs.org/linuxppc/patch?person=988&id=14670
> http://patchwork.ozlabs.org/linuxppc/patch?person=988&id=14671
> http://patchwork.ozlabs.org/linuxppc/patch?person=988&id=14672
> http://patchwork.ozlabs.org/linuxppc/patch?person=988&id=14673
>
> Those did not make it to 2.6.24, Grant Likely suggested to wait until
> 2.6.25 window opens.


I'll be picking these up next week.  I haven't had time to do it earlier.

Cheers,
g.



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Secret Lab Technologies Ltd.
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Re: [PATCH -mm 18/43] powerpc compat_binfmt_elf

[Kyle McMartin]

On Fri, Dec 21, 2007 at 12:56:09AM -0800, Roland McGrath wrote:
> > On Thu, Dec 20, 2007 at 03:58:16AM -0800, Roland McGrath wrote:
> > > +obj-$(CONFIG_PPC64)  += ../../../fs/compat_binfmt_elf.o
> > 
> > Building files from another directory is nasty.  Please add a
> > CONFIG_BINFMT_COMPAT_ELF so we can simply build it in fs/
> 
> If that's better, please post the precise Kconfig magic you have in mind to
> have it set when it should be.
> 

Just taking a stab that hch means,

config BINFMT_COMPAT_ELF
def_bool n
depends on 64BIT

and then in arch/powerpc/Kconfig

config COMPAT
bool
default y if PPC64
select BINFMT_COMPAT_ELF

or somesuch.

Regards, Kyle
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Re: Time for cell code reshuffle?

[Geoff Levand]

Arnd Bergmann wrote:
> We've been discussing in the past a few times where we should best put
> the spufs code, and when to do it. Since Jeremy and I now have all the
> current patches in powerpc.git, maybe we should do it now.
> 
> To the question, where what it should go, I'd leave the decision to
> Jeremy, but my current idea would be:
> 
> arch/powerpc/platforms/cell/spufs -> arch/powerpc/spufs
> arch/powerpc/platforms/cell/spu_{callbacks,base,syscalls,fault,notify}.[co]
>  -> arch/powerpc/spufs/{callbacks,base,syscalls,fault,notify}.[co]


I think we should consider support for SpursEngine.  At the moment I have no
idea of what it needs, and if no one else does we need to find out.


> If we do it in git now, that should result in a minimal breakage of patches.
> 
> A related question is what to do about the location of the other cell
> related files. platforms/ps3 is already pretty self-contained once we have
> spufs outside of platforms/cell, but there is still some code shared between
> platforms/cell and platforms/celleb, and each of these directories also 
> contains
> code that is only relevant for a subset of the platforms.


It seems platforms/cell should have the shared and/or generic code, and the 
other
stuff moved into a new platform directory, but is it worth the effort? 

-Geoff

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[PATCH 4/4] PowerPC: Add PCI entry to 440GRx Rainier DTS.

[Valentine Barshak]

This adds PCI entry to PowerPC 440GRx Rainier DTS.

Signed-off-by: Valentine Barshak <[EMAIL PROTECTED]>
---
 arch/powerpc/boot/dts/rainier.dts |   27 +++
 1 files changed, 27 insertions(+)

--- linux-2.6.orig/arch/powerpc/boot/dts/rainier.dts2007-12-19 
16:00:01.0 +0300
+++ linux-2.6/arch/powerpc/boot/dts/rainier.dts 2007-12-20 21:59:42.0 
+0300
@@ -317,6 +317,33 @@
has-new-stacr-staopc;
};
};
+
+   PCI0: [EMAIL PROTECTED] {
+   device_type = "pci";
+   #interrupt-cells = <1>;
+   #size-cells = <2>;
+   #address-cells = <3>;
+   compatible = "ibm,plb440grx-pci", "ibm,plb-pci";
+   primary;
+   reg = <1 eec0 8 /* Config space access */
+  1 eed0 4 /* IACK */
+  1 eed0 4 /* Special cycle */
+  1 ef40 40>;  /* Internal registers */
+
+   /* Outbound ranges, one memory and one IO,
+* later cannot be changed. Chip supports a second
+* IO range but we don't use it for now
+*/
+   ranges = <0200 0 8000 1 8000 0 1000
+   0100 0  1 e800 0 0010>;
+
+   /* Inbound 2GB range starting at 0 */
+   dma-ranges = <4200 0 0 0 0 0 8000>;
+
+   /* All PCI interrupts are routed to IRQ 67 */
+   interrupt-map-mask = < 0 0 0>;
+   interrupt-map = <  0 0 0 &UIC2 3 8 >;
+   };
};
 
chosen {
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Re: [PATCH 0/4] arch/powerpc support for SBC8560 board

[Scott Wood]

On Thu, Dec 20, 2007 at 10:38:15PM -0500, Paul Gortmaker wrote:
> Here is my interpretation of what is happening here -- we come in via
> find_legacy_serial_ports() to pick a console port.  It grabs "chosen"
> to get np stdout, and then checks the parent of the 16550 compat ports
> against the following, requiring at least one of them to match:
> 
>   parent->type == "soc" ? add_legacy_soc_port()
> 
>   parent->type == "isa" ? add_legacy_isa_port()
> 
>   parent->type == "tsi-bridge" ? add_legacy_soc_port()
> 
>   parent->type == "opb" ? add_legacy_soc_port()

We should probably add a parent-is-compatible-with-"simple-bus" check, to
avoid needing to extend this hack even further.

> > Out of interest how exactly are the duart's wired on the 8560.  Are they 
> > off localbus?
> 
> The board has a bunch of stuff hanging off of CS5 -- an RTC, a 7 segment
> display, an EEPROM, some BCSR-like registers, and of course the two
> UARTs which are supposed to be 16C2550.  According to TFM, an EPM7128
> PLD is responsible for mashing/sub-decoding this all onto/off of CS5.
> CS3 and CS4 are the LB-SDRAM.

I'd put these devices under a /localbus node.

-Scott
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Re: Yet more patches added to for-2.6.25/master branches

[Grant Likely]

On 12/21/07, Marian Balakowicz <[EMAIL PROTECTED]> wrote:
> Grant Likely wrote:
> >
> > On 12/21/07, *Marian Balakowicz* <[EMAIL PROTECTED]
> >
> > Any changes to add new 52xx targets:
> >
> > http://patchwork.ozlabs.org/linuxppc/patch?person=988&id=14661
> [...]
> >
> > Those did not make it to 2.6.24, Grant Likely suggested to wait until
> > 2.6.25 window opens.
> >
> >
> > I'll be picking these up next week.  I haven't had time to do it earlier.
>
> Great, I'll retest the set with the latest vanilla next week.

Actually, you should retest against Paulus' latest tree instead
because that is what it will be merged against.

Cheers,
g.




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Re: Yet more patches added to for-2.6.25/master branches

[Marian Balakowicz]

Grant Likely wrote:
> 
> On 12/21/07, *Marian Balakowicz* <[EMAIL PROTECTED]
> 
> Any changes to add new 52xx targets:
> 
> http://patchwork.ozlabs.org/linuxppc/patch?person=988&id=14661
[...]
> 
> Those did not make it to 2.6.24, Grant Likely suggested to wait until
> 2.6.25 window opens.
> 
> 
> I'll be picking these up next week.  I haven't had time to do it earlier.

Great, I'll retest the set with the latest vanilla next week.

Thanks,
Marian
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Re: Yet more patches added to for-2.6.25/master branches

[Marian Balakowicz]

Grant Likely wrote:
> On 12/21/07, Marian Balakowicz <[EMAIL PROTECTED]> wrote:
>> Grant Likely wrote:
>>> On 12/21/07, *Marian Balakowicz* <[EMAIL PROTECTED]
>>>
>>> Any changes to add new 52xx targets:
>>>
>>> http://patchwork.ozlabs.org/linuxppc/patch?person=988&id=14661
>> [...]
>>> Those did not make it to 2.6.24, Grant Likely suggested to wait until
>>> 2.6.25 window opens.
>>>
>>>
>>> I'll be picking these up next week.  I haven't had time to do it earlier.
>> Great, I'll retest the set with the latest vanilla next week.
> 
> Actually, you should retest against Paulus' latest tree instead
> because that is what it will be merged against.

OK, got it.

Cheers,
Marian
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Re: Time for cell code reshuffle?

[Arnd Bergmann]

On Friday 21 December 2007, Geoff Levand wrote:
> Arnd Bergmann wrote:
>
> > arch/powerpc/platforms/cell/spufs -> arch/powerpc/spufs
> > arch/powerpc/platforms/cell/spu_{callbacks,base,syscalls,fault,notify}.[co]
> >  -> arch/powerpc/spufs/{callbacks,base,syscalls,fault,notify}.[co]
> 
> 
> I think we should consider support for SpursEngine.  At the moment I have no
> idea of what it needs, and if no one else does we need to find out.

Hmm, since there is not much documentation available for SpursEngine, it's
rather hard to tell what needs to be done for it.

If we think that it will hit the kernel anytime soon, we could use fs/spufs
instead of arch/powerpc/spufs right away. Interestingly, this is where it was
initially, but got moved to arch/powerpc/platforms/cell/spufs after a lot
of discussion ;-).

> It seems platforms/cell should have the shared and/or generic code, and the 
> other
> stuff moved into a new platform directory, but is it worth the effort? 

There is very little code in platforms/cell that can not be generic, so I think
it's not worth splitting it. The only IBM blade specific files are
cbe_cpufreq_pmi.c and parts of setup.c and pervasive.c. Everything else could
be shared by about any generic implementation without a hypervisor.

Arnd <><
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Re: [PATCH -mm 18/43] powerpc compat_binfmt_elf

[Arnd Bergmann]

On Friday 21 December 2007, Kyle McMartin wrote:
> Just taking a stab that hch means,
> 
> config BINFMT_COMPAT_ELF
> def_bool n
> depends on 64BIT
> 

I'd call it COMPAT_BINFMT_ELF, for consistency with the file name.
Also, the definition and the depends are redundant if you expect the
option to be autoselected. You can do either of

config COMPAT_BINFMT_ELF
bool

or 

config COMPAT_BINFMT_ELF
def_bool y
depends on COMPAT

The second option makes sense at the point where all architectures with
compat code are using the same compat_binfmt_elf code.

Arnd <><
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Re: [PATCH 2/4] PowerPC: update 440EP(x)/440GR(x) identical PVR issue workaround

[Stefan Roese]

Hi Valentine,

On Friday 21 December 2007, Valentine Barshak wrote:
> > Good catch.  I'll have to look more closely to see if anything else
> > would be broken by changing the cpu node name from "PowerPC,[EMAIL 
> > PROTECTED]" to
> > "[EMAIL PROTECTED]".
> >
> > josh
>
> Looks like we need a u-boot update for 405Ex Kilauea board.
> Mine (U-Boot 1.3.0-rc3-gccc2fe86-dirty (Oct 25 2007 - 12:18:41))
> fails to boot with new cpu node changes:
>
> Uncompressing Kernel Image ... OK
> Booting using the fdt at 0x40
> le to update property /cpus/PowerPC,[EMAIL PROTECTED]:timebase-frequency,
> err=FDT_ERR_NOTFOUND
> Unable to update property /cpus/PowerPC,[EMAIL PROTECTED]:clock-frequency,
> err=FDT_ERR_NOTFOUND

Already done. :) Please take a look at the current implementation in the 
for-1.3.2 branch of the u-boot-ppc4xx custodian repo:

http://www.denx.de/cgi-bin/gitweb.cgi?p=u-boot/u-boot-ppc4xx.git;a=shortlog;h=for-1.3.2

This works for both cpu node names.

Best regards,
Stefan
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[PATCH POWERPC] i2c: adds support for i2c bus on Frescale CPM1/CPM2 controllers

[Jochen Friedrich]

Using the port of 2.4 code from Vitaly Bordug <[EMAIL PROTECTED]>
and the actual algorithm used by the i2c driver of the DBox code on
cvs.tuxboc.org from Tmbinc, Gillem ([EMAIL PROTECTED]). Renamed i2c-rpx.c and
i2c-algo-8xx.c to i2c-cpm.c and converted the driver to an
of_platform_driver.

Signed-off-by: Jochen Friedrich <[EMAIL PROTECTED]>
---
 arch/powerpc/boot/dts/mpc866ads.dts  |   10 +
 arch/powerpc/boot/dts/mpc885ads.dts  |   10 +
 arch/powerpc/platforms/8xx/mpc885ads_setup.c |5 +
 drivers/i2c/busses/Kconfig   |   10 +
 drivers/i2c/busses/Makefile  |1 +
 drivers/i2c/busses/i2c-cpm.c |  776 ++
 6 files changed, 812 insertions(+), 0 deletions(-)
 create mode 100644 drivers/i2c/busses/i2c-cpm.c

diff --git a/arch/powerpc/boot/dts/mpc866ads.dts 
b/arch/powerpc/boot/dts/mpc866ads.dts
index 90f2293..c79cac1 100644
--- a/arch/powerpc/boot/dts/mpc866ads.dts
+++ b/arch/powerpc/boot/dts/mpc866ads.dts
@@ -141,6 +141,16 @@
interrupts = <1e 3>;
interrupt-parent = <&Cpm_pic>;
};
+
+   [EMAIL PROTECTED] {
+   compatible = "fsl,mpc866-i2c",
+"fsl,cpm1-i2c",
+"fsl,cpm-i2c";
+   reg = <860 20 3c80 30>;
+   interrupts = <10 3>;
+   interrupt-parent = <&Cpm_pic>;
+   fsl,cpm-command = <0010>;
+   };
};
};
 };
diff --git a/arch/powerpc/boot/dts/mpc885ads.dts 
b/arch/powerpc/boot/dts/mpc885ads.dts
index 8848e63..fd9c9d7 100644
--- a/arch/powerpc/boot/dts/mpc885ads.dts
+++ b/arch/powerpc/boot/dts/mpc885ads.dts
@@ -213,6 +213,16 @@
fsl,cpm-command = <0080>;
linux,network-index = <2>;
};
+
+   [EMAIL PROTECTED] {
+   compatible = "fsl,mpc885-i2c",
+"fsl,cpm1-i2c",
+"fsl,cpm-i2c";
+   reg = <860 20 3c80 30>;
+   interrupts = <10>;
+   interrupt-parent = <&CPM_PIC>;
+   fsl,cpm-command = <0010>;
+   };
};
};
 
diff --git a/arch/powerpc/platforms/8xx/mpc885ads_setup.c 
b/arch/powerpc/platforms/8xx/mpc885ads_setup.c
index 2cf1b6a..4377521 100644
--- a/arch/powerpc/platforms/8xx/mpc885ads_setup.c
+++ b/arch/powerpc/platforms/8xx/mpc885ads_setup.c
@@ -157,6 +157,11 @@ static struct cpm_pin mpc885ads_pins[] = {
{CPM_PORTE, 28, CPM_PIN_OUTPUT},
{CPM_PORTE, 29, CPM_PIN_OUTPUT},
 #endif
+   /* I2C */
+#ifdef CONFIG_I2C_8XX
+   {CPM_PORTB, 26, CPM_PIN_INPUT | CPM_PIN_OPENDRAIN},
+   {CPM_PORTB, 27, CPM_PIN_INPUT | CPM_PIN_OPENDRAIN},
+#endif
 };
 
 static void __init init_ioports(void)
diff --git a/drivers/i2c/busses/Kconfig b/drivers/i2c/busses/Kconfig
index c466c6c..5950172 100644
--- a/drivers/i2c/busses/Kconfig
+++ b/drivers/i2c/busses/Kconfig
@@ -114,6 +114,16 @@ config I2C_BLACKFIN_TWI_CLK_KHZ
help
  The unit of the TWI clock is kHz.
 
+config I2C_CPM
+   tristate "Freescale CPM1 or CPM2 (MPC8xx/826x)"
+   depends on (CPM1 || CPM2) && I2C && PPC_OF
+   help
+ This supports the use of the I2C interface on Freescale
+ processors with CPM1 or CPM2.
+
+ This driver can also be built as a module.  If so, the module
+ will be called i2c-cpm.
+
 config I2C_DAVINCI
tristate "DaVinci I2C driver"
depends on ARCH_DAVINCI
diff --git a/drivers/i2c/busses/Makefile b/drivers/i2c/busses/Makefile
index 81d43c2..a39 100644
--- a/drivers/i2c/busses/Makefile
+++ b/drivers/i2c/busses/Makefile
@@ -11,6 +11,7 @@ obj-$(CONFIG_I2C_AMD8111) += i2c-amd8111.o
 obj-$(CONFIG_I2C_AT91) += i2c-at91.o
 obj-$(CONFIG_I2C_AU1550)   += i2c-au1550.o
 obj-$(CONFIG_I2C_BLACKFIN_TWI) += i2c-bfin-twi.o
+obj-$(CONFIG_I2C_CPM)  += i2c-cpm.o
 obj-$(CONFIG_I2C_DAVINCI)  += i2c-davinci.o
 obj-$(CONFIG_I2C_ELEKTOR)  += i2c-elektor.o
 obj-$(CONFIG_I2C_GPIO) += i2c-gpio.o
diff --git a/drivers/i2c/busses/i2c-cpm.c b/drivers/i2c/busses/i2c-cpm.c
new file mode 100644
index 000..c3714f6
--- /dev/null
+++ b/drivers/i2c/busses/i2c-cpm.c
@@ -0,0 +1,776 @@
+/*
+ * Freescale CPM1/CPM2 I2C interface.
+ * Copyright (c) 1999 Dan Malek ([EMAIL PROTECTED]).
+ *
+ * moved into proper i2c interface;
+ * Brad Parker ([EMAIL PROTECTED])
+ *
+ * (C) 2007 Montavista Software, Inc.
+ * Vitaly Bordug <[EMAIL PROTECTED]>
+ *
+ * RPX lite specific parts of the i2c interface
+ * Update:  There actually isn't anyth

[PATCH 3/4] [POWERPC][SPI] use brg-frequency for SPI in QE

[Anton Vorontsov]

In case of QE we can use brg-frequency (which is qeclk/2).
Thus no need to divide sysclk in the spi_mpc83xx.

This patch also adds code to use get_brgfreq() on QE chips.

Signed-off-by: Anton Vorontsov <[EMAIL PROTECTED]>
Acked-by: David Brownell <[EMAIL PROTECTED]>
---
 arch/powerpc/sysdev/fsl_soc.c |   39 +++
 drivers/spi/spi_mpc83xx.c |6 +-
 2 files changed, 28 insertions(+), 17 deletions(-)

diff --git a/arch/powerpc/sysdev/fsl_soc.c b/arch/powerpc/sysdev/fsl_soc.c
index 60d9c4e..746f4c5 100644
--- a/arch/powerpc/sysdev/fsl_soc.c
+++ b/arch/powerpc/sysdev/fsl_soc.c
@@ -66,7 +66,7 @@ phys_addr_t get_immrbase(void)
 
 EXPORT_SYMBOL(get_immrbase);
 
-#if defined(CONFIG_CPM2) || defined(CONFIG_8xx)
+#if defined(CONFIG_CPM2) || defined(CONFIG_QUICC_ENGINE) || defined(CONFIG_8xx)
 
 static u32 brgfreq = -1;
 
@@ -91,11 +91,21 @@ u32 get_brgfreq(void)
 
/* Legacy device binding -- will go away when no users are left. */
node = of_find_node_by_type(NULL, "cpm");
+   if (!node)
+   node = of_find_compatible_node(NULL, NULL, "fsl,qe");
+   if (!node)
+   node = of_find_node_by_type(NULL, "qe");
+
if (node) {
prop = of_get_property(node, "brg-frequency", &size);
if (prop && size == 4)
brgfreq = *prop;
 
+   if (brgfreq == -1 || brgfreq == 0) {
+   prop = of_get_property(node, "bus-frequency", &size);
+   if (prop && size == 4)
+   brgfreq = *prop / 2;
+   }
of_node_put(node);
}
 
@@ -1223,22 +1233,27 @@ int __init fsl_spi_init(struct spi_board_info 
*board_infos,
 {
struct device_node *np;
unsigned int i;
-   const u32 *sysclk;
+   u32 sysclk;
 
/* SPI controller is either clocked from QE or SoC clock */
-   np = of_find_compatible_node(NULL, NULL, "fsl,qe");
-   if (!np)
-   np = of_find_node_by_type(NULL, "qe");
+   sysclk = get_brgfreq();
+   if (sysclk == -1) {
+   const u32 *freq;
+   int size;
 
-   if (!np)
np = of_find_node_by_type(NULL, "soc");
+   if (!np)
+   return -ENODEV;
 
-   if (!np)
-   return -ENODEV;
+   freq = of_get_property(np, "bus-frequency", &size);
+   if (!freq || size != sizeof(*freq)) {
+   of_node_put(np);
+   return -ENODEV;
+   }
 
-   sysclk = of_get_property(np, "bus-frequency", NULL);
-   if (!sysclk)
-   return -ENODEV;
+   sysclk = *freq;
+   of_node_put(np);
+   }
 
for (np = NULL, i = 1;
 (np = of_find_compatible_node(np, "spi", "fsl_spi")) != NULL;
@@ -1255,7 +1270,7 @@ int __init fsl_spi_init(struct spi_board_info 
*board_infos,
 
memset(res, 0, sizeof(res));
 
-   pdata.sysclk = *sysclk;
+   pdata.sysclk = sysclk;
 
prop = of_get_property(np, "reg", NULL);
if (!prop)
diff --git a/drivers/spi/spi_mpc83xx.c b/drivers/spi/spi_mpc83xx.c
index 4580b9c..04f7cd9 100644
--- a/drivers/spi/spi_mpc83xx.c
+++ b/drivers/spi/spi_mpc83xx.c
@@ -436,11 +436,7 @@ static int __init mpc83xx_spi_probe(struct platform_device 
*dev)
mpc83xx_spi->qe_mode = pdata->qe_mode;
mpc83xx_spi->get_rx = mpc83xx_spi_rx_buf_u8;
mpc83xx_spi->get_tx = mpc83xx_spi_tx_buf_u8;
-
-   if (mpc83xx_spi->qe_mode)
-   mpc83xx_spi->spibrg = pdata->sysclk / 2;
-   else
-   mpc83xx_spi->spibrg = pdata->sysclk;
+   mpc83xx_spi->spibrg = pdata->sysclk;
 
mpc83xx_spi->rx_shift = 0;
mpc83xx_spi->tx_shift = 0;
-- 
1.5.2.2

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[PATCH 4/4] [POWERPC] fsl_spi_init and users: stop using device_type = "spi"

[Anton Vorontsov]

Also:
- rename "fsl_spi" to "fsl,spi";
- add and use cell-index property, if found;
- split probing code out of fsl_spi_init, thus we can call
  it for legacy device_type probing and new "compatible" probing.

Per http://ozlabs.org/pipermail/linuxppc-dev/2007-December/048388.html

Signed-off-by: Anton Vorontsov <[EMAIL PROTECTED]>
---
 arch/powerpc/boot/dts/mpc8313erdb.dts|4 +-
 arch/powerpc/boot/dts/mpc832x_mds.dts|8 ++--
 arch/powerpc/boot/dts/mpc832x_rdb.dts|8 ++--
 arch/powerpc/boot/dts/mpc8349emitx.dts   |4 +-
 arch/powerpc/boot/dts/mpc8349emitxgp.dts |4 +-
 arch/powerpc/boot/dts/mpc834x_mds.dts|4 +-
 arch/powerpc/boot/dts/mpc836x_mds.dts|8 ++--
 arch/powerpc/boot/dts/mpc8568mds.dts |8 ++--
 arch/powerpc/sysdev/fsl_soc.c|   87 ++---
 9 files changed, 78 insertions(+), 57 deletions(-)

diff --git a/arch/powerpc/boot/dts/mpc8313erdb.dts 
b/arch/powerpc/boot/dts/mpc8313erdb.dts
index c5b6665..a0492b6 100644
--- a/arch/powerpc/boot/dts/mpc8313erdb.dts
+++ b/arch/powerpc/boot/dts/mpc8313erdb.dts
@@ -82,8 +82,8 @@
};
 
[EMAIL PROTECTED] {
-   device_type = "spi";
-   compatible = "fsl_spi";
+   cell-index = <0>;
+   compatible = "fsl,spi";
reg = <7000 1000>;
interrupts = <10 8>;
interrupt-parent = < &ipic >;
diff --git a/arch/powerpc/boot/dts/mpc832x_mds.dts 
b/arch/powerpc/boot/dts/mpc832x_mds.dts
index 8844d30..36ecd39 100644
--- a/arch/powerpc/boot/dts/mpc832x_mds.dts
+++ b/arch/powerpc/boot/dts/mpc832x_mds.dts
@@ -193,8 +193,8 @@
};
 
[EMAIL PROTECTED] {
-   device_type = "spi";
-   compatible = "fsl_spi";
+   cell-index = <0>;
+   compatible = "fsl,spi";
reg = <4c0 40>;
interrupts = <2>;
interrupt-parent = < &qeic >;
@@ -202,8 +202,8 @@
};
 
[EMAIL PROTECTED] {
-   device_type = "spi";
-   compatible = "fsl_spi";
+   cell-index = <1>;
+   compatible = "fsl,spi";
reg = <500 40>;
interrupts = <1>;
interrupt-parent = < &qeic >;
diff --git a/arch/powerpc/boot/dts/mpc832x_rdb.dts 
b/arch/powerpc/boot/dts/mpc832x_rdb.dts
index a7a2e45..ce63b13 100644
--- a/arch/powerpc/boot/dts/mpc832x_rdb.dts
+++ b/arch/powerpc/boot/dts/mpc832x_rdb.dts
@@ -183,8 +183,8 @@
};
 
[EMAIL PROTECTED] {
-   device_type = "spi";
-   compatible = "fsl_spi";
+   cell-index = <0>;
+   compatible = "fsl,spi";
reg = <4c0 40>;
interrupts = <2>;
interrupt-parent = <&qeic>;
@@ -192,8 +192,8 @@
};
 
[EMAIL PROTECTED] {
-   device_type = "spi";
-   compatible = "fsl_spi";
+   cell-index = <1>;
+   compatible = "fsl,spi";
reg = <500 40>;
interrupts = <1>;
interrupt-parent = <&qeic>;
diff --git a/arch/powerpc/boot/dts/mpc8349emitx.dts 
b/arch/powerpc/boot/dts/mpc8349emitx.dts
index e354f26..f8fc5f6 100644
--- a/arch/powerpc/boot/dts/mpc8349emitx.dts
+++ b/arch/powerpc/boot/dts/mpc8349emitx.dts
@@ -82,8 +82,8 @@
};
 
[EMAIL PROTECTED] {
-   device_type = "spi";
-   compatible = "fsl_spi";
+   cell-index = <0>;
+   compatible = "fsl,spi";
reg = <7000 1000>;
interrupts = <10 8>;
interrupt-parent = < &ipic >;
diff --git a/arch/powerpc/boot/dts/mpc8349emitxgp.dts 
b/arch/powerpc/boot/dts/mpc8349emitxgp.dts
index ebdf0b7..50c 100644
--- a/arch/powerpc/boot/dts/mpc8349emitxgp.dts
+++ b/arch/powerpc/boot/dts/mpc8349emitxgp.dts
@@ -80,8 +80,8 @@
};
 
[EMAIL PROTECTED] {
-   device_type = "spi";
-   compatible = "fsl_spi";
+   cell-index = <0>;
+   compatible = "fsl,spi";
reg = <7000 1000>;
interrupts = <10 8>;
interrupt-parent = < &ipic >;
diff --git a/arch/powerpc/boot/dts/mpc834x_mds.dts 
b/arch/powerpc/boot/dts/mpc834x_mds.dts
index 0ba13eb..6ed36a1 100644
--- a/arch/powerpc/boot/dts/mpc834x_mds.dts
+++ b/arch/powerpc/boot/dts/mpc834x_mds.dts
@@ -93,8 +93,8 @@
};
 
   

[PATCH] [POWERPC] MPC8360E-RDK: Device tree and board file

[Anton Vorontsov]

This is new board made by Freescale Semiconductor Inc. and
Logic Product Development.

Currently supported:
1. UEC1,2,7,4
2. I2C
3. SPI
4. NS16550 serial
5. PCI and miniPCI
6. Intel NOR StrataFlash X16 64Mbit PC28F640P30T85

Not supported so far:
1. StMICRO NAND512W3A2BN6E, 512 Mbit (supported with FSL UPM patches)
2. QE SCCs (slow UCCs, used as an UARTs)
3. ADC AD7843
4. FHCI USB
5. Graphics controller, Fujitsu MB86277

Signed-off-by: Anton Vorontsov <[EMAIL PROTECTED]>
---
 arch/powerpc/boot/dts/mpc836x_rdk.dts |  331 +
 arch/powerpc/platforms/83xx/Kconfig   |   11 +-
 arch/powerpc/platforms/83xx/Makefile  |1 +
 arch/powerpc/platforms/83xx/mpc836x_rdk.c |  118 ++
 4 files changed, 460 insertions(+), 1 deletions(-)
 create mode 100644 arch/powerpc/boot/dts/mpc836x_rdk.dts
 create mode 100644 arch/powerpc/platforms/83xx/mpc836x_rdk.c

diff --git a/arch/powerpc/boot/dts/mpc836x_rdk.dts 
b/arch/powerpc/boot/dts/mpc836x_rdk.dts
new file mode 100644
index 000..3f8d2b0
--- /dev/null
+++ b/arch/powerpc/boot/dts/mpc836x_rdk.dts
@@ -0,0 +1,331 @@
+/*
+ * MPC8360E RDK Device Tree Source
+ *
+ * Copyright 2006 Freescale Semiconductor Inc.
+ * Copyright 2007 MontaVista Software, Inc.
+ *   Anton Vorontsov <[EMAIL PROTECTED]>
+ *
+ * This program is free software; you can redistribute  it and/or modify it
+ * under  the terms of  the GNU General  Public License as published by the
+ * Free Software Foundation;  either version 2 of the  License, or (at your
+ * option) any later version.
+ */
+
+/dts-v1/;
+
+/ {
+   #address-cells = <1>;
+   #size-cells = <1>;
+   compatible = "MPC8360ERDK", "MPC836xRDK", "MPC83xxRDK";
+   model = "MPC8360RDK";
+
+   aliases {
+   serial0 = &serial0;
+   serial1 = &serial1;
+   ethernet0 = &enet0;
+   ethernet1 = &enet1;
+   ethernet2 = &enet2;
+   ethernet3 = &enet3;
+   pci0 = &pci0;
+   };
+
+   cpus {
+   #address-cells = <1>;
+   #size-cells = <0>;
+
+   PowerPC,[EMAIL PROTECTED] {
+   device_type = "cpu";
+   reg = <0>;
+   d-cache-line-size = <32>;
+   i-cache-line-size = <32>;
+   d-cache-size = <32768>;
+   i-cache-size = <32768>;
+   /* filled by u-boot */
+   timebase-frequency = <0>; 
+   bus-frequency = <0>;
+   clock-frequency = <0>;
+   };
+   };
+
+   [EMAIL PROTECTED] {
+   #address-cells = <1>;
+   #size-cells = <1>;
+   device_type = "soc";
+   ranges = <0 0xe000 0x0010>;
+   reg = <0xe000 0x0200>;
+   /* filled by u-boot */
+   bus-frequency = <0>;
+
+   [EMAIL PROTECTED] {
+   compatible = "mpc83xx_wdt";
+   reg = <0x200 0x100>;
+   };
+
+   [EMAIL PROTECTED] {
+   #address-cells = <1>;
+   #size-cells = <0>;
+   cell-index = <0>;
+   compatible = "fsl-i2c";
+   reg = <0x3000 0x100>;
+   interrupts = <14 8>;
+   interrupt-parent = <&ipic>;
+   dfsrr;
+   };
+
+   [EMAIL PROTECTED] {
+   #address-cells = <1>;
+   #size-cells = <0>;
+   cell-index = <1>;
+   compatible = "fsl-i2c";
+   reg = <0x3100 0x100>;
+   interrupts = <16 8>;
+   interrupt-parent = <&ipic>;
+   dfsrr;
+   };
+
+   serial0: [EMAIL PROTECTED] {
+   device_type = "serial";
+   compatible = "ns16550";
+   reg = <0x4500 0x100>;
+   interrupts = <9 8>;
+   interrupt-parent = <&ipic>;
+   /* filled by u-boot */
+   clock-frequency = <0>;
+   };
+
+   serial1: [EMAIL PROTECTED] {
+   device_type = "serial";
+   compatible = "ns16550";
+   reg = <0x4600 0x100>;
+   interrupts = <10 8>;
+   interrupt-parent = <&ipic>;
+   /* filled by u-boot */
+   clock-frequency = <0>;
+   };
+
+   [EMAIL PROTECTED] {
+   compatible = "fsl,sec2-crypto";
+   reg = <0x3 0x1>;
+   interrupts = <11 8>;
+   interrupt-parent = <&ipic>;
+   

[PATCH 0/4] PowerPC: implement GPIO API

[Anton Vorontsov]

Hi all,

OF device tree GPIOs bindings are similar to IRQs:

pario0: [EMAIL PROTECTED] {
#gpio-cells = <2>;
num-ports = <7>;
};

[EMAIL PROTECTED] {
gpios = ;
gpio-parent = <&pario0>;
};

"bank pin" scheme is controller specific, so controllers that want
to implement flat mappings or any other could do so.

So far I implemented GPIO API for QE and CPM2 chips. GPIO API for
CPM1 implemented by Jochen Friedrich <[EMAIL PROTECTED]>, included in
this patchset.

- QE GPIO API tested to work with FSL UPM NAND driver and
  MPC8360E-RDK (STMicro NAND512W3A2BN6E);
- CPM2 GPIO API tested to work with MPC8555E+Samsung HY27UF081G6 (LP);
- CPM1 GPIO API untested.

GPIO API is described in Documentation/gpio.txt, and these
patches are tend to support most of it.

As an additional bonus, PowerPC now gets access to few pleasing
drivers:

- drivers/leds/leds-gpio.c (we could use it to play with
  on-board LEDs);
- drivers/i2c/busses/i2c-gpio.c (generic I2C bit-banging driver);
- drivers/input/keyboard/gpio_keys.c - gpio keys (requires
  gpio_to_irq, so far not implemented);
- Could be more (I named the ones I knew about).

Also, in the upcoming kernels, there will be GPIOLIB[1] addition to
the generic GPIO API, to support off-chip GPIO expanders (like MFDs
on I2C/LBC). But so far we support on-chip GPIOs only, with single
controller built-in.

Changes since RFC:
- Implemented #gpio-cells handling;
- Per-bank spinlocks removed;
- Added a patch which implements GPIO API for CPM1;
- Few minor fixes.

Thanks,

[1] 
http://www.kernel.org/pub/linux/kernel/people/akpm/patches/2.6/2.6.24-rc4/2.6.24-rc4-mm1/broken-out/generic-gpio-gpio_chip-support.patch

-- 
Anton Vorontsov
email: [EMAIL PROTECTED]
backup email: [EMAIL PROTECTED]
irc://irc.freenode.net/bd2
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Re: [PATCH -mm 18/43] powerpc compat_binfmt_elf

[Sam Ravnborg]

On Fri, Dec 21, 2007 at 12:51:06PM -0500, Kyle McMartin wrote:
> On Fri, Dec 21, 2007 at 12:56:09AM -0800, Roland McGrath wrote:
> > > On Thu, Dec 20, 2007 at 03:58:16AM -0800, Roland McGrath wrote:
> > > > +obj-$(CONFIG_PPC64)+= ../../../fs/compat_binfmt_elf.o
> > > 
> > > Building files from another directory is nasty.  Please add a
> > > CONFIG_BINFMT_COMPAT_ELF so we can simply build it in fs/
> > 
> > If that's better, please post the precise Kconfig magic you have in mind to
> > have it set when it should be.
Kyle made a proposal but I like to get in to the party too...

> > 
> 
> Just taking a stab that hch means,
> 
> config BINFMT_COMPAT_ELF
>   def_bool n
>   depends on 64BIT
> 
> and then in arch/powerpc/Kconfig
> 
> config COMPAT
>   bool
>   default y if PPC64
>   select BINFMT_COMPAT_ELF
> 
> or somesuch.

We recently discussed a common prefix for the selctable symbols
and consensus pointed out "HAVE_" so let us try to use it.
I did not quite understand the "depends on 64BIT" in Kyles example.
Does we really want to use compat_binfmt_elf for all archs that
define 64BIT? Anyway I added this in the example below.

fs/Makefile:
obj-$(COMPAT_BINFMT_ELF) += compat_binfmt_elf.o

fs/Kconfig:
config COMPAT_BINFMT_ELF
depends on HAVE_COMPAT_BINFMT_ELF || 64BIT

# COMPAT_BINFMT_ELF must be selected when an
# architecture supoorts ...
config HAVE_COMPAT_BINFMT_ELF


arch/powerpc/Kconfig:

config COMPAT
bool
default PPC64
select HAVE_COMPAT_BINFMT_ELF


In the example above the extra indirection:
HAVE_COMPAT_BINFMT_ELF => COMPAT_BNFMT_ELF is not really needed
but tomorrow when we add another "depends on" to COMPAT_INFMT_ELF
it is needed to avoid the misbehaving select that just ignore the
dependencies and select the symbol anyway.

Sam
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[PATCH 3/4] [POWERPC] CPM2: implement GPIO API

[Anton Vorontsov]

Signed-off-by: Anton Vorontsov <[EMAIL PROTECTED]>
---
 arch/powerpc/platforms/Kconfig|1 +
 arch/powerpc/sysdev/cpm2_common.c |  121 +
 2 files changed, 122 insertions(+), 0 deletions(-)

diff --git a/arch/powerpc/platforms/Kconfig b/arch/powerpc/platforms/Kconfig
index 3d9ff27..cc2d54e 100644
--- a/arch/powerpc/platforms/Kconfig
+++ b/arch/powerpc/platforms/Kconfig
@@ -277,6 +277,7 @@ config CPM2
default n
select CPM
select PPC_LIB_RHEAP
+   select GENERIC_GPIO
help
  The CPM2 (Communications Processor Module) is a coprocessor on
  embedded CPUs made by Freescale.  Selecting this option means that
diff --git a/arch/powerpc/sysdev/cpm2_common.c 
b/arch/powerpc/sysdev/cpm2_common.c
index f7188e2..fe25978 100644
--- a/arch/powerpc/sysdev/cpm2_common.c
+++ b/arch/powerpc/sysdev/cpm2_common.c
@@ -31,12 +31,14 @@
 #include 
 #include 
 #include 
+#include 
 #include 
 #include 
 #include 
 
 #include 
 #include 
+#include 
 #include 
 #include 
 #include 
@@ -61,8 +63,43 @@ cpm2_map_t __iomem *cpm2_immr;
   of space for CPM as it is larger
   than on PQ2 */
 
+static spinlock_t cpm2_port_lock = __SPIN_LOCK_UNLOCKED(cpm2_port_lock);
+static int cpm2_num_ports;
+
+static int par_io_xlate(struct device_node *np, int index)
+{
+   return __of_parse_gpio_bank_pin(np, index, 32, cpm2_num_ports);
+}
+
+static struct of_gpio_chip of_gpio_chip = {
+   .xlate = par_io_xlate,
+};
+
+int cpm2_init_par_io(void)
+{
+   struct device_node *np;
+   const u32 *num_ports;
+
+   np = of_find_compatible_node(NULL, NULL, "fsl,cpm2-pario");
+   if (!np)
+   return -ENOENT;
+
+   num_ports = of_get_property(np, "num-ports", NULL);
+   if (!num_ports) {
+   of_node_put(np);
+   return -ENOENT;
+   }
+   cpm2_num_ports = *num_ports;
+
+   np->data = &of_gpio_chip;
+
+   return 0;
+}
+
 void __init cpm2_reset(void)
 {
+   int ret;
+
 #ifdef CONFIG_PPC_85xx
cpm2_immr = ioremap(CPM_MAP_ADDR, CPM_MAP_SIZE);
 #else
@@ -80,6 +117,10 @@ void __init cpm2_reset(void)
/* Tell everyone where the comm processor resides.
 */
cpmp = &cpm2_immr->im_cpm;
+
+   ret = cpm2_init_par_io();
+   if (ret)
+   pr_warning("CPM2 PIO not initialized!\n");
 }
 
 static DEFINE_SPINLOCK(cmd_lock);
@@ -468,3 +509,83 @@ void cpm2_set_pin(int port, int pin, int flags)
else
clrbits32(&iop[port].odr, pin);
 }
+
+int gpio_request(unsigned int gpio, const char *label)
+{
+   if (gpio / 32 >= cpm2_num_ports)
+   return -EINVAL;
+   return 0;
+}
+EXPORT_SYMBOL_GPL(gpio_request);
+
+int gpio_direction_input(unsigned int gpio)
+{
+   unsigned long flags;
+   int port = gpio / 32;
+   int pin = gpio % 32;
+
+   spin_lock_irqsave(&cpm2_port_lock, flags);
+
+   cpm2_set_pin(port, pin, CPM_PIN_INPUT | CPM_PIN_GPIO);
+
+   spin_unlock_irqrestore(&cpm2_port_lock, flags);
+   return 0;
+}
+EXPORT_SYMBOL_GPL(gpio_direction_input);
+
+int gpio_direction_output(unsigned int gpio, int value)
+{
+   struct cpm2_ioports __iomem *iop =
+   (struct cpm2_ioports __iomem *)&cpm2_immr->im_ioport;
+   int port = gpio / 32;
+   int pin = gpio % 32;
+   unsigned long flags;
+
+   spin_lock_irqsave(&cpm2_port_lock, flags);
+
+   cpm2_set_pin(port, pin, CPM_PIN_OUTPUT | CPM_PIN_GPIO);
+
+   pin = 1 << (31 - pin);
+   if (value)
+   setbits32(&iop[port].dat, pin);
+   else
+   clrbits32(&iop[port].dat, pin);
+
+   spin_unlock_irqrestore(&cpm2_port_lock, flags);
+   return 0;
+}
+EXPORT_SYMBOL_GPL(gpio_direction_output);
+
+int gpio_get_value(unsigned int gpio)
+{
+   struct cpm2_ioports __iomem *iop =
+   (struct cpm2_ioports __iomem *)&cpm2_immr->im_ioport;
+   int port = gpio / 32;
+   int pin = gpio % 32;
+
+   pin = 1 << (31 - pin);
+
+   return !!(in_be32(&iop[port].dat) & pin);
+}
+EXPORT_SYMBOL_GPL(gpio_get_value);
+
+int gpio_set_value(unsigned int gpio, int value)
+{
+   struct cpm2_ioports __iomem *iop =
+   (struct cpm2_ioports __iomem *)&cpm2_immr->im_ioport;
+   int port = gpio / 32;
+   int pin = gpio % 32;
+   unsigned long flags;
+
+   pin = 1 << (31 - pin);
+
+   spin_lock_irqsave(&cpm2_port_lock, flags);
+   if (value)
+   setbits32(&iop[port].dat, pin);
+   else
+   clrbits32(&iop[port].dat, pin);
+   spin_unlock_irqrestore(&cpm2_port_lock, flags);
+
+   return 0;
+}
+EXPORT_SYMBOL_GPL(gpio_set_value);
-- 
1.5.2.2

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[PATCH 1/4] [POWERPC] qe_lib and users: get rid of device_type and model

[Anton Vorontsov]

Now we're searching for "fsl,qe", "fsl,qe-muram", "fsl,qe-muram-data".

Per http://ozlabs.org/pipermail/linuxppc-dev/2007-December/048388.html

Signed-off-by: Anton Vorontsov <[EMAIL PROTECTED]>
---
 arch/powerpc/boot/dts/mpc832x_mds.dts |7 ---
 arch/powerpc/boot/dts/mpc832x_rdb.dts |7 ---
 arch/powerpc/boot/dts/mpc836x_mds.dts |7 ---
 arch/powerpc/boot/dts/mpc8568mds.dts  |7 ---
 arch/powerpc/platforms/83xx/mpc832x_mds.c |1 +
 arch/powerpc/platforms/83xx/mpc832x_rdb.c |1 +
 arch/powerpc/platforms/83xx/mpc836x_mds.c |1 +
 arch/powerpc/platforms/85xx/mpc85xx_mds.c |4 +++-
 arch/powerpc/sysdev/fsl_soc.c |5 -
 arch/powerpc/sysdev/qe_lib/qe.c   |   16 +---
 10 files changed, 39 insertions(+), 17 deletions(-)

diff --git a/arch/powerpc/boot/dts/mpc832x_mds.dts 
b/arch/powerpc/boot/dts/mpc832x_mds.dts
index 26ac467..588d658 100644
--- a/arch/powerpc/boot/dts/mpc832x_mds.dts
+++ b/arch/powerpc/boot/dts/mpc832x_mds.dts
@@ -175,18 +175,19 @@
[EMAIL PROTECTED] {
#address-cells = <1>;
#size-cells = <1>;
-   device_type = "qe";
-   model = "QE";
+   compatible = "fsl,qe";
ranges = <0 e010 0010>;
reg = ;
brg-frequency = <0>;
bus-frequency = ;
 
[EMAIL PROTECTED] {
-   device_type = "muram";
+   compatible = "fsl,qe-muram", "fsl,cpm-muram";
ranges = <0 0001 4000>;
 
[EMAIL PROTECTED] {
+   compatible = "fsl,qe-muram-data",
+"fsl,cpm-muram-data";
reg = <0 4000>;
};
};
diff --git a/arch/powerpc/boot/dts/mpc832x_rdb.dts 
b/arch/powerpc/boot/dts/mpc832x_rdb.dts
index 10ff7aa..719f375 100644
--- a/arch/powerpc/boot/dts/mpc832x_rdb.dts
+++ b/arch/powerpc/boot/dts/mpc832x_rdb.dts
@@ -165,18 +165,19 @@
[EMAIL PROTECTED] {
#address-cells = <1>;
#size-cells = <1>;
-   device_type = "qe";
-   model = "QE";
+   compatible = "fsl,qe";
ranges = <0 e010 0010>;
reg = ;
brg-frequency = <0>;
bus-frequency = ;
 
[EMAIL PROTECTED] {
-   device_type = "muram";
+   compatible = "fsl,qe-muram", "fsl,cpm-muram";
ranges = <0 0001 4000>;
 
[EMAIL PROTECTED] {
+   compatible = "fsl,qe-muram-data",
+"fsl,cpm-muram-data";
reg = <0 4000>;
};
};
diff --git a/arch/powerpc/boot/dts/mpc836x_mds.dts 
b/arch/powerpc/boot/dts/mpc836x_mds.dts
index fd841b2..8d7124e 100644
--- a/arch/powerpc/boot/dts/mpc836x_mds.dts
+++ b/arch/powerpc/boot/dts/mpc836x_mds.dts
@@ -206,18 +206,19 @@
[EMAIL PROTECTED] {
#address-cells = <1>;
#size-cells = <1>;
-   device_type = "qe";
-   model = "QE";
+   compatible = "fsl,qe";
ranges = <0 e010 0010>;
reg = ;
brg-frequency = <0>;
bus-frequency = <179A7B00>;
 
[EMAIL PROTECTED] {
-   device_type = "muram";
+   device_type = "fsl,qe-muram", "fsl,cpm-muram";
ranges = <0 0001 c000>;
 
[EMAIL PROTECTED]
+   device_type = "fsl,qe-muram-data",
+ "fsl,cpm-muram-data";
reg = <0 c000>;
};
};
diff --git a/arch/powerpc/boot/dts/mpc8568mds.dts 
b/arch/powerpc/boot/dts/mpc8568mds.dts
index 5818a7c..89add8d 100644
--- a/arch/powerpc/boot/dts/mpc8568mds.dts
+++ b/arch/powerpc/boot/dts/mpc8568mds.dts
@@ -283,18 +283,19 @@
[EMAIL PROTECTED] {
#address-cells = <1>;
#size-cells = <1>;
-   device_type = "qe";
-   model = "QE";
+   compatible = "fsl,qe";
ranges = <0 e008 0004>;
reg = ;
brg-frequency = <0>;
bus-frequency = <179A7B00>;
 
[EMAIL PROTECTED] {
-   device_type = "muram";
+   compatible = "fsl,qe-muram", "fsl,cpm-muram";
ranges = <0 0001 c000>;
 
[EMAIL PROTECTED]
+   compatible = "fsl,qe-muram-data",
+"fsl,cpm-muram-data";

Re: [PATCH 2/4] PowerPC: update 440EP(x)/440GR(x) identical PVR issue workaround

[Valentine Barshak]

Josh Boyer wrote:
> On Fri, 21 Dec 2007 19:24:02 +0300
> Valentine Barshak <[EMAIL PROTECTED]> wrote:
> 
>> Commit 3ee133269861dc449ad5be761aa8570b1b05571f introduced
>> a CPU "model" property and thus broke PowerPC 440EP(x)/440GR(x)
>> identical PVR workaround. The patch updates it to use the new
>> model property for CPU identification.
> 
> Good catch.  I'll have to look more closely to see if anything else
> would be broken by changing the cpu node name from "PowerPC,[EMAIL 
> PROTECTED]" to
> "[EMAIL PROTECTED]".
> 
> josh

Looks like we need a u-boot update for 405Ex Kilauea board.
Mine (U-Boot 1.3.0-rc3-gccc2fe86-dirty (Oct 25 2007 - 12:18:41))
fails to boot with new cpu node changes:

Uncompressing Kernel Image ... OK
Booting using the fdt at 0x40
le to update property /cpus/PowerPC,[EMAIL PROTECTED]:timebase-frequency, 
err=FDT_ERR_NOTFOUND
Unable to update property /cpus/PowerPC,[EMAIL PROTECTED]:clock-frequency, 
err=FDT_ERR_NOTFOUND

Thanks,
Valentine.
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[PATCH 2/3] [POWERPC][NAND] FSL UPM NAND driver

[Anton Vorontsov]

It's using FSL UPM infrastructure. So far only 8 bit accessors
are implemented.

Signed-off-by: Anton Vorontsov <[EMAIL PROTECTED]>
---
 drivers/mtd/nand/Kconfig   |7 +
 drivers/mtd/nand/Makefile  |1 +
 drivers/mtd/nand/fsl_upm.c |  313 
 3 files changed, 321 insertions(+), 0 deletions(-)
 create mode 100644 drivers/mtd/nand/fsl_upm.c

diff --git a/drivers/mtd/nand/Kconfig b/drivers/mtd/nand/Kconfig
index 246d451..91b448f 100644
--- a/drivers/mtd/nand/Kconfig
+++ b/drivers/mtd/nand/Kconfig
@@ -306,4 +306,11 @@ config MTD_ALAUDA
  These two (and possibly other) Alauda-based cardreaders for
  SmartMedia and xD allow raw flash access.
 
+config MTD_NAND_FSL_UPM
+   tristate "MTD driver for NAND on Freescale UPM"
+   depends on MTD_NAND && FSL_UPM && GENERIC_GPIO
+   help
+ Enables support for NAND Flash wired to Freescale processors'
+ localbus with pre-programmed User-Programmable Machine.
+
 endif # MTD_NAND
diff --git a/drivers/mtd/nand/Makefile b/drivers/mtd/nand/Makefile
index 3ad6c01..d553ea3 100644
--- a/drivers/mtd/nand/Makefile
+++ b/drivers/mtd/nand/Makefile
@@ -29,5 +29,6 @@ obj-$(CONFIG_MTD_NAND_CM_X270)+= cmx270_nand.o
 obj-$(CONFIG_MTD_NAND_BASLER_EXCITE)   += excite_nandflash.o
 obj-$(CONFIG_MTD_NAND_PLATFORM)+= plat_nand.o
 obj-$(CONFIG_MTD_ALAUDA)   += alauda.o
+obj-$(CONFIG_MTD_NAND_FSL_UPM) += fsl_upm.o
 
 nand-objs := nand_base.o nand_bbt.o
diff --git a/drivers/mtd/nand/fsl_upm.c b/drivers/mtd/nand/fsl_upm.c
new file mode 100644
index 000..ac26199
--- /dev/null
+++ b/drivers/mtd/nand/fsl_upm.c
@@ -0,0 +1,313 @@
+/*
+ * Freescale UPM NAND driver.
+ *
+ * Copyright (c) 2007  MontaVista Software, Inc.
+ * Copyright (c) 2007  Anton Vorontsov <[EMAIL PROTECTED]>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ */
+
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+struct upm_data {
+   struct device *dev;
+   struct mtd_info mtd;
+   struct nand_chip chip;
+   int last_ctrl;
+#ifdef CONFIG_MTD_PARTITIONS
+   struct mtd_partition *parts;
+#endif
+
+   struct fsl_upm upm;
+
+   int width;
+   int upm_addr_offset;
+   int upm_cmd_offset;
+   void __iomem *io_base;
+   int rnb_gpio;
+   const u32 *wait_pattern;
+   const u32 *wait_write;
+   int chip_delay;
+};
+
+#define to_upm_data(mtd) container_of(mtd, struct upm_data, mtd)
+
+static int upm_chip_ready(struct mtd_info *mtd)
+{
+   struct upm_data *ud = to_upm_data(mtd);
+
+   if (gpio_get_value(ud->rnb_gpio))
+   return 1;
+
+   dev_vdbg(ud->dev, "busy\n");
+   return 0;
+}
+
+static void upm_wait_rnb(struct upm_data *ud)
+{
+   int cnt = 100;
+
+   if (ud->rnb_gpio >= 0) {
+   while (--cnt && !upm_chip_ready(&ud->mtd))
+   cpu_relax();
+   }
+
+   if (!cnt)
+   dev_err(ud->dev, "tired waiting for RNB\n");
+}
+
+static void upm_cmd_ctrl(struct mtd_info *mtd, int cmd, unsigned int ctrl)
+{
+   struct upm_data *ud = to_upm_data(mtd);
+
+   if (!(ctrl & ud->last_ctrl)) {
+   fsl_upm_end_pattern(&ud->upm);
+
+   if (cmd == NAND_CMD_NONE)
+   return;
+
+   ud->last_ctrl = ctrl & (NAND_ALE | NAND_CLE);
+   }
+
+   if (ctrl & NAND_CTRL_CHANGE) {
+   if (ctrl & NAND_ALE)
+   fsl_upm_start_pattern(&ud->upm, ud->upm_addr_offset);
+   else if (ctrl & NAND_CLE)
+   fsl_upm_start_pattern(&ud->upm, ud->upm_cmd_offset);
+   }
+
+   fsl_upm_run_pattern(&ud->upm, ud->io_base, ud->width, cmd);
+
+   if (ud->wait_pattern)
+   upm_wait_rnb(ud);
+}
+
+static uint8_t upm_read_byte(struct mtd_info *mtd)
+{
+   struct upm_data *ud = to_upm_data(mtd);
+
+   return in_8(ud->chip.IO_ADDR_R);
+}
+
+static void upm_read_buf(struct mtd_info *mtd, uint8_t *buf, int len)
+{
+   struct upm_data *ud = to_upm_data(mtd);
+   int i;
+
+   for (i = 0; i < len; i++)
+   buf[i] = in_8(ud->chip.IO_ADDR_R);
+}
+
+static void upm_write_buf(struct mtd_info *mtd, const uint8_t *buf, int len)
+{
+   struct upm_data *ud = to_upm_data(mtd);
+   int i;
+
+   for (i = 0; i < len; i++) {
+   out_8(ud->chip.IO_ADDR_W, buf[i]);
+   if (ud->wait_write)
+   upm_wait_rnb(ud);
+   }
+}
+
+static int __devinit upm_chip_init(struct upm_data *ud)
+{
+   int ret;
+#ifdef CONFIG_MTD_PARTITIONS
+   static const char *part_types[] = { "cmdlinepart", NULL, };
+#endif
+
+   

[PATCH v3 0/4] device_type/compatible cleanups

[Anton Vorontsov]

Hi all,

Here is the third version (let's hope the last :-).

Changes since v2:
- SPI conversion fixed and actually tested on MPC8323E-RDB to not
  break anything;
- Few more users of device_type = "qe" converted to
  compatible = "fsl,qe";
- Got Ack on SPI part from David.

Changes since v1:
- Device tree lookup changes should be backward compatible with
  older dtbs;
- Few of_put_node() cleanups;
- cell-index property added to spi nodes;
- cpm-muram{,-data} added as an addition to qe-muram{,-data}.


Thanks,

-- 
Anton Vorontsov
email: [EMAIL PROTECTED]
backup email: [EMAIL PROTECTED]
irc://irc.freenode.net/bd2
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[PATCH 2/4] [POWERPC][NET] ucc_geth_mii and users: get rid of device_type

[Anton Vorontsov]

device_type property is bogus, thus use proper compatible.

Also change compatible property to "fsl,ucc-mdio".

Per http://ozlabs.org/pipermail/linuxppc-dev/2007-December/048388.html

Signed-off-by: Anton Vorontsov <[EMAIL PROTECTED]>
---
 arch/powerpc/boot/dts/mpc832x_mds.dts |3 +--
 arch/powerpc/boot/dts/mpc832x_rdb.dts |3 +--
 arch/powerpc/boot/dts/mpc836x_mds.dts |3 +--
 arch/powerpc/boot/dts/mpc8568mds.dts  |2 +-
 drivers/net/ucc_geth_mii.c|3 +++
 5 files changed, 7 insertions(+), 7 deletions(-)

diff --git a/arch/powerpc/boot/dts/mpc832x_mds.dts 
b/arch/powerpc/boot/dts/mpc832x_mds.dts
index 588d658..8844d30 100644
--- a/arch/powerpc/boot/dts/mpc832x_mds.dts
+++ b/arch/powerpc/boot/dts/mpc832x_mds.dts
@@ -255,8 +255,7 @@
#address-cells = <1>;
#size-cells = <0>;
reg = <2320 18>;
-   device_type = "mdio";
-   compatible = "ucc_geth_phy";
+   compatible = "fsl,ucc-mdio";
 
phy3: [EMAIL PROTECTED] {
interrupt-parent = < &ipic >;
diff --git a/arch/powerpc/boot/dts/mpc832x_rdb.dts 
b/arch/powerpc/boot/dts/mpc832x_rdb.dts
index 719f375..a7a2e45 100644
--- a/arch/powerpc/boot/dts/mpc832x_rdb.dts
+++ b/arch/powerpc/boot/dts/mpc832x_rdb.dts
@@ -236,8 +236,7 @@
#address-cells = <1>;
#size-cells = <0>;
reg = <3120 18>;
-   device_type = "mdio";
-   compatible = "ucc_geth_phy";
+   compatible = "fsl,ucc-mdio";
 
phy00:[EMAIL PROTECTED] {
interrupt-parent = <&pic>;
diff --git a/arch/powerpc/boot/dts/mpc836x_mds.dts 
b/arch/powerpc/boot/dts/mpc836x_mds.dts
index 8d7124e..5f0b427 100644
--- a/arch/powerpc/boot/dts/mpc836x_mds.dts
+++ b/arch/powerpc/boot/dts/mpc836x_mds.dts
@@ -288,8 +288,7 @@
#address-cells = <1>;
#size-cells = <0>;
reg = <2120 18>;
-   device_type = "mdio";
-   compatible = "ucc_geth_phy";
+   compatible = "fsl,ucc-mdio";
 
phy0: [EMAIL PROTECTED] {
interrupt-parent = < &ipic >;
diff --git a/arch/powerpc/boot/dts/mpc8568mds.dts 
b/arch/powerpc/boot/dts/mpc8568mds.dts
index 89add8d..ea70010 100644
--- a/arch/powerpc/boot/dts/mpc8568mds.dts
+++ b/arch/powerpc/boot/dts/mpc8568mds.dts
@@ -356,7 +356,7 @@
#address-cells = <1>;
#size-cells = <0>;
reg = <2120 18>;
-   compatible = "ucc_geth_phy";
+   compatible = "fsl,ucc-mdio";
 
/* These are the same PHYs as on
 * gianfar's MDIO bus */
diff --git a/drivers/net/ucc_geth_mii.c b/drivers/net/ucc_geth_mii.c
index df884f0..e3ba14a 100644
--- a/drivers/net/ucc_geth_mii.c
+++ b/drivers/net/ucc_geth_mii.c
@@ -256,6 +256,9 @@ static struct of_device_id uec_mdio_match[] = {
.type = "mdio",
.compatible = "ucc_geth_phy",
},
+   {
+   .compatible = "fsl,ucc-mdio",
+   },
{},
 };
 
-- 
1.5.2.2

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[PATCH 1/4] [POWERPC] Implement GPIO API embryo

[Anton Vorontsov]

This patch implements GPIO API as described in Documentation/gpio.txt.
Two calls unimplemented though: irq_to_gpio and gpio_to_irq.

This patch also provides OF helpers.

Signed-off-by: Anton Vorontsov <[EMAIL PROTECTED]>
---
 arch/powerpc/Kconfig |3 ++
 arch/powerpc/kernel/prom_parse.c |   64 ++
 include/asm-powerpc/gpio.h   |   47 
 include/asm-powerpc/prom.h   |   23 +
 4 files changed, 137 insertions(+), 0 deletions(-)
 create mode 100644 include/asm-powerpc/gpio.h

diff --git a/arch/powerpc/Kconfig b/arch/powerpc/Kconfig
index 232c298..a4fa173 100644
--- a/arch/powerpc/Kconfig
+++ b/arch/powerpc/Kconfig
@@ -73,6 +73,9 @@ config GENERIC_FIND_NEXT_BIT
bool
default y
 
+config GENERIC_GPIO
+   bool
+
 config ARCH_NO_VIRT_TO_BUS
def_bool PPC64
 
diff --git a/arch/powerpc/kernel/prom_parse.c b/arch/powerpc/kernel/prom_parse.c
index 90eb3a3..9875598 100644
--- a/arch/powerpc/kernel/prom_parse.c
+++ b/arch/powerpc/kernel/prom_parse.c
@@ -7,6 +7,7 @@
 #include 
 #include 
 #include 
+#include 
 #include 
 
 #ifdef DEBUG
@@ -1079,3 +1080,66 @@ void __iomem *of_iomap(struct device_node *np, int index)
return ioremap(res.start, 1 + res.end - res.start);
 }
 EXPORT_SYMBOL(of_iomap);
+
+int __of_parse_gpio_bank_pin(struct device_node *np, int index,
+int bank_width, int max_bank)
+{
+   int bank;
+   int pin;
+   const u32 *gpios;
+
+   /*
+* We can get there only if of_get_gpio() succeeded, thus
+* no need checking for "gpios" existence.
+*/
+   gpios = of_get_property(np, "gpios", NULL);
+   bank = gpios[index * 2];
+   pin = gpios[index * 2 + 1];
+
+   if (bank >= max_bank || pin >= bank_width)
+   return -EINVAL;
+
+   return bank * bank_width + pin;
+}
+EXPORT_SYMBOL_GPL(__of_parse_gpio_bank_pin);
+
+int of_get_gpio(struct device_node *np, int index)
+{
+   int ret = -EINVAL;
+   const phandle *gc_ph;
+   struct device_node *gc;
+   struct of_gpio_chip *of_gpio_chip;
+   int size;
+   const u32 *gpio_cells;
+   const u32 *gpios;
+   u32 nr_cells;
+
+   gc_ph = of_get_property(np, "gpio-parent", NULL);
+   if (!gc_ph)
+   return ret;
+
+   gc = of_find_node_by_phandle(*gc_ph);
+   if (!gc || !gc->data)
+   return ret;
+
+   gpio_cells = of_get_property(gc, "#gpio-cells", &size);
+   if (!gpio_cells || size != sizeof(*gpio_cells) || *gpio_cells == 0)
+   goto err;
+
+   gpios = of_get_property(np, "gpios", &size);
+   if (!gpios)
+   goto err;
+   nr_cells = size / sizeof(u32);
+
+   if (nr_cells < *gpio_cells || nr_cells % *gpio_cells ||
+   index > nr_cells / *gpio_cells - 1)
+   goto err;
+
+   of_gpio_chip = gc->data;
+
+   ret = of_gpio_chip->xlate(np, index);
+err:
+   of_node_put(gc);
+   return ret;
+}
+EXPORT_SYMBOL(of_get_gpio);
diff --git a/include/asm-powerpc/gpio.h b/include/asm-powerpc/gpio.h
new file mode 100644
index 000..e0a4f85
--- /dev/null
+++ b/include/asm-powerpc/gpio.h
@@ -0,0 +1,47 @@
+/*
+ * Generic GPIO API implementation for PowerPC.
+ *
+ * Copyright (c) 2007  MontaVista Software, Inc.
+ * Copyright (c) 2007  Anton Vorontsov <[EMAIL PROTECTED]>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ */
+
+#ifndef __ASM_POWERPC_GPIO_H
+#define __ASM_POWERPC_GPIO_H
+
+extern int gpio_request(unsigned int gpio, const char *label);
+static inline void gpio_free(unsigned int gpio) {}
+
+extern int gpio_direction_input(unsigned int gpio);
+extern int gpio_direction_output(unsigned int gpio, int value);
+
+extern int gpio_get_value(unsigned int gpio);
+extern int gpio_set_value(unsigned int gpio, int value);
+
+/*
+ * Not implemented, yet.
+ */
+static inline int gpio_to_irq(unsigned int gpio)
+{
+   return -ENOSYS;
+}
+
+static inline int irq_to_gpio(unsigned int irq)
+{
+   return -ENOSYS;
+}
+
+/*
+ * OF specific gpio_chip handler.
+ */
+struct of_gpio_chip {
+   int (*xlate)(struct device_node *np, int index);
+};
+
+#include 
+
+#endif /* __ASM_POWERPC_GPIO_H */
diff --git a/include/asm-powerpc/prom.h b/include/asm-powerpc/prom.h
index 78b7b0d..f882efc 100644
--- a/include/asm-powerpc/prom.h
+++ b/include/asm-powerpc/prom.h
@@ -330,6 +330,29 @@ extern int of_irq_to_resource(struct device_node *dev, int 
index,
  */
 extern void __iomem *of_iomap(struct device_node *device, int index);
 
+/**
+ * __of_parse_gpio_bank_pin - Helper function to translate "bank pin" GPIOs
+ * @np:device node to get GPIO from
+ * @index: index of the GPIO
+ * @bank_width:   

[PATCH 2/4] [POWERPC] QE: implement GPIO API

[Anton Vorontsov]

Signed-off-by: Anton Vorontsov <[EMAIL PROTECTED]>
---
 arch/powerpc/platforms/Kconfig |1 +
 arch/powerpc/sysdev/qe_lib/qe_io.c |   82 +++-
 2 files changed, 81 insertions(+), 2 deletions(-)

diff --git a/arch/powerpc/platforms/Kconfig b/arch/powerpc/platforms/Kconfig
index ea22cad..3d9ff27 100644
--- a/arch/powerpc/platforms/Kconfig
+++ b/arch/powerpc/platforms/Kconfig
@@ -265,6 +265,7 @@ config TAU_AVERAGE
 config QUICC_ENGINE
bool
select PPC_LIB_RHEAP
+   select GENERIC_GPIO
help
  The QUICC Engine (QE) is a new generation of communications
  coprocessors on Freescale embedded CPUs (akin to CPM in older chips).
diff --git a/arch/powerpc/sysdev/qe_lib/qe_io.c 
b/arch/powerpc/sysdev/qe_lib/qe_io.c
index e53ea4d..3c9e5fe 100644
--- a/arch/powerpc/sysdev/qe_lib/qe_io.c
+++ b/arch/powerpc/sysdev/qe_lib/qe_io.c
@@ -23,6 +23,7 @@
 
 #include 
 #include 
+#include 
 #include 
 
 #undef DEBUG
@@ -43,6 +44,16 @@ struct port_regs {
 
 static struct port_regs *par_io = NULL;
 static int num_par_io_ports = 0;
+static spinlock_t qe_pio_lock = __SPIN_LOCK_UNLOCKED(qe_pio_lock);
+
+static int par_io_xlate(struct device_node *np, int index)
+{
+   return __of_parse_gpio_bank_pin(np, index, 32, num_par_io_ports);
+}
+
+static struct of_gpio_chip of_gpio_chip = {
+   .xlate = par_io_xlate,
+};
 
 int par_io_init(struct device_node *np)
 {
@@ -60,6 +71,8 @@ int par_io_init(struct device_node *np)
if (num_ports)
num_par_io_ports = *num_ports;
 
+   np->data = &of_gpio_chip;
+
return 0;
 }
 
@@ -67,9 +80,12 @@ int par_io_config_pin(u8 port, u8 pin, int dir, int 
open_drain,
  int assignment, int has_irq)
 {
u32 pin_mask1bit, pin_mask2bits, new_mask2bits, tmp_val;
+   unsigned long flags;
 
-   if (!par_io)
-   return -1;
+   if (!par_io || port >= num_par_io_ports)
+   return -EINVAL;
+
+   spin_lock_irqsave(&qe_pio_lock, flags);
 
/* calculate pin location for single and 2 bits information */
pin_mask1bit = (u32) (1 << (NUM_OF_PINS - (pin + 1)));
@@ -126,6 +142,8 @@ int par_io_config_pin(u8 port, u8 pin, int dir, int 
open_drain,
out_be32(&par_io[port].cppar1, new_mask2bits | tmp_val);
}
 
+   spin_unlock_irqrestore(&qe_pio_lock, flags);
+
return 0;
 }
 EXPORT_SYMBOL(par_io_config_pin);
@@ -133,6 +151,7 @@ EXPORT_SYMBOL(par_io_config_pin);
 int par_io_data_set(u8 port, u8 pin, u8 val)
 {
u32 pin_mask, tmp_val;
+   unsigned long flags;
 
if (port >= num_par_io_ports)
return -EINVAL;
@@ -141,6 +160,8 @@ int par_io_data_set(u8 port, u8 pin, u8 val)
/* calculate pin location */
pin_mask = (u32) (1 << (NUM_OF_PINS - 1 - pin));
 
+   spin_lock_irqsave(&qe_pio_lock, flags);
+
tmp_val = in_be32(&par_io[port].cpdata);
 
if (val == 0)   /* clear */
@@ -148,10 +169,25 @@ int par_io_data_set(u8 port, u8 pin, u8 val)
else/* set */
out_be32(&par_io[port].cpdata, pin_mask | tmp_val);
 
+   spin_unlock_irqrestore(&qe_pio_lock, flags);
return 0;
 }
 EXPORT_SYMBOL(par_io_data_set);
 
+static inline int par_io_data_get(u8 port, u8 pin)
+{
+   u32 pin_mask;
+
+   if (port >= num_par_io_ports)
+   return -EINVAL;
+   if (pin >= NUM_OF_PINS)
+   return -EINVAL;
+   /* calculate pin location */
+   pin_mask = (u32) (1 << (NUM_OF_PINS - 1 - pin));
+
+   return !!(in_be32(&par_io[port].cpdata) & pin_mask);
+}
+
 int par_io_of_config(struct device_node *np)
 {
struct device_node *pio;
@@ -195,6 +231,48 @@ int par_io_of_config(struct device_node *np)
 }
 EXPORT_SYMBOL(par_io_of_config);
 
+int gpio_request(unsigned int gpio, const char *label)
+{
+   if (!par_io)
+   return -ENODEV;
+
+   if (gpio / 32 >= num_par_io_ports)
+   return -EINVAL;
+
+   return 0;
+}
+EXPORT_SYMBOL_GPL(gpio_request);
+
+int gpio_direction_input(unsigned int gpio)
+{
+   return par_io_config_pin(gpio / 32, gpio % 32, 2, 0, 0, 0);
+}
+EXPORT_SYMBOL_GPL(gpio_direction_input);
+
+int gpio_direction_output(unsigned int gpio, int value)
+{
+   int ret;
+
+   ret = par_io_config_pin(gpio / 32, gpio % 32, 1, 0, 0, 0);
+   if (ret)
+   return ret;
+
+   return par_io_data_set(gpio / 32, gpio % 32, value);
+}
+EXPORT_SYMBOL_GPL(gpio_direction_output);
+
+int gpio_get_value(unsigned int gpio)
+{
+   return par_io_data_get(gpio / 32, gpio % 32);
+}
+EXPORT_SYMBOL_GPL(gpio_get_value);
+
+int gpio_set_value(unsigned int gpio, int value)
+{
+   return par_io_data_set(gpio / 32, gpio % 32, value);
+}
+EXPORT_SYMBOL_GPL(gpio_set_value);
+
 #ifdef DEBUG
 static void dump_par_io(void)
 {
-- 
1.5.2.2

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[PATCH 1/3] [POWERPC] FSL UPM: routines to manage FSL UPMs

[Anton Vorontsov]

Here are few routines needed to manage FSL UPMs. It doesn't include
UPM programming, yet. So far u-boot manages to program everything.

Signed-off-by: Anton Vorontsov <[EMAIL PROTECTED]>
---
 arch/powerpc/Kconfig  |3 +
 arch/powerpc/sysdev/Makefile  |1 +
 arch/powerpc/sysdev/fsl_upm.c |   65 +
 include/asm-powerpc/fsl_upm.h |   90 +
 4 files changed, 159 insertions(+), 0 deletions(-)
 create mode 100644 arch/powerpc/sysdev/fsl_upm.c
 create mode 100644 include/asm-powerpc/fsl_upm.h

diff --git a/arch/powerpc/Kconfig b/arch/powerpc/Kconfig
index a4fa173..aab8106 100644
--- a/arch/powerpc/Kconfig
+++ b/arch/powerpc/Kconfig
@@ -463,6 +463,9 @@ config FSL_PCI
bool
select PPC_INDIRECT_PCI
 
+config FSL_UPM
+   bool
+
 # Yes MCA RS/6000s exist but Linux-PPC does not currently support any
 config MCA
bool
diff --git a/arch/powerpc/sysdev/Makefile b/arch/powerpc/sysdev/Makefile
index 99a77d7..98dbfdd 100644
--- a/arch/powerpc/sysdev/Makefile
+++ b/arch/powerpc/sysdev/Makefile
@@ -12,6 +12,7 @@ obj-$(CONFIG_U3_DART) += dart_iommu.o
 obj-$(CONFIG_MMIO_NVRAM)   += mmio_nvram.o
 obj-$(CONFIG_FSL_SOC)  += fsl_soc.o
 obj-$(CONFIG_FSL_PCI)  += fsl_pci.o
+obj-$(CONFIG_FSL_UPM)  += fsl_upm.o
 obj-$(CONFIG_TSI108_BRIDGE)+= tsi108_pci.o tsi108_dev.o
 obj-$(CONFIG_QUICC_ENGINE) += qe_lib/
 obj-$(CONFIG_PPC_BESTCOMM) += bestcomm/
diff --git a/arch/powerpc/sysdev/fsl_upm.c b/arch/powerpc/sysdev/fsl_upm.c
new file mode 100644
index 000..6e35bf4
--- /dev/null
+++ b/arch/powerpc/sysdev/fsl_upm.c
@@ -0,0 +1,65 @@
+/*
+ * Freescale UPM routines.
+ *
+ * Copyright (c) 2007  MontaVista Software, Inc.
+ * Copyright (c) 2007  Anton Vorontsov <[EMAIL PROTECTED]>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ */
+
+#include 
+#include 
+#include 
+
+spinlock_t upm_lock = __SPIN_LOCK_UNLOCKED(upm_lock);
+unsigned long upm_lock_flags;
+
+int fsl_upm_get_for(struct device_node *node, const char *name,
+   struct fsl_upm *upm)
+{
+   int ret;
+   struct device_node *lbus;
+   struct resource lbc_res;
+   ptrdiff_t mxmr_offs;
+
+   lbus = of_get_parent(node);
+   if (!lbus) {
+   pr_err("FSL UPM: can't get parent local bus node\n");
+   return -ENOENT;
+   }
+
+   ret = of_address_to_resource(lbus, 0, &lbc_res);
+   if (ret) {
+   pr_err("FSL UPM: can't get parent local bus base\n");
+   return -ENOMEM;
+   }
+
+   switch (name[0]) {
+   case 'A':
+   mxmr_offs = LBC_MAMR;
+   break;
+   case 'B':
+   mxmr_offs = LBC_MBMR;
+   break;
+   case 'C':
+   mxmr_offs = LBC_MCMR;
+   break;
+   default:
+   pr_err("FSL UPM: unknown UPM requested\n");
+   return -EINVAL;
+   break;
+   }
+
+   upm->lbc_base = ioremap_nocache(lbc_res.start,
+   lbc_res.end - lbc_res.start + 1);
+   if (!upm->lbc_base)
+   return -ENOMEM;
+
+   upm->mxmr = upm->lbc_base + mxmr_offs;
+   upm->mar = upm->lbc_base + LBC_MAR;
+
+   return 0;
+}
diff --git a/include/asm-powerpc/fsl_upm.h b/include/asm-powerpc/fsl_upm.h
new file mode 100644
index 000..fe5a5d9
--- /dev/null
+++ b/include/asm-powerpc/fsl_upm.h
@@ -0,0 +1,90 @@
+/*
+ * Freescale UPM routines.
+ *
+ * Copyright (c) 2007  MontaVista Software, Inc.
+ * Copyright (c) 2007  Anton Vorontsov <[EMAIL PROTECTED]>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ */
+
+#ifndef __ASM_POWERPC_FSL_UPM
+#define __ASM_POWERPC_FSL_UPM
+
+#include 
+#include 
+
+#define LBC_MAR0x68
+#define LBC_MAMR   0x70
+#define LBC_MBMR   0x74
+#define LBC_MCMR   0x78
+
+#define LBC_MXMR_RUNP  0x3000
+
+struct fsl_upm {
+   void __iomem *lbc_base;
+   void __iomem *mxmr;
+   void __iomem *mar;
+};
+
+extern spinlock_t upm_lock;
+extern unsigned long upm_lock_flags;
+
+extern int fsl_upm_get_for(struct device_node *node, const char *name,
+  struct fsl_upm *upm);
+
+static inline void fsl_upm_free(struct fsl_upm *upm)
+{
+   iounmap(upm->lbc_base);
+   upm->lbc_base = NULL;
+}
+
+static inline int fsl_upm_got(struct fsl_upm *upm)
+{
+   return !!upm->lbc_base;
+}
+
+static inline void fsl_upm_start_pattern(struct fsl_upm *upm, u32 pat_offset)
+{
+   spin_lock_irqsave(&upm_lock, 

[PATCH 0/3] fsl upm, nand driver and MPC8360E-RDK as its first user

[Anton Vorontsov]

Hi all,

Here is the FSL UPM infrastructure and FSL UPM NAND driver which is
using it. This patchset depends on GPIO API.

Changes since RFC:
- Lockless variant removed;
- Implemented "width" property;
- Few cosmetic changes.

Thanks,

-- 
Anton Vorontsov
email: [EMAIL PROTECTED]
backup email: [EMAIL PROTECTED]
irc://irc.freenode.net/bd2
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Re: [PATCH 0/4] PowerPC: implement GPIO API

[Grant Likely]

On 12/21/07, Anton Vorontsov <[EMAIL PROTECTED]> wrote:
> Also, in the upcoming kernels, there will be GPIOLIB[1] addition to
> the generic GPIO API, to support off-chip GPIO expanders (like MFDs
> on I2C/LBC). But so far we support on-chip GPIOs only, with single
> controller built-in.
>
> Changes since RFC:
> - Implemented #gpio-cells handling;
> - Per-bank spinlocks removed;
> - Added a patch which implements GPIO API for CPM1;
> - Few minor fixes.

Also need to add documentation to booting-without-of.txt.

In general this looks like a good direction, but I do not like the
hard linking for QE and CPM gpios to the 'top level' gpio API.  I
think I'd prefer this stuff to stay out of mainline until the gpiolib
stuff gets merged (which should be soon IIRC).

Cheers,
g.


-- 
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Secret Lab Technologies Ltd.
[EMAIL PROTECTED]
(403) 399-0195
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[PATCH 4/4] [POWERPC] CPM1: implement GPIO API

[Anton Vorontsov]

From: Jochen Friedrich <[EMAIL PROTECTED]>

Signed-off-by: Jochen Friedrich <[EMAIL PROTECTED]>
Signed-off-by: Anton Vorontsov <[EMAIL PROTECTED]>
---

Jochen, I kept your Signed-off-by, though this isn't your original
patch. Hope you're okay with it. I also hope you'll test it. ;-)

 arch/powerpc/platforms/8xx/Kconfig |1 +
 arch/powerpc/sysdev/commproc.c |  178 +++-
 2 files changed, 178 insertions(+), 1 deletions(-)

diff --git a/arch/powerpc/platforms/8xx/Kconfig 
b/arch/powerpc/platforms/8xx/Kconfig
index 91fbe42..6962914 100644
--- a/arch/powerpc/platforms/8xx/Kconfig
+++ b/arch/powerpc/platforms/8xx/Kconfig
@@ -4,6 +4,7 @@ config FADS
 config CPM1
bool
select CPM
+   select GENERIC_GPIO
 
 choice
prompt "8xx Machine Type"
diff --git a/arch/powerpc/sysdev/commproc.c b/arch/powerpc/sysdev/commproc.c
index 621bc6c..8aea29c 100644
--- a/arch/powerpc/sysdev/commproc.c
+++ b/arch/powerpc/sysdev/commproc.c
@@ -27,6 +27,7 @@
 #include 
 #include 
 #include 
+#include 
 #include 
 #include 
 #include 
@@ -36,6 +37,7 @@
 #include 
 #include 
 #include 
+#include 
 #include 
 #include 
 #include 
@@ -56,6 +58,39 @@ static cpic8xx_t __iomem *cpic_reg;
 
 static struct irq_host *cpm_pic_host;
 
+static spinlock_t cpm1_port_lock = __SPIN_LOCK_UNLOCKED(cpm1_port_lock);
+static int cpm1_num_ports;
+
+static int par_io_xlate(struct device_node *np, int index)
+{
+   return __of_parse_gpio_bank_pin(np, index, 32, cpm1_num_ports);
+}
+
+static struct of_gpio_chip of_gpio_chip = {
+   .xlate = par_io_xlate,
+};
+
+int cpm_init_par_io(void)
+{
+   struct device_node *np;
+   const u32 *num_ports;
+
+   np = of_find_node_by_name(NULL, "fsl,cpm1-pario");
+   if (!np)
+   return -ENOENT;
+
+   num_ports = of_get_property(np, "num-ports", NULL);
+   if (!num_ports) {
+   of_node_put(np);
+   return -ENOENT;
+   }
+   cpm1_num_ports = *num_ports;
+
+   np->data = &of_gpio_chip;
+
+   return 0;
+}
+
 static void cpm_mask_irq(unsigned int irq)
 {
unsigned int cpm_vec = (unsigned int)irq_map[irq].hwirq;
@@ -199,6 +234,7 @@ end:
 void __init cpm_reset(void)
 {
sysconf8xx_t __iomem *siu_conf;
+   int ret;
 
mpc8xx_immr = ioremap(get_immrbase(), 0x4000);
if (!mpc8xx_immr) {
@@ -238,6 +274,10 @@ void __init cpm_reset(void)
/* Reclaim the DP memory for our use. */
m8xx_cpm_dpinit();
 #endif
+
+   ret = cpm_init_par_io();
+   if (ret)
+   pr_warning("CPM PIO not initialized!\n");
 }
 
 static DEFINE_SPINLOCK(cmd_lock);
@@ -441,7 +481,7 @@ struct cpm_ioport16 {
 };
 
 struct cpm_ioport32 {
-   __be32 dir, par, sor;
+   __be32 dir, par, sor, dat;
 };
 
 static void cpm1_set_pin32(int port, int pin, int flags)
@@ -486,6 +526,39 @@ static void cpm1_set_pin32(int port, int pin, int flags)
}
 }
 
+static void cpm1_set_value32(int port, int pin, int value)
+{
+   struct cpm_ioport32 __iomem *iop;
+   pin = 1 << (31 - pin);
+
+   if (port == CPM_PORTB)
+   iop = (struct cpm_ioport32 __iomem *)
+ &mpc8xx_immr->im_cpm.cp_pbdir;
+   else
+   iop = (struct cpm_ioport32 __iomem *)
+ &mpc8xx_immr->im_cpm.cp_pedir;
+
+   if (value)
+   setbits32(&iop->dat, pin);
+   else
+   clrbits32(&iop->dat, pin);
+}
+
+static int cpm1_get_value32(int port, int pin)
+{
+   struct cpm_ioport32 __iomem *iop;
+   pin = 1 << (31 - pin);
+
+   if (port == CPM_PORTB)
+   iop = (struct cpm_ioport32 __iomem *)
+ &mpc8xx_immr->im_cpm.cp_pbdir;
+   else
+   iop = (struct cpm_ioport32 __iomem *)
+ &mpc8xx_immr->im_cpm.cp_pedir;
+
+   return !!(in_be32(&iop->dat) & pin);
+}
+
 static void cpm1_set_pin16(int port, int pin, int flags)
 {
struct cpm_ioport16 __iomem *iop =
@@ -520,6 +593,35 @@ static void cpm1_set_pin16(int port, int pin, int flags)
}
 }
 
+static void cpm1_set_value16(int port, int pin, int value)
+{
+   struct cpm_ioport16 __iomem *iop =
+   (struct cpm_ioport16 __iomem *)&mpc8xx_immr->im_ioport;
+
+   pin = 1 << (15 - pin);
+
+   if (port != 0)
+   iop += port - 1;
+
+   if (value)
+   setbits16(&iop->dat, pin);
+   else
+   clrbits16(&iop->dat, pin);
+}
+
+static int cpm1_get_value16(int port, int pin)
+{
+   struct cpm_ioport16 __iomem *iop =
+   (struct cpm_ioport16 __iomem *)&mpc8xx_immr->im_ioport;
+
+   pin = 1 << (15 - pin);
+
+   if (port != 0)
+   iop += port - 1;
+
+   return !!(in_be16(&iop->dat) & pin);
+}
+
 void cpm1_set_pin(enum cpm_port port, int pin, int flags)
 {
if (port == CPM_PORTB || port == CPM_PORTE)
@@ -648,3 +750,77 @@ int cpm1_clk_setup(enum cpm_clk_target target, int clock

[PATCH 3/3] [POWERPC] MPC8360E-RDK: add support for NAND on UPM

[Anton Vorontsov]

Signed-off-by: Anton Vorontsov <[EMAIL PROTECTED]>
---
 arch/powerpc/boot/dts/mpc836x_rdk.dts |   19 +--
 arch/powerpc/platforms/83xx/Kconfig   |1 +
 2 files changed, 18 insertions(+), 2 deletions(-)

diff --git a/arch/powerpc/boot/dts/mpc836x_rdk.dts 
b/arch/powerpc/boot/dts/mpc836x_rdk.dts
index 3f8d2b0..43420b1 100644
--- a/arch/powerpc/boot/dts/mpc836x_rdk.dts
+++ b/arch/powerpc/boot/dts/mpc836x_rdk.dts
@@ -126,7 +126,8 @@
reg = <0x700 0x100>;
};
 
-   [EMAIL PROTECTED] {
+   qe_pio: [EMAIL PROTECTED] {
+   #gpio-cells = <2>;
compatible = "fsl,qe-pario";
reg = <0x1400 0x100>;
num-ports = <7>;
@@ -292,7 +293,8 @@
compatible = "fsl,mpc8360-localbus",
 "fsl,pq2pro-localbus";
reg = <0xe0005000 0xd8>;
-   ranges = <0 0 0xff80 0x80>;
+   ranges = <0 0 0xff80 0x80
+ 1 0 0x6000 0x001000>;
 
[EMAIL PROTECTED],0 {
compatible = "intel,PC28F640P30T85", "cfi-flash";
@@ -300,6 +302,19 @@
bank-width = <2>;
device-width = <1>;
};
+
+   [EMAIL PROTECTED],0 {
+   compatible = "stmicro,NAND512W3A2BN6E", "fsl,upm-nand";
+   reg = <1 0 1>;
+   width = <1>;
+   upm = "A";
+   upm-addr-offset = <16>;
+   upm-cmd-offset = <8>;
+   gpios = <4 18>;
+   gpio-parent = <&qe_pio>;
+   wait-pattern;
+   wait-write;
+   };
};
 
pci0: [EMAIL PROTECTED] {
diff --git a/arch/powerpc/platforms/83xx/Kconfig 
b/arch/powerpc/platforms/83xx/Kconfig
index 0d5a87c..723a8fe 100644
--- a/arch/powerpc/platforms/83xx/Kconfig
+++ b/arch/powerpc/platforms/83xx/Kconfig
@@ -88,6 +88,7 @@ config PPC_MPC836x
bool
select PPC_UDBG_16550
select PPC_INDIRECT_PCI
+   select FSL_UPM
default y if MPC836x_MDS || MPC836x_RDK
 
 config PPC_MPC837x
-- 
1.5.2.2
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Re: [PATCH 0/4] PowerPC: implement GPIO API

[Anton Vorontsov]

On Fri, Dec 21, 2007 at 01:50:10PM -0700, Grant Likely wrote:
> On 12/21/07, Anton Vorontsov <[EMAIL PROTECTED]> wrote:
> > Also, in the upcoming kernels, there will be GPIOLIB[1] addition to
> > the generic GPIO API, to support off-chip GPIO expanders (like MFDs
> > on I2C/LBC). But so far we support on-chip GPIOs only, with single
> > controller built-in.
> >
> > Changes since RFC:
> > - Implemented #gpio-cells handling;
> > - Per-bank spinlocks removed;
> > - Added a patch which implements GPIO API for CPM1;
> > - Few minor fixes.
> 
> Also need to add documentation to booting-without-of.txt.
> 
> In general this looks like a good direction, but I do not like the
> hard linking for QE and CPM gpios to the 'top level' gpio API.  I
> think I'd prefer this stuff to stay out of mainline until the gpiolib

Well, generally I'm okay to wait for gpiolib. Though...

> stuff gets merged (which should be soon IIRC).
  I doubt about that. :-)

I'm looking after gpiolib development (and, well, I also partipiated
in the discussion of earlier versions with former name "gpiodev") for
almost a _year_.

And they're still arguing about fluffy details of implementation.. :-/

As I've probably said once already: if there are plans to build single
kernel with QE+CPM1+CPM2 inside tomorrow -- then of course, I'd better
wait.

But if these plans are distant enough, I see no reason why we can't
enjoy of current API.

Thanks!

-- 
Anton Vorontsov
email: [EMAIL PROTECTED]
backup email: [EMAIL PROTECTED]
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Re: [PATCH 1/3] [POWERPC] FSL UPM: routines to manage FSL UPMs

[Olof Johansson]

On Fri, Dec 21, 2007 at 11:39:25PM +0300, Anton Vorontsov wrote:
> Here are few routines needed to manage FSL UPMs. It doesn't include
> UPM programming, yet. So far u-boot manages to program everything.
> 
> Signed-off-by: Anton Vorontsov <[EMAIL PROTECTED]>
> ---
>  arch/powerpc/Kconfig  |3 +
>  arch/powerpc/sysdev/Makefile  |1 +
>  arch/powerpc/sysdev/fsl_upm.c |   65 +
>  include/asm-powerpc/fsl_upm.h |   90 
> +
>  4 files changed, 159 insertions(+), 0 deletions(-)
>  create mode 100644 arch/powerpc/sysdev/fsl_upm.c
>  create mode 100644 include/asm-powerpc/fsl_upm.h
> 
> diff --git a/arch/powerpc/Kconfig b/arch/powerpc/Kconfig
> index a4fa173..aab8106 100644
> --- a/arch/powerpc/Kconfig
> +++ b/arch/powerpc/Kconfig
> @@ -463,6 +463,9 @@ config FSL_PCI
>   bool
>   select PPC_INDIRECT_PCI
>  
> +config FSL_UPM
> + bool

Please describe new config options, even if they're silent ones.


-Olof
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Re: [PATCH 1/4] [POWERPC] qe_lib and users: get rid of device_type and model

[Olof Johansson]

Hi,

On Fri, Dec 21, 2007 at 11:20:54PM +0300, Anton Vorontsov wrote:
> diff --git a/arch/powerpc/platforms/85xx/mpc85xx_mds.c 
> b/arch/powerpc/platforms/85xx/mpc85xx_mds.c
> index e6c63a5..a152bf8 100644
> --- a/arch/powerpc/platforms/85xx/mpc85xx_mds.c
> +++ b/arch/powerpc/platforms/85xx/mpc85xx_mds.c
> @@ -94,7 +94,8 @@ static void __init mpc85xx_mds_setup_arch(void)
>  #endif
>  
>  #ifdef CONFIG_QUICC_ENGINE
> - if ((np = of_find_node_by_name(NULL, "qe")) != NULL) {
> + np = of_find_node_by_name(NULL, "fsl,qe");
> + if (np) {

That won't work. Did you mean of_find_compatible_node()? If so, you
still need to fall back to looking up by name for older device trees
that don't have the compatible field.


-Olof
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Re: [PATCH 18/21] [POWERPC] bamboo: remove bogus "ranges" property in EBC node

[Benjamin Herrenschmidt]

On Fri, 2007-12-21 at 06:09 -0600, Josh Boyer wrote:
> On Fri, 21 Dec 2007 15:39:35 +1100
> Benjamin Herrenschmidt <[EMAIL PROTECTED]> wrote:
> 
> > This removes a bogus empty "ranges" property in the EBC device node
> > of the Bamboo board device-tree.
> > 
> > The "ranges" property will be created by the boot wrapper, there is
> > no need to have an empty property there, and that causes recent
> > dtc to complain.
> 
> The wrapper doesn't do anything with EBC for bamboo because the EBC
> stuff is a nightmare on this board.  The patch can stand, but I'll
> fixup the comments in the changelog.

The wrapper could still create ranges for the chip select settings no ?

In any case, empty "ranges" is bogus.

Ben.


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Re: [PATCH 0/4] PowerPC: implement GPIO API

[Grant Likely]

On 12/21/07, Anton Vorontsov <[EMAIL PROTECTED]> wrote:
> As I've probably said once already: if there are plans to build single
> kernel with QE+CPM1+CPM2 inside tomorrow -- then of course, I'd better
> wait.
>
> But if these plans are distant enough, I see no reason why we can't
> enjoy of current API.

Oh, I'm not saying don't enjoy it.  :-)  I'm just saying keep it out
of mainline.  I've got a bunch of Virtex stuff that falls into that
category.  Those who are interested can pick the non mainlined patches
out of my git tree.

I suggest doing the same with the GPIO support.  Either that or do our
own simple ppc specific GPIO multiplexer until the common stuff has
its act together.  :-)  We can always migrate over later.

I don't want to see more barriers added to prevent all of 8xxx going
multiplatform.

Cheers,
g.


-- 
Grant Likely, B.Sc., P.Eng.
Secret Lab Technologies Ltd.
[EMAIL PROTECTED]
(403) 399-0195
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Re: [PATCH POWERPC] i2c: adds support for i2c bus on Frescale CPM1/CPM2 controllers

[Vitaly Bordug]

On Fri, 21 Dec 2007 20:36:28 +0100
Jochen Friedrich wrote:

> Using the port of 2.4 code from Vitaly Bordug
> <[EMAIL PROTECTED]> and the actual algorithm used by the i2c
> driver of the DBox code on cvs.tuxboc.org from Tmbinc, Gillem
> ([EMAIL PROTECTED]). Renamed i2c-rpx.c and i2c-algo-8xx.c to i2c-cpm.c and
> converted the driver to an of_platform_driver.
> 

I had an attempt a while ago to do this but haven't had enough time to get it 
completed, so
I am glad to see it finally picked up. There was some sort of discussion that 
time, you seem to have some of those points
addressed but  something not, please
check: http://lkml.org/lkml/2007/5/8/45

(for instance, cpm_i2c_shutdown() and i2c_cpm_del_bus() are void because they 
cant' fail) 

Also, why this was directed to Scott? This is lm-sensors stuff and is
Jean Delvare <[EMAIL PROTECTED]> material...

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Re: [PATCH 1/21] [POWERPC] Reworking machine check handling and Fix 440/440A

[Benjamin Herrenschmidt]

On Fri, 2007-12-21 at 06:01 -0600, Josh Boyer wrote:
> On Fri, 21 Dec 2007 15:39:21 +1100
> Benjamin Herrenschmidt <[EMAIL PROTECTED]> wrote:
> 
> 
> > Index: linux-merge/include/asm-ppc/reg_booke.h
> > ===
> > --- linux-merge.orig/include/asm-ppc/reg_booke.h2007-09-28 
> > 11:42:10.0 +1000
> > +++ linux-merge/include/asm-ppc/reg_booke.h 2007-12-20 11:35:40.0 
> > +1100
> > @@ -207,7 +207,7 @@
> >  #defineCCR1_TCS0x0080 /* Timer Clock Select */
> > 
> >  /* Bit definitions for the MCSR. */
> > -#ifdef CONFIG_440A
> > +#ifdef CONFIG_44x
> 
> Should be #ifdef CONFIG_4xx as I pointed out last time.  I'll fix it
> when I commit.

Ah weird, I though I fixed it... I must have fixed powerpc and not ppc.

Ben.


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Re: [PATCH 3/4] [POWERPC] CPM2: implement GPIO API

[Arnd Bergmann]

On Friday 21 December 2007, Anton Vorontsov wrote:
>  
> +static spinlock_t cpm2_port_lock = __SPIN_LOCK_UNLOCKED(cpm2_port_lock);

This needs to be

static DEFINE_SPINLOCK(cpm2_port_lock);

I think at least lockdep doesn't work the way you do it here.

> +int cpm2_init_par_io(void)
> +{
> + struct device_node *np;
> + const u32 *num_ports;
> +
> + np = of_find_compatible_node(NULL, NULL, "fsl,cpm2-pario");
> + if (!np)
> + return -ENOENT;
> +
> + num_ports = of_get_property(np, "num-ports", NULL);
> + if (!num_ports) {
> + of_node_put(np);
> + return -ENOENT;
> + }
> + cpm2_num_ports = *num_ports;
> +
> + np->data = &of_gpio_chip;
> +
> + return 0;
> +}

This function should also do the call to of_iomap, so you don't
need to pull the address out of the cpm2_immr, which I believe
we're trying to get rid of.

Arnd <><
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Re: Enable RTC for Ebony and Walnut

[Olof Johansson]

Hi,

On Fri, Dec 21, 2007 at 01:21:30PM +1100, David Gibson wrote:
> Index: working-2.6/arch/powerpc/platforms/Kconfig
> ===
> --- working-2.6.orig/arch/powerpc/platforms/Kconfig   2007-12-10 
> 10:52:44.0 +1100
> +++ working-2.6/arch/powerpc/platforms/Kconfig2007-12-21 
> 13:11:34.0 +1100
> @@ -315,6 +315,9 @@ config FSL_ULI1575
>  config CPM
>   bool
>  
> +config OF_RTC
> + bool
> +

New config options should have descriptions, even if they're silent
ones.


Thanks,

-Olof
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Re: [PATCH 4/4] PowerPC: Add PCI node to 440GRx Rainier DTS.

[Benjamin Herrenschmidt]

On Fri, 2007-12-21 at 19:27 +0300, Valentine Barshak wrote:
> +   /* All PCI interrupts are routed to IRQ 67 */
> +   interrupt-map-mask = < 0 0 0>;
> +   interrupt-map = <  0 0 0 &UIC2 3 8 >;
> +   };

Same question as for Sequoia...

Ben.


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Re: [DTC PATCH 1/2] Add yyerrorf() for formatted error messages.

[Scott Wood]

On Fri, Dec 21, 2007 at 11:04:39AM +1100, David Gibson wrote:
> On Thu, Dec 20, 2007 at 10:48:23AM -0600, Scott Wood wrote:
> > Signed-off-by: Scott Wood <[EMAIL PROTECTED]>
> 
> No need for a new function.  If yyerror() is defined as a varargs
> function it's still compatible with bison's built-in usage.

Not if yyerror() is called with a percent symbol in the string, which
looks possible if a percent token is added and verbose syntax errors are
enabled.

-Scott
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Re: [PATCH 3/4] PowerPC: Add PCI entry to 440EPx Sequoia DTS.

[Benjamin Herrenschmidt]

On Fri, 2007-12-21 at 19:26 +0300, Valentine Barshak wrote:
> +
> +   /* All PCI interrupts are routed to IRQ 67 */
> +   interrupt-map-mask = < 0 0 0>;
> +   interrupt-map = <  0 0 0 &UIC2 3 8 >;
> +   };
> };

Wow, all 4 lines of all slots ?

Ben.


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Re: [PATCH 18/21] [POWERPC] bamboo: remove bogus "ranges" property in EBC node

[Josh Boyer]

On Sat, 22 Dec 2007 08:16:55 +1100
Benjamin Herrenschmidt <[EMAIL PROTECTED]> wrote:

> 
> On Fri, 2007-12-21 at 06:09 -0600, Josh Boyer wrote:
> > On Fri, 21 Dec 2007 15:39:35 +1100
> > Benjamin Herrenschmidt <[EMAIL PROTECTED]> wrote:
> > 
> > > This removes a bogus empty "ranges" property in the EBC device node
> > > of the Bamboo board device-tree.
> > > 
> > > The "ranges" property will be created by the boot wrapper, there is
> > > no need to have an empty property there, and that causes recent
> > > dtc to complain.
> > 
> > The wrapper doesn't do anything with EBC for bamboo because the EBC
> > stuff is a nightmare on this board.  The patch can stand, but I'll
> > fixup the comments in the changelog.
> 
> The wrapper could still create ranges for the chip select settings no ?

It could.  It doesn't though.  Perhaps our interpretation of "will be
created" differed.

> In any case, empty "ranges" is bogus.

Correct.  Which is why I said I'd just edit the changelog :).

josh
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Re: [PATCH 8/21] [POWERPC] EP405 boards support for arch/powerpc

[Stephen Rothwell]

Hi Ben,

Just a couple of trivial things.

On Fri, 21 Dec 2007 15:39:26 +1100 Benjamin Herrenschmidt <[EMAIL PROTECTED]> 
wrote:
>
> +++ linux-merge/arch/powerpc/boot/4xx.c   2007-12-21 14:19:46.0 
> +1100
> @@ -179,13 +179,16 @@ void ibm40x_dbcr_reset(void)
>  #define EMAC_RESET 0x2000
>  void ibm4xx_quiesce_eth(u32 *emac0, u32 *emac1)
>  {
> - /* Quiesce the MAL and EMAC(s) since PIBS/OpenBIOS don't do this for us 
> */
> + /* Quiesce the MAL and EMAC(s) since PIBS/OpenBIOS don't
> +  * do this for us
> +  */
>   if (emac0)
>   *emac0 = EMAC_RESET;
>   if (emac1)
>   *emac1 = EMAC_RESET;
>  
>   mtdcr(DCRN_MAL0_CFG, MAL_RESET);
> + while (mfdcr(DCRN_MAL0_CFG) & MAL_RESET) {};

You need the {} or the ; but not both and please put them indented on the
next line so that it is very clear that this is an empty loop.

> + if (cpc0_cr0 & 0x80) {
> + /* uart0 uses the external clock */
> + uart0 = ser_clk;
> + } else {
> + uart0 = cpu / udiv;
> + }

The braces aren't really needed. (Yes, I noticed that you just moved the
code here)

> + if (cpc0_cr0 & 0x40) {
> + /* uart1 uses the external clock */
> + uart1 = ser_clk;
> + } else {
> + uart1 = cpu / udiv;
> + }

And again.

> +++ linux-merge/arch/powerpc/platforms/40x/ep405.c2007-12-21 
> 14:19:46.0 +1100
> +
> +static struct of_device_id ep405_of_bus[] = {

__initdata (preferably) or const

-- 
Cheers,
Stephen Rothwell[EMAIL PROTECTED]
http://www.canb.auug.org.au/~sfr/


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Re: [PATCH 0/4] PowerPC: implement GPIO API

[Anton Vorontsov]

On Fri, Dec 21, 2007 at 02:17:57PM -0700, Grant Likely wrote:
> On 12/21/07, Anton Vorontsov <[EMAIL PROTECTED]> wrote:
> > As I've probably said once already: if there are plans to build single
> > kernel with QE+CPM1+CPM2 inside tomorrow -- then of course, I'd better
> > wait.
> >
> > But if these plans are distant enough, I see no reason why we can't
> > enjoy of current API.
> 
> Oh, I'm not saying don't enjoy it.  :-)  I'm just saying keep it out
> of mainline.  I've got a bunch of Virtex stuff that falls into that
> category.  Those who are interested can pick the non mainlined patches
> out of my git tree.

Ok. I'm fine either way.

Here we go. For anyone interested in the GPIOs on PowerPC, you
can keep an eye on this git tree:

git://git.infradead.org/users/cbou/powerpc-gpio.git

As time will permit, I'll start gpiolib work in the "gpiolib"
branch in that repo, which will include gpiolib -mm patches +
powerpc bits.

Note: I'm quite often rebasing my work, be aware. ;-)


Thanks!

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Re: [PATCH 3/4] [POWERPC] CPM2: implement GPIO API

[Anton Vorontsov]

On Fri, Dec 21, 2007 at 10:16:32PM +0100, Arnd Bergmann wrote:
> On Friday 21 December 2007, Anton Vorontsov wrote:
> >  
> > +static spinlock_t cpm2_port_lock = __SPIN_LOCK_UNLOCKED(cpm2_port_lock);
> 
> This needs to be
> 
> static DEFINE_SPINLOCK(cpm2_port_lock);

These are equivalents.

#define DEFINE_SPINLOCK(x)  spinlock_t x = __SPIN_LOCK_UNLOCKED(x)

> I think at least lockdep doesn't work the way you do it here.

Is it anyhow special regarding what exact macro is used?..

spinlocks.txt says:

SPIN_LOCK_UNLOCKED and RW_LOCK_UNLOCKED defeat lockdep state tracking and
are hence deprecated.

Please use DEFINE_SPINLOCK()/DEFINE_RWLOCK() or
__SPIN_LOCK_UNLOCKED()/__RW_LOCK_UNLOCKED() as appropriate for static
initialization.
-

..should be equivalent, though I prefer open-coded version, until
it fits 80 column width. ;-)

> > +int cpm2_init_par_io(void)
> > +{
> > +   struct device_node *np;
> > +   const u32 *num_ports;
> > +
> > +   np = of_find_compatible_node(NULL, NULL, "fsl,cpm2-pario");
> > +   if (!np)
> > +   return -ENOENT;
> > +
> > +   num_ports = of_get_property(np, "num-ports", NULL);
> > +   if (!num_ports) {
> > +   of_node_put(np);
> > +   return -ENOENT;
> > +   }
> > +   cpm2_num_ports = *num_ports;
> > +
> > +   np->data = &of_gpio_chip;
> > +
> > +   return 0;
> > +}
> 
> This function should also do the call to of_iomap, so you don't
> need to pull the address out of the cpm2_immr, which I believe
> we're trying to get rid of.

Yup, thanks!

-- 
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Re: Oops: Kernel access of bad area

[Christian Kujau]

On Thu, 20 Dec 2007, Nathan Lynch wrote:
> Better to include the full stack trace in such reports,

Hm, I did not want to clutter the mail with all this stuff, but you're 
right, in this case it would've made sense...

> So it looks like the kernel oopsed while firefox was dumping core,
> yuck. It's a real bug.  Hopefully someone on the list can help...

As it's the first time this happened and I could not reproduce it so far 
(the only thing I can reproduce is the ffox crash :)), I doubt it'll be 
"fixable" somehow...

Thanks,
Christian.
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Re: [PATCH 8/21] [POWERPC] EP405 boards support for arch/powerpc

[Benjamin Herrenschmidt]

On Sat, 2007-12-22 at 10:24 +1100, Stephen Rothwell wrote:

> > +++ linux-merge/arch/powerpc/boot/4xx.c 2007-12-21 14:19:46.0 
> > +1100
> > @@ -179,13 +179,16 @@ void ibm40x_dbcr_reset(void)
> >  #define EMAC_RESET 0x2000
> >  void ibm4xx_quiesce_eth(u32 *emac0, u32 *emac1)
> >  {
> > -   /* Quiesce the MAL and EMAC(s) since PIBS/OpenBIOS don't do this for us 
> > */
> > +   /* Quiesce the MAL and EMAC(s) since PIBS/OpenBIOS don't
> > +* do this for us
> > +*/
> > if (emac0)
> > *emac0 = EMAC_RESET;
> > if (emac1)
> > *emac1 = EMAC_RESET;
> >  
> > mtdcr(DCRN_MAL0_CFG, MAL_RESET);
> > +   while (mfdcr(DCRN_MAL0_CFG) & MAL_RESET) {};
> 
> You need the {} or the ; but not both and please put them indented on the
> next line so that it is very clear that this is an empty loop.

Code was copy/pasted from somewhere else... we can always do a fixup
later.

> > +   if (cpc0_cr0 & 0x80) {
> > +   /* uart0 uses the external clock */
> > +   uart0 = ser_clk;
> > +   } else {
> > +   uart0 = cpu / udiv;
> > +   }
> 
> The braces aren't really needed. (Yes, I noticed that you just moved the
> code here)

Yup :-)

> > +   if (cpc0_cr0 & 0x40) {
> > +   /* uart1 uses the external clock */
> > +   uart1 = ser_clk;
> > +   } else {
> > +   uart1 = cpu / udiv;
> > +   }
> 
> And again.

I'd rather do cleanups separately. I won't send new patches until I'm
back from vacation so Josh, if you want to fix those little nits up,
feel free.

> > +++ linux-merge/arch/powerpc/platforms/40x/ep405.c  2007-12-21 
> > 14:19:46.0 +1100
> > +
> > +static struct of_device_id ep405_of_bus[] = {
> 
> __initdata (preferably) or const

Ben.


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Re: [PATCH 10/21] [POWERPC] Base support for 440GX Taishan eval board

[Stephen Rothwell]

On Fri, 21 Dec 2007 15:39:28 +1100 Benjamin Herrenschmidt <[EMAIL PROTECTED]> 
wrote:
>
> +++ linux-merge/arch/powerpc/platforms/44x/taishan.c  2007-12-21 
> 14:20:04.0 +1100
> +
> +static struct of_device_id taishan_of_bus[] = {

__initdata (preferably) or const, please.

-- 
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Re: [PATCH 17/21] [POWERPC] Base support for 440SPe "Katmai" eval board

[Stephen Rothwell]

On Fri, 21 Dec 2007 15:39:34 +1100 Benjamin Herrenschmidt <[EMAIL PROTECTED]> 
wrote:
>
> +++ linux-merge/arch/powerpc/platforms/44x/katmai.c   2007-12-21 
> 14:34:33.0 +1100
> +
> +static struct of_device_id katmai_of_bus[] = {

__initdata (preferably) or const, please.

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Re: [PATCH 1/4] [POWERPC] qe_lib and users: get rid of device_type and model

[Anton Vorontsov]

On Fri, Dec 21, 2007 at 03:25:53PM -0600, Olof Johansson wrote:
> Hi,
> 
> On Fri, Dec 21, 2007 at 11:20:54PM +0300, Anton Vorontsov wrote:
> > diff --git a/arch/powerpc/platforms/85xx/mpc85xx_mds.c 
> > b/arch/powerpc/platforms/85xx/mpc85xx_mds.c
> > index e6c63a5..a152bf8 100644
> > --- a/arch/powerpc/platforms/85xx/mpc85xx_mds.c
> > +++ b/arch/powerpc/platforms/85xx/mpc85xx_mds.c
> > @@ -94,7 +94,8 @@ static void __init mpc85xx_mds_setup_arch(void)
> >  #endif
> >  
> >  #ifdef CONFIG_QUICC_ENGINE
> > -   if ((np = of_find_node_by_name(NULL, "qe")) != NULL) {
> > +   np = of_find_node_by_name(NULL, "fsl,qe");
> > +   if (np) {
> 
> That won't work. Did you mean of_find_compatible_node()?

Yes. :-(

> If so, you
> still need to fall back to looking up by name for older device trees
> that don't have the compatible field.

Yup.

Okay.. I'm approaching lucky v7. ;-)

Much thanks for catching this,

-- 
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Re: [PATCH 8/21] [POWERPC] EP405 boards support for arch/powerpc

[Josh Boyer]

On Sat, 22 Dec 2007 10:24:24 +1100
Stephen Rothwell <[EMAIL PROTECTED]> wrote:

> Hi Ben,
> 
> Just a couple of trivial things.

All fair comments.  And I realize that everyone is busy and such,
but this is the 4th or 5th time these patches have hit the list.

I'm hesitant to let perfection get in the way of good enough at this
point.  I can always fix these up when I commit.

josh
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Re: [PATCH 17/21] [POWERPC] Base support for 440SPe "Katmai" eval board

[Josh Boyer]

On Sat, 22 Dec 2007 11:21:05 +1100
Stephen Rothwell <[EMAIL PROTECTED]> wrote:

> On Fri, 21 Dec 2007 15:39:34 +1100 Benjamin Herrenschmidt <[EMAIL PROTECTED]> 
> wrote:
> >
> > +++ linux-merge/arch/powerpc/platforms/44x/katmai.c 2007-12-21 
> > 14:34:33.0 +1100
> > +
> > +static struct of_device_id katmai_of_bus[] = {
> 
> __initdata (preferably) or const, please.

I'll fix this with a separate commit.  The same comment applies for all
the 4xx platforms already in the kernel.

josh
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Re: [PATCH 2/3] sbc8548: Add device tree source for Wind River SBC8548 board

[David Gibson]

On Fri, Dec 21, 2007 at 12:20:24PM -0500, Paul Gortmaker wrote:
> In message: Re: [PATCH 2/3] sbc8548: Add device tree source for Wind River 
> SBC8548 board
> on 21/12/2007 Kumar Gala wrote:
> 
> >
> > On Dec 21, 2007, at 12:43 AM, Paul Gortmaker wrote:
> >
> >> This adds the device tree source for the Wind River SBC8548 board. 
> 
> [...]
> 
> > mind looking at converting this to a dts-v1 format?
> >
> > - k
> 
> I figured there might be value in having it as a separate commit, seeing
> as there aren't that many other dts-v1 as a reference (yet).  Not sure
> if I've got all the v1 type changes in that you had in mind, but I fed
> it through the latest dtc from git and fed it to the board and it still
> seems happy with it.

There are really only two changes with dts-v1.
1) All integers become C-style, so, decimal by default with
leading 0, 0x or 0b for octal/hex/binary.  d# h# o# are no longer
supported.
2) References to pths must be writte as &{/some/node/or/other}
instead of &/some/node/or/other.  References to labels remain fine as
just &label.

The explicit new source version isn't because the format changes are
large, just because there was no way to make them in a
backwards-compatible way.

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| _way_ _around_!
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Re: [DTC PATCH 1/2] Add yyerrorf() for formatted error messages.

[David Gibson]

On Fri, Dec 21, 2007 at 03:28:56PM -0600, Scott Wood wrote:
> On Fri, Dec 21, 2007 at 11:04:39AM +1100, David Gibson wrote:
> > On Thu, Dec 20, 2007 at 10:48:23AM -0600, Scott Wood wrote:
> > > Signed-off-by: Scott Wood <[EMAIL PROTECTED]>
> > 
> > No need for a new function.  If yyerror() is defined as a varargs
> > function it's still compatible with bison's built-in usage.
> 
> Not if yyerror() is called with a percent symbol in the string, which
> looks possible if a percent token is added and verbose syntax errors are
> enabled.

Ah, yes, I guess so.

However from discussion on the other thread, it looks like this
extended yyerror() isn't really what you want.  Maybe instead we
should look a more general error/warning printing function, and make
yyerror() call that.

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Re: [RESEND DTC PATCH 2/2] Add support for binary includes.

[David Gibson]

On Fri, Dec 21, 2007 at 11:09:21AM -0600, Scott Wood wrote:
> On Fri, Dec 21, 2007 at 11:29:22AM +1100, David Gibson wrote:
> > On Thu, Dec 20, 2007 at 01:52:59PM -0600, Scott Wood wrote:
> > > A property's data can be populated with a file's contents
> > > as follows:
> > > 
> > > node {
> > >   prop = /bin-include/ "path/to/data";
> > > };
> > 
> > I'd be inclined to use /incbin/ rather than /bin-include/.  It's only
> > slightly less obvious, but it's then the same as the gas pseudo-op as
> > well as being a little briefer.
> 
> OK.
> 
> > > Search paths are not yet implemented; non-absolute lookups are relative to
> > > the directory from which dtc was invoked.
> > 
> > Hrm.  I think that's a bit too bogus.  Although it's rather more work
> > to implement, I think we have to make relative paths relative to the
> > location of the dts file until search paths are implemented.
> 
> OK.  I was being lazy. :-P

In general I'd approve, but having to invoke dtc in the right place
for the dts file is a bit too big a usability problem, I think.

> > > + | propdataprefix DT_BININCLUDE DT_STRING
> > > + {
> > > + struct stat st;
> > > + FILE *f;
> > > + int fd;
> > > + 
> > > + f = fopen($3.val, "rb");
> > > + if (!f) {
> > > + yyerrorf("Cannot open file \"%s\": %s",
> > > +  $3.val, strerror(errno));
> > > + YYERROR;
> > 
> > Hrm.  I'm not sure that being unable to open the file should cause a
> > *parse* error which is what YYERROR will do.  Probably better to print
> > an error message, but let the parsing continue, with the property
> > value being as though the file were empty.
> 
> Yeah, I wanted something that would cause dtc to return an error code,
> and it doesn't seem that calling yyerror(f) will do that at present.  I
> guess I should fix that rather than overload YYERROR.

No.  As per the yacc interface, yyerror() prints only, it doesn't
terminate.

You could use die(), although that might be an excessively scary
message for the situation.

> > > + }
> > > +
> > > + fd = fileno(f);
> > > + if (fstat(fd, &st) < 0) {
> > > + yyerrorf("Cannot stat file \"%s\": %s",
> > > +  $3.val, strerror(errno));
> > > + YYERROR;
> > > + }
> > 
> > I'm also not sure that stat()ing the file is a good way to get the
> > size.  This requires that the included file be a regular file with a
> > sane st_size value, and I can imagine cases where it might be useful
> > to incbin from a /dev node or other special file.  Obviosuly
> > implementing that will require work to data_copy_file().
> 
> Hmm...  do you have a use case in mind?

Nothing really specific.  I'm thinking of a dts that maybe pulls in
some blobs from a pre-existing firmware, by sucking in files from
/proc/device-tree.  Or maybe something to produce a dts for a guest
under a hypervisor that takes an image of a real NVRAM or other device
to embed in the tree as a virtual NVRAM for the guest.

It's not a big deal, but since it shouldn't be that hard in principle
to read in a whole file without getting an st_size first.

> > Actually, I think the way to go here would be to have two variants of
> > the incbin directive:  one which takes just a filename and includes
> > the whole file contents, another which takes a filename and a number
> > and includes just the first N bytes of the file.
> 
> Maybe.  /incbinrange/ "path/name" start len?

I'd prefer to avoid two different keywords if possible.  I'll see if I
can think of a reasonable syntax.

> > > diff --git a/dtc.h b/dtc.h
> > > index 9b89689..87b5bb1 100644
> > > --- a/dtc.h
> > > +++ b/dtc.h
> > > @@ -138,6 +138,7 @@ struct data data_grow_for(struct data d, int xlen);
> > >  struct data data_copy_mem(const char *mem, int len);
> > >  struct data data_copy_escape_string(const char *s, int len);
> > >  struct data data_copy_file(FILE *f, size_t len);
> > > +struct data data_bin_include(const char *filename);
> > 
> > This looks like a hangover from an earlier version.
> 
> Oops, yes.
> 
> -Scott
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Re: GPIO causing bus error

[Jeff Mock]

Well, I have a system that is pretty similar to yours.  Our boards have 
a 440GX and two Xilinx 2VP70's.  The FPGAs are loaded using slave serial 
mode (not jtag) from GPIO pins, but still pretty similar.

I haven't had any problems loading the FPGAs this way.

 From your description I can't tell when you load the FPGAs during the 
boot process.  Our approach is as follows:

A module is loaded that creates /dev/fpga. You can 'cat' a bitstream 
file to /dev/fpga and the driver will wiggle the GPIO pins appropriately 
to the load the bitstream in the FPGAs.  The script run at boot time 
will do something like:

# zcat /etc/fpga_img.gz > /dev/fpga

At that point we load modules that create devices appropriate for the 
FPGA image and the system is off running a domain specific application. 
The process can be reversed to unload the drivers, load a new FPGA image 
and new drivers without rebooting.

One thing that comes to mind is that our GPIO pins are used for a number 
of disparate needs beyond FPGA loading.  I keep a semaphore for 
accessing the GPIO pins so that the different drivers that touch the 
GPIO pins don't step on each other.  Only one driver can touch the GPIO 
pins at a time.  Failing to do this in our application would definitely 
create occasional failures.

jeff


Wyse, Chris wrote:
> Hi,
>  
> I'm having trouble with an unusual problem.  I'm working on relatively 
> new hardware, so it's possible that there could be a hardware issue 
> involved. 
>  
> I have an FPGA on my PPC440GX board that gets loaded via JTAG during the 
> kernel boot process (Linux 2.6.10).  It uses the 440GX GPIO lines to 
> send the necessary JTAG commands to the FPGA to perform the initial 
> load.  This process is USUALLY functional, but on some of the boards 
> (which we produce), the GPIO write fails with a bus error.  On the 
> boards that fail, it only occurs after a cold boot, and only if the 
> board has been powered off for a few minutes.  A quick hard reboot will 
> not generate the problem.  When I issue the failing write to the GPIO 
> lines, some of the SDRAM gets corrupted.  I don't appear to be taking 
> any interrupts that might have corrupted the RAM.
>  
> I've checked the TLB entries, and it maps correctly to the PPC register 
> area.  Additionally, I can read and write to other registers using the 
> same TLB mapping WITHOUT any error.  I can also READ the GPIO lines 
> without an error - the error is only on the write.   I've checked the 
> SDR0_PFC0 bits to make sure everything is set properly (it is).  The bus 
> error indicates "PLB Timeout Error Status Master 2, Master 2 slave error 
> occurred" (Master 2 is the write-only data cache unit (DCU)) and "Write 
> Error Interrupt Master 2, Write error detected - master 2 interrupt 
> request is active".  I'm not sure why there would be any error in the 
> DCU, since the region I'm writing to is cache inhibited and guarded.
>  
> If I issue a soft reset of the GPIO subsystem, I can read and write to 
> the GPIO lines again.
>  
> The error does not occur on the first write to the GPIO.  I go through 
> the failing routine several times before it fails.  However, when it 
> fails, it consistently fails at the same spot, after the same number of 
> passes through the code.
>  
> I'm using RGMII ethernet on EMAC2 (Group 4), but the GPIO lines that I'm 
> using are not the Trace/GPIO lines (26-31) so I believe that they should 
> work fine (and they usually do).  Also, the errata mentions that 
> SDR0_PFC0[G11E] has no effect - but I'm not using GPIO 11 anyway.
>  
> Here are some relevant register values after the error:
>  
> SDR0_PFC0 : 0x083FFE00
> POB0_BESR0: 0x8400
> POB0_BEARH: 0x0001
> POB0_BEARL: 0x4701
> GPIO0_OR  : 0x000400C0
> GPIO0_TCR : 0x00278AE0
> GPIO0_ODR : 0x
> GPIO0_IR  : 0x
>  
> I've attached two log files, that contain most of the 440 registers, one 
> for before the error and one after.  In the log files, the bus error has 
> been cleared, so use the values shown above.
>  
> I'm looking for some suggestions on what to try to debug/resolve this 
> issue.  I'm open to both hardware and software based suggestions.  Any 
> help would be greatly appreciated.
>  
>  
> Chris Wyse
> Senior Member of Technical Staff
> Embedded Technologies
> 860-978-0849 cell/office
> 413-778-9101 fax
> http://www.windriver.com 
>  
>  
> 
> 
> 
> 
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RE: [techfield] GPIO causing bus error

[Elayda, Bernardo (Bernie)]

Hi Chris,
 
I'm going to look at this problem from the FPGA hardware level because I
used to work for one of the FPGA companies.
 
I'm not familiar with your PPC440GX board, so some of my suggestions may
be difficult to implement or totally unreasonable, especially if it
requires soldering to an FPGA in a ball grid array or extermely fine
pitch pins.
 
(1) You should capture the configuration sequence on FPGA's JTAG pins
using a logic analyzer in functional mode.
 
In functional mode, you can capture an extermely long sequence of
configuration events.  Also, in the past, I've used this mode and found
that when the FPGA doesn't configure, usually there are too few or too
many clocks on the TCK line.
 
(2) Sometimes, rarely, the FPGA design itself can cause a boot up
problem.
 
Instead of using the real design, send a 'blank' design with no logic
implemented at all.  If this works, then it's the FPGA design itself
that is causing the boot problem.
 
(3) When the boot process happens, what is the power sequence of the
FPGA?
 
Most FPGA's out there like a nice smooth power profile that ramps up
quickly.  Check and see if the profile is quick and smooth vs. spikey
and erratic.  Also, sometimes configuration data gets sent before the
FPGA is ready to receive data.  Try delaying the sending of
configuration data by a millisecond or so.
 
(4) Manually delay the configuration of the FPGA.
 
In other words, let the system boot, but modify the code to allow the
FPGA to configure only after a button is pushed.  In theory, if the FPGA
power has properply initialized the FPGA, you could keep the system this
way forever until a 'button' is pushed to configure the FPGA.  if this
works, this tends to imply that there is a timing issue.  If it doesn't
work, it's possible that the FPGA's JTAG tap is actually in a state that
won't allow configuration to complete, such as non shift-dr or non
shift-ir state.
 
(5) If your FPGA is using one of the SVF-based software configuration
methods via JTAG, make sure you are using the latest SVF player and
latest software for generating the FPGA bitstream.  The configuration
method may have changed.  The FPGA silicon you are using may be newer
than the configuration algorithm that has been implemented.
 
I hope this helps!
 
Regards,
Bernie Elayda
the ex-X guy



From: [EMAIL PROTECTED]
[mailto:[EMAIL PROTECTED] On Behalf Of Wyse, Chris
Sent: Friday, December 21, 2007 7:55 AM
To: linuxppc-dev@ozlabs.org; [EMAIL PROTECTED]; +techfield;
+linux-embedded; +linux-eng; linux-kernel; Wessel, Jason;
[EMAIL PROTECTED]
Cc: Touron, Emmanuel; Read, Tricia; Ayer, Charles; Slimm, Rob
Subject: [techfield] GPIO causing bus error


Hi,
 
I'm having trouble with an unusual problem.  I'm working on relatively
new hardware, so it's possible that there could be a hardware issue
involved. 
 
I have an FPGA on my PPC440GX board that gets loaded via JTAG during the
kernel boot process (Linux 2.6.10).  It uses the 440GX GPIO lines to
send the necessary JTAG commands to the FPGA to perform the initial
load.  This process is USUALLY functional, but on some of the boards
(which we produce), the GPIO write fails with a bus error.  On the
boards that fail, it only occurs after a cold boot, and only if the
board has been powered off for a few minutes.  A quick hard reboot will
not generate the problem.  When I issue the failing write to the GPIO
lines, some of the SDRAM gets corrupted.  I don't appear to be taking
any interrupts that might have corrupted the RAM.
 
I've checked the TLB entries, and it maps correctly to the PPC register
area.  Additionally, I can read and write to other registers using the
same TLB mapping WITHOUT any error.  I can also READ the GPIO lines
without an error - the error is only on the write.   I've checked the
SDR0_PFC0 bits to make sure everything is set properly (it is).  The bus
error indicates "PLB Timeout Error Status Master 2, Master 2 slave error
occurred" (Master 2 is the write-only data cache unit (DCU)) and "Write
Error Interrupt Master 2, Write error detected - master 2 interrupt
request is active".  I'm not sure why there would be any error in the
DCU, since the region I'm writing to is cache inhibited and guarded.
 
If I issue a soft reset of the GPIO subsystem, I can read and write to
the GPIO lines again.
 
The error does not occur on the first write to the GPIO.  I go through
the failing routine several times before it fails.  However, when it
fails, it consistently fails at the same spot, after the same number of
passes through the code.
 
I'm using RGMII ethernet on EMAC2 (Group 4), but the GPIO lines that I'm
using are not the Trace/GPIO lines (26-31) so I believe that they should
work fine (and they usually do).  Also, the errata mentions that
SDR0_PFC0[G11E] has no effect - but I'm not using GPIO 11 anyway.
 
Here are some relevant register values after the error:
 
SDR0_PFC0 : 0x083FFE00
POB0_BESR0: 0x8400
POB0_BEARH: 0

Re: [PATCH 4/4] PowerPC: Add PCI node to 440GRx Rainier DTS.

[Benjamin Herrenschmidt]

On Sat, 2007-12-22 at 06:54 +0100, Stefan Roese wrote:
> On Friday 21 December 2007, Benjamin Herrenschmidt wrote:
> > On Fri, 2007-12-21 at 19:27 +0300, Valentine Barshak wrote:
> > > +   /* All PCI interrupts are routed to IRQ 67 */
> > > +   interrupt-map-mask = < 0 0 0>;
> > > +   interrupt-map = <  0 0 0 &UIC2 3 8 >;
> > > +   };
> >
> > Same question as for Sequoia...
> 
> Correct here too. Rainier (440GRx) is basically a stripped of version of the 
> Sequioa (440EPx).

I hope they accompany it with a design note: "don't do that in your
actual products" :-)

Ben.


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Re: [PATCH 3/4] PowerPC: Add PCI entry to 440EPx Sequoia DTS.

[Stefan Roese]

On Friday 21 December 2007, Benjamin Herrenschmidt wrote:
> On Fri, 2007-12-21 at 19:26 +0300, Valentine Barshak wrote:
> > +
> > +   /* All PCI interrupts are routed to IRQ 67 */
> > +   interrupt-map-mask = < 0 0 0>;
> > +   interrupt-map = <  0 0 0 &UIC2 3 8 >;
> > +   };
> > };
>
> Wow, all 4 lines of all slots ?

Yes, that's unfortunately correct. :-(

Best regards,
Stefan
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Re: [PATCH 4/4] PowerPC: Add PCI node to 440GRx Rainier DTS.

[Stefan Roese]

On Friday 21 December 2007, Benjamin Herrenschmidt wrote:
> On Fri, 2007-12-21 at 19:27 +0300, Valentine Barshak wrote:
> > +   /* All PCI interrupts are routed to IRQ 67 */
> > +   interrupt-map-mask = < 0 0 0>;
> > +   interrupt-map = <  0 0 0 &UIC2 3 8 >;
> > +   };
>
> Same question as for Sequoia...

Correct here too. Rainier (440GRx) is basically a stripped of version of the 
Sequioa (440EPx).

Berst regards,
Stefan
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