Re: [PATCH v5 1/3] dt-bindings: reset: microchip sparx5 reset driver bindings
Hi Alex,
On Mon, 2021-02-15 at 18:32 +0100, Alexandre Belloni wrote:
> EXTERNAL EMAIL: Do not click links or open attachments unless you
> know the content is safe
>
> On 10/02/2021 10:19:50+0100, Steen Hegelund wrote:
> > Document the Sparx5 reset device driver bindings
> >
> > The driver uses two IO ranges on sparx5 for access to
> > the reset control and the reset status.
> >
> > Signed-off-by: Steen Hegelund
> > ---
> > .../bindings/reset/microchip,rst.yaml | 55
> > +++
> > 1 file changed, 55 insertions(+)
> > create mode 100644
> > Documentation/devicetree/bindings/reset/microchip,rst.yaml
> >
> > diff --git
> > a/Documentation/devicetree/bindings/reset/microchip,rst.yaml
> > b/Documentation/devicetree/bindings/reset/microchip,rst.yaml
> > new file mode 100644
> > index ..80046172c9f8
> > --- /dev/null
> > +++ b/Documentation/devicetree/bindings/reset/microchip,rst.yaml
> > @@ -0,0 +1,55 @@
> > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> > +%YAML 1.2
> > +---
> > +$id: "http://devicetree.org/schemas/reset/microchip,rst.yaml#";
> > +$schema: "http://devicetree.org/meta-schemas/core.yaml#";
> > +
> > +title: Microchip Sparx5 Switch Reset Controller
> > +
> > +maintainers:
> > + - Steen Hegelund
> > + - Lars Povlsen
> > +
> > +description: |
> > + The Microchip Sparx5 Switch provides reset control and
> > implements the following
> > + functions
> > + - One Time Switch Core Reset (Soft Reset)
> > +
> > +properties:
> > + $nodename:
> > + pattern: "^reset-controller@[0-9a-f]+$"
> > +
> > + compatible:
> > + const: microchip,sparx5-switch-reset
> > +
> > + reg:
> > + items:
> > + - description: cpu block registers
> > + - description: global control block registers
> > +
> > + reg-names:
> > + items:
> > + - const: cpu
> > + - const: gcb
> > +
>
> I still think this is not right because then you will be mapping the
> same set of register using multiple drivers without any form of
> synchronisation which will work because you are mapping the region
> without requesting it. But this may lead to issues later.
>
> At least, you should make cpu start at 0x80 and of size 4. Else, you
> won't be able to define and use the GPRs that are in front of
> CPU_REGS:RESET.
>
> I would still keep DEVCPU_GCB:CHIP_REGS as a syscon, especially since
> you are mapping the whole set of registers.
Ok. I will use a syscon for the General Control Block and a very small
range for the CPU Reset register, to minimize the register footprint.
>
>
> > + "#reset-cells":
> > + const: 1
> > +
> > +required:
> > + - compatible
> > + - reg
> > + - reg-names
> > + - "#reset-cells"
> > +
> > +additionalProperties: false
> > +
> > +examples:
> > + - |
> > + reset: reset-controller@0 {
> > + compatible = "microchip,sparx5-switch-reset";
> > + #reset-cells = <1>;
> > + reg = <0x0 0xd0>,
> > + <0x1101 0x1>;
> > + reg-names = "cpu", "gcb";
> > + };
> > +
> > --
> > 2.30.0
> >
>
> --
> Alexandre Belloni, Bootlin
> Embedded Linux and Kernel engineering
> https://bootlin.com
Thanks for your comments
--
BR
Steen
-=-=-=-=-=-=-=-=-=-=-=-=-=-=
steen.hegel...@microchip.com
Re: [PATCH v14 2/4] phy: Add media type and speed serdes configuration interfaces
Hi Andrew and Kishon, On Mon, 2021-02-15 at 15:07 +0100, Andrew Lunn wrote: > EXTERNAL EMAIL: Do not click links or open attachments unless you > know the content is safe > > On Mon, Feb 15, 2021 at 05:25:10PM +0530, Kishon Vijay Abraham I > wrote: > > Okay. Is it going to be some sort of manual negotiation where the > > Ethernet controller invokes set_speed with different speeds? Or the > > Ethernet controller will get the speed using some out of band > > mechanism > > and invokes set_speed once with the actual speed? > > Hi Kishon > > There are a few different mechanism possible. > > The SFP has an EEPROM which contains lots of parameters. One is the > maximum baud rate the module supports. PHYLINK will combine this > information with the MAC capabilities to determine the default speed. > > The users can select the mode the MAC works in, e.g. 1000BaseX vs > 2500BaseX, via ethtool -s. Different modes needs different speeds. > > Some copper PHYs will change there host side interface baud rate when > the media side interface changes mode. 10GBASE-X for 10G copper, > 5GBase-X for 5G COPPER, 2500Base-X for 2.5G copper, and SGMII for > old school 10/100/1G Ethernet. > > Mainline Linux has no support for it, but some 'vendor crap' will do > a > manual negotiation, simply trying different speeds and see if the > SERDES establishes link. There is nothing standardised for this, as > far as i know. > > Andrew Yes, in case I mention the only way to ensure communication is human intervention to set the speed to the highest common denominator. BR Steen
Re: [PATCH v14 2/4] phy: Add media type and speed serdes configuration interfaces
Hi David,
On Wed, 2021-02-10 at 15:32 -0800, David Miller wrote:
> EXTERNAL EMAIL: Do not click links or open attachments unless you
> know the content is safe
>
> From: Steen Hegelund
> Date: Wed, 10 Feb 2021 09:52:53 +0100
>
> > Provide new phy configuration interfaces for media type and speed
> > that
> > allows allows e.g. PHYs used for ethernet to be configured with
> > this
> > information.
> >
> > Signed-off-by: Lars Povlsen
> > Signed-off-by: Steen Hegelund
> > Reviewed-by: Andrew Lunn
> > Reviewed-by: Alexandre Belloni
> > ---
> > drivers/phy/phy-core.c | 30 ++
> > include/linux/phy/phy.h | 26 ++
> > 2 files changed, 56 insertions(+)
> >
> > diff --git a/drivers/phy/phy-core.c b/drivers/phy/phy-core.c
> > index 71cb10826326..ccb575b13777 100644
> > --- a/drivers/phy/phy-core.c
> > +++ b/drivers/phy/phy-core.c
> > @@ -373,6 +373,36 @@ int phy_set_mode_ext(struct phy *phy, enum
> > phy_mode mode, int submode)
> > }
> > EXPORT_SYMBOL_GPL(phy_set_mode_ext);
> >
> > +int phy_set_media(struct phy *phy, enum phy_media media)
> > +{
> > + int ret;
> > +
> > + if (!phy || !phy->ops->set_media)
> > + return 0;
> > +
> > + mutex_lock(&phy->mutex);
> > + ret = phy->ops->set_media(phy, media);
> > + mutex_unlock(&phy->mutex);
> > +
> > + return ret;
> > +}
> > +EXPORT_SYMBOL_GPL(phy_set_media);
> > +
> > +int phy_set_speed(struct phy *phy, int speed)
> > +{
> > + int ret;
> > +
> > + if (!phy || !phy->ops->set_speed)
> > + return 0;
> > +
> > + mutex_lock(&phy->mutex);
> > + ret = phy->ops->set_speed(phy, speed);
> > + mutex_unlock(&phy->mutex);
> > +
> > + return ret;
> > +}
> > +EXPORT_SYMBOL_GPL(phy_set_speed);
> > +
> > int phy_reset(struct phy *phy)
> > {
> > int ret;
> > diff --git a/include/linux/phy/phy.h b/include/linux/phy/phy.h
> > index e435bdb0bab3..e4fd69a1faa7 100644
> > --- a/include/linux/phy/phy.h
> > +++ b/include/linux/phy/phy.h
> > @@ -44,6 +44,12 @@ enum phy_mode {
> > PHY_MODE_DP
> > };
> >
> > +enum phy_media {
> > + PHY_MEDIA_DEFAULT,
> > + PHY_MEDIA_SR,
> > + PHY_MEDIA_DAC,
> > +};
> > +
> > /**
> > * union phy_configure_opts - Opaque generic phy configuration
> > *
> > @@ -64,6 +70,8 @@ union phy_configure_opts {
> > * @power_on: powering on the phy
> > * @power_off: powering off the phy
> > * @set_mode: set the mode of the phy
> > + * @set_media: set the media type of the phy (optional)
> > + * @set_speed: set the speed of the phy (optional)
> > * @reset: resetting the phy
> > * @calibrate: calibrate the phy
> > * @release: ops to be performed while the consumer relinquishes
> > the PHY
> > @@ -75,6 +83,8 @@ struct phy_ops {
> > int (*power_on)(struct phy *phy);
> > int (*power_off)(struct phy *phy);
> > int (*set_mode)(struct phy *phy, enum phy_mode mode, int
> > submode);
> > + int (*set_media)(struct phy *phy, enum phy_media media);
> > + int (*set_speed)(struct phy *phy, int speed);
> >
> > /**
> > * @configure:
> > @@ -215,6 +225,8 @@ int phy_power_off(struct phy *phy);
> > int phy_set_mode_ext(struct phy *phy, enum phy_mode mode, int
> > submode);
> > #define phy_set_mode(phy, mode) \
> > phy_set_mode_ext(phy, mode, 0)
> > +int phy_set_media(struct phy *phy, enum phy_media media);
> > +int phy_set_speed(struct phy *phy, int speed);
> > int phy_configure(struct phy *phy, union phy_configure_opts
> > *opts);
> > int phy_validate(struct phy *phy, enum phy_mode mode, int submode,
> > union phy_configure_opts *opts);
> > @@ -344,6 +356,20 @@ static inline int phy_set_mode_ext(struct phy
> > *phy, enum phy_mode mode,
> > #define phy_set_mode(phy, mode) \
> > phy_set_mode_ext(phy, mode, 0)
> >
> > +static inline int phy_set_media(struct phy *phy, enum phy_media
> > media)
> > +{
> > + if (!phy)
> > + return 0;
> > + return -ENOSYS;
> > +}
>
> Maybe ENODEV instead?
Sure. I will update that.
--
BR
Steen
-=-=-=-=-=-=-=-=-=-=-=-=-=-=
steen.hegel...@microchip.com
Re: [PATCH v14 2/4] phy: Add media type and speed serdes configuration interfaces
Hi Kishon,
On Fri, 2021-02-12 at 17:02 +0530, Kishon Vijay Abraham I wrote:
> EXTERNAL EMAIL: Do not click links or open attachments unless you
> know the content is safe
>
> Hi Steen,
>
> On 10/02/21 2:22 pm, Steen Hegelund wrote:
> > Provide new phy configuration interfaces for media type and speed
> > that
> > allows allows e.g. PHYs used for ethernet to be configured with
> > this
> > information.
> >
> > Signed-off-by: Lars Povlsen
> > Signed-off-by: Steen Hegelund
> > Reviewed-by: Andrew Lunn
> > Reviewed-by: Alexandre Belloni
> > ---
> > drivers/phy/phy-core.c | 30 ++
> > include/linux/phy/phy.h | 26 ++
> > 2 files changed, 56 insertions(+)
> >
> > diff --git a/drivers/phy/phy-core.c b/drivers/phy/phy-core.c
> > index 71cb10826326..ccb575b13777 100644
> > --- a/drivers/phy/phy-core.c
> > +++ b/drivers/phy/phy-core.c
> > @@ -373,6 +373,36 @@ int phy_set_mode_ext(struct phy *phy, enum
> > phy_mode mode, int submode)
> > }
> > EXPORT_SYMBOL_GPL(phy_set_mode_ext);
> >
> > +int phy_set_media(struct phy *phy, enum phy_media media)
> > +{
> > + int ret;
> > +
> > + if (!phy || !phy->ops->set_media)
> > + return 0;
> > +
> > + mutex_lock(&phy->mutex);
> > + ret = phy->ops->set_media(phy, media);
> > + mutex_unlock(&phy->mutex);
> > +
> > + return ret;
> > +}
> > +EXPORT_SYMBOL_GPL(phy_set_media);
> > +
> > +int phy_set_speed(struct phy *phy, int speed)
> > +{
> > + int ret;
> > +
> > + if (!phy || !phy->ops->set_speed)
> > + return 0;
> > +
> > + mutex_lock(&phy->mutex);
> > + ret = phy->ops->set_speed(phy, speed);
> > + mutex_unlock(&phy->mutex);
> > +
> > + return ret;
> > +}
> > +EXPORT_SYMBOL_GPL(phy_set_speed);
>
> Can't speed derived from mode? Do we need a separate set_speed
> function?
>
> Thanks
> Kishon
Yes the client will need to be able to choose the speed as needed:
e.g. lower than the serdes mode supports, in case the the media or the
other end is not capable of running that speed.
An example is a 10G and 25G serdes connected via DAC and as there is no
inband autoneg, the 25G client would have to manually select 10G speed
to communicate with its partner.
>
> > +
> > int phy_reset(struct phy *phy)
> > {
> > int ret;
> > diff --git a/include/linux/phy/phy.h b/include/linux/phy/phy.h
> > index e435bdb0bab3..e4fd69a1faa7 100644
> > --- a/include/linux/phy/phy.h
> > +++ b/include/linux/phy/phy.h
> > @@ -44,6 +44,12 @@ enum phy_mode {
> > PHY_MODE_DP
> > };
> >
> > +enum phy_media {
> > + PHY_MEDIA_DEFAULT,
> > + PHY_MEDIA_SR,
> > + PHY_MEDIA_DAC,
> > +};
> > +
> > /**
> > * union phy_configure_opts - Opaque generic phy configuration
> > *
> > @@ -64,6 +70,8 @@ union phy_configure_opts {
> > * @power_on: powering on the phy
> > * @power_off: powering off the phy
> > * @set_mode: set the mode of the phy
> > + * @set_media: set the media type of the phy (optional)
> > + * @set_speed: set the speed of the phy (optional)
> > * @reset: resetting the phy
> > * @calibrate: calibrate the phy
> > * @release: ops to be performed while the consumer relinquishes
> > the PHY
> > @@ -75,6 +83,8 @@ struct phy_ops {
> > int (*power_on)(struct phy *phy);
> > int (*power_off)(struct phy *phy);
> > int (*set_mode)(struct phy *phy, enum phy_mode mode, int
> > submode);
> > + int (*set_media)(struct phy *phy, enum phy_media media);
> > + int (*set_speed)(struct phy *phy, int speed);
> >
> > /**
> > * @configure:
> > @@ -215,6 +225,8 @@ int phy_power_off(struct phy *phy);
> > int phy_set_mode_ext(struct phy *phy, enum phy_mode mode, int
> > submode);
> > #define phy_set_mode(phy, mode) \
> > phy_set_mode_ext(phy, mode, 0)
> > +int phy_set_media(struct phy *phy, enum phy_media media);
> > +int phy_set_speed(struct phy *phy, int speed);
> > int phy_configure(struct phy *phy, union phy_configure_opts
> > *opts);
> > int phy_validate(struct phy *phy, enum phy_mode mode, int submode,
> > union phy_configure_opts *opts);
> > @@ -344,6 +356,20 @@ static inline int phy_set_mode_ext(struct phy
> > *phy, enum phy_mode mode,
> > #define phy_set_mode(phy, mode) \
> > phy_set_mode_ext(phy, mode, 0)
> >
> > +static inline int phy_set_media(struct phy *phy, enum phy_media
> > media)
> > +{
> > + if (!phy)
> > + return 0;
> > + return -ENOSYS;
> > +}
> > +
> > +static inline int phy_set_speed(struct phy *phy, int speed)
> > +{
> > + if (!phy)
> > + return 0;
> > + return -ENOSYS;
> > +}
> > +
> > static inline enum phy_mode phy_get_mode(struct phy *phy)
> > {
> > return PHY_MODE_INVALID;
> >
Thanks for your comments.
--
BR
Steen
-=-=-=-=-=-=-=-=-=-=-=-=-=-=
steen.hegel...@microchip.com
[PATCH v14 0/4] Adding the Sparx5 Serdes driver
Rebased on v5.11-rc1 v9 -> v10: Only add the new folder to the phy Kconfig (no sort fix) Corrected the serdes mode conversion for 2.5G mode. Clarified the SGMII and 1000BASEX conversion. Improved some of the more cryptic error messages. Expanded the validate function a bit, and removed the link status from the return value. v8 -> v9: Replace pr_err with dev_err Expanded the description here in the cover letter (should probably og into the driver, at least part of it). v7 -> v8: Provide the IO targets as offsets from the start of the IO range Initialise resource index v6 -> v7: This series changes the way the IO targets are provided to the driver. Now only one IO range is available in the DT, and the driver has a table to map its targets (as their order is still not sequential), thus reducing the DT needed information and binding requirements. The register access macros have been converted to functions. - Bindings: - reg prop: minItems set to 1 - reg-names prop: removed - Driver - Use one IO range and map targets via this. - Change register access macros to use functions. - Provided a new header files with reg access functions. - Device tree - Provide only one IO range v5 -> v6: Series error: This had the same content as v5 v4 -> v5: - Bindings: - Removed .yaml from compatible string - reg prop: removed description and added minItems - reg-names prop: removed description and added const name list and minItems - #phy-cells prop: removed description and added maxItems - Configuration interface - Removed include of linux/phy.h - Added include of linux/types.h - Driver - Added include of linux/phy.h v3 -> v4: - Add a reg-names item to the binding description - Add a clocks item to the binding description - Removed the clock parameter from the configuration interface - Use the clock dt node to get the coreclock, and using that when doing the actual serdes configuration - Added a clocks entry with a system clock reference to the serdes node in the device tree v2 -> v3: - Sorted the Kconfig sourced folders - Sorted the Makefile included folders - Changed the configuration interface documentation to use kernel style v1 -> v2: Fixed kernel test robot warnings - Made these structures static: - media_presets_25g - mode_presets_25g - media_presets_10g - mode_presets_10g - Removed these duplicate initializations: - sparx5_sd25g28_params.cfg_rx_reserve_15_8 - sparx5_sd25g28_params.cfg_pi_en - sparx5_sd25g28_params.cfg_cdrck_en - sparx5_sd10g28_params.cfg_cdrck_en Steen Hegelund (4): dt-bindings: phy: Add sparx5-serdes bindings phy: Add media type and speed serdes configuration interfaces phy: Add Sparx5 ethernet serdes PHY driver arm64: dts: sparx5: Add Sparx5 serdes driver node .../bindings/phy/microchip,sparx5-serdes.yaml | 100 + arch/arm64/boot/dts/microchip/sparx5.dtsi |8 + drivers/phy/Kconfig |1 + drivers/phy/Makefile |1 + drivers/phy/microchip/Kconfig | 12 + drivers/phy/microchip/Makefile|6 + drivers/phy/microchip/sparx5_serdes.c | 2467 +++ drivers/phy/microchip/sparx5_serdes.h | 136 + drivers/phy/microchip/sparx5_serdes_regs.h| 2695 + drivers/phy/phy-core.c| 30 + include/linux/phy/phy.h | 26 + 11 files changed, 5482 insertions(+) create mode 100644 Documentation/devicetree/bindings/phy/microchip,sparx5-serdes.yaml create mode 100644 drivers/phy/microchip/Kconfig create mode 100644 drivers/phy/microchip/Makefile create mode 100644 drivers/phy/microchip/sparx5_serdes.c create mode 100644 drivers/phy/microchip/sparx5_serdes.h create mode 100644 drivers/phy/microchip/sparx5_serdes_regs.h -- 2.30.0
[PATCH v14 1/4] dt-bindings: phy: Add sparx5-serdes bindings
Document the Sparx5 ethernet serdes phy driver bindings.
Signed-off-by: Lars Povlsen
Signed-off-by: Steen Hegelund
Reviewed-by: Rob Herring
Reviewed-by: Andrew Lunn
Reviewed-by: Alexandre Belloni
---
.../bindings/phy/microchip,sparx5-serdes.yaml | 100 ++
1 file changed, 100 insertions(+)
create mode 100644
Documentation/devicetree/bindings/phy/microchip,sparx5-serdes.yaml
diff --git a/Documentation/devicetree/bindings/phy/microchip,sparx5-serdes.yaml
b/Documentation/devicetree/bindings/phy/microchip,sparx5-serdes.yaml
new file mode 100644
index ..bdbdb3bbddbe
--- /dev/null
+++ b/Documentation/devicetree/bindings/phy/microchip,sparx5-serdes.yaml
@@ -0,0 +1,100 @@
+# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/phy/microchip,sparx5-serdes.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Microchip Sparx5 Serdes controller
+
+maintainers:
+ - Steen Hegelund
+
+description: |
+ The Sparx5 SERDES interfaces share the same basic functionality, but
+ support different operating modes and line rates.
+
+ The following list lists the SERDES features:
+
+ * RX Adaptive Decision Feedback Equalizer (DFE)
+ * Programmable continuous time linear equalizer (CTLE)
+ * Rx variable gain control
+ * Rx built-in fault detector (loss-of-lock/loss-of-signal)
+ * Adjustable tx de-emphasis (FFE)
+ * Tx output amplitude control
+ * Supports rx eye monitor
+ * Multiple loopback modes
+ * Prbs generator and checker
+ * Polarity inversion control
+
+ SERDES6G:
+
+ The SERDES6G is a high-speed SERDES interface, which can operate at
+ the following data rates:
+
+ * 100 Mbps (100BASE-FX)
+ * 1.25 Gbps (SGMII/1000BASE-X/1000BASE-KX)
+ * 3.125 Gbps (2.5GBASE-X/2.5GBASE-KX)
+ * 5.15625 Gbps (5GBASE-KR/5G-USXGMII)
+
+ SERDES10G
+
+ The SERDES10G is a high-speed SERDES interface, which can operate at
+ the following data rates:
+
+ * 100 Mbps (100BASE-FX)
+ * 1.25 Gbps (SGMII/1000BASE-X/1000BASE-KX)
+ * 3.125 Gbps (2.5GBASE-X/2.5GBASE-KX)
+ * 5 Gbps (QSGMII/USGMII)
+ * 5.15625 Gbps (5GBASE-KR/5G-USXGMII)
+ * 10 Gbps (10G-USGMII)
+ * 10.3125 Gbps (10GBASE-R/10GBASE-KR/USXGMII)
+
+ SERDES25G
+
+ The SERDES25G is a high-speed SERDES interface, which can operate at
+ the following data rates:
+
+ * 1.25 Gbps (SGMII/1000BASE-X/1000BASE-KX)
+ * 3.125 Gbps (2.5GBASE-X/2.5GBASE-KX)
+ * 5 Gbps (QSGMII/USGMII)
+ * 5.15625 Gbps (5GBASE-KR/5G-USXGMII)
+ * 10 Gbps (10G-USGMII)
+ * 10.3125 Gbps (10GBASE-R/10GBASE-KR/USXGMII)
+ * 25.78125 Gbps (25GBASE-KR/25GBASE-CR/25GBASE-SR/25GBASE-LR/25GBASE-ER)
+
+properties:
+ $nodename:
+pattern: "^serdes@[0-9a-f]+$"
+
+ compatible:
+const: microchip,sparx5-serdes
+
+ reg:
+minItems: 1
+
+ '#phy-cells':
+const: 1
+description: |
+ - The main serdes input port
+
+ clocks:
+maxItems: 1
+
+required:
+ - compatible
+ - reg
+ - '#phy-cells'
+ - clocks
+
+additionalProperties: false
+
+examples:
+ - |
+serdes: serdes@10808000 {
+ compatible = "microchip,sparx5-serdes";
+ #phy-cells = <1>;
+ clocks = <&sys_clk>;
+ reg = <0x10808000 0x5d>;
+};
+
+...
--
2.30.0
[PATCH v14 2/4] phy: Add media type and speed serdes configuration interfaces
Provide new phy configuration interfaces for media type and speed that
allows allows e.g. PHYs used for ethernet to be configured with this
information.
Signed-off-by: Lars Povlsen
Signed-off-by: Steen Hegelund
Reviewed-by: Andrew Lunn
Reviewed-by: Alexandre Belloni
---
drivers/phy/phy-core.c | 30 ++
include/linux/phy/phy.h | 26 ++
2 files changed, 56 insertions(+)
diff --git a/drivers/phy/phy-core.c b/drivers/phy/phy-core.c
index 71cb10826326..ccb575b13777 100644
--- a/drivers/phy/phy-core.c
+++ b/drivers/phy/phy-core.c
@@ -373,6 +373,36 @@ int phy_set_mode_ext(struct phy *phy, enum phy_mode mode,
int submode)
}
EXPORT_SYMBOL_GPL(phy_set_mode_ext);
+int phy_set_media(struct phy *phy, enum phy_media media)
+{
+ int ret;
+
+ if (!phy || !phy->ops->set_media)
+ return 0;
+
+ mutex_lock(&phy->mutex);
+ ret = phy->ops->set_media(phy, media);
+ mutex_unlock(&phy->mutex);
+
+ return ret;
+}
+EXPORT_SYMBOL_GPL(phy_set_media);
+
+int phy_set_speed(struct phy *phy, int speed)
+{
+ int ret;
+
+ if (!phy || !phy->ops->set_speed)
+ return 0;
+
+ mutex_lock(&phy->mutex);
+ ret = phy->ops->set_speed(phy, speed);
+ mutex_unlock(&phy->mutex);
+
+ return ret;
+}
+EXPORT_SYMBOL_GPL(phy_set_speed);
+
int phy_reset(struct phy *phy)
{
int ret;
diff --git a/include/linux/phy/phy.h b/include/linux/phy/phy.h
index e435bdb0bab3..e4fd69a1faa7 100644
--- a/include/linux/phy/phy.h
+++ b/include/linux/phy/phy.h
@@ -44,6 +44,12 @@ enum phy_mode {
PHY_MODE_DP
};
+enum phy_media {
+ PHY_MEDIA_DEFAULT,
+ PHY_MEDIA_SR,
+ PHY_MEDIA_DAC,
+};
+
/**
* union phy_configure_opts - Opaque generic phy configuration
*
@@ -64,6 +70,8 @@ union phy_configure_opts {
* @power_on: powering on the phy
* @power_off: powering off the phy
* @set_mode: set the mode of the phy
+ * @set_media: set the media type of the phy (optional)
+ * @set_speed: set the speed of the phy (optional)
* @reset: resetting the phy
* @calibrate: calibrate the phy
* @release: ops to be performed while the consumer relinquishes the PHY
@@ -75,6 +83,8 @@ struct phy_ops {
int (*power_on)(struct phy *phy);
int (*power_off)(struct phy *phy);
int (*set_mode)(struct phy *phy, enum phy_mode mode, int submode);
+ int (*set_media)(struct phy *phy, enum phy_media media);
+ int (*set_speed)(struct phy *phy, int speed);
/**
* @configure:
@@ -215,6 +225,8 @@ int phy_power_off(struct phy *phy);
int phy_set_mode_ext(struct phy *phy, enum phy_mode mode, int submode);
#define phy_set_mode(phy, mode) \
phy_set_mode_ext(phy, mode, 0)
+int phy_set_media(struct phy *phy, enum phy_media media);
+int phy_set_speed(struct phy *phy, int speed);
int phy_configure(struct phy *phy, union phy_configure_opts *opts);
int phy_validate(struct phy *phy, enum phy_mode mode, int submode,
union phy_configure_opts *opts);
@@ -344,6 +356,20 @@ static inline int phy_set_mode_ext(struct phy *phy, enum
phy_mode mode,
#define phy_set_mode(phy, mode) \
phy_set_mode_ext(phy, mode, 0)
+static inline int phy_set_media(struct phy *phy, enum phy_media media)
+{
+ if (!phy)
+ return 0;
+ return -ENOSYS;
+}
+
+static inline int phy_set_speed(struct phy *phy, int speed)
+{
+ if (!phy)
+ return 0;
+ return -ENOSYS;
+}
+
static inline enum phy_mode phy_get_mode(struct phy *phy)
{
return PHY_MODE_INVALID;
--
2.30.0
[PATCH v14 4/4] arm64: dts: sparx5: Add Sparx5 serdes driver node
Add Sparx5 serdes driver node, and enable it generally for all
reference boards.
Signed-off-by: Lars Povlsen
Signed-off-by: Steen Hegelund
Reviewed-by: Andrew Lunn
Reviewed-by: Alexandre Belloni
---
arch/arm64/boot/dts/microchip/sparx5.dtsi | 8
1 file changed, 8 insertions(+)
diff --git a/arch/arm64/boot/dts/microchip/sparx5.dtsi
b/arch/arm64/boot/dts/microchip/sparx5.dtsi
index 380281f312d8..29c606194bc7 100644
--- a/arch/arm64/boot/dts/microchip/sparx5.dtsi
+++ b/arch/arm64/boot/dts/microchip/sparx5.dtsi
@@ -383,5 +383,13 @@ tmon0: tmon@610508110 {
#thermal-sensor-cells = <0>;
clocks = <&ahb_clk>;
};
+
+ serdes: serdes@10808000 {
+ compatible = "microchip,sparx5-serdes";
+ #phy-cells = <1>;
+ clocks = <&sys_clk>;
+ reg = <0x6 0x10808000 0x5d>;
+ };
+
};
};
--
2.30.0
[PATCH v5 0/3] Adding the Sparx5 Switch Reset Driver
This series provides the Microchip Sparx5 Switch Reset Driver The Sparx5 Switch SoC has a number of components that can be reset individually, but at least the Switch Core needs to be in a well defined state at power on, when any of the Sparx5 drivers starts to access the Switch Core, this reset driver is available. The reset driver is loaded early via the postcore_initcall interface, and will then be available for the other Sparx5 drivers (SGPIO, SwitchDev etc) that are loaded next, and the first of them to be loaded can perform the one-time Switch Core reset that is needed. The driver has protection so that the system busses, DDR controller, PCI-E and ARM A53 CPU and a few other subsystems are not touched by the reset. The Sparx5 Chip Register Model can be browsed at this location: https://github.com/microchip-ung/sparx-5_reginfo History: v4 -> v5 Changed the two syscons into IO ranges and updated the bindings to reflect this change. v3 -> v4 Added commit message descriptions v2 -> v3 Removed unused headers Renamed the reset controller dev member. Use regmap_read_poll_timeout instead of polling a function. Used two separate syscon entries in the binding Simplified the syscon error handling. Simplified the devm_reset_controller_register error handling. Moved the contents of the mchp_sparx5_reset_config function into the probe function. v1 -> v2 Removed debug prints Changed the error handling to save the error code before jumping. Steen Hegelund (3): dt-bindings: reset: microchip sparx5 reset driver bindings reset: mchp: sparx5: add switch reset driver arm64: dts: reset: add microchip sparx5 switch reset driver .../bindings/reset/microchip,rst.yaml | 55 arch/arm64/boot/dts/microchip/sparx5.dtsi | 9 +- drivers/reset/Kconfig | 8 ++ drivers/reset/Makefile| 1 + drivers/reset/reset-microchip-sparx5.c| 130 ++ 5 files changed, 200 insertions(+), 3 deletions(-) create mode 100644 Documentation/devicetree/bindings/reset/microchip,rst.yaml create mode 100644 drivers/reset/reset-microchip-sparx5.c -- 2.30.0
[PATCH v5 2/3] reset: mchp: sparx5: add switch reset driver
The Sparx5 Switch SoC has a number of components that can be reset
indiviually, but at least the Switch Core needs to be in a well defined
state at power on, when any of the Sparx5 drivers starts to access the
Switch Core, this reset driver is available.
The reset driver is loaded early via the postcore_initcall interface, and
will then be available for the other Sparx5 drivers (SGPIO, SwitchDev etc)
that are loaded next, and the first of them to be loaded can perform the
one-time Switch Core reset that is needed.
The driver has protection so that the system busses, DDR controller, PCI-E
and ARM A53 CPU and a few other subsystems are not touched by the reset.
Signed-off-by: Steen Hegelund
---
drivers/reset/Kconfig | 8 ++
drivers/reset/Makefile | 1 +
drivers/reset/reset-microchip-sparx5.c | 130 +
3 files changed, 139 insertions(+)
create mode 100644 drivers/reset/reset-microchip-sparx5.c
diff --git a/drivers/reset/Kconfig b/drivers/reset/Kconfig
index 71ab75a46491..05c240c47a8a 100644
--- a/drivers/reset/Kconfig
+++ b/drivers/reset/Kconfig
@@ -101,6 +101,14 @@ config RESET_LPC18XX
help
This enables the reset controller driver for NXP LPC18xx/43xx SoCs.
+config RESET_MCHP_SPARX5
+ bool "Microchip Sparx5 reset driver"
+ depends on HAS_IOMEM || COMPILE_TEST
+ default y if SPARX5_SWITCH
+ select MFD_SYSCON
+ help
+ This driver supports switch core reset for the Microchip Sparx5 SoC.
+
config RESET_MESON
tristate "Meson Reset Driver"
depends on ARCH_MESON || COMPILE_TEST
diff --git a/drivers/reset/Makefile b/drivers/reset/Makefile
index 1054123fd187..341fd9ab4bf6 100644
--- a/drivers/reset/Makefile
+++ b/drivers/reset/Makefile
@@ -15,6 +15,7 @@ obj-$(CONFIG_RESET_IMX7) += reset-imx7.o
obj-$(CONFIG_RESET_INTEL_GW) += reset-intel-gw.o
obj-$(CONFIG_RESET_LANTIQ) += reset-lantiq.o
obj-$(CONFIG_RESET_LPC18XX) += reset-lpc18xx.o
+obj-$(CONFIG_RESET_MCHP_SPARX5) += reset-microchip-sparx5.o
obj-$(CONFIG_RESET_MESON) += reset-meson.o
obj-$(CONFIG_RESET_MESON_AUDIO_ARB) += reset-meson-audio-arb.o
obj-$(CONFIG_RESET_NPCM) += reset-npcm.o
diff --git a/drivers/reset/reset-microchip-sparx5.c
b/drivers/reset/reset-microchip-sparx5.c
new file mode 100644
index ..b243a12af085
--- /dev/null
+++ b/drivers/reset/reset-microchip-sparx5.c
@@ -0,0 +1,130 @@
+// SPDX-License-Identifier: GPL-2.0+
+/* Microchip Sparx5 Switch Reset driver
+ *
+ * Copyright (c) 2020 Microchip Technology Inc. and its subsidiaries.
+ *
+ * The Sparx5 Chip Register Model can be browsed at this location:
+ * https://github.com/microchip-ung/sparx-5_reginfo
+ */
+#include
+#include
+#include
+#include
+#include
+#include
+
+#define PROTECT_REG0x84
+#define PROTECT_BITBIT(10)
+#define SOFT_RESET_REG 0x08
+#define SOFT_RESET_BIT BIT(1)
+
+struct mchp_reset_context {
+ struct regmap *cpu_ctrl;
+ struct regmap *gcb_ctrl;
+ struct reset_controller_dev rcdev;
+};
+
+static struct regmap_config sparx5_reset_regmap_config = {
+ .reg_bits = 32,
+ .val_bits = 32,
+ .reg_stride = 4,
+};
+
+static int sparx5_switch_reset(struct reset_controller_dev *rcdev,
+ unsigned long id)
+{
+ struct mchp_reset_context *ctx =
+ container_of(rcdev, struct mchp_reset_context, rcdev);
+ u32 val;
+
+ /* Make sure the core is PROTECTED from reset */
+ regmap_update_bits(ctx->cpu_ctrl, PROTECT_REG, PROTECT_BIT,
PROTECT_BIT);
+
+ /* Start soft reset */
+ regmap_write(ctx->gcb_ctrl, SOFT_RESET_REG, SOFT_RESET_BIT);
+
+ /* Wait for soft reset done */
+ return regmap_read_poll_timeout(ctx->gcb_ctrl, SOFT_RESET_REG, val,
+ (val & SOFT_RESET_BIT) == 0,
+ 1, 100);
+}
+
+static const struct reset_control_ops sparx5_reset_ops = {
+ .reset = sparx5_switch_reset,
+};
+
+static int mchp_sparx5_map_io(struct platform_device *pdev, char *name,
+ struct regmap **target)
+{
+ struct resource *res;
+ void __iomem *mem;
+ struct regmap *map;
+
+ res = platform_get_resource_byname(pdev, IORESOURCE_MEM, name);
+ if (!res) {
+ dev_err(&pdev->dev, "No '%s' resource\n", name);
+ return -ENODEV;
+ }
+ mem = devm_ioremap(&pdev->dev, res->start, res->end - res->start + 1);
+ if (!mem) {
+ dev_err(&pdev->dev, "Could not map '%s' resource\n", name);
+ return -ENXIO;
+ }
+ sparx5_reset_regmap_config.name = res->name;
+ map = devm_regmap_init_mmio(&pdev->dev, mem,
&sparx5_reset_regmap_config);
+ if (IS_ERR(map))
+ return PTR_ERR
[PATCH v5 3/3] arm64: dts: reset: add microchip sparx5 switch reset driver
This provides reset driver support for the Microchip Sparx5 PCB134 and
PCB135 reference boards.
Signed-off-by: Steen Hegelund
---
arch/arm64/boot/dts/microchip/sparx5.dtsi | 9 ++---
1 file changed, 6 insertions(+), 3 deletions(-)
diff --git a/arch/arm64/boot/dts/microchip/sparx5.dtsi
b/arch/arm64/boot/dts/microchip/sparx5.dtsi
index 380281f312d8..06ecaa9ac8aa 100644
--- a/arch/arm64/boot/dts/microchip/sparx5.dtsi
+++ b/arch/arm64/boot/dts/microchip/sparx5.dtsi
@@ -132,9 +132,12 @@ mux: mux-controller {
};
};
- reset@611010008 {
- compatible = "microchip,sparx5-chip-reset";
- reg = <0x6 0x11010008 0x4>;
+ reset: reset-controller@0 {
+ compatible = "microchip,sparx5-switch-reset";
+ reg = <0x6 0x 0xd0>,
+ <0x6 0x1101 0x1>;
+ reg-names = "cpu", "gcb";
+ #reset-cells = <1>;
};
uart0: serial@60010 {
--
2.30.0
[PATCH v5 1/3] dt-bindings: reset: microchip sparx5 reset driver bindings
Document the Sparx5 reset device driver bindings
The driver uses two IO ranges on sparx5 for access to
the reset control and the reset status.
Signed-off-by: Steen Hegelund
---
.../bindings/reset/microchip,rst.yaml | 55 +++
1 file changed, 55 insertions(+)
create mode 100644 Documentation/devicetree/bindings/reset/microchip,rst.yaml
diff --git a/Documentation/devicetree/bindings/reset/microchip,rst.yaml
b/Documentation/devicetree/bindings/reset/microchip,rst.yaml
new file mode 100644
index ..80046172c9f8
--- /dev/null
+++ b/Documentation/devicetree/bindings/reset/microchip,rst.yaml
@@ -0,0 +1,55 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: "http://devicetree.org/schemas/reset/microchip,rst.yaml#";
+$schema: "http://devicetree.org/meta-schemas/core.yaml#";
+
+title: Microchip Sparx5 Switch Reset Controller
+
+maintainers:
+ - Steen Hegelund
+ - Lars Povlsen
+
+description: |
+ The Microchip Sparx5 Switch provides reset control and implements the
following
+ functions
+- One Time Switch Core Reset (Soft Reset)
+
+properties:
+ $nodename:
+pattern: "^reset-controller@[0-9a-f]+$"
+
+ compatible:
+const: microchip,sparx5-switch-reset
+
+ reg:
+items:
+ - description: cpu block registers
+ - description: global control block registers
+
+ reg-names:
+items:
+ - const: cpu
+ - const: gcb
+
+ "#reset-cells":
+const: 1
+
+required:
+ - compatible
+ - reg
+ - reg-names
+ - "#reset-cells"
+
+additionalProperties: false
+
+examples:
+ - |
+reset: reset-controller@0 {
+compatible = "microchip,sparx5-switch-reset";
+#reset-cells = <1>;
+reg = <0x0 0xd0>,
+ <0x1101 0x1>;
+reg-names = "cpu", "gcb";
+};
+
--
2.30.0
Re: [PATCH v14 2/4] phy: Add media type and speed serdes configuration interfaces
Hi Kishon, On Tue, 2021-02-16 at 15:54 +0530, Kishon Vijay Abraham I wrote: > EXTERNAL EMAIL: Do not click links or open attachments unless you > know the content is safe > > Hi, > > On 16/02/21 2:07 pm, Steen Hegelund wrote: > > Hi Andrew and Kishon, > > > > On Mon, 2021-02-15 at 15:07 +0100, Andrew Lunn wrote: > > > EXTERNAL EMAIL: Do not click links or open attachments unless you > > > know the content is safe > > > > > > On Mon, Feb 15, 2021 at 05:25:10PM +0530, Kishon Vijay Abraham I > > > wrote: > > > > Okay. Is it going to be some sort of manual negotiation where > > > > the > > > > Ethernet controller invokes set_speed with different speeds? Or > > > > the > > > > Ethernet controller will get the speed using some out of band > > > > mechanism > > > > and invokes set_speed once with the actual speed? > > > > > > Hi Kishon > > > > > > There are a few different mechanism possible. > > > > > > The SFP has an EEPROM which contains lots of parameters. One is > > > the > > > maximum baud rate the module supports. PHYLINK will combine this > > > information with the MAC capabilities to determine the default > > > speed. > > > > > > The users can select the mode the MAC works in, e.g. 1000BaseX vs > > > 2500BaseX, via ethtool -s. Different modes needs different > > > speeds. > > > > > > Some copper PHYs will change there host side interface baud rate > > > when > > > the media side interface changes mode. 10GBASE-X for 10G copper, > > > 5GBase-X for 5G COPPER, 2500Base-X for 2.5G copper, and SGMII for > > > old school 10/100/1G Ethernet. > > > > > > Mainline Linux has no support for it, but some 'vendor crap' will > > > do > > > a > > > manual negotiation, simply trying different speeds and see if the > > > SERDES establishes link. There is nothing standardised for this, > > > as > > > far as i know. > > > > > > Andrew > > > > Yes, in case I mention the only way to ensure communication is > > human > > intervention to set the speed to the highest common denominator. > > Okay.. is it the same case for set_media as well? Yes, but in the media type case, we should be able to get the type from the DAC cable EPPROM information as mentioned by Andrew, so human intervention should not be needed. > > Thanks > Kishon Thanks for your comments. -- BR Steen -=-=-=-=-=-=-=-=-=-=-=-=-=-= steen.hegel...@microchip.com
[PATCH v15 0/4] Adding the Sparx5 Serdes driver
et SerDes configuration structure and its header file. Implementation changes: - Implemented the new media and speed interfaces in the Serdes driver - Removed the configure interface function in the SerDes driver - The existing configuration function is now only used internally v11 -> v12: Used bitfields for bools in configuration structures. Removed vertical alignment in structures. Removed CONFIG_DEBUG_KERNEL guard around warning checks v10 -> v11: Rebased on v5.11-rc1 v9 -> v10: Only add the new folder to the phy Kconfig (no sort fix) Corrected the serdes mode conversion for 2.5G mode. Clarified the SGMII and 1000BASEX conversion. Improved some of the more cryptic error messages. Expanded the validate function a bit, and removed the link status from the return value. v8 -> v9: Replace pr_err with dev_err Expanded the description here in the cover letter (should probably og into the driver, at least part of it). v7 -> v8: Provide the IO targets as offsets from the start of the IO range Initialise resource index v6 -> v7: This series changes the way the IO targets are provided to the driver. Now only one IO range is available in the DT, and the driver has a table to map its targets (as their order is still not sequential), thus reducing the DT needed information and binding requirements. The register access macros have been converted to functions. - Bindings: - reg prop: minItems set to 1 - reg-names prop: removed - Driver - Use one IO range and map targets via this. - Change register access macros to use functions. - Provided a new header files with reg access functions. - Device tree - Provide only one IO range v5 -> v6: Series error: This had the same content as v5 v4 -> v5: - Bindings: - Removed .yaml from compatible string - reg prop: removed description and added minItems - reg-names prop: removed description and added const name list and minItems - #phy-cells prop: removed description and added maxItems - Configuration interface - Removed include of linux/phy.h - Added include of linux/types.h - Driver - Added include of linux/phy.h v3 -> v4: - Add a reg-names item to the binding description - Add a clocks item to the binding description - Removed the clock parameter from the configuration interface - Use the clock dt node to get the coreclock, and using that when doing the actual serdes configuration - Added a clocks entry with a system clock reference to the serdes node in the device tree v2 -> v3: - Sorted the Kconfig sourced folders - Sorted the Makefile included folders - Changed the configuration interface documentation to use kernel style v1 -> v2: Fixed kernel test robot warnings - Made these structures static: - media_presets_25g - mode_presets_25g - media_presets_10g - mode_presets_10g - Removed these duplicate initializations: - sparx5_sd25g28_params.cfg_rx_reserve_15_8 - sparx5_sd25g28_params.cfg_pi_en - sparx5_sd25g28_params.cfg_cdrck_en - sparx5_sd10g28_params.cfg_cdrck_en Steen Hegelund (4): dt-bindings: phy: Add sparx5-serdes bindings phy: Add media type and speed serdes configuration interfaces phy: Add Sparx5 ethernet serdes PHY driver arm64: dts: sparx5: Add Sparx5 serdes driver node .../bindings/phy/microchip,sparx5-serdes.yaml | 100 + arch/arm64/boot/dts/microchip/sparx5.dtsi |8 + drivers/phy/Kconfig |1 + drivers/phy/Makefile |1 + drivers/phy/microchip/Kconfig | 12 + drivers/phy/microchip/Makefile|6 + drivers/phy/microchip/sparx5_serdes.c | 2480 +++ drivers/phy/microchip/sparx5_serdes.h | 136 + drivers/phy/microchip/sparx5_serdes_regs.h| 2695 + drivers/phy/phy-core.c| 30 + include/linux/phy/phy.h | 26 + 11 files changed, 5495 insertions(+) create mode 100644 Documentation/devicetree/bindings/phy/microchip,sparx5-serdes.yaml create mode 100644 drivers/phy/microchip/Kconfig create mode 100644 drivers/phy/microchip/Makefile create mode 100644 drivers/phy/microchip/sparx5_serdes.c create mode 100644 drivers/phy/microchip/sparx5_serdes.h create mode 100644 drivers/phy/microchip/sparx5_serdes_regs.h -- 2.30.0
[PATCH v15 2/4] phy: Add media type and speed serdes configuration interfaces
Provide new phy configuration interfaces for media type and speed that
allows e.g. PHYs used for ethernet to be configured with this
information.
Signed-off-by: Lars Povlsen
Signed-off-by: Steen Hegelund
Reviewed-by: Andrew Lunn
Reviewed-by: Alexandre Belloni
---
drivers/phy/phy-core.c | 30 ++
include/linux/phy/phy.h | 26 ++
2 files changed, 56 insertions(+)
diff --git a/drivers/phy/phy-core.c b/drivers/phy/phy-core.c
index 71cb10826326..ccb575b13777 100644
--- a/drivers/phy/phy-core.c
+++ b/drivers/phy/phy-core.c
@@ -373,6 +373,36 @@ int phy_set_mode_ext(struct phy *phy, enum phy_mode mode,
int submode)
}
EXPORT_SYMBOL_GPL(phy_set_mode_ext);
+int phy_set_media(struct phy *phy, enum phy_media media)
+{
+ int ret;
+
+ if (!phy || !phy->ops->set_media)
+ return 0;
+
+ mutex_lock(&phy->mutex);
+ ret = phy->ops->set_media(phy, media);
+ mutex_unlock(&phy->mutex);
+
+ return ret;
+}
+EXPORT_SYMBOL_GPL(phy_set_media);
+
+int phy_set_speed(struct phy *phy, int speed)
+{
+ int ret;
+
+ if (!phy || !phy->ops->set_speed)
+ return 0;
+
+ mutex_lock(&phy->mutex);
+ ret = phy->ops->set_speed(phy, speed);
+ mutex_unlock(&phy->mutex);
+
+ return ret;
+}
+EXPORT_SYMBOL_GPL(phy_set_speed);
+
int phy_reset(struct phy *phy)
{
int ret;
diff --git a/include/linux/phy/phy.h b/include/linux/phy/phy.h
index e435bdb0bab3..0ed434d02196 100644
--- a/include/linux/phy/phy.h
+++ b/include/linux/phy/phy.h
@@ -44,6 +44,12 @@ enum phy_mode {
PHY_MODE_DP
};
+enum phy_media {
+ PHY_MEDIA_DEFAULT,
+ PHY_MEDIA_SR,
+ PHY_MEDIA_DAC,
+};
+
/**
* union phy_configure_opts - Opaque generic phy configuration
*
@@ -64,6 +70,8 @@ union phy_configure_opts {
* @power_on: powering on the phy
* @power_off: powering off the phy
* @set_mode: set the mode of the phy
+ * @set_media: set the media type of the phy (optional)
+ * @set_speed: set the speed of the phy (optional)
* @reset: resetting the phy
* @calibrate: calibrate the phy
* @release: ops to be performed while the consumer relinquishes the PHY
@@ -75,6 +83,8 @@ struct phy_ops {
int (*power_on)(struct phy *phy);
int (*power_off)(struct phy *phy);
int (*set_mode)(struct phy *phy, enum phy_mode mode, int submode);
+ int (*set_media)(struct phy *phy, enum phy_media media);
+ int (*set_speed)(struct phy *phy, int speed);
/**
* @configure:
@@ -215,6 +225,8 @@ int phy_power_off(struct phy *phy);
int phy_set_mode_ext(struct phy *phy, enum phy_mode mode, int submode);
#define phy_set_mode(phy, mode) \
phy_set_mode_ext(phy, mode, 0)
+int phy_set_media(struct phy *phy, enum phy_media media);
+int phy_set_speed(struct phy *phy, int speed);
int phy_configure(struct phy *phy, union phy_configure_opts *opts);
int phy_validate(struct phy *phy, enum phy_mode mode, int submode,
union phy_configure_opts *opts);
@@ -344,6 +356,20 @@ static inline int phy_set_mode_ext(struct phy *phy, enum
phy_mode mode,
#define phy_set_mode(phy, mode) \
phy_set_mode_ext(phy, mode, 0)
+static inline int phy_set_media(struct phy *phy, enum phy_media media)
+{
+ if (!phy)
+ return 0;
+ return -ENODEV;
+}
+
+static inline int phy_set_speed(struct phy *phy, int speed)
+{
+ if (!phy)
+ return 0;
+ return -ENODEV;
+}
+
static inline enum phy_mode phy_get_mode(struct phy *phy)
{
return PHY_MODE_INVALID;
--
2.30.0
[PATCH v15 1/4] dt-bindings: phy: Add sparx5-serdes bindings
Document the Sparx5 ethernet serdes phy driver bindings.
Signed-off-by: Lars Povlsen
Signed-off-by: Steen Hegelund
Reviewed-by: Rob Herring
Reviewed-by: Andrew Lunn
Reviewed-by: Alexandre Belloni
---
.../bindings/phy/microchip,sparx5-serdes.yaml | 100 ++
1 file changed, 100 insertions(+)
create mode 100644
Documentation/devicetree/bindings/phy/microchip,sparx5-serdes.yaml
diff --git a/Documentation/devicetree/bindings/phy/microchip,sparx5-serdes.yaml
b/Documentation/devicetree/bindings/phy/microchip,sparx5-serdes.yaml
new file mode 100644
index ..bdbdb3bbddbe
--- /dev/null
+++ b/Documentation/devicetree/bindings/phy/microchip,sparx5-serdes.yaml
@@ -0,0 +1,100 @@
+# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/phy/microchip,sparx5-serdes.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Microchip Sparx5 Serdes controller
+
+maintainers:
+ - Steen Hegelund
+
+description: |
+ The Sparx5 SERDES interfaces share the same basic functionality, but
+ support different operating modes and line rates.
+
+ The following list lists the SERDES features:
+
+ * RX Adaptive Decision Feedback Equalizer (DFE)
+ * Programmable continuous time linear equalizer (CTLE)
+ * Rx variable gain control
+ * Rx built-in fault detector (loss-of-lock/loss-of-signal)
+ * Adjustable tx de-emphasis (FFE)
+ * Tx output amplitude control
+ * Supports rx eye monitor
+ * Multiple loopback modes
+ * Prbs generator and checker
+ * Polarity inversion control
+
+ SERDES6G:
+
+ The SERDES6G is a high-speed SERDES interface, which can operate at
+ the following data rates:
+
+ * 100 Mbps (100BASE-FX)
+ * 1.25 Gbps (SGMII/1000BASE-X/1000BASE-KX)
+ * 3.125 Gbps (2.5GBASE-X/2.5GBASE-KX)
+ * 5.15625 Gbps (5GBASE-KR/5G-USXGMII)
+
+ SERDES10G
+
+ The SERDES10G is a high-speed SERDES interface, which can operate at
+ the following data rates:
+
+ * 100 Mbps (100BASE-FX)
+ * 1.25 Gbps (SGMII/1000BASE-X/1000BASE-KX)
+ * 3.125 Gbps (2.5GBASE-X/2.5GBASE-KX)
+ * 5 Gbps (QSGMII/USGMII)
+ * 5.15625 Gbps (5GBASE-KR/5G-USXGMII)
+ * 10 Gbps (10G-USGMII)
+ * 10.3125 Gbps (10GBASE-R/10GBASE-KR/USXGMII)
+
+ SERDES25G
+
+ The SERDES25G is a high-speed SERDES interface, which can operate at
+ the following data rates:
+
+ * 1.25 Gbps (SGMII/1000BASE-X/1000BASE-KX)
+ * 3.125 Gbps (2.5GBASE-X/2.5GBASE-KX)
+ * 5 Gbps (QSGMII/USGMII)
+ * 5.15625 Gbps (5GBASE-KR/5G-USXGMII)
+ * 10 Gbps (10G-USGMII)
+ * 10.3125 Gbps (10GBASE-R/10GBASE-KR/USXGMII)
+ * 25.78125 Gbps (25GBASE-KR/25GBASE-CR/25GBASE-SR/25GBASE-LR/25GBASE-ER)
+
+properties:
+ $nodename:
+pattern: "^serdes@[0-9a-f]+$"
+
+ compatible:
+const: microchip,sparx5-serdes
+
+ reg:
+minItems: 1
+
+ '#phy-cells':
+const: 1
+description: |
+ - The main serdes input port
+
+ clocks:
+maxItems: 1
+
+required:
+ - compatible
+ - reg
+ - '#phy-cells'
+ - clocks
+
+additionalProperties: false
+
+examples:
+ - |
+serdes: serdes@10808000 {
+ compatible = "microchip,sparx5-serdes";
+ #phy-cells = <1>;
+ clocks = <&sys_clk>;
+ reg = <0x10808000 0x5d>;
+};
+
+...
--
2.30.0
[PATCH v15 4/4] arm64: dts: sparx5: Add Sparx5 serdes driver node
Add Sparx5 serdes driver node, and enable it generally for all
reference boards.
Signed-off-by: Lars Povlsen
Signed-off-by: Steen Hegelund
Reviewed-by: Andrew Lunn
Reviewed-by: Alexandre Belloni
---
arch/arm64/boot/dts/microchip/sparx5.dtsi | 8
1 file changed, 8 insertions(+)
diff --git a/arch/arm64/boot/dts/microchip/sparx5.dtsi
b/arch/arm64/boot/dts/microchip/sparx5.dtsi
index 380281f312d8..29c606194bc7 100644
--- a/arch/arm64/boot/dts/microchip/sparx5.dtsi
+++ b/arch/arm64/boot/dts/microchip/sparx5.dtsi
@@ -383,5 +383,13 @@ tmon0: tmon@610508110 {
#thermal-sensor-cells = <0>;
clocks = <&ahb_clk>;
};
+
+ serdes: serdes@10808000 {
+ compatible = "microchip,sparx5-serdes";
+ #phy-cells = <1>;
+ clocks = <&sys_clk>;
+ reg = <0x6 0x10808000 0x5d>;
+ };
+
};
};
--
2.30.0
Re: [PATCH v4 0/3] Adding the Sparx5 Switch Reset Driver
Hi Philipp, I just wanted to know if there are any outstanding items that you would like me to handle, or you think that the driver is acceptable as it is now? BR Steen On Wed, 2021-01-20 at 09:19 +0100, Steen Hegelund wrote: > This series provides the Microchip Sparx5 Switch Reset Driver > > The Sparx5 Switch SoC has a number of components that can be reset > individually, but at least the Switch Core needs to be in a well > defined > state at power on, when any of the Sparx5 drivers starts to access > the > Switch Core, this reset driver is available. > > The reset driver is loaded early via the postcore_initcall interface, > and > will then be available for the other Sparx5 drivers (SGPIO, SwitchDev > etc) > that are loaded next, and the first of them to be loaded can perform > the > one-time Switch Core reset that is needed. > > The driver has protection so that the system busses, DDR controller, > PCI-E > and ARM A53 CPU and a few other subsystems are not touched by the > reset. > > The Sparx5 Chip Register Model can be browsed at this location: > https://github.com/microchip-ung/sparx-5_reginfo > > History: > > v3 -> v4 Added commit message descriptions > > v2 -> v3 Removed unused headers > Renamed the reset controller dev member. > Use regmap_read_poll_timeout instead of polling a function. > Used two separate syscon entries in the binding > Simplified the syscon error handling. > Simplified the devm_reset_controller_register error > handling. > Moved the contents of the mchp_sparx5_reset_config function > into > the probe function. > > v1 -> v2 Removed debug prints > Changed the error handling to save the error code before > jumping. > > Steen Hegelund (3): > dt-bindings: reset: microchip sparx5 reset driver bindings > reset: mchp: sparx5: add switch reset driver > arm64: dts: reset: add microchip sparx5 switch reset driver > > .../bindings/reset/microchip,rst.yaml | 59 + > arch/arm64/boot/dts/microchip/sparx5.dtsi | 14 +- > drivers/reset/Kconfig | 8 ++ > drivers/reset/Makefile | 1 + > drivers/reset/reset-microchip-sparx5.c | 120 > ++ > 5 files changed, 199 insertions(+), 3 deletions(-) > create mode 100644 > Documentation/devicetree/bindings/reset/microchip,rst.yaml > create mode 100644 drivers/reset/reset-microchip-sparx5.c >
[PATCH v6 0/3] Adding the Sparx5 Switch Reset Driver
This series provides the Microchip Sparx5 Switch Reset Driver The Sparx5 Switch SoC has a number of components that can be reset individually, but at least the Switch Core needs to be in a well defined state at power on, when any of the Sparx5 drivers starts to access the Switch Core, this reset driver is available. The reset driver is loaded early via the postcore_initcall interface, and will then be available for the other Sparx5 drivers (SGPIO, SwitchDev etc) that are loaded next, and the first of them to be loaded can perform the one-time Switch Core reset that is needed. The driver has protection so that the system busses, DDR controller, PCI-E and ARM A53 CPU and a few other subsystems are not touched by the reset. The Sparx5 Chip Register Model can be browsed at this location: https://github.com/microchip-ung/sparx-5_reginfo History: v5 -> v6 Using the existing CPU syscon for reset protection and add a small IO range for the GCB Reset Register. v4 -> v5 Changed the two syscons into IO ranges and updated the bindings to reflect this change. v3 -> v4 Added commit message descriptions v2 -> v3 Removed unused headers Renamed the reset controller dev member. Use regmap_read_poll_timeout instead of polling a function. Used two separate syscon entries in the binding Simplified the syscon error handling. Simplified the devm_reset_controller_register error handling. Moved the contents of the mchp_sparx5_reset_config function into the probe function. v1 -> v2 Removed debug prints Changed the error handling to save the error code before jumping. Steen Hegelund (3): dt-bindings: reset: microchip sparx5 reset driver bindings reset: mchp: sparx5: add switch reset driver arm64: dts: reset: add microchip sparx5 switch reset driver .../bindings/reset/microchip,rst.yaml | 58 +++ arch/arm64/boot/dts/microchip/sparx5.dtsi | 7 +- drivers/reset/Kconfig | 8 + drivers/reset/Makefile| 1 + drivers/reset/reset-microchip-sparx5.c| 151 ++ 5 files changed, 223 insertions(+), 2 deletions(-) create mode 100644 Documentation/devicetree/bindings/reset/microchip,rst.yaml create mode 100644 drivers/reset/reset-microchip-sparx5.c -- 2.30.0
[PATCH v6 1/3] dt-bindings: reset: microchip sparx5 reset driver bindings
Document the Sparx5 reset device driver bindings
The driver uses a syscon and an IO range on sparx5 for access to
the reset control and the reset status.
Signed-off-by: Steen Hegelund
---
.../bindings/reset/microchip,rst.yaml | 58 +++
1 file changed, 58 insertions(+)
create mode 100644 Documentation/devicetree/bindings/reset/microchip,rst.yaml
diff --git a/Documentation/devicetree/bindings/reset/microchip,rst.yaml
b/Documentation/devicetree/bindings/reset/microchip,rst.yaml
new file mode 100644
index ..370579aeeca1
--- /dev/null
+++ b/Documentation/devicetree/bindings/reset/microchip,rst.yaml
@@ -0,0 +1,58 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: "http://devicetree.org/schemas/reset/microchip,rst.yaml#";
+$schema: "http://devicetree.org/meta-schemas/core.yaml#";
+
+title: Microchip Sparx5 Switch Reset Controller
+
+maintainers:
+ - Steen Hegelund
+ - Lars Povlsen
+
+description: |
+ The Microchip Sparx5 Switch provides reset control and implements the
following
+ functions
+- One Time Switch Core Reset (Soft Reset)
+
+properties:
+ $nodename:
+pattern: "^reset-controller@[0-9a-f]+$"
+
+ compatible:
+const: microchip,sparx5-switch-reset
+
+ reg:
+items:
+ - description: global control block registers
+
+ reg-names:
+items:
+ - const: gcb
+
+ "#reset-cells":
+const: 1
+
+ cpu-syscon:
+$ref: "/schemas/types.yaml#/definitions/phandle"
+description: syscon used to access CPU reset
+
+required:
+ - compatible
+ - reg
+ - reg-names
+ - "#reset-cells"
+ - cpu-syscon
+
+additionalProperties: false
+
+examples:
+ - |
+reset: reset-controller@11010008 {
+compatible = "microchip,sparx5-switch-reset";
+reg = <0x11010008 0x4>;
+reg-names = "gcb";
+#reset-cells = <1>;
+cpu-syscon = <&cpu_ctrl>;
+};
+
--
2.30.0
[PATCH v6 3/3] arm64: dts: reset: add microchip sparx5 switch reset driver
This provides reset driver support for the Microchip Sparx5 PCB134 and
PCB135 reference boards.
Signed-off-by: Steen Hegelund
---
arch/arm64/boot/dts/microchip/sparx5.dtsi | 7 +--
1 file changed, 5 insertions(+), 2 deletions(-)
diff --git a/arch/arm64/boot/dts/microchip/sparx5.dtsi
b/arch/arm64/boot/dts/microchip/sparx5.dtsi
index 380281f312d8..dc3ada5cf9fc 100644
--- a/arch/arm64/boot/dts/microchip/sparx5.dtsi
+++ b/arch/arm64/boot/dts/microchip/sparx5.dtsi
@@ -132,9 +132,12 @@ mux: mux-controller {
};
};
- reset@611010008 {
- compatible = "microchip,sparx5-chip-reset";
+ reset: reset-controller@611010008 {
+ compatible = "microchip,sparx5-switch-reset";
reg = <0x6 0x11010008 0x4>;
+ reg-names = "gcb";
+ #reset-cells = <1>;
+ cpu-syscon = <&cpu_ctrl>;
};
uart0: serial@60010 {
--
2.30.0
[PATCH v6 2/3] reset: mchp: sparx5: add switch reset driver
The Sparx5 Switch SoC has a number of components that can be reset
indiviually, but at least the Switch Core needs to be in a well defined
state at power on, when any of the Sparx5 drivers starts to access the
Switch Core, this reset driver is available.
The reset driver is loaded early via the postcore_initcall interface, and
will then be available for the other Sparx5 drivers (SGPIO, SwitchDev etc)
that are loaded next, and the first of them to be loaded can perform the
one-time Switch Core reset that is needed.
The driver has protection so that the system busses, DDR controller, PCI-E
and ARM A53 CPU and a few other subsystems are not touched by the reset.
Signed-off-by: Steen Hegelund
---
drivers/reset/Kconfig | 8 ++
drivers/reset/Makefile | 1 +
drivers/reset/reset-microchip-sparx5.c | 151 +
3 files changed, 160 insertions(+)
create mode 100644 drivers/reset/reset-microchip-sparx5.c
diff --git a/drivers/reset/Kconfig b/drivers/reset/Kconfig
index 71ab75a46491..05c240c47a8a 100644
--- a/drivers/reset/Kconfig
+++ b/drivers/reset/Kconfig
@@ -101,6 +101,14 @@ config RESET_LPC18XX
help
This enables the reset controller driver for NXP LPC18xx/43xx SoCs.
+config RESET_MCHP_SPARX5
+ bool "Microchip Sparx5 reset driver"
+ depends on HAS_IOMEM || COMPILE_TEST
+ default y if SPARX5_SWITCH
+ select MFD_SYSCON
+ help
+ This driver supports switch core reset for the Microchip Sparx5 SoC.
+
config RESET_MESON
tristate "Meson Reset Driver"
depends on ARCH_MESON || COMPILE_TEST
diff --git a/drivers/reset/Makefile b/drivers/reset/Makefile
index 1054123fd187..341fd9ab4bf6 100644
--- a/drivers/reset/Makefile
+++ b/drivers/reset/Makefile
@@ -15,6 +15,7 @@ obj-$(CONFIG_RESET_IMX7) += reset-imx7.o
obj-$(CONFIG_RESET_INTEL_GW) += reset-intel-gw.o
obj-$(CONFIG_RESET_LANTIQ) += reset-lantiq.o
obj-$(CONFIG_RESET_LPC18XX) += reset-lpc18xx.o
+obj-$(CONFIG_RESET_MCHP_SPARX5) += reset-microchip-sparx5.o
obj-$(CONFIG_RESET_MESON) += reset-meson.o
obj-$(CONFIG_RESET_MESON_AUDIO_ARB) += reset-meson-audio-arb.o
obj-$(CONFIG_RESET_NPCM) += reset-npcm.o
diff --git a/drivers/reset/reset-microchip-sparx5.c
b/drivers/reset/reset-microchip-sparx5.c
new file mode 100644
index ..36f00ef68f0d
--- /dev/null
+++ b/drivers/reset/reset-microchip-sparx5.c
@@ -0,0 +1,151 @@
+// SPDX-License-Identifier: GPL-2.0+
+/* Microchip Sparx5 Switch Reset driver
+ *
+ * Copyright (c) 2020 Microchip Technology Inc. and its subsidiaries.
+ *
+ * The Sparx5 Chip Register Model can be browsed at this location:
+ * https://github.com/microchip-ung/sparx-5_reginfo
+ */
+#include
+#include
+#include
+#include
+#include
+#include
+
+#define PROTECT_REG0x84
+#define PROTECT_BITBIT(10)
+#define SOFT_RESET_REG 0x00
+#define SOFT_RESET_BIT BIT(1)
+
+struct mchp_reset_context {
+ struct regmap *cpu_ctrl;
+ struct regmap *gcb_ctrl;
+ struct reset_controller_dev rcdev;
+};
+
+static struct regmap_config sparx5_reset_regmap_config = {
+ .reg_bits = 32,
+ .val_bits = 32,
+ .reg_stride = 4,
+};
+
+static int sparx5_switch_reset(struct reset_controller_dev *rcdev,
+ unsigned long id)
+{
+ struct mchp_reset_context *ctx =
+ container_of(rcdev, struct mchp_reset_context, rcdev);
+ u32 val;
+
+ /* Make sure the core is PROTECTED from reset */
+ regmap_update_bits(ctx->cpu_ctrl, PROTECT_REG, PROTECT_BIT,
PROTECT_BIT);
+
+ /* Start soft reset */
+ regmap_write(ctx->gcb_ctrl, SOFT_RESET_REG, SOFT_RESET_BIT);
+
+ /* Wait for soft reset done */
+ return regmap_read_poll_timeout(ctx->gcb_ctrl, SOFT_RESET_REG, val,
+ (val & SOFT_RESET_BIT) == 0,
+ 1, 100);
+}
+
+static const struct reset_control_ops sparx5_reset_ops = {
+ .reset = sparx5_switch_reset,
+};
+
+static int mchp_sparx5_map_syscon(struct platform_device *pdev, char *name,
+ struct regmap **target)
+{
+ struct device_node *syscon_np;
+ struct regmap *regmap;
+ int err;
+
+ syscon_np = of_parse_phandle(pdev->dev.of_node, name, 0);
+ if (!syscon_np)
+ return -ENODEV;
+ regmap = syscon_node_to_regmap(syscon_np);
+ of_node_put(syscon_np);
+ if (IS_ERR(regmap)) {
+ err = PTR_ERR(regmap);
+ dev_err(&pdev->dev, "No '%s' map: %d\n", name, err);
+ return err;
+ }
+ *target = regmap;
+ return 0;
+}
+
+static int mchp_sparx5_map_io(struct platform_device *pdev, char *name,
+ struct regmap **target)
+{
+ struct resource *res;
+ struct regmap *map;
+ void __iomem *mem;
+
+
Re: [PATCH v6 2/3] reset: mchp: sparx5: add switch reset driver
Hi Alex,
On Thu, 2021-02-25 at 21:40 +0100, Alexandre Belloni wrote:
> EXTERNAL EMAIL: Do not click links or open attachments unless you
> know the content is safe
>
> Hello,
>
> >
...
> > +static int mchp_sparx5_map_io(struct platform_device *pdev, char
> > *name,
> > + struct regmap **target)
> > +{
> > + struct resource *res;
> > + struct regmap *map;
> > + void __iomem *mem;
> > +
> > + res = platform_get_resource_byname(pdev, IORESOURCE_MEM,
> > name);
> > + if (!res) {
> > + dev_err(&pdev->dev, "No '%s' resource\n", name);
> > + return -ENODEV;
> > + }
> > + mem = devm_ioremap(&pdev->dev, res->start, res->end - res-
> > >start + 1);
> > + if (!mem) {
> > + dev_err(&pdev->dev, "Could not map '%s' resource\n",
> > name);
> > + return -ENXIO;
> > + }
>
> Someone is going to tell you to use
> devm_platform_get_and_ioremap_resource so it may as well be me ;)
Very nice.
Thanks for the info. I will use that instead.
>
> --
> Alexandre Belloni, co-owner and COO, Bootlin
> Embedded Linux and Kernel engineering
> https://bootlin.com
--
BR
Steen
-=-=-=-=-=-=-=-=-=-=-=-=-=-=
steen.hegel...@microchip.com
[PATCH v10 0/4] Adding the Sparx5 Serdes driver
requirements. The register access macros have been converted to functions. - Bindings: - reg prop: minItems set to 1 - reg-names prop: removed - Driver - Use one IO range and map targets via this. - Change register access macros to use functions. - Provided a new header files with reg access functions. - Device tree - Provide only one IO range v5 -> v6: Series error: This had the same content as v5 v4 -> v5: - Bindings: - Removed .yaml from compatible string - reg prop: removed description and added minItems - reg-names prop: removed description and added const name list and minItems - #phy-cells prop: removed description and added maxItems - Configuration interface - Removed include of linux/phy.h - Added include of linux/types.h - Driver - Added include of linux/phy.h v3 -> v4: - Add a reg-names item to the binding description - Add a clocks item to the binding description - Removed the clock parameter from the configuration interface - Use the clock dt node to get the coreclock, and using that when doing the actual serdes configuration - Added a clocks entry with a system clock reference to the serdes node in the device tree v2 -> v3: - Sorted the Kconfig sourced folders - Sorted the Makefile included folders - Changed the configuration interface documentation to use kernel style v1 -> v2: Fixed kernel test robot warnings - Made these structures static: - media_presets_25g - mode_presets_25g - media_presets_10g - mode_presets_10g - Removed these duplicate initializations: - sparx5_sd25g28_params.cfg_rx_reserve_15_8 - sparx5_sd25g28_params.cfg_pi_en - sparx5_sd25g28_params.cfg_cdrck_en - sparx5_sd10g28_params.cfg_cdrck_en Lars Povlsen (2): dt-bindings: phy: Add sparx5-serdes bindings arm64: dts: sparx5: Add Sparx5 serdes driver node Steen Hegelund (2): phy: Add ethernet serdes configuration option phy: Add Sparx5 ethernet serdes PHY driver .../bindings/phy/microchip,sparx5-serdes.yaml | 100 + arch/arm64/boot/dts/microchip/sparx5.dtsi |8 + drivers/phy/Kconfig |1 + drivers/phy/Makefile |1 + drivers/phy/microchip/Kconfig | 12 + drivers/phy/microchip/Makefile|6 + drivers/phy/microchip/sparx5_serdes.c | 2443 +++ drivers/phy/microchip/sparx5_serdes.h | 129 + drivers/phy/microchip/sparx5_serdes_regs.h| 2695 + include/linux/phy/phy-ethernet-serdes.h | 30 + include/linux/phy/phy.h |4 + 11 files changed, 5429 insertions(+) create mode 100644 Documentation/devicetree/bindings/phy/microchip,sparx5-serdes.yaml create mode 100644 drivers/phy/microchip/Kconfig create mode 100644 drivers/phy/microchip/Makefile create mode 100644 drivers/phy/microchip/sparx5_serdes.c create mode 100644 drivers/phy/microchip/sparx5_serdes.h create mode 100644 drivers/phy/microchip/sparx5_serdes_regs.h create mode 100644 include/linux/phy/phy-ethernet-serdes.h -- 2.29.2
[PATCH v10 1/4] dt-bindings: phy: Add sparx5-serdes bindings
Document the Sparx5 ethernet serdes phy driver bindings.
Signed-off-by: Lars Povlsen
Signed-off-by: Steen Hegelund
Reviewed-by: Rob Herring
---
.../bindings/phy/microchip,sparx5-serdes.yaml | 100 ++
1 file changed, 100 insertions(+)
create mode 100644
Documentation/devicetree/bindings/phy/microchip,sparx5-serdes.yaml
diff --git a/Documentation/devicetree/bindings/phy/microchip,sparx5-serdes.yaml
b/Documentation/devicetree/bindings/phy/microchip,sparx5-serdes.yaml
new file mode 100644
index ..bdbdb3bbddbe
--- /dev/null
+++ b/Documentation/devicetree/bindings/phy/microchip,sparx5-serdes.yaml
@@ -0,0 +1,100 @@
+# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/phy/microchip,sparx5-serdes.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Microchip Sparx5 Serdes controller
+
+maintainers:
+ - Steen Hegelund
+
+description: |
+ The Sparx5 SERDES interfaces share the same basic functionality, but
+ support different operating modes and line rates.
+
+ The following list lists the SERDES features:
+
+ * RX Adaptive Decision Feedback Equalizer (DFE)
+ * Programmable continuous time linear equalizer (CTLE)
+ * Rx variable gain control
+ * Rx built-in fault detector (loss-of-lock/loss-of-signal)
+ * Adjustable tx de-emphasis (FFE)
+ * Tx output amplitude control
+ * Supports rx eye monitor
+ * Multiple loopback modes
+ * Prbs generator and checker
+ * Polarity inversion control
+
+ SERDES6G:
+
+ The SERDES6G is a high-speed SERDES interface, which can operate at
+ the following data rates:
+
+ * 100 Mbps (100BASE-FX)
+ * 1.25 Gbps (SGMII/1000BASE-X/1000BASE-KX)
+ * 3.125 Gbps (2.5GBASE-X/2.5GBASE-KX)
+ * 5.15625 Gbps (5GBASE-KR/5G-USXGMII)
+
+ SERDES10G
+
+ The SERDES10G is a high-speed SERDES interface, which can operate at
+ the following data rates:
+
+ * 100 Mbps (100BASE-FX)
+ * 1.25 Gbps (SGMII/1000BASE-X/1000BASE-KX)
+ * 3.125 Gbps (2.5GBASE-X/2.5GBASE-KX)
+ * 5 Gbps (QSGMII/USGMII)
+ * 5.15625 Gbps (5GBASE-KR/5G-USXGMII)
+ * 10 Gbps (10G-USGMII)
+ * 10.3125 Gbps (10GBASE-R/10GBASE-KR/USXGMII)
+
+ SERDES25G
+
+ The SERDES25G is a high-speed SERDES interface, which can operate at
+ the following data rates:
+
+ * 1.25 Gbps (SGMII/1000BASE-X/1000BASE-KX)
+ * 3.125 Gbps (2.5GBASE-X/2.5GBASE-KX)
+ * 5 Gbps (QSGMII/USGMII)
+ * 5.15625 Gbps (5GBASE-KR/5G-USXGMII)
+ * 10 Gbps (10G-USGMII)
+ * 10.3125 Gbps (10GBASE-R/10GBASE-KR/USXGMII)
+ * 25.78125 Gbps (25GBASE-KR/25GBASE-CR/25GBASE-SR/25GBASE-LR/25GBASE-ER)
+
+properties:
+ $nodename:
+pattern: "^serdes@[0-9a-f]+$"
+
+ compatible:
+const: microchip,sparx5-serdes
+
+ reg:
+minItems: 1
+
+ '#phy-cells':
+const: 1
+description: |
+ - The main serdes input port
+
+ clocks:
+maxItems: 1
+
+required:
+ - compatible
+ - reg
+ - '#phy-cells'
+ - clocks
+
+additionalProperties: false
+
+examples:
+ - |
+serdes: serdes@10808000 {
+ compatible = "microchip,sparx5-serdes";
+ #phy-cells = <1>;
+ clocks = <&sys_clk>;
+ reg = <0x10808000 0x5d>;
+};
+
+...
--
2.29.2
[PATCH v10 4/4] arm64: dts: sparx5: Add Sparx5 serdes driver node
Add Sparx5 serdes driver node, and enable it generally for all
reference boards.
Signed-off-by: Lars Povlsen
Signed-off-by: Steen Hegelund
---
arch/arm64/boot/dts/microchip/sparx5.dtsi | 8
1 file changed, 8 insertions(+)
diff --git a/arch/arm64/boot/dts/microchip/sparx5.dtsi
b/arch/arm64/boot/dts/microchip/sparx5.dtsi
index 8e7724d413fb..797601a9d542 100644
--- a/arch/arm64/boot/dts/microchip/sparx5.dtsi
+++ b/arch/arm64/boot/dts/microchip/sparx5.dtsi
@@ -287,5 +287,13 @@ tmon0: tmon@610508110 {
#thermal-sensor-cells = <0>;
clocks = <&ahb_clk>;
};
+
+ serdes: serdes@10808000 {
+ compatible = "microchip,sparx5-serdes";
+ #phy-cells = <1>;
+ clocks = <&sys_clk>;
+ reg = <0x6 0x10808000 0x5d>;
+ };
+
};
};
--
2.29.2
[PATCH v10 2/4] phy: Add ethernet serdes configuration option
Provide a new ethernet phy configuration structure, that
allow PHYs used for ethernet to be configured with
speed, media type and clock information.
Signed-off-by: Lars Povlsen
Signed-off-by: Steen Hegelund
---
include/linux/phy/phy-ethernet-serdes.h | 30 +
include/linux/phy/phy.h | 4
2 files changed, 34 insertions(+)
create mode 100644 include/linux/phy/phy-ethernet-serdes.h
diff --git a/include/linux/phy/phy-ethernet-serdes.h
b/include/linux/phy/phy-ethernet-serdes.h
new file mode 100644
index ..d2462fadf179
--- /dev/null
+++ b/include/linux/phy/phy-ethernet-serdes.h
@@ -0,0 +1,30 @@
+/* SPDX-License-Identifier: (GPL-2.0 OR MIT) */
+/*
+ * Microchip Sparx5 Ethernet SerDes driver
+ *
+ * Copyright (c) 2020 Microschip Inc
+ */
+#ifndef __PHY_ETHERNET_SERDES_H_
+#define __PHY_ETHERNET_SERDES_H_
+
+#include
+
+enum ethernet_media_type {
+ ETH_MEDIA_DEFAULT,
+ ETH_MEDIA_SR,
+ ETH_MEDIA_DAC,
+};
+
+/**
+ * struct phy_configure_opts_eth_serdes - Ethernet SerDes This structure is
used
+ * to represent the configuration state of a Ethernet Serdes PHY.
+ * @speed: Speed of the serdes interface in Mbps
+ * @media_type: Specifies which media the serdes will be using
+ */
+struct phy_configure_opts_eth_serdes {
+ u32speed;
+ enum ethernet_media_type media_type;
+};
+
+#endif
+
diff --git a/include/linux/phy/phy.h b/include/linux/phy/phy.h
index e435bdb0bab3..78ecb375cede 100644
--- a/include/linux/phy/phy.h
+++ b/include/linux/phy/phy.h
@@ -18,6 +18,7 @@
#include
#include
+#include
struct phy;
@@ -49,11 +50,14 @@ enum phy_mode {
*
* @mipi_dphy: Configuration set applicable for phys supporting
* the MIPI_DPHY phy mode.
+ * @eth_serdes: Configuration set applicable for phys supporting
+ * the ethernet serdes.
* @dp:Configuration set applicable for phys supporting
* the DisplayPort protocol.
*/
union phy_configure_opts {
struct phy_configure_opts_mipi_dphy mipi_dphy;
+ struct phy_configure_opts_eth_serdeseth_serdes;
struct phy_configure_opts_dpdp;
};
--
2.29.2
Re: [RFC PATCH v2 1/8] dt-bindings: net: sparx5: Add sparx5-switch bindings
On Sun, 2020-12-20 at 16:55 -0800, Florian Fainelli wrote: > EXTERNAL EMAIL: Do not click links or open attachments unless you > know the content is safe > > On 12/16/2020 11:51 PM, Steen Hegelund wrote: > > Document the Sparx5 switch device driver bindings > > > > Signed-off-by: Steen Hegelund > > Signed-off-by: Lars Povlsen > > --- > > [snip] > > > + max-speed: > > + maxItems: 1 > > + description: Bandwidth allocated to this port > > + > > + phys: > > + description: phandle of a Ethernet Serdes PHY > > + > > + phy-handle: > > + description: phandle of a Ethernet PHY > > + > > + phy-mode: > > + description: Interface between the serdes and the phy > > Can you specify this pertains to the Serdes and Ethernet PHY? Hi Florian, Yes: I will clarify that phy-mode is for the optional Ethernet cuPHY. Thanks for your comments Steen > -- > Florian
Re: [RFC PATCH v2 0/8] Adding the Sparx5 Switch Driver
Hi Florian, On Sun, 2020-12-20 at 16:58 -0800, Florian Fainelli wrote: > > > > The Sparx5 Switch chip register model can be browsed here: > > Link: > > https://microchip-ung.github.io/sparx-5_reginfo/reginfo_sparx-5.html > > Out of curiosity, what tool was used to generate the register > information page? It looks really neat and well organized. It is an in-house tool that is used in our so-called VML-flow (Versatile Markup Language), so it is not out in the open yet. The same model file is used internally in many ways - but exposing it to the public is something we have not tried before, and having this view is so much nicer that the usual datasheet, I find... And thanks for the kind words - I passed them on to the author. BR Steen > -- > Florian
Re: [RFC PATCH v2 1/8] dt-bindings: net: sparx5: Add sparx5-switch bindings
Hi Rob, On Mon, 2020-12-21 at 14:40 -0700, Rob Herring wrote: > EXTERNAL EMAIL: Do not click links or open attachments unless you > know the content is safe > > On Thu, Dec 17, 2020 at 08:51:27AM +0100, Steen Hegelund wrote: > > Document the Sparx5 switch device driver bindings > > > > Signed-off-by: Steen Hegelund > > Signed-off-by: Lars Povlsen > > --- > > .../bindings/net/microchip,sparx5-switch.yaml | 178 > > ++ > > 1 file changed, 178 insertions(+) > > create mode 100644 > > Documentation/devicetree/bindings/net/microchip,sparx5-switch.yaml > > > > diff --git > > a/Documentation/devicetree/bindings/net/microchip,sparx5- > > switch.yaml > > b/Documentation/devicetree/bindings/net/microchip,sparx5- > > switch.yaml > > new file mode 100644 > > index ..6e3ef8285e9a > > --- /dev/null > > +++ b/Documentation/devicetree/bindings/net/microchip,sparx5- > > switch.yaml > > @@ -0,0 +1,178 @@ > > +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause > > +%YAML 1.2 > > +--- > > +$id: > > http://devicetree.org/schemas/net/microchip,sparx5-switch.yaml# > > +$schema: http://devicetree.org/meta-schemas/core.yaml# > > + > > +title: Microchip Sparx5 Ethernet switch controller > > + > > +maintainers: > > + - Lars Povlsen > > + - Steen Hegelund > > + > > +description: | > > + The SparX-5 Enterprise Ethernet switch family provides a rich > > set of > > + Enterprise switching features such as advanced TCAM-based VLAN > > and > > + QoS processing enabling delivery of differentiated services, and > > + security through TCAM-based frame processing using versatile > > content > > + aware processor (VCAP). > > + > > + IPv4/IPv6 Layer 3 (L3) unicast and multicast routing is > > supported > > + with up to 18K IPv4/9K IPv6 unicast LPM entries and up to 9K > > IPv4/3K > > + IPv6 (S,G) multicast groups. > > + > > + L3 security features include source guard and reverse path > > + forwarding (uRPF) tasks. Additional L3 features include VRF-Lite > > and > > + IP tunnels (IP over GRE/IP). > > + > > + The SparX-5 switch family targets managed Layer 2 and Layer 3 > > + equipment in SMB, SME, and Enterprise where high port count > > + 1G/2.5G/5G/10G switching with 10G/25G aggregation links is > > required. > > + > > +properties: > > + $nodename: > > + pattern: "^switch@[0-9a-f]+$" > > + > > + compatible: > > + const: microchip,sparx5-switch > > + > > + reg: > > + minItems: 2 > > + > > + reg-names: > > + minItems: 2 > > This is the default based on 'items' length. Does that mean that I should omit minItems here? > > > + items: > > + - const: devices > > + - const: gcb > > + > > + interrupts: > > + maxItems: 1 > > + description: Interrupt used for reception of packets to the > > CPU > > + > > + ethernet-ports: > > + type: object > > + properties: > > + '#address-cells': > > + const: 1 > > + '#size-cells': > > + const: 0 > > + > > + patternProperties: > > + "^port@[0-9]+$": > > + type: object > > + description: Switch ports > > + > > + allOf: > > + - $ref: ethernet-controller.yaml# > > + > > + properties: > > + reg: > > + description: Switch port number > > + > > + max-speed: > > + maxItems: 1 > > Is that an array? No it is just a single value. > > > + description: Bandwidth allocated to this port > > + > > + phys: > > How many? (maxItems) I will add "maxItems: 1" > > > + description: phandle of a Ethernet Serdes PHY > > + > > + phy-handle: > > + description: phandle of a Ethernet PHY > > + > > + phy-mode: > > + description: Interface between the serdes and the phy > > The whole set of modes defined is supported? This driver does not impose any limits on phy-mode. It is passed on to the phy, so all modes are supported as I see it. > > > + > > + sfp: > > + description: phandle of an SFP > > + > > + managed: > > + maxItems: 1 > > An array? No just a single item. Thanks f
Re: [RFC PATCH v2 3/8] net: sparx5: add hostmode with phylink support
Hi Andrew,
On Sat, 2020-12-19 at 20:51 +0100, Andrew Lunn wrote:
> EXTERNAL EMAIL: Do not click links or open attachments unless you
> know the content is safe
>
> > + /* Create a phylink for PHY management. Also handles SFPs */
> > + spx5_port->phylink_config.dev = &spx5_port->ndev->dev;
> > + spx5_port->phylink_co
> > nfig.type = PHYLINK_NETDEV;
> > + spx5_port->phylink_config.pcs_poll = true;
> > +
> > + /* phylink needs a valid interface mode to parse dt node */
> > + if (phy_mode == PHY_INTERFACE_MODE_NA)
> > + phy_mode = PHY_INTERFACE_MODE_10GBASER;
>
> Maybe just enforce a valid value in DT?
Maybe I need to clarify that you must choose between an Ethernet cuPHY
or an SFP, so it is optional.
>
> > +/* Configuration */
> > +static inline bool sparx5_use_cu_phy(struct sparx5_port *port)
> > +{
> > + return port->conf.phy_mode != PHY_INTERFACE_MODE_NA;
> > +}
>
> That is a rather odd definition of copper.
Should I rather use a bool property to select between the two options
(cuPHY or SFP)?
>
> > diff --git a/drivers/net/ethernet/microchip/sparx5/sparx5_netdev.c
> > b/drivers/net/ethernet/microchip/sparx5/sparx5_netdev.c
> > new file mode 100644
> > index ..6f9282e9d3f4
> > --- /dev/null
> > +++ b/drivers/net/ethernet/microchip/sparx5/sparx5_netdev.c
> > @@ -0,0 +1,203 @@
> > +// SPDX-License-Identifier: GPL-2.0+
> > +/* Microchip Sparx5 Switch driver
> > + *
> > + * Copyright (c) 2020 Microchip Technology Inc. and its
> > subsidiaries.
> > + */
> > +
> > +#include "sparx5_main.h"
>
> I don't actually know what is preferred here, but very few drivers
> i've reviewed put all the required headers into another header
> file. They normally list them in each .c file.
I will look at reworking this.
>
> > +static int sparx5_port_open(struct net_device *ndev)
> > +{
> > + struct sparx5_port *port = netdev_priv(ndev);
> > + int err = 0;
> > +
> > + err = phylink_of_phy_connect(port->phylink, port->of_node,
> > 0);
> > + if (err) {
> > + netdev_err(ndev, "Could not attach to PHY\n");
> > + return err;
> > + }
> > +
> > + phylink_start(port->phylink);
> > +
> > + if (!ndev->phydev) {
>
> Humm. When is ndev->phydev set? I don't think phylink ever sets it.
Indirectly: phylink_of_phy_connect uses phy_attach_direct and that sets
the phydev.
>
> > + /* power up serdes */
> > + port->conf.power_down = false;
> > + err = phy_power_on(port->serdes);
> > + if (err)
> > + netdev_err(ndev, "%s failed\n", __func__);
> > + }
> > +
> > + return err;
> > +}
>
> > +struct net_device *sparx5_create_netdev(struct sparx5 *sparx5, u32
> > portno)
> > +{
> > + struct net_device *ndev;
> > + struct sparx5_port *spx5_port;
> > +
> > + ndev = devm_alloc_etherdev(sparx5->dev, sizeof(struct
> > sparx5_port));
> > + if (!ndev)
> > + return ERR_PTR(-ENOMEM);
> > +
> > + SET_NETDEV_DEV(ndev, sparx5->dev);
> > + spx5_port = netdev_priv(ndev);
> > + spx5_port->ndev = ndev;
> > + spx5_port->sparx5 = sparx5;
> > + spx5_port->portno = portno;
> > + sparx5_set_port_ifh(spx5_port->ifh, portno);
> > + snprintf(ndev->name, IFNAMSIZ, "eth%d", portno);
> > +
> > + ether_setup(ndev);
>
> devm_alloc_etherdev() should of already called ether_setup().
Ah - yes it is the setup(dev) call in alloc_netdev_mqs. I will remove
that then.
>
> > + ndev->netdev_ops = &sparx5_port_netdev_ops;
> > + ndev->features |= NETIF_F_LLTX; /* software tx */
> > +
> > + ether_addr_copy(ndev->dev_addr, sparx5->base_mac);
> > + ndev->dev_addr[ETH_ALEN - 1] += portno + 1;
>
> That will cause some surprises with wrap around. Use eth_addr_inc()
OK - will do.
>
> > +static void sparx5_xtr_grp(struct sparx5 *sparx5, u8 grp, bool
> > byte_swap)
> > +{
> > + int i, byte_cnt = 0;
> > + bool eof_flag = false, pruned_flag = false, abort_flag =
> > false;
> > + u32 ifh[IFH_LEN];
> > + struct sk_buff *skb;
> > + struct frame_info fi;
> > + struct sparx5_port *port;
> > + struct net_device *netdev;
> > + u32 *rxbuf;
> > +
> > + /* Get IFH */
> > + for (i = 0; i < IFH_LEN; i++)
> > + ifh[i] = spx5_rd(sparx5, QS_XTR_RD(grp));
> > +
> > + /* Decode IFH (whats needed) */
> > + sparx5_ifh_parse(ifh, &fi);
> > +
> > + /* Map to port netdev */
> > + port = fi.src_port < SPX5_PORTS ?
> > + sparx5->ports[fi.src_port] : NULL;
> > + if (!port || !port->ndev) {
> > + dev_err(sparx5->dev, "Data on inactive port %d\n",
> > fi.src_port);
> > + sparx5_xtr_flush(sparx5, grp);
> > + return;
> > + }
> > +
> > + /* Have netdev, get skb */
> > + netdev = port->ndev;
> > + skb = netdev_alloc_skb(netdev, netdev->mtu + ETH_HLEN);
> > + if (!skb) {
> > + sparx5_xtr_flush(sparx5, grp);
> > +
Re: [RFC PATCH v2 2/8] net: sparx5: add the basic sparx5 driver
Hi Andrew,
On Sat, 2020-12-19 at 20:11 +0100, Andrew Lunn wrote:
> EXTERNAL EMAIL: Do not click links or open attachments unless you
> know the content is safe
>
> On Thu, Dec 17, 2020 at 08:51:28AM +0100, Steen Hegelund wrote:
>
> > +static struct sparx5_io_resource sparx5_iomap[] = {
>
> This could be made const i think,.
Yes
>
> > + { TARGET_DEV2G5, 0, 0 }, /* 0x610004000:
> > dev2g5_0 */
> > + { TARGET_DEV5G, 0x4000, 0 }, /* 0x610008000:
> > dev5g_0 */
> > + { TARGET_PCS5G_BR, 0x8000, 0 }, /* 0x61000c000:
> > pcs5g_br_0 */
> > + { TARGET_DEV2G5 + 1, 0xc000, 0 }, /* 0x61001:
> > dev2g5_1 */
>
> > +static int sparx5_create_targets(struct sparx5 *sparx5)
> > +{
> > + int idx, jdx;
> > + struct resource *iores[IO_RANGES];
> > + void __iomem *iomem[IO_RANGES];
> > + void __iomem *begin[IO_RANGES];
> > + int range_id[IO_RANGES];
>
> Reverse Christmas tree. idx, jdx need to come last.
Yes - I will check the entire file for RCT...
>
> > +
> > + /* Check if done previously (deferred by serdes load) */
> > + if (sparx5->regs[sparx5_iomap[0].id])
> > + return 0;
>
> Could you explain this a bit more. Do you mean -EPROBE_DEFER?
Yes that was the intended usage. I will change the startup flow to try
to avoid checking this-
>
> > +static int sparx5_probe_port(struct sparx5 *sparx5,
> > + struct device_node *portnp,
> > + struct phy *serdes,
> > + u32 portno,
> > + struct sparx5_port_config *conf)
> > +{
> > + struct sparx5_port *spx5_port;
> > + struct net_device *ndev;
> > + int err;
> > +
> > + err = sparx5_create_targets(sparx5);
> > + if (err)
> > + return err;
>
> This sees odd here. Don't sparx5_create_targets() create all the
> targets, where as this creates one specific port? Seems like
> sparx5_create_targets() should be in the devices as a whole probe,
> not
> the port probe.
You are right - the name does not really fit (anymore). I will rework
this.
>
> > + spx5_port = netdev_priv(ndev);
> > + spx5_port->of_node = portnp;
> > + spx5_port->serdes = serdes;
> > + spx5_port->pvid = NULL_VID;
> > + spx5_port->signd_internal = true;
> > + spx5_port->signd_active_high = true;
> > + spx5_port->signd_enable = true;
> > + spx5_port->flow_control = false;
> > + spx5_port->max_vlan_tags = SPX5_PORT_MAX_TAGS_NONE;
> > + spx5_port->vlan_type = SPX5_VLAN_PORT_TYPE_UNAWARE;
> > + spx5_port->custom_etype = 0x8880; /* Vitesse */
> > + conf->portmode = conf->phy_mode;
> > + spx5_port->conf.speed = SPEED_UNKNOWN;
> > + spx5_port->conf.power_down = true;
> > + sparx5->ports[portno] = spx5_port;
> > + return 0;
>
> I'm also not sure this has the correct name. This does not look like
> a
> typical probe function.
Agree.
>
>
> > +}
> > +
> > +static int sparx5_init_switchcore(struct sparx5 *sparx5)
> > +{
> > + u32 value, pending, jdx, idx;
> > + struct {
> > + bool gazwrap;
> > + void __iomem *init_reg;
> > + u32 init_val;
> > + } ram, ram_init_list[] = {
> > + {false, spx5_reg_get(sparx5, ANA_AC_STAT_RESET),
> > + ANA_AC_STAT_RESET_RESET},
> > + {false, spx5_reg_get(sparx5, ASM_STAT_CFG),
> > + ASM_STAT_CFG_STAT_CNT_CLR_SHOT},
> > + {true, spx5_reg_get(sparx5, QSYS_RAM_INIT), 0},
> > + {true, spx5_reg_get(sparx5, REW_RAM_INIT), 0},
> > + {true, spx5_reg_get(sparx5, VOP_RAM_INIT), 0},
> > + {true, spx5_reg_get(sparx5, ANA_AC_RAM_INIT), 0},
> > + {true, spx5_reg_get(sparx5, ASM_RAM_INIT), 0},
> > + {true, spx5_reg_get(sparx5, EACL_RAM_INIT), 0},
> > + {true, spx5_reg_get(sparx5, VCAP_SUPER_RAM_INIT),
> > 0},
> > + {true, spx5_reg_get(sparx5, DSM_RAM_INIT), 0}
> > + };
>
> Looks like this could be const as well. And this does not really fit
> reverse christmas tree.
I will update this.
>
> > +
> > + spx5_rmw(EACL_POL_EACL_CFG_EACL_FORCE_INIT_SET(1),
> > + EACL_POL_EACL_CFG_EACL_FORCE_INIT,
> > + sparx5,
> > + EACL_POL_EACL_
Re: [RFC PATCH v2 2/8] net: sparx5: add the basic sparx5 driver
ere, and in other places, a comment like:
/* More code to be added in later patches */
would of been nice, just as a heads up. That is the problem with
linear patch review.
Will do
> > +static int __init sparx5_switch_reset(void)
> > +{
> > + const char *syscon_cpu = "microchip,sparx5-cpu-syscon",
> > + *syscon_gcb = "microchip,sparx5-gcb-syscon";
> > + struct regmap *cpu_ctrl, *gcb_ctrl;
> > + u32 val;
> > +
> > + cpu_ctrl = syscon_regmap_lookup_by_compatible(syscon_cpu);
> > + if (IS_ERR(cpu_ctrl)) {
> > + pr_err("No '%s' syscon map\n", syscon_cpu);
> > + return PTR_ERR(cpu_ctrl);
> > + }
> > +
> > + gcb_ctrl = syscon_regmap_lookup_by_compatible(syscon_gcb);
> > + if (IS_ERR(gcb_ctrl)) {
> > + pr_err("No '%s' syscon map\n", syscon_gcb);
> > + return PTR_ERR(gcb_ctrl);
> > + }
> > +
> > + /* Make sure the core is PROTECTED from reset */
> > + regmap_update_bits(cpu_ctrl, RESET_PROT_STAT,
> > +SYS_RST_PROT_VCORE, SYS_RST_PROT_VCORE);
> > +
> > + regmap_write(gcb_ctrl, spx5_offset(GCB_SOFT_RST),
> > + GCB_SOFT_RST_SOFT_SWC_RST_SET(1));
> > +
> > + return readx_poll_timeout(sparx5_read_gcb_soft_rst, gcb_ctrl,
> > val,
> > + GCB_SOFT_RST_SOFT_SWC_RST_GET(val)
> > == 0,
> > + 1, 100);
> > +}
> > +postcore_initcall(sparx5_switch_reset);
>
> That is pretty unusual. Why cannot this be done at probe time?
The problem is that the switch core reset also affects (reset) the
SGPIO controller.
We tried to put this in the reset driver, but it was rejected. If the
reset is done at probe time, the SGPIO driver may already have
initialized state.
The switch core reset will then reset all SGPIO registers.
Ah, O.K. Dumb question. Why is the SGPIO driver a separate driver? It
sounds like it should be embedded inside this driver if it is sharing
hardware.
The same SGPIO block is present (with suitable scaling of the number of
SGPIOS) in all our switches, so this driver will be reused on all the
platforms when we get them upstreamed (or at least that is the plan).
Another option would be to look at the reset subsystem, and have this
driver export a reset controller, which the SGPIO driver can bind to.
Given that the GPIO driver has been merged, if this will work, it is
probably a better solution.
Alex has already commented on this, but this is probably the goal as I
understand.
Andrew
BR
Steen
---
Steen Hegelund
steen.hegel...@microchip.com
Re: [RFC PATCH v2 3/8] net: sparx5: add hostmode with phylink support
Hi Andrew,
On 22.12.2020 15:41, Andrew Lunn wrote:
EXTERNAL EMAIL: Do not click links or open attachments unless you know the
content is safe
On Tue, Dec 22, 2020 at 10:46:12AM +0100, Steen Hegelund wrote:
Hi Andrew,
On Sat, 2020-12-19 at 20:51 +0100, Andrew Lunn wrote:
> EXTERNAL EMAIL: Do not click links or open attachments unless you
> know the content is safe
>
> > + /* Create a phylink for PHY management. Also handles SFPs */
> > + spx5_port->phylink_config.dev = &spx5_port->ndev->dev;
> > + spx5_port->phylink_co
> > nfig.type = PHYLINK_NETDEV;
> > + spx5_port->phylink_config.pcs_poll = true;
> > +
> > + /* phylink needs a valid interface mode to parse dt node */
> > + if (phy_mode == PHY_INTERFACE_MODE_NA)
> > + phy_mode = PHY_INTERFACE_MODE_10GBASER;
>
> Maybe just enforce a valid value in DT?
Maybe I need to clarify that you must choose between an Ethernet cuPHY
or an SFP, so it is optional.
But you also need to watch out for somebody putting a copper modules
in an SFP port. phylink will then set the mode to SGMII for a 1G
copper module, etc.
The cuPHY SFPs are handled by phylink out-of-the-box if the
kernel has added support for the particular cuPHY driver, and that is
done just by specifying the SFP phandle.
So here we just need to know if the user has attached a cuPHY directly
or an SFP.
The phylink_of_phy_connect function provides a way to add a cuPHY
direcly to the PHYLINK instance, but I have not found a way that you can
specify a specific cuPHY embedded in an SFP, so here PHYLINK determines
what is the appropriate PHY (driver) to use.
Could this be done in a simpler way?
> > +/* Configuration */
> > +static inline bool sparx5_use_cu_phy(struct sparx5_port *port)
> > +{
> > + return port->conf.phy_mode != PHY_INTERFACE_MODE_NA;
> > +}
>
> That is a rather odd definition of copper.
Should I rather use a bool property to select between the two options
(cuPHY or SFP)?
I guess what you are trying to indicate is between a hard wired Copper
PHY and an SFP cage? You have some sort of MII switch which allows the
MAC to be connected to either the QSGMII PHY, or an SFP cage? But
since the SFP cage could be populated with a copper PHY, and PHYLINK
will then instantiate a phylib copper PHY driver for it, looking at
phy_mode is not reliable. You need a property which selects the port,
not the technology.
Yes the intention was to be able to distinguish between the hardwired
cuPHY case and the SFP case.
I am OK with adding a property to distinguish between the two cases, but
if the SFP handle is present, PHYLINK has been able to handle an
embedded cuPHY (if the driver is available) and use that in the tests
that I have done so far. So my thinking was that if a phy handle is
present, then the user wants a directly attached cuPHY, not an SFP.
> > +static int sparx5_port_open(struct net_device *ndev)
> > +{
> > + struct sparx5_port *port = netdev_priv(ndev);
> > + int err = 0;
> > +
> > + err = phylink_of_phy_connect(port->phylink, port->of_node,
> > 0);
> > + if (err) {
> > + netdev_err(ndev, "Could not attach to PHY\n");
> > + return err;
> > + }
> > +
> > + phylink_start(port->phylink);
> > +
> > + if (!ndev->phydev) {
>
> Humm. When is ndev->phydev set? I don't think phylink ever sets it.
Indirectly: phylink_of_phy_connect uses phy_attach_direct and that sets
the phydev.
Ah, O.K. But watch out for a copper SFP module!
Hmm, my expectation is that we have this covered by now.
> > +static void sparx5_xtr_grp(struct sparx5 *sparx5, u8 grp, bool
> > byte_swap)
> > +{
> > + int i, byte_cnt = 0;
> > + bool eof_flag = false, pruned_flag = false, abort_flag =
> > false;
> > + u32 ifh[IFH_LEN];
> > + struct sk_buff *skb;
> > + struct frame_info fi;
> > + struct sparx5_port *port;
> > + struct net_device *netdev;
> > + u32 *rxbuf;
> > +
> > + /* Get IFH */
> > + for (i = 0; i < IFH_LEN; i++)
> > + ifh[i] = spx5_rd(sparx5, QS_XTR_RD(grp));
> > +
> > + /* Decode IFH (whats needed) */
> > + sparx5_ifh_parse(ifh, &fi);
> > +
> > + /* Map to port netdev */
> > + port = fi.src_port < SPX5_PORTS ?
> > + sparx5->ports[fi.src_port] : NULL;
> > + if (!port || !port->ndev) {
> > + dev_err(sparx5->dev, "Data on inactive port %d\n",
> > fi.src_port);
> > + sparx5_xtr_flush(sparx5, grp);
> > + return;
> > + }
> > +
> >
Re: [RFC PATCH v2 5/8] net: sparx5: add switching, vlan and mactable support
port->pvid = vid;
+
+ /* Untagged egress vlan clasification */
classification
OK.
+ if (untagged && port->vid != vid) {
+ if (port->vid) {
+ netdev_err(port->ndev,
+"Port already has a native VLAN: %d\n",
+port->vid);
+ return -EBUSY;
+ }
+ port->vid = vid;
+ }
+
+ sparx5_vlan_port_apply(sparx5, port);
+
+ return 0;
+}
+void sparx5_update_fwd(struct sparx5 *sparx5)
+{
+ u32 mask[3];
+ DECLARE_BITMAP(workmask, SPX5_PORTS);
+ int port;
+
+ /* Divide up fwd mask in 32 bit words */
+ bitmap_to_arr32(mask, sparx5->bridge_fwd_mask, SPX5_PORTS);
+
+ /* Update flood masks */
+ for (port = PGID_UC_FLOOD; port <= PGID_BCAST; port++) {
+ spx5_wr(mask[0], sparx5, ANA_AC_PGID_CFG(port));
+ spx5_wr(mask[1], sparx5, ANA_AC_PGID_CFG1(port));
+ spx5_wr(mask[2], sparx5, ANA_AC_PGID_CFG2(port));
+ }
+
+ /* Update SRC masks */
+ for (port = 0; port < SPX5_PORTS; port++) {
+ if (test_bit(port, sparx5->bridge_fwd_mask)) {
+ /* Allow to send to all bridged but self */
+ bitmap_copy(workmask, sparx5->bridge_fwd_mask,
SPX5_PORTS);
+ clear_bit(port, workmask);
+ bitmap_to_arr32(mask, workmask, SPX5_PORTS);
+ spx5_wr(mask[0], sparx5, ANA_AC_SRC_CFG(port));
+ spx5_wr(mask[1], sparx5, ANA_AC_SRC_CFG1(port));
+ spx5_wr(mask[2], sparx5, ANA_AC_SRC_CFG2(port));
+ } else {
+ spx5_wr(0, sparx5, ANA_AC_SRC_CFG(port));
+ spx5_wr(0, sparx5, ANA_AC_SRC_CFG1(port));
+ spx5_wr(0, sparx5, ANA_AC_SRC_CFG2(port));
+ }
Humm, interesting. This seems to control what other ports a port can
send to. That is one of the basic features you need for supporting
multiple bridges. So i assume your problems is you cannot partition
the MAC table?
No, the MAC table is VLAN aware.
Andrew
BR
Steen
---
Steen Hegelund
steen.hegel...@microchip.com
Re: [RFC PATCH v2 8/8] arm64: dts: sparx5: Add the Sparx5 switch node
On 19.12.2020 21:24, Andrew Lunn wrote:
EXTERNAL EMAIL: Do not click links or open attachments unless you know the
content is safe
+ port13: port@13 {
+ reg = <13>;
+ /* Example: CU SFP, 1G speed */
+ max-speed = <1>;
One too many 0's for 1G.
Ah, but this is allocation for the port, not the speed. This just
used by the calendar module to allocate slots on the taxis as requested.
So I would say it is OK to overallocate in this case (but you could
argue it does not make much sense).
+ /* 25G SFPs */
+ port56: port@56 {
+ reg = <56>;
+ max-speed = <1>;
Why limit a 25G SFP to 10G?
In the PCB134 case it is to keep the total allocation below 200Gbits
((12+8)*10G). There is a port mux mode that provides 8*25G on the 25G
SerDes'es, but that would be a different DT.
The Datasheet shows which port mux combinations are possible, and not
all combinations of SerDes, Speed and interface are allowed.
The PCB134 was designed to showcase this "many 10G ports" mode, so that
is why we have the current DT.
Andrew
BR
Steen
---
Steen Hegelund
steen.hegel...@microchip.com
[PATCH v9 1/4] dt-bindings: phy: Add sparx5-serdes bindings
Document the Sparx5 ethernet serdes phy driver bindings.
Signed-off-by: Lars Povlsen
Signed-off-by: Steen Hegelund
---
.../bindings/phy/microchip,sparx5-serdes.yaml | 100 ++
1 file changed, 100 insertions(+)
create mode 100644
Documentation/devicetree/bindings/phy/microchip,sparx5-serdes.yaml
diff --git a/Documentation/devicetree/bindings/phy/microchip,sparx5-serdes.yaml
b/Documentation/devicetree/bindings/phy/microchip,sparx5-serdes.yaml
new file mode 100644
index ..bdbdb3bbddbe
--- /dev/null
+++ b/Documentation/devicetree/bindings/phy/microchip,sparx5-serdes.yaml
@@ -0,0 +1,100 @@
+# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/phy/microchip,sparx5-serdes.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Microchip Sparx5 Serdes controller
+
+maintainers:
+ - Steen Hegelund
+
+description: |
+ The Sparx5 SERDES interfaces share the same basic functionality, but
+ support different operating modes and line rates.
+
+ The following list lists the SERDES features:
+
+ * RX Adaptive Decision Feedback Equalizer (DFE)
+ * Programmable continuous time linear equalizer (CTLE)
+ * Rx variable gain control
+ * Rx built-in fault detector (loss-of-lock/loss-of-signal)
+ * Adjustable tx de-emphasis (FFE)
+ * Tx output amplitude control
+ * Supports rx eye monitor
+ * Multiple loopback modes
+ * Prbs generator and checker
+ * Polarity inversion control
+
+ SERDES6G:
+
+ The SERDES6G is a high-speed SERDES interface, which can operate at
+ the following data rates:
+
+ * 100 Mbps (100BASE-FX)
+ * 1.25 Gbps (SGMII/1000BASE-X/1000BASE-KX)
+ * 3.125 Gbps (2.5GBASE-X/2.5GBASE-KX)
+ * 5.15625 Gbps (5GBASE-KR/5G-USXGMII)
+
+ SERDES10G
+
+ The SERDES10G is a high-speed SERDES interface, which can operate at
+ the following data rates:
+
+ * 100 Mbps (100BASE-FX)
+ * 1.25 Gbps (SGMII/1000BASE-X/1000BASE-KX)
+ * 3.125 Gbps (2.5GBASE-X/2.5GBASE-KX)
+ * 5 Gbps (QSGMII/USGMII)
+ * 5.15625 Gbps (5GBASE-KR/5G-USXGMII)
+ * 10 Gbps (10G-USGMII)
+ * 10.3125 Gbps (10GBASE-R/10GBASE-KR/USXGMII)
+
+ SERDES25G
+
+ The SERDES25G is a high-speed SERDES interface, which can operate at
+ the following data rates:
+
+ * 1.25 Gbps (SGMII/1000BASE-X/1000BASE-KX)
+ * 3.125 Gbps (2.5GBASE-X/2.5GBASE-KX)
+ * 5 Gbps (QSGMII/USGMII)
+ * 5.15625 Gbps (5GBASE-KR/5G-USXGMII)
+ * 10 Gbps (10G-USGMII)
+ * 10.3125 Gbps (10GBASE-R/10GBASE-KR/USXGMII)
+ * 25.78125 Gbps (25GBASE-KR/25GBASE-CR/25GBASE-SR/25GBASE-LR/25GBASE-ER)
+
+properties:
+ $nodename:
+pattern: "^serdes@[0-9a-f]+$"
+
+ compatible:
+const: microchip,sparx5-serdes
+
+ reg:
+minItems: 1
+
+ '#phy-cells':
+const: 1
+description: |
+ - The main serdes input port
+
+ clocks:
+maxItems: 1
+
+required:
+ - compatible
+ - reg
+ - '#phy-cells'
+ - clocks
+
+additionalProperties: false
+
+examples:
+ - |
+serdes: serdes@10808000 {
+ compatible = "microchip,sparx5-serdes";
+ #phy-cells = <1>;
+ clocks = <&sys_clk>;
+ reg = <0x10808000 0x5d>;
+};
+
+...
--
2.29.2
[PATCH v9 0/4] Adding the Sparx5 Serdes driver
functions. - Device tree - Provide only one IO range v5 -> v6: Series error: This had the same content as v5 v4 -> v5: - Bindings: - Removed .yaml from compatible string - reg prop: removed description and added minItems - reg-names prop: removed description and added const name list and minItems - #phy-cells prop: removed description and added maxItems - Configuration interface - Removed include of linux/phy.h - Added include of linux/types.h - Driver - Added include of linux/phy.h v3 -> v4: - Add a reg-names item to the binding description - Add a clocks item to the binding description - Removed the clock parameter from the configuration interface - Use the clock dt node to get the coreclock, and using that when doing the actual serdes configuration - Added a clocks entry with a system clock reference to the serdes node in the device tree v2 -> v3: - Sorted the Kconfig sourced folders - Sorted the Makefile included folders - Changed the configuration interface documentation to use kernel style v1 -> v2: Fixed kernel test robot warnings - Made these structures static: - media_presets_25g - mode_presets_25g - media_presets_10g - mode_presets_10g - Removed these duplicate initializations: - sparx5_sd25g28_params.cfg_rx_reserve_15_8 - sparx5_sd25g28_params.cfg_pi_en - sparx5_sd25g28_params.cfg_cdrck_en - sparx5_sd10g28_params.cfg_cdrck_en Lars Povlsen (2): dt-bindings: phy: Add sparx5-serdes bindings arm64: dts: sparx5: Add Sparx5 serdes driver node Steen Hegelund (2): phy: Add ethernet serdes configuration option phy: Add Sparx5 ethernet serdes PHY driver .../bindings/phy/microchip,sparx5-serdes.yaml | 100 + arch/arm64/boot/dts/microchip/sparx5.dtsi |8 + drivers/phy/Kconfig |3 +- drivers/phy/Makefile |1 + drivers/phy/microchip/Kconfig | 12 + drivers/phy/microchip/Makefile|6 + drivers/phy/microchip/sparx5_serdes.c | 2436 +++ drivers/phy/microchip/sparx5_serdes.h | 129 + drivers/phy/microchip/sparx5_serdes_regs.h| 2695 + include/linux/phy/phy-ethernet-serdes.h | 30 + include/linux/phy/phy.h |4 + 11 files changed, 5423 insertions(+), 1 deletion(-) create mode 100644 Documentation/devicetree/bindings/phy/microchip,sparx5-serdes.yaml create mode 100644 drivers/phy/microchip/Kconfig create mode 100644 drivers/phy/microchip/Makefile create mode 100644 drivers/phy/microchip/sparx5_serdes.c create mode 100644 drivers/phy/microchip/sparx5_serdes.h create mode 100644 drivers/phy/microchip/sparx5_serdes_regs.h create mode 100644 include/linux/phy/phy-ethernet-serdes.h -- 2.29.2
[PATCH v9 2/4] phy: Add ethernet serdes configuration option
Provide a new ethernet phy configuration structure, that
allow PHYs used for ethernet to be configured with
speed, media type and clock information.
Signed-off-by: Lars Povlsen
Signed-off-by: Steen Hegelund
---
include/linux/phy/phy-ethernet-serdes.h | 30 +
include/linux/phy/phy.h | 4
2 files changed, 34 insertions(+)
create mode 100644 include/linux/phy/phy-ethernet-serdes.h
diff --git a/include/linux/phy/phy-ethernet-serdes.h
b/include/linux/phy/phy-ethernet-serdes.h
new file mode 100644
index ..d2462fadf179
--- /dev/null
+++ b/include/linux/phy/phy-ethernet-serdes.h
@@ -0,0 +1,30 @@
+/* SPDX-License-Identifier: (GPL-2.0 OR MIT) */
+/*
+ * Microchip Sparx5 Ethernet SerDes driver
+ *
+ * Copyright (c) 2020 Microschip Inc
+ */
+#ifndef __PHY_ETHERNET_SERDES_H_
+#define __PHY_ETHERNET_SERDES_H_
+
+#include
+
+enum ethernet_media_type {
+ ETH_MEDIA_DEFAULT,
+ ETH_MEDIA_SR,
+ ETH_MEDIA_DAC,
+};
+
+/**
+ * struct phy_configure_opts_eth_serdes - Ethernet SerDes This structure is
used
+ * to represent the configuration state of a Ethernet Serdes PHY.
+ * @speed: Speed of the serdes interface in Mbps
+ * @media_type: Specifies which media the serdes will be using
+ */
+struct phy_configure_opts_eth_serdes {
+ u32speed;
+ enum ethernet_media_type media_type;
+};
+
+#endif
+
diff --git a/include/linux/phy/phy.h b/include/linux/phy/phy.h
index e435bdb0bab3..78ecb375cede 100644
--- a/include/linux/phy/phy.h
+++ b/include/linux/phy/phy.h
@@ -18,6 +18,7 @@
#include
#include
+#include
struct phy;
@@ -49,11 +50,14 @@ enum phy_mode {
*
* @mipi_dphy: Configuration set applicable for phys supporting
* the MIPI_DPHY phy mode.
+ * @eth_serdes: Configuration set applicable for phys supporting
+ * the ethernet serdes.
* @dp:Configuration set applicable for phys supporting
* the DisplayPort protocol.
*/
union phy_configure_opts {
struct phy_configure_opts_mipi_dphy mipi_dphy;
+ struct phy_configure_opts_eth_serdeseth_serdes;
struct phy_configure_opts_dpdp;
};
--
2.29.2
[PATCH v9 4/4] arm64: dts: sparx5: Add Sparx5 serdes driver node
Add Sparx5 serdes driver node, and enable it generally for all
reference boards.
Signed-off-by: Lars Povlsen
Signed-off-by: Steen Hegelund
---
arch/arm64/boot/dts/microchip/sparx5.dtsi | 8
1 file changed, 8 insertions(+)
diff --git a/arch/arm64/boot/dts/microchip/sparx5.dtsi
b/arch/arm64/boot/dts/microchip/sparx5.dtsi
index 8e7724d413fb..797601a9d542 100644
--- a/arch/arm64/boot/dts/microchip/sparx5.dtsi
+++ b/arch/arm64/boot/dts/microchip/sparx5.dtsi
@@ -287,5 +287,13 @@ tmon0: tmon@610508110 {
#thermal-sensor-cells = <0>;
clocks = <&ahb_clk>;
};
+
+ serdes: serdes@10808000 {
+ compatible = "microchip,sparx5-serdes";
+ #phy-cells = <1>;
+ clocks = <&sys_clk>;
+ reg = <0x6 0x10808000 0x5d>;
+ };
+
};
};
--
2.29.2
[PATCH 0/3] Adding the Sparx5 Switch Reset Driver
This series provides the Microchip Sparx5 Switch Reset Driver The Sparx5 Switch SoC has a number of components that can be reset individually, but at least the Switch Core needs to be in a well defined state at power on, when any of the Sparx5 drivers starts to access the Switch Core, this reset driver is available. The reset driver is loaded early via the postcore_initcall interface, and will then be available for the other Sparx5 drivers (SGPIO, SwitchDev etc) that are loaded next, and the first of them to be loaded can perform the one-time Switch Core reset that is needed. The driver has protection so that the system busses, DDR controller, PCI-E and ARM A53 CPU and a few other subsystems are not touched by the reset. The Sparx5 Chip Register Model can be browsed at this location: https://github.com/microchip-ung/sparx-5_reginfo Steen Hegelund (3): dt-bindings: reset: microchip sparx5 reset driver bindings reset: mchp: sparx5: add switch reset driver arm64: dts: reset: add microchip sparx5 switch reset driver .../bindings/reset/microchip,rst.yaml | 52 +++ arch/arm64/boot/dts/microchip/sparx5.dtsi | 13 +- drivers/reset/Kconfig | 8 + drivers/reset/Makefile| 1 + drivers/reset/reset-microchip-sparx5.c| 145 ++ 5 files changed, 216 insertions(+), 3 deletions(-) create mode 100644 Documentation/devicetree/bindings/reset/microchip,rst.yaml create mode 100644 drivers/reset/reset-microchip-sparx5.c -- 2.29.2
[PATCH 3/3] arm64: dts: reset: add microchip sparx5 switch reset driver
Signed-off-by: Steen Hegelund
---
arch/arm64/boot/dts/microchip/sparx5.dtsi | 13 ++---
1 file changed, 10 insertions(+), 3 deletions(-)
diff --git a/arch/arm64/boot/dts/microchip/sparx5.dtsi
b/arch/arm64/boot/dts/microchip/sparx5.dtsi
index 380281f312d8..6f0a21c362e3 100644
--- a/arch/arm64/boot/dts/microchip/sparx5.dtsi
+++ b/arch/arm64/boot/dts/microchip/sparx5.dtsi
@@ -132,9 +132,16 @@ mux: mux-controller {
};
};
- reset@611010008 {
- compatible = "microchip,sparx5-chip-reset";
- reg = <0x6 0x11010008 0x4>;
+ gcb_ctrl: syscon@61101 {
+ compatible = "microchip,sparx5-gcb-syscon", "syscon";
+ reg = <0x6 0x1101 0x1>;
+ };
+
+ reset: reset-controller@0 {
+ compatible = "microchip,sparx5-switch-reset";
+ reg = <0x6 0x0 0x0>;
+ #reset-cells = <1>;
+ syscons = <&cpu_ctrl>,<&gcb_ctrl>;
};
uart0: serial@60010 {
--
2.29.2
[PATCH 1/3] dt-bindings: reset: microchip sparx5 reset driver bindings
Signed-off-by: Steen Hegelund
---
.../bindings/reset/microchip,rst.yaml | 52 +++
1 file changed, 52 insertions(+)
create mode 100644 Documentation/devicetree/bindings/reset/microchip,rst.yaml
diff --git a/Documentation/devicetree/bindings/reset/microchip,rst.yaml
b/Documentation/devicetree/bindings/reset/microchip,rst.yaml
new file mode 100644
index ..b5526753e85d
--- /dev/null
+++ b/Documentation/devicetree/bindings/reset/microchip,rst.yaml
@@ -0,0 +1,52 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: "http://devicetree.org/schemas/reset/microchip,rst.yaml#";
+$schema: "http://devicetree.org/meta-schemas/core.yaml#";
+
+title: Microchip Sparx5 Switch Reset Controller
+
+maintainers:
+ - Steen Hegelund
+ - Lars Povlsen
+
+description: |
+ The Microchip Sparx5 Switch provides reset control and implements the
following
+ functions
+- One Time Switch Core Reset (Soft Reset)
+
+properties:
+ $nodename:
+pattern: "^reset-controller@[0-9a-f]+$"
+
+ compatible:
+const: microchip,sparx5-switch-reset
+
+ reg:
+maxItems: 1
+
+ "#reset-cells":
+const: 1
+
+ syscons:
+$ref: "/schemas/types.yaml#/definitions/phandle-array"
+description: Array of syscons used to access reset registers
+minItems: 2
+
+required:
+ - compatible
+ - reg
+ - "#reset-cells"
+ - syscons
+
+additionalProperties: false
+
+examples:
+ - |
+reset: reset-controller@0 {
+compatible = "microchip,sparx5-switch-reset";
+reg = <0x0 0x0>;
+#reset-cells = <1>;
+syscons = <&cpu_ctrl>,<&gcb_ctrl>;
+};
+
--
2.29.2
[PATCH 2/3] reset: mchp: sparx5: add switch reset driver
Signed-off-by: Steen Hegelund
---
drivers/reset/Kconfig | 8 ++
drivers/reset/Makefile | 1 +
drivers/reset/reset-microchip-sparx5.c | 145 +
3 files changed, 154 insertions(+)
create mode 100644 drivers/reset/reset-microchip-sparx5.c
diff --git a/drivers/reset/Kconfig b/drivers/reset/Kconfig
index 71ab75a46491..05c240c47a8a 100644
--- a/drivers/reset/Kconfig
+++ b/drivers/reset/Kconfig
@@ -101,6 +101,14 @@ config RESET_LPC18XX
help
This enables the reset controller driver for NXP LPC18xx/43xx SoCs.
+config RESET_MCHP_SPARX5
+ bool "Microchip Sparx5 reset driver"
+ depends on HAS_IOMEM || COMPILE_TEST
+ default y if SPARX5_SWITCH
+ select MFD_SYSCON
+ help
+ This driver supports switch core reset for the Microchip Sparx5 SoC.
+
config RESET_MESON
tristate "Meson Reset Driver"
depends on ARCH_MESON || COMPILE_TEST
diff --git a/drivers/reset/Makefile b/drivers/reset/Makefile
index 1054123fd187..341fd9ab4bf6 100644
--- a/drivers/reset/Makefile
+++ b/drivers/reset/Makefile
@@ -15,6 +15,7 @@ obj-$(CONFIG_RESET_IMX7) += reset-imx7.o
obj-$(CONFIG_RESET_INTEL_GW) += reset-intel-gw.o
obj-$(CONFIG_RESET_LANTIQ) += reset-lantiq.o
obj-$(CONFIG_RESET_LPC18XX) += reset-lpc18xx.o
+obj-$(CONFIG_RESET_MCHP_SPARX5) += reset-microchip-sparx5.o
obj-$(CONFIG_RESET_MESON) += reset-meson.o
obj-$(CONFIG_RESET_MESON_AUDIO_ARB) += reset-meson-audio-arb.o
obj-$(CONFIG_RESET_NPCM) += reset-npcm.o
diff --git a/drivers/reset/reset-microchip-sparx5.c
b/drivers/reset/reset-microchip-sparx5.c
new file mode 100644
index ..bb636ebd22d2
--- /dev/null
+++ b/drivers/reset/reset-microchip-sparx5.c
@@ -0,0 +1,145 @@
+// SPDX-License-Identifier: GPL-2.0+
+/* Microchip Sparx5 Switch Reset driver
+ *
+ * Copyright (c) 2020 Microchip Technology Inc. and its subsidiaries.
+ *
+ * The Sparx5 Chip Register Model can be browsed at this location:
+ * https://github.com/microchip-ung/sparx-5_reginfo
+ */
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+#define PROTECT_REG0x84
+#define PROTECT_BITBIT(10)
+#define SOFT_RESET_REG 0x08
+#define SOFT_RESET_BIT BIT(1)
+
+struct mchp_reset_context {
+ struct device *dev;
+ struct regmap *cpu_ctrl;
+ struct regmap *gcb_ctrl;
+ struct reset_controller_dev reset_ctrl;
+};
+
+static u32 sparx5_read_soft_rst(struct mchp_reset_context *ctx)
+{
+ u32 val;
+
+ regmap_read(ctx->gcb_ctrl, SOFT_RESET_REG, &val);
+ return val;
+}
+
+static int sparx5_switch_reset(struct reset_controller_dev *rcdev,
+ unsigned long id)
+{
+ struct mchp_reset_context *ctx =
+ container_of(rcdev, struct mchp_reset_context, reset_ctrl);
+ u32 val;
+
+ /* Make sure the core is PROTECTED from reset */
+ regmap_update_bits(ctx->cpu_ctrl, PROTECT_REG, PROTECT_BIT,
PROTECT_BIT);
+
+ dev_info(ctx->dev, "soft reset of switchcore\n");
+
+ /* Start soft reset */
+ regmap_write(ctx->gcb_ctrl, SOFT_RESET_REG, SOFT_RESET_BIT);
+
+ /* Wait for soft reset done */
+ return read_poll_timeout(sparx5_read_soft_rst, val,
+(val & SOFT_RESET_BIT) == 0,
+1, 100, false,
+ctx);
+}
+
+static const struct reset_control_ops sparx5_reset_ops = {
+ .reset = sparx5_switch_reset,
+};
+
+static int mchp_sparx5_reset_config(struct platform_device *pdev,
+ struct mchp_reset_context *ctx)
+{
+ struct device_node *dn = pdev->dev.of_node;
+ struct regmap *cpu_ctrl, *gcb_ctrl;
+ struct device_node *syscon_np;
+ int err;
+
+ syscon_np = of_parse_phandle(dn, "syscons", 0);
+ if (!syscon_np)
+ return -ENODEV;
+ cpu_ctrl = syscon_node_to_regmap(syscon_np);
+ if (IS_ERR(cpu_ctrl))
+ goto err_cpu;
+ of_node_put(syscon_np);
+
+ syscon_np = of_parse_phandle(dn, "syscons", 1);
+ if (!syscon_np)
+ return -ENODEV;
+ gcb_ctrl = syscon_node_to_regmap(syscon_np);
+ if (IS_ERR(gcb_ctrl))
+ goto err_gcb;
+ of_node_put(syscon_np);
+
+ ctx->cpu_ctrl = cpu_ctrl;
+ ctx->gcb_ctrl = gcb_ctrl;
+
+ ctx->reset_ctrl.owner = THIS_MODULE;
+ ctx->reset_ctrl.nr_resets = 1;
+ ctx->reset_ctrl.ops = &sparx5_reset_ops;
+ ctx->reset_ctrl.of_node = dn;
+
+ err = devm_reset_controller_register(&pdev->dev, &ctx->reset_ctrl);
+ if (err)
+ dev_err(&pdev->dev, "could not register reset controller\n");
+ pr_info("%s:%d\n", __func__, __LINE__);
+ return err;
+err_cpu:
+ of_
Re: [PATCH 2/3] reset: mchp: sparx5: add switch reset driver
On Thu, 2021-01-14 at 00:23 +0100, Andrew Lunn wrote:
> EXTERNAL EMAIL: Do not click links or open attachments unless you
> know the content is safe
>
> > +static int sparx5_switch_reset(struct reset_controller_dev *rcdev,
> > + unsigned long id)
> > +{
> > + struct mchp_reset_context *ctx =
> > + container_of(rcdev, struct mchp_reset_context,
> > reset_ctrl);
> > + u32 val;
> > +
> > + /* Make sure the core is PROTECTED from reset */
> > + regmap_update_bits(ctx->cpu_ctrl, PROTECT_REG, PROTECT_BIT,
> > PROTECT_BIT);
> > +
> > + dev_info(ctx->dev, "soft reset of switchcore\n");
>
> dev_dbg()?
I will remove that.
>
> > +
> > + /* Start soft reset */
> > + regmap_write(ctx->gcb_ctrl, SOFT_RESET_REG, SOFT_RESET_BIT);
> > +
> > + /* Wait for soft reset done */
> > + return read_poll_timeout(sparx5_read_soft_rst, val,
> > + (val & SOFT_RESET_BIT) == 0,
> > + 1, 100, false,
> > + ctx);
> > +}
>
> > +static int mchp_sparx5_reset_config(struct platform_device *pdev,
> > + struct mchp_reset_context *ctx)
> > +{
> > + struct device_node *dn = pdev->dev.of_node;
> > + struct regmap *cpu_ctrl, *gcb_ctrl;
> > + struct device_node *syscon_np;
> > + int err;
> > +
> > + syscon_np = of_parse_phandle(dn, "syscons", 0);
> > + if (!syscon_np)
> > + return -ENODEV;
> > + cpu_ctrl = syscon_node_to_regmap(syscon_np);
> > + if (IS_ERR(cpu_ctrl))
> > + goto err_cpu;
> > + of_node_put(syscon_np);
> > +
> > + syscon_np = of_parse_phandle(dn, "syscons", 1);
> > + if (!syscon_np)
> > + return -ENODEV;
> > + gcb_ctrl = syscon_node_to_regmap(syscon_np);
> > + if (IS_ERR(gcb_ctrl))
> > + goto err_gcb;
> > + of_node_put(syscon_np);
> > +
> > + ctx->cpu_ctrl = cpu_ctrl;
> > + ctx->gcb_ctrl = gcb_ctrl;
> > +
> > + ctx->reset_ctrl.owner = THIS_MODULE;
> > + ctx->reset_ctrl.nr_resets = 1;
> > + ctx->reset_ctrl.ops = &sparx5_reset_ops;
> > + ctx->reset_ctrl.of_node = dn;
> > +
> > + err = devm_reset_controller_register(&pdev->dev, &ctx-
> > >reset_ctrl);
> > + if (err)
> > + dev_err(&pdev->dev, "could not register reset
> > controller\n");
> > + pr_info("%s:%d\n", __func__, __LINE__);
> > + return err;
> > +err_cpu:
> > + of_node_put(syscon_np);
> > + dev_err(&pdev->dev, "No cpu syscon map\n");
> > + return PTR_ERR(cpu_ctrl);
> > +err_gcb:
> > + of_node_put(syscon_np);
> > + dev_err(&pdev->dev, "No gcb syscon map\n");
> > + return PTR_ERR(gcb_ctrl);
>
> It would be normal to put the dev_err() before the goto, set err =
> PTR_ERR() and then goto out;
OK. I will change that.
>
>
> > +}
> > +
> > +static int mchp_sparx5_reset_probe(struct platform_device *pdev)
> > +{
> > + struct device *dev = &pdev->dev;
> > + struct mchp_reset_context *ctx;
> > +
> > + pr_info("%s:%d\n", __func__, __LINE__);
>
> More left over debug.
Yes. That will have to go.
>
> > + ctx = devm_kzalloc(dev, sizeof(*ctx), GFP_KERNEL);
> > + if (!ctx)
> > + return -ENOMEM;
> > + ctx->dev = dev;
> > + return mchp_sparx5_reset_config(pdev, ctx);
> > +}
> > +
> > +static const struct of_device_id mchp_sparx5_reset_of_match[] = {
> > + {
> > + .compatible = "microchip,sparx5-switch-reset",
> > + },
> > + { /*sentinel*/ }
> > +};
>
> > +static int __init mchp_sparx5_reset_init(void)
> > +{
> > + return platform_driver_register(&mchp_sparx5_reset_driver);
> > +}
> > +
> > +postcore_initcall(mchp_sparx5_reset_init);
>
> Does it actually need to be postcore? The users of the reset should
> look for -EPROBE_DEFER and try again later. And this then becomes
> just
> a normal driver.
I tried using that, but the SGPIO driver bailed out after 3 DEFER
attempts, so that is why I changed it to use the postcore_initcall.
Maybe it is because the SGPIO driver is a builtin_platform_driver?
>
> Andrew
[PATCH v2 0/3] Adding the Sparx5 Switch Reset Driver
This series provides the Microchip Sparx5 Switch Reset Driver The Sparx5 Switch SoC has a number of components that can be reset individually, but at least the Switch Core needs to be in a well defined state at power on, when any of the Sparx5 drivers starts to access the Switch Core, this reset driver is available. The reset driver is loaded early via the postcore_initcall interface, and will then be available for the other Sparx5 drivers (SGPIO, SwitchDev etc) that are loaded next, and the first of them to be loaded can perform the one-time Switch Core reset that is needed. The driver has protection so that the system busses, DDR controller, PCI-E and ARM A53 CPU and a few other subsystems are not touched by the reset. The Sparx5 Chip Register Model can be browsed at this location: https://github.com/microchip-ung/sparx-5_reginfo History: v1 - v2: Removed debug prints Changed the error handling to save the error code before jumping. Steen Hegelund (3): dt-bindings: reset: microchip sparx5 reset driver bindings reset: mchp: sparx5: add switch reset driver arm64: dts: reset: add microchip sparx5 switch reset driver .../bindings/reset/microchip,rst.yaml | 52 +++ arch/arm64/boot/dts/microchip/sparx5.dtsi | 13 +- drivers/reset/Kconfig | 8 + drivers/reset/Makefile| 1 + drivers/reset/reset-microchip-sparx5.c| 146 ++ 5 files changed, 217 insertions(+), 3 deletions(-) create mode 100644 Documentation/devicetree/bindings/reset/microchip,rst.yaml create mode 100644 drivers/reset/reset-microchip-sparx5.c -- 2.29.2
[PATCH v2 3/3] arm64: dts: reset: add microchip sparx5 switch reset driver
Signed-off-by: Steen Hegelund
---
arch/arm64/boot/dts/microchip/sparx5.dtsi | 13 ++---
1 file changed, 10 insertions(+), 3 deletions(-)
diff --git a/arch/arm64/boot/dts/microchip/sparx5.dtsi
b/arch/arm64/boot/dts/microchip/sparx5.dtsi
index 380281f312d8..6f0a21c362e3 100644
--- a/arch/arm64/boot/dts/microchip/sparx5.dtsi
+++ b/arch/arm64/boot/dts/microchip/sparx5.dtsi
@@ -132,9 +132,16 @@ mux: mux-controller {
};
};
- reset@611010008 {
- compatible = "microchip,sparx5-chip-reset";
- reg = <0x6 0x11010008 0x4>;
+ gcb_ctrl: syscon@61101 {
+ compatible = "microchip,sparx5-gcb-syscon", "syscon";
+ reg = <0x6 0x1101 0x1>;
+ };
+
+ reset: reset-controller@0 {
+ compatible = "microchip,sparx5-switch-reset";
+ reg = <0x6 0x0 0x0>;
+ #reset-cells = <1>;
+ syscons = <&cpu_ctrl>,<&gcb_ctrl>;
};
uart0: serial@60010 {
--
2.29.2
[PATCH v2 2/3] reset: mchp: sparx5: add switch reset driver
Signed-off-by: Steen Hegelund
---
drivers/reset/Kconfig | 8 ++
drivers/reset/Makefile | 1 +
drivers/reset/reset-microchip-sparx5.c | 146 +
3 files changed, 155 insertions(+)
create mode 100644 drivers/reset/reset-microchip-sparx5.c
diff --git a/drivers/reset/Kconfig b/drivers/reset/Kconfig
index 71ab75a46491..05c240c47a8a 100644
--- a/drivers/reset/Kconfig
+++ b/drivers/reset/Kconfig
@@ -101,6 +101,14 @@ config RESET_LPC18XX
help
This enables the reset controller driver for NXP LPC18xx/43xx SoCs.
+config RESET_MCHP_SPARX5
+ bool "Microchip Sparx5 reset driver"
+ depends on HAS_IOMEM || COMPILE_TEST
+ default y if SPARX5_SWITCH
+ select MFD_SYSCON
+ help
+ This driver supports switch core reset for the Microchip Sparx5 SoC.
+
config RESET_MESON
tristate "Meson Reset Driver"
depends on ARCH_MESON || COMPILE_TEST
diff --git a/drivers/reset/Makefile b/drivers/reset/Makefile
index 1054123fd187..341fd9ab4bf6 100644
--- a/drivers/reset/Makefile
+++ b/drivers/reset/Makefile
@@ -15,6 +15,7 @@ obj-$(CONFIG_RESET_IMX7) += reset-imx7.o
obj-$(CONFIG_RESET_INTEL_GW) += reset-intel-gw.o
obj-$(CONFIG_RESET_LANTIQ) += reset-lantiq.o
obj-$(CONFIG_RESET_LPC18XX) += reset-lpc18xx.o
+obj-$(CONFIG_RESET_MCHP_SPARX5) += reset-microchip-sparx5.o
obj-$(CONFIG_RESET_MESON) += reset-meson.o
obj-$(CONFIG_RESET_MESON_AUDIO_ARB) += reset-meson-audio-arb.o
obj-$(CONFIG_RESET_NPCM) += reset-npcm.o
diff --git a/drivers/reset/reset-microchip-sparx5.c
b/drivers/reset/reset-microchip-sparx5.c
new file mode 100644
index ..f5899891356d
--- /dev/null
+++ b/drivers/reset/reset-microchip-sparx5.c
@@ -0,0 +1,146 @@
+// SPDX-License-Identifier: GPL-2.0+
+/* Microchip Sparx5 Switch Reset driver
+ *
+ * Copyright (c) 2020 Microchip Technology Inc. and its subsidiaries.
+ *
+ * The Sparx5 Chip Register Model can be browsed at this location:
+ * https://github.com/microchip-ung/sparx-5_reginfo
+ */
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+#define PROTECT_REG0x84
+#define PROTECT_BITBIT(10)
+#define SOFT_RESET_REG 0x08
+#define SOFT_RESET_BIT BIT(1)
+
+struct mchp_reset_context {
+ struct device *dev;
+ struct regmap *cpu_ctrl;
+ struct regmap *gcb_ctrl;
+ struct reset_controller_dev reset_ctrl;
+};
+
+static u32 sparx5_read_soft_rst(struct mchp_reset_context *ctx)
+{
+ u32 val;
+
+ regmap_read(ctx->gcb_ctrl, SOFT_RESET_REG, &val);
+ return val;
+}
+
+static int sparx5_switch_reset(struct reset_controller_dev *rcdev,
+ unsigned long id)
+{
+ struct mchp_reset_context *ctx =
+ container_of(rcdev, struct mchp_reset_context, reset_ctrl);
+ u32 val;
+
+ /* Make sure the core is PROTECTED from reset */
+ regmap_update_bits(ctx->cpu_ctrl, PROTECT_REG, PROTECT_BIT,
PROTECT_BIT);
+
+ /* Start soft reset */
+ regmap_write(ctx->gcb_ctrl, SOFT_RESET_REG, SOFT_RESET_BIT);
+
+ /* Wait for soft reset done */
+ return read_poll_timeout(sparx5_read_soft_rst, val,
+(val & SOFT_RESET_BIT) == 0,
+1, 100, false,
+ctx);
+}
+
+static const struct reset_control_ops sparx5_reset_ops = {
+ .reset = sparx5_switch_reset,
+};
+
+static int mchp_sparx5_reset_config(struct platform_device *pdev,
+ struct mchp_reset_context *ctx)
+{
+ struct device_node *dn = pdev->dev.of_node;
+ struct regmap *cpu_ctrl, *gcb_ctrl;
+ struct device_node *syscon_np;
+ int err;
+
+ syscon_np = of_parse_phandle(dn, "syscons", 0);
+ if (!syscon_np)
+ return -ENODEV;
+ cpu_ctrl = syscon_node_to_regmap(syscon_np);
+ if (IS_ERR(cpu_ctrl)) {
+ err = PTR_ERR(cpu_ctrl);
+ goto syscon_err;
+ }
+ of_node_put(syscon_np);
+
+ syscon_np = of_parse_phandle(dn, "syscons", 1);
+ if (!syscon_np)
+ return -ENODEV;
+ gcb_ctrl = syscon_node_to_regmap(syscon_np);
+ if (IS_ERR(gcb_ctrl)) {
+ err = PTR_ERR(gcb_ctrl);
+ goto syscon_err;
+ }
+ of_node_put(syscon_np);
+
+ ctx->cpu_ctrl = cpu_ctrl;
+ ctx->gcb_ctrl = gcb_ctrl;
+
+ ctx->reset_ctrl.owner = THIS_MODULE;
+ ctx->reset_ctrl.nr_resets = 1;
+ ctx->reset_ctrl.ops = &sparx5_reset_ops;
+ ctx->reset_ctrl.of_node = dn;
+
+ err = devm_reset_controller_register(&pdev->dev, &ctx->reset_ctrl);
+ if (err)
+ dev_err(&pdev->dev, "could not register reset controller\n");
+ return err;
+
+syscon_err:
+
[PATCH v2 1/3] dt-bindings: reset: microchip sparx5 reset driver bindings
Signed-off-by: Steen Hegelund
---
.../bindings/reset/microchip,rst.yaml | 52 +++
1 file changed, 52 insertions(+)
create mode 100644 Documentation/devicetree/bindings/reset/microchip,rst.yaml
diff --git a/Documentation/devicetree/bindings/reset/microchip,rst.yaml
b/Documentation/devicetree/bindings/reset/microchip,rst.yaml
new file mode 100644
index ..b5526753e85d
--- /dev/null
+++ b/Documentation/devicetree/bindings/reset/microchip,rst.yaml
@@ -0,0 +1,52 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: "http://devicetree.org/schemas/reset/microchip,rst.yaml#";
+$schema: "http://devicetree.org/meta-schemas/core.yaml#";
+
+title: Microchip Sparx5 Switch Reset Controller
+
+maintainers:
+ - Steen Hegelund
+ - Lars Povlsen
+
+description: |
+ The Microchip Sparx5 Switch provides reset control and implements the
following
+ functions
+- One Time Switch Core Reset (Soft Reset)
+
+properties:
+ $nodename:
+pattern: "^reset-controller@[0-9a-f]+$"
+
+ compatible:
+const: microchip,sparx5-switch-reset
+
+ reg:
+maxItems: 1
+
+ "#reset-cells":
+const: 1
+
+ syscons:
+$ref: "/schemas/types.yaml#/definitions/phandle-array"
+description: Array of syscons used to access reset registers
+minItems: 2
+
+required:
+ - compatible
+ - reg
+ - "#reset-cells"
+ - syscons
+
+additionalProperties: false
+
+examples:
+ - |
+reset: reset-controller@0 {
+compatible = "microchip,sparx5-switch-reset";
+reg = <0x0 0x0>;
+#reset-cells = <1>;
+syscons = <&cpu_ctrl>,<&gcb_ctrl>;
+};
+
--
2.29.2
Re: [PATCH 1/3] dt-bindings: reset: microchip sparx5 reset driver bindings
Hi Philipp, On Thu, 2021-01-14 at 10:39 +0100, Philipp Zabel wrote: > EXTERNAL EMAIL: Do not click links or open attachments unless you > know the content is safe > > Hi Steen, > > On Wed, 2021-01-13 at 21:19 +0100, Steen Hegelund wrote: > > Signed-off-by: Steen Hegelund > > --- > > .../bindings/reset/microchip,rst.yaml | 52 > > +++ > > 1 file changed, 52 insertions(+) > > create mode 100644 > > Documentation/devicetree/bindings/reset/microchip,rst.yaml > > > > diff --git > > a/Documentation/devicetree/bindings/reset/microchip,rst.yaml > > b/Documentation/devicetree/bindings/reset/microchip,rst.yaml > > new file mode 100644 > > index ..b5526753e85d > > --- /dev/null > > +++ b/Documentation/devicetree/bindings/reset/microchip,rst.yaml > > @@ -0,0 +1,52 @@ > > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) > > +%YAML 1.2 > > +--- > > +$id: "http://devicetree.org/schemas/reset/microchip,rst.yaml#"; > > +$schema: "http://devicetree.org/meta-schemas/core.yaml#"; > > + > > +title: Microchip Sparx5 Switch Reset Controller > > + > > +maintainers: > > + - Steen Hegelund > > + - Lars Povlsen > > + > > +description: | > > + The Microchip Sparx5 Switch provides reset control and > > implements the following > > + functions > > + - One Time Switch Core Reset (Soft Reset) > > + > > +properties: > > + $nodename: > > + pattern: "^reset-controller@[0-9a-f]+$" > > + > > + compatible: > > + const: microchip,sparx5-switch-reset > > + > > + reg: > > + maxItems: 1 > > + > > + "#reset-cells": > > + const: 1 > > + > > + syscons: > > + $ref: "/schemas/types.yaml#/definitions/phandle-array" > > + description: Array of syscons used to access reset registers > > + minItems: 2 > > The order seems to be important in the driver, so this should specify > which is the CPU syscon and which is the GCB syscon. I'm not sure if > it > would be better to have two separately named syscon properties with a > single phandle each. Yes you got a point. I will change that. > > regards > Philipp BR Steen
Re: [PATCH 2/3] reset: mchp: sparx5: add switch reset driver
Hi Philipp,
On Thu, 2021-01-14 at 10:39 +0100, Philipp Zabel wrote:
> EXTERNAL EMAIL: Do not click links or open attachments unless you
> know the content is safe
>
> Hi Steen,
>
> thank you for the patch. In addition to Andrew's comments, I have a
> few
> more below:
>
> On Wed, 2021-01-13 at 21:19 +0100, Steen Hegelund wrote:
> > Signed-off-by: Steen Hegelund
> > ---
> > drivers/reset/Kconfig | 8 ++
> > drivers/reset/Makefile | 1 +
> > drivers/reset/reset-microchip-sparx5.c | 145
> > +
> > 3 files changed, 154 insertions(+)
> > create mode 100644 drivers/reset/reset-microchip-sparx5.c
> >
> > diff --git a/drivers/reset/Kconfig b/drivers/reset/Kconfig
> > index 71ab75a46491..05c240c47a8a 100644
> > --- a/drivers/reset/Kconfig
> > +++ b/drivers/reset/Kconfig
> > @@ -101,6 +101,14 @@ config RESET_LPC18XX
> > help
> > This enables the reset controller driver for NXP
> > LPC18xx/43xx SoCs.
> >
> > +config RESET_MCHP_SPARX5
> > + bool "Microchip Sparx5 reset driver"
> > + depends on HAS_IOMEM || COMPILE_TEST
> > + default y if SPARX5_SWITCH
> > + select MFD_SYSCON
> > + help
> > + This driver supports switch core reset for the Microchip
> > Sparx5 SoC.
> > +
> > config RESET_MESON
> > tristate "Meson Reset Driver"
> > depends on ARCH_MESON || COMPILE_TEST
> > diff --git a/drivers/reset/Makefile b/drivers/reset/Makefile
> > index 1054123fd187..341fd9ab4bf6 100644
> > --- a/drivers/reset/Makefile
> > +++ b/drivers/reset/Makefile
> > @@ -15,6 +15,7 @@ obj-$(CONFIG_RESET_IMX7) += reset-imx7.o
> > obj-$(CONFIG_RESET_INTEL_GW) += reset-intel-gw.o
> > obj-$(CONFIG_RESET_LANTIQ) += reset-lantiq.o
> > obj-$(CONFIG_RESET_LPC18XX) += reset-lpc18xx.o
> > +obj-$(CONFIG_RESET_MCHP_SPARX5) += reset-microchip-sparx5.o
> > obj-$(CONFIG_RESET_MESON) += reset-meson.o
> > obj-$(CONFIG_RESET_MESON_AUDIO_ARB) += reset-meson-audio-arb.o
> > obj-$(CONFIG_RESET_NPCM) += reset-npcm.o
> > diff --git a/drivers/reset/reset-microchip-sparx5.c
> > b/drivers/reset/reset-microchip-sparx5.c
> > new file mode 100644
> > index ..bb636ebd22d2
> > --- /dev/null
> > +++ b/drivers/reset/reset-microchip-sparx5.c
> > @@ -0,0 +1,145 @@
> > +// SPDX-License-Identifier: GPL-2.0+
> > +/* Microchip Sparx5 Switch Reset driver
> > + *
> > + * Copyright (c) 2020 Microchip Technology Inc. and its
> > subsidiaries.
> > + *
> > + * The Sparx5 Chip Register Model can be browsed at this location:
> > + * https://github.com/microchip-ung/sparx-5_reginfo
> > + */
> > +#include
> > +#include
> > +#include
>
> Please drop all unused headers.
Will do.
>
> > +#include
> > +#include
> > +#include
> > +#include
> > +#include
> > +#include
> > +
> > +#define PROTECT_REG 0x84
> > +#define PROTECT_BIT BIT(10)
> > +#define SOFT_RESET_REG 0x08
> > +#define SOFT_RESET_BIT BIT(1)
> > +
> > +struct mchp_reset_context {
> > + struct device *dev;
> > + struct regmap *cpu_ctrl;
> > + struct regmap *gcb_ctrl;
> > + struct reset_controller_dev reset_ctrl;
>
> For consistency, I'd like this to be called rcdev, or something else
> that doesn't sound like this should be a struct reset_control.
OK.
>
> > +};
> > +
> > +static u32 sparx5_read_soft_rst(struct mchp_reset_context *ctx)
> > +{
> > + u32 val;
> > +
> > + regmap_read(ctx->gcb_ctrl, SOFT_RESET_REG, &val);
> > + return val;
> > +}
>
> This can be dropped if you use regmap_read_poll_timeout() below.
Yes.
>
> > +static int sparx5_switch_reset(struct reset_controller_dev *rcdev,
> > + unsigned long id)
> > +{
> > + struct mchp_reset_context *ctx =
> > + container_of(rcdev, struct mchp_reset_context,
> > reset_ctrl);
> > + u32 val;
> > +
> > + /* Make sure the core is PROTECTED from reset */
> > + regmap_update_bits(ctx->cpu_ctrl, PROTECT_REG, PROTECT_BIT,
> > PROTECT_BIT);
> > +
> > + dev_info(ctx->dev, "soft reset of switchcore\n");
> > +
> > + /* Start soft reset */
> > + regmap_write(ctx->gcb_ctrl, SOFT_RESET_REG, SOFT_RESET_BIT);
> > +
> > + /* Wait for soft reset done */
> > + return read_poll_timeout(s
[PATCH v3 0/3] Adding the Sparx5 Switch Reset Driver
This series provides the Microchip Sparx5 Switch Reset Driver The Sparx5 Switch SoC has a number of components that can be reset individually, but at least the Switch Core needs to be in a well defined state at power on, when any of the Sparx5 drivers starts to access the Switch Core, this reset driver is available. The reset driver is loaded early via the postcore_initcall interface, and will then be available for the other Sparx5 drivers (SGPIO, SwitchDev etc) that are loaded next, and the first of them to be loaded can perform the one-time Switch Core reset that is needed. The driver has protection so that the system busses, DDR controller, PCI-E and ARM A53 CPU and a few other subsystems are not touched by the reset. The Sparx5 Chip Register Model can be browsed at this location: https://github.com/microchip-ung/sparx-5_reginfo History: v2 - v3: Removed unused headers Renamed the reset controller dev member. Use regmap_read_poll_timeout instead of polling a function. Used two separate syscon entries in the binding Simplified the syscon error handling. Simplified the devm_reset_controller_register error handling. Moved the contents of the mchp_sparx5_reset_config function into the probe function. v1 - v2: Removed debug prints Changed the error handling to save the error code before jumping. Steen Hegelund (3): dt-bindings: reset: microchip sparx5 reset driver bindings reset: mchp: sparx5: add switch reset driver arm64: dts: reset: add microchip sparx5 switch reset driver .../bindings/reset/microchip,rst.yaml | 59 + arch/arm64/boot/dts/microchip/sparx5.dtsi | 14 +- drivers/reset/Kconfig | 8 ++ drivers/reset/Makefile| 1 + drivers/reset/reset-microchip-sparx5.c| 120 ++ 5 files changed, 199 insertions(+), 3 deletions(-) create mode 100644 Documentation/devicetree/bindings/reset/microchip,rst.yaml create mode 100644 drivers/reset/reset-microchip-sparx5.c -- 2.29.2
[PATCH v3 2/3] reset: mchp: sparx5: add switch reset driver
Signed-off-by: Steen Hegelund
---
drivers/reset/Kconfig | 8 ++
drivers/reset/Makefile | 1 +
drivers/reset/reset-microchip-sparx5.c | 120 +
3 files changed, 129 insertions(+)
create mode 100644 drivers/reset/reset-microchip-sparx5.c
diff --git a/drivers/reset/Kconfig b/drivers/reset/Kconfig
index 71ab75a46491..05c240c47a8a 100644
--- a/drivers/reset/Kconfig
+++ b/drivers/reset/Kconfig
@@ -101,6 +101,14 @@ config RESET_LPC18XX
help
This enables the reset controller driver for NXP LPC18xx/43xx SoCs.
+config RESET_MCHP_SPARX5
+ bool "Microchip Sparx5 reset driver"
+ depends on HAS_IOMEM || COMPILE_TEST
+ default y if SPARX5_SWITCH
+ select MFD_SYSCON
+ help
+ This driver supports switch core reset for the Microchip Sparx5 SoC.
+
config RESET_MESON
tristate "Meson Reset Driver"
depends on ARCH_MESON || COMPILE_TEST
diff --git a/drivers/reset/Makefile b/drivers/reset/Makefile
index 1054123fd187..341fd9ab4bf6 100644
--- a/drivers/reset/Makefile
+++ b/drivers/reset/Makefile
@@ -15,6 +15,7 @@ obj-$(CONFIG_RESET_IMX7) += reset-imx7.o
obj-$(CONFIG_RESET_INTEL_GW) += reset-intel-gw.o
obj-$(CONFIG_RESET_LANTIQ) += reset-lantiq.o
obj-$(CONFIG_RESET_LPC18XX) += reset-lpc18xx.o
+obj-$(CONFIG_RESET_MCHP_SPARX5) += reset-microchip-sparx5.o
obj-$(CONFIG_RESET_MESON) += reset-meson.o
obj-$(CONFIG_RESET_MESON_AUDIO_ARB) += reset-meson-audio-arb.o
obj-$(CONFIG_RESET_NPCM) += reset-npcm.o
diff --git a/drivers/reset/reset-microchip-sparx5.c
b/drivers/reset/reset-microchip-sparx5.c
new file mode 100644
index ..0dbd2b6161ef
--- /dev/null
+++ b/drivers/reset/reset-microchip-sparx5.c
@@ -0,0 +1,120 @@
+// SPDX-License-Identifier: GPL-2.0+
+/* Microchip Sparx5 Switch Reset driver
+ *
+ * Copyright (c) 2020 Microchip Technology Inc. and its subsidiaries.
+ *
+ * The Sparx5 Chip Register Model can be browsed at this location:
+ * https://github.com/microchip-ung/sparx-5_reginfo
+ */
+#include
+#include
+#include
+#include
+#include
+#include
+
+#define PROTECT_REG0x84
+#define PROTECT_BITBIT(10)
+#define SOFT_RESET_REG 0x08
+#define SOFT_RESET_BIT BIT(1)
+
+struct mchp_reset_context {
+ struct regmap *cpu_ctrl;
+ struct regmap *gcb_ctrl;
+ struct reset_controller_dev rcdev;
+};
+
+static int sparx5_switch_reset(struct reset_controller_dev *rcdev,
+ unsigned long id)
+{
+ struct mchp_reset_context *ctx =
+ container_of(rcdev, struct mchp_reset_context, rcdev);
+ u32 val;
+
+ /* Make sure the core is PROTECTED from reset */
+ regmap_update_bits(ctx->cpu_ctrl, PROTECT_REG, PROTECT_BIT,
PROTECT_BIT);
+
+ /* Start soft reset */
+ regmap_write(ctx->gcb_ctrl, SOFT_RESET_REG, SOFT_RESET_BIT);
+
+ /* Wait for soft reset done */
+ return regmap_read_poll_timeout(ctx->gcb_ctrl, SOFT_RESET_REG, val,
+ (val & SOFT_RESET_BIT) == 0,
+ 1, 100);
+}
+
+static const struct reset_control_ops sparx5_reset_ops = {
+ .reset = sparx5_switch_reset,
+};
+
+static int mchp_sparx5_reset_probe(struct platform_device *pdev)
+{
+ struct device_node *dn = pdev->dev.of_node;
+ struct regmap *cpu_ctrl, *gcb_ctrl;
+ struct device *dev = &pdev->dev;
+ struct mchp_reset_context *ctx;
+ struct device_node *syscon_np;
+ int err;
+
+ ctx = devm_kzalloc(dev, sizeof(*ctx), GFP_KERNEL);
+ if (!ctx)
+ return -ENOMEM;
+
+ syscon_np = of_parse_phandle(dn, "cpu-syscon", 0);
+ if (!syscon_np)
+ return -ENODEV;
+ cpu_ctrl = syscon_node_to_regmap(syscon_np);
+ of_node_put(syscon_np);
+ if (IS_ERR(cpu_ctrl)) {
+ err = PTR_ERR(cpu_ctrl);
+ dev_err(dev, "No cpu-syscon map: %d\n", err);
+ return err;
+ }
+
+ syscon_np = of_parse_phandle(dn, "gcb-syscon", 0);
+ if (!syscon_np)
+ return -ENODEV;
+ gcb_ctrl = syscon_node_to_regmap(syscon_np);
+ of_node_put(syscon_np);
+ if (IS_ERR(gcb_ctrl)) {
+ err = PTR_ERR(gcb_ctrl);
+ dev_err(dev, "No gcb-syscon map: %d\n", err);
+ return err;
+ }
+
+ ctx->cpu_ctrl = cpu_ctrl;
+ ctx->gcb_ctrl = gcb_ctrl;
+
+ ctx->rcdev.owner = THIS_MODULE;
+ ctx->rcdev.nr_resets = 1;
+ ctx->rcdev.ops = &sparx5_reset_ops;
+ ctx->rcdev.of_node = dn;
+
+ return devm_reset_controller_register(dev, &ctx->rcdev);
+}
+
+static const struct of_device_id mchp_sparx5_reset_of_match[] = {
+ {
+ .compatible = "microchip,sparx5-switch-reset",
+ },
+ { /*sentinel*/ }
+
[PATCH v3 3/3] arm64: dts: reset: add microchip sparx5 switch reset driver
Signed-off-by: Steen Hegelund
---
arch/arm64/boot/dts/microchip/sparx5.dtsi | 14 +++---
1 file changed, 11 insertions(+), 3 deletions(-)
diff --git a/arch/arm64/boot/dts/microchip/sparx5.dtsi
b/arch/arm64/boot/dts/microchip/sparx5.dtsi
index 380281f312d8..4edbb9fcdce0 100644
--- a/arch/arm64/boot/dts/microchip/sparx5.dtsi
+++ b/arch/arm64/boot/dts/microchip/sparx5.dtsi
@@ -132,9 +132,17 @@ mux: mux-controller {
};
};
- reset@611010008 {
- compatible = "microchip,sparx5-chip-reset";
- reg = <0x6 0x11010008 0x4>;
+ gcb_ctrl: syscon@61101 {
+ compatible = "microchip,sparx5-gcb-syscon", "syscon";
+ reg = <0x6 0x1101 0x1>;
+ };
+
+ reset: reset-controller@0 {
+ compatible = "microchip,sparx5-switch-reset";
+ reg = <0x6 0x0 0x0>;
+ #reset-cells = <1>;
+ cpu-syscon = <&cpu_ctrl>;
+ gcb-syscon = <&gcb_ctrl>;
};
uart0: serial@60010 {
--
2.29.2
[PATCH v3 1/3] dt-bindings: reset: microchip sparx5 reset driver bindings
Signed-off-by: Steen Hegelund
---
.../bindings/reset/microchip,rst.yaml | 59 +++
1 file changed, 59 insertions(+)
create mode 100644 Documentation/devicetree/bindings/reset/microchip,rst.yaml
diff --git a/Documentation/devicetree/bindings/reset/microchip,rst.yaml
b/Documentation/devicetree/bindings/reset/microchip,rst.yaml
new file mode 100644
index ..af01016e246f
--- /dev/null
+++ b/Documentation/devicetree/bindings/reset/microchip,rst.yaml
@@ -0,0 +1,59 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: "http://devicetree.org/schemas/reset/microchip,rst.yaml#";
+$schema: "http://devicetree.org/meta-schemas/core.yaml#";
+
+title: Microchip Sparx5 Switch Reset Controller
+
+maintainers:
+ - Steen Hegelund
+ - Lars Povlsen
+
+description: |
+ The Microchip Sparx5 Switch provides reset control and implements the
following
+ functions
+- One Time Switch Core Reset (Soft Reset)
+
+properties:
+ $nodename:
+pattern: "^reset-controller@[0-9a-f]+$"
+
+ compatible:
+const: microchip,sparx5-switch-reset
+
+ reg:
+maxItems: 1
+
+ "#reset-cells":
+const: 1
+
+ cpu-syscon:
+$ref: "/schemas/types.yaml#/definitions/phandle"
+description: syscon used to access CPU reset
+maxItems: 1
+
+ gcb-syscon:
+$ref: "/schemas/types.yaml#/definitions/phandle"
+description: syscon used to access Global Control Block
+maxItems: 1
+
+required:
+ - compatible
+ - reg
+ - "#reset-cells"
+ - cpu-syscon
+ - gcb-syscon
+
+additionalProperties: false
+
+examples:
+ - |
+reset: reset-controller@0 {
+compatible = "microchip,sparx5-switch-reset";
+reg = <0x0 0x0>;
+#reset-cells = <1>;
+cpu-syscon = <&cpu_ctrl>;
+gcb-syscon = <&gcb_ctrl>;
+};
+
--
2.29.2
Re: [PATCH v12 2/4] phy: Add ethernet serdes configuration option
Hi Kishon,
On Fri, 2021-01-15 at 14:14 +0530, Kishon Vijay Abraham I wrote:
> EXTERNAL EMAIL: Do not click links or open attachments unless you
> know the content is safe
>
> Hi,
>
> On 07/01/21 2:49 pm, Steen Hegelund wrote:
> > Provide a new ethernet phy configuration structure, that
> > allow PHYs used for ethernet to be configured with
> > speed, media type and clock information.
> >
> > Signed-off-by: Lars Povlsen
> > Signed-off-by: Steen Hegelund
> > Reviewed-by: Andrew Lunn
> > ---
> > include/linux/phy/phy-ethernet-serdes.h | 30
> > +
> > include/linux/phy/phy.h | 4
> > 2 files changed, 34 insertions(+)
> > create mode 100644 include/linux/phy/phy-ethernet-serdes.h
> >
> > diff --git a/include/linux/phy/phy-ethernet-serdes.h
> > b/include/linux/phy/phy-ethernet-serdes.h
> > new file mode 100644
> > index ..d2462fadf179
> > --- /dev/null
> > +++ b/include/linux/phy/phy-ethernet-serdes.h
> > @@ -0,0 +1,30 @@
> > +/* SPDX-License-Identifier: (GPL-2.0 OR MIT) */
> > +/*
> > + * Microchip Sparx5 Ethernet SerDes driver
> > + *
> > + * Copyright (c) 2020 Microschip Inc
> > + */
> > +#ifndef __PHY_ETHERNET_SERDES_H_
> > +#define __PHY_ETHERNET_SERDES_H_
> > +
> > +#include
> > +
> > +enum ethernet_media_type {
> > + ETH_MEDIA_DEFAULT,
> > + ETH_MEDIA_SR,
> > + ETH_MEDIA_DAC,
> > +};
> > +
> > +/**
> > + * struct phy_configure_opts_eth_serdes - Ethernet SerDes This
> > structure is used
> > + * to represent the configuration state of a Ethernet Serdes PHY.
> > + * @speed: Speed of the serdes interface in Mbps
> > + * @media_type: Specifies which media the serdes will be using
> > + */
> > +struct phy_configure_opts_eth_serdes {
> > + u32 speed;
> > + enum ethernet_media_type media_type;
> > +};
>
> Is media type going to be determined dynamically by the Ethernet
> controller. If it's not determined dynamically, it shouldn't be in
> PHY
> ops but rather as a DT parameter.
Yes the media type is dynamic, as it will be determined by the feedback
from the attached SFP or DAC attached, which can be changed at any
time, so it is not static in a way that allows it to be part of the DT.
>
> phy_configure_opts is mostly used with things like DP where the
> controller probes the configurations supported by SERDES using the
> configure and validate ops. I don't think for Ethernet it is
> required.
>From what you explained I think the situation is very similar with the
Ethernet SerDes in that the actual media (and speed) is not known in
advance, but will be obtained "out-of-band" by the client and may
change at any point in time when the user changes the physical setup
(e.g cables).
>
> Thanks
> Kishon
>
> > +
> > +#endif
> > +
> > diff --git a/include/linux/phy/phy.h b/include/linux/phy/phy.h
> > index e435bdb0bab3..78ecb375cede 100644
> > --- a/include/linux/phy/phy.h
> > +++ b/include/linux/phy/phy.h
> > @@ -18,6 +18,7 @@
> >
> > #include
> > #include
> > +#include
> >
> > struct phy;
> >
> > @@ -49,11 +50,14 @@ enum phy_mode {
> > *
> > * @mipi_dphy: Configuration set applicable for phys
> > supporting
> > * the MIPI_DPHY phy mode.
> > + * @eth_serdes: Configuration set applicable for phys supporting
> > + * the ethernet serdes.
> > * @dp: Configuration set applicable for phys
> > supporting
> > * the DisplayPort protocol.
> > */
> > union phy_configure_opts {
> > struct phy_configure_opts_mipi_dphy mipi_dphy;
> > + struct phy_configure_opts_eth_serdes eth_serdes;
> > struct phy_configure_opts_dp dp;
> > };
> >
> >
BR
Steen
Re: [PATCH linux-next 1/1] phy: Sparx5 Eth SerDes: Use direct register operations
Hi Andrew,
On Tue, 2021-03-30 at 15:34 +0200, Andrew Lunn wrote:
> EXTERNAL EMAIL: Do not click links or open attachments unless you know the
> content is safe
>
> > > > +static int sparx5_sd25g28_apply_params(struct sparx5_serdes_macro
> > > > *macro,
> > > > +struct sparx5_sd25g28_params
> > > > *params)
> > > > {
> > > > - struct sparx5_serdes_regval item[] = {
> > >
> > > Could you just add const here, and then it is no longer on the stack?
> > >
> > >Andrew
> >
> > No it still counts against the stack even as a const structure.
>
> I'm surprised. Maybe it needs static as well?
>
> I'm just thinking you can get a much smaller patch if you don't need
> to modify the table, just add additional qualifiers.
>
>Andrew
I get your point, but the problem is that the initialization depends on the
input parameters: serdes
index, port index, media type, speed etc, so it cannot be made static, and
making it const still
uses the stack.
BR
Steen
[PATCH v7 0/3] Adding the Sparx5 Switch Reset Driver
This series provides the Microchip Sparx5 Switch Reset Driver The Sparx5 Switch SoC has a number of components that can be reset individually, but at least the Switch Core needs to be in a well defined state at power on, when any of the Sparx5 drivers starts to access the Switch Core, this reset driver is available. The reset driver is loaded early via the postcore_initcall interface, and will then be available for the other Sparx5 drivers (SGPIO, SwitchDev etc) that are loaded next, and the first of them to be loaded can perform the one-time Switch Core reset that is needed. The driver has protection so that the system busses, DDR controller, PCI-E and ARM A53 CPU and a few other subsystems are not touched by the reset. The Sparx5 Chip Register Model can be browsed at this location: https://github.com/microchip-ung/sparx-5_reginfo History: v6 -> v7 Use devm_platform_get_and_ioremap_resource to get the IO range. Rebase on v5.12-rc1 v5 -> v6 Using the existing CPU syscon for reset protection and add a small IO range for the GCB Reset Register. v4 -> v5 Changed the two syscons into IO ranges and updated the bindings to reflect this change. v3 -> v4 Added commit message descriptions v2 -> v3 Removed unused headers Renamed the reset controller dev member. Use regmap_read_poll_timeout instead of polling a function. Used two separate syscon entries in the binding Simplified the syscon error handling. Simplified the devm_reset_controller_register error handling. Moved the contents of the mchp_sparx5_reset_config function into the probe function. v1 -> v2 Removed debug prints Changed the error handling to save the error code before jumping. Steen Hegelund (3): dt-bindings: reset: microchip sparx5 reset driver bindings reset: mchp: sparx5: add switch reset driver arm64: dts: reset: add microchip sparx5 switch reset driver .../bindings/reset/microchip,rst.yaml | 58 +++ arch/arm64/boot/dts/microchip/sparx5.dtsi | 7 +- drivers/reset/Kconfig | 8 + drivers/reset/Makefile| 1 + drivers/reset/reset-microchip-sparx5.c| 146 ++ 5 files changed, 218 insertions(+), 2 deletions(-) create mode 100644 Documentation/devicetree/bindings/reset/microchip,rst.yaml create mode 100644 drivers/reset/reset-microchip-sparx5.c -- 2.30.1
[PATCH v7 1/3] dt-bindings: reset: microchip sparx5 reset driver bindings
Document the Sparx5 reset device driver bindings
The driver uses a syscon and an IO range on sparx5 for access to
the reset control and the reset status.
Signed-off-by: Steen Hegelund
---
.../bindings/reset/microchip,rst.yaml | 58 +++
1 file changed, 58 insertions(+)
create mode 100644 Documentation/devicetree/bindings/reset/microchip,rst.yaml
diff --git a/Documentation/devicetree/bindings/reset/microchip,rst.yaml
b/Documentation/devicetree/bindings/reset/microchip,rst.yaml
new file mode 100644
index ..370579aeeca1
--- /dev/null
+++ b/Documentation/devicetree/bindings/reset/microchip,rst.yaml
@@ -0,0 +1,58 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: "http://devicetree.org/schemas/reset/microchip,rst.yaml#";
+$schema: "http://devicetree.org/meta-schemas/core.yaml#";
+
+title: Microchip Sparx5 Switch Reset Controller
+
+maintainers:
+ - Steen Hegelund
+ - Lars Povlsen
+
+description: |
+ The Microchip Sparx5 Switch provides reset control and implements the
following
+ functions
+- One Time Switch Core Reset (Soft Reset)
+
+properties:
+ $nodename:
+pattern: "^reset-controller@[0-9a-f]+$"
+
+ compatible:
+const: microchip,sparx5-switch-reset
+
+ reg:
+items:
+ - description: global control block registers
+
+ reg-names:
+items:
+ - const: gcb
+
+ "#reset-cells":
+const: 1
+
+ cpu-syscon:
+$ref: "/schemas/types.yaml#/definitions/phandle"
+description: syscon used to access CPU reset
+
+required:
+ - compatible
+ - reg
+ - reg-names
+ - "#reset-cells"
+ - cpu-syscon
+
+additionalProperties: false
+
+examples:
+ - |
+reset: reset-controller@11010008 {
+compatible = "microchip,sparx5-switch-reset";
+reg = <0x11010008 0x4>;
+reg-names = "gcb";
+#reset-cells = <1>;
+cpu-syscon = <&cpu_ctrl>;
+};
+
--
2.30.1
[PATCH v7 2/3] reset: mchp: sparx5: add switch reset driver
The Sparx5 Switch SoC has a number of components that can be reset
indiviually, but at least the Switch Core needs to be in a well defined
state at power on, when any of the Sparx5 drivers starts to access the
Switch Core, this reset driver is available.
The reset driver is loaded early via the postcore_initcall interface, and
will then be available for the other Sparx5 drivers (SGPIO, SwitchDev etc)
that are loaded next, and the first of them to be loaded can perform the
one-time Switch Core reset that is needed.
The driver has protection so that the system busses, DDR controller, PCI-E
and ARM A53 CPU and a few other subsystems are not touched by the reset.
Signed-off-by: Steen Hegelund
---
drivers/reset/Kconfig | 8 ++
drivers/reset/Makefile | 1 +
drivers/reset/reset-microchip-sparx5.c | 146 +
3 files changed, 155 insertions(+)
create mode 100644 drivers/reset/reset-microchip-sparx5.c
diff --git a/drivers/reset/Kconfig b/drivers/reset/Kconfig
index 4171c6f76385..c26798092ccf 100644
--- a/drivers/reset/Kconfig
+++ b/drivers/reset/Kconfig
@@ -111,6 +111,14 @@ config RESET_LPC18XX
help
This enables the reset controller driver for NXP LPC18xx/43xx SoCs.
+config RESET_MCHP_SPARX5
+ bool "Microchip Sparx5 reset driver"
+ depends on HAS_IOMEM || COMPILE_TEST
+ default y if SPARX5_SWITCH
+ select MFD_SYSCON
+ help
+ This driver supports switch core reset for the Microchip Sparx5 SoC.
+
config RESET_MESON
tristate "Meson Reset Driver"
depends on ARCH_MESON || COMPILE_TEST
diff --git a/drivers/reset/Makefile b/drivers/reset/Makefile
index 65a118a91b27..c1d6aa9b1b52 100644
--- a/drivers/reset/Makefile
+++ b/drivers/reset/Makefile
@@ -16,6 +16,7 @@ obj-$(CONFIG_RESET_INTEL_GW) += reset-intel-gw.o
obj-$(CONFIG_RESET_K210) += reset-k210.o
obj-$(CONFIG_RESET_LANTIQ) += reset-lantiq.o
obj-$(CONFIG_RESET_LPC18XX) += reset-lpc18xx.o
+obj-$(CONFIG_RESET_MCHP_SPARX5) += reset-microchip-sparx5.o
obj-$(CONFIG_RESET_MESON) += reset-meson.o
obj-$(CONFIG_RESET_MESON_AUDIO_ARB) += reset-meson-audio-arb.o
obj-$(CONFIG_RESET_NPCM) += reset-npcm.o
diff --git a/drivers/reset/reset-microchip-sparx5.c
b/drivers/reset/reset-microchip-sparx5.c
new file mode 100644
index ..cff39a643a14
--- /dev/null
+++ b/drivers/reset/reset-microchip-sparx5.c
@@ -0,0 +1,146 @@
+// SPDX-License-Identifier: GPL-2.0+
+/* Microchip Sparx5 Switch Reset driver
+ *
+ * Copyright (c) 2020 Microchip Technology Inc. and its subsidiaries.
+ *
+ * The Sparx5 Chip Register Model can be browsed at this location:
+ * https://github.com/microchip-ung/sparx-5_reginfo
+ */
+#include
+#include
+#include
+#include
+#include
+#include
+
+#define PROTECT_REG0x84
+#define PROTECT_BITBIT(10)
+#define SOFT_RESET_REG 0x00
+#define SOFT_RESET_BIT BIT(1)
+
+struct mchp_reset_context {
+ struct regmap *cpu_ctrl;
+ struct regmap *gcb_ctrl;
+ struct reset_controller_dev rcdev;
+};
+
+static struct regmap_config sparx5_reset_regmap_config = {
+ .reg_bits = 32,
+ .val_bits = 32,
+ .reg_stride = 4,
+};
+
+static int sparx5_switch_reset(struct reset_controller_dev *rcdev,
+ unsigned long id)
+{
+ struct mchp_reset_context *ctx =
+ container_of(rcdev, struct mchp_reset_context, rcdev);
+ u32 val;
+
+ /* Make sure the core is PROTECTED from reset */
+ regmap_update_bits(ctx->cpu_ctrl, PROTECT_REG, PROTECT_BIT,
PROTECT_BIT);
+
+ /* Start soft reset */
+ regmap_write(ctx->gcb_ctrl, SOFT_RESET_REG, SOFT_RESET_BIT);
+
+ /* Wait for soft reset done */
+ return regmap_read_poll_timeout(ctx->gcb_ctrl, SOFT_RESET_REG, val,
+ (val & SOFT_RESET_BIT) == 0,
+ 1, 100);
+}
+
+static const struct reset_control_ops sparx5_reset_ops = {
+ .reset = sparx5_switch_reset,
+};
+
+static int mchp_sparx5_map_syscon(struct platform_device *pdev, char *name,
+ struct regmap **target)
+{
+ struct device_node *syscon_np;
+ struct regmap *regmap;
+ int err;
+
+ syscon_np = of_parse_phandle(pdev->dev.of_node, name, 0);
+ if (!syscon_np)
+ return -ENODEV;
+ regmap = syscon_node_to_regmap(syscon_np);
+ of_node_put(syscon_np);
+ if (IS_ERR(regmap)) {
+ err = PTR_ERR(regmap);
+ dev_err(&pdev->dev, "No '%s' map: %d\n", name, err);
+ return err;
+ }
+ *target = regmap;
+ return 0;
+}
+
+static int mchp_sparx5_map_io(struct platform_device *pdev, int index,
+ struct regmap **target)
+{
+ struct resource *res;
+ struct regmap *map;
+ void __iomem *mem;
+
+
[PATCH v7 3/3] arm64: dts: reset: add microchip sparx5 switch reset driver
This provides reset driver support for the Microchip Sparx5 PCB134 and
PCB135 reference boards.
Signed-off-by: Steen Hegelund
---
arch/arm64/boot/dts/microchip/sparx5.dtsi | 7 +--
1 file changed, 5 insertions(+), 2 deletions(-)
diff --git a/arch/arm64/boot/dts/microchip/sparx5.dtsi
b/arch/arm64/boot/dts/microchip/sparx5.dtsi
index 380281f312d8..dc3ada5cf9fc 100644
--- a/arch/arm64/boot/dts/microchip/sparx5.dtsi
+++ b/arch/arm64/boot/dts/microchip/sparx5.dtsi
@@ -132,9 +132,12 @@ mux: mux-controller {
};
};
- reset@611010008 {
- compatible = "microchip,sparx5-chip-reset";
+ reset: reset-controller@611010008 {
+ compatible = "microchip,sparx5-switch-reset";
reg = <0x6 0x11010008 0x4>;
+ reg-names = "gcb";
+ #reset-cells = <1>;
+ cpu-syscon = <&cpu_ctrl>;
};
uart0: serial@60010 {
--
2.30.1
Re: [PATCH v15 0/4] Adding the Sparx5 Serdes driver
Hi Jacub, On Mon, 2021-03-15 at 10:26 -0700, Jakub Kicinski wrote: > EXTERNAL EMAIL: Do not click links or open attachments unless you know the > content is safe > > On Mon, 15 Mar 2021 16:04:24 +0100 Steen Hegelund wrote: > > Hi Kishon, Vinod, Andrew, Jacub, and David, > > > > I just wanted to know if you think that the Generic PHY subsystem might > > not be the right place for this Ethernet SerDes PHY driver after all. > > > > Originally I chose this subsystem for historic reasons: The > > Microchip/Microsemi Ocelot SerDes driver was added here when it was > > upstreamed. > > On the other hand the Ocelot Serdes can do both PCIe and Ethernet, so > > it might fit the signature of a generic PHY better. > > Are you saying this PHY is Ethernet only? Yes this particular PHY is Ethernet only (but the Sparx5 also has a separate PCI PHY). > > > At the moment the acceptance of the Sparx5 Serdes driver is blocking us > > from adding the Sparx5 SwitchDev driver (to net), so it is really > > important for us to resolve which subsystem the Serdes driver belongs > > to. > > > > I am very much looking forward to your response. > > FWIW even if this is merged via gen phy subsystem we can pull it into > net-next as well to unblock your other work in this dev cycle. You just > need to send the patches as a pull request, based on merge-base between > the gen phy tree and net-next. -- BR Steen -=-=-=-=-=-=-=-=-=-=-=-=-=-= steen.hegel...@microchip.com
Re: [PATCH v15 0/4] Adding the Sparx5 Serdes driver
Hi Vinod, On Tue, 2021-03-16 at 10:23 +0530, Vinod Koul wrote: > EXTERNAL EMAIL: Do not click links or open attachments unless you know the > content is safe > > Hello Steen, > > On 15-03-21, 16:04, Steen Hegelund wrote: > > Hi Kishon, Vinod, Andrew, Jacub, and David, > > > > I just wanted to know if you think that the Generic PHY subsystem might > > not be the right place for this Ethernet SerDes PHY driver after all. > > > > Originally I chose this subsystem for historic reasons: The > > Microchip/Microsemi Ocelot SerDes driver was added here when it was > > upstreamed. > > On the other hand the Ocelot Serdes can do both PCIe and Ethernet, so > > it might fit the signature of a generic PHY better. > > > > At the moment the acceptance of the Sparx5 Serdes driver is blocking us > > from adding the Sparx5 SwitchDev driver (to net), so it is really > > important for us to resolve which subsystem the Serdes driver belongs > > to. > > > > I am very much looking forward to your response. > > Generic PHY IMO is the right place for this series, I shall review it > shortly and do the needful. I have asked Kishon to check the new phy API > and ack it... > > Thanks > -- > ~Vinod Thank you very much for the confirmation. BR Steen
Re: [PATCH v7 3/3] arm64: dts: reset: add microchip sparx5 switch reset driver
Hi Rob,
On Mon, 2021-03-08 at 12:59 -0700, Rob Herring wrote:
> EXTERNAL EMAIL: Do not click links or open attachments unless you
> know the content is safe
>
> On Wed, Mar 03, 2021 at 09:11:58AM +0100, Steen Hegelund wrote:
> > This provides reset driver support for the Microchip Sparx5 PCB134
> > and
> > PCB135 reference boards.
>
> This still looks like an incompatible change with no explanation.
>
> What happens on an old kernel that expects "microchip,sparx5-chip-
> reset"
> and doesn't understand "microchip,sparx5-switch-reset"?
Sorry about forgetting that item.
I will add a note to say that this is an incompatible change.
In practice, I do not think the reset driver has really been taken into
use yet.
>
> >
> > Signed-off-by: Steen Hegelund
> > ---
> > arch/arm64/boot/dts/microchip/sparx5.dtsi | 7 +--
> > 1 file changed, 5 insertions(+), 2 deletions(-)
> >
> > diff --git a/arch/arm64/boot/dts/microchip/sparx5.dtsi
> > b/arch/arm64/boot/dts/microchip/sparx5.dtsi
> > index 380281f312d8..dc3ada5cf9fc 100644
> > --- a/arch/arm64/boot/dts/microchip/sparx5.dtsi
> > +++ b/arch/arm64/boot/dts/microchip/sparx5.dtsi
> > @@ -132,9 +132,12 @@ mux: mux-controller {
> > };
> > };
> >
> > - reset@611010008 {
> > - compatible = "microchip,sparx5-chip-reset";
> > + reset: reset-controller@611010008 {
> > + compatible = "microchip,sparx5-switch-reset";
> > reg = <0x6 0x11010008 0x4>;
> > + reg-names = "gcb";
> > + #reset-cells = <1>;
> > + cpu-syscon = <&cpu_ctrl>;
> > };
> >
> > uart0: serial@60010 {
> > --
> > 2.30.1
> >
--
BR
Steen
-=-=-=-=-=-=-=-=-=-=-=-=-=-=
steen.hegel...@microchip.com
[PATCH v8 0/3] Adding the Sparx5 Switch Reset Driver
This series provides the Microchip Sparx5 Switch Reset Driver The Sparx5 Switch SoC has a number of components that can be reset individually, but at least the Switch Core needs to be in a well defined state at power on, when any of the Sparx5 drivers starts to access the Switch Core, this reset driver is available. The reset driver is loaded early via the postcore_initcall interface, and will then be available for the other Sparx5 drivers (SGPIO, SwitchDev etc) that are loaded next, and the first of them to be loaded can perform the one-time Switch Core reset that is needed. The driver has protection so that the system busses, DDR controller, PCI-E and ARM A53 CPU and a few other subsystems are not touched by the reset. Sparx5 will no longer use the existing Ocelot chip reset driver, but use this new switch reset driver as it has the reset controller interface that allows the first client to perform the reset on behalf of all the Sparx5 component drivers. The Sparx5 Chip Register Model can be browsed at this location: https://github.com/microchip-ung/sparx-5_reginfo and the datasheet is available here: https://ww1.microchip.com/downloads/en/DeviceDoc/SparX-5_Family_L2L3_Enterprise_10G_Ethernet_Switches_Datasheet_3822B.pdf History: v7 -> v8 Updated the commit descriptions to explain the change from using the existing Ocelot chip reset driver to use a new switch reset driver. v6 -> v7 Use devm_platform_get_and_ioremap_resource to get the IO range. Rebase on v5.12-rc1 v5 -> v6 Using the existing CPU syscon for reset protection and add a small IO range for the GCB Reset Register. v4 -> v5 Changed the two syscons into IO ranges and updated the bindings to reflect this change. v3 -> v4 Added commit message descriptions v2 -> v3 Removed unused headers Renamed the reset controller dev member. Use regmap_read_poll_timeout instead of polling a function. Used two separate syscon entries in the binding Simplified the syscon error handling. Simplified the devm_reset_controller_register error handling. Moved the contents of the mchp_sparx5_reset_config function into the probe function. v1 -> v2 Removed debug prints Changed the error handling to save the error code before jumping. Steen Hegelund (3): dt-bindings: reset: microchip sparx5 reset driver bindings reset: mchp: sparx5: add switch reset driver arm64: dts: reset: add microchip sparx5 switch reset driver .../bindings/reset/microchip,rst.yaml | 58 +++ arch/arm64/boot/dts/microchip/sparx5.dtsi | 7 +- drivers/reset/Kconfig | 8 + drivers/reset/Makefile| 1 + drivers/reset/reset-microchip-sparx5.c| 146 ++ 5 files changed, 218 insertions(+), 2 deletions(-) create mode 100644 Documentation/devicetree/bindings/reset/microchip,rst.yaml create mode 100644 drivers/reset/reset-microchip-sparx5.c -- 2.30.2
[PATCH v8 1/3] dt-bindings: reset: microchip sparx5 reset driver bindings
Document the Sparx5 reset device driver bindings
The driver uses a syscon and an IO range on sparx5 for access to
the reset control and the reset status.
Sparx5 will no longer use the existing Ocelot chip reset driver, but use
this new switch reset driver as it has the reset controller interface that
allows the first client to perform the reset on behalf of all the Sparx5
component drivers.
Signed-off-by: Steen Hegelund
---
.../bindings/reset/microchip,rst.yaml | 58 +++
1 file changed, 58 insertions(+)
create mode 100644 Documentation/devicetree/bindings/reset/microchip,rst.yaml
diff --git a/Documentation/devicetree/bindings/reset/microchip,rst.yaml
b/Documentation/devicetree/bindings/reset/microchip,rst.yaml
new file mode 100644
index ..370579aeeca1
--- /dev/null
+++ b/Documentation/devicetree/bindings/reset/microchip,rst.yaml
@@ -0,0 +1,58 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: "http://devicetree.org/schemas/reset/microchip,rst.yaml#";
+$schema: "http://devicetree.org/meta-schemas/core.yaml#";
+
+title: Microchip Sparx5 Switch Reset Controller
+
+maintainers:
+ - Steen Hegelund
+ - Lars Povlsen
+
+description: |
+ The Microchip Sparx5 Switch provides reset control and implements the
following
+ functions
+- One Time Switch Core Reset (Soft Reset)
+
+properties:
+ $nodename:
+pattern: "^reset-controller@[0-9a-f]+$"
+
+ compatible:
+const: microchip,sparx5-switch-reset
+
+ reg:
+items:
+ - description: global control block registers
+
+ reg-names:
+items:
+ - const: gcb
+
+ "#reset-cells":
+const: 1
+
+ cpu-syscon:
+$ref: "/schemas/types.yaml#/definitions/phandle"
+description: syscon used to access CPU reset
+
+required:
+ - compatible
+ - reg
+ - reg-names
+ - "#reset-cells"
+ - cpu-syscon
+
+additionalProperties: false
+
+examples:
+ - |
+reset: reset-controller@11010008 {
+compatible = "microchip,sparx5-switch-reset";
+reg = <0x11010008 0x4>;
+reg-names = "gcb";
+#reset-cells = <1>;
+cpu-syscon = <&cpu_ctrl>;
+};
+
--
2.30.2
[PATCH v8 3/3] arm64: dts: reset: add microchip sparx5 switch reset driver
This provides reset driver support for the Microchip Sparx5 PCB134 and
PCB135 reference boards.
The Sparx5 Switch will no longer use the Ocelot Chip Reset Driver (with the
compatible string "microchip,sparx5-chip-reset"), but use a separate driver
that exposes a reset controller interface and has the compatiple string
"microchip,sparx5-switch-reset".
Eventually the Sparx5 reset support will be removed from the Ocelot chip
reset driver.
Signed-off-by: Steen Hegelund
Reviewed-by: Alexandre Belloni
---
arch/arm64/boot/dts/microchip/sparx5.dtsi | 7 +--
1 file changed, 5 insertions(+), 2 deletions(-)
diff --git a/arch/arm64/boot/dts/microchip/sparx5.dtsi
b/arch/arm64/boot/dts/microchip/sparx5.dtsi
index 380281f312d8..dc3ada5cf9fc 100644
--- a/arch/arm64/boot/dts/microchip/sparx5.dtsi
+++ b/arch/arm64/boot/dts/microchip/sparx5.dtsi
@@ -132,9 +132,12 @@ mux: mux-controller {
};
};
- reset@611010008 {
- compatible = "microchip,sparx5-chip-reset";
+ reset: reset-controller@611010008 {
+ compatible = "microchip,sparx5-switch-reset";
reg = <0x6 0x11010008 0x4>;
+ reg-names = "gcb";
+ #reset-cells = <1>;
+ cpu-syscon = <&cpu_ctrl>;
};
uart0: serial@60010 {
--
2.30.2
[PATCH v8 2/3] reset: mchp: sparx5: add switch reset driver
The Sparx5 Switch SoC has a number of components that can be reset
indiviually, but at least the Switch Core needs to be in a well defined
state at power on, when any of the Sparx5 drivers starts to access the
Switch Core, this reset driver is available.
The reset driver is loaded early via the postcore_initcall interface, and
will then be available for the other Sparx5 drivers (SGPIO, SwitchDev etc)
that are loaded next, and the first of them to be loaded can perform the
one-time Switch Core reset that is needed.
The driver has protection so that the system busses, DDR controller, PCI-E
and ARM A53 CPU and a few other subsystems are not touched by the reset.
Signed-off-by: Steen Hegelund
Reviewed-by: Alexandre Belloni
---
drivers/reset/Kconfig | 8 ++
drivers/reset/Makefile | 1 +
drivers/reset/reset-microchip-sparx5.c | 146 +
3 files changed, 155 insertions(+)
create mode 100644 drivers/reset/reset-microchip-sparx5.c
diff --git a/drivers/reset/Kconfig b/drivers/reset/Kconfig
index 4171c6f76385..c26798092ccf 100644
--- a/drivers/reset/Kconfig
+++ b/drivers/reset/Kconfig
@@ -111,6 +111,14 @@ config RESET_LPC18XX
help
This enables the reset controller driver for NXP LPC18xx/43xx SoCs.
+config RESET_MCHP_SPARX5
+ bool "Microchip Sparx5 reset driver"
+ depends on HAS_IOMEM || COMPILE_TEST
+ default y if SPARX5_SWITCH
+ select MFD_SYSCON
+ help
+ This driver supports switch core reset for the Microchip Sparx5 SoC.
+
config RESET_MESON
tristate "Meson Reset Driver"
depends on ARCH_MESON || COMPILE_TEST
diff --git a/drivers/reset/Makefile b/drivers/reset/Makefile
index 65a118a91b27..c1d6aa9b1b52 100644
--- a/drivers/reset/Makefile
+++ b/drivers/reset/Makefile
@@ -16,6 +16,7 @@ obj-$(CONFIG_RESET_INTEL_GW) += reset-intel-gw.o
obj-$(CONFIG_RESET_K210) += reset-k210.o
obj-$(CONFIG_RESET_LANTIQ) += reset-lantiq.o
obj-$(CONFIG_RESET_LPC18XX) += reset-lpc18xx.o
+obj-$(CONFIG_RESET_MCHP_SPARX5) += reset-microchip-sparx5.o
obj-$(CONFIG_RESET_MESON) += reset-meson.o
obj-$(CONFIG_RESET_MESON_AUDIO_ARB) += reset-meson-audio-arb.o
obj-$(CONFIG_RESET_NPCM) += reset-npcm.o
diff --git a/drivers/reset/reset-microchip-sparx5.c
b/drivers/reset/reset-microchip-sparx5.c
new file mode 100644
index ..cff39a643a14
--- /dev/null
+++ b/drivers/reset/reset-microchip-sparx5.c
@@ -0,0 +1,146 @@
+// SPDX-License-Identifier: GPL-2.0+
+/* Microchip Sparx5 Switch Reset driver
+ *
+ * Copyright (c) 2020 Microchip Technology Inc. and its subsidiaries.
+ *
+ * The Sparx5 Chip Register Model can be browsed at this location:
+ * https://github.com/microchip-ung/sparx-5_reginfo
+ */
+#include
+#include
+#include
+#include
+#include
+#include
+
+#define PROTECT_REG0x84
+#define PROTECT_BITBIT(10)
+#define SOFT_RESET_REG 0x00
+#define SOFT_RESET_BIT BIT(1)
+
+struct mchp_reset_context {
+ struct regmap *cpu_ctrl;
+ struct regmap *gcb_ctrl;
+ struct reset_controller_dev rcdev;
+};
+
+static struct regmap_config sparx5_reset_regmap_config = {
+ .reg_bits = 32,
+ .val_bits = 32,
+ .reg_stride = 4,
+};
+
+static int sparx5_switch_reset(struct reset_controller_dev *rcdev,
+ unsigned long id)
+{
+ struct mchp_reset_context *ctx =
+ container_of(rcdev, struct mchp_reset_context, rcdev);
+ u32 val;
+
+ /* Make sure the core is PROTECTED from reset */
+ regmap_update_bits(ctx->cpu_ctrl, PROTECT_REG, PROTECT_BIT,
PROTECT_BIT);
+
+ /* Start soft reset */
+ regmap_write(ctx->gcb_ctrl, SOFT_RESET_REG, SOFT_RESET_BIT);
+
+ /* Wait for soft reset done */
+ return regmap_read_poll_timeout(ctx->gcb_ctrl, SOFT_RESET_REG, val,
+ (val & SOFT_RESET_BIT) == 0,
+ 1, 100);
+}
+
+static const struct reset_control_ops sparx5_reset_ops = {
+ .reset = sparx5_switch_reset,
+};
+
+static int mchp_sparx5_map_syscon(struct platform_device *pdev, char *name,
+ struct regmap **target)
+{
+ struct device_node *syscon_np;
+ struct regmap *regmap;
+ int err;
+
+ syscon_np = of_parse_phandle(pdev->dev.of_node, name, 0);
+ if (!syscon_np)
+ return -ENODEV;
+ regmap = syscon_node_to_regmap(syscon_np);
+ of_node_put(syscon_np);
+ if (IS_ERR(regmap)) {
+ err = PTR_ERR(regmap);
+ dev_err(&pdev->dev, "No '%s' map: %d\n", name, err);
+ return err;
+ }
+ *target = regmap;
+ return 0;
+}
+
+static int mchp_sparx5_map_io(struct platform_device *pdev, int index,
+ struct regmap **target)
+{
+ struct resource *res;
+
[PATCH linux-next 0/1] Sparx5 SerDes: Fixed stack frame size warning
- The SerDes driver changes its table based register operations into direct register operations to avoid the large stack footprint reported by a kernel robot. - The 25g reset operation was changed slightly to make it equivalent to the 20g reset operation. Steen Hegelund (1): phy: Sparx5 Eth SerDes: Use direct register operations drivers/phy/microchip/sparx5_serdes.c | 1869 + 1 file changed, 951 insertions(+), 918 deletions(-) -- 2.31.1
[PATCH linux-next 1/1] phy: Sparx5 Eth SerDes: Use direct register operations
Use direct register operations instead of a table of register
information to lower the stack usage.
Signed-off-by: Steen Hegelund
Reported-by: kernel test robot
---
drivers/phy/microchip/sparx5_serdes.c | 1869 +
1 file changed, 951 insertions(+), 918 deletions(-)
diff --git a/drivers/phy/microchip/sparx5_serdes.c
b/drivers/phy/microchip/sparx5_serdes.c
index 06bcf0c166cf..43de68a62c2f 100644
--- a/drivers/phy/microchip/sparx5_serdes.c
+++ b/drivers/phy/microchip/sparx5_serdes.c
@@ -343,12 +343,6 @@ struct sparx5_sd10g28_params {
u8 fx_100;
};
-struct sparx5_serdes_regval {
- u32 value;
- u32 mask;
- void __iomem *addr;
-};
-
static struct sparx5_sd25g28_media_preset media_presets_25g[] = {
{ /* ETH_MEDIA_DEFAULT */
.cfg_en_adv = 0,
@@ -945,431 +939,411 @@ static void sparx5_sd25g28_reset(void __iomem *regs[],
}
}
-static int sparx5_sd25g28_apply_params(struct device *dev,
- void __iomem *regs[],
- struct sparx5_sd25g28_params *params,
- u32 sd_index)
+static int sparx5_sd25g28_apply_params(struct sparx5_serdes_macro *macro,
+ struct sparx5_sd25g28_params *params)
{
- struct sparx5_serdes_regval item[] = {
- {
- SD_LANE_25G_SD_LANE_CFG_MACRO_RST_SET(1),
- SD_LANE_25G_SD_LANE_CFG_MACRO_RST,
- sdx5_addr(regs, SD_LANE_25G_SD_LANE_CFG(sd_index))
- },
- {
- SD25G_LANE_CMU_FF_REGISTER_TABLE_INDEX_SET(0xFF),
- SD25G_LANE_CMU_FF_REGISTER_TABLE_INDEX,
- sdx5_addr(regs, SD25G_LANE_CMU_FF(sd_index))
- },
- {
- SD25G_LANE_CMU_1A_R_DWIDTHCTRL_FROM_HWT_SET
- (params->r_d_width_ctrl_from_hwt) |
-
SD25G_LANE_CMU_1A_R_REG_MANUAL_SET(params->r_reg_manual),
- SD25G_LANE_CMU_1A_R_DWIDTHCTRL_FROM_HWT |
- SD25G_LANE_CMU_1A_R_REG_MANUAL,
- sdx5_addr(regs, SD25G_LANE_CMU_1A(sd_index))
- },
- {
- SD25G_LANE_CMU_31_CFG_COMMON_RESERVE_7_0_SET
- (params->cfg_common_reserve_7_0),
- SD25G_LANE_CMU_31_CFG_COMMON_RESERVE_7_0,
- sdx5_addr(regs, SD25G_LANE_CMU_31(sd_index))
- },
- {
-
SD25G_LANE_CMU_09_CFG_EN_DUMMY_SET(params->cfg_en_dummy),
- SD25G_LANE_CMU_09_CFG_EN_DUMMY,
- sdx5_addr(regs, SD25G_LANE_CMU_09(sd_index))
- },
- {
-
SD25G_LANE_CMU_13_CFG_PLL_RESERVE_3_0_SET(params->cfg_pll_reserve_3_0),
- SD25G_LANE_CMU_13_CFG_PLL_RESERVE_3_0,
- sdx5_addr(regs, SD25G_LANE_CMU_13(sd_index))
- },
- {
-
SD25G_LANE_CMU_40_L0_CFG_TXCAL_EN_SET(params->l0_cfg_txcal_en),
- SD25G_LANE_CMU_40_L0_CFG_TXCAL_EN,
- sdx5_addr(regs, SD25G_LANE_CMU_40(sd_index))
- },
- {
- SD25G_LANE_CMU_46_L0_CFG_TX_RESERVE_15_8_SET
- (params->l0_cfg_tx_reserve_15_8),
- SD25G_LANE_CMU_46_L0_CFG_TX_RESERVE_15_8,
- sdx5_addr(regs, SD25G_LANE_CMU_46(sd_index))
- },
- {
-
SD25G_LANE_CMU_45_L0_CFG_TX_RESERVE_7_0_SET(params->l0_cfg_tx_reserve_7_0),
- SD25G_LANE_CMU_45_L0_CFG_TX_RESERVE_7_0,
- sdx5_addr(regs, SD25G_LANE_CMU_45(sd_index))
- },
- {
- SD25G_LANE_CMU_0B_CFG_VCO_CAL_RESETN_SET(0),
- SD25G_LANE_CMU_0B_CFG_VCO_CAL_RESETN,
- sdx5_addr(regs, SD25G_LANE_CMU_0B(sd_index))
- },
- {
- SD25G_LANE_CMU_0B_CFG_VCO_CAL_RESETN_SET(1),
- SD25G_LANE_CMU_0B_CFG_VCO_CAL_RESETN,
- sdx5_addr(regs, SD25G_LANE_CMU_0B(sd_index))
- },
- {
- SD25G_LANE_CMU_19_R_CK_RESETB_SET(0),
- SD25G_LANE_CMU_19_R_CK_RESETB,
- sdx5_addr(regs, SD25G_LANE_CMU_19(sd_index))
- },
- {
- SD25G_LANE_CMU_19_R_CK_RESETB_SET(1),
- SD25G_LANE_CMU_19_R_CK_RESETB,
- sdx5_addr(regs, SD25G_LANE_CMU_19(sd_index))
- },
- {
- SD25G_LANE
Re: [PATCH v8 0/3] Adding the Sparx5 Switch Reset Driver
Hi Philipp, I just wanted to know if there are any outstanding items, or you think that the driver is acceptable as it is now? BR Steen On Tue, 2021-03-16 at 10:08 +0100, Steen Hegelund wrote: > This series provides the Microchip Sparx5 Switch Reset Driver > > The Sparx5 Switch SoC has a number of components that can be reset > individually, but at least the Switch Core needs to be in a well defined > state at power on, when any of the Sparx5 drivers starts to access the > Switch Core, this reset driver is available. > > The reset driver is loaded early via the postcore_initcall interface, and > will then be available for the other Sparx5 drivers (SGPIO, SwitchDev etc) > that are loaded next, and the first of them to be loaded can perform the > one-time Switch Core reset that is needed. > > The driver has protection so that the system busses, DDR controller, PCI-E > and ARM A53 CPU and a few other subsystems are not touched by the reset. > > Sparx5 will no longer use the existing Ocelot chip reset driver, but use > this new switch reset driver as it has the reset controller interface that > allows the first client to perform the reset on behalf of all the Sparx5 > component drivers. > > The Sparx5 Chip Register Model can be browsed at this location: > https://github.com/microchip-ung/sparx-5_reginfo > and the datasheet is available here: > https://ww1.microchip.com/downloads/en/DeviceDoc/SparX-5_Family_L2L3_Enterprise_10G_Ethernet_Switches_Datasheet_3822B.pdf > > History: > > v7 -> v8 Updated the commit descriptions to explain the change from using > the existing Ocelot chip reset driver to use a new switch reset > driver. > > v6 -> v7 Use devm_platform_get_and_ioremap_resource to get the IO range. > Rebase on v5.12-rc1 > > v5 -> v6 Using the existing CPU syscon for reset protection and add a small > IO range for the GCB Reset Register. > > v4 -> v5 Changed the two syscons into IO ranges and updated the bindings to > reflect this change. > > v3 -> v4 Added commit message descriptions > > v2 -> v3 Removed unused headers > Renamed the reset controller dev member. > Use regmap_read_poll_timeout instead of polling a function. > Used two separate syscon entries in the binding > Simplified the syscon error handling. > Simplified the devm_reset_controller_register error handling. > Moved the contents of the mchp_sparx5_reset_config function into > the probe function. > > v1 -> v2 Removed debug prints > Changed the error handling to save the error code before jumping. > > Steen Hegelund (3): > dt-bindings: reset: microchip sparx5 reset driver bindings > reset: mchp: sparx5: add switch reset driver > arm64: dts: reset: add microchip sparx5 switch reset driver > > .../bindings/reset/microchip,rst.yaml | 58 +++ > arch/arm64/boot/dts/microchip/sparx5.dtsi | 7 +- > drivers/reset/Kconfig | 8 + > drivers/reset/Makefile| 1 + > drivers/reset/reset-microchip-sparx5.c| 146 ++ > 5 files changed, 218 insertions(+), 2 deletions(-) > create mode 100644 Documentation/devicetree/bindings/reset/microchip,rst.yaml > create mode 100644 drivers/reset/reset-microchip-sparx5.c >
[PATCH linux-next v2 0/1] Sparx5 SerDes: Fixed stack frame size warning
History: v2: - Corrected a 10g lane reset signal. v1: - The SerDes driver changes its table based register operations into direct register operations to avoid the large stack footprint reported by a kernel robot. - The 25g reset operation was changed slightly to make it equivalent to the 20g reset operation. Steen Hegelund (1): phy: Sparx5 Eth SerDes: Use direct register operations drivers/phy/microchip/sparx5_serdes.c | 1869 + 1 file changed, 951 insertions(+), 918 deletions(-) -- 2.31.1
[PATCH linux-next v2 1/1] phy: Sparx5 Eth SerDes: Use direct register operations
Use direct register operations instead of a table of register
information to lower the stack usage.
Signed-off-by: Steen Hegelund
Reported-by: kernel test robot
---
drivers/phy/microchip/sparx5_serdes.c | 1869 +
1 file changed, 951 insertions(+), 918 deletions(-)
diff --git a/drivers/phy/microchip/sparx5_serdes.c
b/drivers/phy/microchip/sparx5_serdes.c
index 06bcf0c166cf..338a4220b45f 100644
--- a/drivers/phy/microchip/sparx5_serdes.c
+++ b/drivers/phy/microchip/sparx5_serdes.c
@@ -343,12 +343,6 @@ struct sparx5_sd10g28_params {
u8 fx_100;
};
-struct sparx5_serdes_regval {
- u32 value;
- u32 mask;
- void __iomem *addr;
-};
-
static struct sparx5_sd25g28_media_preset media_presets_25g[] = {
{ /* ETH_MEDIA_DEFAULT */
.cfg_en_adv = 0,
@@ -945,431 +939,411 @@ static void sparx5_sd25g28_reset(void __iomem *regs[],
}
}
-static int sparx5_sd25g28_apply_params(struct device *dev,
- void __iomem *regs[],
- struct sparx5_sd25g28_params *params,
- u32 sd_index)
+static int sparx5_sd25g28_apply_params(struct sparx5_serdes_macro *macro,
+ struct sparx5_sd25g28_params *params)
{
- struct sparx5_serdes_regval item[] = {
- {
- SD_LANE_25G_SD_LANE_CFG_MACRO_RST_SET(1),
- SD_LANE_25G_SD_LANE_CFG_MACRO_RST,
- sdx5_addr(regs, SD_LANE_25G_SD_LANE_CFG(sd_index))
- },
- {
- SD25G_LANE_CMU_FF_REGISTER_TABLE_INDEX_SET(0xFF),
- SD25G_LANE_CMU_FF_REGISTER_TABLE_INDEX,
- sdx5_addr(regs, SD25G_LANE_CMU_FF(sd_index))
- },
- {
- SD25G_LANE_CMU_1A_R_DWIDTHCTRL_FROM_HWT_SET
- (params->r_d_width_ctrl_from_hwt) |
-
SD25G_LANE_CMU_1A_R_REG_MANUAL_SET(params->r_reg_manual),
- SD25G_LANE_CMU_1A_R_DWIDTHCTRL_FROM_HWT |
- SD25G_LANE_CMU_1A_R_REG_MANUAL,
- sdx5_addr(regs, SD25G_LANE_CMU_1A(sd_index))
- },
- {
- SD25G_LANE_CMU_31_CFG_COMMON_RESERVE_7_0_SET
- (params->cfg_common_reserve_7_0),
- SD25G_LANE_CMU_31_CFG_COMMON_RESERVE_7_0,
- sdx5_addr(regs, SD25G_LANE_CMU_31(sd_index))
- },
- {
-
SD25G_LANE_CMU_09_CFG_EN_DUMMY_SET(params->cfg_en_dummy),
- SD25G_LANE_CMU_09_CFG_EN_DUMMY,
- sdx5_addr(regs, SD25G_LANE_CMU_09(sd_index))
- },
- {
-
SD25G_LANE_CMU_13_CFG_PLL_RESERVE_3_0_SET(params->cfg_pll_reserve_3_0),
- SD25G_LANE_CMU_13_CFG_PLL_RESERVE_3_0,
- sdx5_addr(regs, SD25G_LANE_CMU_13(sd_index))
- },
- {
-
SD25G_LANE_CMU_40_L0_CFG_TXCAL_EN_SET(params->l0_cfg_txcal_en),
- SD25G_LANE_CMU_40_L0_CFG_TXCAL_EN,
- sdx5_addr(regs, SD25G_LANE_CMU_40(sd_index))
- },
- {
- SD25G_LANE_CMU_46_L0_CFG_TX_RESERVE_15_8_SET
- (params->l0_cfg_tx_reserve_15_8),
- SD25G_LANE_CMU_46_L0_CFG_TX_RESERVE_15_8,
- sdx5_addr(regs, SD25G_LANE_CMU_46(sd_index))
- },
- {
-
SD25G_LANE_CMU_45_L0_CFG_TX_RESERVE_7_0_SET(params->l0_cfg_tx_reserve_7_0),
- SD25G_LANE_CMU_45_L0_CFG_TX_RESERVE_7_0,
- sdx5_addr(regs, SD25G_LANE_CMU_45(sd_index))
- },
- {
- SD25G_LANE_CMU_0B_CFG_VCO_CAL_RESETN_SET(0),
- SD25G_LANE_CMU_0B_CFG_VCO_CAL_RESETN,
- sdx5_addr(regs, SD25G_LANE_CMU_0B(sd_index))
- },
- {
- SD25G_LANE_CMU_0B_CFG_VCO_CAL_RESETN_SET(1),
- SD25G_LANE_CMU_0B_CFG_VCO_CAL_RESETN,
- sdx5_addr(regs, SD25G_LANE_CMU_0B(sd_index))
- },
- {
- SD25G_LANE_CMU_19_R_CK_RESETB_SET(0),
- SD25G_LANE_CMU_19_R_CK_RESETB,
- sdx5_addr(regs, SD25G_LANE_CMU_19(sd_index))
- },
- {
- SD25G_LANE_CMU_19_R_CK_RESETB_SET(1),
- SD25G_LANE_CMU_19_R_CK_RESETB,
- sdx5_addr(regs, SD25G_LANE_CMU_19(sd_index))
- },
- {
- SD25G_LANE
Re: [PATCH linux-next 1/1] phy: Sparx5 Eth SerDes: Use direct register operations
Hi Andrew,
On Mon, 2021-03-29 at 20:55 +0200, Andrew Lunn wrote:
> EXTERNAL EMAIL: Do not click links or open attachments unless you know the
> content is safe
>
> On Mon, Mar 29, 2021 at 10:14:38AM +0200, Steen Hegelund wrote:
> > Use direct register operations instead of a table of register
> > information to lower the stack usage.
> >
> > Signed-off-by: Steen Hegelund
> > Reported-by: kernel test robot
> > ---
> > drivers/phy/microchip/sparx5_serdes.c | 1869 +
> > 1 file changed, 951 insertions(+), 918 deletions(-)
> >
> > diff --git a/drivers/phy/microchip/sparx5_serdes.c
> > b/drivers/phy/microchip/sparx5_serdes.c
> > index 06bcf0c166cf..43de68a62c2f 100644
> > --- a/drivers/phy/microchip/sparx5_serdes.c
> > +++ b/drivers/phy/microchip/sparx5_serdes.c
> > @@ -343,12 +343,6 @@ struct sparx5_sd10g28_params {
> > u8 fx_100;
> > };
> >
> > -struct sparx5_serdes_regval {
> > - u32 value;
> > - u32 mask;
> > - void __iomem *addr;
> > -};
> > -
> > static struct sparx5_sd25g28_media_preset media_presets_25g[] = {
> > { /* ETH_MEDIA_DEFAULT */
> > .cfg_en_adv = 0,
> > @@ -945,431 +939,411 @@ static void sparx5_sd25g28_reset(void __iomem
> > *regs[],
> > }
> > }
> >
> > -static int sparx5_sd25g28_apply_params(struct device *dev,
> > -void __iomem *regs[],
> > -struct sparx5_sd25g28_params *params,
> > -u32 sd_index)
> > +static int sparx5_sd25g28_apply_params(struct sparx5_serdes_macro *macro,
> > +struct sparx5_sd25g28_params *params)
> > {
> > - struct sparx5_serdes_regval item[] = {
>
> Could you just add const here, and then it is no longer on the stack?
>
>Andrew
No it still counts against the stack even as a const structure.
BR
Steen
[PATCH v9 0/3] Adding the Sparx5 Switch Reset Driver
This series provides the Microchip Sparx5 Switch Reset Driver The Sparx5 Switch SoC has a number of components that can be reset individually, but at least the Switch Core needs to be in a well defined state at power on, when any of the Sparx5 drivers starts to access the Switch Core, this reset driver is available. The reset driver is loaded early via the postcore_initcall interface, and will then be available for the other Sparx5 drivers (SGPIO, SwitchDev etc) that are loaded next, and the first of them to be loaded can perform the one-time Switch Core reset that is needed. The driver has protection so that the system busses, DDR controller, PCI-E and ARM A53 CPU and a few other subsystems are not touched by the reset. Sparx5 will no longer use the existing Ocelot chip reset driver, but use this new switch reset driver as it has the reset controller interface that allows the first client to perform the reset on behalf of all the Sparx5 component drivers. The Sparx5 Chip Register Model can be browsed at this location: https://github.com/microchip-ung/sparx-5_reginfo and the datasheet is available here: https://ww1.microchip.com/downloads/en/DeviceDoc/SparX-5_Family_L2L3_Enterprise_10G_Ethernet_Switches_Datasheet_3822B.pdf History: v8 -> v9 Added reviewed-by tag. v7 -> v8 Updated the commit descriptions to explain the change from using the existing Ocelot chip reset driver to use a new switch reset driver. v6 -> v7 Use devm_platform_get_and_ioremap_resource to get the IO range. Rebase on v5.12-rc1 v5 -> v6 Using the existing CPU syscon for reset protection and add a small IO range for the GCB Reset Register. v4 -> v5 Changed the two syscons into IO ranges and updated the bindings to reflect this change. v3 -> v4 Added commit message descriptions v2 -> v3 Removed unused headers Renamed the reset controller dev member. Use regmap_read_poll_timeout instead of polling a function. Used two separate syscon entries in the binding Simplified the syscon error handling. Simplified the devm_reset_controller_register error handling. Moved the contents of the mchp_sparx5_reset_config function into the probe function. v1 -> v2 Removed debug prints Changed the error handling to save the error code before jumping. Steen Hegelund (3): dt-bindings: reset: microchip sparx5 reset driver bindings reset: mchp: sparx5: add switch reset driver arm64: dts: reset: add microchip sparx5 switch reset driver .../bindings/reset/microchip,rst.yaml | 58 +++ arch/arm64/boot/dts/microchip/sparx5.dtsi | 7 +- drivers/reset/Kconfig | 8 + drivers/reset/Makefile| 1 + drivers/reset/reset-microchip-sparx5.c| 146 ++ 5 files changed, 218 insertions(+), 2 deletions(-) create mode 100644 Documentation/devicetree/bindings/reset/microchip,rst.yaml create mode 100644 drivers/reset/reset-microchip-sparx5.c -- 2.31.1
[PATCH v9 1/3] dt-bindings: reset: microchip sparx5 reset driver bindings
Document the Sparx5 reset device driver bindings
The driver uses a syscon and an IO range on sparx5 for access to
the reset control and the reset status.
Sparx5 will no longer use the existing Ocelot chip reset driver, but use
this new switch reset driver as it has the reset controller interface that
allows the first client to perform the reset on behalf of all the Sparx5
component drivers.
Signed-off-by: Steen Hegelund
Reviewed-by: Rob Herring
---
.../bindings/reset/microchip,rst.yaml | 58 +++
1 file changed, 58 insertions(+)
create mode 100644 Documentation/devicetree/bindings/reset/microchip,rst.yaml
diff --git a/Documentation/devicetree/bindings/reset/microchip,rst.yaml
b/Documentation/devicetree/bindings/reset/microchip,rst.yaml
new file mode 100644
index ..370579aeeca1
--- /dev/null
+++ b/Documentation/devicetree/bindings/reset/microchip,rst.yaml
@@ -0,0 +1,58 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: "http://devicetree.org/schemas/reset/microchip,rst.yaml#";
+$schema: "http://devicetree.org/meta-schemas/core.yaml#";
+
+title: Microchip Sparx5 Switch Reset Controller
+
+maintainers:
+ - Steen Hegelund
+ - Lars Povlsen
+
+description: |
+ The Microchip Sparx5 Switch provides reset control and implements the
following
+ functions
+- One Time Switch Core Reset (Soft Reset)
+
+properties:
+ $nodename:
+pattern: "^reset-controller@[0-9a-f]+$"
+
+ compatible:
+const: microchip,sparx5-switch-reset
+
+ reg:
+items:
+ - description: global control block registers
+
+ reg-names:
+items:
+ - const: gcb
+
+ "#reset-cells":
+const: 1
+
+ cpu-syscon:
+$ref: "/schemas/types.yaml#/definitions/phandle"
+description: syscon used to access CPU reset
+
+required:
+ - compatible
+ - reg
+ - reg-names
+ - "#reset-cells"
+ - cpu-syscon
+
+additionalProperties: false
+
+examples:
+ - |
+reset: reset-controller@11010008 {
+compatible = "microchip,sparx5-switch-reset";
+reg = <0x11010008 0x4>;
+reg-names = "gcb";
+#reset-cells = <1>;
+cpu-syscon = <&cpu_ctrl>;
+};
+
--
2.31.1
[PATCH v9 2/3] reset: mchp: sparx5: add switch reset driver
The Sparx5 Switch SoC has a number of components that can be reset
indiviually, but at least the Switch Core needs to be in a well defined
state at power on, when any of the Sparx5 drivers starts to access the
Switch Core, this reset driver is available.
The reset driver is loaded early via the postcore_initcall interface, and
will then be available for the other Sparx5 drivers (SGPIO, SwitchDev etc)
that are loaded next, and the first of them to be loaded can perform the
one-time Switch Core reset that is needed.
The driver has protection so that the system busses, DDR controller, PCI-E
and ARM A53 CPU and a few other subsystems are not touched by the reset.
Signed-off-by: Steen Hegelund
Reviewed-by: Alexandre Belloni
---
drivers/reset/Kconfig | 8 ++
drivers/reset/Makefile | 1 +
drivers/reset/reset-microchip-sparx5.c | 146 +
3 files changed, 155 insertions(+)
create mode 100644 drivers/reset/reset-microchip-sparx5.c
diff --git a/drivers/reset/Kconfig b/drivers/reset/Kconfig
index 4171c6f76385..c26798092ccf 100644
--- a/drivers/reset/Kconfig
+++ b/drivers/reset/Kconfig
@@ -111,6 +111,14 @@ config RESET_LPC18XX
help
This enables the reset controller driver for NXP LPC18xx/43xx SoCs.
+config RESET_MCHP_SPARX5
+ bool "Microchip Sparx5 reset driver"
+ depends on HAS_IOMEM || COMPILE_TEST
+ default y if SPARX5_SWITCH
+ select MFD_SYSCON
+ help
+ This driver supports switch core reset for the Microchip Sparx5 SoC.
+
config RESET_MESON
tristate "Meson Reset Driver"
depends on ARCH_MESON || COMPILE_TEST
diff --git a/drivers/reset/Makefile b/drivers/reset/Makefile
index 65a118a91b27..c1d6aa9b1b52 100644
--- a/drivers/reset/Makefile
+++ b/drivers/reset/Makefile
@@ -16,6 +16,7 @@ obj-$(CONFIG_RESET_INTEL_GW) += reset-intel-gw.o
obj-$(CONFIG_RESET_K210) += reset-k210.o
obj-$(CONFIG_RESET_LANTIQ) += reset-lantiq.o
obj-$(CONFIG_RESET_LPC18XX) += reset-lpc18xx.o
+obj-$(CONFIG_RESET_MCHP_SPARX5) += reset-microchip-sparx5.o
obj-$(CONFIG_RESET_MESON) += reset-meson.o
obj-$(CONFIG_RESET_MESON_AUDIO_ARB) += reset-meson-audio-arb.o
obj-$(CONFIG_RESET_NPCM) += reset-npcm.o
diff --git a/drivers/reset/reset-microchip-sparx5.c
b/drivers/reset/reset-microchip-sparx5.c
new file mode 100644
index ..cff39a643a14
--- /dev/null
+++ b/drivers/reset/reset-microchip-sparx5.c
@@ -0,0 +1,146 @@
+// SPDX-License-Identifier: GPL-2.0+
+/* Microchip Sparx5 Switch Reset driver
+ *
+ * Copyright (c) 2020 Microchip Technology Inc. and its subsidiaries.
+ *
+ * The Sparx5 Chip Register Model can be browsed at this location:
+ * https://github.com/microchip-ung/sparx-5_reginfo
+ */
+#include
+#include
+#include
+#include
+#include
+#include
+
+#define PROTECT_REG0x84
+#define PROTECT_BITBIT(10)
+#define SOFT_RESET_REG 0x00
+#define SOFT_RESET_BIT BIT(1)
+
+struct mchp_reset_context {
+ struct regmap *cpu_ctrl;
+ struct regmap *gcb_ctrl;
+ struct reset_controller_dev rcdev;
+};
+
+static struct regmap_config sparx5_reset_regmap_config = {
+ .reg_bits = 32,
+ .val_bits = 32,
+ .reg_stride = 4,
+};
+
+static int sparx5_switch_reset(struct reset_controller_dev *rcdev,
+ unsigned long id)
+{
+ struct mchp_reset_context *ctx =
+ container_of(rcdev, struct mchp_reset_context, rcdev);
+ u32 val;
+
+ /* Make sure the core is PROTECTED from reset */
+ regmap_update_bits(ctx->cpu_ctrl, PROTECT_REG, PROTECT_BIT,
PROTECT_BIT);
+
+ /* Start soft reset */
+ regmap_write(ctx->gcb_ctrl, SOFT_RESET_REG, SOFT_RESET_BIT);
+
+ /* Wait for soft reset done */
+ return regmap_read_poll_timeout(ctx->gcb_ctrl, SOFT_RESET_REG, val,
+ (val & SOFT_RESET_BIT) == 0,
+ 1, 100);
+}
+
+static const struct reset_control_ops sparx5_reset_ops = {
+ .reset = sparx5_switch_reset,
+};
+
+static int mchp_sparx5_map_syscon(struct platform_device *pdev, char *name,
+ struct regmap **target)
+{
+ struct device_node *syscon_np;
+ struct regmap *regmap;
+ int err;
+
+ syscon_np = of_parse_phandle(pdev->dev.of_node, name, 0);
+ if (!syscon_np)
+ return -ENODEV;
+ regmap = syscon_node_to_regmap(syscon_np);
+ of_node_put(syscon_np);
+ if (IS_ERR(regmap)) {
+ err = PTR_ERR(regmap);
+ dev_err(&pdev->dev, "No '%s' map: %d\n", name, err);
+ return err;
+ }
+ *target = regmap;
+ return 0;
+}
+
+static int mchp_sparx5_map_io(struct platform_device *pdev, int index,
+ struct regmap **target)
+{
+ struct resource *res;
+
[PATCH v9 3/3] arm64: dts: reset: add microchip sparx5 switch reset driver
This provides reset driver support for the Microchip Sparx5 PCB134 and
PCB135 reference boards.
The Sparx5 Switch will no longer use the Ocelot Chip Reset Driver (with the
compatible string "microchip,sparx5-chip-reset"), but use a separate driver
that exposes a reset controller interface and has the compatiple string
"microchip,sparx5-switch-reset".
Eventually the Sparx5 reset support will be removed from the Ocelot chip
reset driver.
Signed-off-by: Steen Hegelund
Reviewed-by: Alexandre Belloni
---
arch/arm64/boot/dts/microchip/sparx5.dtsi | 7 +--
1 file changed, 5 insertions(+), 2 deletions(-)
diff --git a/arch/arm64/boot/dts/microchip/sparx5.dtsi
b/arch/arm64/boot/dts/microchip/sparx5.dtsi
index 380281f312d8..dc3ada5cf9fc 100644
--- a/arch/arm64/boot/dts/microchip/sparx5.dtsi
+++ b/arch/arm64/boot/dts/microchip/sparx5.dtsi
@@ -132,9 +132,12 @@ mux: mux-controller {
};
};
- reset@611010008 {
- compatible = "microchip,sparx5-chip-reset";
+ reset: reset-controller@611010008 {
+ compatible = "microchip,sparx5-switch-reset";
reg = <0x6 0x11010008 0x4>;
+ reg-names = "gcb";
+ #reset-cells = <1>;
+ cpu-syscon = <&cpu_ctrl>;
};
uart0: serial@60010 {
--
2.31.1
[PATCH net-next 00/10] Adding the Sparx5 Switch Driver
This series provides the Microchip Sparx5 Switch Driver The Sparx5 Carrier Ethernet and Industrial switch family delivers 64 Ethernet ports and up to 200 Gbps of switching bandwidth. It provides a rich set of Ethernet switching features such as hierarchical QoS, hardware-based OAM and service activation testing, protection switching, IEEE 1588, and Synchronous Ethernet. Using provider bridging (Q-in-Q) and MPLS/MPLS-TP technology, it delivers MEF CE 2.0 Ethernet virtual connections (EVCs) and features advanced TCAM classification in both ingress and egress. Per-EVC features include advanced L3-aware classification, a rich set of statistics, OAM for end-to-end performance monitoring, and dual-rate policing and shaping. Time sensitive networking (TSN) is supported through a comprehensive set of features including frame preemption, cut-through, frame replication and elimination for reliability, enhanced scheduling: credit-based shaping, time-aware shaping, cyclic queuing, and forwarding, and per-stream policing and filtering. Together with IEEE 1588 and IEEE 802.1AS support, this guarantees low-latency deterministic networking for Fronthaul, Carrier, and Industrial Ethernet. The Sparx5 switch family consists of following SKUs: - VSC7546 Sparx5-64 up to 64 Gbps of bandwidth with the following primary port configurations: - 6 *10G - 16 * 2.5G + 2 * 10G - 24 * 1G + 4 * 10G - VSC7549 Sparx5-90 up to 90 Gbps of bandwidth with the following primary port configurations: - 9 * 10G - 16 * 2.5G + 4 * 10G - 48 * 1G + 4 * 10G - VSC7552 Sparx5-128 up to 128 Gbps of bandwidth with the following primary port configurations: - 12 * 10G - 16 * 2.5G + 8 * 10G - 48 * 1G + 8 * 10G - VSC7556 Sparx5-160 up to 160 Gbps of bandwidth with the following primary port configurations: - 16 * 10G - 10 * 10G + 2 * 25G - 16 * 2.5G + 10 * 10G - 48 * 1G + 10 * 10G - VSC7558 Sparx5-200 up to 200 Gbps of bandwidth with the following primary port configurations: - 20 * 10G - 8 * 25G In addition, the device supports one 10/100/1000/2500/5000 Mbps SGMII/SerDes node processor interface (NPI) Ethernet port. The Sparx5 support is developed on the PCB134 and PCB135 evaluation boards. - PCB134 main networking features: - 12x SFP+ front 10G module slots (connected to Sparx5 through SFI). - 8x SFP28 front 25G module slots (connected to Sparx5 through SFI high speed). - Optional, one additional 10/100/1000BASE-T (RJ45) Ethernet port (on-board VSC8211 PHY connected to Sparx5 through SGMII). - PCB135 main networking features: - 48x1G (10/100/1000M) RJ45 front ports using 12xVSC8514 QuadPHY’s each connected to VSC7558 through QSGMII. - 4x10G (1G/2.5G/5G/10G) RJ45 front ports using the AQR407 10G QuadPHY each port connects to VSC7558 through SFI. - 4x SFP28 25G module slots on back connected to VSC7558 through SFI high speed. - Optional, one additional 1G (10/100/1000M) RJ45 port using an on-board VSC8211 PHY, which can be connected to VSC7558 NPI port through SGMII using a loopback add-on PCB) This series provides support for: - SFPs and DAC cables via PHYLINK with a number of 5G, 10G and 25G devices and media types. - Port module configuration for 10M to 25G speeds with SGMII, QSGMII, 1000BASEX, 2500BASEX and 10GBASER as appropriate for these modes. - SerDes configuration via the Sparx5 SerDes driver (see below). - Host mode providing register based injection and extraction. - Switch mode providing MAC/VLAN table learning and Layer2 switching offloaded to the Sparx5 switch. - STP state, VLAN support, host/bridge port mode, Forwarding DB, and configuration and statistics via ethtool. More support will be added at a later stage. The Sparx5 Chip Register Model can be browsed at this location: https://github.com/microchip-ung/sparx-5_reginfo and the datasheet is available here: https://ww1.microchip.com/downloads/en/DeviceDoc/SparX-5_Family_L2L3_Enterprise_10G_Ethernet_Switches_Datasheet_3822B.pdf The series depends on the following series currently on their way into the kernel: - Sparx5 SerDes Driver Link: https://lore.kernel.org/r/20210218161451.3489955-1-steen.hegel...@microchip.com/ - Sparx5 Reset Driver Link: https://lore.kernel.org/r/20210416084054.2922327-1-steen.hegel...@microchip.com/ Steen Hegelund (10): dt-bindings: net: sparx5: Add sparx5-switch bindings net: sparx5: add the basic sparx5 driver net: sparx5: add hostmode with phylink support net: sparx5: add port module support net: sparx5: add mactable support net: sparx5: add vlan support net: sparx5: add switching support net: sparx5: add calendar bandwidth allocation support net: sparx5: add ethtool configuration and statistics support arm64: dts: sparx5: Add the Sparx5 switch node .../bindings/net/microchip,sparx5-switch.yaml | 227 + arch/arm64/boot/dts/microchip/sparx5.dtsi | 94 +- .../dts/microchip
[PATCH net-next 01/10] dt-bindings: net: sparx5: Add sparx5-switch bindings
Document the Sparx5 switch device driver bindings
Signed-off-by: Steen Hegelund
Signed-off-by: Lars Povlsen
Signed-off-by: Bjarni Jonasson
---
.../bindings/net/microchip,sparx5-switch.yaml | 227 ++
1 file changed, 227 insertions(+)
create mode 100644
Documentation/devicetree/bindings/net/microchip,sparx5-switch.yaml
diff --git a/Documentation/devicetree/bindings/net/microchip,sparx5-switch.yaml
b/Documentation/devicetree/bindings/net/microchip,sparx5-switch.yaml
new file mode 100644
index ..2eeb5230d8c8
--- /dev/null
+++ b/Documentation/devicetree/bindings/net/microchip,sparx5-switch.yaml
@@ -0,0 +1,227 @@
+# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/net/microchip,sparx5-switch.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Microchip Sparx5 Ethernet switch controller
+
+maintainers:
+ - Steen Hegelund
+ - Lars Povlsen
+
+description: |
+ The SparX-5 Enterprise Ethernet switch family provides a rich set of
+ Enterprise switching features such as advanced TCAM-based VLAN and
+ QoS processing enabling delivery of differentiated services, and
+ security through TCAM-based frame processing using versatile content
+ aware processor (VCAP).
+
+ IPv4/IPv6 Layer 3 (L3) unicast and multicast routing is supported
+ with up to 18K IPv4/9K IPv6 unicast LPM entries and up to 9K IPv4/3K
+ IPv6 (S,G) multicast groups.
+
+ L3 security features include source guard and reverse path
+ forwarding (uRPF) tasks. Additional L3 features include VRF-Lite and
+ IP tunnels (IP over GRE/IP).
+
+ The SparX-5 switch family targets managed Layer 2 and Layer 3
+ equipment in SMB, SME, and Enterprise where high port count
+ 1G/2.5G/5G/10G switching with 10G/25G aggregation links is required.
+
+properties:
+ $nodename:
+pattern: "^switch@[0-9a-f]+$"
+
+ compatible:
+const: microchip,sparx5-switch
+
+ reg:
+minItems: 3
+items:
+ - description: cpu target
+ - description: devices target
+ - description: general control block target
+
+ reg-names:
+items:
+ - const: cpu
+ - const: devices
+ - const: gcb
+
+ interrupts:
+minItems: 1
+items:
+ - description: register based extraction
+ - description: frame dma based extraction
+
+ interrupt-names:
+minItems: 1
+items:
+ - const: xtr
+ - const: fdma
+
+ resets:
+items:
+ - description: Reset controller used for switch core reset (soft reset)
+
+ reset-names:
+items:
+ - const: switch
+
+ mac-address: true
+
+ ethernet-ports:
+type: object
+patternProperties:
+ "^port@[0-9a-f]+$":
+type: object
+
+properties:
+ '#address-cells':
+const: 1
+ '#size-cells':
+const: 0
+
+ reg:
+description: Switch port number
+
+ phys:
+maxItems: 1
+description:
+ phandle of a Ethernet SerDes PHY. This defines which SerDes
+ instance will handle the Ethernet traffic.
+
+ phy-mode:
+description:
+ This specifies the interface used by the Ethernet SerDes towards
+ the PHY or SFP.
+
+ microchip,bandwidth:
+description: Specifies bandwidth in Mbit/s allocated to the port.
+$ref: "/schemas/types.yaml#/definitions/uint32"
+maximum: 25000
+
+ phy-handle:
+description:
+ phandle of a Ethernet PHY. This is optional and if provided it
+ points to the cuPHY used by the Ethernet SerDes.
+
+ sfp:
+description:
+ phandle of an SFP. This is optional and used when not specifying
+ a cuPHY. It points to the SFP node that describes the SFP used
by
+ the Ethernet SerDes.
+
+ managed: true
+
+ microchip,sd-sgpio:
+description:
+ Index of the ports Signal Detect SGPIO in the set of 384 SGPIOs
+ This is optional, and only needed if the default used index is
+ is not correct.
+$ref: "/schemas/types.yaml#/definitions/uint32"
+minimum: 0
+maximum: 383
+
+required:
+ - reg
+ - phys
+ - phy-mode
+ - microchip,bandwidth
+
+oneOf:
+ - required:
+ - phy-handle
+ - required:
+ - sfp
+ - managed
+
+required:
+ - compatible
+ - reg
+ - reg-names
+ - interrupts
+ - interrupt-names
+ - resets
+ - reset-names
+ - ethernet-ports
+
+additionalProperties: false
+
+examples:
+ - |
+#include
+switch: switch@6 {
+ compatible = "microchip,sparx5-switch";
+ reg = <0 0x401000>,
+ <0x10004000 0x7fc000&g
[PATCH net-next 03/10] net: sparx5: add hostmode with phylink support
This patch adds netdevs and phylink support for the ports in the switch.
It also adds register based injection and extraction for these ports.
Frame DMA support for injection and extraction will be added in a later
series.
Signed-off-by: Steen Hegelund
Signed-off-by: Bjarni Jonasson
Signed-off-by: Lars Povlsen
---
.../net/ethernet/microchip/sparx5/Makefile| 2 +-
.../ethernet/microchip/sparx5/sparx5_main.c | 77 -
.../ethernet/microchip/sparx5/sparx5_main.h | 21 ++
.../ethernet/microchip/sparx5/sparx5_netdev.c | 204 +
.../ethernet/microchip/sparx5/sparx5_packet.c | 286 ++
.../microchip/sparx5/sparx5_phylink.c | 170 +++
6 files changed, 750 insertions(+), 10 deletions(-)
create mode 100644 drivers/net/ethernet/microchip/sparx5/sparx5_netdev.c
create mode 100644 drivers/net/ethernet/microchip/sparx5/sparx5_packet.c
create mode 100644 drivers/net/ethernet/microchip/sparx5/sparx5_phylink.c
diff --git a/drivers/net/ethernet/microchip/sparx5/Makefile
b/drivers/net/ethernet/microchip/sparx5/Makefile
index 41a31843d86f..19a593d17f4a 100644
--- a/drivers/net/ethernet/microchip/sparx5/Makefile
+++ b/drivers/net/ethernet/microchip/sparx5/Makefile
@@ -5,4 +5,4 @@
obj-$(CONFIG_SPARX5_SWITCH) += sparx5-switch.o
-sparx5-switch-objs := sparx5_main.o
+sparx5-switch-objs := sparx5_main.o sparx5_packet.o sparx5_netdev.o
sparx5_phylink.o
diff --git a/drivers/net/ethernet/microchip/sparx5/sparx5_main.c
b/drivers/net/ethernet/microchip/sparx5/sparx5_main.c
index 43a67e5c507e..68fd0d5353ba 100644
--- a/drivers/net/ethernet/microchip/sparx5/sparx5_main.c
+++ b/drivers/net/ethernet/microchip/sparx5/sparx5_main.c
@@ -250,9 +250,16 @@ static int sparx5_create_port(struct sparx5 *sparx5,
struct initial_port_config *config)
{
struct sparx5_port *spx5_port;
-
- /* netdev creation to be added in later patches */
- spx5_port = devm_kzalloc(sparx5->dev, sizeof(*spx5_port), GFP_KERNEL);
+ struct net_device *ndev;
+ struct phylink *phylink;
+
+ ndev = sparx5_create_netdev(sparx5, config->portno);
+ if (IS_ERR(ndev)) {
+ dev_err(sparx5->dev, "Could not create net device: %02u\n",
+ config->portno);
+ return PTR_ERR(ndev);
+ }
+ spx5_port = netdev_priv(ndev);
spx5_port->of_node = config->node;
spx5_port->serdes = config->serdes;
spx5_port->pvid = NULL_VID;
@@ -262,8 +269,25 @@ static int sparx5_create_port(struct sparx5 *sparx5,
spx5_port->max_vlan_tags = SPX5_PORT_MAX_TAGS_NONE;
spx5_port->vlan_type = SPX5_VLAN_PORT_TYPE_UNAWARE;
spx5_port->custom_etype = 0x8880; /* Vitesse */
+ sparx5->ports[config->portno] = spx5_port;
+
+ spx5_port->conf = config->conf;
+
+ /* VLAN setup to be added in later patches */
+
+ /* Create a phylink for PHY management. Also handles SFPs */
+ spx5_port->phylink_config.dev = &spx5_port->ndev->dev;
+ spx5_port->phylink_config.type = PHYLINK_NETDEV;
+ spx5_port->phylink_config.pcs_poll = true;
+
+ phylink = phylink_create(&spx5_port->phylink_config,
+of_fwnode_handle(config->node),
+config->conf.phy_mode,
+&sparx5_phylink_mac_ops);
+ if (IS_ERR(phylink))
+ return PTR_ERR(phylink);
- /* PHYLINK support to be added in later patches */
+ spx5_port->phylink = phylink;
return 0;
}
@@ -525,6 +549,7 @@ static void sparx5_board_init(struct sparx5 *sparx5)
static int sparx5_start(struct sparx5 *sparx5)
{
u32 idx;
+ int err;
/* Setup own UPSIDs */
for (idx = 0; idx < 3; idx++) {
@@ -559,13 +584,33 @@ static int sparx5_start(struct sparx5 *sparx5)
/* Enable queue limitation watermarks */
sparx5_qlim_set(sparx5);
- /* netdev and resource calendar support to be added in later patches */
+ /* Resource calendar support to be added in later patches */
+
+ err = sparx5_register_netdevs(sparx5);
+ if (err)
+ return err;
sparx5_board_init(sparx5);
- /* Injection/Extraction config to be added in later patches */
+ /* Start register based INJ/XTR */
+ err = -ENXIO;
+ if (err && sparx5->xtr_irq >= 0) {
+ err = devm_request_irq(sparx5->dev, sparx5->xtr_irq,
+ sparx5_xtr_handler, IRQF_SHARED,
+ "sparx5-xtr", sparx5);
+ if (!err)
+ err = sparx5_manual_injection_mode(sparx5);
+ if (err)
+ sparx5->xtr_irq = -ENXIO;
+ } else {
+ sparx5->xtr_irq = -ENXIO;
+
[PATCH net-next 04/10] net: sparx5: add port module support
This add configuration of the Sparx5 port module instances.
Sparx5 has in total 65 logical ports (denoted D0 to D64) and 33
physical SerDes connections (S0 to S32). The 65th port (D64) is fixed
allocated to SerDes0 (S0). The remaining 64 ports can in various
multiplexing scenarios be connected to the remaining 32 SerDes using
QSGMII, or USGMII or USXGMII extenders. 32 of the ports can have a 1:1
mapping to the 32 SerDes.
Some additional ports (D65 to D69) are internal to the device and do not
connect to port modules or SerDes macros. For example, internal ports are
used for frame injection and extraction to the CPU queues.
The 65 logical ports are split up into the following blocks.
- 13 x 5G ports (D0-D11, D64)
- 32 x 2G5 ports (D16-D47)
- 12 x 10G ports (D12-D15, D48-D55)
- 8 x 25G ports (D56-D63)
Each logical port supports different line speeds, and depending on the
speeds supported, different port modules (MAC+PCS) are needed. A port
supporting 5 Gbps, 10 Gbps, or 25 Gbps as maximum line speed, will have a
DEV5G, DEV10G, or DEV25G module to support the 5 Gbps, 10 Gbps (incl 5
Gbps), or 25 Gbps (including 10 Gbps and 5 Gbps) speeds. As well as, it
will have a shadow DEV2G5 port module to support the lower speeds
(10/100/1000/2500Mbps). When a port needs to operate at lower speed and the
shadow DEV2G5 needs to be connected to its corresponding SerDes
Not all interface modes are supported in this series, but will be added at
a later stage.
Signed-off-by: Steen Hegelund
Signed-off-by: Bjarni Jonasson
Signed-off-by: Lars Povlsen
---
.../net/ethernet/microchip/sparx5/Makefile|3 +-
.../ethernet/microchip/sparx5/sparx5_main.c | 21 +-
.../ethernet/microchip/sparx5/sparx5_netdev.c | 14 +-
.../microchip/sparx5/sparx5_phylink.c | 37 +-
.../ethernet/microchip/sparx5/sparx5_port.c | 1129 +
.../ethernet/microchip/sparx5/sparx5_port.h | 98 ++
6 files changed, 1292 insertions(+), 10 deletions(-)
create mode 100644 drivers/net/ethernet/microchip/sparx5/sparx5_port.c
create mode 100644 drivers/net/ethernet/microchip/sparx5/sparx5_port.h
diff --git a/drivers/net/ethernet/microchip/sparx5/Makefile
b/drivers/net/ethernet/microchip/sparx5/Makefile
index 19a593d17f4a..9c14eec33fd7 100644
--- a/drivers/net/ethernet/microchip/sparx5/Makefile
+++ b/drivers/net/ethernet/microchip/sparx5/Makefile
@@ -5,4 +5,5 @@
obj-$(CONFIG_SPARX5_SWITCH) += sparx5-switch.o
-sparx5-switch-objs := sparx5_main.o sparx5_packet.o sparx5_netdev.o
sparx5_phylink.o
+sparx5-switch-objs := sparx5_main.o sparx5_packet.o \
+ sparx5_netdev.o sparx5_port.o sparx5_phylink.o
diff --git a/drivers/net/ethernet/microchip/sparx5/sparx5_main.c
b/drivers/net/ethernet/microchip/sparx5/sparx5_main.c
index 68fd0d5353ba..0ae8320a5bbb 100644
--- a/drivers/net/ethernet/microchip/sparx5/sparx5_main.c
+++ b/drivers/net/ethernet/microchip/sparx5/sparx5_main.c
@@ -26,6 +26,7 @@
#include "sparx5_main_regs.h"
#include "sparx5_main.h"
+#include "sparx5_port.h"
#define QLIM_WM(fraction) \
((SPX5_BUFFER_MEMORY / SPX5_BUFFER_CELL_SZ - 100) * (fraction) / 100)
@@ -252,6 +253,7 @@ static int sparx5_create_port(struct sparx5 *sparx5,
struct sparx5_port *spx5_port;
struct net_device *ndev;
struct phylink *phylink;
+ int err;
ndev = sparx5_create_netdev(sparx5, config->portno);
if (IS_ERR(ndev)) {
@@ -271,9 +273,26 @@ static int sparx5_create_port(struct sparx5 *sparx5,
spx5_port->custom_etype = 0x8880; /* Vitesse */
sparx5->ports[config->portno] = spx5_port;
+ err = sparx5_port_init(sparx5, spx5_port, &config->conf);
+ if (err) {
+ dev_err(sparx5->dev, "port init failed\n");
+ return err;
+ }
spx5_port->conf = config->conf;
- /* VLAN setup to be added in later patches */
+ /* VLAN support to be added in later patches */
+
+ /* Create a phylink for PHY management. Also handles SFPs */
+ spx5_port->phylink_config.dev = &spx5_port->ndev->dev;
+ spx5_port->phylink_config.type = PHYLINK_NETDEV;
+ spx5_port->phylink_config.pcs_poll = true;
+
+ phylink = phylink_create(&spx5_port->phylink_config,
+of_fwnode_handle(config->node),
+config->conf.phy_mode,
+&sparx5_phylink_mac_ops);
+ if (IS_ERR(phylink))
+ return PTR_ERR(phylink);
/* Create a phylink for PHY management. Also handles SFPs */
spx5_port->phylink_config.dev = &spx5_port->ndev->dev;
diff --git a/drivers/net/ethernet/microchip/sparx5/sparx5_netdev.c
b/drivers/net/ethernet/microchip/sparx5/sparx5_netdev.c
index 5574cdfb212e..9f053b91e8e0 100644
--- a/drivers/net/ethernet/microchip/sparx5/sparx5_netdev.c
+++ b/drivers/net/ethernet/
[PATCH net-next 06/10] net: sparx5: add vlan support
This adds Sparx5 VLAN support.
Sparx5 has more VLAN features than provided here, but these will be added
in later series. For now we only add the basic L2 features.
Signed-off-by: Steen Hegelund
Signed-off-by: Bjarni Jonasson
Signed-off-by: Lars Povlsen
---
.../net/ethernet/microchip/sparx5/Makefile| 2 +-
.../ethernet/microchip/sparx5/sparx5_main.c | 10 +-
.../ethernet/microchip/sparx5/sparx5_main.h | 14 ++
.../ethernet/microchip/sparx5/sparx5_vlan.c | 224 ++
4 files changed, 246 insertions(+), 4 deletions(-)
create mode 100644 drivers/net/ethernet/microchip/sparx5/sparx5_vlan.c
diff --git a/drivers/net/ethernet/microchip/sparx5/Makefile
b/drivers/net/ethernet/microchip/sparx5/Makefile
index 4ccb09d275bc..81685c3f428e 100644
--- a/drivers/net/ethernet/microchip/sparx5/Makefile
+++ b/drivers/net/ethernet/microchip/sparx5/Makefile
@@ -6,4 +6,4 @@
obj-$(CONFIG_SPARX5_SWITCH) += sparx5-switch.o
sparx5-switch-objs := sparx5_main.o sparx5_packet.o \
- sparx5_netdev.o sparx5_port.o sparx5_phylink.o sparx5_mactable.o
+ sparx5_netdev.o sparx5_port.o sparx5_phylink.o sparx5_mactable.o sparx5_vlan.o
diff --git a/drivers/net/ethernet/microchip/sparx5/sparx5_main.c
b/drivers/net/ethernet/microchip/sparx5/sparx5_main.c
index 33568ad0bd2f..fb3618be8e5d 100644
--- a/drivers/net/ethernet/microchip/sparx5/sparx5_main.c
+++ b/drivers/net/ethernet/microchip/sparx5/sparx5_main.c
@@ -280,7 +280,8 @@ static int sparx5_create_port(struct sparx5 *sparx5,
}
spx5_port->conf = config->conf;
- /* VLAN support to be added in later patches */
+ /* Setup VLAN */
+ sparx5_vlan_port_setup(sparx5, spx5_port->portno);
/* Create a phylink for PHY management. Also handles SFPs */
spx5_port->phylink_config.dev = &spx5_port->ndev->dev;
@@ -588,7 +589,9 @@ static int sparx5_start(struct sparx5 *sparx5)
QFWD_SWITCH_PORT_MODE(idx));
}
- /* Forwarding masks to be added in later patches */
+ /* Init masks */
+ sparx5_update_fwd(sparx5);
+
/* CPU copy CPU pgids */
spx5_wr(ANA_AC_PGID_MISC_CFG_PGID_CPU_COPY_ENA_SET(1),
sparx5, ANA_AC_PGID_MISC_CFG(PGID_CPU));
@@ -604,7 +607,8 @@ static int sparx5_start(struct sparx5 *sparx5)
/* Init MAC table, ageing */
sparx5_mact_init(sparx5);
- /* VLAN support to be added in later patches */
+ /* Setup VLANs */
+ sparx5_vlan_init(sparx5);
/* Add host mode BC address (points only to CPU) */
sparx5_mact_learn(sparx5, PGID_CPU, broadcast, NULL_VID);
diff --git a/drivers/net/ethernet/microchip/sparx5/sparx5_main.h
b/drivers/net/ethernet/microchip/sparx5/sparx5_main.h
index 5185104a7a0f..d82700614abf 100644
--- a/drivers/net/ethernet/microchip/sparx5/sparx5_main.h
+++ b/drivers/net/ethernet/microchip/sparx5/sparx5_main.h
@@ -135,6 +135,10 @@ struct sparx5 {
enum sparx5_core_clockfreq coreclock;
/* Switch state */
u8 base_mac[ETH_ALEN];
+ /* Bridged interfaces */
+ DECLARE_BITMAP(bridge_fwd_mask, SPX5_PORTS);
+ DECLARE_BITMAP(bridge_lrn_mask, SPX5_PORTS);
+ DECLARE_BITMAP(vlan_mask[VLAN_N_VID], SPX5_PORTS);
/* SW MAC table */
struct list_head mact_entries;
/* mac table list (mact_entries) mutex */
@@ -171,6 +175,16 @@ int sparx5_mc_unsync(struct net_device *dev, const
unsigned char *addr);
void sparx5_set_ageing(struct sparx5 *sparx5, int msecs);
void sparx5_mact_init(struct sparx5 *sparx5);
+/* sparx5_vlan.c */
+void sparx5_pgid_update_mask(struct sparx5_port *port, int pgid, bool enable);
+void sparx5_update_fwd(struct sparx5 *sparx5);
+void sparx5_vlan_init(struct sparx5 *sparx5);
+void sparx5_vlan_port_setup(struct sparx5 *sparx5, int portno);
+int sparx5_vlan_vid_add(struct sparx5_port *port, u16 vid, bool pvid,
+ bool untagged);
+int sparx5_vlan_vid_del(struct sparx5_port *port, u16 vid);
+void sparx5_vlan_port_apply(struct sparx5 *sparx5, struct sparx5_port *port);
+
/* sparx5_netdev.c */
bool sparx5_netdevice_check(const struct net_device *dev);
struct net_device *sparx5_create_netdev(struct sparx5 *sparx5, u32 portno);
diff --git a/drivers/net/ethernet/microchip/sparx5/sparx5_vlan.c
b/drivers/net/ethernet/microchip/sparx5/sparx5_vlan.c
new file mode 100644
index ..4ce490a25f33
--- /dev/null
+++ b/drivers/net/ethernet/microchip/sparx5/sparx5_vlan.c
@@ -0,0 +1,224 @@
+// SPDX-License-Identifier: GPL-2.0+
+/* Microchip Sparx5 Switch driver
+ *
+ * Copyright (c) 2021 Microchip Technology Inc. and its subsidiaries.
+ */
+
+#include "sparx5_main_regs.h"
+#include "sparx5_main.h"
+
+static int sparx5_vlant_set_mask(struct sparx5 *sparx5, u16 vid)
+{
+ u32 mask[3];
+
+ /* Divide up mask in 32 bit words */
+ bitmap_to_arr32(mask, sparx5->vlan_mask[vid], SPX5_PORTS);
+
+ /* Output mask to respective
[PATCH net-next 05/10] net: sparx5: add mactable support
This adds the Sparx5 MAC tables: listening for MAC table updates and
updating on request.
Signed-off-by: Steen Hegelund
Signed-off-by: Bjarni Jonasson
Signed-off-by: Lars Povlsen
---
.../net/ethernet/microchip/sparx5/Makefile| 2 +-
.../microchip/sparx5/sparx5_mactable.c| 497 ++
.../ethernet/microchip/sparx5/sparx5_main.c | 21 +-
.../ethernet/microchip/sparx5/sparx5_main.h | 26 +
.../ethernet/microchip/sparx5/sparx5_netdev.c | 21 +
5 files changed, 565 insertions(+), 2 deletions(-)
create mode 100644 drivers/net/ethernet/microchip/sparx5/sparx5_mactable.c
diff --git a/drivers/net/ethernet/microchip/sparx5/Makefile
b/drivers/net/ethernet/microchip/sparx5/Makefile
index 9c14eec33fd7..4ccb09d275bc 100644
--- a/drivers/net/ethernet/microchip/sparx5/Makefile
+++ b/drivers/net/ethernet/microchip/sparx5/Makefile
@@ -6,4 +6,4 @@
obj-$(CONFIG_SPARX5_SWITCH) += sparx5-switch.o
sparx5-switch-objs := sparx5_main.o sparx5_packet.o \
- sparx5_netdev.o sparx5_port.o sparx5_phylink.o
+ sparx5_netdev.o sparx5_port.o sparx5_phylink.o sparx5_mactable.o
diff --git a/drivers/net/ethernet/microchip/sparx5/sparx5_mactable.c
b/drivers/net/ethernet/microchip/sparx5/sparx5_mactable.c
new file mode 100644
index ..6c5e04eccaa3
--- /dev/null
+++ b/drivers/net/ethernet/microchip/sparx5/sparx5_mactable.c
@@ -0,0 +1,497 @@
+// SPDX-License-Identifier: GPL-2.0+
+/* Microchip Sparx5 Switch driver
+ *
+ * Copyright (c) 2021 Microchip Technology Inc. and its subsidiaries.
+ */
+
+#include
+#include
+#include
+
+#include "sparx5_main_regs.h"
+#include "sparx5_main.h"
+
+/* Commands for Mac Table Command register */
+#define MAC_CMD_LEARN 0 /* Insert (Learn) 1 entry */
+#define MAC_CMD_UNLEARN 1 /* Unlearn (Forget) 1 entry */
+#define MAC_CMD_LOOKUP2 /* Look up 1 entry */
+#define MAC_CMD_READ 3 /* Read entry at Mac Table Index */
+#define MAC_CMD_WRITE 4 /* Write entry at Mac Table Index */
+#define MAC_CMD_SCAN 5 /* Scan (Age or find next) */
+#define MAC_CMD_FIND_SMALLEST 6 /* Get next entry */
+#define MAC_CMD_CLEAR_ALL 7 /* Delete all entries in table */
+
+/* Commands for MAC_ENTRY_ADDR_TYPE */
+#define MAC_ENTRY_ADDR_TYPE_UPSID_PN 0
+#define MAC_ENTRY_ADDR_TYPE_UPSID_CPU_OR_INT 1
+#define MAC_ENTRY_ADDR_TYPE_GLAG 2
+#define MAC_ENTRY_ADDR_TYPE_MC_IDX 3
+
+#define TABLE_UPDATE_SLEEP_US 10
+#define TABLE_UPDATE_TIMEOUT_US 10
+
+struct sparx5_mact_entry {
+ struct list_head list;
+ unsigned char mac[ETH_ALEN];
+ u32 flags;
+#define MAC_ENT_ALIVE BIT(0)
+#define MAC_ENT_MOVED BIT(1)
+#define MAC_ENT_LOCK BIT(2)
+ u16 vid;
+ u16 port;
+};
+
+static int sparx5_mact_get_status(struct sparx5 *sparx5)
+{
+ return spx5_rd(sparx5, LRN_COMMON_ACCESS_CTRL);
+}
+
+static int sparx5_mact_wait_for_completion(struct sparx5 *sparx5)
+{
+ u32 val;
+
+ return readx_poll_timeout(sparx5_mact_get_status,
+ sparx5, val,
+ LRN_COMMON_ACCESS_CTRL_MAC_TABLE_ACCESS_SHOT_GET(val) == 0,
+ TABLE_UPDATE_SLEEP_US, TABLE_UPDATE_TIMEOUT_US);
+}
+
+static void sparx5_mact_select(struct sparx5 *sparx5,
+ const unsigned char mac[ETH_ALEN],
+ u16 vid)
+{
+ u32 macl = 0, mach = 0;
+
+ /* Set the MAC address to handle and the vlan associated in a format
+* understood by the hardware.
+*/
+ mach |= vid<< 16;
+ mach |= mac[0] << 8;
+ mach |= mac[1] << 0;
+ macl |= mac[2] << 24;
+ macl |= mac[3] << 16;
+ macl |= mac[4] << 8;
+ macl |= mac[5] << 0;
+
+ spx5_wr(mach, sparx5, LRN_MAC_ACCESS_CFG_0);
+ spx5_wr(macl, sparx5, LRN_MAC_ACCESS_CFG_1);
+}
+
+int sparx5_mact_learn(struct sparx5 *sparx5, int pgid,
+ const unsigned char mac[ETH_ALEN], u16 vid)
+{
+ int addr, type, ret;
+
+ if (pgid < SPX5_PORTS) {
+ type = MAC_ENTRY_ADDR_TYPE_UPSID_PN;
+ addr = pgid % 32;
+ addr += (pgid / 32) << 5; /* Add upsid */
+ } else {
+ type = MAC_ENTRY_ADDR_TYPE_MC_IDX;
+ addr = pgid - SPX5_PORTS;
+ }
+
+ mutex_lock(&sparx5->lock);
+
+ sparx5_mact_select(sparx5, mac, vid);
+
+ /* MAC entry properties */
+ spx5_wr(LRN_MAC_ACCESS_CFG_2_MAC_ENTRY_ADDR_SET(addr) |
+ LRN_MAC_ACCESS_CFG_2_MAC_ENTRY_ADDR_TYPE_SET(type) |
+ LRN_MAC_ACCESS_CFG_2_MAC_ENTRY_VLD_SET(1) |
+ LRN_MAC_ACCESS_CFG_2_MAC_ENTRY_LOCKED_SET(1),
+ sparx5, LRN_MAC_ACCESS_CFG_2);
+ spx5_wr(0, sparx5, LRN_MAC_ACCESS_CFG_3);
+
+ /* Insert/learn new entry */
+ spx5_wr(LRN_COMMON_ACCESS_CTRL_CPU_ACCESS_CMD_SET(MAC_CMD_LEARN) |
+ LRN_COMMON_ACCESS_CTR
[PATCH net-next 07/10] net: sparx5: add switching support
This adds SwitchDev support by hardware offloading the
software bridge.
Signed-off-by: Steen Hegelund
Signed-off-by: Bjarni Jonasson
Signed-off-by: Lars Povlsen
---
.../net/ethernet/microchip/sparx5/Makefile| 3 +-
.../microchip/sparx5/sparx5_mactable.c| 3 +
.../ethernet/microchip/sparx5/sparx5_main.c | 13 +-
.../ethernet/microchip/sparx5/sparx5_main.h | 11 +
.../ethernet/microchip/sparx5/sparx5_netdev.c | 10 +
.../ethernet/microchip/sparx5/sparx5_packet.c | 6 +
.../microchip/sparx5/sparx5_switchdev.c | 508 ++
7 files changed, 552 insertions(+), 2 deletions(-)
create mode 100644 drivers/net/ethernet/microchip/sparx5/sparx5_switchdev.c
diff --git a/drivers/net/ethernet/microchip/sparx5/Makefile
b/drivers/net/ethernet/microchip/sparx5/Makefile
index 81685c3f428e..d2788e8b7798 100644
--- a/drivers/net/ethernet/microchip/sparx5/Makefile
+++ b/drivers/net/ethernet/microchip/sparx5/Makefile
@@ -6,4 +6,5 @@
obj-$(CONFIG_SPARX5_SWITCH) += sparx5-switch.o
sparx5-switch-objs := sparx5_main.o sparx5_packet.o \
- sparx5_netdev.o sparx5_port.o sparx5_phylink.o sparx5_mactable.o sparx5_vlan.o
+ sparx5_netdev.o sparx5_port.o sparx5_phylink.o sparx5_mactable.o
sparx5_vlan.o \
+ sparx5_switchdev.o
diff --git a/drivers/net/ethernet/microchip/sparx5/sparx5_mactable.c
b/drivers/net/ethernet/microchip/sparx5/sparx5_mactable.c
index 6c5e04eccaa3..0443f66b5550 100644
--- a/drivers/net/ethernet/microchip/sparx5/sparx5_mactable.c
+++ b/drivers/net/ethernet/microchip/sparx5/sparx5_mactable.c
@@ -371,6 +371,9 @@ static void sparx5_mact_handle_entry(struct sparx5 *sparx5,
if (port >= SPX5_PORTS)
return;
+ if (!test_bit(port, sparx5->bridge_mask))
+ return;
+
mutex_lock(&sparx5->mact_lock);
list_for_each_entry(mact_entry, &sparx5->mact_entries, list) {
if (mact_entry->vid == vid &&
diff --git a/drivers/net/ethernet/microchip/sparx5/sparx5_main.c
b/drivers/net/ethernet/microchip/sparx5/sparx5_main.c
index fb3618be8e5d..8121f0b1c0ea 100644
--- a/drivers/net/ethernet/microchip/sparx5/sparx5_main.c
+++ b/drivers/net/ethernet/microchip/sparx5/sparx5_main.c
@@ -633,6 +633,7 @@ static int sparx5_start(struct sparx5 *sparx5)
return err;
sparx5_board_init(sparx5);
+ err = sparx5_register_notifier_blocks(sparx5);
/* Start register based INJ/XTR */
err = -ENXIO;
@@ -652,7 +653,14 @@ static int sparx5_start(struct sparx5 *sparx5)
static void sparx5_cleanup_ports(struct sparx5 *sparx5)
{
- /* Port cleanup to be added in later patches */
+ int idx;
+
+ for (idx = 0; idx < SPX5_PORTS; ++idx) {
+ struct sparx5_port *port = sparx5->ports[idx];
+
+ if (port && port->ndev)
+ sparx5_destroy_netdev(sparx5, port);
+ }
}
static int mchp_sparx5_probe(struct platform_device *pdev)
@@ -820,6 +828,9 @@ static int mchp_sparx5_remove(struct platform_device *pdev)
sparx5->xtr_irq = -ENXIO;
}
sparx5_cleanup_ports(sparx5);
+ /* Unregister netdevs */
+ sparx5_unregister_notifier_blocks(sparx5);
+
return 0;
}
diff --git a/drivers/net/ethernet/microchip/sparx5/sparx5_main.h
b/drivers/net/ethernet/microchip/sparx5/sparx5_main.h
index d82700614abf..e427adad4555 100644
--- a/drivers/net/ethernet/microchip/sparx5/sparx5_main.h
+++ b/drivers/net/ethernet/microchip/sparx5/sparx5_main.h
@@ -133,9 +133,16 @@ struct sparx5 {
/* port structures are in net device */
struct sparx5_port *ports[SPX5_PORTS];
enum sparx5_core_clockfreq coreclock;
+ /* Notifiers */
+ struct notifier_block netdevice_nb;
+ struct notifier_block switchdev_nb;
+ struct notifier_block switchdev_blocking_nb;
/* Switch state */
u8 base_mac[ETH_ALEN];
+ /* Associated bridge device (when bridged) */
+ struct net_device *hw_bridge_dev;
/* Bridged interfaces */
+ DECLARE_BITMAP(bridge_mask, SPX5_PORTS);
DECLARE_BITMAP(bridge_fwd_mask, SPX5_PORTS);
DECLARE_BITMAP(bridge_lrn_mask, SPX5_PORTS);
DECLARE_BITMAP(vlan_mask[VLAN_N_VID], SPX5_PORTS);
@@ -151,6 +158,10 @@ struct sparx5 {
int xtr_irq;
};
+/* sparx5_switchdev.c */
+int sparx5_register_notifier_blocks(struct sparx5 *sparx5);
+void sparx5_unregister_notifier_blocks(struct sparx5 *sparx5);
+
/* sparx5_packet.c */
irqreturn_t sparx5_xtr_handler(int irq, void *_priv);
int sparx5_port_xmit_impl(struct sk_buff *skb, struct net_device *dev);
diff --git a/drivers/net/ethernet/microchip/sparx5/sparx5_netdev.c
b/drivers/net/ethernet/microchip/sparx5/sparx5_netdev.c
index 48512a59c887..6b0bfd512dfb 100644
--- a/drivers/net/ethernet/microchip/sparx5/sparx5_netdev.c
+++ b/drivers/net/ethernet/microchip/sparx5/sparx5_netdev.c
@@ -117,6 +117,15 @@ static int sparx5_
[PATCH net-next 08/10] net: sparx5: add calendar bandwidth allocation support
This configures the Sparx5 calendars according to the bandwidth
requested in the Device Tree nodes.
It also checks if the total requested bandwidth is within the
specs of the detected Sparx5 models limits.
Signed-off-by: Steen Hegelund
Signed-off-by: Bjarni Jonasson
Signed-off-by: Lars Povlsen
---
.../net/ethernet/microchip/sparx5/Makefile| 2 +-
.../microchip/sparx5/sparx5_calendar.c| 596 ++
.../ethernet/microchip/sparx5/sparx5_main.c | 9 +-
.../ethernet/microchip/sparx5/sparx5_main.h | 4 +
4 files changed, 609 insertions(+), 2 deletions(-)
create mode 100644 drivers/net/ethernet/microchip/sparx5/sparx5_calendar.c
diff --git a/drivers/net/ethernet/microchip/sparx5/Makefile
b/drivers/net/ethernet/microchip/sparx5/Makefile
index d2788e8b7798..e7dea25eb479 100644
--- a/drivers/net/ethernet/microchip/sparx5/Makefile
+++ b/drivers/net/ethernet/microchip/sparx5/Makefile
@@ -7,4 +7,4 @@ obj-$(CONFIG_SPARX5_SWITCH) += sparx5-switch.o
sparx5-switch-objs := sparx5_main.o sparx5_packet.o \
sparx5_netdev.o sparx5_port.o sparx5_phylink.o sparx5_mactable.o
sparx5_vlan.o \
- sparx5_switchdev.o
+ sparx5_switchdev.o sparx5_calendar.o
diff --git a/drivers/net/ethernet/microchip/sparx5/sparx5_calendar.c
b/drivers/net/ethernet/microchip/sparx5/sparx5_calendar.c
new file mode 100644
index ..76a8bb596aec
--- /dev/null
+++ b/drivers/net/ethernet/microchip/sparx5/sparx5_calendar.c
@@ -0,0 +1,596 @@
+// SPDX-License-Identifier: GPL-2.0+
+/* Microchip Sparx5 Switch driver
+ *
+ * Copyright (c) 2021 Microchip Technology Inc. and its subsidiaries.
+ */
+
+#include
+#include
+
+#include "sparx5_main_regs.h"
+#include "sparx5_main.h"
+
+/* QSYS calendar information */
+#define SPX5_PORTS_PER_CALREG 10 /* Ports mapped in a calendar
register */
+#define SPX5_CALBITS_PER_PORT 3 /* Bit per port in calendar
register */
+
+/* DSM calendar information */
+#define SPX5_DSM_CAL_LEN 64
+#define SPX5_DSM_CAL_EMPTY 0x
+#define SPX5_DSM_CAL_MAX_DEVS_PER_TAXI 13
+#define SPX5_DSM_CAL_TAXIS 8
+#define SPX5_DSM_CAL_BW_LOSS 553
+
+#define SPX5_TAXI_PORT_MAX 70
+
+#define SPEED_1250012500
+
+/* Maps from taxis to port numbers */
+static u32
sparx5_taxi_ports[SPX5_DSM_CAL_TAXIS][SPX5_DSM_CAL_MAX_DEVS_PER_TAXI] = {
+ {57, 12, 0, 1, 2, 16, 17, 18, 19, 20, 21, 22, 23},
+ {58, 13, 3, 4, 5, 24, 25, 26, 27, 28, 29, 30, 31},
+ {59, 14, 6, 7, 8, 32, 33, 34, 35, 36, 37, 38, 39},
+ {60, 15, 9, 10, 11, 40, 41, 42, 43, 44, 45, 46, 47},
+ {61, 48, 49, 50, 99, 99, 99, 99, 99, 99, 99, 99, 99},
+ {62, 51, 52, 53, 99, 99, 99, 99, 99, 99, 99, 99, 99},
+ {56, 63, 54, 55, 99, 99, 99, 99, 99, 99, 99, 99, 99},
+ {64, 99, 99, 99, 99, 99, 99, 99, 99, 99, 99, 99, 99},
+};
+
+struct sparx5_calendar_data {
+ u32 schedule[SPX5_DSM_CAL_LEN];
+ u32 avg_dist[SPX5_DSM_CAL_MAX_DEVS_PER_TAXI];
+ u32 taxi_ports[SPX5_DSM_CAL_MAX_DEVS_PER_TAXI];
+ u32 taxi_speeds[SPX5_DSM_CAL_MAX_DEVS_PER_TAXI];
+ u32 dev_slots[SPX5_DSM_CAL_MAX_DEVS_PER_TAXI];
+ u32 new_slots[SPX5_DSM_CAL_LEN];
+ u32 temp_sched[SPX5_DSM_CAL_LEN];
+ u32 indices[SPX5_DSM_CAL_LEN];
+ u32 short_list[SPX5_DSM_CAL_LEN];
+ u32 long_list[SPX5_DSM_CAL_LEN];
+};
+
+static u32 sparx5_target_bandwidth(struct sparx5 *sparx5)
+{
+ switch (sparx5->target_ct) {
+ case SPX5_TARGET_CT_7546:
+ case SPX5_TARGET_CT_7546TSN:
+ return 65000;
+ case SPX5_TARGET_CT_7549:
+ case SPX5_TARGET_CT_7549TSN:
+ return 91000;
+ case SPX5_TARGET_CT_7552:
+ case SPX5_TARGET_CT_7552TSN:
+ return 129000;
+ case SPX5_TARGET_CT_7556:
+ case SPX5_TARGET_CT_7556TSN:
+ return 161000;
+ case SPX5_TARGET_CT_7558:
+ case SPX5_TARGET_CT_7558TSN:
+ return 201000;
+ default:
+ return 0;
+ }
+}
+
+/* This is used in calendar configuration */
+enum sparx5_cal_bw {
+ SPX5_CAL_SPEED_NONE = 0,
+ SPX5_CAL_SPEED_1G = 1,
+ SPX5_CAL_SPEED_2G5 = 2,
+ SPX5_CAL_SPEED_5G = 3,
+ SPX5_CAL_SPEED_10G = 4,
+ SPX5_CAL_SPEED_25G = 5,
+ SPX5_CAL_SPEED_0G5 = 6,
+ SPX5_CAL_SPEED_12G5 = 7
+};
+
+static u32 sparx5_clk_to_bandwidth(enum sparx5_core_clockfreq cclock)
+{
+ switch (cclock) {
+ case SPX5_CORE_CLOCK_250MHZ: return 83000; /* 25 / 3 */
+ case SPX5_CORE_CLOCK_500MHZ: return 166000; /* 50 / 3 */
+ case SPX5_CORE_CLOCK_625MHZ: return 208000; /* 625000 / 3 */
+ default: return 0;
+ }
+ return 0;
+}
+
+static u32 sparx5_cal_speed_to_value(enum sparx5_cal_bw speed)
+{
+ switch (speed) {
+ case SPX5_CAL_SPEED_1G: return 1000;
+ case SPX5_CAL_SPEED_2G5: return 2500;
+ case SPX5_CAL_SPEED_5G: re
[PATCH net-next 09/10] net: sparx5: add ethtool configuration and statistics support
This adds statistic counters for the network interfaces provided
by the driver. It also adds CPU port counters (which are not
exposed by ethtool).
This also adds support for configuring the network interface
parameters via ethtool: speed, duplex, aneg etc.
Signed-off-by: Steen Hegelund
Signed-off-by: Bjarni Jonasson
Signed-off-by: Lars Povlsen
---
.../net/ethernet/microchip/sparx5/Makefile| 2 +-
.../microchip/sparx5/sparx5_ethtool.c | 999 ++
.../ethernet/microchip/sparx5/sparx5_main.c | 4 +
.../ethernet/microchip/sparx5/sparx5_main.h | 12 +
.../ethernet/microchip/sparx5/sparx5_netdev.c | 2 +
5 files changed, 1018 insertions(+), 1 deletion(-)
create mode 100644 drivers/net/ethernet/microchip/sparx5/sparx5_ethtool.c
diff --git a/drivers/net/ethernet/microchip/sparx5/Makefile
b/drivers/net/ethernet/microchip/sparx5/Makefile
index e7dea25eb479..5df99f9a12e9 100644
--- a/drivers/net/ethernet/microchip/sparx5/Makefile
+++ b/drivers/net/ethernet/microchip/sparx5/Makefile
@@ -7,4 +7,4 @@ obj-$(CONFIG_SPARX5_SWITCH) += sparx5-switch.o
sparx5-switch-objs := sparx5_main.o sparx5_packet.o \
sparx5_netdev.o sparx5_port.o sparx5_phylink.o sparx5_mactable.o
sparx5_vlan.o \
- sparx5_switchdev.o sparx5_calendar.o
+ sparx5_switchdev.o sparx5_calendar.o sparx5_ethtool.o
diff --git a/drivers/net/ethernet/microchip/sparx5/sparx5_ethtool.c
b/drivers/net/ethernet/microchip/sparx5/sparx5_ethtool.c
new file mode 100644
index ..5cbde50533b9
--- /dev/null
+++ b/drivers/net/ethernet/microchip/sparx5/sparx5_ethtool.c
@@ -0,0 +1,999 @@
+// SPDX-License-Identifier: GPL-2.0+
+/* Microchip Sparx5 Switch driver
+ *
+ * Copyright (c) 2021 Microchip Technology Inc. and its subsidiaries.
+ */
+
+#include
+
+#include "sparx5_main_regs.h"
+#include "sparx5_main.h"
+#include "sparx5_port.h"
+
+/* Index of ANA_AC port counters */
+#define SPX5_PORT_POLICER_DROPS 0
+
+/* Add a potentially wrapping 32 bit value to a 64 bit counter */
+static void sparx5_update_counter(u64 *cnt, u32 val)
+{
+ if (val < (*cnt & U32_MAX))
+ *cnt += (u64)1 << 32; /* value has wrapped */
+
+ *cnt = (*cnt & ~(u64)U32_MAX) + val;
+}
+
+/* Get a set of Queue System statistics */
+static void sparx5_xqs_prio_stats(struct sparx5 *sparx5,
+ u32 addr,
+ u64 *stats)
+{
+ int idx;
+
+ for (idx = 0; idx < 2 * SPX5_PRIOS; ++idx, ++addr, ++stats)
+ sparx5_update_counter(stats, spx5_rd(sparx5, XQS_CNT(addr)));
+}
+
+#define SPX5_STAT_GET(sname)portstats[spx5_stats_##sname]
+#define SPX5_STAT_SUM(sname)(portstats[spx5_stats_##sname] + \
+portstats[spx5_stats_pmac_##sname])
+#define SPX5_STAT_XQS_PRIOS_COUNTER_SUM(sname)\
+ (portstats[spx5_stats_green_p0_##sname] + \
+ portstats[spx5_stats_green_p1_##sname] + \
+ portstats[spx5_stats_green_p2_##sname] + \
+ portstats[spx5_stats_green_p3_##sname] + \
+ portstats[spx5_stats_green_p4_##sname] + \
+ portstats[spx5_stats_green_p5_##sname] + \
+ portstats[spx5_stats_green_p6_##sname] + \
+ portstats[spx5_stats_green_p7_##sname] + \
+ portstats[spx5_stats_yellow_p0_##sname] + \
+ portstats[spx5_stats_yellow_p1_##sname] + \
+ portstats[spx5_stats_yellow_p2_##sname] + \
+ portstats[spx5_stats_yellow_p3_##sname] + \
+ portstats[spx5_stats_yellow_p4_##sname] + \
+ portstats[spx5_stats_yellow_p5_##sname] + \
+ portstats[spx5_stats_yellow_p6_##sname] + \
+ portstats[spx5_stats_yellow_p7_##sname])
+
+enum sparx5_stats_entry {
+ spx5_stats_rx_in_bytes,
+ spx5_stats_rx_symbol_err,
+ spx5_stats_rx_pause,
+ spx5_stats_rx_unsup_opcode,
+ spx5_stats_rx_ok_bytes,
+ spx5_stats_rx_bad_bytes,
+ spx5_stats_rx_unicast,
+ spx5_stats_rx_multicast,
+ spx5_stats_rx_broadcast,
+ spx5_stats_rx_crc_err,
+ spx5_stats_rx_undersize,
+ spx5_stats_rx_fragments,
+ spx5_stats_rx_inrangelen_err,
+ spx5_stats_rx_outofrangelen_err,
+ spx5_stats_rx_oversize,
+ spx5_stats_rx_jabbers,
+ spx5_stats_rx_size64,
+ spx5_stats_rx_size65_127,
+ spx5_stats_rx_size128_255,
+ spx5_stats_rx_size256_511,
+ spx5_stats_rx_size512_1023,
+ spx5_stats_rx_size1024_1518,
+ spx5_stats_rx_size1519_max,
+ spx5_stats_pmac_rx_symbol_err,
+ spx5_stats_pmac_rx_pause,
+ spx5_stats_pmac_rx_unsup_opcode,
+ spx5_stats_pmac_rx_ok_bytes,
+ spx5_stats_pmac_rx_bad_bytes,
+ spx5_stats_pmac_rx_unicast,
+ spx5_stats_pmac_rx_multicast,
+ spx5_stats_pmac_rx_broadcast,
+ spx5_stats_pmac_rx_crc_err,
+ spx5_stats_pmac_rx_undersize,
+ spx5_stats_pmac_rx_fragments,
+ spx5_stats_pmac_rx_inrangelen
[PATCH net-next 10/10] arm64: dts: sparx5: Add the Sparx5 switch node
This provides the configuration for the currently available evaluation
boards PCB134 and PCB135.
The series depends on the following series currently on their way
into the kernel:
- Sparx5 SerDes Driver
Link:
https://lore.kernel.org/r/20210218161451.3489955-1-steen.hegel...@microchip.com/
- Sparx5 Reset Driver
Link:
https://lore.kernel.org/r/20210416084054.2922327-1-steen.hegel...@microchip.com/
- Serial GPIO Controller
Link:
https://lore.kernel.org/r/20201113145151.68900-1-lars.povl...@microchip.com/
Signed-off-by: Steen Hegelund
Signed-off-by: Lars Povlsen
Signed-off-by: Bjarni Jonasson
---
arch/arm64/boot/dts/microchip/sparx5.dtsi | 94 ++-
.../dts/microchip/sparx5_pcb134_board.dtsi| 481 --
.../dts/microchip/sparx5_pcb135_board.dtsi| 621 +-
3 files changed, 1112 insertions(+), 84 deletions(-)
diff --git a/arch/arm64/boot/dts/microchip/sparx5.dtsi
b/arch/arm64/boot/dts/microchip/sparx5.dtsi
index d64621d1213b..ad07fff40544 100644
--- a/arch/arm64/boot/dts/microchip/sparx5.dtsi
+++ b/arch/arm64/boot/dts/microchip/sparx5.dtsi
@@ -135,9 +135,12 @@ mux: mux-controller {
};
};
- reset@611010008 {
- compatible = "microchip,sparx5-chip-reset";
+ reset: reset-controller@611010008 {
+ compatible = "microchip,sparx5-switch-reset";
reg = <0x6 0x11010008 0x4>;
+ reg-names = "gcb";
+ #reset-cells = <1>;
+ cpu-syscon = <&cpu_ctrl>;
};
uart0: serial@60010 {
@@ -275,6 +278,21 @@ emmc_pins: emmc-pins {
"GPIO_46", "GPIO_47";
function = "emmc";
};
+
+ miim1_pins: miim1-pins {
+ pins = "GPIO_56", "GPIO_57";
+ function = "miim";
+ };
+
+ miim2_pins: miim2-pins {
+ pins = "GPIO_58", "GPIO_59";
+ function = "miim";
+ };
+
+ miim3_pins: miim3-pins {
+ pins = "GPIO_52", "GPIO_53";
+ function = "miim";
+ };
};
sgpio0: gpio@61101036c {
@@ -285,6 +303,8 @@ sgpio0: gpio@61101036c {
clocks = <&sys_clk>;
pinctrl-0 = <&sgpio0_pins>;
pinctrl-names = "default";
+ resets = <&reset 0>;
+ reset-names = "switch";
reg = <0x6 0x1101036c 0x100>;
sgpio_in0: gpio@0 {
compatible = "microchip,sparx5-sgpio-bank";
@@ -292,6 +312,9 @@ sgpio_in0: gpio@0 {
gpio-controller;
#gpio-cells = <3>;
ngpios = <96>;
+ interrupts = ;
+ interrupt-controller;
+ #interrupt-cells = <3>;
};
sgpio_out0: gpio@1 {
compatible = "microchip,sparx5-sgpio-bank";
@@ -310,6 +333,8 @@ sgpio1: gpio@611010484 {
clocks = <&sys_clk>;
pinctrl-0 = <&sgpio1_pins>;
pinctrl-names = "default";
+ resets = <&reset 0>;
+ reset-names = "switch";
reg = <0x6 0x11010484 0x100>;
sgpio_in1: gpio@0 {
compatible = "microchip,sparx5-sgpio-bank";
@@ -317,6 +342,9 @@ sgpio_in1: gpio@0 {
gpio-controller;
#gpio-cells = <3>;
ngpios = <96>;
+ interrupts = ;
+ interrupt-controller;
+ #interrupt-cells = <3>;
};
sgpio_out1: gpio@1 {
compatible = "microchip,sparx5-sgpio-bank";
@@ -335,6 +363,8 @@ sgpio2: gpio@61101059c {
clocks = <&sys_clk>;
pinctrl-0 = <&sgpio2_pins>;
pinctrl-names = "default";
+
Re: [PATCH v15 2/4] phy: Add media type and speed serdes configuration interfaces
Hi Leon,
On Sun, 2021-02-21 at 07:59 +0200, Leon Romanovsky wrote:
> EXTERNAL EMAIL: Do not click links or open attachments unless you
> know the content is safe
>
> On Thu, Feb 18, 2021 at 05:14:49PM +0100, Steen Hegelund wrote:
> > Provide new phy configuration interfaces for media type and speed
> > that
> > allows e.g. PHYs used for ethernet to be configured with this
> > information.
> >
> > Signed-off-by: Lars Povlsen
> > Signed-off-by: Steen Hegelund
> > Reviewed-by: Andrew Lunn
> > Reviewed-by: Alexandre Belloni
> > ---
> >
...
> > int phy_validate(struct phy *phy, enum phy_mode mode, int submode,
> > union phy_configure_opts *opts);
> > @@ -344,6 +356,20 @@ static inline int phy_set_mode_ext(struct phy
> > *phy, enum phy_mode mode,
> > #define phy_set_mode(phy, mode) \
> > phy_set_mode_ext(phy, mode, 0)
> >
> > +static inline int phy_set_media(struct phy *phy, enum phy_media
> > media)
> > +{
> > + if (!phy)
> > + return 0;
>
> I'm curious, why do you check for the NULL in all newly introduced
> functions?
> How is it possible that calls to phy_*() supply NULL as the main
> struct?
>
> Thanks
I do not know the history of that, but all the functions in the
interface that takes a phy as input and returns a status follow that
pattern. Maybe Kishon and Vinod knows the origin?
>
> > + return -ENODEV;
> > +}
> > +
> > +static inline int phy_set_speed(struct phy *phy, int speed)
> > +{
> > + if (!phy)
> > + return 0;
> > + return -ENODEV;
> > +}
> > +
> > static inline enum phy_mode phy_get_mode(struct phy *phy)
> > {
> > return PHY_MODE_INVALID;
> > --
> > 2.30.0
> >
Best Regards
Steen
Re: [PATCH v9 3/4] phy: Add Sparx5 ethernet serdes PHY driver
* * Returns: 0 if the configuration can be applied, an negative * error code otherwise */ So why are returning link up information? Yes that was a bit of a hijacking of the function. I will remove that. I also removed the dependency on this behaviour in the client driver in the meantime. I think a status function on the generic phy would be useful, but I will take that as separate issue. Andrew Thanks for the comments. BR Steen --- Steen Hegelund steen.hegel...@microchip.com
Re: [PATCH v9 3/4] phy: Add Sparx5 ethernet serdes PHY driver
On 10.12.2020 15:16, Andrew Lunn wrote: EXTERNAL EMAIL: Do not click links or open attachments unless you know the content is safe > So why are returning link up information? Yes that was a bit of a hijacking of the function. I will remove that. I also removed the dependency on this behaviour in the client driver in the meantime. I think a status function on the generic phy would be useful, but I will take that as separate issue. In this context of an Ethernet SERDES, do you actually need it? You would normally look at the PCS link status to determine if the link is up. But it is useful debug information. If the PCS is down, but the PHY indicates up, you can guess you have a protocol misconfiguration. Yes - you are probably right about that. I have been exposing this via a procfs interface during the development phase, and it was really useful to have, to track down the origin of the problem in certain situations. But on a system level, the PCS link would have the final say anyway. What exactly does link at this level mean? And thinking of the wider uses of the PHY subsystem, what would link mean at this level for SATA, PCIe, USB? Don't these all have some protocol level above similar to Ethernet PCS which is the real determiner of link? Yes - I think this is really only a debug feature. No need to force this on the other PHY categories. Andrew Thanks for your comments, Andrew. BR Steen --- Steen Hegelund steen.hegel...@microchip.com
Re: [PATCH v2 3/4] phy: Add Sparx5 ethernet serdes PHY driver
On 19.11.2020 11:44, Vinod Koul wrote: EXTERNAL EMAIL: Do not click links or open attachments unless you know the content is safe On 10-11-20, 15:49, Steen Hegelund wrote: Add the Microchip Sparx5 ethernet serdes PHY driver for the 6G, 10G and 25G interfaces available in the Sparx5 SoC. Signed-off-by: Bjarni Jonasson Signed-off-by: Steen Hegelund --- drivers/phy/Kconfig|1 + drivers/phy/Makefile |1 + drivers/phy/microchip/Kconfig | 12 + drivers/phy/microchip/Makefile |6 + drivers/phy/microchip/sparx5_serdes.c | 2464 + drivers/phy/microchip/sparx5_serdes_regs.h | 2773 6 files changed, 5257 insertions(+) create mode 100644 drivers/phy/microchip/Kconfig create mode 100644 drivers/phy/microchip/Makefile create mode 100644 drivers/phy/microchip/sparx5_serdes.c create mode 100644 drivers/phy/microchip/sparx5_serdes_regs.h diff --git a/drivers/phy/Kconfig b/drivers/phy/Kconfig index 01b53f86004c..ef0d17829610 100644 --- a/drivers/phy/Kconfig +++ b/drivers/phy/Kconfig @@ -71,6 +71,7 @@ source "drivers/phy/marvell/Kconfig" source "drivers/phy/mediatek/Kconfig" source "drivers/phy/motorola/Kconfig" source "drivers/phy/mscc/Kconfig" +source "drivers/phy/microchip/Kconfig" Sorted please I will update the list. source "drivers/phy/qualcomm/Kconfig" source "drivers/phy/ralink/Kconfig" source "drivers/phy/renesas/Kconfig" diff --git a/drivers/phy/Makefile b/drivers/phy/Makefile index 6eb2916773c5..822040e1aaa7 100644 --- a/drivers/phy/Makefile +++ b/drivers/phy/Makefile @@ -21,6 +21,7 @@ obj-y += allwinner/ \ mediatek/\ motorola/\ mscc/\ +microchip/ \ Here as well OK qualcomm/\ ralink/ \ renesas/ \ ... 2.29.2 -- ~Vinod BR Steen --- Steen Hegelund steen.hegel...@microchip.com
[PATCH v3 0/4] Adding the Sparx5 Serdes driver
Adding the Sparx5 Serdes driver This series of patches provides the serdes driver for the Microchip Sparx5 ethernet switch. The serdes driver supports the 10G and 25G serdes instances available in the Sparx5. The Sparx5 serdes support several interface modes with several speeds and also allows the client to change the mode and the speed according to changing in the environment such as changing cables from DAC to fiber. The serdes driver is to be used by the Sparx5 switchdev driver that will follow in subsequent series. History: v2 -> v3: - Sorted the Kconfig sourced folders - Sorted the Makefile included folders - Changed the configuration interface documentation to use kernel style v1 -> v2: Fixed kernel test robot warnings - Made these structures static: - media_presets_25g - mode_presets_25g - media_presets_10g - mode_presets_10g - Removed these duplicate initializations: - sparx5_sd25g28_params.cfg_rx_reserve_15_8 - sparx5_sd25g28_params.cfg_pi_en - sparx5_sd25g28_params.cfg_cdrck_en - sparx5_sd10g28_params.cfg_cdrck_en Lars Povlsen (2): dt-bindings: phy: Add sparx5-serdes bindings arm64: dts: sparx5: Add Sparx5 serdes driver node Steen Hegelund (2): phy: Add ethernet serdes configuration option phy: Add Sparx5 ethernet serdes PHY driver .../bindings/phy/microchip,sparx5-serdes.yaml | 283 ++ arch/arm64/boot/dts/microchip/sparx5.dtsi | 195 ++ drivers/phy/Kconfig |3 +- drivers/phy/Makefile |1 + drivers/phy/microchip/Kconfig | 12 + drivers/phy/microchip/Makefile|6 + drivers/phy/microchip/sparx5_serdes.c | 2464 +++ drivers/phy/microchip/sparx5_serdes_regs.h| 2773 + include/linux/phy/phy-ethernet-serdes.h | 33 + include/linux/phy/phy.h |4 + 10 files changed, 5773 insertions(+), 1 deletion(-) create mode 100644 Documentation/devicetree/bindings/phy/microchip,sparx5-serdes.yaml create mode 100644 drivers/phy/microchip/Kconfig create mode 100644 drivers/phy/microchip/Makefile create mode 100644 drivers/phy/microchip/sparx5_serdes.c create mode 100644 drivers/phy/microchip/sparx5_serdes_regs.h create mode 100644 include/linux/phy/phy-ethernet-serdes.h base-commit: 3cea11cd5e3b00d91caf0b4730194039b45c5891 prerequisite-patch-id: b155844f6a5e402ba62a39b1a2b276c8378eeb49 prerequisite-patch-id: 1605ab05e4212d0bba88a858c6dd16df64194282 prerequisite-patch-id: 8d9741ec8a716b179e39d640b3aab8f934c2573d -- 2.29.2
[PATCH v3 1/4] dt-bindings: phy: Add sparx5-serdes bindings
Document the Sparx5 ethernet serdes phy driver bindings.
Signed-off-by: Lars Povlsen
Signed-off-by: Steen Hegelund
---
.../bindings/phy/microchip,sparx5-serdes.yaml | 283 ++
1 file changed, 283 insertions(+)
create mode 100644
Documentation/devicetree/bindings/phy/microchip,sparx5-serdes.yaml
diff --git a/Documentation/devicetree/bindings/phy/microchip,sparx5-serdes.yaml
b/Documentation/devicetree/bindings/phy/microchip,sparx5-serdes.yaml
new file mode 100644
index ..a3a5b68f0a43
--- /dev/null
+++ b/Documentation/devicetree/bindings/phy/microchip,sparx5-serdes.yaml
@@ -0,0 +1,283 @@
+# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/phy/microchip,sparx5-serdes.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Microchip Sparx5 Serdes controller
+
+maintainers:
+ - Steen Hegelund
+
+description: |
+ The Sparx5 SERDES interfaces share the same basic functionality, but
+ support different operating modes and line rates.
+
+ The following list lists the SERDES features:
+
+ * RX Adaptive Decision Feedback Equalizer (DFE)
+ * Programmable continuous time linear equalizer (CTLE)
+ * Rx variable gain control
+ * Rx built-in fault detector (loss-of-lock/loss-of-signal)
+ * Adjustable tx de-emphasis (FFE)
+ * Tx output amplitude control
+ * Supports rx eye monitor
+ * Multiple loopback modes
+ * Prbs generator and checker
+ * Polarity inversion control
+
+ SERDES6G:
+
+ The SERDES6G is a high-speed SERDES interface, which can operate at
+ the following data rates:
+
+ * 100 Mbps (100BASE-FX)
+ * 1.25 Gbps (SGMII/1000BASE-X/1000BASE-KX)
+ * 3.125 Gbps (2.5GBASE-X/2.5GBASE-KX)
+ * 5.15625 Gbps (5GBASE-KR/5G-USXGMII)
+
+ SERDES10G
+
+ The SERDES10G is a high-speed SERDES interface, which can operate at
+ the following data rates:
+
+ * 100 Mbps (100BASE-FX)
+ * 1.25 Gbps (SGMII/1000BASE-X/1000BASE-KX)
+ * 3.125 Gbps (2.5GBASE-X/2.5GBASE-KX)
+ * 5 Gbps (QSGMII/USGMII)
+ * 5.15625 Gbps (5GBASE-KR/5G-USXGMII)
+ * 10 Gbps (10G-USGMII)
+ * 10.3125 Gbps (10GBASE-R/10GBASE-KR/USXGMII)
+
+ SERDES25G
+
+ The SERDES25G is a high-speed SERDES interface, which can operate at
+ the following data rates:
+
+ * 1.25 Gbps (SGMII/1000BASE-X/1000BASE-KX)
+ * 3.125 Gbps (2.5GBASE-X/2.5GBASE-KX)
+ * 5 Gbps (QSGMII/USGMII)
+ * 5.15625 Gbps (5GBASE-KR/5G-USXGMII)
+ * 10 Gbps (10G-USGMII)
+ * 10.3125 Gbps (10GBASE-R/10GBASE-KR/USXGMII)
+ * 25.78125 Gbps (25GBASE-KR/25GBASE-CR/25GBASE-SR/25GBASE-LR/25GBASE-ER)
+
+properties:
+ $nodename:
+pattern: "^serdes@[0-9a-f]+$"
+
+ compatible:
+const: microchip,sparx5-serdes.yaml
+
+ reg:
+description: Address and length of the register set for the device
+
+ '#phy-cells':
+const: 1
+description: |
+ - The main serdes input port
+
+required:
+ - compatible
+ - reg
+ - '#phy-cells'
+
+additionalProperties: false
+
+examples:
+ - |
+serdes: serdes@10808000 {
+ compatible = "microchip,sparx5-serdes";
+ #phy-cells = <1>;
+ reg = <0x10808000 0x8000>, /* sd_cmu_0 */
+<0x1081 0x8000>, /* sd_cmu_1 */
+<0x10818000 0x8000>, /* sd_cmu_2 */
+<0x1082 0x8000>, /* sd_cmu_3 */
+<0x10828000 0x8000>, /* sd_cmu_4 */
+<0x1083 0x8000>, /* sd_cmu_5 */
+<0x10838000 0x8000>, /* sd_cmu_6 */
+<0x1084 0x8000>, /* sd_cmu_7 */
+<0x10848000 0x8000>, /* sd_cmu_8 */
+<0x1085 0x8000>, /* sd_cmu_cfg_0 */
+<0x10858000 0x8000>, /* sd_cmu_cfg_1 */
+<0x1086 0x8000>, /* sd_cmu_cfg_2 */
+<0x10868000 0x8000>, /* sd_cmu_cfg_3 */
+<0x1087 0x8000>, /* sd_cmu_cfg_4 */
+<0x10878000 0x8000>, /* sd_cmu_cfg_5 */
+<0x1088 0x8000>, /* sd_cmu_cfg_6 */
+<0x10888000 0x8000>, /* sd_cmu_cfg_7 */
+<0x1089 0x8000>, /* sd_cmu_cfg_8 */
+<0x10898000 0x8000>, /* sd6g_lane_0 */
+<0x108a 0x8000>, /* sd6g_lane_1 */
+<0x108a8000 0x8000>, /* sd6g_lane_2 */
+<0x108b 0x8000>, /* sd6g_lane_3 */
+<0x108b8000 0x8000>, /* sd6g_lane_4 */
+<0x108c 0x8000>, /* sd6g_lane_5 */
+<0x108c8000 0x8000>, /* sd6g_lane_6 */
+<0x108d 0x8000>, /* sd6g_lane_7 */
+<0x108d8000 0x8000>, /* sd6g_lane_8 */
+<0x108e 0x8000>, /* sd6g_lane_9 */
+<0x108e8000 0x8000>, /* sd6g_lane_10 */
+<0x108f 0x8000>, /* sd6g_lane_11 */
+<0x108f8000 0x8000>, /* sd6g_lane_12 */
+<0x1090 0x8000>, /* sd10g_lane_0 */
+<0x10908000 0x8000>, /* sd10g_lane_1 */
+<0x1091 0x8000>, /* sd10g_lane_2 */
+<0x10918000 0
[PATCH v3 2/4] phy: Add ethernet serdes configuration option
Provide a new ethernet phy configuration structure, that
allow PHYs used for ethernet to be configured with
speed, media type and clock information.
Signed-off-by: Lars Povlsen
Signed-off-by: Steen Hegelund
---
include/linux/phy/phy-ethernet-serdes.h | 33 +
include/linux/phy/phy.h | 4 +++
2 files changed, 37 insertions(+)
create mode 100644 include/linux/phy/phy-ethernet-serdes.h
diff --git a/include/linux/phy/phy-ethernet-serdes.h
b/include/linux/phy/phy-ethernet-serdes.h
new file mode 100644
index ..b800ff22d93f
--- /dev/null
+++ b/include/linux/phy/phy-ethernet-serdes.h
@@ -0,0 +1,33 @@
+/* SPDX-License-Identifier: (GPL-2.0 OR MIT) */
+/*
+ * Microchip Sparx5 Ethernet SerDes driver
+ *
+ * Copyright (c) 2020 Microschip Inc
+ */
+#ifndef __PHY_ETHERNET_SERDES_H_
+#define __PHY_ETHERNET_SERDES_H_
+
+#include
+
+enum ethernet_media_type {
+ ETH_MEDIA_DEFAULT,
+ ETH_MEDIA_SR,
+ ETH_MEDIA_DAC,
+};
+
+/**
+ * struct phy_configure_opts_eth_serdes - Ethernet SerDes This structure is
used
+ * to represent the configuration state of a Ethernet Serdes PHY.
+ * @speed: Speed of the serdes interface in Mbps
+ * @media_type: Specifies which media the serdes will be using
+ * @clk: Specifies the serdes clock in MHz. Default: 0 will provide the highest
+ * supported clock.
+ */
+struct phy_configure_opts_eth_serdes {
+ u32speed;
+ enum ethernet_media_type media_type;
+ u32clk;
+};
+
+#endif
+
diff --git a/include/linux/phy/phy.h b/include/linux/phy/phy.h
index e435bdb0bab3..78ecb375cede 100644
--- a/include/linux/phy/phy.h
+++ b/include/linux/phy/phy.h
@@ -18,6 +18,7 @@
#include
#include
+#include
struct phy;
@@ -49,11 +50,14 @@ enum phy_mode {
*
* @mipi_dphy: Configuration set applicable for phys supporting
* the MIPI_DPHY phy mode.
+ * @eth_serdes: Configuration set applicable for phys supporting
+ * the ethernet serdes.
* @dp:Configuration set applicable for phys supporting
* the DisplayPort protocol.
*/
union phy_configure_opts {
struct phy_configure_opts_mipi_dphy mipi_dphy;
+ struct phy_configure_opts_eth_serdeseth_serdes;
struct phy_configure_opts_dpdp;
};
--
2.29.2
[PATCH v3 4/4] arm64: dts: sparx5: Add Sparx5 serdes driver node
From: Lars Povlsen
Add Sparx5 serdes driver node, and enable it generally for all
reference boards.
Signed-off-by: Lars Povlsen
Signed-off-by: Steen Hegelund
---
arch/arm64/boot/dts/microchip/sparx5.dtsi | 195 ++
1 file changed, 195 insertions(+)
diff --git a/arch/arm64/boot/dts/microchip/sparx5.dtsi
b/arch/arm64/boot/dts/microchip/sparx5.dtsi
index 8e7724d413fb..af927e0002ff 100644
--- a/arch/arm64/boot/dts/microchip/sparx5.dtsi
+++ b/arch/arm64/boot/dts/microchip/sparx5.dtsi
@@ -287,5 +287,200 @@ tmon0: tmon@610508110 {
#thermal-sensor-cells = <0>;
clocks = <&ahb_clk>;
};
+
+ serdes: serdes@10808000 {
+ compatible = "microchip,sparx5-serdes";
+ #phy-cells = <1>;
+ reg = <0x6 0x10808000 0x8000>, /* sd_cmu_0 */
+ <0x6 0x1081 0x8000>, /* sd_cmu_1 */
+ <0x6 0x10818000 0x8000>, /* sd_cmu_2 */
+ <0x6 0x1082 0x8000>, /* sd_cmu_3 */
+ <0x6 0x10828000 0x8000>, /* sd_cmu_4 */
+ <0x6 0x1083 0x8000>, /* sd_cmu_5 */
+ <0x6 0x10838000 0x8000>, /* sd_cmu_6 */
+ <0x6 0x1084 0x8000>, /* sd_cmu_7 */
+ <0x6 0x10848000 0x8000>, /* sd_cmu_8 */
+ <0x6 0x1085 0x8000>, /* sd_cmu_cfg_0 */
+ <0x6 0x10858000 0x8000>, /* sd_cmu_cfg_1 */
+ <0x6 0x1086 0x8000>, /* sd_cmu_cfg_2 */
+ <0x6 0x10868000 0x8000>, /* sd_cmu_cfg_3 */
+ <0x6 0x1087 0x8000>, /* sd_cmu_cfg_4 */
+ <0x6 0x10878000 0x8000>, /* sd_cmu_cfg_5 */
+ <0x6 0x1088 0x8000>, /* sd_cmu_cfg_6 */
+ <0x6 0x10888000 0x8000>, /* sd_cmu_cfg_7 */
+ <0x6 0x1089 0x8000>, /* sd_cmu_cfg_8 */
+ <0x6 0x10898000 0x8000>, /* sd6g_lane_0 */
+ <0x6 0x108a 0x8000>, /* sd6g_lane_1 */
+ <0x6 0x108a8000 0x8000>, /* sd6g_lane_2 */
+ <0x6 0x108b 0x8000>, /* sd6g_lane_3 */
+ <0x6 0x108b8000 0x8000>, /* sd6g_lane_4 */
+ <0x6 0x108c 0x8000>, /* sd6g_lane_5 */
+ <0x6 0x108c8000 0x8000>, /* sd6g_lane_6 */
+ <0x6 0x108d 0x8000>, /* sd6g_lane_7 */
+ <0x6 0x108d8000 0x8000>, /* sd6g_lane_8 */
+ <0x6 0x108e 0x8000>, /* sd6g_lane_9 */
+ <0x6 0x108e8000 0x8000>, /* sd6g_lane_10 */
+ <0x6 0x108f 0x8000>, /* sd6g_lane_11 */
+ <0x6 0x108f8000 0x8000>, /* sd6g_lane_12 */
+ <0x6 0x1090 0x8000>, /* sd10g_lane_0 */
+ <0x6 0x10908000 0x8000>, /* sd10g_lane_1 */
+ <0x6 0x1091 0x8000>, /* sd10g_lane_2 */
+ <0x6 0x10918000 0x8000>, /* sd10g_lane_3 */
+ <0x6 0x109a8000 0x8000>, /* sd_lane_0 */
+ <0x6 0x109b 0x8000>, /* sd_lane_1 */
+ <0x6 0x109b8000 0x8000>, /* sd_lane_2 */
+ <0x6 0x109c 0x8000>, /* sd_lane_3 */
+ <0x6 0x109c8000 0x8000>, /* sd_lane_4 */
+ <0x6 0x109d 0x8000>, /* sd_lane_5 */
+ <0x6 0x109d8000 0x8000>, /* sd_lane_6 */
+ <0x6 0x109e 0x8000>, /* sd_lane_7 */
+ <0x6 0x109e8000 0x8000>, /* sd_lane_8 */
+ <0x6 0x109f 0x8000>, /* sd_lane_9 */
+ <0x6 0x109f8000 0x8000>, /* sd_lane_10 */
+ <0x6 0x10a0 0x8000>, /* sd_lane_11 */
+ <0x6 0x10a08000 0x8000>, /* sd_lane_12 */
+ <0x6 0x10a1 0x8000>, /* sd_lane_13 */
+ <0x6 0x10a18000 0x8000>, /* sd_lane_14 */
+ <0x6 0x10a2 0x8000>, /* sd_lane_15 */
+
Re: [PATCH v2 2/4] phy: Add ethernet serdes configuration option
On 19.11.2020 11:37, Vinod Koul wrote:
EXTERNAL EMAIL: Do not click links or open attachments unless you know the
content is safe
On 10-11-20, 15:49, Steen Hegelund wrote:
Provide a new ethernet phy configuration structure, that
allow PHYs used for ethernet to be configured with
speed, media type and clock information.
Signed-off-by: Lars Povlsen
Signed-off-by: Steen Hegelund
---
include/linux/phy/phy-ethernet-serdes.h | 49 +
include/linux/phy/phy.h | 4 ++
2 files changed, 53 insertions(+)
create mode 100644 include/linux/phy/phy-ethernet-serdes.h
diff --git a/include/linux/phy/phy-ethernet-serdes.h
b/include/linux/phy/phy-ethernet-serdes.h
new file mode 100644
index ..04f496855b00
--- /dev/null
+++ b/include/linux/phy/phy-ethernet-serdes.h
@@ -0,0 +1,49 @@
+/* SPDX-License-Identifier: (GPL-2.0 OR MIT) */
+/*
+ * Microchip Sparx5 Ethernet SerDes driver
+ *
+ * Copyright (c) 2020 Microschip Inc
+ */
+#ifndef __PHY_ETHERNET_SERDES_H_
+#define __PHY_ETHERNET_SERDES_H_
+
+#include
+
+enum ethernet_media_type {
+ ETH_MEDIA_DEFAULT,
+ ETH_MEDIA_SR,
+ ETH_MEDIA_DAC,
+};
+
+/**
+ * struct phy_configure_opts_eth_serdes - Ethernet SerDes
+ *
+ * This structure is used to represent the configuration state of a
+ * Ethernet Serdes PHY.
+ */
+struct phy_configure_opts_eth_serdes {
+ /**
+ * @speed
+ *
+ * Speed of the serdes interface in Mbps
+ */
Can we have this in kernel-doc style pls
I will update the documentation.
+ u32speed;
+
+ /**
+ * @media_type
+ *
+ * Specifies which media the serdes will be using
+ */
+ enum ethernet_media_type media_type;
+
+ /**
+ * @clk
+ *
+ * Specifies the serdes clock in MHz
+ * Default: 0 will provide the highest supported clock.
+ */
+ u32clk;
Why not use std clk interface for this..?
I am not familiar with that. Is that the max_link_rate in struct phy_attrs?
+};
+
+#endif
+
diff --git a/include/linux/phy/phy.h b/include/linux/phy/phy.h
index e435bdb0bab3..78ecb375cede 100644
--- a/include/linux/phy/phy.h
+++ b/include/linux/phy/phy.h
@@ -18,6 +18,7 @@
#include
#include
+#include
struct phy;
@@ -49,11 +50,14 @@ enum phy_mode {
*
* @mipi_dphy: Configuration set applicable for phys supporting
* the MIPI_DPHY phy mode.
+ * @eth_serdes: Configuration set applicable for phys supporting
+ * the ethernet serdes.
* @dp: Configuration set applicable for phys supporting
* the DisplayPort protocol.
*/
union phy_configure_opts {
struct phy_configure_opts_mipi_dphy mipi_dphy;
+ struct phy_configure_opts_eth_serdeseth_serdes;
Kishon, does this look okay for you..?
struct phy_configure_opts_dpdp;
};
--
2.29.2
--
~Vinod
BR
Steen
---
Steen Hegelund
steen.hegel...@microchip.com
Re: [PATCH v2 2/4] phy: Add ethernet serdes configuration option
On 19.11.2020 15:43, Steen Hegelund wrote:
On 19.11.2020 11:37, Vinod Koul wrote:
EXTERNAL EMAIL: Do not click links or open attachments unless you know the
content is safe
On 10-11-20, 15:49, Steen Hegelund wrote:
Provide a new ethernet phy configuration structure, that
allow PHYs used for ethernet to be configured with
speed, media type and clock information.
Signed-off-by: Lars Povlsen
Signed-off-by: Steen Hegelund
---
include/linux/phy/phy-ethernet-serdes.h | 49 +
include/linux/phy/phy.h | 4 ++
2 files changed, 53 insertions(+)
create mode 100644 include/linux/phy/phy-ethernet-serdes.h
diff --git a/include/linux/phy/phy-ethernet-serdes.h
b/include/linux/phy/phy-ethernet-serdes.h
new file mode 100644
index ..04f496855b00
--- /dev/null
+++ b/include/linux/phy/phy-ethernet-serdes.h
@@ -0,0 +1,49 @@
+/* SPDX-License-Identifier: (GPL-2.0 OR MIT) */
+/*
+ * Microchip Sparx5 Ethernet SerDes driver
+ *
+ * Copyright (c) 2020 Microschip Inc
+ */
+#ifndef __PHY_ETHERNET_SERDES_H_
+#define __PHY_ETHERNET_SERDES_H_
+
+#include
+
+enum ethernet_media_type {
+ ETH_MEDIA_DEFAULT,
+ ETH_MEDIA_SR,
+ ETH_MEDIA_DAC,
+};
+
+/**
+ * struct phy_configure_opts_eth_serdes - Ethernet SerDes
+ *
+ * This structure is used to represent the configuration state of a
+ * Ethernet Serdes PHY.
+ */
+struct phy_configure_opts_eth_serdes {
+ /**
+ * @speed
+ *
+ * Speed of the serdes interface in Mbps
+ */
Can we have this in kernel-doc style pls
I will update the documentation.
+ u32speed;
+
+ /**
+ * @media_type
+ *
+ * Specifies which media the serdes will be using
+ */
+ enum ethernet_media_type media_type;
+
+ /**
+ * @clk
+ *
+ * Specifies the serdes clock in MHz
+ * Default: 0 will provide the highest supported clock.
+ */
+ u32clk;
Why not use std clk interface for this..?
I am not familiar with that. Is that the max_link_rate in struct phy_attrs?
Now I get it: A DT clock node referred by the SerDes: Yes that should be
possible. I will try that out...
+};
+
+#endif
+
diff --git a/include/linux/phy/phy.h b/include/linux/phy/phy.h
index e435bdb0bab3..78ecb375cede 100644
--- a/include/linux/phy/phy.h
+++ b/include/linux/phy/phy.h
@@ -18,6 +18,7 @@
#include
#include
+#include
struct phy;
@@ -49,11 +50,14 @@ enum phy_mode {
*
* @mipi_dphy: Configuration set applicable for phys supporting
* the MIPI_DPHY phy mode.
+ * @eth_serdes: Configuration set applicable for phys supporting
+ * the ethernet serdes.
* @dp: Configuration set applicable for phys supporting
* the DisplayPort protocol.
*/
union phy_configure_opts {
struct phy_configure_opts_mipi_dphy mipi_dphy;
+ struct phy_configure_opts_eth_serdeseth_serdes;
Kishon, does this look okay for you..?
struct phy_configure_opts_dpdp;
};
--
2.29.2
--
~Vinod
BR
Steen
---
Steen Hegelund
steen.hegel...@microchip.com
BR
Steen
---
Steen Hegelund
steen.hegel...@microchip.com
Re: [PATCH v2 1/4] dt-bindings: phy: Add sparx5-serdes bindings
On 19.11.2020 11:28, Vinod Koul wrote: EXTERNAL EMAIL: Do not click links or open attachments unless you know the content is safe On 10-11-20, 15:49, Steen Hegelund wrote: Document the Sparx5 ethernet serdes phy driver bindings. Rob ..? Also pls cc devicet...@vger.kernel.org Signed-off-by: Lars Povlsen Signed-off-by: Steen Hegelund --- .../bindings/phy/microchip,sparx5-serdes.yaml | 283 ++ 1 file changed, 283 insertions(+) create mode 100644 Documentation/devicetree/bindings/phy/microchip,sparx5-serdes.yaml diff --git a/Documentation/devicetree/bindings/phy/microchip,sparx5-serdes.yaml b/Documentation/devicetree/bindings/phy/microchip,sparx5-serdes.yaml new file mode 100644 index ..a3a5b68f0a43 --- /dev/null +++ b/Documentation/devicetree/bindings/phy/microchip,sparx5-serdes.yaml @@ -0,0 +1,283 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/phy/microchip,sparx5-serdes.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Microchip Sparx5 Serdes controller + +maintainers: + - Steen Hegelund + +description: | + The Sparx5 SERDES interfaces share the same basic functionality, but + support different operating modes and line rates. + + The following list lists the SERDES features: + + * RX Adaptive Decision Feedback Equalizer (DFE) + * Programmable continuous time linear equalizer (CTLE) + * Rx variable gain control + * Rx built-in fault detector (loss-of-lock/loss-of-signal) + * Adjustable tx de-emphasis (FFE) + * Tx output amplitude control + * Supports rx eye monitor + * Multiple loopback modes + * Prbs generator and checker + * Polarity inversion control + + SERDES6G: + + The SERDES6G is a high-speed SERDES interface, which can operate at + the following data rates: + + * 100 Mbps (100BASE-FX) + * 1.25 Gbps (SGMII/1000BASE-X/1000BASE-KX) + * 3.125 Gbps (2.5GBASE-X/2.5GBASE-KX) + * 5.15625 Gbps (5GBASE-KR/5G-USXGMII) + + SERDES10G + + The SERDES10G is a high-speed SERDES interface, which can operate at + the following data rates: + + * 100 Mbps (100BASE-FX) + * 1.25 Gbps (SGMII/1000BASE-X/1000BASE-KX) + * 3.125 Gbps (2.5GBASE-X/2.5GBASE-KX) + * 5 Gbps (QSGMII/USGMII) + * 5.15625 Gbps (5GBASE-KR/5G-USXGMII) + * 10 Gbps (10G-USGMII) + * 10.3125 Gbps (10GBASE-R/10GBASE-KR/USXGMII) + + SERDES25G + + The SERDES25G is a high-speed SERDES interface, which can operate at + the following data rates: + + * 1.25 Gbps (SGMII/1000BASE-X/1000BASE-KX) + * 3.125 Gbps (2.5GBASE-X/2.5GBASE-KX) + * 5 Gbps (QSGMII/USGMII) + * 5.15625 Gbps (5GBASE-KR/5G-USXGMII) + * 10 Gbps (10G-USGMII) + * 10.3125 Gbps (10GBASE-R/10GBASE-KR/USXGMII) + * 25.78125 Gbps (25GBASE-KR/25GBASE-CR/25GBASE-SR/25GBASE-LR/25GBASE-ER) + +properties: + $nodename: +pattern: "^serdes@[0-9a-f]+$" + + compatible: +const: microchip,sparx5-serdes.yaml + + reg: +description: Address and length of the register set for the device + + '#phy-cells': +const: 1 +description: | + - The main serdes input port + +required: + - compatible + - reg + - '#phy-cells' reg-names missing here I will add them. +}; + +... -- 2.29.2 -- ~Vinod BR Steen ------- Steen Hegelund steen.hegel...@microchip.com
[PATCH v4 2/4] phy: Add ethernet serdes configuration option
Provide a new ethernet phy configuration structure, that
allow PHYs used for ethernet to be configured with
speed, media type and clock information.
Signed-off-by: Lars Povlsen
Signed-off-by: Steen Hegelund
---
include/linux/phy/phy-ethernet-serdes.h | 30 +
include/linux/phy/phy.h | 4
2 files changed, 34 insertions(+)
create mode 100644 include/linux/phy/phy-ethernet-serdes.h
diff --git a/include/linux/phy/phy-ethernet-serdes.h
b/include/linux/phy/phy-ethernet-serdes.h
new file mode 100644
index ..e261aa29951c
--- /dev/null
+++ b/include/linux/phy/phy-ethernet-serdes.h
@@ -0,0 +1,30 @@
+/* SPDX-License-Identifier: (GPL-2.0 OR MIT) */
+/*
+ * Microchip Sparx5 Ethernet SerDes driver
+ *
+ * Copyright (c) 2020 Microschip Inc
+ */
+#ifndef __PHY_ETHERNET_SERDES_H_
+#define __PHY_ETHERNET_SERDES_H_
+
+#include
+
+enum ethernet_media_type {
+ ETH_MEDIA_DEFAULT,
+ ETH_MEDIA_SR,
+ ETH_MEDIA_DAC,
+};
+
+/**
+ * struct phy_configure_opts_eth_serdes - Ethernet SerDes This structure is
used
+ * to represent the configuration state of a Ethernet Serdes PHY.
+ * @speed: Speed of the serdes interface in Mbps
+ * @media_type: Specifies which media the serdes will be using
+ */
+struct phy_configure_opts_eth_serdes {
+ u32speed;
+ enum ethernet_media_type media_type;
+};
+
+#endif
+
diff --git a/include/linux/phy/phy.h b/include/linux/phy/phy.h
index e435bdb0bab3..78ecb375cede 100644
--- a/include/linux/phy/phy.h
+++ b/include/linux/phy/phy.h
@@ -18,6 +18,7 @@
#include
#include
+#include
struct phy;
@@ -49,11 +50,14 @@ enum phy_mode {
*
* @mipi_dphy: Configuration set applicable for phys supporting
* the MIPI_DPHY phy mode.
+ * @eth_serdes: Configuration set applicable for phys supporting
+ * the ethernet serdes.
* @dp:Configuration set applicable for phys supporting
* the DisplayPort protocol.
*/
union phy_configure_opts {
struct phy_configure_opts_mipi_dphy mipi_dphy;
+ struct phy_configure_opts_eth_serdeseth_serdes;
struct phy_configure_opts_dpdp;
};
--
2.29.2
