Re: [PATCH 3/3] crypto: hisilicon/sec - fixes shash test error

[Ard Biesheuvel]

On Sun, 7 Feb 2021 at 03:47, liulongfang  wrote:
>
> On 2021/2/5 19:44, Herbert Xu write:
> > On Fri, Feb 05, 2021 at 06:10:57PM +0800, Longfang Liu wrote:
> >> If this configuration item is not turned on,
> >> the allocation of crypto_tfm will fail when
> >> the shash algorithm calculates the hash
> >> through the software.
> >>
> >> Signed-off-by: Longfang Liu 
> >> ---
> >>  arch/arm64/configs/defconfig | 2 +-
> >>  1 file changed, 1 insertion(+), 1 deletion(-)
> >>
> >> diff --git a/arch/arm64/configs/defconfig b/arch/arm64/configs/defconfig
> >> index 8383016..7cfc9b6 100644
> >> --- a/arch/arm64/configs/defconfig
> >> +++ b/arch/arm64/configs/defconfig
> >> @@ -117,7 +117,7 @@ CONFIG_KVM=y
> >>  CONFIG_ARM64_CRYPTO=y
> >>  CONFIG_CRYPTO_SHA1_ARM64_CE=y
> >>  CONFIG_CRYPTO_SHA2_ARM64_CE=y
> >> -CONFIG_CRYPTO_SHA512_ARM64_CE=m
> >> +CONFIG_CRYPTO_SHA512_ARM64_CE=y
> >
> > If this is truly needed then it should be enabled through Kconfig.
> >
> > Cheers,
> >
> Hi Herbert,
> The option select CRYPTO_SHA512 already exists in Kconfig.

In that case, how can the shash TFM allocation fail?

> Can I change it to this: select CRYPTO_SHA512 || CRYPTO_SHA512_ARM64_CE

No, you cannot select expressions like that.

Could you please explain the problem you are trying to solve?

[PATCH v2] memory: tegra186-emc: Replace DEFINE_SIMPLE_ATTRIBUTE with DEFINE_DEBUGFS_ATTRIBUTE

[Jiapeng Chong]

Fix the following coccicheck warning:

drivers/memory/tegra/tegra186-emc.c:158:0-23: WARNING:
tegra186_emc_debug_max_rate_fops should be defined with
DEFINE_DEBUGFS_ATTRIBUTE.

drivers/memory/tegra/tegra186-emc.c:128:0-23: WARNING:
tegra186_emc_debug_min_rate_fops should be defined with
DEFINE_DEBUGFS_ATTRIBUTE.

Reported-by: Abaci Robot 
Signed-off-by: Jiapeng Chong 
---
Changes in v2:
  - Stripped unrelated parts of the paths (./). 

 drivers/memory/tegra/tegra186-emc.c | 12 ++--
 1 file changed, 6 insertions(+), 6 deletions(-)

diff --git a/drivers/memory/tegra/tegra186-emc.c 
b/drivers/memory/tegra/tegra186-emc.c
index fa8af17..d65e7c2 100644
--- a/drivers/memory/tegra/tegra186-emc.c
+++ b/drivers/memory/tegra/tegra186-emc.c
@@ -125,9 +125,9 @@ static int tegra186_emc_debug_min_rate_set(void *data, u64 
rate)
return 0;
 }
 
-DEFINE_SIMPLE_ATTRIBUTE(tegra186_emc_debug_min_rate_fops,
-   tegra186_emc_debug_min_rate_get,
-   tegra186_emc_debug_min_rate_set, "%llu\n");
+DEFINE_DEBUGFS_ATTRIBUTE(tegra186_emc_debug_min_rate_fops,
+ tegra186_emc_debug_min_rate_get,
+ tegra186_emc_debug_min_rate_set, "%llu\n");
 
 static int tegra186_emc_debug_max_rate_get(void *data, u64 *rate)
 {
@@ -155,9 +155,9 @@ static int tegra186_emc_debug_max_rate_set(void *data, u64 
rate)
return 0;
 }
 
-DEFINE_SIMPLE_ATTRIBUTE(tegra186_emc_debug_max_rate_fops,
-   tegra186_emc_debug_max_rate_get,
-   tegra186_emc_debug_max_rate_set, "%llu\n");
+DEFINE_DEBUGFS_ATTRIBUTE(tegra186_emc_debug_max_rate_fops,
+ tegra186_emc_debug_max_rate_get,
+ tegra186_emc_debug_max_rate_set, "%llu\n");
 
 static int tegra186_emc_probe(struct platform_device *pdev)
 {
-- 
1.8.3.1

Re: [PATCH 04/18] arm64: Kconfig: Introduce CONFIG_ARCH_APPLE

[Hector Martin 'marcan']

On 06/02/2021 22.17, Marc Zyngier wrote:

+config ARCH_APPLE
+   bool "Apple Silicon SoC family"
+   select GENERIC_IRQ_CHIP


nit: This is better selected by the interrupt controller that relies
on the generic irqchip infrastructure.


Ack, changed for v2.

--
Hector Martin "marcan" (mar...@marcan.st)
Public Key: https://mrcn.st/pub

Re: [RFC 9/9] x86/mm: Implement PR_SET/GET_TAGGED_ADDR_CTRL with LAM

[Dmitry Vyukov]

On Fri, Feb 5, 2021 at 4:43 PM H.J. Lu  wrote:
>
> On Fri, Feb 5, 2021 at 7:16 AM Kirill A. Shutemov
>  wrote:
> >
> > Provide prctl() interface to enabled LAM for user addresses. Depending
> > how many tag bits requested it may result in enabling LAM_U57 or
> > LAM_U48.
>
> I prefer the alternate kernel interface based on CET arch_prctl interface 
> which
> is implemented in glibc on users/intel/lam/master branch:
>
> https://gitlab.com/x86-glibc/glibc/-/tree/users/intel/lam/master
>
> and in GCC on users/intel/lam/master branch:
>
> https://gitlab.com/x86-gcc/gcc/-/tree/users/intel/lam/master

Hi Kirill, H.J.,

I don't have strong preference for PR_SET/GET_TAGGED_ADDR_CTRL vs
ARCH_X86_FEATURE_1_ENABLE itself, but tying LAM to ELF and
GNU_PROPERTY in the second option looks strange. LAM can be used
outside of ELF/GNU, right?

[PATCH v3 1/2] perf util: Change intlist int to unsigned long

[Jin Yao]

This is to let intlist support address.

One potential problem is it can't support negative number. But
so far, there is no such kind of use case.

Signed-off-by: Jin Yao 
---
 v3:
   No change.

 v2:
   New in v2.

 tools/perf/util/intlist.c | 27 ---
 tools/perf/util/intlist.h | 10 +-
 tools/perf/util/probe-event.c |  2 +-
 3 files changed, 22 insertions(+), 17 deletions(-)

diff --git a/tools/perf/util/intlist.c b/tools/perf/util/intlist.c
index 84e5304e151a..934092199f89 100644
--- a/tools/perf/util/intlist.c
+++ b/tools/perf/util/intlist.c
@@ -13,7 +13,7 @@
 static struct rb_node *intlist__node_new(struct rblist *rblist __maybe_unused,
 const void *entry)
 {
-   int i = (int)((long)entry);
+   unsigned long i = (unsigned long)entry;
struct rb_node *rc = NULL;
struct int_node *node = malloc(sizeof(*node));
 
@@ -41,15 +41,20 @@ static void intlist__node_delete(struct rblist *rblist 
__maybe_unused,
 
 static int intlist__node_cmp(struct rb_node *rb_node, const void *entry)
 {
-   int i = (int)((long)entry);
+   unsigned long i = (unsigned long)entry;
struct int_node *node = container_of(rb_node, struct int_node, rb_node);
 
-   return node->i - i;
+   if (node->i > i)
+   return 1;
+   else if (node->i < i)
+   return -1;
+
+   return 0;
 }
 
-int intlist__add(struct intlist *ilist, int i)
+int intlist__add(struct intlist *ilist, unsigned long i)
 {
-   return rblist__add_node(&ilist->rblist, (void *)((long)i));
+   return rblist__add_node(&ilist->rblist, (void *)i);
 }
 
 void intlist__remove(struct intlist *ilist, struct int_node *node)
@@ -58,7 +63,7 @@ void intlist__remove(struct intlist *ilist, struct int_node 
*node)
 }
 
 static struct int_node *__intlist__findnew(struct intlist *ilist,
-  int i, bool create)
+  unsigned long i, bool create)
 {
struct int_node *node = NULL;
struct rb_node *rb_node;
@@ -67,9 +72,9 @@ static struct int_node *__intlist__findnew(struct intlist 
*ilist,
return NULL;
 
if (create)
-   rb_node = rblist__findnew(&ilist->rblist, (void *)((long)i));
+   rb_node = rblist__findnew(&ilist->rblist, (void *)i);
else
-   rb_node = rblist__find(&ilist->rblist, (void *)((long)i));
+   rb_node = rblist__find(&ilist->rblist, (void *)i);
 
if (rb_node)
node = container_of(rb_node, struct int_node, rb_node);
@@ -77,12 +82,12 @@ static struct int_node *__intlist__findnew(struct intlist 
*ilist,
return node;
 }
 
-struct int_node *intlist__find(struct intlist *ilist, int i)
+struct int_node *intlist__find(struct intlist *ilist, unsigned long i)
 {
return __intlist__findnew(ilist, i, false);
 }
 
-struct int_node *intlist__findnew(struct intlist *ilist, int i)
+struct int_node *intlist__findnew(struct intlist *ilist, unsigned long i)
 {
return __intlist__findnew(ilist, i, true);
 }
@@ -93,7 +98,7 @@ static int intlist__parse_list(struct intlist *ilist, const 
char *s)
int err;
 
do {
-   long value = strtol(s, &sep, 10);
+   unsigned long value = strtol(s, &sep, 10);
err = -EINVAL;
if (*sep != ',' && *sep != '\0')
break;
diff --git a/tools/perf/util/intlist.h b/tools/perf/util/intlist.h
index 5c19ee001299..e336b174d0c7 100644
--- a/tools/perf/util/intlist.h
+++ b/tools/perf/util/intlist.h
@@ -9,7 +9,7 @@
 
 struct int_node {
struct rb_node rb_node;
-   int i;
+   unsigned long i;
void *priv;
 };
 
@@ -21,13 +21,13 @@ struct intlist *intlist__new(const char *slist);
 void intlist__delete(struct intlist *ilist);
 
 void intlist__remove(struct intlist *ilist, struct int_node *in);
-int intlist__add(struct intlist *ilist, int i);
+int intlist__add(struct intlist *ilist, unsigned long i);
 
 struct int_node *intlist__entry(const struct intlist *ilist, unsigned int idx);
-struct int_node *intlist__find(struct intlist *ilist, int i);
-struct int_node *intlist__findnew(struct intlist *ilist, int i);
+struct int_node *intlist__find(struct intlist *ilist, unsigned long i);
+struct int_node *intlist__findnew(struct intlist *ilist, unsigned long i);
 
-static inline bool intlist__has_entry(struct intlist *ilist, int i)
+static inline bool intlist__has_entry(struct intlist *ilist, unsigned long i)
 {
return intlist__find(ilist, i) != NULL;
 }
diff --git a/tools/perf/util/probe-event.c b/tools/perf/util/probe-event.c
index 8eae2afff71a..137f19c5b686 100644
--- a/tools/perf/util/probe-event.c
+++ b/tools/perf/util/probe-event.c
@@ -1074,7 +1074,7 @@ static int __show_line_range(struct line_range *lr, const 
char *module,
}
 
intlist__for_each_entry(ln, lr->line_list) {
-  

[PATCH v3 2/2] perf script: Support filtering by hex address

[Jin Yao]

Perf-script supports '-S' or '--symbol' options to only list the
trace records in given symbols. Symbol is typically a name
or hex address. If it's hex address, it is the start address of
one symbol.

While it would be useful if we can filter trace records by any hex
address (not only the start address of symbol). So now we support
filtering trace records by more conditions, such as:
- symbol name
- start address of symbol
- any hexadecimal address
- address range

The comparison order is defined as:

1. symbol name comparison
2. symbol start address comparison.
3. any hexadecimal address comparison.
4. address range comparison.

The idea is if we can get a valid address from -S list, we add the
address to addr_list for address comparison otherwise we still leave
it to sym_list for symbol comparison.

Some examples:

root@kbl-ppc:~# ./perf script -S 9a477308
perf  8562 [000] 347303.578858:  1   cycles:  
9a477308 native_write_msr+0x8 ([kernel.kallsyms])
perf  8562 [000] 347303.578860:  1   cycles:  
9a477308 native_write_msr+0x8 ([kernel.kallsyms])
perf  8562 [000] 347303.578861: 11   cycles:  
9a477308 native_write_msr+0x8 ([kernel.kallsyms])
perf  8562 [001] 347303.578903:  1   cycles:  
9a477308 native_write_msr+0x8 ([kernel.kallsyms])
perf  8562 [001] 347303.578905:  1   cycles:  
9a477308 native_write_msr+0x8 ([kernel.kallsyms])
perf  8562 [001] 347303.578906: 15   cycles:  
9a477308 native_write_msr+0x8 ([kernel.kallsyms])
perf  8562 [002] 347303.578952:  1   cycles:  
9a477308 native_write_msr+0x8 ([kernel.kallsyms])
perf  8562 [002] 347303.578953:  1   cycles:  
9a477308 native_write_msr+0x8 ([kernel.kallsyms])

Filter the traced records by hex address 9a477308.

root@kbl-ppc:~# ./perf script -S 
9a4dd4ce,9a4d2de9,9a6bf9f4
perf  8562 [001] 347303.578911: 311706   cycles:  
9a6bf9f4 __kmalloc_node+0x204 ([kernel.kallsyms])
perf  8562 [002] 347303.578960: 354477   cycles:  
9a4d2de9 sched_setaffinity+0x49 ([kernel.kallsyms])
perf  8562 [003] 347303.579015: 450958   cycles:  
9a4dd4ce dequeue_task_fair+0x1ae ([kernel.kallsyms])

Filter the traced records by hex address 9a4dd4ce, 9a4d2de9, 
9a6bf9f4.

root@kbl-ppc:~# ./perf script -S 9a477309 --addr-range 16
perf  8562 [000] 347303.578863:291   cycles:  
9a47730a native_write_msr+0xa ([kernel.kallsyms])
perf  8562 [001] 347303.578907:411   cycles:  
9a47730a native_write_msr+0xa ([kernel.kallsyms])
perf  8562 [002] 347303.578956:462   cycles:  
9a47730f native_write_msr+0xf ([kernel.kallsyms])
perf  8562 [003] 347303.579010:497   cycles:  
9a47730f native_write_msr+0xf ([kernel.kallsyms])
perf  8562 [004] 347303.579059:429   cycles:  
9a47730f native_write_msr+0xf ([kernel.kallsyms])
perf  8562 [005] 347303.579109:408   cycles:  
9a47730a native_write_msr+0xa ([kernel.kallsyms])
perf  8562 [006] 347303.579159:460   cycles:  
9a47730f native_write_msr+0xf ([kernel.kallsyms])
perf  8562 [007] 347303.579213:436   cycles:  
9a47730f native_write_msr+0xf ([kernel.kallsyms])

Filter the traced records from address range [9a477309, 
9a477309 + 15].

root@kbl-ppc:~# ./perf script -S "9b163046,rcu_nmi_exit"
perf  8562 [004] 347303.579060:  12013   cycles:  
9b163046 exc_nmi+0x166 ([kernel.kallsyms])
perf  8562 [007] 347303.579214:  12138   cycles:  
9b165944 rcu_nmi_exit+0x34 ([kernel.kallsyms])

Filter by address + symbol

Signed-off-by: Jin Yao 
---
 v3:
   Update setup_addrlist:
   1. Add more checks for strtoul (errno, space and etc). 
   2. Don't break when detect an invalid address, just save the
  valid address to addr_list. 

 v2:
   Use intlist for address list.

 tools/perf/Documentation/perf-script.txt | 19 +
 tools/perf/builtin-script.c  |  2 +
 tools/perf/util/event.c  | 24 
 tools/perf/util/symbol.c | 49 
 tools/perf/util/symbol_conf.h|  4 +-
 5 files changed, 97 insertions(+), 1 deletion(-)

diff --git a/tools/perf/Documentation/perf-script.txt 
b/tools/perf/Documentation/perf-script.txt
index 60dae302db27..4c37f193a231 100644
--- a/tools/perf/Documentation/perf-script.txt
+++ b/tools/perf/Documentation/perf-script.txt
@@ -422,9 +422,28 @@ include::itrace.txt[]
Only consider the listed symbols. Symbols are typically a name
but they may also be hexadecimal address.
 
+   The

Re: [kbuild-all] Re: [patch 06/12] x86/entry: Convert system vectors to irq stack macro

[Rong Chen]

On 2/5/21 10:13 PM, Peter Zijlstra wrote:

On Fri, Feb 05, 2021 at 11:52:40AM +0800, kernel test robot wrote:

Hi Thomas,

I love your patch! Perhaps something to improve:

[auto build test WARNING on tip/x86/asm]
[also build test WARNING on tip/master linus/master tip/x86/core v5.11-rc6 
next-20210125]
[If your patch is applied to the wrong git tree, kindly drop us a note.
And when submitting patch, we suggest to use '--base' as documented in
https://git-scm.com/docs/git-format-patch]

url:
https://github.com/0day-ci/linux/commits/Thomas-Gleixner/x86-irq-64-Inline-irq-stack-switching/20210205-091059
base:   https://git.kernel.org/pub/scm/linux/kernel/git/tip/tip.git 
5c99720b28381bb400d4f546734c34ddaf608761
config: x86_64-randconfig-r026-20210204 (attached as .config)
compiler: gcc-9 (Debian 9.3.0-15) 9.3.0
reproduce (this is a W=1 build):
 # 
https://github.com/0day-ci/linux/commit/d91ff58e804175dd59e483c7cf236e1fe66c2187
 git remote add linux-review https://github.com/0day-ci/linux
 git fetch --no-tags linux-review 
Thomas-Gleixner/x86-irq-64-Inline-irq-stack-switching/20210205-091059
 git checkout d91ff58e804175dd59e483c7cf236e1fe66c2187
 # save the attached .config to linux build tree
 make W=1 ARCH=x86_64

If you fix the issue, kindly add following tag as appropriate
Reported-by: kernel test robot 

All warnings (new ones prefixed by >>):


arch/x86/hyperv/hv_init.o: warning: objtool: 
sysvec_hyperv_reenlightenment()+0x7f: undefined stack state

--

arch/x86/kernel/cpu/mshyperv.o: warning: objtool: 
sysvec_hyperv_callback()+0x7f: undefined stack state
arch/x86/kernel/cpu/mshyperv.o: warning: objtool: sysvec_hyperv_stimer0()+0x7f: 
undefined stack state

It would help if you'd actually applied the patches to a tree that had
the required objtool patches as described in 0/n. Or better yet, don't
scrape emails if the 0/n includes a git link which you'll run on anyway.


Hi Peter,

Thanks for the advice, we'll add the check to our cluster,
and sorry for the inconvenience.

Best Regards,
Rong Chen

Re: [RFC PATCH 04/11] iommu/arm-smmu-v3: Split block descriptor to a span of page

[Keqian Zhu]

Hi Robin,

On 2021/2/5 3:51, Robin Murphy wrote:
> On 2021-01-28 15:17, Keqian Zhu wrote:
>> From: jiangkunkun 
>>
>> Block descriptor is not a proper granule for dirty log tracking. This
>> adds a new interface named split_block in iommu layer and arm smmuv3
>> implements it, which splits block descriptor to an equivalent span of
>> page descriptors.
>>
>> During spliting block, other interfaces are not expected to be working,
>> so race condition does not exist. And we flush all iotlbs after the split
>> procedure is completed to ease the pressure of iommu, as we will split a
>> huge range of block mappings in general.
> 
> "Not expected to be" is not the same thing as "can not". Presumably the whole 
> point of dirty log tracking is that it can be run speculatively in the 
> background, so is there any actual guarantee that the guest can't, say, issue 
> a hotplug event that would cause some memory to be released back to the host 
> and unmapped while a scan might be in progress? Saying effectively "there is 
> no race condition as long as you assume there is no race condition" isn't all 
> that reassuring...
Sorry for my inaccuracy expression. "Not expected to be" is inappropriate here, 
the actual meaning is "can not".

As the only user of these newly added interfaces is vfio_iommu_type1 for now, 
and vfio_iommu_type1 always acquires "iommu->lock" before invoke them.

> 
> That said, it's not very clear why patches #4 and #5 are here at all, given 
> that patches #6 and #7 appear quite happy to handle block entries.
Split block into page is very important for dirty page tracking. Page mapping 
can greatly reduce the amount of dirty memory handling. The KVM mmu stage2 side 
also has this logic.

Yes, #6 (log_sync) and #7 (log_clear) is designed to be applied for both block 
and page mapping. As the "split" operation may fail (e.g, without BBML1/2 or 
ENOMEM), but we can still track dirty at block granule, which is still a much 
better choice compared to the full dirty policy.

> 
>> Co-developed-by: Keqian Zhu 
>> Signed-off-by: Kunkun Jiang 
>> ---
>>   drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c |  20 
>>   drivers/iommu/io-pgtable-arm.c  | 122 
>>   drivers/iommu/iommu.c   |  40 +++
>>   include/linux/io-pgtable.h  |   2 +
>>   include/linux/iommu.h   |  10 ++
>>   5 files changed, 194 insertions(+)
>>
>> diff --git a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c 
>> b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c
>> index 9208881a571c..5469f4fca820 100644
>> --- a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c
>> +++ b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c
>> @@ -2510,6 +2510,25 @@ static int arm_smmu_domain_set_attr(struct 
>> iommu_domain *domain,
>>   return ret;
>>   }
>>   +static size_t arm_smmu_split_block(struct iommu_domain *domain,
>> +   unsigned long iova, size_t size)
>> +{
>> +struct arm_smmu_device *smmu = to_smmu_domain(domain)->smmu;
>> +struct io_pgtable_ops *ops = to_smmu_domain(domain)->pgtbl_ops;
>> +
>> +if (!(smmu->features & (ARM_SMMU_FEAT_BBML1 | ARM_SMMU_FEAT_BBML2))) {
>> +dev_err(smmu->dev, "don't support BBML1/2 and split block\n");
>> +return 0;
>> +}
>> +
>> +if (!ops || !ops->split_block) {
>> +pr_err("don't support split block\n");
>> +return 0;
>> +}
>> +
>> +return ops->split_block(ops, iova, size);
>> +}
>> +
>>   static int arm_smmu_of_xlate(struct device *dev, struct of_phandle_args 
>> *args)
>>   {
>>   return iommu_fwspec_add_ids(dev, args->args, 1);
>> @@ -2609,6 +2628,7 @@ static struct iommu_ops arm_smmu_ops = {
>>   .device_group= arm_smmu_device_group,
>>   .domain_get_attr= arm_smmu_domain_get_attr,
>>   .domain_set_attr= arm_smmu_domain_set_attr,
>> +.split_block= arm_smmu_split_block,
>>   .of_xlate= arm_smmu_of_xlate,
>>   .get_resv_regions= arm_smmu_get_resv_regions,
>>   .put_resv_regions= generic_iommu_put_resv_regions,
>> diff --git a/drivers/iommu/io-pgtable-arm.c b/drivers/iommu/io-pgtable-arm.c
>> index e299a44808ae..f3b7f7115e38 100644
>> --- a/drivers/iommu/io-pgtable-arm.c
>> +++ b/drivers/iommu/io-pgtable-arm.c
>> @@ -79,6 +79,8 @@
>>   #define ARM_LPAE_PTE_SH_IS(((arm_lpae_iopte)3) << 8)
>>   #define ARM_LPAE_PTE_NS(((arm_lpae_iopte)1) << 5)
>>   #define ARM_LPAE_PTE_VALID(((arm_lpae_iopte)1) << 0)
>> +/* Block descriptor bits */
>> +#define ARM_LPAE_PTE_NT(((arm_lpae_iopte)1) << 16)
>> #define ARM_LPAE_PTE_ATTR_LO_MASK(((arm_lpae_iopte)0x3ff) << 2)
>>   /* Ignore the contiguous bit for block splitting */
>> @@ -679,6 +681,125 @@ static phys_addr_t arm_lpae_iova_to_phys(struct 
>> io_pgtable_ops *ops,
>>   return iopte_to_paddr(pte, data) | iova;
>>   }
>>   +static size_t __arm_lpae_split_block(struct arm_lpae_io_pgtable *data,
>> +   

[RESEND PATCH v8 net-next 00/15] net: mvpp2: Add TX Flow Control support

[stefanc]

From: Stefan Chulski 

Armada hardware has a pause generation mechanism in GOP (MAC).
The GOP generate flow control frames based on an indication programmed in Ports 
Control 0 Register. There is a bit per port.
However assertion of the PortX Pause bits in the ports control 0 register only 
sends a one time pause.
To complement the function the GOP has a mechanism to periodically send pause 
control messages based on periodic counters.
This mechanism ensures that the pause is effective as long as the Appropriate 
PortX Pause is asserted.

Problem is that Packet Processor that actually can drop packets due to lack of 
resources not connected to the GOP flow control generation mechanism.
To solve this issue Armada has firmware running on CM3 CPU dedicated for Flow 
Control support.
Firmware monitors Packet Processor resources and asserts XON/XOFF by writing to 
Ports Control 0 Register.

MSS shared SRAM memory used to communicate between CM3 firmware and PP2 driver.
During init PP2 driver informs firmware about used BM pools, RXQs, congestion 
and depletion thresholds.

The pause frames are generated whenever congestion or depletion in resources is 
detected.
The back pressure is stopped when the resource reaches a sufficient level.
So the congestion/depletion and sufficient level implement a hysteresis that 
reduces the XON/XOFF toggle frequency.

Packet Processor v23 hardware introduces support for RX FIFO fill level monitor.
Patch "add PPv23 version definition" to differ between v23 and v22 hardware.
Patch "add TX FC firmware check" verifies that CM3 firmware supports Flow 
Control monitoring.

v7 --> v8
- Reorder "always compare hw-version vs MVPP21" and "add PPv23 version 
definition" commits
- Typo fixes
- Remove condition fix from "add RXQ flow control configurations"

v6 --> v7
- Reduce patch set from 18 to 15 patches
 - Documentation change combined into a single patch
 - RXQ and BM size change combined into a single patch
 - Ring size change check moved into "add RXQ flow control configurations" 
commit

v5 --> v6
- No change

v4 --> v5
- Add missed Signed-off
- Fix warnings in patches 3 and 12
- Add revision requirement to warning message
- Move mss_spinlock into RXQ flow control configurations patch
- Improve FCA RXQ non occupied descriptor threshold commit message

v3 --> v4
- Remove RFC tag

v2 --> v3
- Remove inline functions
- Add PPv2.3 description into marvell-pp2.txt
- Improve mvpp2_interrupts_mask/unmask procedure
- Improve FC enable/disable procedure
- Add priv->sram_pool check
- Remove gen_pool_destroy call
- Reduce Flow Control timer to x100 faster

v1 --> v2
- Add memory requirements information
- Add EPROBE_DEFER if of_gen_pool_get return NULL
- Move Flow control configuration to mvpp2_mac_link_up callback
- Add firmware version info with Flow control support

Konstantin Porotchkin (1):
  dts: marvell: add CM3 SRAM memory to cp11x ethernet device tree

Stefan Chulski (14):
  doc: marvell: add cm3-mem and PPv2.3 description
  net: mvpp2: add CM3 SRAM memory map
  net: mvpp2: always compare hw-version vs MVPP21
  net: mvpp2: add PPv23 version definition
  net: mvpp2: increase BM pool and RXQ size
  net: mvpp2: add FCA periodic timer configurations
  net: mvpp2: add FCA RXQ non occupied descriptor threshold
  net: mvpp2: enable global flow control
  net: mvpp2: add RXQ flow control configurations
  net: mvpp2: add ethtool flow control configuration support
  net: mvpp2: add BM protection underrun feature support
  net: mvpp2: add PPv23 RX FIFO flow control
  net: mvpp2: set 802.3x GoP Flow Control mode
  net: mvpp2: add TX FC firmware check

 Documentation/devicetree/bindings/net/marvell-pp2.txt |   4 +-
 arch/arm64/boot/dts/marvell/armada-cp11x.dtsi |  10 +
 drivers/net/ethernet/marvell/mvpp2/mvpp2.h| 128 -
 drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c   | 563 
++--
 4 files changed, 655 insertions(+), 50 deletions(-)

-- 
1.9.1

[RESEND PATCH v8 net-next 01/15] doc: marvell: add cm3-mem and PPv2.3 description

[stefanc]

From: Stefan Chulski 

Patch introduce cm3-mem device tree bindings and add PPv2.3 description.

Signed-off-by: Stefan Chulski 
---
 Documentation/devicetree/bindings/net/marvell-pp2.txt | 4 +++-
 1 file changed, 3 insertions(+), 1 deletion(-)

diff --git a/Documentation/devicetree/bindings/net/marvell-pp2.txt 
b/Documentation/devicetree/bindings/net/marvell-pp2.txt
index b783976..df80cff 100644
--- a/Documentation/devicetree/bindings/net/marvell-pp2.txt
+++ b/Documentation/devicetree/bindings/net/marvell-pp2.txt
@@ -1,5 +1,6 @@
 * Marvell Armada 375 Ethernet Controller (PPv2.1)
   Marvell Armada 7K/8K Ethernet Controller (PPv2.2)
+  Marvell CN913X Ethernet Controller (PPv2.3)
 
 Required properties:
 
@@ -12,7 +13,7 @@ Required properties:
- common controller registers
- LMS registers
- one register area per Ethernet port
-  For "marvell,armada-7k-pp2", must contain the following register
+  For "marvell,armada-7k-pp2" used by 7K/8K and CN913X, must contain the 
following register
   sets:
- packet processor registers
- networking interfaces registers
@@ -37,6 +38,7 @@ Required properties (port):
   GOP (Group Of Ports) point of view. This ID is used to index the
   per-port registers in the second register area.
 - phy-mode: See ethernet.txt file in the same directory
+- cm3-mem: phandle to CM3 SRAM definitions
 
 Optional properties (port):
 
-- 
1.9.1

RE: [RFC PATCH v1 0/4] vfio: Add IOPF support for VFIO passthrough

[Tian, Kevin]

> From: Jean-Philippe Brucker 
> Sent: Friday, February 5, 2021 6:37 PM
> 
> Hi,
> 
> On Thu, Feb 04, 2021 at 06:52:10AM +, Tian, Kevin wrote:
> > > >>> The static pinning and mapping problem in VFIO and possible
> solutions
> > > >>> have been discussed a lot [1, 2]. One of the solutions is to add I/O
> > > >>> page fault support for VFIO devices. Different from those relatively
> > > >>> complicated software approaches such as presenting a vIOMMU that
> > > >> provides
> > > >>> the DMA buffer information (might include para-virtualized
> > > optimizations),
> 
> I'm curious about the performance difference between this and the
> map/unmap vIOMMU, as well as the coIOMMU. This is probably a lot faster
> but those don't depend on IOPF which is a pretty rare feature at the
> moment.
> 
> [...]
> > > > In reality, many
> > > > devices allow I/O faulting only in selective contexts. However, there
> > > > is no standard way (e.g. PCISIG) for the device to report whether
> > > > arbitrary I/O fault is allowed. Then we may have to maintain device
> > > > specific knowledge in software, e.g. in an opt-in table to list devices
> > > > which allows arbitrary faults. For devices which only support selective
> > > > faulting, a mediator (either through vendor extensions on vfio-pci-core
> > > > or a mdev wrapper) might be necessary to help lock down non-
> faultable
> > > > mappings and then enable faulting on the rest mappings.
> > >
> > > For devices which only support selective faulting, they could tell it to 
> > > the
> > > IOMMU driver and let it filter out non-faultable faults? Do I get it 
> > > wrong?
> >
> > Not exactly to IOMMU driver. There is already a vfio_pin_pages() for
> > selectively page-pinning. The matter is that 'they' imply some device
> > specific logic to decide which pages must be pinned and such knowledge
> > is outside of VFIO.
> >
> > From enabling p.o.v we could possibly do it in phased approach. First
> > handles devices which tolerate arbitrary DMA faults, and then extends
> > to devices with selective-faulting. The former is simpler, but with one
> > main open whether we want to maintain such device IDs in a static
> > table in VFIO or rely on some hints from other components (e.g. PF
> > driver in VF assignment case). Let's see how Alex thinks about it.
> 
> Do you think selective-faulting will be the norm, or only a problem for
> initial IOPF implementations?  To me it's the selective-faulting kind of
> device that will be the odd one out, but that's pure speculation. Either
> way maintaining a device list seems like a pain.

I would think it's norm for quite some time (e.g. multiple years), as from
what I learned turning a complex accelerator to an implementation 
tolerating arbitrary DMA fault is way complex (in every critical path) and
not cost effective (tracking in-fly requests). It might be OK for some 
purposely-built devices in specific usage but for most it has to be an 
evolving path toward the 100%-faultable goal...

> 
> [...]
> > Yes, it's in plan but just not happened yet. We are still focusing on guest
> > SVA part thus only the 1st-level page fault (+Yi/Jacob). It's always
> welcomed
> > to collaborate/help if you have time. 😊
> 
> By the way the current fault report API is missing a way to invalidate
> partial faults: when the IOMMU device's PRI queue overflows, it may
> auto-respond to page request groups that were already partially reported
> by the IOMMU driver. Upon detecting an overflow, the IOMMU driver needs
> to
> tell all fault consumers to discard their partial groups.
> iopf_queue_discard_partial() [1] does this for the internal IOPF handler
> but we have nothing for the lower-level fault handler at the moment. And
> it gets more complicated when injecting IOPFs to guests, we'd need a
> mechanism to recall partial groups all the way through kernel->userspace
> and userspace->guest.

I didn't know how to recall partial groups through emulated vIOMMUs
(at least for virtual VT-d). Possibly it could be supported by virtio-iommu.
But in any case I consider it more like an optimization instead of a functional
requirement (and could be avoided in below Shenming's suggestion).

> 
> Shenming suggests [2] to also use the IOPF handler for IOPFs managed by
> device drivers. It's worth considering in my opinion because we could hold
> partial groups within the kernel and only report full groups to device
> drivers (and guests). In addition we'd consolidate tracking of IOPFs,
> since they're done both by iommu_report_device_fault() and the IOPF
> handler at the moment.

I also think it's the right thing to do. In concept w/ or w/o DEV_FEAT_IOPF
just reflects how IOPFs are delivered to the system software. In the end 
IOPFs are all about permission violations in the IOMMU page tables thus
we should try to reuse/consolidate the IOMMU fault reporting stack as 
much as possible.

> 
> Note that I plan to upstream the IOPF patch [1] as is because it was
> already in go

[RESEND PATCH v8 net-next 02/15] dts: marvell: add CM3 SRAM memory to cp11x ethernet device tree

[stefanc]

From: Konstantin Porotchkin 

CM3 SRAM address space would be used for Flow Control configuration.

Signed-off-by: Stefan Chulski 
Signed-off-by: Konstantin Porotchkin 
---
 arch/arm64/boot/dts/marvell/armada-cp11x.dtsi | 10 ++
 1 file changed, 10 insertions(+)

diff --git a/arch/arm64/boot/dts/marvell/armada-cp11x.dtsi 
b/arch/arm64/boot/dts/marvell/armada-cp11x.dtsi
index 9dcf16b..359cf42 100644
--- a/arch/arm64/boot/dts/marvell/armada-cp11x.dtsi
+++ b/arch/arm64/boot/dts/marvell/armada-cp11x.dtsi
@@ -69,6 +69,8 @@
status = "disabled";
dma-coherent;
 
+   cm3-mem = <&CP11X_LABEL(cm3_sram)>;
+
CP11X_LABEL(eth0): eth0 {
interrupts = <39 IRQ_TYPE_LEVEL_HIGH>,
<43 IRQ_TYPE_LEVEL_HIGH>,
@@ -211,6 +213,14 @@
};
};
 
+   CP11X_LABEL(cm3_sram): cm3@22 {
+   compatible = "mmio-sram";
+   reg = <0x22 0x800>;
+   #address-cells = <1>;
+   #size-cells = <1>;
+   ranges = <0 0x22 0x800>;
+   };
+
CP11X_LABEL(rtc): rtc@284000 {
compatible = "marvell,armada-8k-rtc";
reg = <0x284000 0x20>, <0x284080 0x24>;
-- 
1.9.1

[RESEND PATCH v8 net-next 03/15] net: mvpp2: add CM3 SRAM memory map

[stefanc]

From: Stefan Chulski 

This patch adds CM3 memory map and CM3 read/write callbacks.
No functionality changes.

Signed-off-by: Stefan Chulski 
---
 drivers/net/ethernet/marvell/mvpp2/mvpp2.h  |  7 +++
 drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c | 63 +++-
 2 files changed, 67 insertions(+), 3 deletions(-)

diff --git a/drivers/net/ethernet/marvell/mvpp2/mvpp2.h 
b/drivers/net/ethernet/marvell/mvpp2/mvpp2.h
index 6bd7e40..aec9179 100644
--- a/drivers/net/ethernet/marvell/mvpp2/mvpp2.h
+++ b/drivers/net/ethernet/marvell/mvpp2/mvpp2.h
@@ -748,6 +748,9 @@
 #define MVPP2_TX_FIFO_THRESHOLD(kb)\
((kb) * 1024 - MVPP2_TX_FIFO_THRESHOLD_MIN)
 
+/* MSS Flow control */
+#define MSS_SRAM_SIZE  0x800
+
 /* RX buffer constants */
 #define MVPP2_SKB_SHINFO_SIZE \
SKB_DATA_ALIGN(sizeof(struct skb_shared_info))
@@ -925,6 +928,7 @@ struct mvpp2 {
/* Shared registers' base addresses */
void __iomem *lms_base;
void __iomem *iface_base;
+   void __iomem *cm3_base;
 
/* On PPv2.2, each "software thread" can access the base
 * register through a separate address space, each 64 KB apart
@@ -996,6 +1000,9 @@ struct mvpp2 {
 
/* page_pool allocator */
struct page_pool *page_pool[MVPP2_PORT_MAX_RXQ];
+
+   /* CM3 SRAM pool */
+   struct gen_pool *sram_pool;
 };
 
 struct mvpp2_pcpu_stats {
diff --git a/drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c 
b/drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c
index a07cf60..307f9fd 100644
--- a/drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c
+++ b/drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c
@@ -25,6 +25,7 @@
 #include 
 #include 
 #include 
+#include 
 #include 
 #include 
 #include 
@@ -6846,6 +6847,44 @@ static int mvpp2_init(struct platform_device *pdev, 
struct mvpp2 *priv)
return 0;
 }
 
+static int mvpp2_get_sram(struct platform_device *pdev,
+ struct mvpp2 *priv)
+{
+   struct device_node *dn = pdev->dev.of_node;
+   static bool defer_once;
+   struct resource *res;
+
+   if (has_acpi_companion(&pdev->dev)) {
+   res = platform_get_resource(pdev, IORESOURCE_MEM, 2);
+   if (!res) {
+   dev_warn(&pdev->dev, "ACPI is too old, Flow control not 
supported\n");
+   return 0;
+   }
+   priv->cm3_base = devm_ioremap_resource(&pdev->dev, res);
+   if (IS_ERR(priv->cm3_base))
+   return PTR_ERR(priv->cm3_base);
+   } else {
+   priv->sram_pool = of_gen_pool_get(dn, "cm3-mem", 0);
+   if (!priv->sram_pool) {
+   if (!defer_once) {
+   defer_once = true;
+   /* Try defer once */
+   return -EPROBE_DEFER;
+   }
+   dev_warn(&pdev->dev, "DT is too old, Flow control not 
supported\n");
+   return -ENOMEM;
+   }
+   /* cm3_base allocated with offset zero into the SRAM since 
mapping size
+* is equal to requested size.
+*/
+   priv->cm3_base = (void __iomem *)gen_pool_alloc(priv->sram_pool,
+   MSS_SRAM_SIZE);
+   if (!priv->cm3_base)
+   return -ENOMEM;
+   }
+   return 0;
+}
+
 static int mvpp2_probe(struct platform_device *pdev)
 {
const struct acpi_device_id *acpi_id;
@@ -6902,6 +6941,13 @@ static int mvpp2_probe(struct platform_device *pdev)
priv->iface_base = devm_ioremap_resource(&pdev->dev, res);
if (IS_ERR(priv->iface_base))
return PTR_ERR(priv->iface_base);
+
+   /* Map CM3 SRAM */
+   err = mvpp2_get_sram(pdev, priv);
+   if (err == -EPROBE_DEFER)
+   return err;
+   else if (err)
+   dev_warn(&pdev->dev, "Fail to alloc CM3 SRAM\n");
}
 
if (priv->hw_version == MVPP22 && dev_of_node(&pdev->dev)) {
@@ -6947,11 +6993,13 @@ static int mvpp2_probe(struct platform_device *pdev)
 
if (dev_of_node(&pdev->dev)) {
priv->pp_clk = devm_clk_get(&pdev->dev, "pp_clk");
-   if (IS_ERR(priv->pp_clk))
-   return PTR_ERR(priv->pp_clk);
+   if (IS_ERR(priv->pp_clk)) {
+   err = PTR_ERR(priv->pp_clk);
+   goto err_cm3;
+   }
err = clk_prepare_enable(priv->pp_clk);
if (err < 0)
-   return err;
+   goto err_cm3;
 
priv->gop_clk = devm_clk_get(&pdev->dev, "gop_clk");
if (IS_ERR(priv->gop_clk)) {
@@ -7087,6 +7135,11 @@ static int mvpp2_probe(struct platform_device *pdev)
clk_disable_u

[RESEND PATCH v8 net-next 05/15] net: mvpp2: add PPv23 version definition

[stefanc]

From: Stefan Chulski 

This patch add PPv23 version definition.
PPv23 is new packet processor in CP115.
Everything that supported by PPv22, also supported by PPv23.
No functional changes in this stage.

Signed-off-by: Stefan Chulski 
---
 drivers/net/ethernet/marvell/mvpp2/mvpp2.h  | 24 
 drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c | 17 +-
 2 files changed, 25 insertions(+), 16 deletions(-)

diff --git a/drivers/net/ethernet/marvell/mvpp2/mvpp2.h 
b/drivers/net/ethernet/marvell/mvpp2/mvpp2.h
index aec9179..89b3ede 100644
--- a/drivers/net/ethernet/marvell/mvpp2/mvpp2.h
+++ b/drivers/net/ethernet/marvell/mvpp2/mvpp2.h
@@ -60,6 +60,9 @@
 /* Top Registers */
 #define MVPP2_MH_REG(port) (0x5040 + 4 * (port))
 #define MVPP2_DSA_EXTENDED BIT(5)
+#define MVPP2_VER_ID_REG   0x50b0
+#define MVPP2_VER_PP22 0x10
+#define MVPP2_VER_PP23 0x11
 
 /* Parser Registers */
 #define MVPP2_PRS_INIT_LOOKUP_REG  0x1000
@@ -469,7 +472,7 @@
 #define MVPP22_GMAC_INT_SUM_MASK_LINK_STAT BIT(1)
 #defineMVPP22_GMAC_INT_SUM_MASK_PTPBIT(2)
 
-/* Per-port XGMAC registers. PPv2.2 only, only for GOP port 0,
+/* Per-port XGMAC registers. PPv2.2 and PPv2.3, only for GOP port 0,
  * relative to port->base.
  */
 #define MVPP22_XLG_CTRL0_REG   0x100
@@ -506,7 +509,7 @@
 #define MVPP22_XLG_CTRL4_MACMODSELECT_GMAC BIT(12)
 #define MVPP22_XLG_CTRL4_EN_IDLE_CHECK BIT(14)
 
-/* SMI registers. PPv2.2 only, relative to priv->iface_base. */
+/* SMI registers. PPv2.2 and PPv2.3, relative to priv->iface_base. */
 #define MVPP22_SMI_MISC_CFG_REG0x1204
 #define MVPP22_SMI_POLLING_EN  BIT(10)
 
@@ -582,7 +585,7 @@
 #define MVPP2_QUEUE_NEXT_DESC(q, index) \
(((index) < (q)->last_desc) ? ((index) + 1) : 0)
 
-/* XPCS registers. PPv2.2 only */
+/* XPCS registers.PPv2.2 and PPv2.3 */
 #define MVPP22_MPCS_BASE(port) (0x7000 + (port) * 0x1000)
 #define MVPP22_MPCS_CTRL   0x14
 #define MVPP22_MPCS_CTRL_FWD_ERR_CONN  BIT(10)
@@ -593,7 +596,7 @@
 #define MVPP22_MPCS_CLK_RESET_DIV_RATIO(n) ((n) << 4)
 #define MVPP22_MPCS_CLK_RESET_DIV_SET  BIT(11)
 
-/* XPCS registers. PPv2.2 only */
+/* XPCS registers. PPv2.2 and PPv2.3 */
 #define MVPP22_XPCS_BASE(port) (0x7400 + (port) * 0x1000)
 #define MVPP22_XPCS_CFG0   0x0
 #define MVPP22_XPCS_CFG0_RESET_DIS BIT(0)
@@ -930,15 +933,16 @@ struct mvpp2 {
void __iomem *iface_base;
void __iomem *cm3_base;
 
-   /* On PPv2.2, each "software thread" can access the base
+   /* On PPv2.2 and PPv2.3, each "software thread" can access the base
 * register through a separate address space, each 64 KB apart
 * from each other. Typically, such address spaces will be
 * used per CPU.
 */
void __iomem *swth_base[MVPP2_MAX_THREADS];
 
-   /* On PPv2.2, some port control registers are located into the system
-* controller space. These registers are accessible through a regmap.
+   /* On PPv2.2 and PPv2.3, some port control registers are located into
+* the system controller space. These registers are accessible
+* through a regmap.
 */
struct regmap *sysctrl_base;
 
@@ -980,7 +984,7 @@ struct mvpp2 {
u32 tclk;
 
/* HW version */
-   enum { MVPP21, MVPP22 } hw_version;
+   enum { MVPP21, MVPP22, MVPP23 } hw_version;
 
/* Maximum number of RXQs per port */
unsigned int max_port_rxqs;
@@ -1227,7 +1231,7 @@ struct mvpp21_rx_desc {
__le32 reserved8;
 };
 
-/* HW TX descriptor for PPv2.2 */
+/* HW TX descriptor for PPv2.2 and PPv2.3 */
 struct mvpp22_tx_desc {
__le32 command;
u8  packet_offset;
@@ -1239,7 +1243,7 @@ struct mvpp22_tx_desc {
__le64 buf_cookie_misc;
 };
 
-/* HW RX descriptor for PPv2.2 */
+/* HW RX descriptor for PPv2.2 and PPv2.3 */
 struct mvpp22_rx_desc {
__le32 status;
__le16 reserved1;
diff --git a/drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c 
b/drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c
index 2c9da52..d80947a 100644
--- a/drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c
+++ b/drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c
@@ -385,7 +385,7 @@ static int mvpp2_bm_pool_create(struct device *dev, struct 
mvpp2 *priv,
if (!IS_ALIGNED(size, 16))
return -EINVAL;
 
-   /* PPv2.1 needs 8 bytes per buffer pointer, PPv2.2 needs 16
+   /* PPv2.1 needs 8 bytes per buffer pointer, PPv2.2 and PPv2.3 needs 16
 * bytes per buffer pointer
 */
if (priv->hw_version == MVPP21)
@@ -1173,7 +1173,7 @@ static void mvpp2_interrupts_unmask(void *arg)
u32 val;
int i;
 
-   if (port->priv->hw_version != MVPP22)
+   if

[RESEND PATCH v8 net-next 04/15] net: mvpp2: always compare hw-version vs MVPP21

[stefanc]

From: Stefan Chulski 

Currently we have PP2v1 and PP2v2 hw-versions, with some different
handlers depending upon condition hw_version = MVPP21/MVPP22.
In a future there will be also PP2v3. Let's use now the generic
"if equal/notEqual MVPP21" for all cases instead of "if MVPP22".

This patch does not change any functionality.
It is not intended to introduce PP2v3.
It just modifies MVPP21/MVPP22 check-condition
bringing it to generic and unified form correct for new-code
introducing and PP2v3 net-next generation.

Signed-off-by: Stefan Chulski 
---
 drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c | 36 ++--
 1 file changed, 18 insertions(+), 18 deletions(-)

diff --git a/drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c 
b/drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c
index 307f9fd..2c9da52 100644
--- a/drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c
+++ b/drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c
@@ -320,7 +320,7 @@ static int mvpp2_get_nrxqs(struct mvpp2 *priv)
 {
unsigned int nrxqs;
 
-   if (priv->hw_version == MVPP22 && queue_mode == MVPP2_QDIST_SINGLE_MODE)
+   if (priv->hw_version != MVPP21 && queue_mode == MVPP2_QDIST_SINGLE_MODE)
return 1;
 
/* According to the PPv2.2 datasheet and our experiments on
@@ -447,7 +447,7 @@ static void mvpp2_bm_bufs_get_addrs(struct device *dev, 
struct mvpp2 *priv,
  MVPP2_BM_PHY_ALLOC_REG(bm_pool->id));
*phys_addr = mvpp2_thread_read(priv, thread, MVPP2_BM_VIRT_ALLOC_REG);
 
-   if (priv->hw_version == MVPP22) {
+   if (priv->hw_version != MVPP21) {
u32 val;
u32 dma_addr_highbits, phys_addr_highbits;
 
@@ -743,7 +743,7 @@ static inline void mvpp2_bm_pool_put(struct mvpp2_port 
*port, int pool,
if (test_bit(thread, &port->priv->lock_map))
spin_lock_irqsave(&port->bm_lock[thread], flags);
 
-   if (port->priv->hw_version == MVPP22) {
+   if (port->priv->hw_version != MVPP21) {
u32 val = 0;
 
if (sizeof(dma_addr_t) == 8)
@@ -1200,7 +1200,7 @@ static bool mvpp2_port_supports_xlg(struct mvpp2_port 
*port)
 
 static bool mvpp2_port_supports_rgmii(struct mvpp2_port *port)
 {
-   return !(port->priv->hw_version == MVPP22 && port->gop_id == 0);
+   return !(port->priv->hw_version != MVPP21 && port->gop_id == 0);
 }
 
 /* Port configuration routines */
@@ -1818,7 +1818,7 @@ static void mvpp2_mac_reset_assert(struct mvpp2_port 
*port)
  MVPP2_GMAC_PORT_RESET_MASK;
writel(val, port->base + MVPP2_GMAC_CTRL_2_REG);
 
-   if (port->priv->hw_version == MVPP22 && port->gop_id == 0) {
+   if (port->priv->hw_version != MVPP21 && port->gop_id == 0) {
val = readl(port->base + MVPP22_XLG_CTRL0_REG) &
  ~MVPP22_XLG_CTRL0_MAC_RESET_DIS;
writel(val, port->base + MVPP22_XLG_CTRL0_REG);
@@ -1831,7 +1831,7 @@ static void mvpp22_pcs_reset_assert(struct mvpp2_port 
*port)
void __iomem *mpcs, *xpcs;
u32 val;
 
-   if (port->priv->hw_version != MVPP22 || port->gop_id != 0)
+   if (port->priv->hw_version == MVPP21 || port->gop_id != 0)
return;
 
mpcs = priv->iface_base + MVPP22_MPCS_BASE(port->gop_id);
@@ -1852,7 +1852,7 @@ static void mvpp22_pcs_reset_deassert(struct mvpp2_port 
*port)
void __iomem *mpcs, *xpcs;
u32 val;
 
-   if (port->priv->hw_version != MVPP22 || port->gop_id != 0)
+   if (port->priv->hw_version == MVPP21 || port->gop_id != 0)
return;
 
mpcs = priv->iface_base + MVPP22_MPCS_BASE(port->gop_id);
@@ -4189,7 +4189,7 @@ static void mvpp2_start_dev(struct mvpp2_port *port)
/* Enable interrupts on all threads */
mvpp2_interrupts_enable(port);
 
-   if (port->priv->hw_version == MVPP22)
+   if (port->priv->hw_version != MVPP21)
mvpp22_mode_reconfigure(port);
 
if (port->phylink) {
@@ -4405,7 +4405,7 @@ static int mvpp2_open(struct net_device *dev)
valid = true;
}
 
-   if (priv->hw_version == MVPP22 && port->port_irq) {
+   if (priv->hw_version != MVPP21 && port->port_irq) {
err = request_irq(port->port_irq, mvpp2_port_isr, 0,
  dev->name, port);
if (err) {
@@ -6053,7 +6053,7 @@ static int mvpp2__mac_prepare(struct phylink_config 
*config, unsigned int mode,
 MVPP2_GMAC_PORT_RESET_MASK,
 MVPP2_GMAC_PORT_RESET_MASK);
 
-   if (port->priv->hw_version == MVPP22) {
+   if (port->priv->hw_version != MVPP21) {
mvpp22_gop_mask_irq(port);
 
phy_power_off(port->comphy);
@@ -6107,7 +6107,7 @@ static int mvpp2_mac_finish(struct phylink_config 
*config, unsigned int mode,
 {
struct mvpp2_port *port = mvpp2_phylink_to_port(config);
 
-

[RESEND PATCH v8 net-next 06/15] net: mvpp2: increase BM pool and RXQ size

[stefanc]

From: Stefan Chulski 

BM pool and RXQ size increased to support Firmware Flow Control.
Minimum depletion thresholds to support FC are 1024 buffers.
BM pool size increased to 2048 to have some 1024 buffers
space between depletion thresholds and BM pool size.

Jumbo frames require a 9888B buffer, so memory requirements
for data buffers increased from 7MB to 24MB.

Signed-off-by: Stefan Chulski 
---
 drivers/net/ethernet/marvell/mvpp2/mvpp2.h | 8 
 1 file changed, 4 insertions(+), 4 deletions(-)

diff --git a/drivers/net/ethernet/marvell/mvpp2/mvpp2.h 
b/drivers/net/ethernet/marvell/mvpp2/mvpp2.h
index 89b3ede..cac9885 100644
--- a/drivers/net/ethernet/marvell/mvpp2/mvpp2.h
+++ b/drivers/net/ethernet/marvell/mvpp2/mvpp2.h
@@ -715,8 +715,8 @@
 #define MVPP2_PORT_MAX_RXQ 32
 
 /* Max number of Rx descriptors */
-#define MVPP2_MAX_RXD_MAX  1024
-#define MVPP2_MAX_RXD_DFLT 128
+#define MVPP2_MAX_RXD_MAX  2048
+#define MVPP2_MAX_RXD_DFLT 1024
 
 /* Max number of Tx descriptors */
 #define MVPP2_MAX_TXD_MAX  2048
@@ -851,8 +851,8 @@ enum mvpp22_ptp_packet_format {
 #define MVPP22_PTP_TIMESTAMPQUEUESELECTBIT(18)
 
 /* BM constants */
-#define MVPP2_BM_JUMBO_BUF_NUM 512
-#define MVPP2_BM_LONG_BUF_NUM  1024
+#define MVPP2_BM_JUMBO_BUF_NUM 2048
+#define MVPP2_BM_LONG_BUF_NUM  2048
 #define MVPP2_BM_SHORT_BUF_NUM 2048
 #define MVPP2_BM_POOL_SIZE_MAX (16*1024 - MVPP2_BM_POOL_PTR_ALIGN/4)
 #define MVPP2_BM_POOL_PTR_ALIGN128
-- 
1.9.1

Re: [PATCH] jfs: turn diLog(), dataLog() and txLog() into void functions

[kernel test robot]

Hi Yang,

Thank you for the patch! Yet something to improve:

[auto build test ERROR on shaggy/jfs-next]
[also build test ERROR on v5.11-rc6 next-20210125]
[If your patch is applied to the wrong git tree, kindly drop us a note.
And when submitting patch, we suggest to use '--base' as documented in
https://git-scm.com/docs/git-format-patch]

url:
https://github.com/0day-ci/linux/commits/Yang-Li/jfs-turn-diLog-dataLog-and-txLog-into-void-functions/20210207-143938
base:   https://github.com/kleikamp/linux-shaggy jfs-next
config: i386-randconfig-m021-20210207 (attached as .config)
compiler: gcc-9 (Debian 9.3.0-15) 9.3.0
reproduce (this is a W=1 build):
# 
https://github.com/0day-ci/linux/commit/8b7ab4ba41269109e7cb95106023e96d640842e9
git remote add linux-review https://github.com/0day-ci/linux
git fetch --no-tags linux-review 
Yang-Li/jfs-turn-diLog-dataLog-and-txLog-into-void-functions/20210207-143938
git checkout 8b7ab4ba41269109e7cb95106023e96d640842e9
# save the attached .config to linux build tree
make W=1 ARCH=i386 

If you fix the issue, kindly add following tag as appropriate
Reported-by: kernel test robot 

All errors (new ones prefixed by >>):

>> fs/jfs/jfs_txnmgr.c:1368:13: error: conflicting types for 'txLog'
1368 | static void txLog(struct jfs_log *log, struct tblock *tblk, struct 
commit *cd)
 | ^
   fs/jfs/jfs_txnmgr.c:162:12: note: previous declaration of 'txLog' was here
 162 | static int txLog(struct jfs_log * log, struct tblock * tblk,
 |^
>> fs/jfs/jfs_txnmgr.c:1424:13: error: conflicting types for 'diLog'
1424 | static void diLog(struct jfs_log *log, struct tblock *tblk, struct 
lrd *lrd,
 | ^
   fs/jfs/jfs_txnmgr.c:151:12: note: previous declaration of 'diLog' was here
 151 | static int diLog(struct jfs_log * log, struct tblock * tblk, struct 
lrd * lrd,
 |^
>> fs/jfs/jfs_txnmgr.c:1536:13: error: conflicting types for 'dataLog'
1536 | static void dataLog(struct jfs_log *log, struct tblock *tblk, struct 
lrd *lrd,
 | ^~~
   fs/jfs/jfs_txnmgr.c:153:12: note: previous declaration of 'dataLog' was here
 153 | static int dataLog(struct jfs_log * log, struct tblock * tblk, 
struct lrd * lrd,
 |^~~
   fs/jfs/jfs_txnmgr.c:151:12: warning: 'diLog' used but never defined
 151 | static int diLog(struct jfs_log * log, struct tblock * tblk, struct 
lrd * lrd,
 |^
   fs/jfs/jfs_txnmgr.c:153:12: warning: 'dataLog' used but never defined
 153 | static int dataLog(struct jfs_log * log, struct tblock * tblk, 
struct lrd * lrd,
 |^~~
   fs/jfs/jfs_txnmgr.c:162:12: warning: 'txLog' used but never defined
 162 | static int txLog(struct jfs_log * log, struct tblock * tblk,
 |^
   fs/jfs/jfs_txnmgr.c:1536:13: warning: 'dataLog' defined but not used 
[-Wunused-function]
1536 | static void dataLog(struct jfs_log *log, struct tblock *tblk, struct 
lrd *lrd,
 | ^~~
   fs/jfs/jfs_txnmgr.c:1424:13: warning: 'diLog' defined but not used 
[-Wunused-function]
1424 | static void diLog(struct jfs_log *log, struct tblock *tblk, struct 
lrd *lrd,
 | ^
   fs/jfs/jfs_txnmgr.c:1368:13: warning: 'txLog' defined but not used 
[-Wunused-function]
1368 | static void txLog(struct jfs_log *log, struct tblock *tblk, struct 
commit *cd)
 | ^


vim +/txLog +1368 fs/jfs/jfs_txnmgr.c

  1356  
  1357  /*
  1358   * NAME:txLog()
  1359   *
  1360   * FUNCTION:Writes AFTER log records for all lines modified
  1361   *  by tid for segments specified by inodes in comdata.
  1362   *  Code assumes only WRITELOCKS are recorded in lockwords.
  1363   *
  1364   * PARAMETERS:
  1365   *
  1366   * RETURN :
  1367   */
> 1368  static void txLog(struct jfs_log *log, struct tblock *tblk, struct 
> commit *cd)
  1369  {
  1370  struct inode *ip;
  1371  lid_t lid;
  1372  struct tlock *tlck;
  1373  struct lrd *lrd = &cd->lrd;
  1374  
  1375  /*
  1376   * write log record(s) for each tlock of transaction,
  1377   */
  1378  for (lid = tblk->next; lid; lid = tlck->next) {
  1379  tlck = lid_to_tlock(lid);
  1380  
  1381  tlck->flag |= tlckLOG;
  1382  
  1383  /* initialize lrd common */
  1384  ip = tlck->ip;
  1385  lrd->aggregate = 
cpu_to_le32(JFS_SBI(ip->i_sb)->aggregate);
  1386  lrd->log.redopage.fileset = 
cpu_to_le32(JFS_IP(ip)->fileset);
  1387

[RESEND PATCH v8 net-next 07/15] net: mvpp2: add FCA periodic timer configurations

[stefanc]

From: Stefan Chulski 

Flow Control periodic timer would be used if port in
XOFF to transmit periodic XOFF frames.

Signed-off-by: Stefan Chulski 
---
 drivers/net/ethernet/marvell/mvpp2/mvpp2.h  | 13 +-
 drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c | 45 
 2 files changed, 57 insertions(+), 1 deletion(-)

diff --git a/drivers/net/ethernet/marvell/mvpp2/mvpp2.h 
b/drivers/net/ethernet/marvell/mvpp2/mvpp2.h
index cac9885..73f087c 100644
--- a/drivers/net/ethernet/marvell/mvpp2/mvpp2.h
+++ b/drivers/net/ethernet/marvell/mvpp2/mvpp2.h
@@ -596,6 +596,15 @@
 #define MVPP22_MPCS_CLK_RESET_DIV_RATIO(n) ((n) << 4)
 #define MVPP22_MPCS_CLK_RESET_DIV_SET  BIT(11)
 
+/* FCA registers. PPv2.2 and PPv2.3 */
+#define MVPP22_FCA_BASE(port)  (0x7600 + (port) * 0x1000)
+#define MVPP22_FCA_REG_SIZE16
+#define MVPP22_FCA_REG_MASK0x
+#define MVPP22_FCA_CONTROL_REG 0x0
+#define MVPP22_FCA_ENABLE_PERIODIC BIT(11)
+#define MVPP22_PERIODIC_COUNTER_LSB_REG(0x110)
+#define MVPP22_PERIODIC_COUNTER_MSB_REG(0x114)
+
 /* XPCS registers. PPv2.2 and PPv2.3 */
 #define MVPP22_XPCS_BASE(port) (0x7400 + (port) * 0x1000)
 #define MVPP22_XPCS_CFG0   0x0
@@ -752,7 +761,9 @@
((kb) * 1024 - MVPP2_TX_FIFO_THRESHOLD_MIN)
 
 /* MSS Flow control */
-#define MSS_SRAM_SIZE  0x800
+#define MSS_SRAM_SIZE  0x800
+#define FC_QUANTA  0x
+#define FC_CLK_DIVIDER 100
 
 /* RX buffer constants */
 #define MVPP2_SKB_SHINFO_SIZE \
diff --git a/drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c 
b/drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c
index d80947a..6e59d07 100644
--- a/drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c
+++ b/drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c
@@ -1281,6 +1281,49 @@ static void mvpp22_gop_init_10gkr(struct mvpp2_port 
*port)
writel(val, mpcs + MVPP22_MPCS_CLK_RESET);
 }
 
+static void mvpp22_gop_fca_enable_periodic(struct mvpp2_port *port, bool en)
+{
+   struct mvpp2 *priv = port->priv;
+   void __iomem *fca = priv->iface_base + MVPP22_FCA_BASE(port->gop_id);
+   u32 val;
+
+   val = readl(fca + MVPP22_FCA_CONTROL_REG);
+   val &= ~MVPP22_FCA_ENABLE_PERIODIC;
+   if (en)
+   val |= MVPP22_FCA_ENABLE_PERIODIC;
+   writel(val, fca + MVPP22_FCA_CONTROL_REG);
+}
+
+static void mvpp22_gop_fca_set_timer(struct mvpp2_port *port, u32 timer)
+{
+   struct mvpp2 *priv = port->priv;
+   void __iomem *fca = priv->iface_base + MVPP22_FCA_BASE(port->gop_id);
+   u32 lsb, msb;
+
+   lsb = timer & MVPP22_FCA_REG_MASK;
+   msb = timer >> MVPP22_FCA_REG_SIZE;
+
+   writel(lsb, fca + MVPP22_PERIODIC_COUNTER_LSB_REG);
+   writel(msb, fca + MVPP22_PERIODIC_COUNTER_MSB_REG);
+}
+
+/* Set Flow Control timer x100 faster than pause quanta to ensure that link
+ * partner won't send traffic if port is in XOFF mode.
+ */
+static void mvpp22_gop_fca_set_periodic_timer(struct mvpp2_port *port)
+{
+   u32 timer;
+
+   timer = (port->priv->tclk / (USEC_PER_SEC * FC_CLK_DIVIDER))
+   * FC_QUANTA;
+
+   mvpp22_gop_fca_enable_periodic(port, false);
+
+   mvpp22_gop_fca_set_timer(port, timer);
+
+   mvpp22_gop_fca_enable_periodic(port, true);
+}
+
 static int mvpp22_gop_init(struct mvpp2_port *port)
 {
struct mvpp2 *priv = port->priv;
@@ -1325,6 +1368,8 @@ static int mvpp22_gop_init(struct mvpp2_port *port)
val |= GENCONF_SOFT_RESET1_GOP;
regmap_write(priv->sysctrl_base, GENCONF_SOFT_RESET1, val);
 
+   mvpp22_gop_fca_set_periodic_timer(port);
+
 unsupported_conf:
return 0;
 
-- 
1.9.1

[RESEND PATCH v8 net-next 08/15] net: mvpp2: add FCA RXQ non occupied descriptor threshold

[stefanc]

From: Stefan Chulski 

The firmware needs to monitor the RX Non-occupied descriptor
bits for flow control to move to XOFF mode.
These bits need to be unmasked to be functional, but they will
not raise interrupts as we leave the RX exception summary
bit in MVPP2_ISR_RX_TX_MASK_REG clear.

Signed-off-by: Stefan Chulski 
---
 drivers/net/ethernet/marvell/mvpp2/mvpp2.h  |  3 ++
 drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c | 44 
 2 files changed, 40 insertions(+), 7 deletions(-)

diff --git a/drivers/net/ethernet/marvell/mvpp2/mvpp2.h 
b/drivers/net/ethernet/marvell/mvpp2/mvpp2.h
index 73f087c..ca84995 100644
--- a/drivers/net/ethernet/marvell/mvpp2/mvpp2.h
+++ b/drivers/net/ethernet/marvell/mvpp2/mvpp2.h
@@ -295,6 +295,8 @@
 #define MVPP2_PON_CAUSE_TXP_OCCUP_DESC_ALL_MASK0x3fc0
 #define MVPP2_PON_CAUSE_MISC_SUM_MASK  BIT(31)
 #define MVPP2_ISR_MISC_CAUSE_REG   0x55b0
+#define MVPP2_ISR_RX_ERR_CAUSE_REG(port)   (0x5520 + 4 * (port))
+#define MVPP2_ISR_RX_ERR_CAUSE_NONOCC_MASK 0x00ff
 
 /* Buffer Manager registers */
 #define MVPP2_BM_POOL_BASE_REG(pool)   (0x6000 + ((pool) * 4))
@@ -764,6 +766,7 @@
 #define MSS_SRAM_SIZE  0x800
 #define FC_QUANTA  0x
 #define FC_CLK_DIVIDER 100
+#define MSS_THRESHOLD_STOP 768
 
 /* RX buffer constants */
 #define MVPP2_SKB_SHINFO_SIZE \
diff --git a/drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c 
b/drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c
index 6e59d07..a72a390 100644
--- a/drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c
+++ b/drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c
@@ -1134,14 +1134,19 @@ static inline void mvpp2_qvec_interrupt_disable(struct 
mvpp2_queue_vector *qvec)
 static void mvpp2_interrupts_mask(void *arg)
 {
struct mvpp2_port *port = arg;
+   int cpu = smp_processor_id();
+   u32 thread;
 
/* If the thread isn't used, don't do anything */
-   if (smp_processor_id() > port->priv->nthreads)
+   if (cpu > port->priv->nthreads)
return;
 
-   mvpp2_thread_write(port->priv,
-  mvpp2_cpu_to_thread(port->priv, smp_processor_id()),
+   thread = mvpp2_cpu_to_thread(port->priv, cpu);
+
+   mvpp2_thread_write(port->priv, thread,
   MVPP2_ISR_RX_TX_MASK_REG(port->id), 0);
+   mvpp2_thread_write(port->priv, thread,
+  MVPP2_ISR_RX_ERR_CAUSE_REG(port->id), 0);
 }
 
 /* Unmask the current thread's Rx/Tx interrupts.
@@ -1151,20 +1156,25 @@ static void mvpp2_interrupts_mask(void *arg)
 static void mvpp2_interrupts_unmask(void *arg)
 {
struct mvpp2_port *port = arg;
-   u32 val;
+   int cpu = smp_processor_id();
+   u32 val, thread;
 
/* If the thread isn't used, don't do anything */
-   if (smp_processor_id() > port->priv->nthreads)
+   if (cpu > port->priv->nthreads)
return;
 
+   thread = mvpp2_cpu_to_thread(port->priv, cpu);
+
val = MVPP2_CAUSE_MISC_SUM_MASK |
MVPP2_CAUSE_RXQ_OCCUP_DESC_ALL_MASK(port->priv->hw_version);
if (port->has_tx_irqs)
val |= MVPP2_CAUSE_TXQ_OCCUP_DESC_ALL_MASK;
 
-   mvpp2_thread_write(port->priv,
-  mvpp2_cpu_to_thread(port->priv, smp_processor_id()),
+   mvpp2_thread_write(port->priv, thread,
   MVPP2_ISR_RX_TX_MASK_REG(port->id), val);
+   mvpp2_thread_write(port->priv, thread,
+  MVPP2_ISR_RX_ERR_CAUSE_REG(port->id),
+  MVPP2_ISR_RX_ERR_CAUSE_NONOCC_MASK);
 }
 
 static void
@@ -1189,6 +1199,9 @@ static void mvpp2_interrupts_unmask(void *arg)
 
mvpp2_thread_write(port->priv, v->sw_thread_id,
   MVPP2_ISR_RX_TX_MASK_REG(port->id), val);
+   mvpp2_thread_write(port->priv, v->sw_thread_id,
+  MVPP2_ISR_RX_ERR_CAUSE_REG(port->id),
+  MVPP2_ISR_RX_ERR_CAUSE_NONOCC_MASK);
}
 }
 
@@ -2394,6 +2407,20 @@ static void mvpp2_txp_max_tx_size_set(struct mvpp2_port 
*port)
}
 }
 
+/* Set the number of non-occupied descriptors threshold */
+static void mvpp2_set_rxq_free_tresh(struct mvpp2_port *port,
+struct mvpp2_rx_queue *rxq)
+{
+   u32 val;
+
+   mvpp2_write(port->priv, MVPP2_RXQ_NUM_REG, rxq->id);
+
+   val = mvpp2_read(port->priv, MVPP2_RXQ_THRESH_REG);
+   val &= ~MVPP2_RXQ_NON_OCCUPIED_MASK;
+   val |= MSS_THRESHOLD_STOP << MVPP2_RXQ_NON_OCCUPIED_OFFSET;
+   mvpp2_write(port->priv, MVPP2_RXQ_THRESH_REG, val);
+}
+
 /* Set the number of packets that will be received before Rx interrupt
  * will be generated by HW.
  */
@@ -2649,6 +2676,9 @@ static int mvpp2_rxq_init(struct mvpp2_port *port,
mvpp2_rx_pkts_coal_set(port, rxq);
mvpp2_rx_time_coal_set(port, rxq);
 
+   /* Set 

[RESEND PATCH v8 net-next 10/15] net: mvpp2: add RXQ flow control configurations

[stefanc]

From: Stefan Chulski 

This patch adds RXQ flow control configurations.
Flow control disabled by default.
Minimum ring size limited to 1024 descriptors.

Signed-off-by: Stefan Chulski 
---
 drivers/net/ethernet/marvell/mvpp2/mvpp2.h  |  35 +-
 drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c | 116 
 2 files changed, 150 insertions(+), 1 deletion(-)

diff --git a/drivers/net/ethernet/marvell/mvpp2/mvpp2.h 
b/drivers/net/ethernet/marvell/mvpp2/mvpp2.h
index e010410..0f27be0 100644
--- a/drivers/net/ethernet/marvell/mvpp2/mvpp2.h
+++ b/drivers/net/ethernet/marvell/mvpp2/mvpp2.h
@@ -766,9 +766,36 @@
 #define MSS_SRAM_SIZE  0x800
 #define MSS_FC_COM_REG 0
 #define FLOW_CONTROL_ENABLE_BITBIT(0)
+#define FLOW_CONTROL_UPDATE_COMMAND_BITBIT(31)
 #define FC_QUANTA  0x
 #define FC_CLK_DIVIDER 100
-#define MSS_THRESHOLD_STOP 768
+
+#define MSS_RXQ_TRESH_BASE 0x200
+#define MSS_RXQ_TRESH_OFFS 4
+#define MSS_RXQ_TRESH_REG(q, fq)   (MSS_RXQ_TRESH_BASE + (((q) + (fq)) \
+   * MSS_RXQ_TRESH_OFFS))
+
+#define MSS_RXQ_TRESH_START_MASK   0x
+#define MSS_RXQ_TRESH_STOP_MASK(0x << 
MSS_RXQ_TRESH_STOP_OFFS)
+#define MSS_RXQ_TRESH_STOP_OFFS16
+
+#define MSS_RXQ_ASS_BASE   0x80
+#define MSS_RXQ_ASS_OFFS   4
+#define MSS_RXQ_ASS_PER_REG4
+#define MSS_RXQ_ASS_PER_OFFS   8
+#define MSS_RXQ_ASS_PORTID_OFFS0
+#define MSS_RXQ_ASS_PORTID_MASK0x3
+#define MSS_RXQ_ASS_HOSTID_OFFS2
+#define MSS_RXQ_ASS_HOSTID_MASK0x3F
+
+#define MSS_RXQ_ASS_Q_BASE(q, fq) q) + (fq)) % MSS_RXQ_ASS_PER_REG)
 \
+ * MSS_RXQ_ASS_PER_OFFS)
+#define MSS_RXQ_ASS_PQ_BASE(q, fq) q) + (fq)) / MSS_RXQ_ASS_PER_REG) \
+  * MSS_RXQ_ASS_OFFS)
+#define MSS_RXQ_ASS_REG(q, fq) (MSS_RXQ_ASS_BASE + MSS_RXQ_ASS_PQ_BASE(q, fq))
+
+#define MSS_THRESHOLD_STOP 768
+#define MSS_THRESHOLD_START1024
 
 /* RX buffer constants */
 #define MVPP2_SKB_SHINFO_SIZE \
@@ -1026,6 +1053,9 @@ struct mvpp2 {
 
/* Global TX Flow Control config */
bool global_tx_fc;
+
+   /* Spinlocks for CM3 shared memory configuration */
+   spinlock_t mss_spinlock;
 };
 
 struct mvpp2_pcpu_stats {
@@ -1188,6 +1218,9 @@ struct mvpp2_port {
bool rx_hwtstamp;
enum hwtstamp_tx_types tx_hwtstamp_type;
struct mvpp2_hwtstamp_queue tx_hwtstamp_queue[2];
+
+   /* Firmware TX flow control */
+   bool tx_fc;
 };
 
 /* The mvpp2_tx_desc and mvpp2_rx_desc structures describe the
diff --git a/drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c 
b/drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c
index fec1c81..29ba62a 100644
--- a/drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c
+++ b/drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c
@@ -742,6 +742,110 @@ static void *mvpp2_buf_alloc(struct mvpp2_port *port,
return data;
 }
 
+/* Routine enable flow control for RXQs condition */
+static void mvpp2_rxq_enable_fc(struct mvpp2_port *port)
+{
+   int val, cm3_state, host_id, q;
+   int fq = port->first_rxq;
+   unsigned long flags;
+
+   spin_lock_irqsave(&port->priv->mss_spinlock, flags);
+
+   /* Remove Flow control enable bit to prevent race between FW and Kernel
+* If Flow control was enabled, it would be re-enabled.
+*/
+   val = mvpp2_cm3_read(port->priv, MSS_FC_COM_REG);
+   cm3_state = (val & FLOW_CONTROL_ENABLE_BIT);
+   val &= ~FLOW_CONTROL_ENABLE_BIT;
+   mvpp2_cm3_write(port->priv, MSS_FC_COM_REG, val);
+
+   /* Set same Flow control for all RXQs */
+   for (q = 0; q < port->nrxqs; q++) {
+   /* Set stop and start Flow control RXQ thresholds */
+   val = MSS_THRESHOLD_START;
+   val |= (MSS_THRESHOLD_STOP << MSS_RXQ_TRESH_STOP_OFFS);
+   mvpp2_cm3_write(port->priv, MSS_RXQ_TRESH_REG(q, fq), val);
+
+   val = mvpp2_cm3_read(port->priv, MSS_RXQ_ASS_REG(q, fq));
+   /* Set RXQ port ID */
+   val &= ~(MSS_RXQ_ASS_PORTID_MASK << MSS_RXQ_ASS_Q_BASE(q, fq));
+   val |= (port->id << MSS_RXQ_ASS_Q_BASE(q, fq));
+   val &= ~(MSS_RXQ_ASS_HOSTID_MASK << (MSS_RXQ_ASS_Q_BASE(q, fq)
+   + MSS_RXQ_ASS_HOSTID_OFFS));
+
+   /* Calculate RXQ host ID:
+* In Single queue mode: Host ID equal to Host ID used for
+*   shared RX interrupt
+* In Multi queue mode: Host ID equal to number of
+*  RXQ ID / number of CoS queues
+* In Single resource mode: Host ID always equal to 0
+*/
+   if (queue_mode == MVPP2_QDIST_SINGLE_MODE)
+   host_id = port->nqvecs;
+

[RESEND PATCH v8 net-next 11/15] net: mvpp2: add ethtool flow control configuration support

[stefanc]

From: Stefan Chulski 

This patch add ethtool flow control configuration support.

Tx flow control retrieved correctly by ethtool get function.
FW per port ethtool configuration capability added.

Patch also takes care about mtu change procedure, if PPv2 switch
BM pools during mtu change.

Signed-off-by: Stefan Chulski 
---
 drivers/net/ethernet/marvell/mvpp2/mvpp2.h  | 13 +++
 drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c | 98 
 2 files changed, 111 insertions(+)

diff --git a/drivers/net/ethernet/marvell/mvpp2/mvpp2.h 
b/drivers/net/ethernet/marvell/mvpp2/mvpp2.h
index 0f27be0..9071ab6 100644
--- a/drivers/net/ethernet/marvell/mvpp2/mvpp2.h
+++ b/drivers/net/ethernet/marvell/mvpp2/mvpp2.h
@@ -775,6 +775,19 @@
 #define MSS_RXQ_TRESH_REG(q, fq)   (MSS_RXQ_TRESH_BASE + (((q) + (fq)) \
* MSS_RXQ_TRESH_OFFS))
 
+#define MSS_BUF_POOL_BASE  0x40
+#define MSS_BUF_POOL_OFFS  4
+#define MSS_BUF_POOL_REG(id)   (MSS_BUF_POOL_BASE  \
+   + (id) * MSS_BUF_POOL_OFFS)
+
+#define MSS_BUF_POOL_STOP_MASK 0xFFF
+#define MSS_BUF_POOL_START_MASK(0xFFF << 
MSS_BUF_POOL_START_OFFS)
+#define MSS_BUF_POOL_START_OFFS12
+#define MSS_BUF_POOL_PORTS_MASK(0xF << MSS_BUF_POOL_PORTS_OFFS)
+#define MSS_BUF_POOL_PORTS_OFFS24
+#define MSS_BUF_POOL_PORT_OFFS(id) (0x1 << \
+   ((id) + MSS_BUF_POOL_PORTS_OFFS))
+
 #define MSS_RXQ_TRESH_START_MASK   0x
 #define MSS_RXQ_TRESH_STOP_MASK(0x << 
MSS_RXQ_TRESH_STOP_OFFS)
 #define MSS_RXQ_TRESH_STOP_OFFS16
diff --git a/drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c 
b/drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c
index 29ba62a..5d80c5e 100644
--- a/drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c
+++ b/drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c
@@ -846,6 +846,59 @@ static void mvpp2_rxq_disable_fc(struct mvpp2_port *port)
spin_unlock_irqrestore(&port->priv->mss_spinlock, flags);
 }
 
+/* Routine disable/enable flow control for BM pool condition */
+static void mvpp2_bm_pool_update_fc(struct mvpp2_port *port,
+   struct mvpp2_bm_pool *pool,
+   bool en)
+{
+   int val, cm3_state;
+   unsigned long flags;
+
+   spin_lock_irqsave(&port->priv->mss_spinlock, flags);
+
+   /* Remove Flow control enable bit to prevent race between FW and Kernel
+* If Flow control were enabled, it would be re-enabled.
+*/
+   val = mvpp2_cm3_read(port->priv, MSS_FC_COM_REG);
+   cm3_state = (val & FLOW_CONTROL_ENABLE_BIT);
+   val &= ~FLOW_CONTROL_ENABLE_BIT;
+   mvpp2_cm3_write(port->priv, MSS_FC_COM_REG, val);
+
+   /* Check if BM pool should be enabled/disable */
+   if (en) {
+   /* Set BM pool start and stop thresholds per port */
+   val = mvpp2_cm3_read(port->priv, MSS_BUF_POOL_REG(pool->id));
+   val |= MSS_BUF_POOL_PORT_OFFS(port->id);
+   val &= ~MSS_BUF_POOL_START_MASK;
+   val |= (MSS_THRESHOLD_START << MSS_BUF_POOL_START_OFFS);
+   val &= ~MSS_BUF_POOL_STOP_MASK;
+   val |= MSS_THRESHOLD_STOP;
+   mvpp2_cm3_write(port->priv, MSS_BUF_POOL_REG(pool->id), val);
+   } else {
+   /* Remove BM pool from the port */
+   val = mvpp2_cm3_read(port->priv, MSS_BUF_POOL_REG(pool->id));
+   val &= ~MSS_BUF_POOL_PORT_OFFS(port->id);
+
+   /* Zero BM pool start and stop thresholds to disable pool
+* flow control if pool empty (not used by any port)
+*/
+   if (!pool->buf_num) {
+   val &= ~MSS_BUF_POOL_START_MASK;
+   val &= ~MSS_BUF_POOL_STOP_MASK;
+   }
+
+   mvpp2_cm3_write(port->priv, MSS_BUF_POOL_REG(pool->id), val);
+   }
+
+   /* Notify Firmware that Flow control config space ready for update */
+   val = mvpp2_cm3_read(port->priv, MSS_FC_COM_REG);
+   val |= FLOW_CONTROL_UPDATE_COMMAND_BIT;
+   val |= cm3_state;
+   mvpp2_cm3_write(port->priv, MSS_FC_COM_REG, val);
+
+   spin_unlock_irqrestore(&port->priv->mss_spinlock, flags);
+}
+
 /* Release buffer to BM */
 static inline void mvpp2_bm_pool_put(struct mvpp2_port *port, int pool,
 dma_addr_t buf_dma_addr,
@@ -1176,6 +1229,16 @@ static int mvpp2_bm_update_mtu(struct net_device *dev, 
int mtu)
new_long_pool = MVPP2_BM_LONG;
 
if (new_long_pool != port->pool_long->id) {
+   if (port->tx_fc) {
+   if (pkt_size > MVPP2_BM_LONG_PKT_SIZE)
+   mvpp2_bm_pool_update_fc(port,
+

[RESEND PATCH v8 net-next 12/15] net: mvpp2: add BM protection underrun feature support

[stefanc]

From: Stefan Chulski 

The PP2v23 hardware supports a feature allowing to double the
size of BPPI by decreasing number of pools from 16 to 8.
Increasing of BPPI size protect BM drop from BPPI underrun.
Underrun could occurred due to stress on DDR and as result slow buffer
transition from BPPE to BPPI.
New BPPI threshold recommended by spec is:
BPPI low threshold - 640 buffers
BPPI high threshold - 832 buffers
Supported only in PPv23.

Signed-off-by: Stefan Chulski 
---
 drivers/net/ethernet/marvell/mvpp2/mvpp2.h  |  8 +
 drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c | 35 +++-
 2 files changed, 42 insertions(+), 1 deletion(-)

diff --git a/drivers/net/ethernet/marvell/mvpp2/mvpp2.h 
b/drivers/net/ethernet/marvell/mvpp2/mvpp2.h
index 9071ab6..1967493 100644
--- a/drivers/net/ethernet/marvell/mvpp2/mvpp2.h
+++ b/drivers/net/ethernet/marvell/mvpp2/mvpp2.h
@@ -324,6 +324,10 @@
 #define MVPP2_BM_HIGH_THRESH_MASK  0x7f
 #define MVPP2_BM_HIGH_THRESH_VALUE(val)((val) << \
MVPP2_BM_HIGH_THRESH_OFFS)
+#define MVPP2_BM_BPPI_HIGH_THRESH  0x1E
+#define MVPP2_BM_BPPI_LOW_THRESH   0x1C
+#define MVPP23_BM_BPPI_HIGH_THRESH 0x34
+#define MVPP23_BM_BPPI_LOW_THRESH  0x28
 #define MVPP2_BM_INTR_CAUSE_REG(pool)  (0x6240 + ((pool) * 4))
 #define MVPP2_BM_RELEASED_DELAY_MASK   BIT(0)
 #define MVPP2_BM_ALLOC_FAILED_MASK BIT(1)
@@ -352,6 +356,10 @@
 #define MVPP2_OVERRUN_ETH_DROP 0x7000
 #define MVPP2_CLS_ETH_DROP 0x7020
 
+#define MVPP22_BM_POOL_BASE_ADDR_HIGH_REG  0x6310
+#define MVPP22_BM_POOL_BASE_ADDR_HIGH_MASK 0xff
+#define MVPP23_BM_8POOL_MODE   BIT(8)
+
 /* Hit counters registers */
 #define MVPP2_CTRS_IDX 0x7040
 #define MVPP22_CTRS_TX_CTR(port, txq)  ((txq) | ((port) << 3) | BIT(7))
diff --git a/drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c 
b/drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c
index 5d80c5e..e41b173 100644
--- a/drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c
+++ b/drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c
@@ -70,6 +70,11 @@ enum mvpp2_bm_pool_log_num {
 module_param(queue_mode, int, 0444);
 MODULE_PARM_DESC(queue_mode, "Set queue_mode (single=0, multi=1)");
 
+static int bm_underrun_protect = 1;
+
+module_param(bm_underrun_protect, int, 0444);
+MODULE_PARM_DESC(bm_underrun_protect, "Set BM underrun protect feature (0-1), 
def=1");
+
 /* Utility/helper methods */
 
 void mvpp2_write(struct mvpp2 *priv, u32 offset, u32 data)
@@ -424,6 +429,21 @@ static int mvpp2_bm_pool_create(struct device *dev, struct 
mvpp2 *priv,
 
val = mvpp2_read(priv, MVPP2_BM_POOL_CTRL_REG(bm_pool->id));
val |= MVPP2_BM_START_MASK;
+
+   val &= ~MVPP2_BM_LOW_THRESH_MASK;
+   val &= ~MVPP2_BM_HIGH_THRESH_MASK;
+
+   /* Set 8 Pools BPPI threshold if BM underrun protection feature
+* was enabled
+*/
+   if (priv->hw_version == MVPP23 && bm_underrun_protect) {
+   val |= MVPP2_BM_LOW_THRESH_VALUE(MVPP23_BM_BPPI_LOW_THRESH);
+   val |= MVPP2_BM_HIGH_THRESH_VALUE(MVPP23_BM_BPPI_HIGH_THRESH);
+   } else {
+   val |= MVPP2_BM_LOW_THRESH_VALUE(MVPP2_BM_BPPI_LOW_THRESH);
+   val |= MVPP2_BM_HIGH_THRESH_VALUE(MVPP2_BM_BPPI_HIGH_THRESH);
+   }
+
mvpp2_write(priv, MVPP2_BM_POOL_CTRL_REG(bm_pool->id), val);
 
bm_pool->size = size;
@@ -592,6 +612,16 @@ static int mvpp2_bm_pools_init(struct device *dev, struct 
mvpp2 *priv)
return err;
 }
 
+/* Routine enable PPv23 8 pool mode */
+static void mvpp23_bm_set_8pool_mode(struct mvpp2 *priv)
+{
+   int val;
+
+   val = mvpp2_read(priv, MVPP22_BM_POOL_BASE_ADDR_HIGH_REG);
+   val |= MVPP23_BM_8POOL_MODE;
+   mvpp2_write(priv, MVPP22_BM_POOL_BASE_ADDR_HIGH_REG, val);
+}
+
 static int mvpp2_bm_init(struct device *dev, struct mvpp2 *priv)
 {
enum dma_data_direction dma_dir = DMA_FROM_DEVICE;
@@ -645,6 +675,9 @@ static int mvpp2_bm_init(struct device *dev, struct mvpp2 
*priv)
if (!priv->bm_pools)
return -ENOMEM;
 
+   if (priv->hw_version == MVPP23 && bm_underrun_protect)
+   mvpp23_bm_set_8pool_mode(priv);
+
err = mvpp2_bm_pools_init(dev, priv);
if (err < 0)
return err;
@@ -6491,7 +6524,7 @@ static void mvpp2_mac_link_up(struct phylink_config 
*config,
 val);
}
 
-   if (port->priv->global_tx_fc) {
+   if (port->priv->global_tx_fc && bm_underrun_protect) {
port->tx_fc = tx_pause;
if (tx_pause)
mvpp2_rxq_enable_fc(port);
-- 
1.9.1

[RESEND PATCH v8 net-next 09/15] net: mvpp2: enable global flow control

[stefanc]

From: Stefan Chulski 

This patch enables global flow control in FW and in the phylink validate mask.

Signed-off-by: Stefan Chulski 
---
 drivers/net/ethernet/marvell/mvpp2/mvpp2.h  | 13 ++---
 drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c | 30 +++-
 2 files changed, 38 insertions(+), 5 deletions(-)

diff --git a/drivers/net/ethernet/marvell/mvpp2/mvpp2.h 
b/drivers/net/ethernet/marvell/mvpp2/mvpp2.h
index ca84995..e010410 100644
--- a/drivers/net/ethernet/marvell/mvpp2/mvpp2.h
+++ b/drivers/net/ethernet/marvell/mvpp2/mvpp2.h
@@ -763,10 +763,12 @@
((kb) * 1024 - MVPP2_TX_FIFO_THRESHOLD_MIN)
 
 /* MSS Flow control */
-#define MSS_SRAM_SIZE  0x800
-#define FC_QUANTA  0x
-#define FC_CLK_DIVIDER 100
-#define MSS_THRESHOLD_STOP 768
+#define MSS_SRAM_SIZE  0x800
+#define MSS_FC_COM_REG 0
+#define FLOW_CONTROL_ENABLE_BITBIT(0)
+#define FC_QUANTA  0x
+#define FC_CLK_DIVIDER 100
+#define MSS_THRESHOLD_STOP 768
 
 /* RX buffer constants */
 #define MVPP2_SKB_SHINFO_SIZE \
@@ -1021,6 +1023,9 @@ struct mvpp2 {
 
/* CM3 SRAM pool */
struct gen_pool *sram_pool;
+
+   /* Global TX Flow Control config */
+   bool global_tx_fc;
 };
 
 struct mvpp2_pcpu_stats {
diff --git a/drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c 
b/drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c
index a72a390..fec1c81 100644
--- a/drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c
+++ b/drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c
@@ -92,6 +92,16 @@ static inline u32 mvpp2_cpu_to_thread(struct mvpp2 *priv, 
int cpu)
return cpu % priv->nthreads;
 }
 
+static void mvpp2_cm3_write(struct mvpp2 *priv, u32 offset, u32 data)
+{
+   writel(data, priv->cm3_base + offset);
+}
+
+static u32 mvpp2_cm3_read(struct mvpp2 *priv, u32 offset)
+{
+   return readl(priv->cm3_base + offset);
+}
+
 static struct page_pool *
 mvpp2_create_page_pool(struct device *dev, int num, int len,
   enum dma_data_direction dma_dir)
@@ -5951,6 +5961,11 @@ static void mvpp2_phylink_validate(struct phylink_config 
*config,
phylink_set(mask, Autoneg);
phylink_set_port_modes(mask);
 
+   if (port->priv->global_tx_fc) {
+   phylink_set(mask, Pause);
+   phylink_set(mask, Asym_Pause);
+   }
+
switch (state->interface) {
case PHY_INTERFACE_MODE_10GBASER:
case PHY_INTERFACE_MODE_XAUI:
@@ -6969,7 +6984,7 @@ static int mvpp2_probe(struct platform_device *pdev)
struct resource *res;
void __iomem *base;
int i, shared;
-   int err;
+   int err, val;
 
priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL);
if (!priv)
@@ -7023,6 +7038,10 @@ static int mvpp2_probe(struct platform_device *pdev)
return err;
else if (err)
dev_warn(&pdev->dev, "Fail to alloc CM3 SRAM\n");
+
+   /* Enable global Flow Control only if handler to SRAM not NULL 
*/
+   if (priv->cm3_base)
+   priv->global_tx_fc = true;
}
 
if (priv->hw_version != MVPP21 && dev_of_node(&pdev->dev)) {
@@ -7190,6 +7209,15 @@ static int mvpp2_probe(struct platform_device *pdev)
goto err_port_probe;
}
 
+   /* Enable global flow control. In this stage global
+* flow control enabled, but still disabled per port.
+*/
+   if (priv->global_tx_fc && priv->hw_version != MVPP21) {
+   val = mvpp2_cm3_read(priv, MSS_FC_COM_REG);
+   val |= FLOW_CONTROL_ENABLE_BIT;
+   mvpp2_cm3_write(priv, MSS_FC_COM_REG, val);
+   }
+
mvpp2_dbgfs_init(priv, pdev->name);
 
platform_set_drvdata(pdev, priv);
-- 
1.9.1

[RESEND PATCH v8 net-next 13/15] net: mvpp2: add PPv23 RX FIFO flow control

[stefanc]

From: Stefan Chulski 

New FIFO flow control feature was added in PPv23.
PPv2 FIFO polled by HW and trigger pause frame if FIFO
fill level is below threshold.
FIFO HW flow control enabled with CM3 RXQ&BM flow
control with ethtool.
Current  FIFO thresholds is:
9KB for port with maximum speed 10Gb/s port
4KB for port with maximum speed 5Gb/s port
2KB for port with maximum speed 1Gb/s port

Signed-off-by: Stefan Chulski 
---
 drivers/net/ethernet/marvell/mvpp2/mvpp2.h  | 15 ++
 drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c | 53 
 2 files changed, 68 insertions(+)

diff --git a/drivers/net/ethernet/marvell/mvpp2/mvpp2.h 
b/drivers/net/ethernet/marvell/mvpp2/mvpp2.h
index 1967493..9947385 100644
--- a/drivers/net/ethernet/marvell/mvpp2/mvpp2.h
+++ b/drivers/net/ethernet/marvell/mvpp2/mvpp2.h
@@ -770,6 +770,18 @@
 #define MVPP2_TX_FIFO_THRESHOLD(kb)\
((kb) * 1024 - MVPP2_TX_FIFO_THRESHOLD_MIN)
 
+/* RX FIFO threshold in 1KB granularity */
+#define MVPP23_PORT0_FIFO_TRSH (9 * 1024)
+#define MVPP23_PORT1_FIFO_TRSH (4 * 1024)
+#define MVPP23_PORT2_FIFO_TRSH (2 * 1024)
+
+/* RX Flow Control Registers */
+#define MVPP2_RX_FC_REG(port)  (0x150 + 4 * (port))
+#define MVPP2_RX_FC_EN BIT(24)
+#define MVPP2_RX_FC_TRSH_OFFS  16
+#define MVPP2_RX_FC_TRSH_MASK  (0xFF << MVPP2_RX_FC_TRSH_OFFS)
+#define MVPP2_RX_FC_TRSH_UNIT  256
+
 /* MSS Flow control */
 #define MSS_SRAM_SIZE  0x800
 #define MSS_FC_COM_REG 0
@@ -1502,6 +1514,8 @@ struct mvpp2_bm_pool {
 
 void mvpp2_dbgfs_cleanup(struct mvpp2 *priv);
 
+void mvpp23_rx_fifo_fc_en(struct mvpp2 *priv, int port, bool en);
+
 #ifdef CONFIG_MVPP2_PTP
 int mvpp22_tai_probe(struct device *dev, struct mvpp2 *priv);
 void mvpp22_tai_tstamp(struct mvpp2_tai *tai, u32 tstamp,
@@ -1534,4 +1548,5 @@ static inline bool mvpp22_rx_hwtstamping(struct 
mvpp2_port *port)
 {
return IS_ENABLED(CONFIG_MVPP2_PTP) && port->rx_hwtstamp;
 }
+
 #endif
diff --git a/drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c 
b/drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c
index e41b173..5a51697 100644
--- a/drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c
+++ b/drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c
@@ -6537,6 +6537,8 @@ static void mvpp2_mac_link_up(struct phylink_config 
*config,
mvpp2_bm_pool_update_fc(port, port->pool_long, 
tx_pause);
mvpp2_bm_pool_update_fc(port, port->pool_short, 
tx_pause);
}
+   if (port->priv->hw_version == MVPP23)
+   mvpp23_rx_fifo_fc_en(port->priv, port->id, tx_pause);
}
 
mvpp2_port_enable(port);
@@ -7005,6 +7007,55 @@ static void mvpp22_rx_fifo_init(struct mvpp2 *priv)
mvpp2_write(priv, MVPP2_RX_FIFO_INIT_REG, 0x1);
 }
 
+/* Configure Rx FIFO Flow control thresholds */
+static void mvpp23_rx_fifo_fc_set_tresh(struct mvpp2 *priv)
+{
+   int port, val;
+
+   /* Port 0: maximum speed -10Gb/s port
+* required by spec RX FIFO threshold 9KB
+* Port 1: maximum speed -5Gb/s port
+* required by spec RX FIFO threshold 4KB
+* Port 2: maximum speed -1Gb/s port
+* required by spec RX FIFO threshold 2KB
+*/
+
+   /* Without loopback port */
+   for (port = 0; port < (MVPP2_MAX_PORTS - 1); port++) {
+   if (port == 0) {
+   val = (MVPP23_PORT0_FIFO_TRSH / MVPP2_RX_FC_TRSH_UNIT)
+   << MVPP2_RX_FC_TRSH_OFFS;
+   val &= MVPP2_RX_FC_TRSH_MASK;
+   mvpp2_write(priv, MVPP2_RX_FC_REG(port), val);
+   } else if (port == 1) {
+   val = (MVPP23_PORT1_FIFO_TRSH / MVPP2_RX_FC_TRSH_UNIT)
+   << MVPP2_RX_FC_TRSH_OFFS;
+   val &= MVPP2_RX_FC_TRSH_MASK;
+   mvpp2_write(priv, MVPP2_RX_FC_REG(port), val);
+   } else {
+   val = (MVPP23_PORT2_FIFO_TRSH / MVPP2_RX_FC_TRSH_UNIT)
+   << MVPP2_RX_FC_TRSH_OFFS;
+   val &= MVPP2_RX_FC_TRSH_MASK;
+   mvpp2_write(priv, MVPP2_RX_FC_REG(port), val);
+   }
+   }
+}
+
+/* Configure Rx FIFO Flow control thresholds */
+void mvpp23_rx_fifo_fc_en(struct mvpp2 *priv, int port, bool en)
+{
+   int val;
+
+   val = mvpp2_read(priv, MVPP2_RX_FC_REG(port));
+
+   if (en)
+   val |= MVPP2_RX_FC_EN;
+   else
+   val &= ~MVPP2_RX_FC_EN;
+
+   mvpp2_write(priv, MVPP2_RX_FC_REG(port), val);
+}
+
 static void mvpp22_tx_fifo_set_hw(struct mvpp2 *priv, int port, int size)
 {
int threshold = MVPP2_TX_FIFO_THRESHOLD(size);
@@ -7156,6 +7207,8 @@ static int mvpp2_init(struct platform_device *pdev, 
struct mvpp2 *priv)
} else {
mvpp22_rx_fifo_init(priv);
   

Re: Linux 4.4.256

[Greg Kroah-Hartman]

On Sat, Feb 06, 2021 at 10:49:26AM -0800, Guenter Roeck wrote:
> On Sat, Feb 06, 2021 at 07:13:39PM +0100, Greg Kroah-Hartman wrote:
> > On Sat, Feb 06, 2021 at 08:59:42AM -0800, Guenter Roeck wrote:
> > > On 2/6/21 5:22 AM, Willy Tarreau wrote:
> > > > On Sat, Feb 06, 2021 at 02:11:13PM +0100, Willy Tarreau wrote:
> > > >> Something like this looks more robust to me, it will use SUBLEVEL for
> > > >> values 0 to 255 and 255 for any larger value:
> > > >>
> > > >> -  expr $(VERSION) \* 65536 + 0$(PATCHLEVEL) \* 256 + 
> > > >> 0$(SUBLEVEL)); \
> > > >> +  expr $(VERSION) \* 65536 + 0$(PATCHLEVEL) \* 256 + 255 \* 
> > > >> (0$(SUBLEVEL) > 255) + 0$(SUBLEVEL) * (0$(SUBLEVEL \<= 255)); \
> > > > 
> > > > Bah, I obviously missed a backslash above and forgot spaces around 
> > > > parens.
> > > > Here's a tested version:
> > > > 
> > > > diff --git a/Makefile b/Makefile
> > > > index 7d86ad6ad36c..9b91b8815b40 100644
> > > > --- a/Makefile
> > > > +++ b/Makefile
> > > > @@ -1252,7 +1252,7 @@ endef
> > > >  
> > > >  define filechk_version.h
> > > > echo \#define LINUX_VERSION_CODE $(shell
> > > >  \
> > > > -   expr $(VERSION) \* 65536 + 0$(PATCHLEVEL) \* 256 + 
> > > > 0$(SUBLEVEL)); \
> > > > +   expr $(VERSION) \* 65536 + 0$(PATCHLEVEL) \* 256 + 255 \* \( 
> > > > 0$(SUBLEVEL) \> 255 \) + 0$(SUBLEVEL) \* \( 0$(SUBLEVEL) \<= 255 \) ); \
> > > > echo '#define KERNEL_VERSION(a,b,c) (((a) << 16) + ((b) << 8) + 
> > > > (c))'
> > > >  endef
> > > >  
> > > 
> > > I like that version.
> > 
> > See the patch that Sasha queued up already, it just fixes it at 255 for
> > now, and we will update with what is in Linus's tree like the above when
> > that gets merged in 5.12-rc1.
> > 
> > > Two questions: Are there any concerns that KERNEL_VERSION(4, 4, 256)
> > > matches KERNEL_VERSION(4, 5. 0),
> > 
> > As that "release" did nothing, no, I'm not too worried about it, are
> > you?
> > 
> There are lots (35) of "KERNEL_VERSION(4, 5, 0)" in chromeos-4.4.
> That should not matter with the clamped LINUX_VERSION_CODE, but
> I'd prefer to clamp KERNEL_VERSION as well just to be sure. On
> top of that, some of the vendor code we carry along does check
> SUBVERSION, but that is probably more of an academic concern.

Ah, the internal checks, I think the other patch by Sasha will let that
get bigger and should work for you as well.  Can you try it out?

thanks,

greg k-h

[RESEND PATCH v8 net-next 14/15] net: mvpp2: set 802.3x GoP Flow Control mode

[stefanc]

From: Stefan Chulski 

This patch fix GMAC TX flow control autoneg.
Flow control autoneg wrongly were disabled with enabled TX
flow control.

Signed-off-by: Stefan Chulski 
---
 drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c 
b/drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c
index 5a51697..5526214 100644
--- a/drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c
+++ b/drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c
@@ -6284,7 +6284,7 @@ static void mvpp2_gmac_config(struct mvpp2_port *port, 
unsigned int mode,
old_ctrl4 = ctrl4 = readl(port->base + MVPP22_GMAC_CTRL_4_REG);
 
ctrl0 &= ~MVPP2_GMAC_PORT_TYPE_MASK;
-   ctrl2 &= ~(MVPP2_GMAC_INBAND_AN_MASK | MVPP2_GMAC_PCS_ENABLE_MASK);
+   ctrl2 &= ~(MVPP2_GMAC_INBAND_AN_MASK | MVPP2_GMAC_PCS_ENABLE_MASK | 
MVPP2_GMAC_FLOW_CTRL_MASK);
 
/* Configure port type */
if (phy_interface_mode_is_8023z(state->interface)) {
-- 
1.9.1

Re: [RFC 0/9] Linear Address Masking enabling

[Dmitry Vyukov]

On Fri, Feb 5, 2021 at 4:16 PM Kirill A. Shutemov
 wrote:
>
> Linear Address Masking[1] (LAM) modifies the checking that is applied to
> 64-bit linear addresses, allowing software to use of the untranslated
> address bits for metadata.
>
> The patchset brings support for LAM for userspace addresses.
>
> The most sensitive part of enabling is change in tlb.c, where CR3 flags
> get set. Please take a look that what I'm doing makes sense.
>
> The patchset is RFC quality and the code requires more testing before it
> can be applied.
>
> The userspace API is not finalized yet. The patchset extends API used by
> ARM64: PR_GET/SET_TAGGED_ADDR_CTRL. The API is adjusted to not imply ARM
> TBI: it now allows to request a number of bits of metadata needed and
> report where these bits are located in the address.
>
> There's an alternative proposal[2] for the API based on Intel CET
> interface. Please let us know if you prefer one over another.
>
> The feature competes for bits with 5-level paging: LAM_U48 makes it
> impossible to map anything about 47-bits. The patchset made these
> capability mutually exclusive: whatever used first wins. LAM_U57 can be
> combined with mappings above 47-bits.
>
> I include QEMU patch in case if somebody wants to play with the feature.

Exciting! Do you plan to send the QEMU patch to QEMU?

> The branch:
>
> git://git.kernel.org/pub/scm/linux/kernel/git/kas/linux.git lam
>
> Any comments are welcome.
>
> [1] ISE, Chapter 14. 
> https://software.intel.com/content/dam/develop/external/us/en/documents-tps/architecture-instruction-set-extensions-programming-reference.pdf
> [2] 
> https://github.com/hjl-tools/linux/commit/e85fa032e5b276ddf17edd056f92f599db9e8369
>
> Kirill A. Shutemov (9):
>   mm, arm64: Update PR_SET/GET_TAGGED_ADDR_CTRL interface
>   x86/mm: Fix CR3_ADDR_MASK
>   x86: CPUID and CR3/CR4 flags for Linear Address Masking
>   x86/mm: Introduce TIF_LAM_U57 and TIF_LAM_U48
>   x86/mm: Provide untagged_addr() helper
>   x86/uaccess: Remove tags from the address before checking
>   x86/mm: Handle tagged memory accesses from kernel threads
>   x86/mm: Make LAM_U48 and mappings above 47-bits mutually exclusive
>   x86/mm: Implement PR_SET/GET_TAGGED_ADDR_CTRL with LAM
>
>  arch/arm64/include/asm/processor.h|  12 +-
>  arch/arm64/kernel/process.c   |  45 +-
>  arch/arm64/kernel/ptrace.c|   4 +-
>  arch/x86/include/asm/cpufeatures.h|   1 +
>  arch/x86/include/asm/elf.h|   3 +-
>  arch/x86/include/asm/mmu.h|   1 +
>  arch/x86/include/asm/mmu_context.h|  13 ++
>  arch/x86/include/asm/page_32.h|   3 +
>  arch/x86/include/asm/page_64.h|  19 +++
>  arch/x86/include/asm/processor-flags.h|   2 +-
>  arch/x86/include/asm/processor.h  |  10 ++
>  arch/x86/include/asm/thread_info.h|   9 +-
>  arch/x86/include/asm/tlbflush.h   |   5 +
>  arch/x86/include/asm/uaccess.h|  16 +-
>  arch/x86/include/uapi/asm/processor-flags.h   |   6 +
>  arch/x86/kernel/process_64.c  | 145 ++
>  arch/x86/kernel/sys_x86_64.c  |   5 +-
>  arch/x86/mm/hugetlbpage.c |   6 +-
>  arch/x86/mm/mmap.c|   9 +-
>  arch/x86/mm/tlb.c | 124 +--
>  kernel/sys.c  |  14 +-
>  .../testing/selftests/arm64/tags/tags_test.c  |  31 
>  .../selftests/{arm64 => vm}/tags/.gitignore   |   0
>  .../selftests/{arm64 => vm}/tags/Makefile |   0
>  .../{arm64 => vm}/tags/run_tags_test.sh   |   0
>  tools/testing/selftests/vm/tags/tags_test.c   |  57 +++
>  26 files changed, 464 insertions(+), 76 deletions(-)
>  delete mode 100644 tools/testing/selftests/arm64/tags/tags_test.c
>  rename tools/testing/selftests/{arm64 => vm}/tags/.gitignore (100%)
>  rename tools/testing/selftests/{arm64 => vm}/tags/Makefile (100%)
>  rename tools/testing/selftests/{arm64 => vm}/tags/run_tags_test.sh (100%)
>  create mode 100644 tools/testing/selftests/vm/tags/tags_test.c
>
> --
> 2.26.2
>

[RESEND PATCH v8 net-next 15/15] net: mvpp2: add TX FC firmware check

[stefanc]

From: Stefan Chulski 

Patch check that TX FC firmware is running in CM3.
If not, global TX FC would be disabled.

Signed-off-by: Stefan Chulski 
---
 drivers/net/ethernet/marvell/mvpp2/mvpp2.h  |  1 +
 drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c | 42 
 2 files changed, 36 insertions(+), 7 deletions(-)

diff --git a/drivers/net/ethernet/marvell/mvpp2/mvpp2.h 
b/drivers/net/ethernet/marvell/mvpp2/mvpp2.h
index 9947385..25013a4 100644
--- a/drivers/net/ethernet/marvell/mvpp2/mvpp2.h
+++ b/drivers/net/ethernet/marvell/mvpp2/mvpp2.h
@@ -829,6 +829,7 @@
 
 #define MSS_THRESHOLD_STOP 768
 #define MSS_THRESHOLD_START1024
+#define MSS_FC_MAX_TIMEOUT 5000
 
 /* RX buffer constants */
 #define MVPP2_SKB_SHINFO_SIZE \
diff --git a/drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c 
b/drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c
index 5526214..dfc2e71 100644
--- a/drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c
+++ b/drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c
@@ -932,6 +932,34 @@ static void mvpp2_bm_pool_update_fc(struct mvpp2_port 
*port,
spin_unlock_irqrestore(&port->priv->mss_spinlock, flags);
 }
 
+static int mvpp2_enable_global_fc(struct mvpp2 *priv)
+{
+   int val, timeout = 0;
+
+   /* Enable global flow control. In this stage global
+* flow control enabled, but still disabled per port.
+*/
+   val = mvpp2_cm3_read(priv, MSS_FC_COM_REG);
+   val |= FLOW_CONTROL_ENABLE_BIT;
+   mvpp2_cm3_write(priv, MSS_FC_COM_REG, val);
+
+   /* Check if Firmware running and disable FC if not*/
+   val |= FLOW_CONTROL_UPDATE_COMMAND_BIT;
+   mvpp2_cm3_write(priv, MSS_FC_COM_REG, val);
+
+   while (timeout < MSS_FC_MAX_TIMEOUT) {
+   val = mvpp2_cm3_read(priv, MSS_FC_COM_REG);
+
+   if (!(val & FLOW_CONTROL_UPDATE_COMMAND_BIT))
+   return 0;
+   usleep_range(10, 20);
+   timeout++;
+   }
+
+   priv->global_tx_fc = false;
+   return -EOPNOTSUPP;
+}
+
 /* Release buffer to BM */
 static inline void mvpp2_bm_pool_put(struct mvpp2_port *port, int pool,
 dma_addr_t buf_dma_addr,
@@ -7281,7 +7309,7 @@ static int mvpp2_probe(struct platform_device *pdev)
struct resource *res;
void __iomem *base;
int i, shared;
-   int err, val;
+   int err;
 
priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL);
if (!priv)
@@ -7509,13 +7537,13 @@ static int mvpp2_probe(struct platform_device *pdev)
goto err_port_probe;
}
 
-   /* Enable global flow control. In this stage global
-* flow control enabled, but still disabled per port.
-*/
if (priv->global_tx_fc && priv->hw_version != MVPP21) {
-   val = mvpp2_cm3_read(priv, MSS_FC_COM_REG);
-   val |= FLOW_CONTROL_ENABLE_BIT;
-   mvpp2_cm3_write(priv, MSS_FC_COM_REG, val);
+   err = mvpp2_enable_global_fc(priv);
+   if (err) {
+   dev_warn(&pdev->dev, "CM3 firmware not running, version 
should be higher than 18.09 ");
+   dev_warn(&pdev->dev, "and chip revision B0\n");
+   dev_warn(&pdev->dev, "Flow control not supported\n");
+   }
}
 
mvpp2_dbgfs_init(priv, pdev->name);
-- 
1.9.1

[RFC PATCH v3 1/2] mempinfd: Add new syscall to provide memory pin

[Zhou Wang]

SVA(share virtual address) offers a way for device to share process virtual
address space safely, which makes more convenient for user space device
driver coding. However, IO page faults may happen when doing DMA
operations. As the latency of IO page fault is relatively big, DMA
performance will be affected severely when there are IO page faults.
>From a long term view, DMA performance will be not stable.

In high-performance I/O cases, accelerators might want to perform
I/O on a memory without IO page faults which can result in dramatically
increased latency. Current memory related APIs could not achieve this
requirement, e.g. mlock can only avoid memory to swap to backup device,
page migration can still trigger IO page fault.

Various drivers working under traditional non-SVA mode are using
their own specific ioctl to do pin. Such ioctl can be seen in v4l2,
gpu, infiniband, media, vfio, etc. Drivers are usually doing dma
mapping while doing pin.

But, in SVA mode, pin could be a common need which isn't necessarily
bound with any drivers, and neither is dma mapping needed by drivers
since devices are using the virtual address of CPU. Thus, It is better
to introduce a new common syscall for it.

This patch leverages the design of userfaultfd and adds mempinfd for pin
to avoid messing up mm_struct. A fd will be got by mempinfd, then user
space can do pin/unpin pages by ioctls of this fd, all pinned pages under
one file will be unpinned in file release process. Like pin page cases in
other places, can_do_mlock is used to check permission and input
parameters.

Signed-off-by: Zhou Wang 
Signed-off-by: Sihang Chen 
Suggested-by: Barry Song 
---
 arch/arm64/include/asm/unistd.h   |   2 +-
 arch/arm64/include/asm/unistd32.h |   2 +
 fs/Makefile   |   1 +
 fs/mempinfd.c | 199 ++
 include/linux/syscalls.h  |   1 +
 include/uapi/asm-generic/unistd.h |   4 +-
 include/uapi/linux/mempinfd.h |  23 +
 init/Kconfig  |   6 ++
 8 files changed, 236 insertions(+), 2 deletions(-)
 create mode 100644 fs/mempinfd.c
 create mode 100644 include/uapi/linux/mempinfd.h

diff --git a/arch/arm64/include/asm/unistd.h b/arch/arm64/include/asm/unistd.h
index 86a9d7b3..949788f 100644
--- a/arch/arm64/include/asm/unistd.h
+++ b/arch/arm64/include/asm/unistd.h
@@ -38,7 +38,7 @@
 #define __ARM_NR_compat_set_tls(__ARM_NR_COMPAT_BASE + 5)
 #define __ARM_NR_COMPAT_END(__ARM_NR_COMPAT_BASE + 0x800)
 
-#define __NR_compat_syscalls   442
+#define __NR_compat_syscalls   443
 #endif
 
 #define __ARCH_WANT_SYS_CLONE
diff --git a/arch/arm64/include/asm/unistd32.h 
b/arch/arm64/include/asm/unistd32.h
index cccfbbe..3f49529 100644
--- a/arch/arm64/include/asm/unistd32.h
+++ b/arch/arm64/include/asm/unistd32.h
@@ -891,6 +891,8 @@ __SYSCALL(__NR_faccessat2, sys_faccessat2)
 __SYSCALL(__NR_process_madvise, sys_process_madvise)
 #define __NR_epoll_pwait2 441
 __SYSCALL(__NR_epoll_pwait2, compat_sys_epoll_pwait2)
+#define __NR_mempinfd 442
+__SYSCALL(__NR_mempinfd, sys_mempinfd)
 
 /*
  * Please add new compat syscalls above this comment and update
diff --git a/fs/Makefile b/fs/Makefile
index 999d1a2..e1cbf12 100644
--- a/fs/Makefile
+++ b/fs/Makefile
@@ -54,6 +54,7 @@ obj-$(CONFIG_COREDUMP)+= coredump.o
 obj-$(CONFIG_SYSCTL)   += drop_caches.o
 
 obj-$(CONFIG_FHANDLE)  += fhandle.o
+obj-$(CONFIG_MEMPINFD) += mempinfd.o
 obj-y  += iomap/
 
 obj-y  += quota/
diff --git a/fs/mempinfd.c b/fs/mempinfd.c
new file mode 100644
index 000..23d3911
--- /dev/null
+++ b/fs/mempinfd.c
@@ -0,0 +1,199 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/* Copyright (c) 2021 HiSilicon Limited. */
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+struct mem_pin_container {
+   struct xarray array;
+   struct mutex lock;
+};
+
+struct pin_pages {
+   unsigned long first;
+   unsigned long nr_pages;
+   struct page **pages;
+};
+
+static int mempinfd_release(struct inode *inode, struct file *file)
+{
+   struct mem_pin_container *priv = file->private_data;
+   struct pin_pages *p;
+   unsigned long idx;
+
+   xa_for_each(&priv->array, idx, p) {
+   unpin_user_pages(p->pages, p->nr_pages);
+   xa_erase(&priv->array, p->first);
+   vfree(p->pages);
+   kfree(p);
+   }
+
+   mutex_destroy(&priv->lock);
+   xa_destroy(&priv->array);
+   kfree(priv);
+
+   return 0;
+}
+
+static int mempinfd_input_check(u64 addr, u64 size)
+{
+   if (!size || addr + size < addr)
+   return -EINVAL;
+
+   if (!can_do_mlock())
+   return -EPERM;
+
+   return 0;
+}
+
+static int mem_pin_page(struct mem_pin_container *priv,
+   struct mem_pin_a

[RFC PATCH v3 0/2] mempinfd: Add new syscall to provide memory pin

[Zhou Wang]

This series adds a new mempinfd syscall to offer a common way to pin/unpin
memory.

Patch 1/2 is about mempinfd codes.
Patch 2/2 adds a simple test tool about mempinfd.

Change logs:

v2 -> v3:
 - Follow suggestions from Greg and Kevin, add a new syscall.
 - Add input check.
 - Use xa_insert to replace xa_store.
 - Add lock to pretect pin and xa_insert.
v1 -> v2:
 - Some tiny fixes.
 - Follow Greg's suggestion to get mm-list and iommu-list involved.

Links:
--
 - v2: https://www.spinics.net/lists/kernel/msg3808926.html
 - v1: https://www.spinics.net/lists/kernel/msg3805205.html

Zhou Wang (2):
  mempinfd: Add new syscall to provide memory pin
  selftests/vm: add mempinfd test

 arch/arm64/include/asm/unistd.h   |   2 +-
 arch/arm64/include/asm/unistd32.h |   2 +
 fs/Makefile   |   1 +
 fs/mempinfd.c | 199 ++
 include/linux/syscalls.h  |   1 +
 include/uapi/asm-generic/unistd.h |   4 +-
 include/uapi/linux/mempinfd.h |  23 
 init/Kconfig  |   6 +
 tools/testing/selftests/vm/Makefile   |   1 +
 tools/testing/selftests/vm/mempinfd.c | 131 ++
 10 files changed, 368 insertions(+), 2 deletions(-)
 create mode 100644 fs/mempinfd.c
 create mode 100644 include/uapi/linux/mempinfd.h
 create mode 100644 tools/testing/selftests/vm/mempinfd.c

-- 
2.8.1

[RFC PATCH v3 2/2] selftests/vm: add mempinfd test

[Zhou Wang]

This test gets a fd from new mempinfd syscall and creates multiple threads
to do pin/unpin memory.

Signed-off-by: Zhou Wang 
Suggested-by: Barry Song 
---
 tools/testing/selftests/vm/Makefile   |   1 +
 tools/testing/selftests/vm/mempinfd.c | 131 ++
 2 files changed, 132 insertions(+)
 create mode 100644 tools/testing/selftests/vm/mempinfd.c

diff --git a/tools/testing/selftests/vm/Makefile 
b/tools/testing/selftests/vm/Makefile
index d42115e..2d5b509 100644
--- a/tools/testing/selftests/vm/Makefile
+++ b/tools/testing/selftests/vm/Makefile
@@ -42,6 +42,7 @@ TEST_GEN_FILES += on-fault-limit
 TEST_GEN_FILES += thuge-gen
 TEST_GEN_FILES += transhuge-stress
 TEST_GEN_FILES += userfaultfd
+TEST_GEN_FILES += mempinfd
 
 ifeq ($(MACHINE),x86_64)
 CAN_BUILD_I386 := $(shell ./../x86/check_cc.sh $(CC) 
../x86/trivial_32bit_program.c -m32)
diff --git a/tools/testing/selftests/vm/mempinfd.c 
b/tools/testing/selftests/vm/mempinfd.c
new file mode 100644
index 000..51d5cbf
--- /dev/null
+++ b/tools/testing/selftests/vm/mempinfd.c
@@ -0,0 +1,131 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/* Copyright (c) 2021 HiSilicon Limited. */
+#define _GNU_SOURCE
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+#include "../kselftest.h"
+
+#ifdef __NR_mempinfd
+
+#define DEF_PIN_SIZE   (4096 * 1024)
+#define MAX_THREAD_NUM 20
+#define DEF_THREAD_NUM 1
+#define DEF_TIMES  1
+
+struct test_data {
+   int fd;
+   unsigned long mem_size;
+   unsigned long times;
+};
+
+static void *do_pin_test(void *data)
+{
+   struct mem_pin_address addr;
+   struct test_data *d = data;
+   unsigned long times;
+   int ret, fd;
+   int i = 0;
+   void *p;
+
+   p = malloc(d->mem_size);
+   if (!p) {
+   fprintf(stderr, "fail to allocate memory\n");
+   return NULL;
+   }
+
+   addr.addr = (__u64)p;
+   addr.size = d->mem_size;
+   times = d->mem_size;
+   fd = d->fd;
+
+   while (i++ < times) {
+   ret = ioctl(fd, MEM_CMD_PIN, &addr);
+   if (ret) {
+   fprintf(stderr, "fail to pin memory\n");
+   return NULL;
+   }
+
+   usleep(1000);
+
+   ret = ioctl(fd, MEM_CMD_UNPIN, &addr);
+   if (ret) {
+   fprintf(stderr, "fail to unpin memory\n");
+   return NULL;
+   }
+   }
+
+   free(p);
+
+   return NULL;
+}
+
+int main(int argc, char **argv)
+{
+   unsigned long thread_num = DEF_THREAD_NUM;
+   unsigned long mem_size = DEF_PIN_SIZE;
+   unsigned long times = DEF_TIMES;
+   pthread_t threads[MAX_THREAD_NUM];
+   struct test_data data;
+   int fd, opt, i;
+   int ret = 0;
+
+   while ((opt = getopt(argc, argv, "s:n:t:")) != -1) {
+   switch (opt) {
+   case 's':
+   mem_size = atoi(optarg);
+   break;
+   case 'n':
+   thread_num = atoi(optarg);
+   if (thread_num > MAX_THREAD_NUM)
+   return -1;
+   break;
+   case 't':
+   times = atoi(optarg);
+   break;
+   default:
+   return -1;
+   }
+   }
+
+   fd = syscall(__NR_mempinfd);
+   if (fd < 0) {
+   fprintf(stderr, "mempinfd syscall not available in this 
kernel\n");
+   return -1;
+   }
+
+   data.fd = fd;
+   data.mem_size = mem_size;
+   data.times = times;
+
+   for (i = 0; i < thread_num; i++) {
+   ret = pthread_create(&threads[i], NULL, do_pin_test, &data);
+   if (ret) {
+   fprintf(stderr, "fail to create thread %d: %d\n",
+   i, -errno);
+   return -1;
+   }
+   }
+
+   for (i = 0; i < thread_num; i++)
+   pthread_join(threads[i], NULL);
+
+   close(fd);
+
+   return 0;
+}
+
+#else /* __NR_mempinfd */
+
+#warning "missing __NR_mempinfd definition"
+int main(void)
+{
+   printf("skip: Skipping mempinfd test (missing __NR_mempinfd)\n");
+   return KSFT_SKIP;
+}
+
+#endif /* __NR_mempinfd */
-- 
2.8.1

Re: [PATCH 08/18] arm64: cpufeature: Add a feature for FIQ support

[Hector Martin 'marcan']

On 06/02/2021 22.58, Marc Zyngier wrote:

Hector Martin  wrote:

+static void cpu_sync_irq_to_fiq(struct arm64_cpu_capabilities const *cap)
+{
+   u64 daif = read_sysreg(daif);
+
+   /*
+* By this point in the boot process IRQs are likely masked and FIOs
+* aren't, so we need to sync things to avoid spurious early FIQs.
+*/
+
+   if (daif & PSR_I_BIT)
+   daif |= PSR_F_BIT;
+   else
+   daif &= ~PSR_F_BIT;
+
+   write_sysreg(daif, daif);


Could this happen too late? If, as explained above, we can get a FIQ
until we mask it here, what prevents something (a timer?) from kicking
and creating havoc just before the sync?


Nothing, other than timers not being enabled this early (hopefully the 
bootloader doesn't leave a rogue timer running for us...)



If the answer is "nothing", then it probably means that the default
behaviour should be to treat PSTATE.I and PSTATE.F as containing the
same value at all times, and not just as an afterthought when we
detect that we're on a CPU type or another.


I thought of this too. Originally I thought PSTATE.F was always set on 
other systems, and thus unmasking FIQs could cause problems if there is 
a pending rogue FIQ for some reason. However, while writing this patch I 
realized that as part of normal process state changes we already unmask 
FIQs anyway (see DAIF_PROCCTX).


Thus, in fact, this patch actually changes things (when the cpufeature 
is set) to mask FIQs in some cases where they currently aren't, and 
conversely to unmask them in some cases where they currently are. But 
the fact that FIQ masking is somewhat inconsistent to begin with 
suggests that we should be able to mess with it without causing breakage 
for other systems.


So I guess in this case it would be legitimate to just make I==F on 
every system, and if something breaks it should be fixed by making 
whatever is causing a rogue FIQ not do that, right?


That would leave the vector switcheroo as the only thing the cpufeature 
does, which would certainly simplify a lot of the patch.



This could expand into enabling Group-0 interrupts with GICv3 on
systems that have a single security state (such as virtual machines),
though I don't really see a good use case for it.


I could see having a separate vector path opening up the door for 
performance hacks for very specific use cases that want really low 
latency for *one* thing (e.g. the mess the Raspberry Pi folks do to work 
around that braindead USB controller's performance issues), though I 
imagine there would have to be very compelling reasons to develop a 
framework to do this sanely upstream.


Incidentally, I have a personal interest in real-time performance 
(especially audio); once the dust settles and we have a workable kernel 
for normal use I do hope to spend some time taking a deep dive into 
latencies and finding RT-unfriendly code, but that's pretty far off 
right now. Maybe PREEMPT_RT will even be merged by then :-) (I hope that 
without SMM to screw things up on these machines they might make very 
nice RT-capable boxes...)


--
Hector Martin "marcan" (mar...@marcan.st)
Public Key: https://mrcn.st/pub

Re: [PATCH] staging: emxx_udc: Fix incorrectly defined global

[Greg KH]

On Sun, Feb 07, 2021 at 05:30:31AM +0530, Kumar Kartikeya Dwivedi wrote:
> The global gpio_desc pointer and int were defined in the header,
> instead put the definitions in the translation unit and add an extern
> declaration for consumers of the header (currently only one, which is
> perhaps why the linker didn't complain about symbol collisions).
> 
> This fixes sparse related warnings for this driver:
> drivers/staging/emxx_udc/emxx_udc.c: note: in included file:
> drivers/staging/emxx_udc/emxx_udc.h:23:18: warning: symbol 'vbus_gpio' was 
> not declared. Should it be static?
> drivers/staging/emxx_udc/emxx_udc.h:24:5: warning: symbol 'vbus_irq' was not 
> declared. Should it be static?
> 
> Signed-off-by: Kumar Kartikeya Dwivedi 
> ---
>  drivers/staging/emxx_udc/emxx_udc.c | 3 +++
>  drivers/staging/emxx_udc/emxx_udc.h | 4 ++--
>  2 files changed, 5 insertions(+), 2 deletions(-)
> 
> diff --git a/drivers/staging/emxx_udc/emxx_udc.c 
> b/drivers/staging/emxx_udc/emxx_udc.c
> index a30b4f5b1..6983c3e31 100644
> --- a/drivers/staging/emxx_udc/emxx_udc.c
> +++ b/drivers/staging/emxx_udc/emxx_udc.c
> @@ -34,6 +34,9 @@
>  #define  DRIVER_DESC "EMXX UDC driver"
>  #define  DMA_ADDR_INVALID(~(dma_addr_t)0)
>  
> +struct gpio_desc *vbus_gpio;
> +int vbus_irq;

A tiny driver can not create global variables with generic names like
this, sorry.  That will polute the global namespace.

thanks,

greg k-h

Re: [PATCH] staging: emxx_udc: Fix incorrectly defined global

[Greg KH]

On Sun, Feb 07, 2021 at 01:08:27PM +0530, Kumar Kartikeya Dwivedi wrote:
> On Sun, Feb 07, 2021 at 12:04:41PM IST, Stephen Rothwell wrote:
> > 
> > Given that drivers/staging/emxx_udc/emxx_udc.h is only included by
> > drivers/staging/emxx_udc/emxx_udc.c, shouldn't these variables just be
> > declared static in emxx_udc.c and removed from emxx_udc.h?
> >
> 
> Either would be correct. I went this way because it was originally trying to
> (incorrectly) define a global variable instead. I guess they can be static now
> and when more users are added, the linkage can be adjusted as needed.
> 
> Here's another version of the patch:



Please resend in the proper format that a second version of a patch
should be in (the documentation describes how to do this.)

thanks,

greg k-h

[PATCH v2] jfs: turn diLog(), dataLog() and txLog() into void functions

[Yang Li]

These functions always return '0' and no callers use the return value.
So make it a void function.

This eliminates the following coccicheck warning:
./fs/jfs/jfs_txnmgr.c:1365:5-7: Unneeded variable: "rc". Return "0" on
line 1414
./fs/jfs/jfs_txnmgr.c:1422:5-7: Unneeded variable: "rc". Return "0" on
line 1527

Reported-by: Abaci Robot 
Signed-off-by: Yang Li 
---

Changes in v2
-turn functions forward references to void type.

 fs/jfs/jfs_txnmgr.c | 32 +++-
 1 file changed, 15 insertions(+), 17 deletions(-)

diff --git a/fs/jfs/jfs_txnmgr.c b/fs/jfs/jfs_txnmgr.c
index dca8edd..5f54a4c 100644
--- a/fs/jfs/jfs_txnmgr.c
+++ b/fs/jfs/jfs_txnmgr.c
@@ -148,10 +148,10 @@ static inline void TXN_SLEEP_DROP_LOCK(wait_queue_head_t 
* event)
 /*
  * forward references
  */
-static int diLog(struct jfs_log * log, struct tblock * tblk, struct lrd * lrd,
-   struct tlock * tlck, struct commit * cd);
-static int dataLog(struct jfs_log * log, struct tblock * tblk, struct lrd * 
lrd,
-   struct tlock * tlck);
+static void diLog(struct jfs_log *log, struct tblock *tblk, struct lrd *lrd,
+   struct tlock *tlck, struct commit *cd);
+static void dataLog(struct jfs_log *log, struct tblock *tblk, struct lrd *lrd,
+   struct tlock *tlck);
 static void dtLog(struct jfs_log * log, struct tblock * tblk, struct lrd * lrd,
struct tlock * tlck);
 static void mapLog(struct jfs_log * log, struct tblock * tblk, struct lrd * 
lrd,
@@ -159,8 +159,8 @@ static void mapLog(struct jfs_log * log, struct tblock * 
tblk, struct lrd * lrd,
 static void txAllocPMap(struct inode *ip, struct maplock * maplock,
struct tblock * tblk);
 static void txForce(struct tblock * tblk);
-static int txLog(struct jfs_log * log, struct tblock * tblk,
-   struct commit * cd);
+static void txLog(struct jfs_log *log, struct tblock *tblk,
+   struct commit *cd);
 static void txUpdateMap(struct tblock * tblk);
 static void txRelease(struct tblock * tblk);
 static void xtLog(struct jfs_log * log, struct tblock * tblk, struct lrd * lrd,
@@ -1365,9 +1365,8 @@ int txCommit(tid_t tid,   /* transaction 
identifier */
  *
  * RETURN :
  */
-static int txLog(struct jfs_log * log, struct tblock * tblk, struct commit * 
cd)
+static void txLog(struct jfs_log *log, struct tblock *tblk, struct commit *cd)
 {
-   int rc = 0;
struct inode *ip;
lid_t lid;
struct tlock *tlck;
@@ -1414,7 +1413,7 @@ static int txLog(struct jfs_log * log, struct tblock * 
tblk, struct commit * cd)
}
}
 
-   return rc;
+   return;
 }
 
 /*
@@ -1422,10 +1421,9 @@ static int txLog(struct jfs_log * log, struct tblock * 
tblk, struct commit * cd)
  *
  * function:   log inode tlock and format maplock to update bmap;
  */
-static int diLog(struct jfs_log * log, struct tblock * tblk, struct lrd * lrd,
-struct tlock * tlck, struct commit * cd)
+static void diLog(struct jfs_log *log, struct tblock *tblk, struct lrd *lrd,
+struct tlock *tlck, struct commit *cd)
 {
-   int rc = 0;
struct metapage *mp;
pxd_t *pxd;
struct pxd_lock *pxdlock;
@@ -1527,7 +1525,7 @@ static int diLog(struct jfs_log * log, struct tblock * 
tblk, struct lrd * lrd,
}
 #endif /* _JFS_WIP */
 
-   return rc;
+   return;
 }
 
 /*
@@ -1535,8 +1533,8 @@ static int diLog(struct jfs_log * log, struct tblock * 
tblk, struct lrd * lrd,
  *
  * function:   log data tlock
  */
-static int dataLog(struct jfs_log * log, struct tblock * tblk, struct lrd * 
lrd,
-   struct tlock * tlck)
+static void dataLog(struct jfs_log *log, struct tblock *tblk, struct lrd *lrd,
+   struct tlock *tlck)
 {
struct metapage *mp;
pxd_t *pxd;
@@ -1562,7 +1560,7 @@ static int dataLog(struct jfs_log * log, struct tblock * 
tblk, struct lrd * lrd,
metapage_homeok(mp);
discard_metapage(mp);
tlck->mp = NULL;
-   return 0;
+   return;
}
 
PXDaddress(pxd, mp->index);
@@ -1573,7 +1571,7 @@ static int dataLog(struct jfs_log * log, struct tblock * 
tblk, struct lrd * lrd,
/* mark page as homeward bound */
tlck->flag |= tlckWRITEPAGE;
 
-   return 0;
+   return;
 }
 
 /*
-- 
1.8.3.1

Re: [PATCH] staging: gasket: Align code to match with open parenthesis and fix the lines ending with open parenthesis

[Greg KH]

On Sun, Feb 07, 2021 at 01:11:36PM +0530, Mahak gupta wrote:
> This patch fixes warnings of checkpatch.pl. According to the coding style
> of linux, code should be aligned properly to match with open parenthesis
> and lines should not end with open parenthesis.
> 
> Signed-off-by: mhk19 
> ---
>  drivers/staging/gasket/gasket_ioctl.c | 18 --
>  1 file changed, 8 insertions(+), 10 deletions(-)
> 
> diff --git a/drivers/staging/gasket/gasket_ioctl.c
> b/drivers/staging/gasket/gasket_ioctl.c
> index e3047d36d8db..a966231bad42 100644
> --- a/drivers/staging/gasket/gasket_ioctl.c
> +++ b/drivers/staging/gasket/gasket_ioctl.c
> @@ -40,7 +40,7 @@ static int gasket_set_event_fd(struct gasket_dev
> *gasket_dev,
> 
>  /* Read the size of the page table. */
>  static int gasket_read_page_table_size(struct gasket_dev *gasket_dev,
> -   struct gasket_page_table_ioctl __user *argp)
> +  struct gasket_page_table_ioctl
> __user *argp)
>  {
> int ret = 0;
> struct gasket_page_table_ioctl ibuf;
> @@ -51,8 +51,7 @@ static int gasket_read_page_table_size(struct gasket_dev
> *gasket_dev,
> if (ibuf.page_table_index >= gasket_dev->num_page_tables)
> return -EFAULT;
> 
> -   ibuf.size = gasket_page_table_num_entries(
> -   gasket_dev->page_table[ibuf.page_table_index]);
> +   ibuf.size =
> gasket_page_table_num_entries(gasket_dev->page_table[ibuf.page_table_index]);
> 
> trace_gasket_ioctl_page_table_data(ibuf.page_table_index, ibuf.size,
>ibuf.host_address,
> @@ -66,7 +65,7 @@ static int gasket_read_page_table_size(struct gasket_dev
> *gasket_dev,
> 
>  /* Read the size of the simple page table. */
>  static int gasket_read_simple_page_table_size(struct gasket_dev
> *gasket_dev,
> -   struct gasket_page_table_ioctl __user *argp)
> + struct
> gasket_page_table_ioctl __user *argp)
>  {
> int ret = 0;
> struct gasket_page_table_ioctl ibuf;
> @@ -92,7 +91,7 @@ static int gasket_read_simple_page_table_size(struct
> gasket_dev *gasket_dev,
> 
>  /* Set the boundary between the simple and extended page tables. */
>  static int gasket_partition_page_table(struct gasket_dev *gasket_dev,
> -   struct gasket_page_table_ioctl __user *argp)
> +  struct gasket_page_table_ioctl
> __user *argp)
>  {
> int ret;
> struct gasket_page_table_ioctl ibuf;
> @@ -107,8 +106,8 @@ static int gasket_partition_page_table(struct
> gasket_dev *gasket_dev,
> 
> if (ibuf.page_table_index >= gasket_dev->num_page_tables)
> return -EFAULT;
> -   max_page_table_size = gasket_page_table_max_size(
> -   gasket_dev->page_table[ibuf.page_table_index]);
> +   max_page_table_size = gasket_page_table_max_size
> +   (gasket_dev->page_table[ibuf.page_table_index]);
> 
> if (ibuf.size > max_page_table_size) {
> dev_dbg(gasket_dev->dev,
> @@ -119,8 +118,7 @@ static int gasket_partition_page_table(struct
> gasket_dev *gasket_dev,
> 
> mutex_lock(&gasket_dev->mutex);
> 
> -   ret = gasket_page_table_partition(
> -   gasket_dev->page_table[ibuf.page_table_index], ibuf.size);
> +   ret =
> gasket_page_table_partition(gasket_dev->page_table[ibuf.page_table_index],
> ibuf.size);
> mutex_unlock(&gasket_dev->mutex);
> 
> return ret;
> @@ -183,7 +181,7 @@ static int gasket_unmap_buffers(struct gasket_dev
> *gasket_dev,
>   * corresponding memory.
>   */
>  static int gasket_config_coherent_allocator(struct gasket_dev *gasket_dev,
> -   struct gasket_coherent_alloc_config_ioctl __user *argp)
> +   struct
> gasket_coherent_alloc_config_ioctl __user *argp)
>  {
> int ret;
> struct gasket_coherent_alloc_config_ioctl ibuf;
> --
> 2.17.1

Hi,

This is the friendly patch-bot of Greg Kroah-Hartman.  You have sent him
a patch that has triggered this response.  He used to manually respond
to these common problems, but in order to save his sanity (he kept
writing the same thing over and over, yet to different people), I was
created.  Hopefully you will not take offence and will fix the problem
in your patch and resubmit it so that it can be accepted into the Linux
kernel tree.

You are receiving this message because of the following common error(s)
as indicated below:

- Your patch is malformed (tabs converted to spaces, linewrapped, etc.)
  and can not be applied.  Please read the file,
  Documentation/email-clients.txt in order to fix this.

- You sent multiple patches, yet no indication of which ones should be
  applied in which order.  Greg could just guess, but if you are
  receiving this email, he guessed wrong and the patches didn't apply.
  Please read the section entitled "The canonical patch format" in the
  kernel file, 

Re: [PATCH 10/18] arm64: Introduce FIQ support

[Hector Martin 'marcan']

On 07/02/2021 01.22, Arnd Bergmann wrote:

* In the fiq handler code, check if normal interrupts were enabled
   when the fiq hit. Normally they are enabled, so just proceed to
   handle the timer and ipi directly

* if irq was disabled, defer the handling by doing a self-ipi
   through the aic's ipi method, and handle it from there
   when dealing with the next interrupt once interrupts get
   enabled.

This would be similar to the soft-disable feature on powerpc, which
never actually turns off interrupts from regular kernel code but
just checks a flag in local_irq_enable that gets set when a
hardirq happened.


Case #2 seems messy. In AIC, we'd have to either:

* Disable FIQs, and hope that doesn't confuse any save/restore code 
going on, then set a flag and check it in *both* the IRQ and FIQ path 
since either might trigger depending on what happens next, or
* Mask the relevant timer, which we'd then need to make sure does not 
confuse the timer code (Unmask it again when we fire the interrupt? But 
what if the timer code intended to mask it in the interim?)


Neither sounds particularly clean to me... if we had FIQ status masking 
registers this would be more reasonable, but I'm not sure I'd want the 
AIC driver to mess with neither DAIF nor the timer registers. It's bad 
enough that it has to read the latter already (and I hope I can find a 
better way of doing that...).


Plus I don't know if the vector entry code and other scaffolding between 
the vector and the AIC driver would be happy with, effectively, 
recursive interrupts. This could work with a carefully controlled path 
to make sure it doesn't break things, but I'm not so sure about the 
current "just point FIQ and IRQ to the same place" approach here.


--
Hector Martin "marcan" (mar...@marcan.st)
Public Key: https://mrcn.st/pub

[PATCH v2] staging: emxx_udc: Make incorrectly defined global static

[Kumar Kartikeya Dwivedi]

The global gpio_desc pointer and int vbus_irq were defined in the header,
instead put the definitions in the translation unit and make them static as
there's only a single consumer, and these symbols shouldn't pollute the
global namespace.

This fixes the following sparse warnings for this driver:
drivers/staging/emxx_udc/emxx_udc.c: note: in included file:
drivers/staging/emxx_udc/emxx_udc.h:23:18: warning: symbol 'vbus_gpio' was not
declared. Should it be static?  drivers/staging/emxx_udc/emxx_udc.h:24:5:
warning: symbol 'vbus_irq' was not declared. Should it be static?

Signed-off-by: Kumar Kartikeya Dwivedi 
---
 drivers/staging/emxx_udc/emxx_udc.c | 3 +++
 drivers/staging/emxx_udc/emxx_udc.h | 2 --
 2 files changed, 3 insertions(+), 2 deletions(-)

diff --git a/drivers/staging/emxx_udc/emxx_udc.c 
b/drivers/staging/emxx_udc/emxx_udc.c
index a30b4f5b1..3536c03ff 100644
--- a/drivers/staging/emxx_udc/emxx_udc.c
+++ b/drivers/staging/emxx_udc/emxx_udc.c
@@ -34,6 +34,9 @@
 #defineDRIVER_DESC "EMXX UDC driver"
 #defineDMA_ADDR_INVALID(~(dma_addr_t)0)
 
+static struct gpio_desc *vbus_gpio;
+static int vbus_irq;
+
 static const char  driver_name[] = "emxx_udc";
 static const char  driver_desc[] = DRIVER_DESC;
 
diff --git a/drivers/staging/emxx_udc/emxx_udc.h 
b/drivers/staging/emxx_udc/emxx_udc.h
index bca614d69..c9e37a1b8 100644
--- a/drivers/staging/emxx_udc/emxx_udc.h
+++ b/drivers/staging/emxx_udc/emxx_udc.h
@@ -20,8 +20,6 @@
 /* below hacked up for staging integration */
 #define GPIO_VBUS 0 /* GPIO_P153 on KZM9D */
 #define INT_VBUS 0 /* IRQ for GPIO_P153 */
-struct gpio_desc *vbus_gpio;
-int vbus_irq;
 
 /* Board dependence(Wait) */
 
-- 
2.29.2

Re: [PATCH 10/18] arm64: Introduce FIQ support

[Hector Martin 'marcan']

On 07/02/2021 00.37, Marc Zyngier wrote:

See my digression in patch 8. I really wonder what the benefit is to
treat FIQ independently of IRQ, and we might as well generalise
this. We could always panic on getting a FIQ on platforms that don't
expect one.

It'd be good to rope in the other interested parties (Mark for the
early entry code, James for RAS and SError handling).


CCing Mark and James: TL;DR what do you think about unconditionally 
keeping DAIF.I == DAIF.F, would this break other platforms with spurious 
FIQs or conversely mask FIQs when we don't want to in some cases? The 
FIQ vector would remain a panic except on platforms that require using 
it, via an alternatives patch.



kernel_ventry   1, sync // Synchronous EL1h
kernel_ventry   1, irq  // IRQ EL1h
-   kernel_ventry   1, fiq_invalid  // FIQ EL1h
+   // FIQ EL1h
+   kernel_ventry   1, fiq_invalid, 64, irq, ARM64_NEEDS_FIQ


It could be better to create a set of first class FIQ handlers rather
than this alternative target macro. I quickly hacked this instead,
which I find more readable.


I think I ended up with the macro change to keep it 1:1 with IRQ, vs a 
separate branch... but I didn't think of the fallthrough-with-nop trick, 
neat. It is definitely is more readable. Are you OK with me pulling this 
patch in for v2, with your name on it?



-   kernel_ventry   0, fiq_invalid_compat, 32   // FIQ 32-bit EL0
+   kernel_ventry   0, fiq, 32  // FIQ 32-bit EL0


fiq_compat here, right?

--
Hector Martin "marcan" (mar...@marcan.st)
Public Key: https://mrcn.st/pub

Re: [PATCH] ALSA: pci: Assign boolean values to a bool variable

[Takashi Iwai]

On Sun, 07 Feb 2021 08:02:41 +0100,
Jiapeng Chong wrote:
> 
> Fix the following coccicheck warnings:
> 
> ./sound/pci/azt3328.c:2451:2-16: WARNING: Assignment of 0/1 to bool
> variable.
> 
> Reported-by: Abaci Robot 
> Signed-off-by: Jiapeng Chong 

Thanks, applied.


Takashi

[PATCH] drm/amd/pm: Remove unnecessary conversion to bool

[Jiapeng Chong]

Fix the following coccicheck warning:

./drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c:907:47-52:
WARNING: conversion to bool not needed here.

Reported-by: Abaci Robot
Signed-off-by: Jiapeng Chong 
---
 drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c 
b/drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c
index d68d3df..b364862 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c
+++ b/drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c
@@ -904,7 +904,7 @@ static bool 
sienna_cichlid_is_support_fine_grained_dpm(struct smu_context *smu,
dpm_desc = &pptable->DpmDescriptor[clk_index];
 
/* 0 - Fine grained DPM, 1 - Discrete DPM */
-   return dpm_desc->SnapToDiscrete == 0 ? true : false;
+   return dpm_desc->SnapToDiscrete != 0;
 }
 
 static int sienna_cichlid_print_clk_levels(struct smu_context *smu,
-- 
1.8.3.1

Re: [PATCH v2] staging: emxx_udc: Make incorrectly defined global static

[Greg KH]

On Sun, Feb 07, 2021 at 02:16:58PM +0530, Kumar Kartikeya Dwivedi wrote:
> The global gpio_desc pointer and int vbus_irq were defined in the header,
> instead put the definitions in the translation unit and make them static as
> there's only a single consumer, and these symbols shouldn't pollute the
> global namespace.
> 
> This fixes the following sparse warnings for this driver:
> drivers/staging/emxx_udc/emxx_udc.c: note: in included file:
> drivers/staging/emxx_udc/emxx_udc.h:23:18: warning: symbol 'vbus_gpio' was not
> declared. Should it be static?  drivers/staging/emxx_udc/emxx_udc.h:24:5:
> warning: symbol 'vbus_irq' was not declared. Should it be static?
> 
> Signed-off-by: Kumar Kartikeya Dwivedi 
> ---
>  drivers/staging/emxx_udc/emxx_udc.c | 3 +++
>  drivers/staging/emxx_udc/emxx_udc.h | 2 --
>  2 files changed, 3 insertions(+), 2 deletions(-)

Hi,

This is the friendly patch-bot of Greg Kroah-Hartman.  You have sent him
a patch that has triggered this response.  He used to manually respond
to these common problems, but in order to save his sanity (he kept
writing the same thing over and over, yet to different people), I was
created.  Hopefully you will not take offence and will fix the problem
in your patch and resubmit it so that it can be accepted into the Linux
kernel tree.

You are receiving this message because of the following common error(s)
as indicated below:

- This looks like a new version of a previously submitted patch, but you
  did not list below the --- line any changes from the previous version.
  Please read the section entitled "The canonical patch format" in the
  kernel file, Documentation/SubmittingPatches for what needs to be done
  here to properly describe this.

If you wish to discuss this problem further, or you have questions about
how to resolve this issue, please feel free to respond to this email and
Greg will reply once he has dug out from the pending patches received
from other developers.

thanks,

greg k-h's patch email bot

Re: [PATCH] m68k: Drop -fno-strength-reduce from KBUILD_CFLAGS

[John Paul Adrian Glaubitz]

On 2/7/21 8:02 AM, Finn Thain wrote:
> References: commit 565bae6a4a8f ("[SCSI] 53c7xx: kill driver")

Does that mean there is currently no driver for the A4091?

Adrian

-- 
 .''`.  John Paul Adrian Glaubitz
: :' :  Debian Developer - glaub...@debian.org
`. `'   Freie Universitaet Berlin - glaub...@physik.fu-berlin.de
  `-GPG: 62FF 8A75 84E0 2956 9546  0006 7426 3B37 F5B5 F913

[PATCH] MIPS: process: Fix no previous prototype warning

[Jinyang He]

unwind_stack_by_address and unwind_stack need .
arch_align_stack needs 

link: 
https://lists.01.org/hyperkitty/list/kbuild-...@lists.01.org/thread/ZPL2RRA6RZKRQZI5IGOVLFXN2GVZBN3L/
Fixes: ("MIPS: process: Remove unnecessary headers inclusion")
Reported-by: kernel test robot 
Signed-off-by: Jinyang He 
---
 arch/mips/kernel/process.c | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/arch/mips/kernel/process.c b/arch/mips/kernel/process.c
index 0c5bc06..2e591df 100644
--- a/arch/mips/kernel/process.c
+++ b/arch/mips/kernel/process.c
@@ -26,6 +26,7 @@
 #include 
 #include 
 #include 
+#include 
 #include 
 #include 
 #include 
@@ -36,6 +37,7 @@
 #include 
 #include 
 #include 
+#include 
 
 #ifdef CONFIG_HOTPLUG_CPU
 void arch_cpu_idle_dead(void)
-- 
2.1.0

[PATCH] gpiolib: cdev: convert stream-like files from

[Yang Li]

Eliminate the following coccicheck warning:
./drivers/gpio/gpiolib-cdev.c:2307:7-23: WARNING: gpio_fileops: .read()
has stream semantic; safe to change nonseekable_open -> stream_open.

Reported-by: Abaci Robot 
Signed-off-by: Yang Li 
---
 drivers/gpio/gpiolib-cdev.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpio/gpiolib-cdev.c b/drivers/gpio/gpiolib-cdev.c
index 1631727..bad68ef 100644
--- a/drivers/gpio/gpiolib-cdev.c
+++ b/drivers/gpio/gpiolib-cdev.c
@@ -2304,7 +2304,7 @@ static int gpio_chrdev_open(struct inode *inode, struct 
file *file)
get_device(&gdev->dev);
file->private_data = cdev;
 
-   ret = nonseekable_open(inode, file);
+   ret = stream_open(inode, file);
if (ret)
goto out_unregister_notifier;
 
-- 
1.8.3.1

Re: [PATCH v5 1/2] dt-bindings: hwlock: add sun6i_hwspinlock

[Wilken Gottwalt]

On Wed, 23 Dec 2020 15:49:19 -0700
Rob Herring  wrote:

> On Wed, Dec 23, 2020 at 4:34 AM Wilken Gottwalt
>  wrote:
> >
> > Adds documentation on how to use the sun6i_hwspinlock driver for sun6i
> > compatible SoCs.
> 
> Please resend to DT list so that automated checks run and it's in my
> queue (PW). You need to run 'make dt_binding_check' as there are
> several issues.

Mentioning somewhere, that yamllint is required would have helped here a lot.
Without it I always ended up with that, what was quite misleading:

ERROR: dtschema minimum version is v2020.8.1
make[1]: *** [Documentation/devicetree/bindings/Makefile:12: 
check_dtschema_version] Error 1
make: *** [Makefile:1370: dt_binding_check] Error 2

> > Signed-off-by: Wilken Gottwalt 
> > ---
> > Changes in v5:
> >   - changed binding to earliest known supported SoC sun6i-a31
> >   - dropped unnecessary entries
> >
> > Changes in v4:
> >   - changed binding to sun8i-a33-hwpinlock
> >   - added changes suggested by Maxime Ripard
> >
> > Changes in v3:
> >   - changed symbols from sunxi to sun8i
> >
> > Changes in v2:
> >   - fixed memory ranges
> > ---
> >  .../bindings/hwlock/sun6i-a31-hwspinlock.yaml | 44 +++
> >  1 file changed, 44 insertions(+)
> >  create mode 100644 
> > Documentation/devicetree/bindings/hwlock/sun6i-a31-hwspinlock.yaml
> >
> > diff --git 
> > a/Documentation/devicetree/bindings/hwlock/sun6i-a31-hwspinlock.yaml
> > b/Documentation/devicetree/bindings/hwlock/sun6i-a31-hwspinlock.yaml new 
> > file mode 100644
> > index ..481c5c995ad7
> > --- /dev/null
> > +++ b/Documentation/devicetree/bindings/hwlock/sun6i-a31-hwspinlock.yaml
> > @@ -0,0 +1,44 @@
> > +# SPDX-License-Identifier: (GPL-2.0-only or BSD-2-Clause)
> > +%YAML 1.2
> > +---
> > +$id: http://devicetree.org/schemas/hwlock/sun6i-hwspinlock.yaml#
> 
> This will fail checks. Wrong filename.
> 
> > +$schema: http://devicetree.org/meta-schemas/core.yaml#
> > +
> > +title: SUN6I hardware spinlock driver for Allwinner sun6i compatible SoCs
> > +
> > +maintainers:
> > +  - Wilken Gottwalt 
> > +
> > +description:
> > +  The hardware unit provides semaphores between the ARM cores and the 
> > embedded
> > +  companion core on the SoC.
> > +
> > +properties:
> > +  compatible:
> > +const: allwinner,sun6i-a31-hwspinlock
> > +
> > +reg:
> > +  maxItems: 1
> > +
> > +clocks:
> > +  maxItems: 1
> > +
> > +resets:
> > +  maxItems: 1
> > +
> > +required:
> > +  - compatible
> > +  - reg
> > +  - clocks
> > +  - resets
> > +
> > +additionalProperties: false
> > +
> > +examples:
> > +  - |
> > +hwspinlock@1c18000 {
> 
> hwlock@...

sprd, stm32 and omap using hwspinlock. Why is it okay there and not okay in
my version?

> > +  compatible = "allwinner,sun6i-a31-hwspinlock";
> > +  reg = <0x01c18000 0x1000>;
> > +  clocks = <&ccu CLK_BUS_SPINLOCK>;
> > +  resets = <&ccu RST_BUS_SPINLOCK>;
> 
> You need an include for these defines.

So I guess it is needed because I the clocks/resets are used, right? But why
is it not the case for the sprd example, which also uses clocks?

> > +};
> > --
> > 2.29.2
> >

[PATCH] platform/chrome: wilco_ec: convert stream-like files from nonseekable_open -> stream_open

[Yang Li]

Eliminate the following coccicheck warning:
./drivers/platform/chrome/wilco_ec/telemetry.c:259:1-17: WARNING:
telem_fops: .read() and .write() have stream semantic; safe to change
nonseekable_open -> stream_open.

Reported-by: Abaci Robot 
Signed-off-by: Yang Li 
---
 drivers/platform/chrome/wilco_ec/telemetry.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/platform/chrome/wilco_ec/telemetry.c 
b/drivers/platform/chrome/wilco_ec/telemetry.c
index e06d96f..60da7a2 100644
--- a/drivers/platform/chrome/wilco_ec/telemetry.c
+++ b/drivers/platform/chrome/wilco_ec/telemetry.c
@@ -256,7 +256,7 @@ static int telem_open(struct inode *inode, struct file 
*filp)
sess_data->dev_data = dev_data;
sess_data->has_msg = false;
 
-   nonseekable_open(inode, filp);
+   stream_open(inode, filp);
filp->private_data = sess_data;
 
return 0;
-- 
1.8.3.1

[PATCH v3] staging: emxx_udc: Make incorrectly defined global static

[Kumar Kartikeya Dwivedi]

The global gpio_desc pointer and int vbus_irq were defined in the header,
instead put the definitions in the translation unit and make them static as
there's only a single consumer, and these symbols shouldn't pollute the
global namespace.

This fixes the following sparse warnings for this driver:
drivers/staging/emxx_udc/emxx_udc.c: note: in included file:
drivers/staging/emxx_udc/emxx_udc.h:23:18: warning: symbol 'vbus_gpio' was not
declared. Should it be static?  drivers/staging/emxx_udc/emxx_udc.h:24:5:
warning: symbol 'vbus_irq' was not declared. Should it be static?

Signed-off-by: Kumar Kartikeya Dwivedi 
---
Changes in v1:
Switch to variable with static linkage instead of extern
Changes in v2:
Resend a versioned patch
Changes in v3:
Include version changelog below the marker
---
 drivers/staging/emxx_udc/emxx_udc.c | 3 +++
 drivers/staging/emxx_udc/emxx_udc.h | 2 --
 2 files changed, 3 insertions(+), 2 deletions(-)

diff --git a/drivers/staging/emxx_udc/emxx_udc.c 
b/drivers/staging/emxx_udc/emxx_udc.c
index a30b4f5b1..3536c03ff 100644
--- a/drivers/staging/emxx_udc/emxx_udc.c
+++ b/drivers/staging/emxx_udc/emxx_udc.c
@@ -34,6 +34,9 @@
 #defineDRIVER_DESC "EMXX UDC driver"
 #defineDMA_ADDR_INVALID(~(dma_addr_t)0)
 
+static struct gpio_desc *vbus_gpio;
+static int vbus_irq;
+
 static const char  driver_name[] = "emxx_udc";
 static const char  driver_desc[] = DRIVER_DESC;
 
diff --git a/drivers/staging/emxx_udc/emxx_udc.h 
b/drivers/staging/emxx_udc/emxx_udc.h
index bca614d69..c9e37a1b8 100644
--- a/drivers/staging/emxx_udc/emxx_udc.h
+++ b/drivers/staging/emxx_udc/emxx_udc.h
@@ -20,8 +20,6 @@
 /* below hacked up for staging integration */
 #define GPIO_VBUS 0 /* GPIO_P153 on KZM9D */
 #define INT_VBUS 0 /* IRQ for GPIO_P153 */
-struct gpio_desc *vbus_gpio;
-int vbus_irq;
 
 /* Board dependence(Wait) */
 
-- 
2.29.2

Re: [PATCH v2 4/4] hugetlb: Do early cow when page pinned on src mm

[Gal Pressman]

On 05/02/2021 17:51, Peter Xu wrote:
> On Fri, Feb 05, 2021 at 02:58:33PM +, Zhang, Wei wrote:
>> Hi Peter,
> 
> Hi, Wei,
> 
>>
>> Gal and I worked together. We tested the patch v2 and can confirm it is 
>> working as intended.
>>
>> Thank you very much for your quick response!
> 
> My thanks too on the quick testing!  Sorry that I'll need to post v3; please
> feel free to hold off the testing until I got some r-bs with the new version.

BTW, it might already be fixed in v3, but I encountered a compilation warning
with this series:

mm/memory.c: In function ‘copy_present_page’:
mm/memory.c:800:20: warning: unused variable ‘src_mm’ [-Wunused-variable]
  struct mm_struct *src_mm = src_vma->vm_mm;
^~

[PATCH] drm: bridge: convert sysfs sprintf/snprintf family to sysfs_emit

[Jiapeng Chong]

Fix the following coccicheck warning:

drivers/gpu/drm/bridge/lontium-lt9611uxc.c:858:8-16: WARNING: use
scnprintf or sprintf.

Reported-by: Abaci Robot
Signed-off-by: Jiapeng Chong 
---
 drivers/gpu/drm/bridge/lontium-lt9611uxc.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/bridge/lontium-lt9611uxc.c 
b/drivers/gpu/drm/bridge/lontium-lt9611uxc.c
index fee2795..3cac16d 100644
--- a/drivers/gpu/drm/bridge/lontium-lt9611uxc.c
+++ b/drivers/gpu/drm/bridge/lontium-lt9611uxc.c
@@ -855,7 +855,7 @@ static ssize_t lt9611uxc_firmware_show(struct device *dev, 
struct device_attribu
 {
struct lt9611uxc *lt9611uxc = dev_get_drvdata(dev);
 
-   return snprintf(buf, PAGE_SIZE, "%02x\n", lt9611uxc->fw_version);
+   return sysfs_emit(buf, "%02x\n", lt9611uxc->fw_version);
 }
 
 static DEVICE_ATTR_RW(lt9611uxc_firmware);
-- 
1.8.3.1

Re: [PATCH 05/18] tty: serial: samsung_tty: add support for Apple UARTs

[Hector Martin 'marcan']

On 06/02/2021 22.15, Marc Zyngier wrote:

-static int s3c24xx_serial_has_interrupt_mask(struct uart_port *port)
+static int s3c24xx_irq_type(struct uart_port *port)
  {
-   return to_ourport(port)->info->type == PORT_S3C6400;
+   switch (to_ourport(port)->info->type) {
+   case PORT_S3C6400:
+   return IRQ_S3C6400;
+   case PORT_APPLE:
+   return IRQ_APPLE;
+   default:
+   return IRQ_DISCRETE;
+   }
+


nit: For ease of reviewing, it'd be good if you could split this patch
with introducing the S3C6400 and "discrete" support initially, and
only then add the new stuff.


Good idea, will do for v2.


+   if (s3c24xx_irq_type(port) == IRQ_APPLE)
+   s3c24xx_serial_tx_chars(NO_IRQ, ourport);


Instead of directly calling into the handler (which has its own
problems, see below), could you just tickle the interrupt status
register to make an interrupt pending and trigger an actual interrupt?
I have no idea whether the HW supports this kind of trick though.


I thought of that, but I tried really hard to find such a feature with 
no success. The best I can do is unmask and trigger the *RX* timeout 
interrupt which will eventually fire but... this doesn't work so well in 
practice. There is no way to trigger IRQ flags directly (as those bits 
are write-1-to-clear).



-   spin_lock_irqsave(&port->lock, flags);
+   /* Only lock if called from IRQ context */
+   if (irq != NO_IRQ)
+   spin_lock_irqsave(&port->lock, flags);


Isn't that actually dangerous? What prevents the interrupt from firing
right in the middle of this sequence and create havoc when called from
enable_tx_pio()? I fail to see what you gain with sidestepping the
locking.


The callpath here is:

uart_start -> __uart_start -> (uart_ops.start_tx) 
s3c24xx_serial_start_tx -> s3c24xx_serial_start_tx_pio -> enable_tx_pio 
-> s3c24xx_serial_tx_chars


And uart_start takes the uart_port lock. None of the serial functions 
take the lock because the serial core already does, but obviously the 
IRQ handler needs to, *if* it's called as an IRQ handler only.



The default should be IRQ_NONE, otherwise the kernel cannot detect a
screaming spurious interrupt.


Good point, and this needs fixing in s3c64xx_serial_handle_irq too then 
(which is what I based mine off of).



+   ret = request_irq(port->irq, apple_serial_handle_irq, IRQF_SHARED,
+ s3c24xx_serial_portname(port), ourport);


Why IRQF_SHARED? Do you expect any other device sharing the same line
with this UART?


This also came from s3c64xx_serial_startup and... now I wonder why that 
one needs it. Maybe on some SoCs it does get shared? Certainly not for 
discrete rx/tx irq chips (and indeed those don't set the flag)...


CCing Thomas, who added the S3C64xx support (and should probably review 
this patch); is there a reason for IRQF_SHARED there? NB: v1 breaks the 
build on arm or with CONFIG_PM_SLEEP, those will be fixed for v2.


Either way, certainly not for Apple SoCs; I'll get rid of IRQF_SHARED 
for v2.



diff --git a/include/uapi/linux/serial_core.h b/include/uapi/linux/serial_core.h
index 62c22045fe65..59d102b674db 100644
--- a/include/uapi/linux/serial_core.h
+++ b/include/uapi/linux/serial_core.h
@@ -277,4 +277,7 @@
  /* Freescale LINFlexD UART */
  #define PORT_LINFLEXUART  122
  
+/* Apple Silicon (M1/T8103) UART (Samsung variant) */

+#define PORT_APPLE 123
+


Do you actually need a new port type here? Looking at the driver
itself, it is mainly used to work out the IRQ model. Maybe introducing
a new irq_type field in the port structure would be better than
exposing this to userspace (which should see something that is exactly
the same as a S3C UART).


Well... every S3C variant already has its own port type here.

#define PORT_S3C241055
#define PORT_S3C244061
#define PORT_S3C240067
#define PORT_S3C241273
#define PORT_S3C640084

If we don't introduce a new one, which one should we pretend to be? :)

I agree that it might make sense to merge all of these into one, though; 
I don't know what the original reason for splitting them out is. But now 
that they're part of the userspace API, this might not be a good idea. 
Though, unsurprisingly, some googling suggests there are zero users of 
these defines in userspace.


--
Hector Martin "marcan" (mar...@marcan.st)
Public Key: https://mrcn.st/pub

Re: [PATCH v3] staging: emxx_udc: Make incorrectly defined global static

[Greg KH]

On Sun, Feb 07, 2021 at 02:29:12PM +0530, Kumar Kartikeya Dwivedi wrote:
> The global gpio_desc pointer and int vbus_irq were defined in the header,
> instead put the definitions in the translation unit and make them static as
> there's only a single consumer, and these symbols shouldn't pollute the
> global namespace.
> 
> This fixes the following sparse warnings for this driver:
> drivers/staging/emxx_udc/emxx_udc.c: note: in included file:
> drivers/staging/emxx_udc/emxx_udc.h:23:18: warning: symbol 'vbus_gpio' was not
> declared. Should it be static?  drivers/staging/emxx_udc/emxx_udc.h:24:5:
> warning: symbol 'vbus_irq' was not declared. Should it be static?
> 
> Signed-off-by: Kumar Kartikeya Dwivedi 
> ---
> Changes in v1:
> Switch to variable with static linkage instead of extern
> Changes in v2:
> Resend a versioned patch
> Changes in v3:
> Include version changelog below the marker

Much better, thanks, now queued up.

greg k-h

Re: [PATCH] mips: kernel: setup: fix crash kernel resource allocation

[Mike Rapoport]

On Sat, Feb 06, 2021 at 12:59:40PM +, Ivan Khoronzhuk wrote:
> In order to avoid crash kernel corruption, its memory is reserved
> early in memblock and as result, in time when resources are inited
> it's not present in memblock.memory, so crash kernel memory is out
> of ranges listed with for_each_mem_range(). To avoid it and still
> keep memory reserved lets reseve it out of loop by inserting it in
> iomem_resource.

Unless I misread the code, the crash kernel memory is actually allocated
from memblock (memblock_find_in_range + memblock_reserve), but for some
reason memblock_reserve() is called outside
mips_parse_crashkernel(). So the crash kernel memory is surely in both
memblock.memory and memblock.reserved and it will be covered by
for_each_mem_range().

The mips_parse_crashkernel() function and the following reservation of
crash kernel memory should be merged, IMO, and this can be further
simplified with memblock_alloc() helpers.

Is there a particular issue you are trying to fix?
 
> Fixes: a94e4f24ec83 ("MIPS: init: Drop boot_mem_map")
> Signed-off-by: Ivan Khoronzhuk 
> ---
> Based on linux-next/master
> 
>  arch/mips/kernel/setup.c | 8 +---
>  1 file changed, 5 insertions(+), 3 deletions(-)
> 
> diff --git a/arch/mips/kernel/setup.c b/arch/mips/kernel/setup.c
> index 3785c72bc3bc..25e376ef2f2a 100644
> --- a/arch/mips/kernel/setup.c
> +++ b/arch/mips/kernel/setup.c
> @@ -473,14 +473,15 @@ static void __init mips_parse_crashkernel(void)
>   crashk_res.end   = crash_base + crash_size - 1;
>  }
>  
> -static void __init request_crashkernel(struct resource *res)
> +static void __init request_crashkernel(void)
>  {
>   int ret;
>  
>   if (crashk_res.start == crashk_res.end)
>   return;
>  
> - ret = request_resource(res, &crashk_res);
> + /* The crashk resource shoud be located in normal mem */
> + ret = insert_resource(&iomem_resource, &crashk_res);
>   if (!ret)
>   pr_info("Reserving %ldMB of memory at %ldMB for crashkernel\n",
>   (unsigned long)(resource_size(&crashk_res) >> 20),
> @@ -734,8 +735,9 @@ static void __init resource_init(void)
>   request_resource(res, &code_resource);
>   request_resource(res, &data_resource);
>   request_resource(res, &bss_resource);
> - request_crashkernel(res);
>   }
> +
> + request_crashkernel();
>  }
>  
>  #ifdef CONFIG_SMP
> -- 
> 2.23.1
> 

-- 
Sincerely yours,
Mike.

Re: [PATCH 5.10 04/57] net: octeontx2: Make sure the buffer is 128 byte aligned

[Pavel Machek]

Hi!

> commit db2805150a0f27c00ad286a29109397a7723adad upstream.
> 
> The octeontx2 hardware needs the buffer to be 128 byte aligned.
> But in the current implementation of napi_alloc_frag(), it can't
> guarantee the return address is 128 byte aligned even the request size
> is a multiple of 128 bytes, so we have to request an extra 128 bytes and
> use the PTR_ALIGN() to make sure that the buffer is aligned correctly.
> 
> +++ b/drivers/net/ethernet/marvell/octeontx2/nic/otx2_common.c
> @@ -473,10 +473,11 @@ dma_addr_t __otx2_alloc_rbuf(struct otx2
>   dma_addr_t iova;
>   u8 *buf;
>  
> - buf = napi_alloc_frag(pool->rbsize);
> + buf = napi_alloc_frag(pool->rbsize + OTX2_ALIGN);
>   if (unlikely(!buf))
>   return -ENOMEM;
>  
> + buf = PTR_ALIGN(buf, OTX2_ALIGN);

So we allocate a buffer, then change it, and then pass modified
pointer to the page_frag_free(buf); in the error path. That... can't
be right, right?

>   iova = dma_map_single_attrs(pfvf->dev, buf, pool->rbsize,
>   DMA_FROM_DEVICE, DMA_ATTR_SKIP_CPU_SYNC);
>   if (unlikely(dma_mapping_error(pfvf->dev, iova))) {

BTW otx2_alloc_rbuf and __otx2_alloc_rbuf should probably return s64,
as they return negative error code...

Best regards,
Pavel

-- 
http://www.livejournal.com/~pavelmachek


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Description: Digital signature

Re: [PATCH 11/18] arm64: Kconfig: Require FIQ support for ARCH_APPLE

[Hector Martin 'marcan']

On 07/02/2021 00.46, Marc Zyngier wrote:

  config ARCH_APPLE
bool "Apple Silicon SoC family"
select GENERIC_IRQ_CHIP
+   select ARM64_FIQ_SUPPORT


Ah, this is what I was expecting in the previous patch. I guess the
initial ARCH_APPLE patch could be moved down the line and add all the
dependencies in one go.


I was trying to introduce the Kconfig before the code that depends on 
it; is it kosher to have it in the other order, looking for CONFIG_ 
defines that don't exist yet?


Though in this case the only user earlier in the series is the Samsung 
stuff, which doesn't care about FIQs, so I can just sort things as 
FIQ->ARCH_APPLE->samsung->AIC...


I'm not sure about AIC vs. ARCH_APPLE though. Right now the pattern is 
that AIC depends on ARCH_APPLE and also defaults to that. But then you 
can build with ARCH_APPLE and AIC disabled if you so choose, which does 
result in a broken system on these machines. AIC should build without 
ARCH_APPLE (as long as we're on ARM64), so we could reverse that.


--
Hector Martin "marcan" (mar...@marcan.st)
Public Key: https://mrcn.st/pub

Re: [PATCH 5.4 01/32] net: dsa: bcm_sf2: put device node before return

[Pavel Machek]

Hi!

> From: Pan Bian 
> 
> commit cf3c46631e1637582f517a574c77cd6c05793817 upstream.
> 
> Put the device node dn before return error code on failure path.

This fixes one resource leak, but exposes next one: get_device() is
not undone in the second error path and in the end of function.

Best regards,
Pavel

> +++ b/drivers/net/dsa/bcm_sf2.c
> @@ -421,15 +421,19 @@ static int bcm_sf2_mdio_register(struct
>   /* Find our integrated MDIO bus node */
>   dn = of_find_compatible_node(NULL, NULL, "brcm,unimac-mdio");
>   priv->master_mii_bus = of_mdio_find_bus(dn);
> - if (!priv->master_mii_bus)
> + if (!priv->master_mii_bus) {
> + of_node_put(dn);
>   return -EPROBE_DEFER;
> + }
>  
>   get_device(&priv->master_mii_bus->dev);
>   priv->master_mii_dn = dn;
>  
>   priv->slave_mii_bus = devm_mdiobus_alloc(ds->dev);
> - if (!priv->slave_mii_bus)
> + if (!priv->slave_mii_bus) {
> + of_node_put(dn);
>   return -ENOMEM;
> + }
>  
>   priv->slave_mii_bus->priv = priv;
>   priv->slave_mii_bus->name = "sf2 slave mii";
> 

-- 
http://www.livejournal.com/~pavelmachek


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Description: Digital signature

[PATCH] staging: fix ignoring return value warning

[Youling Tang]

Fix the below ignoring return value warning for device_reset.

drivers/staging/mt7621-dma/mtk-hsdma.c:685:2: warning: ignoring return value
of function declared with 'warn_unused_result' attribute [-Wunused-result]
device_reset(&pdev->dev);
^~~~ ~~
drivers/staging/ralink-gdma/ralink-gdma.c:836:2: warning: ignoring return value
of function declared with 'warn_unused_result' attribute [-Wunused-result]
device_reset(&pdev->dev);
^~~~ ~~

Signed-off-by: Youling Tang 
---
 drivers/staging/mt7621-dma/mtk-hsdma.c| 6 +-
 drivers/staging/ralink-gdma/ralink-gdma.c | 6 +-
 2 files changed, 10 insertions(+), 2 deletions(-)

diff --git a/drivers/staging/mt7621-dma/mtk-hsdma.c 
b/drivers/staging/mt7621-dma/mtk-hsdma.c
index bc4bb43..d4ffa52 100644
--- a/drivers/staging/mt7621-dma/mtk-hsdma.c
+++ b/drivers/staging/mt7621-dma/mtk-hsdma.c
@@ -682,7 +682,11 @@ static int mtk_hsdma_probe(struct platform_device *pdev)
return ret;
}
 
-   device_reset(&pdev->dev);
+   ret = device_reset(&pdev->dev);
+   if (ret) {
+   dev_err(&pdev->dev, "failed to reset device\n");
+   return ret;
+   }
 
dd = &hsdma->ddev;
dma_cap_set(DMA_MEMCPY, dd->cap_mask);
diff --git a/drivers/staging/ralink-gdma/ralink-gdma.c 
b/drivers/staging/ralink-gdma/ralink-gdma.c
index 655df31..df99c47 100644
--- a/drivers/staging/ralink-gdma/ralink-gdma.c
+++ b/drivers/staging/ralink-gdma/ralink-gdma.c
@@ -833,7 +833,11 @@ static int gdma_dma_probe(struct platform_device *pdev)
return ret;
}
 
-   device_reset(&pdev->dev);
+   ret = device_reset(&pdev->dev);
+   if (ret) {
+   dev_err(&pdev->dev, "failed to reset device\n");
+   return ret;
+   }
 
dd = &dma_dev->ddev;
dma_cap_set(DMA_MEMCPY, dd->cap_mask);
-- 
2.1.0

Re: [PATCH 05/18] tty: serial: samsung_tty: add support for Apple UARTs

[Hector Martin 'marcan']

On 07/02/2021 18.12, Hector Martin 'marcan' wrote:

On 06/02/2021 22.15, Marc Zyngier wrote:

The default should be IRQ_NONE, otherwise the kernel cannot detect a
screaming spurious interrupt.


Good point, and this needs fixing in s3c64xx_serial_handle_irq too then
(which is what I based mine off of).


+   ret = request_irq(port->irq, apple_serial_handle_irq, IRQF_SHARED,
+ s3c24xx_serial_portname(port), ourport);


Why IRQF_SHARED? Do you expect any other device sharing the same line
with this UART?


This also came from s3c64xx_serial_startup and... now I wonder why that
one needs it. Maybe on some SoCs it does get shared? Certainly not for
discrete rx/tx irq chips (and indeed those don't set the flag)...

CCing Thomas, who added the S3C64xx support (and should probably review
this patch); is there a reason for IRQF_SHARED there? NB: v1 breaks the
build on arm or with CONFIG_PM_SLEEP, those will be fixed for v2.


Seems Thomas does not work for Linaro any more :)

CCing Krzysztof instead, who is the Samsung arch maintainer.



Either way, certainly not for Apple SoCs; I'll get rid of IRQF_SHARED
for v2.


--
Hector Martin "marcan" (mar...@marcan.st)
Public Key: https://mrcn.st/pub

Re: [PATCH v2 2/2] drivers/clocksource: Fixup csky,mptimer compile error with CPU_CK610

[Daniel Lezcano]

On 07/02/2021 04:31, Guo Ren wrote:
> Hi Daniel,
> 
> On Thu, Feb 4, 2021 at 4:48 PM Daniel Lezcano  
> wrote:
>>
>> On 04/02/2021 08:46, guo...@kernel.org wrote:
>>> From: Guo Ren 
>>>
>>> The timer-mp-csky.c only could support CPU_CK860 and it will
>>> compile error with CPU_CK610.
>>>
>>> It has been selected in arch/csky/Kconfig.
>>
>> It would be better if you fix the root cause of the compilation error.
> The timer-mp-csky.c has used specific instructions which only
> supported by CK860 and timer-mp-csky.c is only design for CK860.

I guess you are referring to mfcr() ?

> In arch/csky/Konfig we only select it with CK860.
> select CSKY_MPINTC if CPU_CK860
> select CSKY_MP_TIMER if CPU_CK860
> 
> So here let's select timer-mp-csky.c in arch/csky/Kconfig, not in
> drivers/clocksource/Kconfig.

The COMPILE_TEST option is there to let other architecture to compile
drivers and increase the compilation test coverage.

The proposed change just removes the driver from this coverage.

Ideally, it would be better to keep it with the COMPILE_TEST option, so
changes impacting all the drivers can be caught before submitting the
patches.

By just adding

#ifndef mfcr
#define mfcr(a) 0
#endif

shoud fix the compilation issue, no ?


-- 
 Linaro.org │ Open source software for ARM SoCs

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Re: [PATCH] staging: fix ignoring return value warning

[Greg Kroah-Hartman]

On Sun, Feb 07, 2021 at 05:23:28PM +0800, Youling Tang wrote:
> Fix the below ignoring return value warning for device_reset.
> 
> drivers/staging/mt7621-dma/mtk-hsdma.c:685:2: warning: ignoring return value
> of function declared with 'warn_unused_result' attribute [-Wunused-result]
> device_reset(&pdev->dev);
> ^~~~ ~~
> drivers/staging/ralink-gdma/ralink-gdma.c:836:2: warning: ignoring return 
> value
> of function declared with 'warn_unused_result' attribute [-Wunused-result]
> device_reset(&pdev->dev);
> ^~~~ ~~
> 
> Signed-off-by: Youling Tang 
> ---
>  drivers/staging/mt7621-dma/mtk-hsdma.c| 6 +-
>  drivers/staging/ralink-gdma/ralink-gdma.c | 6 +-
>  2 files changed, 10 insertions(+), 2 deletions(-)
> 
> diff --git a/drivers/staging/mt7621-dma/mtk-hsdma.c 
> b/drivers/staging/mt7621-dma/mtk-hsdma.c
> index bc4bb43..d4ffa52 100644
> --- a/drivers/staging/mt7621-dma/mtk-hsdma.c
> +++ b/drivers/staging/mt7621-dma/mtk-hsdma.c
> @@ -682,7 +682,11 @@ static int mtk_hsdma_probe(struct platform_device *pdev)
>   return ret;
>   }
>  
> - device_reset(&pdev->dev);
> + ret = device_reset(&pdev->dev);
> + if (ret) {
> + dev_err(&pdev->dev, "failed to reset device\n");
> + return ret;
> + }
>  
>   dd = &hsdma->ddev;
>   dma_cap_set(DMA_MEMCPY, dd->cap_mask);
> diff --git a/drivers/staging/ralink-gdma/ralink-gdma.c 
> b/drivers/staging/ralink-gdma/ralink-gdma.c
> index 655df31..df99c47 100644
> --- a/drivers/staging/ralink-gdma/ralink-gdma.c
> +++ b/drivers/staging/ralink-gdma/ralink-gdma.c
> @@ -833,7 +833,11 @@ static int gdma_dma_probe(struct platform_device *pdev)
>   return ret;
>   }
>  
> - device_reset(&pdev->dev);
> + ret = device_reset(&pdev->dev);
> + if (ret) {
> + dev_err(&pdev->dev, "failed to reset device\n");
> + return ret;
> + }
>  
>   dd = &dma_dev->ddev;
>   dma_cap_set(DMA_MEMCPY, dd->cap_mask);
> -- 
> 2.1.0
> 


Hi,

This is the friendly patch-bot of Greg Kroah-Hartman.  You have sent him
a patch that has triggered this response.  He used to manually respond
to these common problems, but in order to save his sanity (he kept
writing the same thing over and over, yet to different people), I was
created.  Hopefully you will not take offence and will fix the problem
in your patch and resubmit it so that it can be accepted into the Linux
kernel tree.

You are receiving this message because of the following common error(s)
as indicated below:

- Your patch did not apply to any known trees that Greg is in control
  of.  Possibly this is because you made it against Linus's tree, not
  the linux-next tree, which is where all of the development for the
  next version of the kernel is at.  Please refresh your patch against
  the linux-next tree, or even better yet, the development tree
  specified in the MAINTAINERS file for the subsystem you are submitting
  a patch for, and resend it.

If you wish to discuss this problem further, or you have questions about
how to resolve this issue, please feel free to respond to this email and
Greg will reply once he has dug out from the pending patches received
from other developers.

thanks,

greg k-h's patch email bot

[PATCH] I was wondering why I can't set the resolution to 2560x1080, while in windows 7 I can without a problem. I looked at the radeon driver code and found it doesn't support this resolution. So I m

[Marcin Raszka]

---
 drivers/gpu/drm/radeon/radeon_benchmark.c  |  5 ++--
 drivers/gpu/drm/radeon/radeon_connectors.c | 30 ++
 drivers/gpu/drm/radeon/radeon_drv.c|  5 
 drivers/gpu/drm/radeon/radeon_encoders.c   |  6 +++--
 4 files changed, 32 insertions(+), 14 deletions(-)

diff --git a/drivers/gpu/drm/radeon/radeon_benchmark.c 
b/drivers/gpu/drm/radeon/radeon_benchmark.c
index ac9a5ec481c3..c283b6b15925 100644
--- a/drivers/gpu/drm/radeon/radeon_benchmark.c
+++ b/drivers/gpu/drm/radeon/radeon_benchmark.c
@@ -30,7 +30,7 @@
 #define RADEON_BENCHMARK_COPY_DMA  0
 
 #define RADEON_BENCHMARK_ITERATIONS 1024
-#define RADEON_BENCHMARK_COMMON_MODES_N 17
+#define RADEON_BENCHMARK_COMMON_MODES_N 18
 
 static int radeon_benchmark_do_move(struct radeon_device *rdev, unsigned size,
uint64_t saddr, uint64_t daddr,
@@ -184,7 +184,8 @@ void radeon_benchmark(struct radeon_device *rdev, int 
test_number)
1680 * 1050 * 4,
1600 * 1200 * 4,
1920 * 1080 * 4,
-   1920 * 1200 * 4
+   1920 * 1200 * 4,
+   2560 * 1080 * 4
};
 
switch (test_number) {
diff --git a/drivers/gpu/drm/radeon/radeon_connectors.c 
b/drivers/gpu/drm/radeon/radeon_connectors.c
index 607ad5620bd9..37927222f5b3 100644
--- a/drivers/gpu/drm/radeon/radeon_connectors.c
+++ b/drivers/gpu/drm/radeon/radeon_connectors.c
@@ -37,6 +37,8 @@
 #include 
 #include 
 
+extern int hdmimhz;
+
 static int radeon_dp_handle_hpd(struct drm_connector *connector)
 {
struct radeon_connector *radeon_connector = 
to_radeon_connector(connector);
@@ -503,7 +505,7 @@ static void radeon_add_common_modes(struct drm_encoder 
*encoder, struct drm_conn
struct mode_size {
int w;
int h;
-   } common_modes[17] = {
+   } common_modes[18] = {
{ 640,  480},
{ 720,  480},
{ 800,  600},
@@ -520,10 +522,11 @@ static void radeon_add_common_modes(struct drm_encoder 
*encoder, struct drm_conn
{1680, 1050},
{1600, 1200},
{1920, 1080},
-   {1920, 1200}
+   {1920, 1200},
+   {2560, 1080}
};
 
-   for (i = 0; i < 17; i++) {
+   for (i = 0; i < 18; i++) {
if (radeon_encoder->devices & (ATOM_DEVICE_TV_SUPPORT)) {
if (common_modes[i].w > 1024 ||
common_modes[i].h > 768)
@@ -1491,25 +1494,32 @@ static enum drm_mode_status 
radeon_dvi_mode_valid(struct drm_connector *connecto
(mode->clock > 135000))
return MODE_CLOCK_HIGH;
 
-   if (radeon_connector->use_digital && (mode->clock > 165000)) {
+   if (radeon_connector->use_digital && (mode->clock > (hdmimhz * 1000))) {
if ((radeon_connector->connector_object_id == 
CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_I) ||
(radeon_connector->connector_object_id == 
CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_D) ||
-   (radeon_connector->connector_object_id == 
CONNECTOR_OBJECT_ID_HDMI_TYPE_B))
+   (radeon_connector->connector_object_id == 
CONNECTOR_OBJECT_ID_HDMI_TYPE_B)){
+   printk("MODE_CLOCK_HIHG0 %d", hdmimhz);
return MODE_OK;
-   else if (ASIC_IS_DCE6(rdev) && 
drm_detect_hdmi_monitor(radeon_connector_edid(connector))) {
+   }else if (ASIC_IS_DCE6(rdev) && 
drm_detect_hdmi_monitor(radeon_connector_edid(connector))) {
/* HDMI 1.3+ supports max clock of 340 Mhz */
-   if (mode->clock > 34)
+   if (mode->clock > 34){
+   printk("MODE_CLOCK_HIHG1 %d", hdmimhz);
return MODE_CLOCK_HIGH;
-   else
+   }else{
+   printk("MODE_OK1");
return MODE_OK;
+   }
} else {
+   printk("MODE_CLOCK_HIHG2 %d", hdmimhz);
return MODE_CLOCK_HIGH;
}
}
 
/* check against the max pixel clock */
-   if ((mode->clock / 10) > rdev->clock.max_pixel_clock)
+   if ((mode->clock / 10) > rdev->clock.max_pixel_clock){
+   printk("MODE_CLOCK_HIHG3 %d", hdmimhz);
return MODE_CLOCK_HIGH;
+   }
 
return MODE_OK;
 }
@@ -1809,7 +1819,7 @@ static enum drm_mode_status radeon_dp_mode_valid(struct 
drm_connector *connector
if (mode->clock > 34)
return MODE_CLOCK_HIGH;
} else {
-   if (mode->clock > 165000)
+   if (mode->clock > (hdmimhz * 1000))
return MODE_CLOCK_HIGH;
  

Re: [PATCH] m68k: Drop -fno-strength-reduce from KBUILD_CFLAGS

[Geert Uytterhoeven]

Hi Adrian,

On Sun, Feb 7, 2021 at 9:51 AM John Paul Adrian Glaubitz
 wrote:
> On 2/7/21 8:02 AM, Finn Thain wrote:
> > References: commit 565bae6a4a8f ("[SCSI] 53c7xx: kill driver")
>
> Does that mean there is currently no driver for the A4091?

Supported by the replacement driver:
45804fbb00eea27b ("[SCSI] 53c700: Amiga Zorro NCR53c710 SCSI")

Gr{oetje,eeting}s,

Geert

-- 
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- ge...@linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds

[PATCH] I was wondering why I can't set the resolution to 2560x1080, while in windows 7 I can without a problem. I looked at the radeon driver code and found it doesn't support this resolution. So I m

[Marcin Raszka]

---
 drivers/gpu/drm/radeon/radeon_benchmark.c  |  5 ++--
 drivers/gpu/drm/radeon/radeon_connectors.c | 30 ++
 drivers/gpu/drm/radeon/radeon_drv.c|  5 
 drivers/gpu/drm/radeon/radeon_encoders.c   |  6 +++--
 4 files changed, 32 insertions(+), 14 deletions(-)

diff --git a/drivers/gpu/drm/radeon/radeon_benchmark.c 
b/drivers/gpu/drm/radeon/radeon_benchmark.c
index ac9a5ec481c3..c283b6b15925 100644
--- a/drivers/gpu/drm/radeon/radeon_benchmark.c
+++ b/drivers/gpu/drm/radeon/radeon_benchmark.c
@@ -30,7 +30,7 @@
 #define RADEON_BENCHMARK_COPY_DMA  0
 
 #define RADEON_BENCHMARK_ITERATIONS 1024
-#define RADEON_BENCHMARK_COMMON_MODES_N 17
+#define RADEON_BENCHMARK_COMMON_MODES_N 18
 
 static int radeon_benchmark_do_move(struct radeon_device *rdev, unsigned size,
uint64_t saddr, uint64_t daddr,
@@ -184,7 +184,8 @@ void radeon_benchmark(struct radeon_device *rdev, int 
test_number)
1680 * 1050 * 4,
1600 * 1200 * 4,
1920 * 1080 * 4,
-   1920 * 1200 * 4
+   1920 * 1200 * 4,
+   2560 * 1080 * 4
};
 
switch (test_number) {
diff --git a/drivers/gpu/drm/radeon/radeon_connectors.c 
b/drivers/gpu/drm/radeon/radeon_connectors.c
index 607ad5620bd9..37927222f5b3 100644
--- a/drivers/gpu/drm/radeon/radeon_connectors.c
+++ b/drivers/gpu/drm/radeon/radeon_connectors.c
@@ -37,6 +37,8 @@
 #include 
 #include 
 
+extern int hdmimhz;
+
 static int radeon_dp_handle_hpd(struct drm_connector *connector)
 {
struct radeon_connector *radeon_connector = 
to_radeon_connector(connector);
@@ -503,7 +505,7 @@ static void radeon_add_common_modes(struct drm_encoder 
*encoder, struct drm_conn
struct mode_size {
int w;
int h;
-   } common_modes[17] = {
+   } common_modes[18] = {
{ 640,  480},
{ 720,  480},
{ 800,  600},
@@ -520,10 +522,11 @@ static void radeon_add_common_modes(struct drm_encoder 
*encoder, struct drm_conn
{1680, 1050},
{1600, 1200},
{1920, 1080},
-   {1920, 1200}
+   {1920, 1200},
+   {2560, 1080}
};
 
-   for (i = 0; i < 17; i++) {
+   for (i = 0; i < 18; i++) {
if (radeon_encoder->devices & (ATOM_DEVICE_TV_SUPPORT)) {
if (common_modes[i].w > 1024 ||
common_modes[i].h > 768)
@@ -1491,25 +1494,32 @@ static enum drm_mode_status 
radeon_dvi_mode_valid(struct drm_connector *connecto
(mode->clock > 135000))
return MODE_CLOCK_HIGH;
 
-   if (radeon_connector->use_digital && (mode->clock > 165000)) {
+   if (radeon_connector->use_digital && (mode->clock > (hdmimhz * 1000))) {
if ((radeon_connector->connector_object_id == 
CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_I) ||
(radeon_connector->connector_object_id == 
CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_D) ||
-   (radeon_connector->connector_object_id == 
CONNECTOR_OBJECT_ID_HDMI_TYPE_B))
+   (radeon_connector->connector_object_id == 
CONNECTOR_OBJECT_ID_HDMI_TYPE_B)){
+   printk("MODE_CLOCK_HIHG0 %d", hdmimhz);
return MODE_OK;
-   else if (ASIC_IS_DCE6(rdev) && 
drm_detect_hdmi_monitor(radeon_connector_edid(connector))) {
+   }else if (ASIC_IS_DCE6(rdev) && 
drm_detect_hdmi_monitor(radeon_connector_edid(connector))) {
/* HDMI 1.3+ supports max clock of 340 Mhz */
-   if (mode->clock > 34)
+   if (mode->clock > 34){
+   printk("MODE_CLOCK_HIHG1 %d", hdmimhz);
return MODE_CLOCK_HIGH;
-   else
+   }else{
+   printk("MODE_OK1");
return MODE_OK;
+   }
} else {
+   printk("MODE_CLOCK_HIHG2 %d", hdmimhz);
return MODE_CLOCK_HIGH;
}
}
 
/* check against the max pixel clock */
-   if ((mode->clock / 10) > rdev->clock.max_pixel_clock)
+   if ((mode->clock / 10) > rdev->clock.max_pixel_clock){
+   printk("MODE_CLOCK_HIHG3 %d", hdmimhz);
return MODE_CLOCK_HIGH;
+   }
 
return MODE_OK;
 }
@@ -1809,7 +1819,7 @@ static enum drm_mode_status radeon_dp_mode_valid(struct 
drm_connector *connector
if (mode->clock > 34)
return MODE_CLOCK_HIGH;
} else {
-   if (mode->clock > 165000)
+   if (mode->clock > (hdmimhz * 1000))
return MODE_CLOCK_HIGH;
  

Re: [PATCH 2/7] ASoC: fsl_rpmsg: Add CPU DAI driver for audio base on rpmsg

[Shengjiu Wang]

On Fri, Feb 5, 2021 at 10:04 PM Mark Brown  wrote:
>
> On Fri, Feb 05, 2021 at 02:57:25PM +0800, Shengjiu Wang wrote:
> > This is a dummy cpu dai driver for rpmsg audio use case,
> > which is mainly used for getting the user's configuration
>
> This is actually doing stuff, it's not a dummy driver.
>
> > +static int fsl_rpmsg_remove(struct platform_device *pdev)
> > +{
> > + return 0;
> > +}
>
> If this isn't needed just remove it.

Thanks Mark. I will update them.

Best regards
Wang shengjiu

Re: [PATCH 4/7] ASoC: imx-audio-rpmsg: Add rpmsg_driver for audio channel

[Shengjiu Wang]

On Fri, Feb 5, 2021 at 10:27 PM Mark Brown  wrote:
>
> On Fri, Feb 05, 2021 at 02:57:27PM +0800, Shengjiu Wang wrote:
>
> > + /* TYPE C is notification from M core */
> > + if (r_msg->header.type == MSG_TYPE_C) {
> > + if (r_msg->header.cmd == TX_PERIOD_DONE) {
>
> > + } else if (r_msg->header.cmd == RX_PERIOD_DONE) {
>
> A switch statement would be clearer and more extensible...
>
> > + /* TYPE B is response msg */
> > + if (r_msg->header.type == MSG_TYPE_B) {
> > + memcpy(&info->r_msg, r_msg, sizeof(struct rpmsg_r_msg));
> > + complete(&info->cmd_complete);
> > + }
>
> ...and make this flow clearer for example.  Do we need to warn on
> unknown messages?

Thanks for reviewing. I will update them.

Best regards
wang shengjiu

Re: [PATCH 5/7] ASoC: imx-pcm-rpmsg: Add platform driver for audio base on rpmsg

[Shengjiu Wang]

On Fri, Feb 5, 2021 at 11:00 PM Mark Brown  wrote:
>
> On Fri, Feb 05, 2021 at 02:57:28PM +0800, Shengjiu Wang wrote:
>
> > + if (params_format(params) == SNDRV_PCM_FORMAT_S16_LE)
> > + msg->s_msg.param.format   = RPMSG_S16_LE;
> > + else if (params_format(params) == SNDRV_PCM_FORMAT_S24_LE)
>
> Again this should be a switch statement.
>
> > + if (params_channels(params) == 1)
> > + msg->s_msg.param.channels = RPMSG_CH_LEFT;
> > + else
> > + msg->s_msg.param.channels = RPMSG_CH_STEREO;
>
> Shouldn't this be reporting an error if the number of channels is more
> than 2?
>
> > + /*
> > +  * if the data in the buffer is less than one period
> > +  * send message immediately.
> > +  * if there is more than one period data, delay one
> > +  * period (timer) to send the message.
> > +  */
> > + if ((avail - writen_num * period_size) <= period_size) {
> > + imx_rpmsg_insert_workqueue(substream, msg, info);
> > + } else if (rpmsg->force_lpa && !timer_pending(timer)) {
> > + int time_msec;
> > +
> > + time_msec = (int)(runtime->period_size * 1000 / 
> > runtime->rate);
> > + mod_timer(timer, jiffies + 
> > msecs_to_jiffies(time_msec));
> > + }
>
> The comment here is at least confusing - why would we not send a full
> buffer immediately if we have one?  This sounds like it's the opposite
> way round to what we'd do if we were trying to cut down the number of
> messages.  It might help to say which buffer and where?
>
> > + /**
> > +  * Every work in the work queue, first we check if there
>
> /** comments are only for kerneldoc.

Thanks Mark, I will update them.

Best regards
wang shengjiu

Re: [PATCH 3/3] crypto: hisilicon/sec - fixes shash test error

[liulongfang]

On 2021/2/7 16:02, Ard Biesheuvel wrote:
> On Sun, 7 Feb 2021 at 03:47, liulongfang  wrote:
>>
>> On 2021/2/5 19:44, Herbert Xu write:
>>> On Fri, Feb 05, 2021 at 06:10:57PM +0800, Longfang Liu wrote:
 If this configuration item is not turned on,
 the allocation of crypto_tfm will fail when
 the shash algorithm calculates the hash
 through the software.

 Signed-off-by: Longfang Liu 
 ---
  arch/arm64/configs/defconfig | 2 +-
  1 file changed, 1 insertion(+), 1 deletion(-)

 diff --git a/arch/arm64/configs/defconfig b/arch/arm64/configs/defconfig
 index 8383016..7cfc9b6 100644
 --- a/arch/arm64/configs/defconfig
 +++ b/arch/arm64/configs/defconfig
 @@ -117,7 +117,7 @@ CONFIG_KVM=y
  CONFIG_ARM64_CRYPTO=y
  CONFIG_CRYPTO_SHA1_ARM64_CE=y
  CONFIG_CRYPTO_SHA2_ARM64_CE=y
 -CONFIG_CRYPTO_SHA512_ARM64_CE=m
 +CONFIG_CRYPTO_SHA512_ARM64_CE=y
>>>
>>> If this is truly needed then it should be enabled through Kconfig.
>>>
>>> Cheers,
>>>
>> Hi Herbert,
>> The option select CRYPTO_SHA512 already exists in Kconfig.
> 
> In that case, how can the shash TFM allocation fail?
> 
Hi
After comparison and investigation, the problem is that the header
file "crypto/internal/hash.h" is not added. After adding this header file,
which CRYPTO_SHA512_ARM64_C compilation option does not need to be enabled.
I will modify it in the next patch.
>> Can I change it to this: select CRYPTO_SHA512 || CRYPTO_SHA512_ARM64_CE
> 
> No, you cannot select expressions like that.
> 
> Could you please explain the problem you are trying to solve?
> .
> 
When allocation shash TFM with hmac(sha512)-cbc(aes) algorithm,
TFM will return an error.
Thanks
Longfang.

arch/mips/loongson64/cop2-ex.c:97:30: error: no member named 'fpu' in 'struct thread_struct'

[kernel test robot]

tree:   https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git 
master
head:   61556703b610a104de324e4f061dc6cf7b218b46
commit: f83e4f9896eff614d0f2547a561fa5f39f9cddde MIPS: Loongson-3: Add some 
unaligned instructions emulation
date:   10 months ago
config: mips-randconfig-r032-20210207 (attached as .config)
compiler: clang version 12.0.0 (https://github.com/llvm/llvm-project 
c9439ca36342fb6013187d0a69aef92736951476)
reproduce (this is a W=1 build):
wget 
https://raw.githubusercontent.com/intel/lkp-tests/master/sbin/make.cross -O 
~/bin/make.cross
chmod +x ~/bin/make.cross
# install mips cross compiling tool for clang build
# apt-get install binutils-mips-linux-gnu
# 
https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/commit/?id=f83e4f9896eff614d0f2547a561fa5f39f9cddde
git remote add linus 
https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
git fetch --no-tags linus master
git checkout f83e4f9896eff614d0f2547a561fa5f39f9cddde
# save the attached .config to linux build tree
COMPILER_INSTALL_PATH=$HOME/0day COMPILER=clang make.cross ARCH=mips 

If you fix the issue, kindly add following tag as appropriate
Reported-by: kernel test robot 

All errors (new ones prefixed by >>):

   arch/mips/loongson64/cop2-ex.c:44:15: error: implicit declaration of 
function '__is_fpu_owner' [-Werror,-Wimplicit-function-declaration]
   fpu_owned = __is_fpu_owner();
   ^
   arch/mips/loongson64/cop2-ex.c:44:15: note: did you mean 'is_fpu_owner'?
   arch/mips/include/asm/fpu.h:269:19: note: 'is_fpu_owner' declared here
   static inline int is_fpu_owner(void)
 ^
>> arch/mips/loongson64/cop2-ex.c:97:30: error: no member named 'fpu' in 
>> 'struct thread_struct'
   set_fpr64(current->thread.fpu.fpr,
 ~~~ ^
   arch/mips/loongson64/cop2-ex.c:99:30: error: no member named 'fpu' in 
'struct thread_struct'
   set_fpr64(current->thread.fpu.fpr,
 ~~~ ^
   arch/mips/loongson64/cop2-ex.c:132:43: error: no member named 'fpu' in 
'struct thread_struct'
   value_next = get_fpr64(current->thread.fpu.fpr,
  ~~~ ^
   arch/mips/loongson64/cop2-ex.c:139:38: error: no member named 'fpu' in 
'struct thread_struct'
   value = get_fpr64(current->thread.fpu.fpr,
 ~~~ ^
   arch/mips/loongson64/cop2-ex.c:206:30: error: no member named 'fpu' in 
'struct thread_struct'
   set_fpr64(current->thread.fpu.fpr,
 ~~~ ^
   arch/mips/loongson64/cop2-ex.c:223:30: error: no member named 'fpu' in 
'struct thread_struct'
   set_fpr64(current->thread.fpu.fpr,
 ~~~ ^
   arch/mips/loongson64/cop2-ex.c:288:38: error: no member named 'fpu' in 
'struct thread_struct'
   value = get_fpr64(current->thread.fpu.fpr,
 ~~~ ^
   arch/mips/loongson64/cop2-ex.c:307:38: error: no member named 'fpu' in 
'struct thread_struct'
   value = get_fpr64(current->thread.fpu.fpr,
 ~~~ ^
   9 errors generated.


vim +97 arch/mips/loongson64/cop2-ex.c

26  
27  static int loongson_cu2_call(struct notifier_block *nfb, unsigned long 
action,
28  void *data)
29  {
30  unsigned int res, fpu_owned;
31  unsigned long ra, value, value_next;
32  union mips_instruction insn;
33  int fr = !test_thread_flag(TIF_32BIT_FPREGS);
34  struct pt_regs *regs = (struct pt_regs *)data;
35  void __user *addr = (void __user *)regs->cp0_badvaddr;
36  unsigned int __user *pc = (unsigned int __user 
*)exception_epc(regs);
37  
38  ra = regs->regs[31];
39  __get_user(insn.word, pc);
40  
41  switch (action) {
42  case CU2_EXCEPTION:
43  preempt_disable();
  > 44  fpu_owned = __is_fpu_owner();
45  if (!fr)
46  set_c0_status(ST0_CU1 | ST0_CU2);
47  else
48  set_c0_status(ST0_CU1 | ST0_CU2 | ST0_FR);
49  enable_fpu_hazard();
50  KSTK_STATUS(current) |= (ST0_CU1 | ST0_C

Re: [RFC PATCH 10/11] vfio/iommu_type1: Optimize dirty bitmap population based on iommu HWDBM

[Yi Sun]

Hi,

On 21-01-28 23:17:41, Keqian Zhu wrote:

[...]

> +static void vfio_dma_dirty_log_start(struct vfio_iommu *iommu,
> +  struct vfio_dma *dma)
> +{
> + struct vfio_domain *d;
> +
> + list_for_each_entry(d, &iommu->domain_list, next) {
> + /* Go through all domain anyway even if we fail */
> + iommu_split_block(d->domain, dma->iova, dma->size);
> + }
> +}

This should be a switch to prepare for dirty log start. Per Intel
Vtd spec, there is SLADE defined in Scalable-Mode PASID Table Entry.
It enables Accessed/Dirty Flags in second-level paging entries.
So, a generic iommu interface here is better. For Intel iommu, it
enables SLADE. For ARM, it splits block.

> +
> +static void vfio_dma_dirty_log_stop(struct vfio_iommu *iommu,
> + struct vfio_dma *dma)
> +{
> + struct vfio_domain *d;
> +
> + list_for_each_entry(d, &iommu->domain_list, next) {
> + /* Go through all domain anyway even if we fail */
> + iommu_merge_page(d->domain, dma->iova, dma->size,
> +  d->prot | dma->prot);
> + }
> +}

Same as above comment, a generic interface is required here.

> +
> +static void vfio_iommu_dirty_log_switch(struct vfio_iommu *iommu, bool start)
> +{
> + struct rb_node *n;
> +
> + /* Split and merge even if all iommu don't support HWDBM now */
> + for (n = rb_first(&iommu->dma_list); n; n = rb_next(n)) {
> + struct vfio_dma *dma = rb_entry(n, struct vfio_dma, node);
> +
> + if (!dma->iommu_mapped)
> + continue;
> +
> + /* Go through all dma range anyway even if we fail */
> + if (start)
> + vfio_dma_dirty_log_start(iommu, dma);
> + else
> + vfio_dma_dirty_log_stop(iommu, dma);
> + }
> +}
> +
>  static int vfio_iommu_type1_dirty_pages(struct vfio_iommu *iommu,
>   unsigned long arg)
>  {
> @@ -2812,8 +2900,10 @@ static int vfio_iommu_type1_dirty_pages(struct 
> vfio_iommu *iommu,
>   pgsize = 1 << __ffs(iommu->pgsize_bitmap);
>   if (!iommu->dirty_page_tracking) {
>   ret = vfio_dma_bitmap_alloc_all(iommu, pgsize);
> - if (!ret)
> + if (!ret) {
>   iommu->dirty_page_tracking = true;
> + vfio_iommu_dirty_log_switch(iommu, true);
> + }
>   }
>   mutex_unlock(&iommu->lock);
>   return ret;
> @@ -2822,6 +2912,7 @@ static int vfio_iommu_type1_dirty_pages(struct 
> vfio_iommu *iommu,
>   if (iommu->dirty_page_tracking) {
>   iommu->dirty_page_tracking = false;
>   vfio_dma_bitmap_free_all(iommu);
> + vfio_iommu_dirty_log_switch(iommu, false);
>   }
>   mutex_unlock(&iommu->lock);
>   return 0;
> -- 
> 2.19.1

[no subject]

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sein für dich.
Bitte kontaktieren Sie meine private E-Mail hier für weitere
Informationen: georgemike7...@gmail.com

Vielen Dank im Voraus,
Mr. George Mike,

[PATCH v2 1/3] crypto: hisilicon/sec - fixes some log printing style

[Longfang Liu]

1. Fix a problem of error log printing
2. Modify error log printing style

Signed-off-by: Longfang Liu 
---
 drivers/crypto/hisilicon/sec2/sec.h|  5 +-
 drivers/crypto/hisilicon/sec2/sec_crypto.c | 82 +++---
 drivers/crypto/hisilicon/sec2/sec_crypto.h |  2 -
 3 files changed, 42 insertions(+), 47 deletions(-)

diff --git a/drivers/crypto/hisilicon/sec2/sec.h 
b/drivers/crypto/hisilicon/sec2/sec.h
index 0849191..a8c10e3 100644
--- a/drivers/crypto/hisilicon/sec2/sec.h
+++ b/drivers/crypto/hisilicon/sec2/sec.h
@@ -4,8 +4,6 @@
 #ifndef __HISI_SEC_V2_H
 #define __HISI_SEC_V2_H
 
-#include 
-
 #include "../qm.h"
 #include "sec_crypto.h"
 
@@ -50,7 +48,7 @@ struct sec_req {
 
int err_type;
int req_id;
-   int flag;
+   u32 flag;
 
/* Status of the SEC request */
bool fake_busy;
@@ -139,6 +137,7 @@ struct sec_ctx {
bool pbuf_supported;
struct sec_cipher_ctx c_ctx;
struct sec_auth_ctx a_ctx;
+   struct device *dev;
 };
 
 enum sec_endian {
diff --git a/drivers/crypto/hisilicon/sec2/sec_crypto.c 
b/drivers/crypto/hisilicon/sec2/sec_crypto.c
index 2eaa516..d2c4a2c 100644
--- a/drivers/crypto/hisilicon/sec2/sec_crypto.c
+++ b/drivers/crypto/hisilicon/sec2/sec_crypto.c
@@ -43,7 +43,6 @@
 
 #define SEC_TOTAL_IV_SZ(SEC_IV_SIZE * QM_Q_DEPTH)
 #define SEC_SGL_SGE_NR 128
-#define SEC_CTX_DEV(ctx)   (&(ctx)->sec->qm.pdev->dev)
 #define SEC_CIPHER_AUTH0xfe
 #define SEC_AUTH_CIPHER0x1
 #define SEC_MAX_MAC_LEN64
@@ -96,7 +95,7 @@ static int sec_alloc_req_id(struct sec_req *req, struct 
sec_qp_ctx *qp_ctx)
  0, QM_Q_DEPTH, GFP_ATOMIC);
mutex_unlock(&qp_ctx->req_lock);
if (unlikely(req_id < 0)) {
-   dev_err(SEC_CTX_DEV(req->ctx), "alloc req id fail!\n");
+   dev_err(req->ctx->dev, "alloc req id fail!\n");
return req_id;
}
 
@@ -112,7 +111,7 @@ static void sec_free_req_id(struct sec_req *req)
int req_id = req->req_id;
 
if (unlikely(req_id < 0 || req_id >= QM_Q_DEPTH)) {
-   dev_err(SEC_CTX_DEV(req->ctx), "free request id invalid!\n");
+   dev_err(req->ctx->dev, "free request id invalid!\n");
return;
}
 
@@ -138,7 +137,7 @@ static int sec_aead_verify(struct sec_req *req)
aead_req->cryptlen + aead_req->assoclen -
authsize);
if (unlikely(sz != authsize || memcmp(mac_out, mac, sz))) {
-   dev_err(SEC_CTX_DEV(req->ctx), "aead verify failure!\n");
+   dev_err(req->ctx->dev, "aead verify failure!\n");
return -EBADMSG;
}
 
@@ -177,7 +176,7 @@ static void sec_req_cb(struct hisi_qp *qp, void *resp)
if (unlikely(req->err_type || done != SEC_SQE_DONE ||
(ctx->alg_type == SEC_SKCIPHER && flag != SEC_SQE_CFLAG) ||
(ctx->alg_type == SEC_AEAD && flag != SEC_SQE_AEAD_FLAG))) {
-   dev_err(SEC_CTX_DEV(ctx),
+   dev_err_ratelimited(ctx->dev,
"err_type[%d],done[%d],flag[%d]\n",
req->err_type, done, flag);
err = -EIO;
@@ -326,8 +325,8 @@ static int sec_alloc_pbuf_resource(struct device *dev, 
struct sec_alg_res *res)
 static int sec_alg_resource_alloc(struct sec_ctx *ctx,
  struct sec_qp_ctx *qp_ctx)
 {
-   struct device *dev = SEC_CTX_DEV(ctx);
struct sec_alg_res *res = qp_ctx->res;
+   struct device *dev = ctx->dev;
int ret;
 
ret = sec_alloc_civ_resource(dev, res);
@@ -360,7 +359,7 @@ static int sec_alg_resource_alloc(struct sec_ctx *ctx,
 static void sec_alg_resource_free(struct sec_ctx *ctx,
  struct sec_qp_ctx *qp_ctx)
 {
-   struct device *dev = SEC_CTX_DEV(ctx);
+   struct device *dev = ctx->dev;
 
sec_free_civ_resource(dev, qp_ctx->res);
 
@@ -373,7 +372,7 @@ static void sec_alg_resource_free(struct sec_ctx *ctx,
 static int sec_create_qp_ctx(struct hisi_qm *qm, struct sec_ctx *ctx,
 int qp_ctx_id, int alg_type)
 {
-   struct device *dev = SEC_CTX_DEV(ctx);
+   struct device *dev = ctx->dev;
struct sec_qp_ctx *qp_ctx;
struct hisi_qp *qp;
int ret = -ENOMEM;
@@ -428,7 +427,7 @@ static int sec_create_qp_ctx(struct hisi_qm *qm, struct 
sec_ctx *ctx,
 static void sec_release_qp_ctx(struct sec_ctx *ctx,
   struct sec_qp_ctx *qp_ctx)
 {
-   struct device *dev = SEC_CTX_DEV(ctx);
+   struct device *dev = ctx->dev;
 
hisi_qm_stop_qp(qp_ctx->qp);
sec_alg_resource_free(ctx, qp_ctx);
@@ -452,6 +451,7 @@ static int sec_ctx_base_init(struct sec_ctx *ctx)
 
sec = container_of(ctx->qps[0]->qm, struct sec_dev, qm);
ctx->sec = sec;
+   ctx->dev = &sec->

[PATCH v2 0/3] crypto:hisilicon/sec - fixes some coding style

[Longfang Liu]

1. Fix two problems.
2. Fix some coding style.

Changes v1 -> v2:
  - Modify the way to fix shash test error.

Longfang Liu (3):
  crypto: hisilicon/sec - fixes some log printing style
  crypto: hisilicon/sec - fixes some driver coding style
  crypto: hisilicon/sec - fixes shash test error

 drivers/crypto/hisilicon/sec2/sec.h|   5 +-
 drivers/crypto/hisilicon/sec2/sec_crypto.c |  83 +-
 drivers/crypto/hisilicon/sec2/sec_crypto.h |   2 -
 drivers/crypto/hisilicon/sec2/sec_main.c   | 131 +
 4 files changed, 119 insertions(+), 102 deletions(-)

-- 
2.8.1

[PATCH v2 3/3] crypto: hisilicon/sec - fixes shash test error

[Longfang Liu]

If the header file "crypto/internal/hash.h" not
added, the allocation of crypto_tfm will fail when
the shash algorithm calculates the hash
through the software.

Signed-off-by: Longfang Liu 
---
 drivers/crypto/hisilicon/sec2/sec_crypto.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/drivers/crypto/hisilicon/sec2/sec_crypto.c 
b/drivers/crypto/hisilicon/sec2/sec_crypto.c
index d2c4a2c..988faf7 100644
--- a/drivers/crypto/hisilicon/sec2/sec_crypto.c
+++ b/drivers/crypto/hisilicon/sec2/sec_crypto.c
@@ -7,6 +7,7 @@
 #include 
 #include 
 #include 
+#include 
 #include 
 #include 
 #include 
-- 
2.8.1

[PATCH v2 2/3] crypto: hisilicon/sec - fixes some driver coding style

[Longfang Liu]

cleanup static check errors for SEC

Signed-off-by: Longfang Liu 
---
 drivers/crypto/hisilicon/sec2/sec_main.c | 131 ++-
 1 file changed, 76 insertions(+), 55 deletions(-)

diff --git a/drivers/crypto/hisilicon/sec2/sec_main.c 
b/drivers/crypto/hisilicon/sec2/sec_main.c
index 4809c19..65bb46a 100644
--- a/drivers/crypto/hisilicon/sec2/sec_main.c
+++ b/drivers/crypto/hisilicon/sec2/sec_main.c
@@ -35,15 +35,13 @@
 #define SEC_CTX_Q_NUM_MAX  32
 
 #define SEC_CTRL_CNT_CLR_CE0x301120
-#define SEC_CTRL_CNT_CLR_CE_BITBIT(0)
-#define SEC_ENGINE_PF_CFG_OFF  0x30
-#define SEC_ACC_COMMON_REG_OFF 0x1000
+#define SEC_CTRL_CNT_CLR_CE_BITBIT(0)
 #define SEC_CORE_INT_SOURCE0x301010
 #define SEC_CORE_INT_MASK  0x301000
 #define SEC_CORE_INT_STATUS0x301008
 #define SEC_CORE_SRAM_ECC_ERR_INFO 0x301C14
-#define SEC_ECC_NUM(err)   (((err) >> 16) & 0xFF)
-#define SEC_ECC_ADDR(err)  ((err) >> 0)
+#define SEC_ECC_NUM16
+#define SEC_ECC_MASH   0xFF
 #define SEC_CORE_INT_DISABLE   0x0
 #define SEC_CORE_INT_ENABLE0x1ff
 #define SEC_CORE_INT_CLEAR 0x1ff
@@ -55,23 +53,23 @@
 #define SEC_RAS_CE_ENB_MSK 0x88
 #define SEC_RAS_FE_ENB_MSK 0x0
 #define SEC_RAS_NFE_ENB_MSK0x177
-#define SEC_RAS_DISABLE0x0
-#define SEC_MEM_START_INIT_REG 0x0100
-#define SEC_MEM_INIT_DONE_REG  0x0104
+#define SEC_RAS_DISABLE0x0
+#define SEC_MEM_START_INIT_REG 0x301100
+#define SEC_MEM_INIT_DONE_REG  0x301104
 
-#define SEC_CONTROL_REG0x0200
+#define SEC_CONTROL_REG0x301200
 #define SEC_TRNG_EN_SHIFT  8
 #define SEC_CLK_GATE_ENABLEBIT(3)
 #define SEC_CLK_GATE_DISABLE   (~BIT(3))
 #define SEC_AXI_SHUTDOWN_ENABLEBIT(12)
 #define SEC_AXI_SHUTDOWN_DISABLE   0xEFFF
 
-#define SEC_INTERFACE_USER_CTRL0_REG   0x0220
-#define SEC_INTERFACE_USER_CTRL1_REG   0x0224
-#define SEC_SAA_EN_REG 0x0270
-#define SEC_BD_ERR_CHK_EN_REG0 0x0380
-#define SEC_BD_ERR_CHK_EN_REG1 0x0384
-#define SEC_BD_ERR_CHK_EN_REG3 0x038c
+#define SEC_INTERFACE_USER_CTRL0_REG   0x301220
+#define SEC_INTERFACE_USER_CTRL1_REG   0x301224
+#define SEC_SAA_EN_REG 0x301270
+#define SEC_BD_ERR_CHK_EN_REG0 0x301380
+#define SEC_BD_ERR_CHK_EN_REG1 0x301384
+#define SEC_BD_ERR_CHK_EN_REG3 0x30138c
 
 #define SEC_USER0_SMMU_NORMAL  (BIT(23) | BIT(15))
 #define SEC_USER1_SMMU_NORMAL  (BIT(31) | BIT(23) | BIT(15) | BIT(7))
@@ -95,9 +93,6 @@
 #define SEC_SQE_MASK_OFFSET64
 #define SEC_SQE_MASK_LEN   48
 
-#define SEC_ADDR(qm, offset) ((qm)->io_base + (offset) + \
-SEC_ENGINE_PF_CFG_OFF + SEC_ACC_COMMON_REG_OFF)
-
 struct sec_hw_error {
u32 int_msk;
const char *msg;
@@ -117,16 +112,43 @@ static struct hisi_qm_list sec_devices = {
 };
 
 static const struct sec_hw_error sec_hw_errors[] = {
-   {.int_msk = BIT(0), .msg = "sec_axi_rresp_err_rint"},
-   {.int_msk = BIT(1), .msg = "sec_axi_bresp_err_rint"},
-   {.int_msk = BIT(2), .msg = "sec_ecc_2bit_err_rint"},
-   {.int_msk = BIT(3), .msg = "sec_ecc_1bit_err_rint"},
-   {.int_msk = BIT(4), .msg = "sec_req_trng_timeout_rint"},
-   {.int_msk = BIT(5), .msg = "sec_fsm_hbeat_rint"},
-   {.int_msk = BIT(6), .msg = "sec_channel_req_rng_timeout_rint"},
-   {.int_msk = BIT(7), .msg = "sec_bd_err_rint"},
-   {.int_msk = BIT(8), .msg = "sec_chain_buff_err_rint"},
-   { /* sentinel */ }
+   {
+   .int_msk = BIT(0),
+   .msg = "sec_axi_rresp_err_rint"
+   },
+   {
+   .int_msk = BIT(1),
+   .msg = "sec_axi_bresp_err_rint"
+   },
+   {
+   .int_msk = BIT(2),
+   .msg = "sec_ecc_2bit_err_rint"
+   },
+   {
+   .int_msk = BIT(3),
+   .msg = "sec_ecc_1bit_err_rint"
+   },
+   {
+   .int_msk = BIT(4),
+   .msg = "sec_req_trng_timeout_rint"
+   },
+   {
+   .int_msk = BIT(5),
+   .msg = "sec_fsm_hbeat_rint"
+   },
+   {
+   .int_msk = BIT(6),
+   .msg = "sec_channel_req_rng_timeout_rint"
+   },
+   {
+   .int_msk = BIT(7),
+   .msg = "sec_bd_err_rint"
+   },
+   {
+   .int_msk = BIT(8),
+   .msg = "sec_chain_buff_err_rint"
+   },
+   {}
 };
 
 static const char * const sec_dbg_file_name[] = {
@@ -277,9 +299,7 @@ static u8 sec_get_endian(struct hisi_qm *qm)
"cannot access a register in VF!\n");
return SEC_L

[PATCH] powerpc/uaccess: Perform barrier_nospec() in KUAP allowance helpers

[Christophe Leroy]

barrier_nospec() in uaccess helpers is there to protect against
speculative accesses around access_ok().

When using user_access_begin() sequences together with
unsafe_get_user() like macros, barrier_nospec() is called for
every single read although we know the access_ok() is done
onece.

Since all user accesses must be granted by a call to either
allow_read_from_user() or allow_read_write_user() which will
always happen after the access_ok() check, move the barrier_nospec()
there.

Reported-by: Christopher M. Riedl 
Signed-off-by: Christophe Leroy 
---
 arch/powerpc/include/asm/kup.h |  2 ++
 arch/powerpc/include/asm/uaccess.h | 12 +---
 2 files changed, 3 insertions(+), 11 deletions(-)

diff --git a/arch/powerpc/include/asm/kup.h b/arch/powerpc/include/asm/kup.h
index bf221a2a523e..7ec21af49a45 100644
--- a/arch/powerpc/include/asm/kup.h
+++ b/arch/powerpc/include/asm/kup.h
@@ -91,6 +91,7 @@ static __always_inline void setup_kup(void)
 
 static inline void allow_read_from_user(const void __user *from, unsigned long 
size)
 {
+   barrier_nospec();
allow_user_access(NULL, from, size, KUAP_READ);
 }
 
@@ -102,6 +103,7 @@ static inline void allow_write_to_user(void __user *to, 
unsigned long size)
 static inline void allow_read_write_user(void __user *to, const void __user 
*from,
 unsigned long size)
 {
+   barrier_nospec();
allow_user_access(to, from, size, KUAP_READ_WRITE);
 }
 
diff --git a/arch/powerpc/include/asm/uaccess.h 
b/arch/powerpc/include/asm/uaccess.h
index 501c9a79038c..46123ae6a4c9 100644
--- a/arch/powerpc/include/asm/uaccess.h
+++ b/arch/powerpc/include/asm/uaccess.h
@@ -315,7 +315,6 @@ do {
\
__chk_user_ptr(__gu_addr);  \
if (!is_kernel_addr((unsigned long)__gu_addr))  \
might_fault();  \
-   barrier_nospec();   \
if (do_allow)   
\
__get_user_size(__gu_val, __gu_addr, __gu_size, __gu_err);  
\
else
\
@@ -333,10 +332,8 @@ do {   
\
__typeof__(size) __gu_size = (size);\
\
might_fault();  \
-   if (access_ok(__gu_addr, __gu_size)) {  \
-   barrier_nospec();   \
+   if (access_ok(__gu_addr, __gu_size))\
__get_user_size(__gu_val, __gu_addr, __gu_size, __gu_err); \
-   }   \
(x) = (__force __typeof__(*(ptr)))__gu_val; 
\
\
__gu_err;   \
@@ -350,7 +347,6 @@ do {
\
__typeof__(size) __gu_size = (size);\
\
__chk_user_ptr(__gu_addr);  \
-   barrier_nospec();   \
__get_user_size(__gu_val, __gu_addr, __gu_size, __gu_err); \
(x) = (__force __typeof__(*(ptr)))__gu_val; \
\
@@ -395,7 +391,6 @@ raw_copy_in_user(void __user *to, const void __user *from, 
unsigned long n)
 {
unsigned long ret;
 
-   barrier_nospec();
allow_read_write_user(to, from, n);
ret = __copy_tofrom_user(to, from, n);
prevent_read_write_user(to, from, n);
@@ -412,19 +407,15 @@ static inline unsigned long raw_copy_from_user(void *to,
 
switch (n) {
case 1:
-   barrier_nospec();
__get_user_size(*(u8 *)to, from, 1, ret);
break;
case 2:
-   barrier_nospec();
__get_user_size(*(u16 *)to, from, 2, ret);
break;
case 4:
-   barrier_nospec();
__get_user_size(*(u32 *)to, from, 4, ret);
break;
case 8:
-   barrier_nospec();
__get_user_size(*(u64 *)to, from, 8, ret);
break;
}
@@ -432,7 +423,6 @@ static inline unsigned long raw_copy_from_user(void *to,
return 0;
}
 
-   barrier_nospec();
   

Re: [PATCH v2] jfs: turn diLog(), dataLog() and txLog() into void functions

[kernel test robot]

Hi Yang,

Thank you for the patch! Yet something to improve:

[auto build test ERROR on shaggy/jfs-next]
[also build test ERROR on v5.11-rc6 next-20210125]
[If your patch is applied to the wrong git tree, kindly drop us a note.
And when submitting patch, we suggest to use '--base' as documented in
https://git-scm.com/docs/git-format-patch]

url:
https://github.com/0day-ci/linux/commits/Yang-Li/jfs-turn-diLog-dataLog-and-txLog-into-void-functions/20210207-164143
base:   https://github.com/kleikamp/linux-shaggy jfs-next
config: i386-randconfig-s001-20210207 (attached as .config)
compiler: gcc-9 (Debian 9.3.0-15) 9.3.0
reproduce:
# apt-get install sparse
# sparse version: v0.6.3-215-g0fb77bb6-dirty
# 
https://github.com/0day-ci/linux/commit/1d4e3ad79325df64962835ecc11999b520ffbc80
git remote add linux-review https://github.com/0day-ci/linux
git fetch --no-tags linux-review 
Yang-Li/jfs-turn-diLog-dataLog-and-txLog-into-void-functions/20210207-164143
git checkout 1d4e3ad79325df64962835ecc11999b520ffbc80
# save the attached .config to linux build tree
make W=1 C=1 CF='-fdiagnostic-prefix -D__CHECK_ENDIAN__' ARCH=i386 

If you fix the issue, kindly add following tag as appropriate
Reported-by: kernel test robot 

All errors (new ones prefixed by >>):

   fs/jfs/jfs_txnmgr.c: In function 'txCommit':
>> fs/jfs/jfs_txnmgr.c:1259:10: error: void value not ignored as it ought to be
1259 |  if ((rc = txLog(log, tblk, &cd)))
 |  ^


vim +1259 fs/jfs/jfs_txnmgr.c

^1da177e4c3f41 Linus Torvalds2005-04-16  1084  
^1da177e4c3f41 Linus Torvalds2005-04-16  1085  /*
^1da177e4c3f41 Linus Torvalds2005-04-16  1086   *   transaction 
commit management
^1da177e4c3f41 Linus Torvalds2005-04-16  1087   *   
-
^1da177e4c3f41 Linus Torvalds2005-04-16  1088   */
^1da177e4c3f41 Linus Torvalds2005-04-16  1089  
^1da177e4c3f41 Linus Torvalds2005-04-16  1090  /*
^1da177e4c3f41 Linus Torvalds2005-04-16  1091   * NAME: txCommit()
^1da177e4c3f41 Linus Torvalds2005-04-16  1092   *
^1da177e4c3f41 Linus Torvalds2005-04-16  1093   * FUNCTION: commit the 
changes to the objects specified in
^1da177e4c3f41 Linus Torvalds2005-04-16  1094   *   clist.  For 
journalled segments only the
^1da177e4c3f41 Linus Torvalds2005-04-16  1095   *   changes of the 
caller are committed, ie by tid.
^1da177e4c3f41 Linus Torvalds2005-04-16  1096   *   for 
non-journalled segments the data are flushed to
^1da177e4c3f41 Linus Torvalds2005-04-16  1097   *   disk and then 
the change to the disk inode and indirect
^1da177e4c3f41 Linus Torvalds2005-04-16  1098   *   blocks 
committed (so blocks newly allocated to the
^1da177e4c3f41 Linus Torvalds2005-04-16  1099   *   segment will be 
made a part of the segment atomically).
^1da177e4c3f41 Linus Torvalds2005-04-16  1100   *
^1da177e4c3f41 Linus Torvalds2005-04-16  1101   *   all of the 
segments specified in clist must be in
^1da177e4c3f41 Linus Torvalds2005-04-16  1102   *   one file 
system. no more than 6 segments are needed
^1da177e4c3f41 Linus Torvalds2005-04-16  1103   *   to handle all 
unix svcs.
^1da177e4c3f41 Linus Torvalds2005-04-16  1104   *
^1da177e4c3f41 Linus Torvalds2005-04-16  1105   *   if the i_nlink 
field (i.e. disk inode link count)
^1da177e4c3f41 Linus Torvalds2005-04-16  1106   *   is zero, and 
the type of inode is a regular file or
^1da177e4c3f41 Linus Torvalds2005-04-16  1107   *   directory, or 
symbolic link , the inode is truncated
^1da177e4c3f41 Linus Torvalds2005-04-16  1108   *   to zero length. 
the truncation is committed but the
^1da177e4c3f41 Linus Torvalds2005-04-16  1109   *   VM resources 
are unaffected until it is closed (see
^1da177e4c3f41 Linus Torvalds2005-04-16  1110   *   iput and 
iclose).
^1da177e4c3f41 Linus Torvalds2005-04-16     *
^1da177e4c3f41 Linus Torvalds2005-04-16  1112   * PARAMETER:
^1da177e4c3f41 Linus Torvalds2005-04-16  1113   *
^1da177e4c3f41 Linus Torvalds2005-04-16  1114   * RETURN:
^1da177e4c3f41 Linus Torvalds2005-04-16  1115   *
^1da177e4c3f41 Linus Torvalds2005-04-16  1116   * serialization:
^1da177e4c3f41 Linus Torvalds2005-04-16  1117   *   on entry the 
inode lock on each segment is assumed
^1da177e4c3f41 Linus Torvalds2005-04-16  1118   *   to be held.
^1da177e4c3f41 Linus Torvalds2005-04-16  1119   *
^1da177e4c3f41 Linus Torvalds2005-04-16  1120   * i/o error:
^1da177e4c3f41 Linus Torvalds2005-04-16  1121   */
^1da177e4c3f41 Linus Torvalds2005-04-16  1122  int txCommit(tid_t tid,  
/* transaction identifier */
^1da177e4c3f41 Linus Torvalds2005-04-16  1123

Re: [PATCH] Input: synaptic - reverting dcb00fc799dc03fd320e123e4c81b3278c763ea5 because it breaks the touchpad for one guy on Reddit.

[Hans de Goede]

Hi,

On 2/7/21 4:50 AM, Colton Booth wrote:
> I can't test myself since I don't have the correct hardware, BUT this change 
> seems to work for him. I'm thinking he has an early version of the X1E which 
> may use slightly different trackpad revision.

Who is "him"? Do you have a bug-report link or some such ?

With which kernel version is this ?  Could it be that the commit you are 
reverting was
backported to a stable-series release while that stable series is missing the 
rmi4
updates necessary to make things work on newer models ?

What are the symptoms / problems "him" is seeing when not reverting this?

On case it is not clear: NACK due to insufficient information why this is
necessary / missing description and root cause analysis of the actual problem.

Regards,

Hans


> 
> Signed-off-by: Colton Booth 
> ---
>  drivers/input/mouse/synaptics.c | 2 --
>  1 file changed, 2 deletions(-)
> 
> diff --git a/drivers/input/mouse/synaptics.c b/drivers/input/mouse/synaptics.c
> index ffad142801b3..2d3f03921dbc 100644
> --- a/drivers/input/mouse/synaptics.c
> +++ b/drivers/input/mouse/synaptics.c
> @@ -179,9 +179,7 @@ static const char * const smbus_pnp_ids[] = {
>   "LEN0093", /* T480 */
>   "LEN0096", /* X280 */
>   "LEN0097", /* X280 -> ALPS trackpoint */
> - "LEN0099", /* X1 Extreme Gen 1 / P1 Gen 1 */
>   "LEN009b", /* T580 */
> - "LEN0402", /* X1 Extreme Gen 2 / P1 Gen 2 */
>   "LEN200f", /* T450s */
>   "LEN2044", /* L470  */
>   "LEN2054", /* E480 */
> 

Re: [PATCH v6 2/4] soc: qcom: Add SoC sleep stats driver

[kernel test robot]

Hi Maulik,

Thank you for the patch! Yet something to improve:

[auto build test ERROR on robh/for-next]
[also build test ERROR on arm64/for-next/core linux/master linus/master 
v5.11-rc6 next-20210125]
[If your patch is applied to the wrong git tree, kindly drop us a note.
And when submitting patch, we suggest to use '--base' as documented in
https://git-scm.com/docs/git-format-patch]

url:
https://github.com/0day-ci/linux/commits/Maulik-Shah/Introduce-SoC-sleep-stats-driver/20210204-223344
base:   https://git.kernel.org/pub/scm/linux/kernel/git/robh/linux.git for-next
config: h8300-randconfig-r013-20210207 (attached as .config)
compiler: h8300-linux-gcc (GCC) 9.3.0
reproduce (this is a W=1 build):
wget 
https://raw.githubusercontent.com/intel/lkp-tests/master/sbin/make.cross -O 
~/bin/make.cross
chmod +x ~/bin/make.cross
# 
https://github.com/0day-ci/linux/commit/60e8c659b52a5c1ac2b1a91d02df00ddecdccba8
git remote add linux-review https://github.com/0day-ci/linux
git fetch --no-tags linux-review 
Maulik-Shah/Introduce-SoC-sleep-stats-driver/20210204-223344
git checkout 60e8c659b52a5c1ac2b1a91d02df00ddecdccba8
# save the attached .config to linux build tree
COMPILER_INSTALL_PATH=$HOME/0day COMPILER=gcc-9.3.0 make.cross 
ARCH=h8300 

If you fix the issue, kindly add following tag as appropriate
Reported-by: kernel test robot 

All errors (new ones prefixed by >>):

   drivers/soc/qcom/soc_sleep_stats.c: In function 'soc_sleep_stats_show':
>> drivers/soc/qcom/soc_sleep_stats.c:113:25: error: implicit declaration of 
>> function 'readq'; did you mean 'readl'? 
>> [-Werror=implicit-function-declaration]
 113 |  stat.last_entered_at = readq(reg + LAST_ENTERED_AT_ADDR);
 | ^
 | readl
   cc1: some warnings being treated as errors


vim +113 drivers/soc/qcom/soc_sleep_stats.c

   105  
   106  static int soc_sleep_stats_show(struct seq_file *s, void *d)
   107  {
   108  struct stats_prv_data *prv_data = s->private;
   109  void __iomem *reg = prv_data->reg;
   110  struct sleep_stats stat;
   111  
   112  stat.count = readl(reg + COUNT_ADDR);
 > 113  stat.last_entered_at = readq(reg + LAST_ENTERED_AT_ADDR);
   114  stat.last_exited_at = readq(reg + LAST_EXITED_AT_ADDR);
   115  stat.accumulated = readq(reg + ACCUMULATED_ADDR);
   116  
   117  print_sleep_stats(s, &stat);
   118  
   119  if (prv_data->appended_stats_avail) {
   120  struct appended_stats app_stat;
   121  
   122  app_stat.client_votes = readl(reg + CLIENT_VOTES_ADDR);
   123  seq_printf(s, "Client_votes = %#x\n", 
app_stat.client_votes);
   124  }
   125  
   126  return 0;
   127  }
   128  

---
0-DAY CI Kernel Test Service, Intel Corporation
https://lists.01.org/hyperkitty/list/kbuild-...@lists.01.org


.config.gz
Description: application/gzip

Re: [PATCH] I was wondering why I can't set the resolution to 2560x1080, while in windows 7 I can without a problem. I looked at the radeon driver code and found it doesn't support this resolution. So

[Willy Tarreau]

Hello,

On Sun, Feb 07, 2021 at 10:46:04AM +0100, Marcin Raszka wrote:
> ---
>  drivers/gpu/drm/radeon/radeon_benchmark.c  |  5 ++--
>  drivers/gpu/drm/radeon/radeon_connectors.c | 30 ++
>  drivers/gpu/drm/radeon/radeon_drv.c|  5 
>  drivers/gpu/drm/radeon/radeon_encoders.c   |  6 +++--
>  4 files changed, 32 insertions(+), 14 deletions(-)
> 
> diff --git a/drivers/gpu/drm/radeon/radeon_benchmark.c 
> b/drivers/gpu/drm/radeon/radeon_benchmark.c
(...)

Please have a look at Documentation/process/submitting-patches.rst to
see how to reformat your patch so that it contains a descriptive commit
message.

Thanks,
Willy

Re: [PATCH] Input: synaptic - reverting dcb00fc799dc03fd320e123e4c81b3278c763ea5 because it breaks the touchpad for one guy on Reddit.

[Hans de Goede]

Hi,

On 2/7/21 11:18 AM, Hans de Goede wrote:
> Hi,
> 
> On 2/7/21 4:50 AM, Colton Booth wrote:
>> I can't test myself since I don't have the correct hardware, BUT this change 
>> seems to work for him. I'm thinking he has an early version of the X1E which 
>> may use slightly different trackpad revision.
> 
> Who is "him"? Do you have a bug-report link or some such ?
> 
> With which kernel version is this ?  Could it be that the commit you are 
> reverting was
> backported to a stable-series release while that stable series is missing the 
> rmi4
> updates necessary to make things work on newer models ?
> 
> What are the symptoms / problems "him" is seeing when not reverting this?
> 
> On case it is not clear: NACK due to insufficient information why this is
> necessary / missing description and root cause analysis of the actual problem.

p.s.

My apologies if this sounds a bit grumpy, I got out of bed on the wrong side 
this morning.

Regards,

Hans





> 
> Regards,
> 
> Hans
> 
> 
>>
>> Signed-off-by: Colton Booth 
>> ---
>>  drivers/input/mouse/synaptics.c | 2 --
>>  1 file changed, 2 deletions(-)
>>
>> diff --git a/drivers/input/mouse/synaptics.c 
>> b/drivers/input/mouse/synaptics.c
>> index ffad142801b3..2d3f03921dbc 100644
>> --- a/drivers/input/mouse/synaptics.c
>> +++ b/drivers/input/mouse/synaptics.c
>> @@ -179,9 +179,7 @@ static const char * const smbus_pnp_ids[] = {
>>  "LEN0093", /* T480 */
>>  "LEN0096", /* X280 */
>>  "LEN0097", /* X280 -> ALPS trackpoint */
>> -"LEN0099", /* X1 Extreme Gen 1 / P1 Gen 1 */
>>  "LEN009b", /* T580 */
>> -"LEN0402", /* X1 Extreme Gen 2 / P1 Gen 2 */
>>  "LEN200f", /* T450s */
>>  "LEN2044", /* L470  */
>>  "LEN2054", /* E480 */
>>

[PATCH v2 0/7] Add audio driver base on rpmsg on i.MX platform

[Shengjiu Wang]

On Asymmetric multiprocessor, there is Cortex-A core and Cortex-M core,
Linux is running on A core, RTOS is running on M core.
The audio hardware device can be controlled by Cortex-M device,
So audio playback/capture can be handled by M core.

Rpmsg is the interface for sending and receiving msg to and from M
core, that we can create a virtual sound on Cortex-A core side.

A core will tell the Cortex-M core sound format/rate/channel,
where is the data buffer, what is the period size, when to start,
when to stop and when suspend or resume happen, each of this behavior
there is defined rpmsg command.

Especially we designed the low power audio case, that is to
allocate a large buffer and fill the data, then Cortex-A core can go
to sleep mode, Cortex-M core continue to play the sound, when the
buffer is consumed, Cortex-M core will trigger the Cortex-A core to
wakeup to fill data.

changes in v2:
- update codes and comments according to Mark's comments

Shengjiu Wang (7):
  ASoC: soc-component: Add snd_soc_pcm_component_ack
  ASoC: fsl_rpmsg: Add CPU DAI driver for audio base on rpmsg
  ASoC: dt-bindings: fsl_rpmsg: Add binding doc for rpmsg cpu dai driver
  ASoC: imx-audio-rpmsg: Add rpmsg_driver for audio channel
  ASoC: imx-pcm-rpmsg: Add platform driver for audio base on rpmsg
  ASoC: imx-rpmsg: Add machine driver for audio base on rpmsg
  ASoC: dt-bindings: imx-rpmsg: Add binding doc for rpmsg machine driver

 .../devicetree/bindings/sound/fsl,rpmsg.yaml  |  80 ++
 .../bindings/sound/imx-audio-rpmsg.yaml   |  48 +
 include/sound/soc-component.h |   3 +
 sound/soc/fsl/Kconfig |  28 +
 sound/soc/fsl/Makefile|   6 +
 sound/soc/fsl/fsl_rpmsg.c | 252 +
 sound/soc/fsl/fsl_rpmsg.h |  38 +
 sound/soc/fsl/imx-audio-rpmsg.c   | 151 +++
 sound/soc/fsl/imx-pcm-rpmsg.c | 919 ++
 sound/soc/fsl/imx-pcm-rpmsg.h | 512 ++
 sound/soc/fsl/imx-rpmsg.c | 148 +++
 sound/soc/soc-component.c |  14 +
 sound/soc/soc-pcm.c   |   2 +
 13 files changed, 2201 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/sound/fsl,rpmsg.yaml
 create mode 100644 Documentation/devicetree/bindings/sound/imx-audio-rpmsg.yaml
 create mode 100644 sound/soc/fsl/fsl_rpmsg.c
 create mode 100644 sound/soc/fsl/fsl_rpmsg.h
 create mode 100644 sound/soc/fsl/imx-audio-rpmsg.c
 create mode 100644 sound/soc/fsl/imx-pcm-rpmsg.c
 create mode 100644 sound/soc/fsl/imx-pcm-rpmsg.h
 create mode 100644 sound/soc/fsl/imx-rpmsg.c

-- 
2.27.0

[PATCH v2 3/7] ASoC: dt-bindings: fsl_rpmsg: Add binding doc for rpmsg cpu dai driver

[Shengjiu Wang]

fsl_rpmsg cpu dai driver is driver for rpmsg audio, which is mainly used
for getting the user's configuration from device tree and configure the
clocks which is used by Cortex-M core. So in this document define the
needed property.

Signed-off-by: Shengjiu Wang 
---
 .../devicetree/bindings/sound/fsl,rpmsg.yaml  | 80 +++
 1 file changed, 80 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/sound/fsl,rpmsg.yaml

diff --git a/Documentation/devicetree/bindings/sound/fsl,rpmsg.yaml 
b/Documentation/devicetree/bindings/sound/fsl,rpmsg.yaml
new file mode 100644
index ..2d3ce10d42fc
--- /dev/null
+++ b/Documentation/devicetree/bindings/sound/fsl,rpmsg.yaml
@@ -0,0 +1,80 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/sound/fsl,rpmsg.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: NXP Audio RPMSG CPU DAI Controller
+
+maintainers:
+  - Shengjiu Wang 
+
+properties:
+  compatible:
+enum:
+  - fsl,imx7ulp-rpmsg
+  - fsl,imx8mn-rpmsg
+  - fsl,imx8mm-rpmsg
+  - fsl,imx8mp-rpmsg
+
+  clocks:
+items:
+  - description: Peripheral clock for register access
+  - description: Master clock
+  - description: DMA clock for DMA register access
+  - description: Parent clock for multiple of 8kHz sample rates
+  - description: Parent clock for multiple of 11kHz sample rates
+minItems: 5
+
+  clock-names:
+items:
+  - const: ipg
+  - const: mclk
+  - const: dma
+  - const: pll8k
+  - const: pll11k
+minItems: 5
+
+  power-domains:
+maxItems: 1
+
+  fsl,audioindex:
+$ref: /schemas/types.yaml#/definitions/uint32
+description: instance index for rpmsg image
+
+  fsl,version:
+$ref: /schemas/types.yaml#/definitions/uint32
+description: rpmsg image version index
+
+  fsl,buffer-size:
+$ref: /schemas/types.yaml#/definitions/uint32
+description: pre allocate dma buffer size
+
+  fsl,enable-lpa:
+$ref: /schemas/types.yaml#/definitions/flag
+description: enable low power audio path.
+
+  fsl,codec-type:
+$ref: /schemas/types.yaml#/definitions/uint32
+description: Sometimes the codec is registered by
+ driver not the device tree, this items
+ can be used to distinguish codecs
+
+required:
+  - compatible
+  - fsl,audioindex
+  - fsl,version
+  - fsl,buffer-size
+
+additionalProperties: false
+
+examples:
+  - |
+rpmsg_audio: rpmsg_audio {
+compatible = "fsl,imx8mn-rpmsg";
+fsl,audioindex = <0> ;
+fsl,version = <2>;
+fsl,buffer-size = <0x600>;
+fsl,enable-lpa;
+status = "okay";
+};
-- 
2.27.0

[PATCH v2 2/7] ASoC: fsl_rpmsg: Add CPU DAI driver for audio base on rpmsg

[Shengjiu Wang]

This is a cpu dai driver for rpmsg audio use case,
which is mainly used for getting the user's configuration
from devicetree and configure the clocks which is used by
Cortex-M core.

Signed-off-by: Shengjiu Wang 
---
 sound/soc/fsl/Kconfig |   7 ++
 sound/soc/fsl/Makefile|   2 +
 sound/soc/fsl/fsl_rpmsg.c | 252 ++
 sound/soc/fsl/fsl_rpmsg.h |  38 ++
 4 files changed, 299 insertions(+)
 create mode 100644 sound/soc/fsl/fsl_rpmsg.c
 create mode 100644 sound/soc/fsl/fsl_rpmsg.h

diff --git a/sound/soc/fsl/Kconfig b/sound/soc/fsl/Kconfig
index d7f30036d434..a688c3c2efbc 100644
--- a/sound/soc/fsl/Kconfig
+++ b/sound/soc/fsl/Kconfig
@@ -115,6 +115,13 @@ config SND_SOC_FSL_AUD2HTX
 config SND_SOC_FSL_UTILS
tristate
 
+config SND_SOC_FSL_RPMSG
+   tristate "Audio Base on RPMSG support"
+   help
+ Say Y if you want to add rpmsg audio support for the Freescale CPUs.
+ This option is only useful for out-of-tree drivers since
+ in-tree drivers select it automatically.
+
 config SND_SOC_IMX_PCM_DMA
tristate
select SND_SOC_GENERIC_DMAENGINE_PCM
diff --git a/sound/soc/fsl/Makefile b/sound/soc/fsl/Makefile
index 8c5fa8a859c0..b63802f345cc 100644
--- a/sound/soc/fsl/Makefile
+++ b/sound/soc/fsl/Makefile
@@ -27,6 +27,7 @@ snd-soc-fsl-mqs-objs := fsl_mqs.o
 snd-soc-fsl-easrc-objs := fsl_easrc.o
 snd-soc-fsl-xcvr-objs := fsl_xcvr.o
 snd-soc-fsl-aud2htx-objs := fsl_aud2htx.o
+snd-soc-fsl-rpmsg-objs := fsl_rpmsg.o
 
 obj-$(CONFIG_SND_SOC_FSL_AUDMIX) += snd-soc-fsl-audmix.o
 obj-$(CONFIG_SND_SOC_FSL_ASOC_CARD) += snd-soc-fsl-asoc-card.o
@@ -42,6 +43,7 @@ obj-$(CONFIG_SND_SOC_FSL_EASRC) += snd-soc-fsl-easrc.o
 obj-$(CONFIG_SND_SOC_POWERPC_DMA) += snd-soc-fsl-dma.o
 obj-$(CONFIG_SND_SOC_FSL_XCVR) += snd-soc-fsl-xcvr.o
 obj-$(CONFIG_SND_SOC_FSL_AUD2HTX) += snd-soc-fsl-aud2htx.o
+obj-$(CONFIG_SND_SOC_FSL_RPMSG) += snd-soc-fsl-rpmsg.o
 
 # MPC5200 Platform Support
 obj-$(CONFIG_SND_MPC52xx_DMA) += mpc5200_dma.o
diff --git a/sound/soc/fsl/fsl_rpmsg.c b/sound/soc/fsl/fsl_rpmsg.c
new file mode 100644
index ..6e218344df0d
--- /dev/null
+++ b/sound/soc/fsl/fsl_rpmsg.c
@@ -0,0 +1,252 @@
+// SPDX-License-Identifier: GPL-2.0+
+// Copyright 2018-2021 NXP
+
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+#include "fsl_rpmsg.h"
+#include "imx-pcm.h"
+
+#define FSL_RPMSG_RATES(SNDRV_PCM_RATE_8000 | \
+   SNDRV_PCM_RATE_16000 | \
+   SNDRV_PCM_RATE_48000)
+#define FSL_RPMSG_FORMATS  SNDRV_PCM_FMTBIT_S16_LE
+
+static const unsigned int fsl_rpmsg_rates[] = {
+   8000, 11025, 16000, 22050, 44100,
+   32000, 48000, 96000, 88200, 176400, 192000,
+   352800, 384000, 705600, 768000, 1411200, 2822400,
+};
+
+static const struct snd_pcm_hw_constraint_list fsl_rpmsg_rate_constraints = {
+   .count = ARRAY_SIZE(fsl_rpmsg_rates),
+   .list = fsl_rpmsg_rates,
+};
+
+static int fsl_rpmsg_hw_params(struct snd_pcm_substream *substream,
+  struct snd_pcm_hw_params *params,
+  struct snd_soc_dai *dai)
+{
+   struct fsl_rpmsg *rpmsg = snd_soc_dai_get_drvdata(dai);
+   struct clk *p = rpmsg->mclk, *pll = 0, *npll = 0;
+   unsigned int rate = params_rate(params);
+   int ret;
+
+   /* Get current pll parent */
+   while (p && rpmsg->pll8k && rpmsg->pll11k) {
+   struct clk *pp = clk_get_parent(p);
+
+   if (clk_is_match(pp, rpmsg->pll8k) ||
+   clk_is_match(pp, rpmsg->pll11k)) {
+   pll = pp;
+   break;
+   }
+   p = pp;
+   }
+
+   /* Switch to another pll parent if needed. */
+   if (pll) {
+   npll = (do_div(rate, 8000) ? rpmsg->pll11k : rpmsg->pll8k);
+   if (!clk_is_match(pll, npll)) {
+   ret = clk_set_parent(p, npll);
+   if (ret < 0)
+   dev_warn(dai->dev, "failed to set parent %s: 
%d\n",
+__clk_get_name(npll), ret);
+   }
+   }
+
+   ret = clk_prepare_enable(rpmsg->mclk);
+   if (ret)
+   dev_err(dai->dev, "failed to enable mclk: %d\n", ret);
+
+   return ret;
+}
+
+static int fsl_rpmsg_hw_free(struct snd_pcm_substream *substream,
+struct snd_soc_dai *dai)
+{
+   struct fsl_rpmsg *rpmsg = snd_soc_dai_get_drvdata(dai);
+
+   clk_disable_unprepare(rpmsg->mclk);
+
+   return 0;
+}
+
+static int fsl_rpmsg_startup(struct snd_pcm_substream *substream,
+struct snd_soc_dai *cpu_dai)
+{
+   int ret;
+
+   ret = snd_pcm_hw_constraint_list(substream->runtime, 0,
+SNDRV_PCM_HW_PARAM_RATE,
+   

[PATCH v2 4/7] ASoC: imx-audio-rpmsg: Add rpmsg_driver for audio channel

[Shengjiu Wang]

This driver is used to accept the message from rpmsg audio
channel, and if this driver is probed, it will help to register
the platform driver, the platform driver will use this
audio channel to send and receive message to and from Cortex-M
core.

Signed-off-by: Shengjiu Wang 
---
 sound/soc/fsl/Kconfig   |   4 +
 sound/soc/fsl/Makefile  |   1 +
 sound/soc/fsl/imx-audio-rpmsg.c | 151 
 3 files changed, 156 insertions(+)
 create mode 100644 sound/soc/fsl/imx-audio-rpmsg.c

diff --git a/sound/soc/fsl/Kconfig b/sound/soc/fsl/Kconfig
index a688c3c2efbc..84d9f0f1f75b 100644
--- a/sound/soc/fsl/Kconfig
+++ b/sound/soc/fsl/Kconfig
@@ -126,6 +126,10 @@ config SND_SOC_IMX_PCM_DMA
tristate
select SND_SOC_GENERIC_DMAENGINE_PCM
 
+config SND_SOC_IMX_AUDIO_RPMSG
+   tristate
+   depends on RPMSG
+
 config SND_SOC_IMX_AUDMUX
tristate "Digital Audio Mux module support"
help
diff --git a/sound/soc/fsl/Makefile b/sound/soc/fsl/Makefile
index b63802f345cc..f08f3cd07ff5 100644
--- a/sound/soc/fsl/Makefile
+++ b/sound/soc/fsl/Makefile
@@ -60,6 +60,7 @@ obj-$(CONFIG_SND_SOC_IMX_AUDMUX) += snd-soc-imx-audmux.o
 
 obj-$(CONFIG_SND_SOC_IMX_PCM_FIQ) += imx-pcm-fiq.o
 obj-$(CONFIG_SND_SOC_IMX_PCM_DMA) += imx-pcm-dma.o
+obj-$(CONFIG_SND_SOC_IMX_AUDIO_RPMSG) += imx-audio-rpmsg.o
 
 # i.MX Machine Support
 snd-soc-eukrea-tlv320-objs := eukrea-tlv320.o
diff --git a/sound/soc/fsl/imx-audio-rpmsg.c b/sound/soc/fsl/imx-audio-rpmsg.c
new file mode 100644
index ..145edb1492b4
--- /dev/null
+++ b/sound/soc/fsl/imx-audio-rpmsg.c
@@ -0,0 +1,151 @@
+// SPDX-License-Identifier: GPL-2.0+
+// Copyright 2017-2020 NXP
+
+#include 
+#include 
+#include "imx-pcm-rpmsg.h"
+
+/*
+ * struct imx_audio_rpmsg: private data
+ *
+ * @rpmsg_pdev: pointer of platform device
+ */
+struct imx_audio_rpmsg {
+   struct platform_device *rpmsg_pdev;
+};
+
+static int imx_audio_rpmsg_cb(struct rpmsg_device *rpdev, void *data, int len,
+ void *priv, u32 src)
+{
+   struct imx_audio_rpmsg *rpmsg = dev_get_drvdata(&rpdev->dev);
+   struct rpmsg_info *info = platform_get_drvdata(rpmsg->rpmsg_pdev);
+   struct rpmsg_r_msg *r_msg = (struct rpmsg_r_msg *)data;
+   struct rpmsg_msg *msg;
+   unsigned long flags;
+
+   dev_dbg(&rpdev->dev, "get from%d: cmd:%d. %d\n",
+   src, r_msg->header.cmd, r_msg->param.resp);
+
+   switch (r_msg->header.type) {
+   case MSG_TYPE_C:
+   /* TYPE C is notification from M core */
+   switch (r_msg->header.cmd) {
+   case TX_PERIOD_DONE:
+   spin_lock_irqsave(&info->lock[TX], flags);
+   msg = &info->msg[TX_PERIOD_DONE + MSG_TYPE_A_NUM];
+
+   /*
+* Low power mode: get the buffer pointer from
+* receive msg.
+*/
+   if (r_msg->header.major == 1 &&
+   r_msg->header.minor == 2)
+   msg->r_msg.param.buffer_tail =
+   r_msg->param.buffer_tail;
+   else
+   msg->r_msg.param.buffer_tail++;
+
+   msg->r_msg.param.buffer_tail %= info->num_period[TX];
+   spin_unlock_irqrestore(&info->lock[TX], flags);
+   info->callback[TX](info->callback_param[TX]);
+   break;
+   case RX_PERIOD_DONE:
+   spin_lock_irqsave(&info->lock[RX], flags);
+   msg = &info->msg[RX_PERIOD_DONE + MSG_TYPE_A_NUM];
+
+   if (r_msg->header.major == 1 &&
+   r_msg->header.minor == 2)
+   msg->r_msg.param.buffer_tail =
+   r_msg->param.buffer_tail;
+   else
+   msg->r_msg.param.buffer_tail++;
+
+   msg->r_msg.param.buffer_tail %= info->num_period[1];
+   spin_unlock_irqrestore(&info->lock[RX], flags);
+   info->callback[RX](info->callback_param[RX]);
+   break;
+   default:
+   dev_warn(&rpdev->dev, "unknown msg command\n");
+   break;
+   }
+   break;
+   case MSG_TYPE_B:
+   /* TYPE B is response msg */
+   memcpy(&info->r_msg, r_msg, sizeof(struct rpmsg_r_msg));
+   complete(&info->cmd_complete);
+   break;
+   default:
+   dev_warn(&rpdev->dev, "unknown msg type\n");
+   break;
+   }
+
+   return 0;
+}
+
+static int imx_audio_rpmsg_probe(struct rpmsg_device *rpdev)
+{
+   struct imx_audio_rpmsg *data;
+   int ret = 0;
+
+   dev_info(&rpdev

[PATCH v2 6/7] ASoC: imx-rpmsg: Add machine driver for audio base on rpmsg

[Shengjiu Wang]

The platform device is not registered by device tree or
cpu dai driver, it is registered by the rpmsg channel,
So add a dedicated machine driver to handle this case.

Signed-off-by: Shengjiu Wang 
---
 sound/soc/fsl/Kconfig |  12 
 sound/soc/fsl/Makefile|   2 +
 sound/soc/fsl/imx-rpmsg.c | 148 ++
 3 files changed, 162 insertions(+)
 create mode 100644 sound/soc/fsl/imx-rpmsg.c

diff --git a/sound/soc/fsl/Kconfig b/sound/soc/fsl/Kconfig
index 749c44fc0759..3557866d3fa2 100644
--- a/sound/soc/fsl/Kconfig
+++ b/sound/soc/fsl/Kconfig
@@ -334,6 +334,18 @@ config SND_SOC_IMX_HDMI
  Say Y if you want to add support for SoC audio on an i.MX board with
  IMX HDMI.
 
+config SND_SOC_IMX_RPMSG
+   tristate "SoC Audio support for i.MX boards with rpmsg"
+   depends on RPMSG
+   select SND_SOC_IMX_PCM_RPMSG
+   select SND_SOC_IMX_AUDIO_RPMSG
+   select SND_SOC_FSL_RPMSG
+   help
+ SoC Audio support for i.MX boards with rpmsg.
+ There should be rpmsg devices defined in other core (M core)
+ Say Y if you want to add support for SoC audio on an i.MX board with
+ a rpmsg devices.
+
 endif # SND_IMX_SOC
 
 endmenu
diff --git a/sound/soc/fsl/Makefile b/sound/soc/fsl/Makefile
index ce4f4324c3a2..f146ce464acd 100644
--- a/sound/soc/fsl/Makefile
+++ b/sound/soc/fsl/Makefile
@@ -70,6 +70,7 @@ snd-soc-imx-sgtl5000-objs := imx-sgtl5000.o
 snd-soc-imx-spdif-objs := imx-spdif.o
 snd-soc-imx-audmix-objs := imx-audmix.o
 snd-soc-imx-hdmi-objs := imx-hdmi.o
+snd-soc-imx-rpmsg-objs := imx-rpmsg.o
 
 obj-$(CONFIG_SND_SOC_EUKREA_TLV320) += snd-soc-eukrea-tlv320.o
 obj-$(CONFIG_SND_SOC_IMX_ES8328) += snd-soc-imx-es8328.o
@@ -77,3 +78,4 @@ obj-$(CONFIG_SND_SOC_IMX_SGTL5000) += snd-soc-imx-sgtl5000.o
 obj-$(CONFIG_SND_SOC_IMX_SPDIF) += snd-soc-imx-spdif.o
 obj-$(CONFIG_SND_SOC_IMX_AUDMIX) += snd-soc-imx-audmix.o
 obj-$(CONFIG_SND_SOC_IMX_HDMI) += snd-soc-imx-hdmi.o
+obj-$(CONFIG_SND_SOC_IMX_RPMSG) += snd-soc-imx-rpmsg.o
diff --git a/sound/soc/fsl/imx-rpmsg.c b/sound/soc/fsl/imx-rpmsg.c
new file mode 100644
index ..a87dcbce4f36
--- /dev/null
+++ b/sound/soc/fsl/imx-rpmsg.c
@@ -0,0 +1,148 @@
+// SPDX-License-Identifier: GPL-2.0+
+// Copyright 2017-2020 NXP
+
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include "imx-pcm-rpmsg.h"
+
+struct imx_rpmsg {
+   struct snd_soc_dai_link dai;
+   struct snd_soc_card card;
+};
+
+static int imx_rpmsg_probe(struct platform_device *pdev)
+{
+   struct snd_soc_dai_link_component *dlc;
+   struct platform_device *cpu_pdev;
+   struct of_phandle_args args;
+   struct device_node *cpu_np;
+   struct imx_rpmsg *data;
+   int ret;
+
+   dlc = devm_kzalloc(&pdev->dev, 3 * sizeof(*dlc), GFP_KERNEL);
+   if (!dlc)
+   return -ENOMEM;
+
+   cpu_np = of_parse_phandle(pdev->dev.of_node, "audio-cpu", 0);
+   if (!cpu_np) {
+   dev_err(&pdev->dev, "cpu dai phandle missing or invalid\n");
+   ret = -EINVAL;
+   goto fail;
+   }
+
+   data = devm_kzalloc(&pdev->dev, sizeof(*data), GFP_KERNEL);
+   if (!data) {
+   ret = -ENOMEM;
+   goto fail;
+   }
+
+   cpu_pdev = of_find_device_by_node(cpu_np);
+   if (!cpu_pdev) {
+   dev_err(&pdev->dev, "failed to find rpmsg platform device\n");
+   ret = -EINVAL;
+   goto fail;
+   }
+
+   ret = of_reserved_mem_device_init_by_idx(&pdev->dev, pdev->dev.of_node, 
0);
+   if (ret)
+   dev_warn(&pdev->dev, "no reserved DMA memory\n");
+
+   data->dai.cpus = &dlc[0];
+   data->dai.num_cpus = 1;
+   data->dai.platforms = &dlc[1];
+   data->dai.num_platforms = 1;
+   data->dai.codecs = &dlc[2];
+   data->dai.num_codecs = 1;
+
+   data->dai.name = "rpmsg hifi";
+   data->dai.stream_name = "rpmsg hifi";
+   data->dai.dai_fmt = SND_SOC_DAIFMT_I2S |
+   SND_SOC_DAIFMT_NB_NF |
+   SND_SOC_DAIFMT_CBS_CFS;
+
+   /* Optional codec node */
+   ret = of_parse_phandle_with_fixed_args(pdev->dev.of_node,
+  "audio-codec", 0, 0, &args);
+   if (ret) {
+   data->dai.codecs->dai_name = "snd-soc-dummy-dai";
+   data->dai.codecs->name = "snd-soc-dummy";
+   } else {
+   data->dai.codecs->of_node = args.np;
+   ret = snd_soc_get_dai_name(&args, &data->dai.codecs->dai_name);
+   if (ret) {
+   dev_err(&pdev->dev, "Unable to get codec_dai_name\n");
+   goto fail;
+   }
+   }
+
+   data->dai.cpus->dai_name = dev_name(&cpu_pdev->dev);
+   data->dai.platforms->name = IMX_PCM_DRV_NAME;
+   data->dai.playback_only = true;

[PATCH v2 1/7] ASoC: soc-component: Add snd_soc_pcm_component_ack

[Shengjiu Wang]

Add snd_soc_pcm_component_ack back, which can be used to get updated
buffer pointer in platform driver.
On Asymmetric multiprocessor, this pointer can be sent to Cortex-M
core for audio processing.

Signed-off-by: Shengjiu Wang 
---
 include/sound/soc-component.h |  3 +++
 sound/soc/soc-component.c | 14 ++
 sound/soc/soc-pcm.c   |  2 ++
 3 files changed, 19 insertions(+)

diff --git a/include/sound/soc-component.h b/include/sound/soc-component.h
index 5b47768222b7..2dc8c7e3d1a6 100644
--- a/include/sound/soc-component.h
+++ b/include/sound/soc-component.h
@@ -146,6 +146,8 @@ struct snd_soc_component_driver {
int (*mmap)(struct snd_soc_component *component,
struct snd_pcm_substream *substream,
struct vm_area_struct *vma);
+   int (*ack)(struct snd_soc_component *component,
+  struct snd_pcm_substream *substream);
 
const struct snd_compress_ops *compress_ops;
 
@@ -498,5 +500,6 @@ int snd_soc_pcm_component_pm_runtime_get(struct 
snd_soc_pcm_runtime *rtd,
 void *stream);
 void snd_soc_pcm_component_pm_runtime_put(struct snd_soc_pcm_runtime *rtd,
  void *stream, int rollback);
+int snd_soc_pcm_component_ack(struct snd_pcm_substream *substream);
 
 #endif /* __SOC_COMPONENT_H */
diff --git a/sound/soc/soc-component.c b/sound/soc/soc-component.c
index 159bf88b9f8c..a9fbb2d26412 100644
--- a/sound/soc/soc-component.c
+++ b/sound/soc/soc-component.c
@@ -1212,3 +1212,17 @@ void snd_soc_pcm_component_pm_runtime_put(struct 
snd_soc_pcm_runtime *rtd,
soc_component_mark_pop(component, stream, pm);
}
 }
+
+int snd_soc_pcm_component_ack(struct snd_pcm_substream *substream)
+{
+   struct snd_soc_pcm_runtime *rtd = asoc_substream_to_rtd(substream);
+   struct snd_soc_component *component;
+   int i;
+
+   /* FIXME: use 1st pointer */
+   for_each_rtd_components(rtd, i, component)
+   if (component->driver->ack)
+   return component->driver->ack(component, substream);
+
+   return 0;
+}
diff --git a/sound/soc/soc-pcm.c b/sound/soc/soc-pcm.c
index b79f064887d4..605acec48971 100644
--- a/sound/soc/soc-pcm.c
+++ b/sound/soc/soc-pcm.c
@@ -2830,6 +2830,8 @@ int soc_new_pcm(struct snd_soc_pcm_runtime *rtd, int num)
rtd->ops.page   = snd_soc_pcm_component_page;
if (drv->mmap)
rtd->ops.mmap   = snd_soc_pcm_component_mmap;
+   if (drv->ack)
+   rtd->ops.ack= snd_soc_pcm_component_ack;
}
 
if (playback)
-- 
2.27.0

[PATCH v2 7/7] ASoC: dt-bindings: imx-rpmsg: Add binding doc for rpmsg machine driver

[Shengjiu Wang]

Imx-rpmsg is a new added machine driver for supporting audio on Cortex-M
core. The Cortex-M core will control the audio interface, DMA and audio
codec, setup the pipeline, the audio driver on Cortex-A core side is just
to communitcate with M core, it is a virtual sound card and don't touch
the hardware.

Signed-off-by: Shengjiu Wang 
---
 .../bindings/sound/imx-audio-rpmsg.yaml   | 48 +++
 1 file changed, 48 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/sound/imx-audio-rpmsg.yaml

diff --git a/Documentation/devicetree/bindings/sound/imx-audio-rpmsg.yaml 
b/Documentation/devicetree/bindings/sound/imx-audio-rpmsg.yaml
new file mode 100644
index ..b941aeb80678
--- /dev/null
+++ b/Documentation/devicetree/bindings/sound/imx-audio-rpmsg.yaml
@@ -0,0 +1,48 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/sound/imx-audio-rpmsg.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: NXP i.MX audio complex with rpmsg
+
+maintainers:
+  - Shengjiu Wang 
+
+properties:
+  compatible:
+enum:
+  - fsl,imx-audio-rpmsg
+
+  model:
+$ref: /schemas/types.yaml#/definitions/string
+description: User specified audio sound card name
+
+  audio-cpu:
+description: The phandle of an CPU DAI controller
+
+  rpmsg-out:
+description: |
+  This is a boolean property. If present, the transmitting function
+  will be enabled,
+
+  rpmsg-in:
+description: |
+  This is a boolean property. If present, the receiving function
+  will be enabled.
+
+required:
+  - compatible
+  - model
+  - audio-cpu
+
+additionalProperties: false
+
+examples:
+  - |
+sound-rpmsg {
+compatible = "fsl,imx-audio-rpmsg";
+model = "ak4497-audio";
+audio-cpu = <&rpmsg_audio>;
+rpmsg-out;
+};
-- 
2.27.0

[PATCH v2 5/7] ASoC: imx-pcm-rpmsg: Add platform driver for audio base on rpmsg

[Shengjiu Wang]

platform driver base on rpmsg is the interface for sending and
receiving rpmsg to and from M core. It will tell the Cortex-M core
sound format/rate/channel, where is the data buffer, where is
the period size, when to start, when to stop and when suspend
or resume happen, each this behavior there is defined rpmsg
command.

Especially we designed the low power audio case, that is to
allocate a large buffer and fill the data, then Cortex-A core can go
to sleep mode, Cortex-M core continue to play the sound, when the
buffer is consumed, Cortex-M core will trigger the Cortex-A core to
wakeup.

Signed-off-by: Shengjiu Wang 
---
 sound/soc/fsl/Kconfig |   5 +
 sound/soc/fsl/Makefile|   1 +
 sound/soc/fsl/imx-pcm-rpmsg.c | 919 ++
 sound/soc/fsl/imx-pcm-rpmsg.h | 512 +++
 4 files changed, 1437 insertions(+)
 create mode 100644 sound/soc/fsl/imx-pcm-rpmsg.c
 create mode 100644 sound/soc/fsl/imx-pcm-rpmsg.h

diff --git a/sound/soc/fsl/Kconfig b/sound/soc/fsl/Kconfig
index 84d9f0f1f75b..749c44fc0759 100644
--- a/sound/soc/fsl/Kconfig
+++ b/sound/soc/fsl/Kconfig
@@ -130,6 +130,11 @@ config SND_SOC_IMX_AUDIO_RPMSG
tristate
depends on RPMSG
 
+config SND_SOC_IMX_PCM_RPMSG
+   tristate
+   depends on SND_SOC_IMX_AUDIO_RPMSG
+   select SND_SOC_GENERIC_DMAENGINE_PCM
+
 config SND_SOC_IMX_AUDMUX
tristate "Digital Audio Mux module support"
help
diff --git a/sound/soc/fsl/Makefile b/sound/soc/fsl/Makefile
index f08f3cd07ff5..ce4f4324c3a2 100644
--- a/sound/soc/fsl/Makefile
+++ b/sound/soc/fsl/Makefile
@@ -61,6 +61,7 @@ obj-$(CONFIG_SND_SOC_IMX_AUDMUX) += snd-soc-imx-audmux.o
 obj-$(CONFIG_SND_SOC_IMX_PCM_FIQ) += imx-pcm-fiq.o
 obj-$(CONFIG_SND_SOC_IMX_PCM_DMA) += imx-pcm-dma.o
 obj-$(CONFIG_SND_SOC_IMX_AUDIO_RPMSG) += imx-audio-rpmsg.o
+obj-$(CONFIG_SND_SOC_IMX_PCM_RPMSG) += imx-pcm-rpmsg.o
 
 # i.MX Machine Support
 snd-soc-eukrea-tlv320-objs := eukrea-tlv320.o
diff --git a/sound/soc/fsl/imx-pcm-rpmsg.c b/sound/soc/fsl/imx-pcm-rpmsg.c
new file mode 100644
index ..f05d5d489560
--- /dev/null
+++ b/sound/soc/fsl/imx-pcm-rpmsg.c
@@ -0,0 +1,919 @@
+// SPDX-License-Identifier: GPL-2.0+
+// Copyright 2017-2021 NXP
+
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+#include "imx-pcm.h"
+#include "fsl_rpmsg.h"
+#include "imx-pcm-rpmsg.h"
+
+static struct snd_pcm_hardware imx_rpmsg_pcm_hardware = {
+   .info = SNDRV_PCM_INFO_INTERLEAVED |
+   SNDRV_PCM_INFO_BLOCK_TRANSFER |
+   SNDRV_PCM_INFO_MMAP |
+   SNDRV_PCM_INFO_MMAP_VALID |
+   SNDRV_PCM_INFO_NO_PERIOD_WAKEUP |
+   SNDRV_PCM_INFO_PAUSE |
+   SNDRV_PCM_INFO_RESUME,
+   .buffer_bytes_max = IMX_DEFAULT_DMABUF_SIZE,
+   .period_bytes_min = 512,
+   .period_bytes_max = 65536,
+   .periods_min = 2,
+   .periods_max = 6000,
+   .fifo_size = 0,
+};
+
+static int imx_rpmsg_pcm_send_message(struct rpmsg_msg *msg,
+ struct rpmsg_info *info)
+{
+   struct rpmsg_device *rpdev = info->rpdev;
+   int ret = 0;
+
+   mutex_lock(&info->msg_lock);
+   if (!rpdev) {
+   dev_err(info->dev, "rpmsg channel not ready\n");
+   mutex_unlock(&info->msg_lock);
+   return -EINVAL;
+   }
+
+   dev_dbg(&rpdev->dev, "send cmd %d\n", msg->s_msg.header.cmd);
+
+   if (!(msg->s_msg.header.type == MSG_TYPE_C))
+   reinit_completion(&info->cmd_complete);
+
+   ret = rpmsg_send(rpdev->ept, (void *)&msg->s_msg,
+sizeof(struct rpmsg_s_msg));
+   if (ret) {
+   dev_err(&rpdev->dev, "rpmsg_send failed: %d\n", ret);
+   mutex_unlock(&info->msg_lock);
+   return ret;
+   }
+
+   /* No receive msg for TYPE_C command */
+   if (msg->s_msg.header.type == MSG_TYPE_C) {
+   mutex_unlock(&info->msg_lock);
+   return 0;
+   }
+
+   /* wait response from rpmsg */
+   ret = wait_for_completion_timeout(&info->cmd_complete,
+ msecs_to_jiffies(RPMSG_TIMEOUT));
+   if (!ret) {
+   dev_err(&rpdev->dev, "rpmsg_send cmd %d timeout!\n",
+   msg->s_msg.header.cmd);
+   mutex_unlock(&info->msg_lock);
+   return -ETIMEDOUT;
+   }
+
+   memcpy(&msg->r_msg, &info->r_msg, sizeof(struct rpmsg_r_msg));
+   memcpy(&info->msg[msg->r_msg.header.cmd].r_msg,
+  &msg->r_msg, sizeof(struct rpmsg_r_msg));
+
+   /*
+* Reset the buffer pointer to be zero, actully we have
+* set the buffer pointer to be zero in imx_rpmsg_terminate_all
+* But if there is timer task queued in queue, after it is
+* executed the buffer pointer will be changed, so need to
+* reset it again with TERMINATE command

Re: [PATCH] ASoC: fsl: constify static snd_soc_dai_ops structs

[Shengjiu Wang]

On Sun, Feb 7, 2021 at 6:58 AM Rikard Falkeborn
 wrote:
>
> The only usage of these is to assign their address to the 'ops' field in
> the snd_soc_dai_driver struct, which is a pointer to const. Make them
> const to allow the compiler to put them in read-only memory.
>
> Signed-off-by: Rikard Falkeborn 

Acked-by: Shengjiu Wang 

[GIT PULL] x86/urgent for v5.11-rc7

[Borislav Petkov]

Hi Linus,

I hope this is the last batch of x86/urgent updates for this round.

Pls pull,
thx.

---

The following changes since commit 6ee1d745b7c9fd573fba142a2efdad76a9f1cb04:

  Linux 5.11-rc5 (2021-01-24 16:47:14 -0800)

are available in the Git repository at:

  git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip.git 
tags/x86_urgent_for_v5.11_rc7

for you to fetch changes up to 816ef8d7a2c4182e19bc06ab65751cb9e3951e94:

  x86/efi: Remove EFI PGD build time checks (2021-02-06 13:54:14 +0100)


- Remove superfluous EFI PGD range checks which lead to those assertions failing
with certain kernel configs and LLVM.

- Disable setting breakpoints on facilities involved in #DB exception handling
to avoid infinite loops.

- Add extra serialization to non-serializing MSRs (IA32_TSC_DEADLINE and
x2 APIC MSRs) to adhere to SDM's recommendation and avoid any theoretical
issues.

- Re-add the EPB MSR reading on turbostat so that it works on older
kernels which don't have the corresponding EPB sysfs file.

- Add Alder Lake to the list of CPUs which support split lock.

- Fix %dr6 register handling in order to be able to set watchpoints with gdb
again.

- Disable CET instrumentation in the kernel so that gcc doesn't add
ENDBR64 to kernel code and thus confuse tracing.


Borislav Petkov (2):
  tools/power/turbostat: Fallback to an MSR read for EPB
  x86/efi: Remove EFI PGD build time checks

Dave Hansen (1):
  x86/apic: Add extra serialization for non-serializing MSRs

Fenghua Yu (1):
  x86/split_lock: Enable the split lock feature on another Alder Lake CPU

Josh Poimboeuf (1):
  x86/build: Disable CET instrumentation in the kernel

Lai Jiangshan (2):
  x86/debug: Prevent data breakpoints on __per_cpu_offset
  x86/debug: Prevent data breakpoints on cpu_dr7

Peter Zijlstra (1):
  x86/debug: Fix DR6 handling

 Makefile  |  6 
 arch/x86/Makefile |  3 ++
 arch/x86/include/asm/apic.h   | 10 --
 arch/x86/include/asm/barrier.h| 18 +++
 arch/x86/kernel/apic/apic.c   |  4 +++
 arch/x86/kernel/apic/x2apic_cluster.c |  6 ++--
 arch/x86/kernel/apic/x2apic_phys.c|  9 --
 arch/x86/kernel/cpu/intel.c   |  1 +
 arch/x86/kernel/hw_breakpoint.c   | 61 +++
 arch/x86/platform/efi/efi_64.c| 19 ---
 tools/power/x86/turbostat/turbostat.c | 10 +-
 11 files changed, 85 insertions(+), 62 deletions(-)

-- 
Regards/Gruss,
Boris.

SUSE Software Solutions Germany GmbH, GF: Felix Imendörffer, HRB 36809, AG 
Nürnberg

Re: [RFC PATCH 10/11] vfio/iommu_type1: Optimize dirty bitmap population based on iommu HWDBM

[Keqian Zhu]

Hi Yi,

On 2021/2/7 17:56, Yi Sun wrote:
> Hi,
> 
> On 21-01-28 23:17:41, Keqian Zhu wrote:
> 
> [...]
> 
>> +static void vfio_dma_dirty_log_start(struct vfio_iommu *iommu,
>> + struct vfio_dma *dma)
>> +{
>> +struct vfio_domain *d;
>> +
>> +list_for_each_entry(d, &iommu->domain_list, next) {
>> +/* Go through all domain anyway even if we fail */
>> +iommu_split_block(d->domain, dma->iova, dma->size);
>> +}
>> +}
> 
> This should be a switch to prepare for dirty log start. Per Intel
> Vtd spec, there is SLADE defined in Scalable-Mode PASID Table Entry.
> It enables Accessed/Dirty Flags in second-level paging entries.
> So, a generic iommu interface here is better. For Intel iommu, it
> enables SLADE. For ARM, it splits block.
Indeed, a generic interface name is better.

The vendor iommu driver plays vendor's specific actions to start dirty log, and 
Intel iommu and ARM smmu may differ. Besides, we may add more actions in ARM 
smmu driver in future.

One question: Though I am not familiar with Intel iommu, I think it also should 
split block mapping besides enable SLADE. Right?

Thanks,
Keqian

Re: [PATCH 5.10 04/57] net: octeontx2: Make sure the buffer is 128 byte aligned

[Kevin Hao]

On Sun, Feb 07, 2021 at 10:20:15AM +0100, Pavel Machek wrote:
> Hi!
> 
> > commit db2805150a0f27c00ad286a29109397a7723adad upstream.
> > 
> > The octeontx2 hardware needs the buffer to be 128 byte aligned.
> > But in the current implementation of napi_alloc_frag(), it can't
> > guarantee the return address is 128 byte aligned even the request size
> > is a multiple of 128 bytes, so we have to request an extra 128 bytes and
> > use the PTR_ALIGN() to make sure that the buffer is aligned correctly.
> > 
> > +++ b/drivers/net/ethernet/marvell/octeontx2/nic/otx2_common.c
> > @@ -473,10 +473,11 @@ dma_addr_t __otx2_alloc_rbuf(struct otx2
> > dma_addr_t iova;
> > u8 *buf;
> >  
> > -   buf = napi_alloc_frag(pool->rbsize);
> > +   buf = napi_alloc_frag(pool->rbsize + OTX2_ALIGN);
> > if (unlikely(!buf))
> > return -ENOMEM;
> >  
> > +   buf = PTR_ALIGN(buf, OTX2_ALIGN);
> 
> So we allocate a buffer, then change it, and then pass modified
> pointer to the page_frag_free(buf); in the error path. That... can't
> be right, right?

It doesn't matter. It will work as far as the address we passed to 
page_frag_free()
is in the range of buf ~ (buf + rbsize).

> 
> > iova = dma_map_single_attrs(pfvf->dev, buf, pool->rbsize,
> > DMA_FROM_DEVICE, DMA_ATTR_SKIP_CPU_SYNC);
> > if (unlikely(dma_mapping_error(pfvf->dev, iova))) {
> 
> BTW otx2_alloc_rbuf and __otx2_alloc_rbuf should probably return s64,
> as they return negative error code...

It does seem buggy to return dma_addr_t for these two functions, I will cook up
a patch to fix this issue.

Thanks,
Kevin

> 
> Best regards,
>   Pavel
> 
> -- 
> http://www.livejournal.com/~pavelmachek




signature.asc
Description: PGP signature

Re: [PATCH v19 3/3] scsi: ufs: Prepare HPB read for cached sub-region

[Bean Huo]

On Sun, 2021-02-07 at 15:36 +0800, Can Guo wrote:
> > 
> > Thanks, I tested Daejun's patchset before, it is also ok (I don't
> > know
> > which version patchset). maybe we can keep current implementation
> > as
> > default, then if there is conflict, and submit the quirk.
> > 
> 
> Yeah, you've tested it, are you sure that Micron's UFS devices are OK
> with this specific code line?
> 
> Micron UFS FW team has confirmed that Micron's HPB entries read out
> by
> "HPB Buffer Read" cmd are in big-endian byte ordering.

Aha, I think you didn't check with right person :), ping me, let me
tell you this confusing story. and see my HPB patch, I didn't the same
with here:

https://patchwork.kernel.org/project/linux-scsi/patch/20200504142032.16619-6-bean...@micron.com/

Bean

Re: [RESEND PATCH v8 net-next 03/15] net: mvpp2: add CM3 SRAM memory map

[Baruch Siach]

Hi Stefan,

On Sun, Feb 07 2021, stef...@marvell.com wrote:
> From: Stefan Chulski 
>
> This patch adds CM3 memory map and CM3 read/write callbacks.
> No functionality changes.
>
> Signed-off-by: Stefan Chulski 
> ---
>  drivers/net/ethernet/marvell/mvpp2/mvpp2.h  |  7 +++
>  drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c | 63 +++-
>  2 files changed, 67 insertions(+), 3 deletions(-)
>
> diff --git a/drivers/net/ethernet/marvell/mvpp2/mvpp2.h 
> b/drivers/net/ethernet/marvell/mvpp2/mvpp2.h
> index 6bd7e40..aec9179 100644
> --- a/drivers/net/ethernet/marvell/mvpp2/mvpp2.h
> +++ b/drivers/net/ethernet/marvell/mvpp2/mvpp2.h
> @@ -748,6 +748,9 @@
>  #define MVPP2_TX_FIFO_THRESHOLD(kb)  \
>   ((kb) * 1024 - MVPP2_TX_FIFO_THRESHOLD_MIN)
>  
> +/* MSS Flow control */
> +#define MSS_SRAM_SIZE0x800
> +
>  /* RX buffer constants */
>  #define MVPP2_SKB_SHINFO_SIZE \
>   SKB_DATA_ALIGN(sizeof(struct skb_shared_info))
> @@ -925,6 +928,7 @@ struct mvpp2 {
>   /* Shared registers' base addresses */
>   void __iomem *lms_base;
>   void __iomem *iface_base;
> + void __iomem *cm3_base;
>  
>   /* On PPv2.2, each "software thread" can access the base
>* register through a separate address space, each 64 KB apart
> @@ -996,6 +1000,9 @@ struct mvpp2 {
>  
>   /* page_pool allocator */
>   struct page_pool *page_pool[MVPP2_PORT_MAX_RXQ];
> +
> + /* CM3 SRAM pool */
> + struct gen_pool *sram_pool;
>  };
>  
>  struct mvpp2_pcpu_stats {
> diff --git a/drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c 
> b/drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c
> index a07cf60..307f9fd 100644
> --- a/drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c
> +++ b/drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c
> @@ -25,6 +25,7 @@
>  #include 
>  #include 
>  #include 
> +#include 
>  #include 
>  #include 
>  #include 
> @@ -6846,6 +6847,44 @@ static int mvpp2_init(struct platform_device *pdev, 
> struct mvpp2 *priv)
>   return 0;
>  }
>  
> +static int mvpp2_get_sram(struct platform_device *pdev,
> +   struct mvpp2 *priv)
> +{
> + struct device_node *dn = pdev->dev.of_node;
> + static bool defer_once;
> + struct resource *res;
> +
> + if (has_acpi_companion(&pdev->dev)) {
> + res = platform_get_resource(pdev, IORESOURCE_MEM, 2);
> + if (!res) {
> + dev_warn(&pdev->dev, "ACPI is too old, Flow control not 
> supported\n");
> + return 0;
> + }
> + priv->cm3_base = devm_ioremap_resource(&pdev->dev, res);
> + if (IS_ERR(priv->cm3_base))
> + return PTR_ERR(priv->cm3_base);
> + } else {
> + priv->sram_pool = of_gen_pool_get(dn, "cm3-mem", 0);
> + if (!priv->sram_pool) {
> + if (!defer_once) {
> + defer_once = true;
> + /* Try defer once */
> + return -EPROBE_DEFER;
> + }
> + dev_warn(&pdev->dev, "DT is too old, Flow control not 
> supported\n");

This warning will show on every DT system with no cm3-mem property, right?

> + return -ENOMEM;
> + }
> + /* cm3_base allocated with offset zero into the SRAM since 
> mapping size
> +  * is equal to requested size.
> +  */
> + priv->cm3_base = (void __iomem *)gen_pool_alloc(priv->sram_pool,
> + MSS_SRAM_SIZE);
> + if (!priv->cm3_base)
> + return -ENOMEM;
> + }
> + return 0;
> +}
> +
>  static int mvpp2_probe(struct platform_device *pdev)
>  {
>   const struct acpi_device_id *acpi_id;
> @@ -6902,6 +6941,13 @@ static int mvpp2_probe(struct platform_device *pdev)
>   priv->iface_base = devm_ioremap_resource(&pdev->dev, res);
>   if (IS_ERR(priv->iface_base))
>   return PTR_ERR(priv->iface_base);
> +
> + /* Map CM3 SRAM */
> + err = mvpp2_get_sram(pdev, priv);
> + if (err == -EPROBE_DEFER)
> + return err;
> + else if (err)
> + dev_warn(&pdev->dev, "Fail to alloc CM3 SRAM\n");

This one will show as well.

I would not expect that from a patch that makes "no functional change".

baruch

>   }
>  
>   if (priv->hw_version == MVPP22 && dev_of_node(&pdev->dev)) {
> @@ -6947,11 +6993,13 @@ static int mvpp2_probe(struct platform_device *pdev)
>  
>   if (dev_of_node(&pdev->dev)) {
>   priv->pp_clk = devm_clk_get(&pdev->dev, "pp_clk");
> - if (IS_ERR(priv->pp_clk))
> - return PTR_ERR(priv->pp_clk);
> + if (IS_ERR(priv->pp_clk)) {
> + err = PTR_ERR(priv->pp_clk);
> + goto err_cm3;
> +  

Re: [PATCH] I was wondering why I can't set the resolution to 2560x1080, while in windows 7 I can without a problem. I looked at the radeon driver code and found it doesn't support this resolution. So

[Joe Perches]

Your subject needs to be changed and a commit log added.

> diff --git a/drivers/gpu/drm/radeon/radeon_connectors.c 
> b/drivers/gpu/drm/radeon/radeon_connectors.c
[]
> @@ -37,6 +37,8 @@
>  #include 
>  #include 
> 
> +extern int hdmimhz;
> +
>  static int radeon_dp_handle_hpd(struct drm_connector *connector)
>  {
>   struct radeon_connector *radeon_connector = 
> to_radeon_connector(connector);
> @@ -503,7 +505,7 @@ static void radeon_add_common_modes(struct drm_encoder 
> *encoder, struct drm_conn
>   struct mode_size {
>   int w;
>   int h;
> - } common_modes[17] = {
> + } common_modes[18] = {

probably better without a specific array size

>   { 640,  480},
>   { 720,  480},
>   { 800,  600},
> @@ -520,10 +522,11 @@ static void radeon_add_common_modes(struct drm_encoder 
> *encoder, struct drm_conn
>   {1680, 1050},
>   {1600, 1200},
>   {1920, 1080},
> - {1920, 1200}
> + {1920, 1200},
> + {2560, 1080}
>   };
>  
> 
> - for (i = 0; i < 17; i++) {
> + for (i = 0; i < 18; i++) {

for (i = 0; i < ARRAY_SIZE(common_modes); i++) {

> @@ -1491,25 +1494,32 @@ static enum drm_mode_status 
> radeon_dvi_mode_valid(struct drm_connector *connecto
>   (mode->clock > 135000))
>   return MODE_CLOCK_HIGH;
>  
> 
> - if (radeon_connector->use_digital && (mode->clock > 165000)) {
> + if (radeon_connector->use_digital && (mode->clock > (hdmimhz * 1000))) {
>   if ((radeon_connector->connector_object_id == 
> CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_I) ||
>   (radeon_connector->connector_object_id == 
> CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_D) ||
> - (radeon_connector->connector_object_id == 
> CONNECTOR_OBJECT_ID_HDMI_TYPE_B))
> + (radeon_connector->connector_object_id == 
> CONNECTOR_OBJECT_ID_HDMI_TYPE_B)){
> + printk("MODE_CLOCK_HIHG0 %d", hdmimhz);

unnecessary debugging printks?

[GIT PULL] timers/urgent for v5.11-rc7

[Borislav Petkov]

Hi Linus,

please pull two more timers-related fixes for v5.11.

Thx.

---

The following changes since commit 211e5db19d15a721b2953ea54b8f26c2963720eb:

  rtc: mc146818: Detect and handle broken RTCs (2021-01-27 09:36:22 +0100)

are available in the Git repository at:

  git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip.git 
tags/timers_urgent_for_v5.11_rc7

for you to fetch changes up to 24c242ec7abb3d21fa0b1da6bb251521dc1717b5:

  ntp: Use freezable workqueue for RTC synchronization (2021-02-05 18:03:13 
+0100)


- Use a freezable workqueue for RTC sync because the sync can happen at any time
and trigger suspend assertion checks in the i2c subsystem.

- Correct a previous RTC validation change to check only bit 6 in register D
because some Intel machines use bits 0-5.


Geert Uytterhoeven (1):
  ntp: Use freezable workqueue for RTC synchronization

Thomas Gleixner (1):
  rtc: mc146818: Dont test for bit 0-5 in Register D

 drivers/rtc/rtc-cmos.c | 4 ++--
 drivers/rtc/rtc-mc146818-lib.c | 4 ++--
 kernel/time/ntp.c  | 4 ++--
 3 files changed, 6 insertions(+), 6 deletions(-)

-- 
Regards/Gruss,
Boris.

SUSE Software Solutions Germany GmbH, GF: Felix Imendörffer, HRB 36809, AG 
Nürnberg

linux-next: Fixes tag needs some work in the soundwire tree

[Stephen Rothwell]

Hi all,

In commit

  531f45f2bdf6 ("soundwire: export sdw_write/read_no_pm functions")

Fixes tag

  Fixes: 60ee9be25571 ('soundwire: bus: add PM/no-PM versions of

has these problem(s):

  - Subject has leading but no trailing parentheses
  - Subject has leading but no trailing quotes

Please do not split Fixes tags over more than one line.

-- 
Cheers,
Stephen Rothwell


pgppI9BVbHzjQ.pgp
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Re: [PATCH v2 6/7] platform: x86: Add intel_skl_int3472 driver

[Daniel Scally]

Hello Andy, Laurent

On 21/01/2021 00:18, Daniel Scally wrote:
> On 20/01/2021 12:57, Andy Shevchenko wrote:
>> On Wed, Jan 20, 2021 at 06:21:41AM +0200, Laurent Pinchart wrote:
>>> On Tue, Jan 19, 2021 at 07:51:14PM +0200, Andy Shevchenko wrote:
 On Tue, Jan 19, 2021 at 06:48:15PM +0200, Laurent Pinchart wrote:
> On Tue, Jan 19, 2021 at 01:08:37PM +0200, Andy Shevchenko wrote:
>> On Tue, Jan 19, 2021 at 10:40:42AM +, Daniel Scally wrote:
>>> On 19/01/2021 09:24, Andy Shevchenko wrote:
 +static struct i2c_driver int3472_tps68470 = {
 +  .driver = {
 +  .name = "int3472-tps68470",
 +  .acpi_match_table = int3472_device_id,
 +  },
 +  .probe_new = skl_int3472_tps68470_probe,
 +};
>> I'm not sure we want to have like this. If I'm not mistaken the I²C 
>> driver can
>> be separated without ACPI IDs (just having I²C IDs) and you may 
>> instantiate it
>> via i2c_new_client_device() or i2c_acpi_new_device() whichever suits 
>> better...
> Sorry, I'm a bit confused by this. The i2c device is already
> present...we just want the driver to bind to them, so what role do 
> those
> functions have there?
 What I meant is something like

  *_i2c.c
real I²C driver for the TPS chip, but solely with I²C ID table, 
 no ACPI
involved (and it sounds like it should be mfd/tps one, in which 
 you
just cut out ACPI IDs and convert to pure I²C one, that what I 
 had
suggested in the first place)
>>> Ahh; sorry - i misunderstood what you meant there. I understand now I
>>> think, but there is one complication; the ACPI subsystem already creates
>>> a client for that i2c adapter and address; i2c_new_client_device()
>>> includes a check to see whether that adapter / address combination has
>>> an i2c device already.  So we would have to have the platform driver
>>> with ACPI ID first find the existing i2c_client and unregister it before
>>> registering the new one...the existing clients have a name matching the
>>> ACPI device instance name (e.g i2c-INT3472:00) which we can't use as an
>>> i2c_device_id of course.
>> See how INT33FE is being handled. Hint: drivers/acpi/scan.c:~1600
>>
>> static const struct acpi_device_id i2c_multi_instantiate_ids[] = {
>>  {"BSG1160", },
>>  {"BSG2150", },
>>  {"INT33FE", },
>>  {"INT3515", },
>>  {}
>> };
>>
>> So, we quirklist it here and instantiate manually from platform driver 
>> (new
>> coming one).
> This is documented as used for devices that have multiple I2cSerialBus
> resources. That's not the case for the INT3472 as far as I can tell. I
> don't think we should abuse this mechanism.
 This is quite a similar case to that one. Let's avoid yak shaving, right?
>>> Exactly my point, that's why I think this patch is good overall, I don't
>>> think it requires a complete rewrite.
>> The approach in the series is to reinvent the MFD driver which I against of.
>> I don;t think we need to kill it there and reborn in a new form and dragging
>> code from there to here to there.
>>
>> On top of that the approach with a quirk driver in the middle seems to me
>> cleaner than using different paths how the two drivers are being initialized.
>> In the proposed approach there will be one making decision point and easy to
>> understand what's going on.
>>
>> The bad example of two making decision points is acpi_lpss.c vs. individual
>> drivers (however in that case it have different ID's, i.e. ACPI vs. PCI),
>
> Right; so if I understand correctly, the proposal is:
>
> 1. Add INT3472 to the i2c_multi_instantiate_ids, which blocks it getting
> created as an i2c device
> 2. instead of intel-skl-int3472 registering an i2c and a platform
> driver, just register a platform driver that binds to the INT3472
> acpi_device_id. We can check hardware type like in
> intel_cht_int33fe_common.c and call either discrete probe that does what
> the discrete driver is doing now, or else call tps68470 which is just a
> stub driver registering an i2c device like intel_cht_int33fe_microb.c
> 3. Change the existing tps68470 mfd driver to match to that created i2c
> device instead of ACPI match, and move the code from
> intel_skl_int3472_tps68470.c to that driver instead
>
> I think I finally got what you meant there, Andy, but correct me if I'm
> wrong please.
>
> I'm not sure that one's better than the other, to be honest. Either the
> multi-function device functionality lives in the conventional place, or
> else _all_ of the int3472 handling code lives together in one module.
Can we come to a consensus on this? I would rather be in agreement than
leave it hanging...I do see the argument that it's better not to rebirt

[GIT PULL] sched/urgent for v5.11-rc7

[Borislav Petkov]

Hi Linus,

pls pull one sched/urgent revert for v5.11.

Thx.

---

The following changes since commit 1048ba83fb1c00cd24172e23e8263972f6b5d9ac:

  Linux 5.11-rc6 (2021-01-31 13:50:09 -0800)

are available in the Git repository at:

  git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip.git 
tags/sched_urgent_for_v5.11_rc7

for you to fetch changes up to 2452483d9546de1c540f330469dc4042ff089731:

  Revert "lib: Restrict cpumask_local_spread to houskeeping CPUs" (2021-02-05 
23:28:29 +0100)


- Revert an attempt to not spread IRQ threads on isolated CPUs which has
a bunch of problems.


Thomas Gleixner (1):
  Revert "lib: Restrict cpumask_local_spread to houskeeping CPUs"

 lib/cpumask.c | 16 +---
 1 file changed, 5 insertions(+), 11 deletions(-)

-- 
Regards/Gruss,
Boris.

SUSE Software Solutions Germany GmbH, GF: Felix Imendörffer, HRB 36809, AG 
Nürnberg

Re: [PATCH] apparmor: fix error check

[John Johansen]

On 10/4/20 7:24 AM, t...@redhat.com wrote:
> From: Tom Rix 
> 
> clang static analysis reports this representative problem:
> 
> label.c:1463:16: warning: Assigned value is garbage or undefined
> label->hname = name;
>  ^ 
> 
> In aa_update_label_name(), this the problem block of code
> 
>   if (aa_label_acntsxprint(&name, ...) == -1)
>   return res;
> 
> On failure, aa_label_acntsxprint() has a more complicated return
> that just -1.  So check for a negative return.
> 
> It was also noted that the aa_label_acntsxprint() main comment refers
> to a nonexistent parameter, so clean up the comment.
> 
> Fixes: f1bd904175e8 ("apparmor: add the base fns() for domain labels")
> Signed-off-by: Tom Rix 
> ---
>  security/apparmor/label.c | 4 ++--
>  1 file changed, 2 insertions(+), 2 deletions(-)
> 
> diff --git a/security/apparmor/label.c b/security/apparmor/label.c
> index e68bcedca976..6222fdfebe4e 100644
> --- a/security/apparmor/label.c
> +++ b/security/apparmor/label.c
> @@ -1454,7 +1454,7 @@ bool aa_update_label_name(struct aa_ns *ns, struct 
> aa_label *label, gfp_t gfp)
>   if (label->hname || labels_ns(label) != ns)
>   return res;
>  
> - if (aa_label_acntsxprint(&name, ns, label, FLAGS_NONE, gfp) == -1)
> + if (aa_label_acntsxprint(&name, ns, label, FLAGS_NONE, gfp) < 0)
>   return res;
>  
>   ls = labels_set(label);
> @@ -1704,7 +1704,7 @@ int aa_label_asxprint(char **strp, struct aa_ns *ns, 
> struct aa_label *label,
>  
>  /**
>   * aa_label_acntsxprint - allocate a __counted string buffer and print label
> - * @strp: buffer to write to. (MAY BE NULL if @size == 0)
> + * @strp: buffer to write to.
>   * @ns: namespace profile is being viewed from
>   * @label: label to view (NOT NULL)
>   * @flags: flags controlling what label info is printed
> 


sorry it seems I missed replying to this. This patch has been pulled into 
apparmor-next