[PATCH v3 05/23] PCI: endpoint: Create configfs entry for EPC device and EPF driver

[Kishon Vijay Abraham I]

Invoke API's provided by pci-ep-cfs to create configfs entry for
every EPC device and EPF driver to help users in creating EPF device
and binding the EPF device to the EPC device.

Signed-off-by: Kishon Vijay Abraham I 
---
 drivers/pci/endpoint/pci-epc-core.c |4 
 drivers/pci/endpoint/pci-epf-core.c |4 
 include/linux/pci-epc.h |2 ++
 include/linux/pci-epf.h |2 ++
 4 files changed, 12 insertions(+)

diff --git a/drivers/pci/endpoint/pci-epc-core.c 
b/drivers/pci/endpoint/pci-epc-core.c
index 06808ed..29cbe9a 100644
--- a/drivers/pci/endpoint/pci-epc-core.c
+++ b/drivers/pci/endpoint/pci-epc-core.c
@@ -24,6 +24,7 @@
 
 #include 
 #include 
+#include 
 
 static struct class *pci_epc_class;
 
@@ -441,6 +442,7 @@ void pci_epc_linkup(struct pci_epc *epc)
  */
 void pci_epc_destroy(struct pci_epc *epc)
 {
+   pci_ep_cfs_remove_epc_group(epc->group);
device_unregister(&epc->dev);
kfree(epc);
 }
@@ -507,6 +509,8 @@ struct pci_epc *
if (ret)
goto put_dev;
 
+   epc->group = pci_ep_cfs_add_epc_group(dev_name(dev));
+
return epc;
 
 put_dev:
diff --git a/drivers/pci/endpoint/pci-epf-core.c 
b/drivers/pci/endpoint/pci-epf-core.c
index 4c903fc..9ec1639 100644
--- a/drivers/pci/endpoint/pci-epf-core.c
+++ b/drivers/pci/endpoint/pci-epf-core.c
@@ -24,6 +24,7 @@
 
 #include 
 #include 
+#include 
 
 static struct bus_type pci_epf_bus_type;
 static struct device_type pci_epf_type;
@@ -143,6 +144,7 @@ void *pci_epf_alloc_space(struct pci_epf *epf, size_t size, 
enum pci_barno bar)
  */
 void pci_epf_unregister_driver(struct pci_epf_driver *driver)
 {
+   pci_ep_cfs_remove_epf_group(driver->group);
driver_unregister(&driver->driver);
 }
 EXPORT_SYMBOL_GPL(pci_epf_unregister_driver);
@@ -172,6 +174,8 @@ int __pci_epf_register_driver(struct pci_epf_driver *driver,
if (ret)
return ret;
 
+   driver->group = pci_ep_cfs_add_epf_group(driver->driver.name);
+
return 0;
 }
 EXPORT_SYMBOL_GPL(__pci_epf_register_driver);
diff --git a/include/linux/pci-epc.h b/include/linux/pci-epc.h
index ad0cd46..d6eb322 100644
--- a/include/linux/pci-epc.h
+++ b/include/linux/pci-epc.h
@@ -77,6 +77,7 @@ struct pci_epc_mem {
  * @ops: function pointers for performing endpoint operations
  * @mem: address space of the endpoint controller
  * @max_functions: max number of functions that can be configured in this EPC
+ * @group: configfs group representing the PCI EPC device
  * @lock: spinlock to protect pci_epc ops
  */
 struct pci_epc {
@@ -85,6 +86,7 @@ struct pci_epc {
const struct pci_epc_ops*ops;
struct pci_epc_mem  *mem;
u8  max_functions;
+   struct config_group *group;
/* spinlock to protect against concurrent access of EP controller */
spinlock_t  lock;
 };
diff --git a/include/linux/pci-epf.h b/include/linux/pci-epf.h
index 54f1338..5ff2c5a 100644
--- a/include/linux/pci-epf.h
+++ b/include/linux/pci-epf.h
@@ -82,6 +82,7 @@ struct pci_epf_ops {
  * @driver: PCI EPF driver
  * @ops: set of function pointers for performing EPF operations
  * @owner: the owner of the module that registers the PCI EPF driver
+ * @group: configfs group corresponding to the PCI EPF driver
  * @id_table: identifies EPF devices for probing
  */
 struct pci_epf_driver {
@@ -91,6 +92,7 @@ struct pci_epf_driver {
struct device_driverdriver;
struct pci_epf_ops  *ops;
struct module   *owner;
+   struct config_group *group;
const struct pci_epf_device_id  *id_table;
 };
 
-- 
1.7.9.5

[PATCH v3 03/23] PCI: endpoint: Introduce configfs entry for configuring EP functions

[Kishon Vijay Abraham I]

Introduce a new configfs entry to configure the EP function (like
configuring the standard configuration header entries) and to
bind the EP function with EP controller.

Signed-off-by: Kishon Vijay Abraham I 
---
 drivers/pci/endpoint/Kconfig  |9 +
 drivers/pci/endpoint/Makefile |1 +
 drivers/pci/endpoint/pci-ep-cfs.c |  509 +
 include/linux/pci-ep-cfs.h|   41 +++
 4 files changed, 560 insertions(+)
 create mode 100644 drivers/pci/endpoint/pci-ep-cfs.c
 create mode 100644 include/linux/pci-ep-cfs.h

diff --git a/drivers/pci/endpoint/Kconfig b/drivers/pci/endpoint/Kconfig
index a5442ac..c86bca9 100644
--- a/drivers/pci/endpoint/Kconfig
+++ b/drivers/pci/endpoint/Kconfig
@@ -17,4 +17,13 @@ config PCI_ENDPOINT
 
   If in doubt, say "N" to disable Endpoint support.
 
+config PCI_ENDPOINT_CONFIGFS
+   bool "PCI Endpoint Configfs Support"
+   depends on PCI_ENDPOINT
+   select CONFIGFS_FS
+   help
+  This will enable the configfs entry that can be used to
+  configure the endpoint function and used to bind the
+  function with a endpoint controller.
+
 endmenu
diff --git a/drivers/pci/endpoint/Makefile b/drivers/pci/endpoint/Makefile
index dc1bc16..7219d51 100644
--- a/drivers/pci/endpoint/Makefile
+++ b/drivers/pci/endpoint/Makefile
@@ -2,5 +2,6 @@
 # Makefile for PCI Endpoint Support
 #
 
+obj-$(CONFIG_PCI_ENDPOINT_CONFIGFS)+= pci-ep-cfs.o
 obj-$(CONFIG_PCI_ENDPOINT) += pci-epc-core.o pci-epf-core.o\
   pci-epc-mem.o
diff --git a/drivers/pci/endpoint/pci-ep-cfs.c 
b/drivers/pci/endpoint/pci-ep-cfs.c
new file mode 100644
index 000..424fdd6
--- /dev/null
+++ b/drivers/pci/endpoint/pci-ep-cfs.c
@@ -0,0 +1,509 @@
+/**
+ * configfs to configure the PCI endpoint
+ *
+ * Copyright (C) 2017 Texas Instruments
+ * Author: Kishon Vijay Abraham I 
+ *
+ * This program is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 of
+ * the License as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see .
+ */
+
+#include 
+#include 
+
+#include 
+#include 
+#include 
+
+static struct config_group *functions_group;
+static struct config_group *controllers_group;
+
+struct pci_epf_group {
+   struct config_group group;
+   struct pci_epf *epf;
+};
+
+struct pci_epc_group {
+   struct config_group group;
+   struct pci_epc *epc;
+   bool start;
+   unsigned long function_num_map;
+};
+
+static inline struct pci_epf_group *to_pci_epf_group(struct config_item *item)
+{
+   return container_of(to_config_group(item), struct pci_epf_group, group);
+}
+
+static inline struct pci_epc_group *to_pci_epc_group(struct config_item *item)
+{
+   return container_of(to_config_group(item), struct pci_epc_group, group);
+}
+
+static ssize_t pci_epc_start_store(struct config_item *item, const char *page,
+  size_t len)
+{
+   int ret;
+   bool start;
+   struct pci_epc *epc;
+   struct pci_epc_group *epc_group = to_pci_epc_group(item);
+
+   epc = epc_group->epc;
+
+   ret = kstrtobool(page, &start);
+   if (ret)
+   return ret;
+
+   if (!start) {
+   pci_epc_stop(epc);
+   return len;
+   }
+
+   ret = pci_epc_start(epc);
+   if (ret) {
+   dev_err(&epc->dev, "failed to start endpoint controller\n");
+   return -EINVAL;
+   }
+
+   epc_group->start = start;
+
+   return len;
+}
+
+static ssize_t pci_epc_start_show(struct config_item *item, char *page)
+{
+   return sprintf(page, "%d\n",
+  to_pci_epc_group(item)->start);
+}
+
+CONFIGFS_ATTR(pci_epc_, start);
+
+static struct configfs_attribute *pci_epc_attrs[] = {
+   &pci_epc_attr_start,
+   NULL,
+};
+
+static int pci_epc_epf_link(struct config_item *epc_item,
+   struct config_item *epf_item)
+{
+   int ret;
+   u32 func_no = 0;
+   struct pci_epc *epc;
+   struct pci_epf *epf;
+   struct pci_epf_group *epf_group = to_pci_epf_group(epf_item);
+   struct pci_epc_group *epc_group = to_pci_epc_group(epc_item);
+
+   epc = epc_group->epc;
+   epf = epf_group->epf;
+   ret = pci_epc_add_epf(epc, epf);
+   if (ret)
+   goto err_add_epf;
+
+   func_no = find_first_zero_bit(&epc_group->function_num_map,
+ sizeof(epc_group->function_num_map));
+   set_bit(func_no

[PATCH v3 02/23] Documentation: PCI: Guide to use PCI Endpoint Core Layer

[Kishon Vijay Abraham I]

Add Documentation to help users use endpoint library to enable endpoint
mode in the PCI controller and add new PCI endpoint functions.

Signed-off-by: Kishon Vijay Abraham I 
---
 Documentation/PCI/00-INDEX  |2 +
 Documentation/PCI/endpoint/pci-endpoint.txt |  215 +++
 2 files changed, 217 insertions(+)
 create mode 100644 Documentation/PCI/endpoint/pci-endpoint.txt

diff --git a/Documentation/PCI/00-INDEX b/Documentation/PCI/00-INDEX
index 147231f..ba950b2 100644
--- a/Documentation/PCI/00-INDEX
+++ b/Documentation/PCI/00-INDEX
@@ -12,3 +12,5 @@ pci.txt
- info on the PCI subsystem for device driver authors
 pcieaer-howto.txt
- the PCI Express Advanced Error Reporting Driver Guide HOWTO
+endpoint/pci-endpoint.txt
+   - guide to add endpoint controller driver and endpoint function driver.
diff --git a/Documentation/PCI/endpoint/pci-endpoint.txt 
b/Documentation/PCI/endpoint/pci-endpoint.txt
new file mode 100644
index 000..4a3e438
--- /dev/null
+++ b/Documentation/PCI/endpoint/pci-endpoint.txt
@@ -0,0 +1,215 @@
+   PCI ENDPOINT FRAMEWORK
+   Kishon Vijay Abraham I 
+
+This document is a guide to use the PCI Endpoint Framework in order to create
+endpoint controller driver, endpoint function driver and using configfs
+interface to bind the function driver to the controller driver.
+
+1. Introduction
+
+*Linux* has a comprehensive PCI subsystem to support PCI controllers that
+operates in Root Complex mode. The subsystem has capability to scan PCI bus,
+assign memory resources and irq resources, load PCI driver (based on
+vendorid, deviceid), support other services like hot-plug, power management,
+advanced error reporting and virtual channels.
+
+However PCI controller IPs integrated in certain SoC is capable of operating
+either in Root Complex mode or Endpoint mode. PCI Endpoint Framework will
+add endpoint mode support in *Linux*. This will help to run Linux in an
+EP system which can have a wide variety of use cases from testing or
+validation, co-processor accelerator etc..
+
+2. PCI Endpoint Core
+
+The PCI Endpoint Core layer comprises of 3 components: the Endpoint Controller
+library, the Endpoint Function library and the configfs layer to bind the
+endpoint function with the endpoint controller.
+
+2.1 PCI Endpoint Controller(EPC) Library
+
+The EPC library provides APIs to be used by the controller that can operate
+in endpoint mode. It also provides APIs to be used by function driver/library
+in order to implement a particular endpoint function.
+
+2.1.1 APIs for the PCI controller Driver
+
+This section lists the APIs that the PCI Endpoint core provides to be used
+by the PCI controller driver.
+
+*) devm_pci_epc_create()/pci_epc_create()
+
+   The PCI controller driver should implement the following ops:
+* write_header: ops to populate configuration space header
+* set_bar: ops to configure the BAR
+* clear_bar: ops to reset the BAR
+* alloc_addr_space: ops to allocate *in* PCI controller address space
+* free_addr_space: ops to free the allocated address space
+* raise_irq: ops to raise a legacy or MSI interrupt
+* start: ops to start the PCI link
+* stop: ops to stop the PCI link
+
+   The PCI controller driver can then create a new EPC device by invoking
+   devm_pci_epc_create/pci_epc_create.
+
+*) devm_pci_epc_destroy()/pci_epc_destroy()
+
+   The PCI controller driver can destroy the EPC device created by either
+   devm_pci_epc_create or pci_epc_create using devm_pci_epc_destroy() or
+   /pci_epc_destroy()
+
+*) pci_epc_linkup()
+
+   In order to notify all the function devices that the EPC device to which
+   they are linked has established a link with the host, the PCI controller
+   driver should invoke pci_epc_linkup().
+
+*) pci_epc_mem_init()
+
+   Initialize the pci_epc_mem structure used for allocating EPC addr space.
+
+*) pci_epc_mem_exit()
+
+   Cleanup the pci_epc_mem structure allocated during pci_epc_mem_init().
+
+2.1.2 APIs for the PCI Endpoint Function Driver
+
+This section lists the APIs that the PCI Endpoint core provides to be used
+by the PCI endpoint function driver.
+
+*) pci_epc_write_header()
+
+   The PCI endpoint function driver should use pci_epc_write_header() to
+   write the standard configuration header to the endpoint controller.
+
+*) pci_epc_set_bar()
+
+   The PCI endpoint function driver should use pci_epc_set_bar() to configure
+   the Base Address Register in order for the host to assign PCI addr space.
+   Register space of the function driver is usually configured
+   using this API.
+
+*) pci_epc_clear_bar()
+
+   The PCI endpoint function driver should use pci_epc_clear_bar() to reset
+   the BAR.
+
+*) pci_epc_raise_irq()
+
+   The PCI endpoint function driver should use pci_epc_raise_irq() to raise
+   Legacy Interrupt or MSI Interrupt.
+
+*) pci_epc_mem_alloc_addr()
+
+   T

[PATCH v3 15/23] dt-bindings: PCI: dra7xx: Add dt bindings to enable unaligned access

[Kishon Vijay Abraham I]

Update device tree binding documentation of TI's dra7xx PCI
controller to include property for enabling unaligned mem access.

Signed-off-by: Kishon Vijay Abraham I 
---
 Documentation/devicetree/bindings/pci/ti-pci.txt |5 +
 1 file changed, 5 insertions(+)

diff --git a/Documentation/devicetree/bindings/pci/ti-pci.txt 
b/Documentation/devicetree/bindings/pci/ti-pci.txt
index 190828a..b69dd7d 100644
--- a/Documentation/devicetree/bindings/pci/ti-pci.txt
+++ b/Documentation/devicetree/bindings/pci/ti-pci.txt
@@ -39,6 +39,11 @@ DEVICE MODE
  - interrupts : one interrupt entries must be specified for main interrupt.
  - num-ib-windows : number of inbound address translation windows
  - num-ob-windows : number of outbound address translation windows
+ - ti,syscon-unaligned-access: phandle to the syscon dt node. The 1st argument
+  should contain the register offset within syscon
+  and the 2nd argument should contain the bit field
+  for setting the bit to enable unaligned
+  access.
 
 Optional Property:
  - gpios : Should be added if a gpio line is required to drive PERST# line
-- 
1.7.9.5

Re: [lkp-robot] [blkcg] ad63af3cb7: BUG:sleeping_function_called_from_invalid_context_at_mm/slab.h

[Tahsin Erdogan]

This is a good catch!

I will post a v5 of the patch shortly to the other email thread.

On Wed, Mar 8, 2017 at 9:25 PM, kernel test robot  wrote:
>
> FYI, we noticed the following commit:
>
> commit: ad63af3cb70378a7f780dbef2387a6d13e53a6c9 ("blkcg: allocate struct 
> blkcg_gq outside request queue spinlock")
> url: 
> https://github.com/0day-ci/linux/commits/Tahsin-Erdogan/blkcg-allocate-struct-blkcg_gq-outside-request-queue-spinlock/20170307-030921
> base: https://git.kernel.org/cgit/linux/kernel/git/axboe/linux-block.git 
> for-next
>
> in testcase: boot
>
> on test machine: qemu-system-x86_64 -enable-kvm -cpu SandyBridge -m 512M
>
> caused below changes (please refer to attached dmesg/kmsg for entire 
> log/backtrace):
>
>
> ++++
> || 3695539290 
> | ad63af3cb7 |
> ++++
> | boot_successes | 12 
> | 12 |
> | boot_failures  | 8  
> | 20 |
> | BUG:kernel_hang_in_test_stage  | 8  
> ||
> | BUG:sleeping_function_called_from_invalid_context_at_mm/slab.h | 0  
> | 20 |
> ++++
>
>
>
> [   23.511528] BUG: sleeping function called from invalid context at 
> mm/slab.h:408
> [   23.543085] in_atomic(): 1, irqs_disabled(): 0, pid: 130, name: udevd
> [   23.563283] CPU: 0 PID: 130 Comm: udevd Not tainted 
> 4.10.0-rc7-00236-gad63af3 #1
> [   23.592056] Hardware name: QEMU Standard PC (i440FX + PIIX, 1996), BIOS 
> 1.9.3-20161025_171302-gandalf 04/01/2014
> [   23.625535] Call Trace:
> [   23.638139]  dump_stack+0x63/0x8a
> [   23.652227]  ___might_sleep+0xd3/0x120
> [   23.667071]  __might_sleep+0x4a/0x80
> [   23.681760]  kmem_cache_alloc_node_trace+0x1d6/0x1f0
> [   23.699087]  blkg_alloc+0x4b/0x230
> [   23.713446]  blkg_lookup_create+0x3dc/0x610
> [   23.729228]  ? blkg_alloc+0x158/0x230
> [   23.744066]  blkcg_init_queue+0x62/0x100
> [   23.759658]  blk_alloc_queue_node+0x25a/0x2c0
> [   23.775866]  ? set_fdc+0x130/0x130 [floppy]
> [   23.791487]  blk_init_queue_node+0x20/0x60
> [   23.807233]  blk_init_queue+0x13/0x20
> [   23.822104]  floppy_module_init+0x234/0xee2 [floppy]
> [   23.838763]  ? vunmap_page_range+0x221/0x390
> [   23.853604]  ? set_cmos+0x68/0x68 [floppy]
> [   23.868345]  do_one_initcall+0x43/0x180
> [   23.883582]  ? __might_sleep+0x4a/0x80
> [   23.898621]  ? kmem_cache_alloc_trace+0x163/0x1b0
> [   23.915435]  do_init_module+0x5f/0x1f8
> [   23.930273]  load_module+0x149e/0x1b10
> [   23.945372]  ? __symbol_put+0x40/0x40
> [   23.960025]  ? kernel_read_file+0x1a3/0x1c0
> [   23.975740]  ? kernel_read_file_from_fd+0x49/0x80
> [   23.992559]  SYSC_finit_module+0xbc/0xf0
> [   24.007991]  SyS_finit_module+0xe/0x10
> [   24.022920]  entry_SYSCALL_64_fastpath+0x1a/0xa9
> [   24.039327] RIP: 0033:0x7f9380e1f4a9
> [   24.053934] RSP: 002b:7ffc09ff8698 EFLAGS: 0202 ORIG_RAX: 
> 0139
> [   24.082614] RAX: ffda RBX: 00a64c20 RCX: 
> 7f9380e1f4a9
> [   24.103686] RDX:  RSI: 7f93810eb0aa RDI: 
> 0007
> [   24.124749] RBP: 7ffc09ff8690 R08:  R09: 
> 00a63490
> [   24.146260] R10: 0007 R11: 0202 R12: 
> 00a64c20
> [   24.167489] R13:  R14: 00a5a2f0 R15: 
> 00a63490
> [   24.191631] parport_pc 00:04: reported by Plug and Play ACPI
> [   24.254724] piix4_smbus :00:01.3: SMBus Host Controller at 0x700, 
> revision 0
> [   24.344624] libata version 3.00 loaded.
> [   24.355991] ata_piix :00:01.1: version 2.13
> [   24.380594] input: PC Speaker as /devices/platform/pcspkr/input/input4
> [   24.454024] scsi host0: ata_piix
> [   24.460472] scsi host1: ata_piix
> [   24.460962] ata1: PATA max MWDMA2 cmd 0x1f0 ctl 0x3f6 bmdma 0xc080 irq 14
> [   24.460985] ata2: PATA max MWDMA2 cmd 0x170 ctl 0x376 bmdma 0xc088 irq 15
> [   24.483223] Error: Driver 'pcspkr' is already registered, aborting...
> [   24.640449] ata2.01: NODEV after polling detection
> [   24.643436] ata2.00: ATAPI: QEMU DVD-ROM, 2.5+, max UDMA/100
> [   24.649435] ata2.00: configured for MWDMA2
> [   24.653487] BUG: sleeping function called from invalid context at 
> mm/slab.h:408
> [   24.653510] in_atomic(): 1, irqs_disabled(): 0, pid: 5, name: kworker/u2:0
> [   24.653515] CPU: 0 PID: 5 Comm: kworker/u2:0 Tainted: GW   
> 4.10.0-rc7-00236-gad63af3 #1
> [   24.653518] Hardware name: QEMU Standard PC (i440FX + PIIX, 1996), BIOS 
> 1.9.3-20161025_171302-gandalf 04/01/2014
> [   24.653548] Workqueue: events_unbound async_run_entry_fn
> [   24.653551] 

[PATCH v3 00/23] PCI: Support for configurable PCI endpoint

[Kishon Vijay Abraham I]

This patch series
 *) add PCI endpoint core layer
 *) modify designware and dra7xx driver to be configured in EP mode
 *) add a PCI endpoint *test* function driver and corresponding host
driver

Changes from v2:
*) changed the configfs structure as suggested by Christoph Hellwig. With
   this change the framework creates configfs entry for EP function driver
   and EP controller. Previously these entries have to be created by the
   the user. (Haven't changed the epc core or epf core except for invoking
   configfs APIs to create entries for EP function driver and EP controller.
   That's mostly because the EP function device can still be created by
   directly invoking the epf core API without using configfs).
*) Now the user has to use configfs entry 'start' to start the link.
   This was previously done by the function driver. However in the case of
   multi function EP, the function driver shouldn't start the link.

Changes from v1:
*) The preparation patches for adding EP support is removed and is sent
   separately
*) Added device ID for DRA74x/DRA72x and used it instead of
   using "PCI_ANY_ID"
*) Added userguide for PCI endpoint test function

Major Improvements from RFC:
 *) support multi-function devices (hw supported not virtual)
 *) Access host side buffers
 *) Raise MSI interrupts
 *) Add user space program to use the host side PCI driver
 *) Adapt all other users of designware to use the new design (only
compile tested. Since I have only dra7xx boards, the new design
has only been tested in dra7xx. I'd require the help of others
to test the platforms they have access to).

This series has been developed over 4.11-rc1 + [1]
This series has also been pushed to [2]

[1] -> https://www.mail-archive.com/linux-kernel@vger.kernel.org/msg1348667.html
[2] -> git://git.kernel.org/pub/scm/linux/kernel/git/kishon/pci-endpoint.git

Kishon Vijay Abraham I (23):
  PCI: endpoint: Add EP core layer to enable EP controller and EP
functions
  Documentation: PCI: Guide to use PCI Endpoint Core Layer
  PCI: endpoint: Introduce configfs entry for configuring EP functions
  Documentation: PCI: Guide to use pci endpoint configfs
  PCI: endpoint: Create configfs entry for EPC device and EPF driver
  Documentation: PCI: Add specification for the *pci test* function
device
  PCI: endpoint: functions: Add an EP function to test PCI
  Documentation: PCI: Add binding documentation for pci-test endpoint
function
  PCI: dwc: designware: Add EP mode support
  dt-bindings: PCI: Add dt bindings for pci designware EP mode
  PCI: dwc: dra7xx: Facilitate wrapper and msi interrupts to be enabled
independently
  PCI: dwc: dra7xx: Add EP mode support
  dt-bindings: PCI: dra7xx: Add dt bindings for pci dra7xx EP mode
  PCI: dwc: dra7xx: Workaround for errata id i870
  dt-bindings: PCI: dra7xx: Add dt bindings to enable unaligned access
  PCI: Add device IDs for DRA74x and DRA72x
  misc: Add host side pci driver for pci test function device
  Documentation: misc-devices: Add Documentation for pci-endpoint-test
driver
  tools: PCI: Add a userspace tool to test PCI endpoint
  tools: PCI: Add sample test script to invoke pcitest
  Documentation: PCI: Add userguide for PCI endpoint test function
  MAINTAINERS: add PCI EP maintainer
  ARM: DRA7: clockdomain: Change the CLKTRCTRL of CM_PCIE_CLKSTCTRL to
SW_WKUP

 Documentation/PCI/00-INDEX |   10 +
 .../PCI/endpoint/function/binding/pci-test.txt |   17 +
 Documentation/PCI/endpoint/pci-endpoint-cfs.txt|  105 
 Documentation/PCI/endpoint/pci-endpoint.txt|  215 
 Documentation/PCI/endpoint/pci-test-function.txt   |   66 +++
 Documentation/PCI/endpoint/pci-test-howto.txt  |  179 ++
 .../devicetree/bindings/pci/designware-pcie.txt|   26 +-
 Documentation/devicetree/bindings/pci/ti-pci.txt   |   42 +-
 Documentation/misc-devices/pci-endpoint-test.txt   |   35 ++
 MAINTAINERS|9 +
 arch/arm/mach-omap2/clockdomains7xx_data.c |2 +-
 drivers/Makefile   |2 +
 drivers/misc/Kconfig   |7 +
 drivers/misc/Makefile  |1 +
 drivers/misc/pci_endpoint_test.c   |  534 ++
 drivers/pci/Kconfig|1 +
 drivers/pci/dwc/Kconfig|   36 +-
 drivers/pci/dwc/Makefile   |5 +-
 drivers/pci/dwc/pci-dra7xx.c   |  274 -
 drivers/pci/dwc/pcie-designware-ep.c   |  340 
 drivers/pci/dwc/pcie-designware.c  |  136 +
 drivers/pci/dwc/pcie-designware.h  |   82 +++
 drivers/pci/endpoint/Kconfig   |   31 ++
 drivers/pci/endpoint/Makefile  |7 +
 drivers/pci/endpoint/functions/Kconfig |   12 +
 drivers/pci/endpoint/functio

Re: [PATCH v3] Input: sparse-keymap - use a managed allocation for keymap copy

[Michał Kępień]

> On Wed, Mar 8, 2017 at 11:05 PM, Dmitry Torokhov
>  wrote:
> > On Wed, Mar 08, 2017 at 10:50:16PM +0200, Andy Shevchenko wrote:
> >> On Wed, Mar 8, 2017 at 8:12 PM, Dmitry Torokhov
> >>  wrote:
> >> > On Wed, Mar 08, 2017 at 09:22:17AM +0100, Michał Kępień wrote:
> 
> >> If there PDx86 related patches are anticipated this cycle, definitely
> >> we need an immutable branch (perhaps based on v4.11-rc1).
> >
> > OK, I'll make one (based on 4.10 final - the patch should apply cleanly
> > there and there is no point of forcing anyone's workflow to use kernel
> > in the beginning of stabilization cycle).
> 
> Fine by me.
> 
> > As to whether there are PDx86 patches - I hope Michał will supply them
> > ;)
> 
> Michał, whenever you send the first one based on this change, please
> mention that it has dependency, I will pull the immutable branch at
> that time.

Noted.  I will prepare the patches and submit them within the next few
days.

-- 
Best regards,
Michał Kępień

[PATCH v3 19/23] tools: PCI: Add a userspace tool to test PCI endpoint

[Kishon Vijay Abraham I]

Add a userspace tool to invoke the ioctls exposed by the
PCI endpoint test driver to perform various PCI tests.

Signed-off-by: Kishon Vijay Abraham I 
---
 tools/pci/pcitest.c |  186 +++
 1 file changed, 186 insertions(+)
 create mode 100644 tools/pci/pcitest.c

diff --git a/tools/pci/pcitest.c b/tools/pci/pcitest.c
new file mode 100644
index 000..39b5b0b
--- /dev/null
+++ b/tools/pci/pcitest.c
@@ -0,0 +1,186 @@
+/**
+ * Userspace PCI Endpoint Test Module
+ *
+ * Copyright (C) 2017 Texas Instruments
+ * Author: Kishon Vijay Abraham I 
+ *
+ * This program is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 of
+ * the License as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see .
+ */
+
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+#include 
+
+#define BILLION 1E9
+
+static char *result[] = { "NOT OKAY", "OKAY" };
+
+struct pci_test {
+   char*device;
+   charbarnum;
+   boollegacyirq;
+   unsigned intmsinum;
+   boolread;
+   boolwrite;
+   boolcopy;
+   unsigned long   size;
+};
+
+static int run_test(struct pci_test *test)
+{
+   long ret;
+   int fd;
+   struct timespec start, end;
+   double time;
+
+   fd = open(test->device, O_RDWR);
+   if (fd < 0) {
+   perror("can't open PCI Endpoint Test device");
+   return fd;
+   }
+
+   if (test->barnum >= 0 && test->barnum <= 5) {
+   ret = ioctl(fd, PCITEST_BAR, test->barnum);
+   fprintf(stdout, "BAR%d:\t\t", test->barnum);
+   if (ret < 0)
+   fprintf(stdout, "TEST FAILED\n");
+   else
+   fprintf(stdout, "%s\n", result[ret]);
+   }
+
+   if (test->legacyirq) {
+   ret = ioctl(fd, PCITEST_LEGACY_IRQ, 0);
+   fprintf(stdout, "LEGACY IRQ:\t");
+   if (ret < 0)
+   fprintf(stdout, "TEST FAILED\n");
+   else
+   fprintf(stdout, "%s\n", result[ret]);
+   }
+
+   if (test->msinum > 0 && test->msinum <= 32) {
+   ret = ioctl(fd, PCITEST_MSI, test->msinum);
+   fprintf(stdout, "MSI%d:\t\t", test->msinum);
+   if (ret < 0)
+   fprintf(stdout, "TEST FAILED\n");
+   else
+   fprintf(stdout, "%s\n", result[ret]);
+   }
+
+   if (test->write) {
+   ret = ioctl(fd, PCITEST_WRITE, test->size);
+   fprintf(stdout, "WRITE (%7ld bytes):\t\t", test->size);
+   if (ret < 0)
+   fprintf(stdout, "TEST FAILED\n");
+   else
+   fprintf(stdout, "%s\n", result[ret]);
+   }
+
+   if (test->read) {
+   ret = ioctl(fd, PCITEST_READ, test->size);
+   fprintf(stdout, "READ (%7ld bytes):\t\t", test->size);
+   if (ret < 0)
+   fprintf(stdout, "TEST FAILED\n");
+   else
+   fprintf(stdout, "%s\n", result[ret]);
+   }
+
+   if (test->copy) {
+   ret = ioctl(fd, PCITEST_COPY, test->size);
+   fprintf(stdout, "COPY (%7ld bytes):\t\t", test->size);
+   if (ret < 0)
+   fprintf(stdout, "TEST FAILED\n");
+   else
+   fprintf(stdout, "%s\n", result[ret]);
+   }
+
+   fflush(stdout);
+}
+
+int main(int argc, char **argv)
+{
+   int c;
+   struct pci_test *test;
+
+   test = calloc(1, sizeof(*test));
+   if (!test) {
+   perror("Fail to allocate memory for pci_test\n");
+   return -ENOMEM;
+   }
+
+   /* since '0' is a valid BAR number, initialize it to -1 */
+   test->barnum = -1;
+
+   /* set default size as 100KB */
+   test->size = 0x19000;
+
+   /* set default endpoint device */
+   test->device = "/dev/pci-endpoint-test.0";
+
+   while ((c = getopt(argc, argv, "D:b:m:lrwcs:")) != EOF)
+   switch (c) {
+   case 'D':
+   test->device = optarg;
+   continue;
+   case 'b':
+   test->barnum = atoi(optarg);
+   if (test->barnum < 0 || test->barnum > 5)
+   goto usage;
+   continue;
+   case 'l':
+   test->legacyirq = true;
+   cont

[PATCH v3 11/23] PCI: dwc: dra7xx: Facilitate wrapper and msi interrupts to be enabled independently

[Kishon Vijay Abraham I]

No functional change. Split dra7xx_pcie_enable_interrupts into
dra7xx_pcie_enable_wrapper_interrupts and dra7xx_pcie_enable_msi_interrupts
so that wrapper interrupts and msi interrupts can be enabled independently.
This is in preparation for adding EP mode support to dra7xx driver since
EP mode doesn't have to enable msi_interrupts.

Signed-off-by: Kishon Vijay Abraham I 
---
 drivers/pci/dwc/pci-dra7xx.c |   24 ++--
 1 file changed, 18 insertions(+), 6 deletions(-)

diff --git a/drivers/pci/dwc/pci-dra7xx.c b/drivers/pci/dwc/pci-dra7xx.c
index 8c53233..be5ebfa 100644
--- a/drivers/pci/dwc/pci-dra7xx.c
+++ b/drivers/pci/dwc/pci-dra7xx.c
@@ -140,18 +140,30 @@ static int dra7xx_pcie_establish_link(struct dra7xx_pcie 
*dra7xx)
return dw_pcie_wait_for_link(pci);
 }
 
-static void dra7xx_pcie_enable_interrupts(struct dra7xx_pcie *dra7xx)
+static void dra7xx_pcie_enable_msi_interrupts(struct dra7xx_pcie *dra7xx)
 {
-   dra7xx_pcie_writel(dra7xx, PCIECTRL_DRA7XX_CONF_IRQSTATUS_MAIN,
-  ~INTERRUPTS);
-   dra7xx_pcie_writel(dra7xx,
-  PCIECTRL_DRA7XX_CONF_IRQENABLE_SET_MAIN, INTERRUPTS);
dra7xx_pcie_writel(dra7xx, PCIECTRL_DRA7XX_CONF_IRQSTATUS_MSI,
   ~LEG_EP_INTERRUPTS & ~MSI);
-   dra7xx_pcie_writel(dra7xx, PCIECTRL_DRA7XX_CONF_IRQENABLE_SET_MSI,
+
+   dra7xx_pcie_writel(dra7xx,
+  PCIECTRL_DRA7XX_CONF_IRQENABLE_SET_MSI,
   MSI | LEG_EP_INTERRUPTS);
 }
 
+static void dra7xx_pcie_enable_wrapper_interrupts(struct dra7xx_pcie *dra7xx)
+{
+   dra7xx_pcie_writel(dra7xx, PCIECTRL_DRA7XX_CONF_IRQSTATUS_MAIN,
+  ~INTERRUPTS);
+   dra7xx_pcie_writel(dra7xx, PCIECTRL_DRA7XX_CONF_IRQENABLE_SET_MAIN,
+  INTERRUPTS);
+}
+
+static void dra7xx_pcie_enable_interrupts(struct dra7xx_pcie *dra7xx)
+{
+   dra7xx_pcie_enable_wrapper_interrupts(dra7xx);
+   dra7xx_pcie_enable_msi_interrupts(dra7xx);
+}
+
 static void dra7xx_pcie_host_init(struct pcie_port *pp)
 {
struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
-- 
1.7.9.5

Re: ath9k_htc: Add support of AirTies 1eda:2315 AR9271 device

[Kalle Valo]

Dmitry Tunin  wrote:
> T:  Bus=01 Lev=02 Prnt=02 Port=02 Cnt=01 Dev#=  7 Spd=480 MxCh= 0
> D:  Ver= 2.00 Cls=ff(vend.) Sub=ff Prot=ff MxPS=64 #Cfgs=  1
> P:  Vendor=1eda ProdID=2315 Rev=01.08
> S:  Manufacturer=ATHEROS
> S:  Product=USB2.0 WLAN
> S:  SerialNumber=12345
> C:  #Ifs= 1 Cfg#= 1 Atr=80 MxPwr=500mA
> I:  If#= 0 Alt= 0 #EPs= 6 Cls=ff(vend.) Sub=00 Prot=00 Driver=(none)
> 
> Signed-off-by: Dmitry Tunin 
> Cc: sta...@vger.kernel.org

Patch applied to ath-next branch of ath.git, thanks.

16ff1fb0e32f ath9k_htc: Add support of AirTies 1eda:2315 AR9271 device

-- 
https://patchwork.kernel.org/patch/9577679/

Documentation about submitting wireless patches and checking status
from patchwork:

https://wireless.wiki.kernel.org/en/developers/documentation/submittingpatches

Re: Arrays of variable length

[Tomas Winkler]

On Mon, Mar 6, 2017 at 2:31 AM, Måns Rullgård  wrote:
> Henrique de Moraes Holschuh  writes:
>
>> On Sun, 05 Mar 2017, Måns Rullgård wrote:
>>> Tomas Winkler  writes:
>>> > Sparse complains for arrays declared with variable length
>>> >
>>> > 'warning: Variable length array is used'
>>> >
>>> > Prior to c99 this was not allowed but lgcc (c99) doesn't have problem
>>> > with that  https://gcc.gnu.org/onlinedocs/gcc/Variable-Length.html.
>>> > And also Linux kernel compilation with W=1 doesn't complain.
>>> >
>>> > Since sparse is used extensively would like to ask what is the correct
>>> > usage of arrays of variable length
>>> > within Linux Kernel.
>>>
>>> Variable-length arrays are a very bad idea.  Don't use them, ever.
>>> If the size has a sane upper bound, just use that value statically.
>>> Otherwise, you have a stack overflow waiting to happen and should be
>>> using some kind of dynamic allocation instead.
>>>
>>> Furthermore, use of VLAs generally results in less efficient code.  For
>>> instance, it forces gcc to waste a register for the frame pointer, and
>>> it often prevents inlining.
>>
>> Well, if we're going to forbid VLAs in the kernel, IMHO the kernel build
>> system should call gcc with -Werror=vla to get that point across early,
>> and flush out any offenders.
>
> If it were up to me, that's exactly what I'd do.

>
Some parts of the kernel depends on VLA such as ___ON_STACK macros in
include/crypto/hash.h
It's actually pretty neat implementation, maybe it's too harsh to
disable  VLA completely.

Tomas

[PATCH v3 22/23] MAINTAINERS: add PCI EP maintainer

[Kishon Vijay Abraham I]

Add maintainer for the newly introduced PCI EP framework.

Signed-off-by: Kishon Vijay Abraham I 
---
 MAINTAINERS |9 +
 1 file changed, 9 insertions(+)

diff --git a/MAINTAINERS b/MAINTAINERS
index c265a5f..3c1b947 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -9581,6 +9581,15 @@ F:   include/linux/pci*
 F: arch/x86/pci/
 F: arch/x86/kernel/quirks.c
 
+PCI EP SUBSYSTEM
+M: Kishon Vijay Abraham I 
+L: linux-...@vger.kernel.org
+T: git 
git://git.kernel.org/pub/scm/linux/kernel/git/kishon/pci-endpoint.git
+S: Supported
+F: drivers/pci/endpoint/
+F: drivers/misc/pci_endpoint_test.c
+F: tools/pci/
+
 PCI DRIVER FOR ALTERA PCIE IP
 M: Ley Foon Tan 
 L: r...@lists.rocketboards.org (moderated for non-subscribers)
-- 
1.7.9.5

[PATCH v3 12/23] PCI: dwc: dra7xx: Add EP mode support

[Kishon Vijay Abraham I]

The PCIe controller integrated in dra7xx SoCs is capable of operating
in endpoint mode. Add endpoint mode support to dra7xx driver.

Signed-off-by: Kishon Vijay Abraham I 
---
 drivers/pci/dwc/Kconfig   |   31 +-
 drivers/pci/dwc/Makefile  |4 +-
 drivers/pci/dwc/pci-dra7xx.c  |  197 ++---
 drivers/pci/dwc/pcie-designware.h |7 ++
 4 files changed, 221 insertions(+), 18 deletions(-)

diff --git a/drivers/pci/dwc/Kconfig b/drivers/pci/dwc/Kconfig
index 00335c7..96e6d17 100644
--- a/drivers/pci/dwc/Kconfig
+++ b/drivers/pci/dwc/Kconfig
@@ -16,14 +16,37 @@ config PCIE_DW_EP
 
 config PCI_DRA7XX
bool "TI DRA7xx PCIe controller"
-   depends on PCI
+   depends on (PCI && PCI_MSI_IRQ_DOMAIN) || PCI_ENDPOINT
depends on OF && HAS_IOMEM && TI_PIPE3
+   help
+Enables support for the PCIe controller in the DRA7xx SoC. There
+are two instances of PCIe controller in DRA7xx. This controller can
+work either as EP or RC. In order to enable host specific features
+PCI_DRA7XX_HOST must be selected and in order to enable device
+specific features PCI_DRA7XX_EP must be selected. This uses
+the Designware core.
+
+if PCI_DRA7XX
+
+config PCI_DRA7XX_HOST
+   bool "PCI DRA7xx Host Mode"
+   depends on PCI
depends on PCI_MSI_IRQ_DOMAIN
select PCIE_DW_HOST
+   default y
help
-Enables support for the PCIe controller in the DRA7xx SoC.  There
-are two instances of PCIe controller in DRA7xx.  This controller can
-act both as EP and RC.  This reuses the Designware core.
+Enables support for the PCIe controller in the DRA7xx SoC to work in
+host mode.
+
+config PCI_DRA7XX_EP
+   bool "PCI DRA7xx Endpoint Mode"
+   depends on PCI_ENDPOINT
+   select PCIE_DW_EP
+   help
+Enables support for the PCIe controller in the DRA7xx SoC to work in
+endpoint mode.
+
+endif
 
 config PCIE_DW_PLAT
bool "Platform bus based DesignWare PCIe Controller"
diff --git a/drivers/pci/dwc/Makefile b/drivers/pci/dwc/Makefile
index b38425d..f31a859 100644
--- a/drivers/pci/dwc/Makefile
+++ b/drivers/pci/dwc/Makefile
@@ -2,7 +2,9 @@ obj-$(CONFIG_PCIE_DW) += pcie-designware.o
 obj-$(CONFIG_PCIE_DW_HOST) += pcie-designware-host.o
 obj-$(CONFIG_PCIE_DW_EP) += pcie-designware-ep.o
 obj-$(CONFIG_PCIE_DW_PLAT) += pcie-designware-plat.o
-obj-$(CONFIG_PCI_DRA7XX) += pci-dra7xx.o
+ifneq ($(filter y,$(CONFIG_PCI_DRA7XX_HOST) $(CONFIG_PCI_DRA7XX_EP)),)
+obj-$(CONFIG_PCI_DRA7XX) += pci-dra7xx.o
+endif
 obj-$(CONFIG_PCI_EXYNOS) += pci-exynos.o
 obj-$(CONFIG_PCI_IMX6) += pci-imx6.o
 obj-$(CONFIG_PCIE_SPEAR13XX) += pcie-spear13xx.o
diff --git a/drivers/pci/dwc/pci-dra7xx.c b/drivers/pci/dwc/pci-dra7xx.c
index be5ebfa..1cd5c2b 100644
--- a/drivers/pci/dwc/pci-dra7xx.c
+++ b/drivers/pci/dwc/pci-dra7xx.c
@@ -10,12 +10,14 @@
  * published by the Free Software Foundation.
  */
 
+#include 
 #include 
 #include 
 #include 
 #include 
 #include 
 #include 
+#include 
 #include 
 #include 
 #include 
@@ -57,6 +59,11 @@
 #defineMSI BIT(4)
 #defineLEG_EP_INTERRUPTS (INTA | INTB | INTC | INTD)
 
+#definePCIECTRL_TI_CONF_DEVICE_TYPE0x0100
+#defineDEVICE_TYPE_EP  0x0
+#defineDEVICE_TYPE_LEG_EP  0x1
+#defineDEVICE_TYPE_RC  0x4
+
 #definePCIECTRL_DRA7XX_CONF_DEVICE_CMD 0x0104
 #defineLTSSM_EN0x1
 
@@ -66,6 +73,13 @@
 
 #define EXP_CAP_ID_OFFSET  0x70
 
+#definePCIECTRL_TI_CONF_INTX_ASSERT0x0124
+#definePCIECTRL_TI_CONF_INTX_DEASSERT  0x0128
+
+#definePCIECTRL_TI_CONF_MSI_XMT0x012c
+#define MSI_REQ_GRANT  BIT(0)
+#define MSI_VECTOR_SHIFT   7
+
 struct dra7xx_pcie {
struct dw_pcie  *pci;
void __iomem*base;  /* DT ti_conf */
@@ -73,6 +87,11 @@ struct dra7xx_pcie {
struct phy  **phy;
int link_gen;
struct irq_domain   *irq_domain;
+   enum dw_pcie_device_mode mode;
+};
+
+struct dra7xx_pcie_of_data {
+   enum dw_pcie_device_mode mode;
 };
 
 #define to_dra7xx_pcie(x)  dev_get_drvdata((x)->dev)
@@ -101,9 +120,19 @@ static int dra7xx_pcie_link_up(struct dw_pcie *pci)
return !!(reg & LINK_UP);
 }
 
-static int dra7xx_pcie_establish_link(struct dra7xx_pcie *dra7xx)
+static void dra7xx_pcie_stop_link(struct dw_pcie *pci)
 {
-   struct dw_pcie *pci = dra7xx->pci;
+   struct dra7xx_pcie *dra7xx = to_dra7xx_pcie(pci);
+   u32 reg;
+
+   reg = dra7xx_pcie_readl(dra7xx, PCI

[PATCH v1] perf report: Drop cycles 0 for LBR print

[Jin Yao]

For some platforms, for example Broadwell, it doesn't support cycles
for LBR. But the perf always prints cycles:0, it's not necessary.

The patch refactors the LBR info print code and drops the cycles:0.

For example: perf report --branch-history --no-children --stdio

On Broadwell:
--0.91%--__random_r random_r.c:394 (iterations:2)
  __random_r random_r.c:360 (predicted:0.0%)
  __random_r random_r.c:380 (predicted:0.0%)
  __random_r random_r.c:357

On Skylake:
--1.07%--main div.c:39 (predicted:52.4% cycles:1 iterations:17)
  main div.c:44 (predicted:52.4% cycles:1)
  main div.c:42 (cycles:2)
  compute_flag div.c:28 (cycles:2)
  compute_flag div.c:27 (cycles:1)
  rand rand.c:28 (cycles:1)
  rand rand.c:28 (cycles:1)
  __random random.c:298 (cycles:1)
  __random random.c:297 (cycles:1)
  __random random.c:295 (cycles:1)
  __random random.c:295 (cycles:1)
  __random random.c:295 (cycles:1)

Signed-off-by: Jin Yao 
---
 tools/perf/util/callchain.c | 111 +---
 1 file changed, 74 insertions(+), 37 deletions(-)

diff --git a/tools/perf/util/callchain.c b/tools/perf/util/callchain.c
index aba9534..f84626d 100644
--- a/tools/perf/util/callchain.c
+++ b/tools/perf/util/callchain.c
@@ -1063,63 +1063,100 @@ int callchain_branch_counts(struct callchain_root 
*root,
  cycles_count);
 }
 
-static int callchain_counts_printf(FILE *fp, char *bf, int bfsize,
-  u64 branch_count, u64 predicted_count,
-  u64 abort_count, u64 cycles_count,
-  u64 iter_count, u64 samples_count)
+static int counts_str_build(char *bf, int bfsize,
+u64 branch_count, u64 predicted_count,
+u64 abort_count, u64 cycles_count,
+u64 iter_count, u64 samples_count)
 {
double predicted_percent = 0.0;
const char *null_str = "";
char iter_str[32];
-   char *str;
-   u64 cycles = 0;
-
-   if (branch_count == 0) {
-   if (fp)
-   return fprintf(fp, " (calltrace)");
+   char cycle_str[32];
+   char *istr, *cstr;
+   u64 cycles;
 
+   if (branch_count == 0)
return scnprintf(bf, bfsize, " (calltrace)");
-   }
+
+   cycles = cycles_count / branch_count;
 
if (iter_count && samples_count) {
-   scnprintf(iter_str, sizeof(iter_str),
-", iterations:%" PRId64 "",
-iter_count / samples_count);
-   str = iter_str;
+   if (cycles > 0)
+   scnprintf(iter_str, sizeof(iter_str),
+" iterations:%" PRId64 "",
+iter_count / samples_count);
+   else
+   scnprintf(iter_str, sizeof(iter_str),
+"iterations:%" PRId64 "",
+iter_count / samples_count);
+   istr = iter_str;
+   } else
+   istr = (char *)null_str;
+
+   if (cycles > 0) {
+   scnprintf(cycle_str, sizeof(cycle_str),
+ "cycles:%" PRId64 "", cycles);
+   cstr = cycle_str;
} else
-   str = (char *)null_str;
+   cstr = (char *)null_str;
 
predicted_percent = predicted_count * 100.0 / branch_count;
-   cycles = cycles_count / branch_count;
 
-   if ((predicted_percent >= 100.0) && (abort_count == 0)) {
-   if (fp)
-   return fprintf(fp, " (cycles:%" PRId64 "%s)",
-  cycles, str);
+   if ((predicted_count == branch_count) && (abort_count == 0)) {
+   if ((cycles > 0) || (istr != (char *)null_str))
+   return scnprintf(bf, bfsize, " (%s%s)", cstr, istr);
+   else
+   return scnprintf(bf, bfsize, "%s", (char *)null_str);
+   }
 
-   return scnprintf(bf, bfsize, " (cycles:%" PRId64 "%s)",
-cycles, str);
+   if ((predicted_count < branch_count) && (abort_count == 0)) {
+   if ((cycles > 0) || (istr != (char *)null_str))
+   return scnprintf(bf, bfsize,
+   " (predicted:%.1f%% %s%s)",
+   predicted_percent, cstr, istr);
+   else {
+   return scnprintf(bf, bfsize,
+   " (predicted:%.1f%%)",
+   predicted_percent);
+   }
}
 
-   if ((predicted_percent < 100.0) && (abort_count == 0)) {
-   if (fp)
-   return fprintf(fp,
-   "

Re: wcn36xx: Fix error handling

[Kalle Valo]

Christophe Jaillet  wrote:
> Reorder 'out_free_dxe_pool' and 'out_free_dxe_ctl' error handling labels
> in order to match the way resources have been allocated.
> 
> Signed-off-by: Christophe JAILLET 

Patch applied to ath-next branch of ath.git, thanks.

4aa2d31f5df8 wcn36xx: Fix error handling

-- 
https://patchwork.kernel.org/patch/9581709/

Documentation about submitting wireless patches and checking status
from patchwork:

https://wireless.wiki.kernel.org/en/developers/documentation/submittingpatches

[PATCH v3 20/23] tools: PCI: Add sample test script to invoke pcitest

[Kishon Vijay Abraham I]

Add a simple test script that invokes the pcitest userspace tool
to perform all the PCI endpoint tests (BAR tests, interrupt tests,
read tests, write tests and copy tests).

Signed-off-by: Kishon Vijay Abraham I 
---
 tools/pci/pcitest.sh |   56 ++
 1 file changed, 56 insertions(+)
 create mode 100644 tools/pci/pcitest.sh

diff --git a/tools/pci/pcitest.sh b/tools/pci/pcitest.sh
new file mode 100644
index 000..5442bbe
--- /dev/null
+++ b/tools/pci/pcitest.sh
@@ -0,0 +1,56 @@
+#!/bin/sh
+
+echo "BAR tests"
+echo
+
+bar=0
+
+while [ $bar -lt 6 ]
+do
+   pcitest -b $bar
+   bar=`expr $bar + 1`
+done
+echo
+
+echo "Interrupt tests"
+echo
+
+pcitest -l
+msi=1
+
+while [ $msi -lt 33 ]
+do
+pcitest -m $msi
+msi=`expr $msi + 1`
+done
+echo
+
+echo "Read Tests"
+echo
+
+pcitest -r -s 1
+pcitest -r -s 1024
+pcitest -r -s 1025
+pcitest -r -s 1024000
+pcitest -r -s 1024001
+echo
+
+echo "Write Tests"
+echo
+
+pcitest -w -s 1
+pcitest -w -s 1024
+pcitest -w -s 1025
+pcitest -w -s 1024000
+pcitest -w -s 1024001
+echo
+
+echo "Copy Tests"
+echo
+
+pcitest -c -s 1
+pcitest -c -s 1024
+pcitest -c -s 1025
+pcitest -c -s 1024000
+pcitest -c -s 1024001
+echo
-- 
1.7.9.5

[PATCH v3 09/23] PCI: dwc: designware: Add EP mode support

[Kishon Vijay Abraham I]

Add endpoint mode support to designware driver. This uses the
EP Core layer introduced recently to add endpoint mode support.
*Any* function driver can now use this designware device
in order to achieve the EP functionality.

Signed-off-by: Kishon Vijay Abraham I 
---
 drivers/pci/dwc/Kconfig  |5 +
 drivers/pci/dwc/Makefile |1 +
 drivers/pci/dwc/pcie-designware-ep.c |  340 ++
 drivers/pci/dwc/pcie-designware.c|  136 ++
 drivers/pci/dwc/pcie-designware.h|   75 
 5 files changed, 557 insertions(+)
 create mode 100644 drivers/pci/dwc/pcie-designware-ep.c

diff --git a/drivers/pci/dwc/Kconfig b/drivers/pci/dwc/Kconfig
index dfb8a69..00335c7 100644
--- a/drivers/pci/dwc/Kconfig
+++ b/drivers/pci/dwc/Kconfig
@@ -9,6 +9,11 @@ config PCIE_DW_HOST
depends on PCI_MSI_IRQ_DOMAIN
 select PCIE_DW
 
+config PCIE_DW_EP
+   bool
+   depends on PCI_ENDPOINT
+   select PCIE_DW
+
 config PCI_DRA7XX
bool "TI DRA7xx PCIe controller"
depends on PCI
diff --git a/drivers/pci/dwc/Makefile b/drivers/pci/dwc/Makefile
index a2df13c..b38425d 100644
--- a/drivers/pci/dwc/Makefile
+++ b/drivers/pci/dwc/Makefile
@@ -1,5 +1,6 @@
 obj-$(CONFIG_PCIE_DW) += pcie-designware.o
 obj-$(CONFIG_PCIE_DW_HOST) += pcie-designware-host.o
+obj-$(CONFIG_PCIE_DW_EP) += pcie-designware-ep.o
 obj-$(CONFIG_PCIE_DW_PLAT) += pcie-designware-plat.o
 obj-$(CONFIG_PCI_DRA7XX) += pci-dra7xx.o
 obj-$(CONFIG_PCI_EXYNOS) += pci-exynos.o
diff --git a/drivers/pci/dwc/pcie-designware-ep.c 
b/drivers/pci/dwc/pcie-designware-ep.c
new file mode 100644
index 000..6e1ed1b
--- /dev/null
+++ b/drivers/pci/dwc/pcie-designware-ep.c
@@ -0,0 +1,340 @@
+/**
+ * Synopsys Designware PCIe Endpoint controller driver
+ *
+ * Copyright (C) 2017 Texas Instruments
+ * Author: Kishon Vijay Abraham I 
+ *
+ * This program is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 of
+ * the License as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see .
+ */
+
+#include 
+
+#include "pcie-designware.h"
+#include 
+#include 
+
+void dw_pcie_ep_linkup(struct dw_pcie_ep *ep)
+{
+   struct pci_epc *epc = ep->epc;
+
+   pci_epc_linkup(epc);
+}
+
+static void dw_pcie_ep_reset_bar(struct dw_pcie *pci, enum pci_barno bar)
+{
+   u32 reg;
+
+   reg = PCI_BASE_ADDRESS_0 + (4 * bar);
+   dw_pcie_write_dbi(pci, pci->dbi_base2, reg, 0x4, 0x0);
+   dw_pcie_write_dbi(pci, pci->dbi_base, reg, 0x4, 0x0);
+}
+
+static int dw_pcie_ep_write_header(struct pci_epc *epc,
+  struct pci_epf_header *hdr)
+{
+   struct dw_pcie_ep *ep = epc_get_drvdata(epc);
+   struct dw_pcie *pci = to_dw_pcie_from_ep(ep);
+   void __iomem *base = pci->dbi_base;
+
+   dw_pcie_write_dbi(pci, base, PCI_VENDOR_ID, 0x2, hdr->vendorid);
+   dw_pcie_write_dbi(pci, base, PCI_DEVICE_ID, 0x2, hdr->deviceid);
+   dw_pcie_write_dbi(pci, base, PCI_REVISION_ID, 0x1, hdr->revid);
+   dw_pcie_write_dbi(pci, base, PCI_CLASS_PROG, 0x1, hdr->progif_code);
+   dw_pcie_write_dbi(pci, base, PCI_CLASS_DEVICE, 0x2,
+ hdr->subclass_code | hdr->baseclass_code << 8);
+   dw_pcie_write_dbi(pci, base, PCI_CACHE_LINE_SIZE, 0x1,
+ hdr->cache_line_size);
+   dw_pcie_write_dbi(pci, base, PCI_SUBSYSTEM_VENDOR_ID, 0x2,
+ hdr->subsys_vendor_id);
+   dw_pcie_write_dbi(pci, base, PCI_SUBSYSTEM_ID, 0x2, hdr->subsys_id);
+   dw_pcie_write_dbi(pci, base, PCI_INTERRUPT_PIN, 0x1,
+ hdr->interrupt_pin);
+
+   return 0;
+}
+
+static int dw_pcie_ep_inbound_atu(struct dw_pcie_ep *ep, enum pci_barno bar,
+ dma_addr_t cpu_addr,
+ enum dw_pcie_as_type as_type)
+{
+   int ret;
+   u32 free_win;
+   struct dw_pcie *pci = to_dw_pcie_from_ep(ep);
+
+   free_win = find_first_zero_bit(&ep->ib_window_map,
+  sizeof(ep->ib_window_map));
+   if (free_win >= ep->num_ib_windows) {
+   dev_err(pci->dev, "no free inbound window\n");
+   return -EINVAL;
+   }
+
+   ret = dw_pcie_prog_inbound_atu(pci, free_win, bar, cpu_addr,
+  as_type);
+   if (ret < 0) {
+   dev_err(pci->dev, "Failed to program IB window\n");
+   return ret;
+   }
+
+   ep->bar_to_atu[bar] = free_win;
+   set_bit(free_

[PATCH v3 23/23] ARM: DRA7: clockdomain: Change the CLKTRCTRL of CM_PCIE_CLKSTCTRL to SW_WKUP

[Kishon Vijay Abraham I]

The PCIe programming sequence in TRM suggests CLKSTCTRL of PCIe should
be set to SW_WKUP. There are no issues when CLKSTCTRL is set to HW_AUTO
in RC mode. However in EP mode, the host system is not able to access the
MEMSPACE and setting the CLKSTCTRL to SW_WKUP fixes it.

Acked-by: Tony Lindgren 
Signed-off-by: Kishon Vijay Abraham I 
---
 arch/arm/mach-omap2/clockdomains7xx_data.c |2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/arch/arm/mach-omap2/clockdomains7xx_data.c 
b/arch/arm/mach-omap2/clockdomains7xx_data.c
index 6c67965..67ebff8 100644
--- a/arch/arm/mach-omap2/clockdomains7xx_data.c
+++ b/arch/arm/mach-omap2/clockdomains7xx_data.c
@@ -524,7 +524,7 @@
.dep_bit  = DRA7XX_PCIE_STATDEP_SHIFT,
.wkdep_srcs   = pcie_wkup_sleep_deps,
.sleepdep_srcs= pcie_wkup_sleep_deps,
-   .flags= CLKDM_CAN_HWSUP_SWSUP,
+   .flags= CLKDM_CAN_SWSUP,
 };
 
 static struct clockdomain atl_7xx_clkdm = {
-- 
1.7.9.5

[PATCH v3 14/23] PCI: dwc: dra7xx: Workaround for errata id i870

[Kishon Vijay Abraham I]

According to errata i870, access to the PCIe slave port
that are not 32-bit aligned will result in incorrect mapping
to TLP Address and Byte enable fields.

Accessing non 32-bit aligned data causes incorrect data in the target
buffer if memcpy is used. Implement the workaround for this
errata here.

Signed-off-by: Kishon Vijay Abraham I 
---
 drivers/pci/dwc/pci-dra7xx.c |   53 ++
 1 file changed, 53 insertions(+)

diff --git a/drivers/pci/dwc/pci-dra7xx.c b/drivers/pci/dwc/pci-dra7xx.c
index 1cd5c2b..71783a6 100644
--- a/drivers/pci/dwc/pci-dra7xx.c
+++ b/drivers/pci/dwc/pci-dra7xx.c
@@ -26,6 +26,8 @@
 #include 
 #include 
 #include 
+#include 
+#include 
 
 #include "pcie-designware.h"
 
@@ -528,6 +530,51 @@ static int dra7xx_pcie_enable_phy(struct dra7xx_pcie 
*dra7xx)
{},
 };
 
+/*
+ * dra7xx_pcie_ep_unaligned_memaccess: workaround for AM572x/AM571x Errata i870
+ * @dra7xx: the dra7xx device where the workaround should be applied
+ *
+ * Access to the PCIe slave port that are not 32-bit aligned will result
+ * in incorrect mapping to TLP Address and Byte enable fields. Therefore,
+ * byte and half-word accesses are not possible to byte offset 0x1, 0x2, or
+ * 0x3.
+ *
+ * To avoid this issue set PCIE_SS1_AXI2OCP_LEGACY_MODE_ENABLE to 1.
+ */
+static int dra7xx_pcie_ep_unaligned_memaccess(struct device *dev)
+{
+   int ret;
+   struct device_node *np = dev->of_node;
+   struct regmap *regmap;
+   unsigned int reg;
+   unsigned int field;
+
+   regmap = syscon_regmap_lookup_by_phandle(np,
+"ti,syscon-unaligned-access");
+   if (IS_ERR(regmap)) {
+   dev_dbg(dev, "can't get ti,syscon-unaligned-access\n");
+   return -EINVAL;
+   }
+
+   if (of_property_read_u32_index(np, "ti,syscon-unaligned-access", 1,
+  ®)) {
+   dev_err(dev, "couldn't get legacy mode register offset\n");
+   return -EINVAL;
+   }
+
+   if (of_property_read_u32_index(np, "ti,syscon-unaligned-access", 2,
+  &field)) {
+   dev_err(dev, "can't get bit field for setting legacy mode\n");
+   return -EINVAL;
+   }
+
+   ret = regmap_update_bits(regmap, reg, field, field);
+   if (ret)
+   dev_err(dev, "failed to enable unaligned access\n");
+
+   return ret;
+}
+
 static int __init dra7xx_pcie_probe(struct platform_device *pdev)
 {
u32 reg;
@@ -637,6 +684,7 @@ static int __init dra7xx_pcie_probe(struct platform_device 
*pdev)
case DW_PCIE_RC_TYPE:
dra7xx_pcie_writel(dra7xx, PCIECTRL_TI_CONF_DEVICE_TYPE,
   DEVICE_TYPE_RC);
+
ret = dra7xx_add_pcie_port(dra7xx, pdev);
if (ret < 0)
goto err_gpio;
@@ -644,6 +692,11 @@ static int __init dra7xx_pcie_probe(struct platform_device 
*pdev)
case DW_PCIE_EP_TYPE:
dra7xx_pcie_writel(dra7xx, PCIECTRL_TI_CONF_DEVICE_TYPE,
   DEVICE_TYPE_EP);
+
+   ret = dra7xx_pcie_ep_unaligned_memaccess(dev);
+   if (ret)
+   goto err_gpio;
+
ret = dra7xx_add_pcie_ep(dra7xx, pdev);
if (ret < 0)
goto err_gpio;
-- 
1.7.9.5

[PATCH v3 01/23] PCI: endpoint: Add EP core layer to enable EP controller and EP functions

[Kishon Vijay Abraham I]

Introduce a new EP core layer in order to support endpoint functions
in linux kernel. This comprises of EPC library
(Endpoint Controller Library) and EPF library (Endpoint
Function Library). EPC library implements functions that is specific
to an endpoint controller and EPF library implements functions
that is specific to an endpoint function.

Signed-off-by: Kishon Vijay Abraham I 
---
 drivers/Makefile|2 +
 drivers/pci/Kconfig |1 +
 drivers/pci/endpoint/Kconfig|   20 ++
 drivers/pci/endpoint/Makefile   |6 +
 drivers/pci/endpoint/pci-epc-core.c |  575 +++
 drivers/pci/endpoint/pci-epc-mem.c  |  143 +
 drivers/pci/endpoint/pci-epf-core.c |  347 +
 include/linux/mod_devicetable.h |   10 +
 include/linux/pci-epc.h |  142 +
 include/linux/pci-epf.h |  160 ++
 10 files changed, 1406 insertions(+)
 create mode 100644 drivers/pci/endpoint/Kconfig
 create mode 100644 drivers/pci/endpoint/Makefile
 create mode 100644 drivers/pci/endpoint/pci-epc-core.c
 create mode 100644 drivers/pci/endpoint/pci-epc-mem.c
 create mode 100644 drivers/pci/endpoint/pci-epf-core.c
 create mode 100644 include/linux/pci-epc.h
 create mode 100644 include/linux/pci-epf.h

diff --git a/drivers/Makefile b/drivers/Makefile
index 2eced9a..a5f8e43 100644
--- a/drivers/Makefile
+++ b/drivers/Makefile
@@ -14,7 +14,9 @@ obj-$(CONFIG_GENERIC_PHY) += phy/
 obj-$(CONFIG_PINCTRL)  += pinctrl/
 obj-$(CONFIG_GPIOLIB)  += gpio/
 obj-y  += pwm/
+
 obj-$(CONFIG_PCI)  += pci/
+obj-$(CONFIG_PCI_ENDPOINT) += pci/endpoint/
 # PCI dwc controller drivers
 obj-y  += pci/dwc/
 
diff --git a/drivers/pci/Kconfig b/drivers/pci/Kconfig
index df14142..9747c1e 100644
--- a/drivers/pci/Kconfig
+++ b/drivers/pci/Kconfig
@@ -134,3 +134,4 @@ config PCI_HYPERV
 source "drivers/pci/hotplug/Kconfig"
 source "drivers/pci/dwc/Kconfig"
 source "drivers/pci/host/Kconfig"
+source "drivers/pci/endpoint/Kconfig"
diff --git a/drivers/pci/endpoint/Kconfig b/drivers/pci/endpoint/Kconfig
new file mode 100644
index 000..a5442ac
--- /dev/null
+++ b/drivers/pci/endpoint/Kconfig
@@ -0,0 +1,20 @@
+#
+# PCI Endpoint Support
+#
+
+menu "PCI Endpoint"
+
+config PCI_ENDPOINT
+   bool "PCI Endpoint Support"
+   help
+  Enable this configuration option to support configurable PCI
+  endpoint. This should be enabled if the platform has a PCI
+  controller that can operate in endpoint mode.
+
+  Enabling this option will build the endpoint library, which
+  includes endpoint controller library and endpoint function
+  library.
+
+  If in doubt, say "N" to disable Endpoint support.
+
+endmenu
diff --git a/drivers/pci/endpoint/Makefile b/drivers/pci/endpoint/Makefile
new file mode 100644
index 000..dc1bc16
--- /dev/null
+++ b/drivers/pci/endpoint/Makefile
@@ -0,0 +1,6 @@
+#
+# Makefile for PCI Endpoint Support
+#
+
+obj-$(CONFIG_PCI_ENDPOINT) += pci-epc-core.o pci-epf-core.o\
+  pci-epc-mem.o
diff --git a/drivers/pci/endpoint/pci-epc-core.c 
b/drivers/pci/endpoint/pci-epc-core.c
new file mode 100644
index 000..06808ed
--- /dev/null
+++ b/drivers/pci/endpoint/pci-epc-core.c
@@ -0,0 +1,575 @@
+/**
+ * PCI Endpoint *Controller* (EPC) library
+ *
+ * Copyright (C) 2017 Texas Instruments
+ * Author: Kishon Vijay Abraham I 
+ *
+ * This program is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 of
+ * the License as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see .
+ */
+
+#include 
+#include 
+#include 
+#include 
+
+#include 
+#include 
+
+static struct class *pci_epc_class;
+
+static void devm_pci_epc_release(struct device *dev, void *res)
+{
+   struct pci_epc *epc = *(struct pci_epc **)res;
+
+   pci_epc_destroy(epc);
+}
+
+static int devm_pci_epc_match(struct device *dev, void *res, void *match_data)
+{
+   struct pci_epc **epc = res;
+
+   return *epc == match_data;
+}
+
+/**
+ * pci_epc_put() - release the pci endpoint controller
+ * @epc: epc returned by pci_epc_get()
+ *
+ * release the refcount the caller obtained by invoking pci_epc_get()
+ */
+void pci_epc_put(struct pci_epc *epc)
+{
+   if (!epc || IS_ERR(epc))
+   return;
+
+   module_put(epc->ops->owner);
+   put_device(&epc->dev);
+}
+EXPORT_SYMBOL_GPL(pci_epc_put);
+
+/**

Re: [PATCH v5 2/5] powerpc: kretprobes: override default function entry offset

[Naveen N. Rao]

On 2017/03/09 05:37PM, Michael Ellerman wrote:
> "Naveen N. Rao"  writes:
> > On 2017/03/08 11:29AM, Arnaldo Carvalho de Melo wrote:
> >> > I wasn't sure if you were planning on picking up KPROBES_ON_FTRACE for 
> >> > v4.11. If so, it would be good to take this patch through the powerpc 
> >> > tree. Otherwise, this can go via Ingo's tree.
> >> 
> >> If you guys convince Ingo that this should go _now_, then just cherry
> >> pick what was merged into tip/perf/core that is needed for the arch
> >> specific stuff and go from there.
> >
> > Ok, in hindsight, I think Michael's concern was actually for v4.12 
> 
> Yes I was talking about 4.12, sorry I thought that was implied :)

I suppose it was evident for everyone except the overzealous me :D
Sorry for all the confusion.

> 
> > itself, in which case this particular patch can go via powerpc tree, 
> > while the rest of the patches in this series can go via your tree.
> >
> > Michael?
> 
> Yeah I think that's the easiest option. The function will be temporarily
> unused until the two trees are merged, but I think that's fine.

Sure, thanks!

- Naveen

[PATCH v3 18/23] Documentation: misc-devices: Add Documentation for pci-endpoint-test driver

[Kishon Vijay Abraham I]

Add Documentation for pci-endpoint-test driver.

Signed-off-by: Kishon Vijay Abraham I 
---
 Documentation/misc-devices/pci-endpoint-test.txt |   35 ++
 1 file changed, 35 insertions(+)
 create mode 100644 Documentation/misc-devices/pci-endpoint-test.txt

diff --git a/Documentation/misc-devices/pci-endpoint-test.txt 
b/Documentation/misc-devices/pci-endpoint-test.txt
new file mode 100644
index 000..4385718
--- /dev/null
+++ b/Documentation/misc-devices/pci-endpoint-test.txt
@@ -0,0 +1,35 @@
+Driver for PCI Endpoint Test Function
+
+This driver should be used as a host side driver if the root complex is
+connected to a configurable pci endpoint running *pci_epf_test* function
+driver configured according to [1].
+
+The "pci_endpoint_test" driver can be used to perform the following tests.
+
+The PCI driver for the test device performs the following tests
+   *) verifying addresses programmed in BAR
+   *) raise legacy IRQ
+   *) raise MSI IRQ
+   *) read data
+   *) write data
+   *) copy data
+
+This misc driver creates /dev/pci-endpoint-test. for every
+*pci_epf_test* function connected to the root complex and "ioctls"
+should be used to perform the above tests.
+
+ioctl
+-
+ PCITEST_BAR: Tests the BAR. The number of the BAR that has to be tested
+ should be passed as argument.
+ PCITEST_LEGACY_IRQ: Tests legacy IRQ
+ PCITEST_MSI: Tests message signalled interrupts. The MSI number that has
+ to be tested should be passed as argument.
+ PCITEST_WRITE: Perform write tests. The size of the buffer should be passed
+   as argument.
+ PCITEST_READ: Perform read tests. The size of the buffer should be passed
+  as argument.
+ PCITEST_COPY: Perform read tests. The size of the buffer should be passed
+  as argument.
+
+[1] -> Documentation/PCI/endpoint/function/binding/pci-test.txt
-- 
1.7.9.5

[PATCH v3 04/23] Documentation: PCI: Guide to use pci endpoint configfs

[Kishon Vijay Abraham I]

Add Documentation to help users use pci endpoint to configure
pci endpoint function and to bind the endpoint function
with endpoint controller.

Signed-off-by: Kishon Vijay Abraham I 
---
 Documentation/PCI/00-INDEX  |2 +
 Documentation/PCI/endpoint/pci-endpoint-cfs.txt |  105 +++
 2 files changed, 107 insertions(+)
 create mode 100644 Documentation/PCI/endpoint/pci-endpoint-cfs.txt

diff --git a/Documentation/PCI/00-INDEX b/Documentation/PCI/00-INDEX
index ba950b2..f84a23c 100644
--- a/Documentation/PCI/00-INDEX
+++ b/Documentation/PCI/00-INDEX
@@ -14,3 +14,5 @@ pcieaer-howto.txt
- the PCI Express Advanced Error Reporting Driver Guide HOWTO
 endpoint/pci-endpoint.txt
- guide to add endpoint controller driver and endpoint function driver.
+endpoint/pci-endpoint-cfs.txt
+   - guide to use configfs to configure the pci endpoint function.
diff --git a/Documentation/PCI/endpoint/pci-endpoint-cfs.txt 
b/Documentation/PCI/endpoint/pci-endpoint-cfs.txt
new file mode 100644
index 000..8b2a828
--- /dev/null
+++ b/Documentation/PCI/endpoint/pci-endpoint-cfs.txt
@@ -0,0 +1,105 @@
+   CONFIGURING PCI ENDPOINT USING CONFIGFS
+Kishon Vijay Abraham I 
+
+The PCI Endpoint Core exposes configfs entry (pci_ep) in order to configure the
+PCI endpoint function and in order to bind the endpoint function
+with the endpoint controller. (For introducing other mechanisms to
+configure the PCI Endpoint Function refer [1]).
+
+*) Mounting configfs
+
+The PCI Endpoint Core layer creates pci_ep directory in the mounted configfs
+directory. configfs can be mounted using the following command.
+
+   mount -t configfs none /sys/kernel/config
+
+*) Directory Structure
+
+The pci_ep configfs has two directories at its root: controllers and
+functions. Every EPC device present in the system will have an entry in
+the *controllers* directory and and every EPF driver present in the system
+will have an entry in the *functions* directory.
+
+/sys/kernel/config/pci_ep/
+   .. controllers/
+   .. functions/
+
+*) Creating EPF Device
+
+Every registered EPF driver will be listed in controllers directory. The
+entries corresponding to EPF driver will be created by the EPF core.
+
+/sys/kernel/config/pci_ep/functions/
+   .. /
+   ... /
+   ... /
+   .. /
+   ... /
+   ... /
+
+In order to create a  of the type probed by , the
+user has to create a directory inside .
+
+Every  directory consists of the following entries that can be
+used to configure the standard configuration header of the endpoint function.
+(These entries are created by the framework when any new  is
+created)
+
+   .. /
+   ... /
+   ... vendorid
+   ... deviceid
+   ... revid
+   ... progif_code
+   ... subclass_code
+   ... baseclass_code
+   ... cache_line_size
+   ... subsys_vendor_id
+   ... subsys_id
+   ... interrupt_pin
+
+*) EPC Device
+
+Every registered EPC device will be listed in controllers directory. The
+entries corresponding to EPC device will be created by the EPC core.
+
+/sys/kernel/config/pci_ep/controllers/
+   .. /
+   ... /
+   ... /
+   ... start
+   .. /
+   ... /
+   ... /
+   ... start
+
+The  directory will have a list of symbolic links to
+. These symbolic links should be created by the user to
+represent the functions present in the endpoint device.
+
+The  directory will also have a *start* field. Once
+"1" is written to this field, the endpoint device will be ready to
+establish the link with the host. This is usually done after
+all the EPF devices are created and linked with the EPC device.
+
+
+| controllers/
+   | /
+   | 
+   | start
+| functions/
+   | /
+   | /
+   | vendorid
+   | deviceid
+   | revid
+   | progif_code
+   | subclass_code
+   | baseclass_code
+   | cache_line_size
+   | subsys_vendor_id
+   | subsys_id
+   | interrupt_pin
+   | function
+
+[1] -> Documentation/PCI/endpoint/pci-en

[PATCH v3 21/23] Documentation: PCI: Add userguide for PCI endpoint test function

[Kishon Vijay Abraham I]

Add documentation to help users use pci-epf-test function driver
and pci_endpoint_test host driver for testing PCI.

Signed-off-by: Kishon Vijay Abraham I 
---
 Documentation/PCI/00-INDEX|2 +
 Documentation/PCI/endpoint/pci-test-howto.txt |  179 +
 2 files changed, 181 insertions(+)
 create mode 100644 Documentation/PCI/endpoint/pci-test-howto.txt

diff --git a/Documentation/PCI/00-INDEX b/Documentation/PCI/00-INDEX
index 53717b7..fd533c7 100644
--- a/Documentation/PCI/00-INDEX
+++ b/Documentation/PCI/00-INDEX
@@ -18,5 +18,7 @@ endpoint/pci-endpoint-cfs.txt
- guide to use configfs to configure the pci endpoint function.
 endpoint/pci-test-function.txt
- specification of *pci test* function device.
+endpoint/pci-test-howto.txt
+   - userguide for PCI endpoint test function.
 endpoint/function/binding/
- binding documentation for pci endpoint function
diff --git a/Documentation/PCI/endpoint/pci-test-howto.txt 
b/Documentation/PCI/endpoint/pci-test-howto.txt
new file mode 100644
index 000..730b70c
--- /dev/null
+++ b/Documentation/PCI/endpoint/pci-test-howto.txt
@@ -0,0 +1,179 @@
+   PCI TEST USERGUIDE
+   Kishon Vijay Abraham I 
+
+This document is a guide to help users use pci-epf-test function driver
+and pci_endpoint_test host driver for testing PCI. The list of steps to
+be followed in the host side and EP side is given below.
+
+1. Endpoint Device
+
+1.1 Endpoint Controller Devices
+
+To find the list of endpoint controller devices in the system:
+
+   # ls /sys/class/pci_epc/
+ 5100.pcie_ep
+
+If PCI_ENDPOINT_CONFIGFS is enabled
+   # ls /sys/kernel/config/pci_ep/controllers
+ 5100.pcie_ep
+
+1.2 Endpoint Function Drivers
+
+To find the list of endpoint function drivers in the system:
+
+   # ls /sys/bus/pci-epf/drivers
+ pci_epf_test
+
+If PCI_ENDPOINT_CONFIGFS is enabled
+   # ls /sys/kernel/config/pci_ep/functions
+ pci_epf_test
+
+1.3 Creating pci-epf-test Device
+
+PCI endpoint function device can be created using the configfs. To create
+pci-epf-test device, the following commands can be used
+
+   # mount -t configfs none /sys/kernel/config
+   # cd /sys/kernel/config/pci_ep/
+   # mkdir functions/pci_epf_test/func1
+
+The "mkdir func1" above creates the pci-epf-test function device that will
+be probed by pci_epf_test driver.
+
+The PCI endpoint framework populates the directory with the following
+configurable fields.
+
+   # ls functions/pci_epf_test/func1
+ baseclass_codeinterrupt_pin   revid   subsys_vendor_id
+ cache_line_size   msi_interrupts  subclass_code   vendorid
+ deviceid  progif_code subsys_id
+
+The pci endpoint function driver populates these entries with default values
+when the device is bound to the driver. The pci-epf-test driver populates
+vendorid with 0x and interrupt_pin with 0x0001
+
+   # cat functions/pci_epf_test/func1/vendorid
+ 0x
+   # cat functions/pci_epf_test/func1/interrupt_pin
+ 0x0001
+
+1.4 Configuring pci-epf-test Device
+
+The user can configure the pci-epf-test device using configfs entry. In order
+to change the vendorid and the number of MSI interrupts used by the function
+device, the following commands can be used.
+
+   # echo 0x104c > functions/pci_epf_test/func1/vendorid
+   # echo 0xb500 > functions/pci_epf_test/func1/deviceid
+   # echo 16 > functions/pci_epf_test/func1/msi_interrupts
+
+1.5 Binding pci-epf-test Device to EP Controller
+
+In order for the endpoint function device to be useful, it has to be bound to
+a PCI endpoint controller driver. Use the configfs to bind the function
+device to one of the controller driver present in the system.
+
+   # ln -s functions/pci_epf_test/func1 controllers/5100.pcie_ep/
+
+Once the above step is completed, the PCI endpoint is ready to establish a link
+with the host.
+
+1.6 Start the Link
+
+In order for the endpoint device to establish a link with the host, the _start_
+field should be populated with '1'.
+
+   # echo 1 > controllers/5100.pcie_ep/start
+
+2. RootComplex Device
+
+2.1 lspci Output
+
+Note that the devices listed here correspond to the value populated in 1.4 
above
+
+   00:00.0 PCI bridge: Texas Instruments Device  (rev 01)
+   01:00.0 Unassigned class [ff00]: Texas Instruments Device b500
+
+2.2 Using Endpoint Test function Device
+
+pcitest.sh added in tools/pci/ can be used to run all the default PCI endpoint
+tests. Before pcitest.sh can be used pcitest.c should be compiled using the
+following commands.
+
+   cd 
+   make headers_install ARCH=arm
+   arm-linux-gnueabihf-gcc -Iusr/include tools/pci/pcitest.c -o pcitest
+   cp pcitest  /usr/sbin/
+   cp tools/pci/pcitest.sh 
+
+2.2.1 pcitest.sh Output
+   # ./pcitest.sh
+   BAR tests

[PATCH v3 17/23] misc: Add host side pci driver for pci test function device

[Kishon Vijay Abraham I]

Add PCI endpoint test driver that can verify base address
register, legacy interrupt/MSI interrupt and read/write/copy
buffers between host and device. The corresponding pci-epf-test
function driver should be used on the EP side.

Signed-off-by: Kishon Vijay Abraham I 
---
 drivers/misc/Kconfig |7 +
 drivers/misc/Makefile|1 +
 drivers/misc/pci_endpoint_test.c |  534 ++
 include/uapi/linux/Kbuild|1 +
 include/uapi/linux/pcitest.h |   19 ++
 5 files changed, 562 insertions(+)
 create mode 100644 drivers/misc/pci_endpoint_test.c
 create mode 100644 include/uapi/linux/pcitest.h

diff --git a/drivers/misc/Kconfig b/drivers/misc/Kconfig
index c290990..15ac29d 100644
--- a/drivers/misc/Kconfig
+++ b/drivers/misc/Kconfig
@@ -771,6 +771,13 @@ config PANEL_BOOT_MESSAGE
 
 endif # PANEL
 
+config PCI_ENDPOINT_TEST
+   depends on PCI || COMPILE_TEST
+   tristate "PCI Endpoint Test driver"
+   ---help---
+   Enable this configuration option to enable the host side test driver
+   for PCI Endpoint.
+
 source "drivers/misc/c2port/Kconfig"
 source "drivers/misc/eeprom/Kconfig"
 source "drivers/misc/cb710/Kconfig"
diff --git a/drivers/misc/Makefile b/drivers/misc/Makefile
index 7a3ea89..6e139cd 100644
--- a/drivers/misc/Makefile
+++ b/drivers/misc/Makefile
@@ -54,6 +54,7 @@ obj-$(CONFIG_ECHO)+= echo/
 obj-$(CONFIG_VEXPRESS_SYSCFG)  += vexpress-syscfg.o
 obj-$(CONFIG_CXL_BASE) += cxl/
 obj-$(CONFIG_PANEL) += panel.o
+obj-$(CONFIG_PCI_ENDPOINT_TEST)+= pci_endpoint_test.o
 
 lkdtm-$(CONFIG_LKDTM)  += lkdtm_core.o
 lkdtm-$(CONFIG_LKDTM)  += lkdtm_bugs.o
diff --git a/drivers/misc/pci_endpoint_test.c b/drivers/misc/pci_endpoint_test.c
new file mode 100644
index 000..5f4f8f8
--- /dev/null
+++ b/drivers/misc/pci_endpoint_test.c
@@ -0,0 +1,534 @@
+/**
+ * Host side test driver to test endpoint functionality
+ *
+ * Copyright (C) 2017 Texas Instruments
+ * Author: Kishon Vijay Abraham I 
+ *
+ * This program is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 of
+ * the License as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see .
+ */
+
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+#include 
+
+#include 
+
+#define DRV_MODULE_NAME"pci-endpoint-test"
+
+#define PCI_ENDPOINT_TEST_MAGIC0x0
+
+#define PCI_ENDPOINT_TEST_COMMAND  0x4
+#define COMMAND_RAISE_LEGACY_IRQ   BIT(0)
+#define COMMAND_RAISE_MSI_IRQ  BIT(1)
+#define MSI_NUMBER_SHIFT   2
+/* 6 bits for MSI number */
+#define COMMAND_READBIT(8)
+#define COMMAND_WRITE   BIT(9)
+#define COMMAND_COPYBIT(10)
+
+#define PCI_ENDPOINT_TEST_STATUS   0x8
+#define STATUS_READ_SUCCESS BIT(0)
+#define STATUS_READ_FAILBIT(1)
+#define STATUS_WRITE_SUCCESSBIT(2)
+#define STATUS_WRITE_FAIL   BIT(3)
+#define STATUS_COPY_SUCCESS BIT(4)
+#define STATUS_COPY_FAILBIT(5)
+#define STATUS_IRQ_RAISED   BIT(6)
+#define STATUS_SRC_ADDR_INVALID BIT(7)
+#define STATUS_DST_ADDR_INVALID BIT(8)
+
+#define PCI_ENDPOINT_TEST_LOWER_SRC_ADDR   0xc
+#define PCI_ENDPOINT_TEST_UPPER_SRC_ADDR   0x10
+
+#define PCI_ENDPOINT_TEST_LOWER_DST_ADDR   0x14
+#define PCI_ENDPOINT_TEST_UPPER_DST_ADDR   0x18
+
+#define PCI_ENDPOINT_TEST_SIZE 0x1c
+#define PCI_ENDPOINT_TEST_CHECKSUM 0x20
+
+static DEFINE_IDA(pci_endpoint_test_ida);
+
+#define to_endpoint_test(priv) container_of((priv), struct pci_endpoint_test, \
+   miscdev)
+enum pci_barno {
+   BAR_0,
+   BAR_1,
+   BAR_2,
+   BAR_3,
+   BAR_4,
+   BAR_5,
+};
+
+struct pci_endpoint_test {
+   struct pci_dev  *pdev;
+   void __iomem*base;
+   void __iomem*bar[6];
+   struct completion irq_raised;
+   int last_irq;
+   /* mutex to protect the ioctls */
+   struct mutexmutex;
+   struct miscdevice miscdev;
+};
+
+static int bar_size[] = { 4, 512, 1024, 16384, 131072, 1048576 };
+
+static inline u32 pci_endpoint_test_readl(struct pci_endpoint_test *test,
+ u32 offset)
+{
+   return readl(test->base + offset);
+}
+
+static inline void pci_endp

[PATCH v3 06/23] Documentation: PCI: Add specification for the *pci test* function device

[Kishon Vijay Abraham I]

Add specification for the *pci test* virtual function device. The endpoint
function driver and the host pci driver should be created based on this
specification.

Signed-off-by: Kishon Vijay Abraham I 
---
 Documentation/PCI/00-INDEX   |2 +
 Documentation/PCI/endpoint/pci-test-function.txt |   66 ++
 2 files changed, 68 insertions(+)
 create mode 100644 Documentation/PCI/endpoint/pci-test-function.txt

diff --git a/Documentation/PCI/00-INDEX b/Documentation/PCI/00-INDEX
index f84a23c..4e5a283 100644
--- a/Documentation/PCI/00-INDEX
+++ b/Documentation/PCI/00-INDEX
@@ -16,3 +16,5 @@ endpoint/pci-endpoint.txt
- guide to add endpoint controller driver and endpoint function driver.
 endpoint/pci-endpoint-cfs.txt
- guide to use configfs to configure the pci endpoint function.
+endpoint/pci-test-function.txt
+   - specification of *pci test* function device.
diff --git a/Documentation/PCI/endpoint/pci-test-function.txt 
b/Documentation/PCI/endpoint/pci-test-function.txt
new file mode 100644
index 000..1324376
--- /dev/null
+++ b/Documentation/PCI/endpoint/pci-test-function.txt
@@ -0,0 +1,66 @@
+   PCI TEST
+   Kishon Vijay Abraham I 
+
+Traditionally PCI RC has always been validated by using standard
+PCI cards like ethernet PCI cards or USB PCI cards or SATA PCI cards.
+However with the addition of EP-core in linux kernel, it is possible
+to configure a PCI controller that can operate in EP mode to work as
+a test device.
+
+The PCI endpoint test device is a virtual device (defined in software)
+used to test the endpoint functionality and serve as a sample driver
+for other PCI endpoint devices (to use the EP framework).
+
+The PCI endpoint test device has the following registers:
+
+   1) PCI_ENDPOINT_TEST_MAGIC
+   2) PCI_ENDPOINT_TEST_COMMAND
+   3) PCI_ENDPOINT_TEST_STATUS
+   4) PCI_ENDPOINT_TEST_SRC_ADDR
+   5) PCI_ENDPOINT_TEST_DST_ADDR
+   6) PCI_ENDPOINT_TEST_SIZE
+   7) PCI_ENDPOINT_TEST_CHECKSUM
+
+*) PCI_ENDPOINT_TEST_MAGIC
+
+This register will be used to test BAR0. A known pattern will be written
+and read back from MAGIC register to verify BAR0.
+
+*) PCI_ENDPOINT_TEST_COMMAND:
+
+This register will be used by the host driver to indicate the function
+that the endpoint device must perform.
+
+Bitfield Description:
+  Bit 0: raise legacy irq
+  Bit 1: raise MSI irq
+  Bit 2 - 7: MSI interrupt number
+  Bit 8: read command (read data from RC buffer)
+  Bit 9: write command (write data to RC buffer)
+  Bit 10   : copy command (copy data from one RC buffer to another
+ RC buffer)
+
+*) PCI_ENDPOINT_TEST_STATUS
+
+This register reflects the status of the PCI endpoint device.
+
+Bitfield Description:
+  Bit 0: read success
+  Bit 1: read fail
+  Bit 2: write success
+  Bit 3: write fail
+  Bit 4: copy success
+  Bit 5: copy fail
+  Bit 6: irq raised
+  Bit 7: source address is invalid
+  Bit 8: destination address is invalid
+
+*) PCI_ENDPOINT_TEST_SRC_ADDR
+
+This register contains the source address (RC buffer address) for the
+COPY/READ command.
+
+*) PCI_ENDPOINT_TEST_DST_ADDR
+
+This register contains the destination address (RC buffer address) for
+the COPY/WRITE command.
-- 
1.7.9.5

Re: + compaction-add-def_blk_aops-migrate-function-for-memory-compaction.patch added to -mm tree

[Vlastimil Babka]

On 03/09/2017 12:55 AM, a...@linux-foundation.org wrote:
> 
> The patch titled
>  Subject: compaction: add def_blk_aops migrate function for memory 
> compaction
> has been added to the -mm tree.  Its filename is
>  compaction-add-def_blk_aops-migrate-function-for-memory-compaction.patch
> 
> This patch should soon appear at
> 
> http://ozlabs.org/~akpm/mmots/broken-out/compaction-add-def_blk_aops-migrate-function-for-memory-compaction.patch
> and later at
> 
> http://ozlabs.org/~akpm/mmotm/broken-out/compaction-add-def_blk_aops-migrate-function-for-memory-compaction.patch
> 
> Before you just go and hit "reply", please:
>a) Consider who else should be cc'ed
>b) Prefer to cc a suitable mailing list as well
>c) Ideally: find the original patch on the mailing list and do a
>   reply-to-all to that, adding suitable additional cc's
> 
> *** Remember to use Documentation/SubmitChecklist when testing your code ***
> 
> The -mm tree is included into linux-next and is updated
> there every 3-4 working days
> 
> --
> From: zhouxianrong 
> Subject: compaction: add def_blk_aops migrate function for memory compaction

That's not really a mm/compaction patch, but a block layer/migration patch. I
don't know internals of those so well, so I added some CC's.

> The reason for doing this is based on two factors.
> 
> 1. larg file read/write operations with order 0 can fragmentize
>memory rapidly.
> 
> 2. when a special filesystem does not supply migratepage callback,
>kernel would fallback to default function fallback_migrate_page.
>but fallback_migrate_page could not migrate diry page nicely;
>specially kcompactd with MIGRATE_SYNC_LIGHT could not migrate
>diry pages due to this until clear_page_dirty_for_io in some
>procedure. i think it is not suitable here in this scenario.
>for dirty pages we should migrate it rather than skip or writeout
>it in kcomapctd with MIGRATE_SYNC_LIGHT. i think this problem is
>for all filesystem without migratepage not only for block device fs.
> 
> So for compaction under large file writing supply migratepage for
> def_blk_aops.

Is this really safe to do? buffer_migrate_page() has some assumptions listed in
its comment (and maybe more that are not listed). Do we know it's safe to use it
for all def_blk_aops users?

> Link: 
> http://lkml.kernel.org/r/1488937915-78955-1-git-send-email-zhouxianr...@huawei.com
> Signed-off-by: zhouxianrong 
> Cc: Kirill A. Shutemov 
> Cc: Johannes Weiner 
> Cc: Minchan Kim 
> Cc: Mel Gorman 
> Cc: Vlastimil Babka 
> Cc: Al Viro 
> Cc: 
> Cc: 
> Cc: 
> Cc: 
> Cc: 
> Cc: 
> Signed-off-by: Andrew Morton 
> ---
> 
>  fs/block_dev.c |3 +++
>  1 file changed, 3 insertions(+)
> 
> diff -puN 
> fs/block_dev.c~compaction-add-def_blk_aops-migrate-function-for-memory-compaction
>  fs/block_dev.c
> --- 
> a/fs/block_dev.c~compaction-add-def_blk_aops-migrate-function-for-memory-compaction
> +++ a/fs/block_dev.c
> @@ -2064,6 +2064,9 @@ static const struct address_space_operat
>   .releasepage= blkdev_releasepage,
>   .direct_IO  = blkdev_direct_IO,
>   .is_dirty_writeback = buffer_check_dirty_writeback,
> +#ifdef CONFIG_MIGRATION
> + .migratepage = buffer_migrate_page,
> +#endif
>  };
>  
>  #define  BLKDEV_FALLOC_FL_SUPPORTED  
> \
> _
> 
> Patches currently in -mm which might be from zhouxianr...@huawei.com are
> 
> compaction-add-def_blk_aops-migrate-function-for-memory-compaction.patch
> 

Re: [TRIVIAL PATCH 1/2] doc: trace/kprobes: add information about NOKPROBE_SYMBOL

[Masami Hiramatsu]

On Wed,  8 Mar 2017 22:34:14 +0530
"Naveen N. Rao"  wrote:

> Update kprobe tracer documentation to also mention that
> NOKPROBE_SYMBOL() and nokprobe_inline add symbols to the kprobes
> blacklist.

Thanks for update!

Acked-by: Masami Hiramatsu 

> 
> Signed-off-by: Naveen N. Rao 
> ---
>  Documentation/trace/kprobetrace.txt | 5 +++--
>  1 file changed, 3 insertions(+), 2 deletions(-)
> 
> diff --git a/Documentation/trace/kprobetrace.txt 
> b/Documentation/trace/kprobetrace.txt
> index 41ef9d8efe95..5ea85059db3b 100644
> --- a/Documentation/trace/kprobetrace.txt
> +++ b/Documentation/trace/kprobetrace.txt
> @@ -8,8 +8,9 @@ Overview
>  
>  These events are similar to tracepoint based events. Instead of Tracepoint,
>  this is based on kprobes (kprobe and kretprobe). So it can probe wherever
> -kprobes can probe (this means, all functions body except for __kprobes
> -functions). Unlike the Tracepoint based event, this can be added and removed
> +kprobes can probe (this means, all functions except those with
> +__kprobes/nokprobe_inline annotation and those marked NOKPROBE_SYMBOL).
> +Unlike the Tracepoint based event, this can be added and removed
>  dynamically, on the fly.
>  
>  To enable this feature, build your kernel with CONFIG_KPROBE_EVENTS=y.
> -- 
> 2.11.1
> 


-- 
Masami Hiramatsu 

[PATCH v5] blkcg: allocate struct blkcg_gq outside request queue spinlock

[Tahsin Erdogan]

blkg_conf_prep() currently calls blkg_lookup_create() while holding
request queue spinlock. This means allocating memory for struct
blkcg_gq has to be made non-blocking. This causes occasional -ENOMEM
failures in call paths like below:

  pcpu_alloc+0x68f/0x710
  __alloc_percpu_gfp+0xd/0x10
  __percpu_counter_init+0x55/0xc0
  cfq_pd_alloc+0x3b2/0x4e0
  blkg_alloc+0x187/0x230
  blkg_create+0x489/0x670
  blkg_lookup_create+0x9a/0x230
  blkg_conf_prep+0x1fb/0x240
  __cfqg_set_weight_device.isra.105+0x5c/0x180
  cfq_set_weight_on_dfl+0x69/0xc0
  cgroup_file_write+0x39/0x1c0
  kernfs_fop_write+0x13f/0x1d0
  __vfs_write+0x23/0x120
  vfs_write+0xc2/0x1f0
  SyS_write+0x44/0xb0
  entry_SYSCALL_64_fastpath+0x18/0xad

In the code path above, percpu allocator cannot call vmalloc() due to
queue spinlock.

A failure in this call path gives grief to tools which are trying to
configure io weights. We see occasional failures happen shortly after
reboots even when system is not under any memory pressure. Machines
with a lot of cpus are more vulnerable to this condition.

Update blkg_create() function to temporarily drop the rcu and queue
locks when it is allowed by gfp mask.

Suggested-by: Tejun Heo 
Signed-off-by: Tahsin Erdogan 
---
v5:
  Removed stale blkg_alloc() in blkcg_init_queue()

  Pushed down radix_tree_preload() into blkg_create() because it
  disables preemption on return and makes it unsafe to call blocking
  memory allocations.

v4:
  Simplified error checking in blkg_create()
  Factored out __blkg_lookup_create()

v3:
  Pushed down all blkg allocations into blkg_create()

v2:
  Moved blkg creation into blkg_lookup_create() to avoid duplicating
  blkg_lookup_create() logic.

 block/blk-cgroup.c | 138 -
 include/linux/blk-cgroup.h |   6 +-
 2 files changed, 91 insertions(+), 53 deletions(-)

diff --git a/block/blk-cgroup.c b/block/blk-cgroup.c
index bbe7ee00bd3d..bdf87f0c1b1b 100644
--- a/block/blk-cgroup.c
+++ b/block/blk-cgroup.c
@@ -165,16 +165,18 @@ struct blkcg_gq *blkg_lookup_slowpath(struct blkcg *blkcg,
 EXPORT_SYMBOL_GPL(blkg_lookup_slowpath);
 
 /*
- * If @new_blkg is %NULL, this function tries to allocate a new one as
- * necessary using %GFP_NOWAIT.  @new_blkg is always consumed on return.
+ * If gfp mask allows blocking, this function temporarily drops rcu and queue
+ * locks to allocate memory.
  */
 static struct blkcg_gq *blkg_create(struct blkcg *blkcg,
-   struct request_queue *q,
-   struct blkcg_gq *new_blkg)
+   struct request_queue *q, gfp_t gfp,
+   const struct blkcg_policy *pol)
 {
-   struct blkcg_gq *blkg;
+   struct blkcg_gq *blkg = NULL;
struct bdi_writeback_congested *wb_congested;
int i, ret;
+   const bool drop_locks = gfpflags_allow_blocking(gfp);
+   bool preloaded = false;
 
WARN_ON_ONCE(!rcu_read_lock_held());
lockdep_assert_held(q->queue_lock);
@@ -185,31 +187,53 @@ static struct blkcg_gq *blkg_create(struct blkcg *blkcg,
goto err_free_blkg;
}
 
+   if (drop_locks) {
+   spin_unlock_irq(q->queue_lock);
+   rcu_read_unlock();
+   }
+
wb_congested = wb_congested_get_create(q->backing_dev_info,
-  blkcg->css.id,
-  GFP_NOWAIT | __GFP_NOWARN);
-   if (!wb_congested) {
+  blkcg->css.id, gfp);
+   blkg = blkg_alloc(blkcg, q, gfp);
+
+   if (drop_locks) {
+   preloaded = !radix_tree_preload(gfp);
+   rcu_read_lock();
+   spin_lock_irq(q->queue_lock);
+   }
+
+   if (unlikely(!wb_congested || !blkg)) {
ret = -ENOMEM;
-   goto err_put_css;
+   goto err_put;
}
 
-   /* allocate */
-   if (!new_blkg) {
-   new_blkg = blkg_alloc(blkcg, q, GFP_NOWAIT | __GFP_NOWARN);
-   if (unlikely(!new_blkg)) {
-   ret = -ENOMEM;
-   goto err_put_congested;
+   blkg->wb_congested = wb_congested;
+
+   if (pol) {
+   WARN_ON(!drop_locks);
+
+   if (!blkcg_policy_enabled(q, pol)) {
+   ret = -EOPNOTSUPP;
+   goto err_put;
+   }
+
+   /*
+* This could be the first entry point of blkcg implementation
+* and we shouldn't allow anything to go through for a bypassing
+* queue.
+*/
+   if (unlikely(blk_queue_bypass(q))) {
+   ret = blk_queue_dying(q) ? -ENODEV : -EBUSY;
+   goto err_put;
}
}
-   blkg = new_blkg;
-   blkg->wb_congested = wb_congested;
 
/* link parent */
  

[PATCH v3 08/23] Documentation: PCI: Add binding documentation for pci-test endpoint function

[Kishon Vijay Abraham I]

Add binding documentation for pci-test endpoint function that helps in
adding and configuring pci-test endpoint function.

Signed-off-by: Kishon Vijay Abraham I 
---
 Documentation/PCI/00-INDEX |2 ++
 .../PCI/endpoint/function/binding/pci-test.txt |   17 +
 2 files changed, 19 insertions(+)
 create mode 100644 Documentation/PCI/endpoint/function/binding/pci-test.txt

diff --git a/Documentation/PCI/00-INDEX b/Documentation/PCI/00-INDEX
index 4e5a283..53717b7 100644
--- a/Documentation/PCI/00-INDEX
+++ b/Documentation/PCI/00-INDEX
@@ -18,3 +18,5 @@ endpoint/pci-endpoint-cfs.txt
- guide to use configfs to configure the pci endpoint function.
 endpoint/pci-test-function.txt
- specification of *pci test* function device.
+endpoint/function/binding/
+   - binding documentation for pci endpoint function
diff --git a/Documentation/PCI/endpoint/function/binding/pci-test.txt 
b/Documentation/PCI/endpoint/function/binding/pci-test.txt
new file mode 100644
index 000..02a6c94
--- /dev/null
+++ b/Documentation/PCI/endpoint/function/binding/pci-test.txt
@@ -0,0 +1,17 @@
+PCI TEST ENDPOINT FUNCTION
+
+name: Should be "pci_epf_test" to bind to the pci_epf_test driver.
+
+Configurable Fields:
+vendorid: should be 0x104c
+deviceid: should be 0xb500 for DRA74x and 0xb501 for DRA72x
+revid   : dont't care
+progif_code : don't care
+subclass_code   : don't care
+baseclass_code  : should be 0xff
+cache_line_size : don't care
+subsys_vendor_id : don't care
+subsys_id   : don't care
+interrupt_pin   : Should be 1 - INTA, 2 - INTB, 3 - INTC, 4 -INTD
+msi_interrupts  : Should be 1 to 32 depending on the number of msi interrupts
+  to test
-- 
1.7.9.5

[PATCH v3 07/23] PCI: endpoint: functions: Add an EP function to test PCI

[Kishon Vijay Abraham I]

Adds a new endpoint function driver (to program the virtual
test device) making use of the EP-core library.

Signed-off-by: Kishon Vijay Abraham I 
---
 drivers/pci/endpoint/Kconfig  |2 +
 drivers/pci/endpoint/Makefile |2 +-
 drivers/pci/endpoint/functions/Kconfig|   12 +
 drivers/pci/endpoint/functions/Makefile   |5 +
 drivers/pci/endpoint/functions/pci-epf-test.c |  510 +
 5 files changed, 530 insertions(+), 1 deletion(-)
 create mode 100644 drivers/pci/endpoint/functions/Kconfig
 create mode 100644 drivers/pci/endpoint/functions/Makefile
 create mode 100644 drivers/pci/endpoint/functions/pci-epf-test.c

diff --git a/drivers/pci/endpoint/Kconfig b/drivers/pci/endpoint/Kconfig
index c86bca9..c23f146 100644
--- a/drivers/pci/endpoint/Kconfig
+++ b/drivers/pci/endpoint/Kconfig
@@ -26,4 +26,6 @@ config PCI_ENDPOINT_CONFIGFS
   configure the endpoint function and used to bind the
   function with a endpoint controller.
 
+source "drivers/pci/endpoint/functions/Kconfig"
+
 endmenu
diff --git a/drivers/pci/endpoint/Makefile b/drivers/pci/endpoint/Makefile
index 7219d51..1041f80 100644
--- a/drivers/pci/endpoint/Makefile
+++ b/drivers/pci/endpoint/Makefile
@@ -4,4 +4,4 @@
 
 obj-$(CONFIG_PCI_ENDPOINT_CONFIGFS)+= pci-ep-cfs.o
 obj-$(CONFIG_PCI_ENDPOINT) += pci-epc-core.o pci-epf-core.o\
-  pci-epc-mem.o
+  pci-epc-mem.o functions/
diff --git a/drivers/pci/endpoint/functions/Kconfig 
b/drivers/pci/endpoint/functions/Kconfig
new file mode 100644
index 000..175edad
--- /dev/null
+++ b/drivers/pci/endpoint/functions/Kconfig
@@ -0,0 +1,12 @@
+#
+# PCI Endpoint Functions
+#
+
+config PCI_EPF_TEST
+   tristate "PCI Endpoint Test driver"
+   depends on PCI_ENDPOINT
+   help
+  Enable this configuration option to enable the test driver
+  for PCI Endpoint.
+
+  If in doubt, say "N" to disable Endpoint test driver.
diff --git a/drivers/pci/endpoint/functions/Makefile 
b/drivers/pci/endpoint/functions/Makefile
new file mode 100644
index 000..6d94a48
--- /dev/null
+++ b/drivers/pci/endpoint/functions/Makefile
@@ -0,0 +1,5 @@
+#
+# Makefile for PCI Endpoint Functions
+#
+
+obj-$(CONFIG_PCI_EPF_TEST) += pci-epf-test.o
diff --git a/drivers/pci/endpoint/functions/pci-epf-test.c 
b/drivers/pci/endpoint/functions/pci-epf-test.c
new file mode 100644
index 000..d6a7a12
--- /dev/null
+++ b/drivers/pci/endpoint/functions/pci-epf-test.c
@@ -0,0 +1,510 @@
+/**
+ * Test driver to test endpoint functionality
+ *
+ * Copyright (C) 2017 Texas Instruments
+ * Author: Kishon Vijay Abraham I 
+ *
+ * This program is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 of
+ * the License as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see .
+ */
+
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+#include 
+#include 
+#include 
+
+#define COMMAND_RAISE_LEGACY_IRQ   BIT(0)
+#define COMMAND_RAISE_MSI_IRQ  BIT(1)
+#define MSI_NUMBER_SHIFT   2
+#define MSI_NUMBER_MASK(0x3f << MSI_NUMBER_SHIFT)
+#define COMMAND_READ   BIT(8)
+#define COMMAND_WRITE  BIT(9)
+#define COMMAND_COPY   BIT(10)
+
+#define STATUS_READ_SUCCESSBIT(0)
+#define STATUS_READ_FAIL   BIT(1)
+#define STATUS_WRITE_SUCCESS   BIT(2)
+#define STATUS_WRITE_FAIL  BIT(3)
+#define STATUS_COPY_SUCCESSBIT(4)
+#define STATUS_COPY_FAIL   BIT(5)
+#define STATUS_IRQ_RAISED  BIT(6)
+#define STATUS_SRC_ADDR_INVALIDBIT(7)
+#define STATUS_DST_ADDR_INVALIDBIT(8)
+
+#define TIMER_RESOLUTION   1
+
+static struct workqueue_struct *kpcitest_workqueue;
+
+struct pci_epf_test {
+   void*reg[6];
+   struct pci_epf  *epf;
+   struct delayed_work cmd_handler;
+};
+
+struct pci_epf_test_reg {
+   u32 magic;
+   u32 command;
+   u32 status;
+   u64 src_addr;
+   u64 dst_addr;
+   u32 size;
+   u32 checksum;
+} __packed;
+
+static struct pci_epf_header test_header = {
+   .vendorid   = PCI_ANY_ID,
+   .deviceid   = PCI_ANY_ID,
+   .baseclass_code = PCI_CLASS_OTHERS,
+   .interrupt_pin  = PCI_INTERRUPT_INTA,
+};
+
+static int bar_size[] = { 512, 102

Re: [PATCH v2] irq: generic-chip: provide irq_free_generic_chip()

[Marc Zyngier]

On Wed, Mar 08 2017 at  5:04:05 pm GMT, Bartosz Golaszewski 
 wrote:
> Some users of irq_alloc_generic_chip() are modules which can be
> removed (e.g. gpio-ml-ioh) but have no means of freeing the allocated
> generic chip. Provide a function for that.
>
> Signed-off-by: Bartosz Golaszewski 

Acked-by: Marc Zyngier 

M.
-- 
Jazz is not dead, it just smell funny.

[PATCH v3 10/23] dt-bindings: PCI: Add dt bindings for pci designware EP mode

[Kishon Vijay Abraham I]

Add device tree binding documentation for pci designware EP mode.

Acked-by: Rob Herring 
Signed-off-by: Kishon Vijay Abraham I 
---
 .../devicetree/bindings/pci/designware-pcie.txt|   26 ++--
 1 file changed, 18 insertions(+), 8 deletions(-)

diff --git a/Documentation/devicetree/bindings/pci/designware-pcie.txt 
b/Documentation/devicetree/bindings/pci/designware-pcie.txt
index 1392c70..b2480dd 100644
--- a/Documentation/devicetree/bindings/pci/designware-pcie.txt
+++ b/Documentation/devicetree/bindings/pci/designware-pcie.txt
@@ -6,30 +6,40 @@ Required properties:
 - reg-names: Must be "config" for the PCIe configuration space.
 (The old way of getting the configuration address space from "ranges"
 is deprecated and should be avoided.)
+- num-lanes: number of lanes to use
+RC mode:
 - #address-cells: set to <3>
 - #size-cells: set to <2>
 - device_type: set to "pci"
 - ranges: ranges for the PCI memory and I/O regions
 - #interrupt-cells: set to <1>
-- interrupt-map-mask and interrupt-map: standard PCI properties
-   to define the mapping of the PCIe interface to interrupt
+- interrupt-map-mask and interrupt-map: standard PCI
+   properties to define the mapping of the PCIe interface to interrupt
numbers.
-- num-lanes: number of lanes to use
+EP mode:
+- num-ib-windows: number of inbound address translation
+windows
+- num-ob-windows: number of outbound address translation
+windows
 
 Optional properties:
-- num-viewport: number of view ports configured in hardware.  If a platform
-  does not specify it, the driver assumes 2.
 - num-lanes: number of lanes to use (this property should be specified unless
   the link is brought already up in BIOS)
 - reset-gpio: gpio pin number of power good signal
-- bus-range: PCI bus numbers covered (it is recommended for new devicetrees to
-  specify this property, to keep backwards compatibility a range of 0x00-0xff
-  is assumed if not present)
 - clocks: Must contain an entry for each entry in clock-names.
See ../clocks/clock-bindings.txt for details.
 - clock-names: Must include the following entries:
- "pcie"
- "pcie_bus"
+RC mode:
+- num-viewport: number of view ports configured in
+  hardware. If a platform does not specify it, the driver assumes 2.
+- bus-range: PCI bus numbers covered (it is recommended
+  for new devicetrees to specify this property, to keep backwards
+  compatibility a range of 0x00-0xff is assumed if not present)
+EP mode:
+- max-functions: maximum number of functions that can be
+  configured
 
 Example configuration:
 
-- 
1.7.9.5

[PATCH v2 2/8] ARM: DRA7: Thermal: Add slope and offset values

[Keerthy]

Currently the slope and offset values for calculating the
hot spot temperature of a particular thermal zone is part
of driver data. Pass them here instead and obtain the values
while of node parsing.

Signed-off-by: Keerthy 
---
 arch/arm/boot/dts/dra7.dtsi | 17 +
 1 file changed, 17 insertions(+)

diff --git a/arch/arm/boot/dts/dra7.dtsi b/arch/arm/boot/dts/dra7.dtsi
index 2c9e56f..10e09dc 100644
--- a/arch/arm/boot/dts/dra7.dtsi
+++ b/arch/arm/boot/dts/dra7.dtsi
@@ -1982,6 +1982,23 @@
 
 &cpu_thermal {
polling-delay = <500>; /* milliseconds */
+   coefficients = <0 2000>;
+};
+
+&gpu_thermal {
+   coefficients = <0 2000>;
+};
+
+&core_thermal {
+   coefficients = <0 2000>;
+};
+
+&dspeve_thermal {
+   coefficients = <0 2000>;
+};
+
+&iva_thermal {
+   coefficients = <0 2000>;
 };
 
 /include/ "dra7xx-clocks.dtsi"
-- 
1.9.1

[PATCH v2 7/8] thermal: ti-soc-thermal: Remove redundant constants

[Keerthy]

Now that slope and offset data are being passed from
device tree no need to populate in driver data.

Signed-off-by: Keerthy 
---
 drivers/thermal/ti-soc-thermal/dra752-thermal-data.c | 10 --
 drivers/thermal/ti-soc-thermal/omap3-thermal-data.c  |  4 
 drivers/thermal/ti-soc-thermal/omap4-thermal-data.c  |  6 --
 drivers/thermal/ti-soc-thermal/omap5-thermal-data.c  |  4 
 drivers/thermal/ti-soc-thermal/ti-bandgap.h  |  4 
 drivers/thermal/ti-soc-thermal/ti-thermal.h  | 16 
 6 files changed, 44 deletions(-)

diff --git a/drivers/thermal/ti-soc-thermal/dra752-thermal-data.c 
b/drivers/thermal/ti-soc-thermal/dra752-thermal-data.c
index 118d7d8..4167373 100644
--- a/drivers/thermal/ti-soc-thermal/dra752-thermal-data.c
+++ b/drivers/thermal/ti-soc-thermal/dra752-thermal-data.c
@@ -410,8 +410,6 @@
.domain = "cpu",
.register_cooling = ti_thermal_register_cpu_cooling,
.unregister_cooling = ti_thermal_unregister_cpu_cooling,
-   .slope = DRA752_GRADIENT_SLOPE,
-   .constant = DRA752_GRADIENT_CONST,
.slope_pcb = DRA752_GRADIENT_SLOPE_W_PCB,
.constant_pcb = DRA752_GRADIENT_CONST_W_PCB,
},
@@ -419,8 +417,6 @@
.registers = &dra752_gpu_temp_sensor_registers,
.ts_data = &dra752_gpu_temp_sensor_data,
.domain = "gpu",
-   .slope = DRA752_GRADIENT_SLOPE,
-   .constant = DRA752_GRADIENT_CONST,
.slope_pcb = DRA752_GRADIENT_SLOPE_W_PCB,
.constant_pcb = DRA752_GRADIENT_CONST_W_PCB,
},
@@ -428,8 +424,6 @@
.registers = &dra752_core_temp_sensor_registers,
.ts_data = &dra752_core_temp_sensor_data,
.domain = "core",
-   .slope = DRA752_GRADIENT_SLOPE,
-   .constant = DRA752_GRADIENT_CONST,
.slope_pcb = DRA752_GRADIENT_SLOPE_W_PCB,
.constant_pcb = DRA752_GRADIENT_CONST_W_PCB,
},
@@ -437,8 +431,6 @@
.registers = &dra752_dspeve_temp_sensor_registers,
.ts_data = &dra752_dspeve_temp_sensor_data,
.domain = "dspeve",
-   .slope = DRA752_GRADIENT_SLOPE,
-   .constant = DRA752_GRADIENT_CONST,
.slope_pcb = DRA752_GRADIENT_SLOPE_W_PCB,
.constant_pcb = DRA752_GRADIENT_CONST_W_PCB,
},
@@ -446,8 +438,6 @@
.registers = &dra752_iva_temp_sensor_registers,
.ts_data = &dra752_iva_temp_sensor_data,
.domain = "iva",
-   .slope = DRA752_GRADIENT_SLOPE,
-   .constant = DRA752_GRADIENT_CONST,
.slope_pcb = DRA752_GRADIENT_SLOPE_W_PCB,
.constant_pcb = DRA752_GRADIENT_CONST_W_PCB,
},
diff --git a/drivers/thermal/ti-soc-thermal/omap3-thermal-data.c 
b/drivers/thermal/ti-soc-thermal/omap3-thermal-data.c
index 3ee3434..c6d2179 100644
--- a/drivers/thermal/ti-soc-thermal/omap3-thermal-data.c
+++ b/drivers/thermal/ti-soc-thermal/omap3-thermal-data.c
@@ -91,8 +91,6 @@
.registers = &omap34xx_mpu_temp_sensor_registers,
.ts_data = &omap34xx_mpu_temp_sensor_data,
.domain = "cpu",
-   .slope = 0,
-   .constant = 2,
.slope_pcb = 0,
.constant_pcb = 2,
.register_cooling = NULL,
@@ -164,8 +162,6 @@
.registers = &omap36xx_mpu_temp_sensor_registers,
.ts_data = &omap36xx_mpu_temp_sensor_data,
.domain = "cpu",
-   .slope = 0,
-   .constant = 2,
.slope_pcb = 0,
.constant_pcb = 2,
.register_cooling = NULL,
diff --git a/drivers/thermal/ti-soc-thermal/omap4-thermal-data.c 
b/drivers/thermal/ti-soc-thermal/omap4-thermal-data.c
index d255d33..fd11133 100644
--- a/drivers/thermal/ti-soc-thermal/omap4-thermal-data.c
+++ b/drivers/thermal/ti-soc-thermal/omap4-thermal-data.c
@@ -82,8 +82,6 @@
.registers = &omap4430_mpu_temp_sensor_registers,
.ts_data = &omap4430_mpu_temp_sensor_data,
.domain = "cpu",
-   .slope = OMAP_GRADIENT_SLOPE_4430,
-   .constant = OMAP_GRADIENT_CONST_4430,
.slope_pcb = OMAP_GRADIENT_SLOPE_W_PCB_4430,
.constant_pcb = OMAP_GRADIENT_CONST_W_PCB_4430,
.register_cooling = ti_thermal_register_cpu_cooling,
@@ -222,8 +220,6 @@
.registers = &omap4460_mpu_temp_sensor_registers,
.ts_data = &omap4460_mpu_temp_sensor_data,
.domain = "cpu",
-   .slope = OMAP_GRADIENT_SLOPE_4460,
-   .constant = OMAP_GRADIENT_CONST_4460,
.slope_pcb = OMAP_GRADIENT_SLOPE_W_PCB_4460,
   

[PATCH v2 1/8] arm: dts: omap3: Add cpu_thermal zone

[Keerthy]

Add cpu_thermal zone.

Signed-off-by: Keerthy 
---
 arch/arm/boot/dts/omap3-cpu-thermal.dtsi | 20 
 arch/arm/boot/dts/omap34xx.dtsi  |  8 ++--
 arch/arm/boot/dts/omap36xx.dtsi  |  8 ++--
 3 files changed, 32 insertions(+), 4 deletions(-)
 create mode 100644 arch/arm/boot/dts/omap3-cpu-thermal.dtsi

diff --git a/arch/arm/boot/dts/omap3-cpu-thermal.dtsi 
b/arch/arm/boot/dts/omap3-cpu-thermal.dtsi
new file mode 100644
index 000..8dc3aa5
--- /dev/null
+++ b/arch/arm/boot/dts/omap3-cpu-thermal.dtsi
@@ -0,0 +1,20 @@
+/*
+ * Device Tree Source for OMAP3 SoC CPU thermal
+ *
+ * Copyright (C) 2017 Texas Instruments Incorporated - http://www.ti.com/
+ *
+ * This file is licensed under the terms of the GNU General Public License
+ * version 2.  This program is licensed "as is" without any warranty of any
+ * kind, whether express or implied.
+ */
+
+#include 
+
+cpu_thermal: cpu_thermal {
+   polling-delay-passive = <250>; /* milliseconds */
+   polling-delay = <1000>; /* milliseconds */
+   coefficients = <0 2>;
+
+   /* sensor   ID */
+   thermal-sensors = <&bandgap 0>;
+};
diff --git a/arch/arm/boot/dts/omap34xx.dtsi b/arch/arm/boot/dts/omap34xx.dtsi
index 834fdf1..ac4f879 100644
--- a/arch/arm/boot/dts/omap34xx.dtsi
+++ b/arch/arm/boot/dts/omap34xx.dtsi
@@ -14,7 +14,7 @@
 
 / {
cpus {
-   cpu@0 {
+   cpu: cpu@0 {
/* OMAP343x/OMAP35xx variants OPP1-5 */
operating-points = <
/* kHzuV */
@@ -56,12 +56,16 @@
};
};
 
-   bandgap@48002524 {
+   bandgap: bandgap@48002524 {
reg = <0x48002524 0x4>;
compatible = "ti,omap34xx-bandgap";
#thermal-sensor-cells = <0>;
};
};
+
+   thermal_zones: thermal-zones {
+   #include "omap3-cpu-thermal.dtsi"
+   };
 };
 
 &ssi {
diff --git a/arch/arm/boot/dts/omap36xx.dtsi b/arch/arm/boot/dts/omap36xx.dtsi
index d1a3e56..ade31d7 100644
--- a/arch/arm/boot/dts/omap36xx.dtsi
+++ b/arch/arm/boot/dts/omap36xx.dtsi
@@ -19,7 +19,7 @@
 
cpus {
/* OMAP3630/OMAP37xx 'standard device' variants OPP50 to OPP130 
*/
-   cpu@0 {
+   cpu: cpu@0 {
operating-points = <
/* kHzuV */
30  1012500
@@ -88,12 +88,16 @@
};
};
 
-   bandgap@48002524 {
+   bandgap: bandgap@48002524 {
reg = <0x48002524 0x4>;
compatible = "ti,omap36xx-bandgap";
#thermal-sensor-cells = <0>;
};
};
+
+   thermal_zones: thermal-zones {
+   #include "omap3-cpu-thermal.dtsi"
+   };
 };
 
 /* OMAP3630 needs dss_96m_fck for VENC */
-- 
1.9.1

[PATCH v2 3/8] ARM: OMAP5: Thermal: Add slope and offset values

[Keerthy]

Currently the slope and offset values for calculating the
hot spot temperature of a particular thermal zone is part
of driver data. Pass them here instead and obtain the values
while of node parsing.

Signed-off-by: Keerthy 
---
 arch/arm/boot/dts/omap5.dtsi | 9 +
 1 file changed, 9 insertions(+)

diff --git a/arch/arm/boot/dts/omap5.dtsi b/arch/arm/boot/dts/omap5.dtsi
index 222155c..eaff2a5 100644
--- a/arch/arm/boot/dts/omap5.dtsi
+++ b/arch/arm/boot/dts/omap5.dtsi
@@ -1127,6 +1127,15 @@
 
 &cpu_thermal {
polling-delay = <500>; /* milliseconds */
+   coefficients = <65 (-1791)>;
 };
 
 /include/ "omap54xx-clocks.dtsi"
+
+&gpu_thermal {
+   coefficients = <117 (-2992)>;
+};
+
+&core_thermal {
+   coefficients = <0 2000>;
+};
-- 
1.9.1

[PATCH v2 8/8] thermal: ti-soc-thermal: Remove redundant code

[Keerthy]

ti_thermal_expose_sensor always takes the
devm_thermal_zone_of_sensor_register call for registration
with the device tree nodes present for all the bandgap sensors
for omap3/4/5 and dra7 family. There are large chunks of unused
code. Removing all of them.

Signed-off-by: Keerthy 
---
 drivers/thermal/ti-soc-thermal/ti-thermal-common.c | 154 +
 1 file changed, 3 insertions(+), 151 deletions(-)

diff --git a/drivers/thermal/ti-soc-thermal/ti-thermal-common.c 
b/drivers/thermal/ti-soc-thermal/ti-thermal-common.c
index 2054a5c..02790f6 100644
--- a/drivers/thermal/ti-soc-thermal/ti-thermal-common.c
+++ b/drivers/thermal/ti-soc-thermal/ti-thermal-common.c
@@ -126,119 +126,6 @@ static inline int ti_thermal_get_temp(struct 
thermal_zone_device *thermal,
return __ti_thermal_get_temp(data, temp);
 }
 
-/* Bind callback functions for thermal zone */
-static int ti_thermal_bind(struct thermal_zone_device *thermal,
-  struct thermal_cooling_device *cdev)
-{
-   struct ti_thermal_data *data = thermal->devdata;
-   int id;
-
-   if (!data || IS_ERR(data))
-   return -ENODEV;
-
-   /* check if this is the cooling device we registered */
-   if (data->cool_dev != cdev)
-   return 0;
-
-   id = data->sensor_id;
-
-   /* Simple thing, two trips, one passive another critical */
-   return thermal_zone_bind_cooling_device(thermal, 0, cdev,
-   /* bind with min and max states defined by cpu_cooling */
-   THERMAL_NO_LIMIT,
-   THERMAL_NO_LIMIT,
-   THERMAL_WEIGHT_DEFAULT);
-}
-
-/* Unbind callback functions for thermal zone */
-static int ti_thermal_unbind(struct thermal_zone_device *thermal,
-struct thermal_cooling_device *cdev)
-{
-   struct ti_thermal_data *data = thermal->devdata;
-
-   if (!data || IS_ERR(data))
-   return -ENODEV;
-
-   /* check if this is the cooling device we registered */
-   if (data->cool_dev != cdev)
-   return 0;
-
-   /* Simple thing, two trips, one passive another critical */
-   return thermal_zone_unbind_cooling_device(thermal, 0, cdev);
-}
-
-/* Get mode callback functions for thermal zone */
-static int ti_thermal_get_mode(struct thermal_zone_device *thermal,
-  enum thermal_device_mode *mode)
-{
-   struct ti_thermal_data *data = thermal->devdata;
-
-   if (data)
-   *mode = data->mode;
-
-   return 0;
-}
-
-/* Set mode callback functions for thermal zone */
-static int ti_thermal_set_mode(struct thermal_zone_device *thermal,
-  enum thermal_device_mode mode)
-{
-   struct ti_thermal_data *data = thermal->devdata;
-   struct ti_bandgap *bgp;
-
-   bgp = data->bgp;
-
-   if (!data->ti_thermal) {
-   dev_notice(&thermal->device, "thermal zone not registered\n");
-   return 0;
-   }
-
-   mutex_lock(&data->ti_thermal->lock);
-
-   if (mode == THERMAL_DEVICE_ENABLED)
-   data->ti_thermal->polling_delay = FAST_TEMP_MONITORING_RATE;
-   else
-   data->ti_thermal->polling_delay = 0;
-
-   mutex_unlock(&data->ti_thermal->lock);
-
-   data->mode = mode;
-   ti_bandgap_write_update_interval(bgp, data->sensor_id,
-   data->ti_thermal->polling_delay);
-   thermal_zone_device_update(data->ti_thermal, THERMAL_EVENT_UNSPECIFIED);
-   dev_dbg(&thermal->device, "thermal polling set for duration=%d msec\n",
-   data->ti_thermal->polling_delay);
-
-   return 0;
-}
-
-/* Get trip type callback functions for thermal zone */
-static int ti_thermal_get_trip_type(struct thermal_zone_device *thermal,
-   int trip, enum thermal_trip_type *type)
-{
-   if (!ti_thermal_is_valid_trip(trip))
-   return -EINVAL;
-
-   if (trip + 1 == OMAP_TRIP_NUMBER)
-   *type = THERMAL_TRIP_CRITICAL;
-   else
-   *type = THERMAL_TRIP_PASSIVE;
-
-   return 0;
-}
-
-/* Get trip temperature callback functions for thermal zone */
-static int ti_thermal_get_trip_temp(struct thermal_zone_device *thermal,
-   int trip, int *temp)
-{
-   if (!ti_thermal_is_valid_trip(trip))
-   return -EINVAL;
-
-   *temp = ti_thermal_get_trip_value(trip);
-
-   return 0;
-}
-
 static int __ti_thermal_get_trend(void *p, int trip, enum thermal_trend *trend)
 {
struct ti_thermal_data *data = p;
@@ -262,38 +149,11 @@ static int __ti_thermal_get_trend(void *p, int trip, enum 
thermal_trend *trend)
return 0;
 }
 
-/* Get the temperature trend callback functions for thermal zone */
-static int ti_thermal_get_trend(struct thermal_zone_device *thermal,
-

[PATCH v2 5/8] ARM: OMAP4460: Thermal: Add slope and offset values

[Keerthy]

Currently the slope and offset values for calculating the
hot spot temperature of a particular thermal zone is part
of driver data. Pass them here instead and obtain the values
while of node parsing.

Signed-off-by: Keerthy 
---
 arch/arm/boot/dts/omap4460.dtsi | 4 
 1 file changed, 4 insertions(+)

diff --git a/arch/arm/boot/dts/omap4460.dtsi b/arch/arm/boot/dts/omap4460.dtsi
index ef66e12..c43f2a2 100644
--- a/arch/arm/boot/dts/omap4460.dtsi
+++ b/arch/arm/boot/dts/omap4460.dtsi
@@ -90,4 +90,8 @@
 
 };
 
+&cpu_thermal {
+   coefficients = <348 (-9301)>;
+};
+
 /include/ "omap446x-clocks.dtsi"
-- 
1.9.1

[PATCH v2 6/8] thermal: ti-soc-thermal: Fetch slope and offset from DT

[Keerthy]

Currently slope and offset values for calculating the hot spot
temperature of a thermal zone is being taken directly from driver
data. So fetch them from device tree.

Signed-off-by: Keerthy 
---
 drivers/thermal/ti-soc-thermal/ti-thermal-common.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/thermal/ti-soc-thermal/ti-thermal-common.c 
b/drivers/thermal/ti-soc-thermal/ti-thermal-common.c
index 0586bd0..2054a5c 100644
--- a/drivers/thermal/ti-soc-thermal/ti-thermal-common.c
+++ b/drivers/thermal/ti-soc-thermal/ti-thermal-common.c
@@ -96,8 +96,8 @@ static inline int __ti_thermal_get_temp(void *devdata, int 
*temp)
return ret;
 
/* Default constants */
-   slope = s->slope;
-   constant = s->constant;
+   slope = thermal_zone_get_slope(data->ti_thermal);
+   constant = thermal_zone_get_offset(data->ti_thermal);
 
pcb_tz = data->pcb_tz;
/* In case pcb zone is available, use the extrapolation rule with it */
-- 
1.9.1

[PATCH net] rxrpc: rxrpc_kernel_send_data() needs to handle failed call better

[David Howells]

If rxrpc_kernel_send_data() is asked to send data through a call that has
already failed (due to a remote abort, received protocol error or network
error), then return the associated error code saved in the call rather than
ESHUTDOWN.

This allows the caller to work out whether to ask for the abort code or not
based on this.

Signed-off-by: David Howells 
---

 net/rxrpc/sendmsg.c |5 +++--
 1 file changed, 3 insertions(+), 2 deletions(-)

diff --git a/net/rxrpc/sendmsg.c b/net/rxrpc/sendmsg.c
index 47ccfeacc1c6..97ab214ca411 100644
--- a/net/rxrpc/sendmsg.c
+++ b/net/rxrpc/sendmsg.c
@@ -618,8 +618,9 @@ int rxrpc_kernel_send_data(struct socket *sock, struct 
rxrpc_call *call,
ret = rxrpc_send_data(rxrpc_sk(sock->sk), call, msg, len);
break;
case RXRPC_CALL_COMPLETE:
-   /* It's too late for this call */
-   ret = -ESHUTDOWN;
+   read_lock_bh(&call->state_lock);
+   ret = -call->error;
+   read_unlock_bh(&call->state_lock);
break;
default:
 /* Request phase complete for this client call */

[PATCH net] net: Work around lockdep limitation in sockets that use sockets

[David Howells]

Lockdep issues a circular dependency warning when AFS issues an operation
through AF_RXRPC from a context in which the VFS/VM holds the mmap_sem.

The theory lockdep comes up with is as follows:

 (1) If the pagefault handler decides it needs to read pages from AFS, it
 calls AFS with mmap_sem held and AFS begins an AF_RXRPC call, but
 creating a call requires the socket lock:

mmap_sem must be taken before sk_lock-AF_RXRPC

 (2) afs_open_socket() opens an AF_RXRPC socket and binds it.  rxrpc_bind()
 binds the underlying UDP socket whilst holding its socket lock.
 inet_bind() takes its own socket lock:

sk_lock-AF_RXRPC must be taken before sk_lock-AF_INET

 (3) Reading from a TCP socket into a userspace buffer might cause a fault
 and thus cause the kernel to take the mmap_sem, but the TCP socket is
 locked whilst doing this:

sk_lock-AF_INET must be taken before mmap_sem

However, lockdep's theory is wrong in this instance because it deals only
with lock classes and not individual locks.  The AF_INET lock in (2) isn't
really equivalent to the AF_INET lock in (3) as the former deals with a
socket entirely internal to the kernel that never sees userspace.  This is
a limitation in the design of lockdep.

Fix the general case by:

 (1) Double up all the locking keys used in sockets so that one set are
 used if the socket is created by userspace and the other set is used
 if the socket is created by the kernel.

 (2) Store the kern parameter passed to sk_alloc() in a variable in the
 sock struct (sk_kern_sock).  This informs sock_lock_init(),
 sock_init_data() and sk_clone_lock() as to the lock keys to be used.

 Note that the child created by sk_clone_lock() inherits the parent's
 kern setting.

 (3) Add a 'kern' parameter to ->accept() that is analogous to the one
 passed in to ->create() that distinguishes whether kernel_accept() or
 sys_accept4() was the caller and can be passed to sk_alloc().

 Note that a lot of accept functions merely dequeue an already
 allocated socket.  I haven't touched these as the new socket already
 exists before we get the parameter.

 Note also that there are a couple of places where I've made the accepted
 socket unconditionally kernel-based:

irda_accept()
rds_rcp_accept_one()
tcp_accept_from_sock()

 because they follow a sock_create_kern() and accept off of that.

Whilst creating this, I noticed that lustre and ocfs don't create sockets
through sock_create_kern() and thus they aren't marked as for-kernel,
though they appear to be internal.  I wonder if these should do that so
that they use the new set of lock keys.

Signed-off-by: David Howells 
---

 crypto/af_alg.c   |9 +-
 crypto/algif_hash.c   |9 +-
 drivers/staging/lustre/lnet/lnet/lib-socket.c |4 -
 fs/dlm/lowcomms.c |2 
 fs/ocfs2/cluster/tcp.c|2 
 include/crypto/if_alg.h   |2 
 include/linux/net.h   |2 
 include/net/inet_common.h |3 -
 include/net/inet_connection_sock.h|2 
 include/net/sctp/structs.h|3 -
 include/net/sock.h|9 +-
 net/atm/svc.c |5 +
 net/ax25/af_ax25.c|3 -
 net/bluetooth/l2cap_sock.c|2 
 net/bluetooth/rfcomm/sock.c   |3 -
 net/bluetooth/sco.c   |2 
 net/core/sock.c   |  106 +
 net/decnet/af_decnet.c|5 +
 net/ipv4/af_inet.c|5 +
 net/ipv4/inet_connection_sock.c   |2 
 net/irda/af_irda.c|5 +
 net/iucv/af_iucv.c|2 
 net/llc/af_llc.c  |4 +
 net/netrom/af_netrom.c|3 -
 net/nfc/llcp_sock.c   |2 
 net/phonet/pep.c  |6 +
 net/phonet/socket.c   |4 -
 net/rds/tcp_listen.c  |2 
 net/rose/af_rose.c|3 -
 net/sctp/ipv6.c   |5 +
 net/sctp/protocol.c   |5 +
 net/sctp/socket.c |4 -
 net/smc/af_smc.c  |2 
 net/socket.c  |4 -
 net/tipc/socket.c |8 +-
 net/unix/af_unix.c|5 +
 net/vmw_vsock/af_vsock.c  |3 -
 net/x25/af_x25.c  |3 -
 38 files changed, 142 insertions(+), 108 deletions(-)

diff --git a/crypto/af_alg.c b/crypto/af

Re: [PATCH] phy: phy-exynos-pcie: fix the wrong error return

[Kishon Vijay Abraham I]

On Wednesday 08 March 2017 01:52 PM, Jaehoon Chung wrote:
> When it doesn't get the blk_base's resource, it was returned
> the error about phy_base, not blk_base.
> This patch is for fixing the wrong error return about blk_base.
> 
> Fixes: cf0adb8e281b ("phy: phy-exynos-pcie: Add support for Exynos PCIe PHY")
> 
> Signed-off-by: Jaehoon Chung 

merged, thanks.

-Kishon
> ---
>  drivers/phy/phy-exynos-pcie.c | 4 ++--
>  1 file changed, 2 insertions(+), 2 deletions(-)
> 
> diff --git a/drivers/phy/phy-exynos-pcie.c b/drivers/phy/phy-exynos-pcie.c
> index 4f60b83..60baf25 100644
> --- a/drivers/phy/phy-exynos-pcie.c
> +++ b/drivers/phy/phy-exynos-pcie.c
> @@ -254,8 +254,8 @@ static int exynos_pcie_phy_probe(struct platform_device 
> *pdev)
>  
>   res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
>   exynos_phy->blk_base = devm_ioremap_resource(dev, res);
> - if (IS_ERR(exynos_phy->phy_base))
> - return PTR_ERR(exynos_phy->phy_base);
> + if (IS_ERR(exynos_phy->blk_base))
> + return PTR_ERR(exynos_phy->blk_base);
>  
>   exynos_phy->drv_data = drv_data;
>  
> 

Re: [lkp-robot] [x86] ed3ce2a917: BUG:unable_to_handle_kernel

[Borislav Petkov]

On Thu, Mar 09, 2017 at 10:13:10AM +0800, Ye Xiaolong wrote:
> >Anyway, the diff is below, please try that ontop of tip's x86/asm branch
> >which already has the clear_page patch:
> >
> >http://git.kernel.org/cgit/linux/kernel/git/tip/tip.git/log/?h=x86/asm
> >
> >Thanks!
> 
> Hmm, I've checkout the tip's x86/asm branch (HEAD is f25d38475 "x86/asm:
> Optimize clear_page()"), but I failed to apply your diff on top of it (error
> log as below).

Right, Ingo merged the diff I gave you already into the patch there
so that x86/asm already contains the fixed version. You could run the
current tip/x86/asm branch to confirm that it fixes the issue for you.

Thanks.

-- 
Regards/Gruss,
Boris.

Good mailing practices for 400: avoid top-posting and trim the reply.

Re: [PATCH v19 0/4] Introduce usb charger framework to deal with the usb gadget power negotation

[Baolin Wang]

Hi,

On 9 March 2017 at 09:50, Jun Li  wrote:
> Hi,
>
>> -Original Message-
>> From: Baolin Wang [mailto:baolin.w...@linaro.org]
>> Sent: Tuesday, March 07, 2017 5:39 PM
>> To: NeilBrown 
>> Cc: Felipe Balbi ; Greg KH ;
>> Sebastian Reichel ; Dmitry Eremin-Solenikov
>> ; David Woodhouse ;
>> r...@kernel.org; Jun Li ; Marek Szyprowski
>> ; Ruslan Bilovol ;
>> Peter Chen ; Alan Stern
>> ; grygorii.stras...@ti.com; Yoshihiro Shimoda
>> ; Lee Jones ;
>> Mark Brown ; John Stultz ;
>> Charles Keepax ;
>> patc...@opensource.wolfsonmicro.com; Linux PM list > p...@vger.kernel.org>; USB ; device-
>> mainlin...@lists.linuxfoundation.org; LKML 
>> Subject: Re: [PATCH v19 0/4] Introduce usb charger framework to deal with
>> the usb gadget power negotation
>>
>> On 3 March 2017 at 10:23, NeilBrown  wrote:
>> > On Mon, Feb 20 2017, Baolin Wang wrote:
>> >
>> >> Currently the Linux kernel does not provide any standard integration
>> >> of this feature that integrates the USB subsystem with the system
>> >> power regulation provided by PMICs meaning that either vendors must
>> >> add this in their kernels or USB gadget devices based on Linux (such
>> >> as mobile phones) may not behave as they should. Thus provide a
>> standard framework for doing this in kernel.
>> >>
>> >> Now introduce one user with wm831x_power to support and test the usb
>> charger.
>> >> Another user introduced to support charger detection by Jun Li:
>> >> https://www.spinics.net/lists/linux-usb/msg139425.html
>> >> Moreover there may be other potential users will use it in future.
>> >>
>> >> 1. Before v19 patchset we've fixed below issues in extcon subsystem
>> >> and usb phy driver, now all were merged. (Thanks for Neil's
>> >> suggestion)
>> >> (1) Have fixed the inconsistencies with USB connector types in extcon
>> >> subsystem by following links:
>> >> https://lkml.org/lkml/2016/12/21/13
>> >> https://lkml.org/lkml/2016/12/21/15
>> >> https://lkml.org/lkml/2016/12/21/79
>> >> https://lkml.org/lkml/2017/1/3/13
>> >>
>> >> (2) Instead of using 'set_power' callback in phy drivers, we will
>> >> introduce USB charger to set PMIC current drawn from USB
>> >> configuration, moreover some 'set_power' callbacks did not implement
>> >> anything to set PMIC current, thus remove them by following links:
>> >> https://lkml.org/lkml/2017/1/18/436
>> >> https://lkml.org/lkml/2017/1/18/439
>> >> https://lkml.org/lkml/2017/1/18/438
>> >> Now only two phy drivers (phy-isp1301-omap.c and phy-gpio-vbus-usb.c)
>> >> still used 'set_power' callback to set current, we can remove them in
>> >> future. (I have no platform with enabling these two phy drivers, so I
>> >> can not test them if I converted 'set_power' callback to USB
>> >> charger.)
>> >>
>> >> 2. Some issues pointed by Neil Brown were sill kept in this v19
>> >> patchset, and I expalined each issue and may be need discuss again:
>> >> (1) Change all usb phys to register an extcon and to send appropriate
>> notifications.
>> >> Firstly, now only 3 USB phy drivers (phy-qcom-8x16-usb.c,
>> >> phy-omap-otg.c and
>> >> phy-msm-usb.c) had registered an extcon, mostly did not. I can not
>> >> change all usb phys to register an extcon, since there are no extcon
>> >> device to register for these different phy drivers.
>> >
>> > You don't have to change every driver.  You just need to make it easy
>> > and obvious how to change drivers in a consistent coherent way.
>> > For a start you would add a 'struct extcon_dev' to 'struct usb_phy',
>> > and possibly add or extend some 'static inline's in linux/usb/phy.h to
>> > send notification on that extcon (if it is non-NULL).
>> > e.g. usb_phy_vbus_on() could send an extcon notification.
>> >
>> > Then any phy driver which adds support for setting phy->extcon_dev
>> > appropriately, immediately gets the relevant notifications sent.
>>
>> OK. We can make these extcon related code into phy common part.
>>
>
> Will generic phy need add extcon as well?

Yes, will add a 'struct extcon_dev*' in 'struct usb_phy', which will
be common code.

>
>> >
>> >> Secondly, I also agreed with Peter's comments: Not only USB PHY to
>> >> register an extcon, but also for the drivers which can detect USB
>> >> charger type, it may be USB controller driver, USB type-c driver,
>> >> pmic driver, and these drivers may not have an extcon device since
>> >> the internal part can finish the vbus detect.
>> >
>> > Whichever part can detect vbus, the driver for that part must be able
>> > to find the extcon and trigger a notification.
>> > Maybe one part can detect VBUS, another can measure the resistance on
>> > ID and a third can work through the state machine to determine if D+
>> > and D- are shorted together.
>> > Somehow these three need to work together to determine what is
>> plugged
>> > in to the external connection port.  Somewhere there much an 'extcon'
>> > device which represents that port and which the three devices can find
>> > and can interact with.
>> > I think it makes se

Re: [lkp-robot] [x86] ed3ce2a917: BUG:unable_to_handle_kernel

[Borislav Petkov]

On Thu, Mar 09, 2017 at 10:30:52AM +0800, Fengguang Wu wrote:
> One possible improvement is to provide "lkp qemu" reproduce steps for
> kernel oops -- it would be way more convenient and safe to follow than
> "lkp run", since the later risks hang the physical machine.

Right, that would mean that the bug should be triggerable in qemu. Some
bugs happen on baremetal only though.

> As for the test description, the dmesg carries markers for the user
> space test start/stop points, so the robot can easily tell whether the
> oops happen during the test or before/after the test -- the latter may
> well (but not always) indicate the oops is not relevant to the testcase,
> but to the regular kernel boot/reboot/kexec process.

Right, if that is made part of the report, it would make the reports
better. Something like: "this happens when preparing our test env" or
"this happens while running this test blabla".

Thanks guys and keep up the good work!

-- 
Regards/Gruss,
Boris.

Good mailing practices for 400: avoid top-posting and trim the reply.

Re: [PATCH 4/4] ASoC: sun8i-codec: Convert to use SND_SOC_DAPM_AIF_IN

[Mylene Josserand]

Hi Chen-Yu,

Thank you for the review.

On 06/03/2017 10:56, Chen-Yu Tsai wrote:

On Fri, Feb 10, 2017 at 5:41 PM, Mylène Josserand
 wrote:

Update the driver to use SND_SOC_DAPM_AIF_IN instead of
SND_SOC_DAPM_DAC.

Set the route names so it must be updated on the device tree too.

Signed-off-by: Mylène Josserand 
---
 arch/arm/boot/dts/sun8i-a33.dtsi |  4 ++--


This patch looks OK, but having the DTS changes in the same patch
probably isn't a good idea. I would really like to see this series
merged for 4.11, so we can expose a good mixer interface to userspace
during the first kernel release supporting the A33 codec. That likely
means some breakage between when the asoc bits and the dts bits land
though.


Yes, as it means some breakage, I did not know if 2 patches will be fine 
or not.




Maxime, any ideas?



I asked him directly and he agrees.

It is fine for me so I will send a v2 with this patch split.

Best regards,

--
Mylène Josserand, Free Electrons
Embedded Linux and Kernel engineering
http://free-electrons.com



Regards
ChenYu


 sound/soc/sunxi/sun8i-codec.c| 20 +++-
 2 files changed, 13 insertions(+), 11 deletions(-)

diff --git a/arch/arm/boot/dts/sun8i-a33.dtsi b/arch/arm/boot/dts/sun8i-a33.dtsi
index 4e34ec6613a0..e9e2e7312460 100644
--- a/arch/arm/boot/dts/sun8i-a33.dtsi
+++ b/arch/arm/boot/dts/sun8i-a33.dtsi
@@ -78,8 +78,8 @@
simple-audio-card,mclk-fs = <512>;
simple-audio-card,aux-devs = <&codec_analog>;
simple-audio-card,routing =
-   "Left DAC", "Digital Left DAC",
-   "Right DAC", "Digital Right DAC";
+   "Left DAC", "AIF1 Slot 0 Left",
+   "Right DAC", "AIF1 Slot 0 Right";
status = "disabled";

simple-audio-card,cpu {
diff --git a/sound/soc/sunxi/sun8i-codec.c b/sound/soc/sunxi/sun8i-codec.c
index a75a983974d9..9b15a5ee235f 100644
--- a/sound/soc/sunxi/sun8i-codec.c
+++ b/sound/soc/sunxi/sun8i-codec.c
@@ -281,11 +281,13 @@ static const struct snd_soc_dapm_widget 
sun8i_codec_dapm_widgets[] = {
SND_SOC_DAPM_SUPPLY("DAC", SUN8I_DAC_DIG_CTRL, SUN8I_DAC_DIG_CTRL_ENDA,
0, NULL, 0),

-   /* Analog DAC */
-   SND_SOC_DAPM_DAC("Digital Left DAC", "Playback", SUN8I_AIF1_DACDAT_CTRL,
-SUN8I_AIF1_DACDAT_CTRL_AIF1_DA0L_ENA, 0),
-   SND_SOC_DAPM_DAC("Digital Right DAC", "Playback", 
SUN8I_AIF1_DACDAT_CTRL,
-SUN8I_AIF1_DACDAT_CTRL_AIF1_DA0R_ENA, 0),
+   /* Analog DAC AIF */
+   SND_SOC_DAPM_AIF_IN("AIF1 Slot 0 Left", "Playback", 0,
+   SUN8I_AIF1_DACDAT_CTRL,
+   SUN8I_AIF1_DACDAT_CTRL_AIF1_DA0L_ENA, 0),
+   SND_SOC_DAPM_AIF_IN("AIF1 Slot 0 Right", "Playback", 0,
+   SUN8I_AIF1_DACDAT_CTRL,
+   SUN8I_AIF1_DACDAT_CTRL_AIF1_DA0R_ENA, 0),

/* DAC Mixers */
SOC_MIXER_ARRAY("Left Digital DAC Mixer", SND_SOC_NOPM, 0, 0,
@@ -329,14 +331,14 @@ static const struct snd_soc_dapm_route 
sun8i_codec_dapm_routes[] = {
{ "DAC", NULL, "MODCLK DAC" },

/* DAC Routes */
-   { "Digital Left DAC", NULL, "DAC" },
-   { "Digital Right DAC", NULL, "DAC" },
+   { "AIF1 Slot 0 Right", NULL, "DAC" },
+   { "AIF1 Slot 0 Left", NULL, "DAC" },

/* DAC Mixer Routes */
{ "Left Digital DAC Mixer", "AIF1 Slot 0 Digital DAC Playback Switch",
- "Digital Left DAC"},
+ "AIF1 Slot 0 Left"},
{ "Right Digital DAC Mixer", "AIF1 Slot 0 Digital DAC Playback Switch ",
- "Digital Right DAC"},
+ "AIF1 Slot 0 Right"},
 };

 static struct snd_soc_dai_ops sun8i_codec_dai_ops = {
--
2.11.0

Re: [RESEND PATCH v3 4/8] phy: phy-mt65xx-usb3: move clock from phy node into port nodes

[Kishon Vijay Abraham I]

Hi,

On Monday 06 March 2017 07:19 PM, Chunfeng Yun wrote:
> the reference clock of HighSpeed port is 48M which comes from PLL;
> the reference clock of SuperSpeed port is 26M which usually comes
> from 26M oscillator directly, but some SoCs are not, add it for
> compatibility, and put them into port node for flexibility.

Won't this break the old dt compatiblity? Making change in dt is fine as long
as older dtb's are still supported.

Thanks
Kishon
> 
> Signed-off-by: Chunfeng Yun 
> ---
>  drivers/phy/phy-mt65xx-usb3.c |   21 +++--
>  1 file changed, 11 insertions(+), 10 deletions(-)
> 
> diff --git a/drivers/phy/phy-mt65xx-usb3.c b/drivers/phy/phy-mt65xx-usb3.c
> index 7fff482..f4a3505 100644
> --- a/drivers/phy/phy-mt65xx-usb3.c
> +++ b/drivers/phy/phy-mt65xx-usb3.c
> @@ -153,6 +153,7 @@ struct mt65xx_phy_pdata {
>  struct mt65xx_phy_instance {
>   struct phy *phy;
>   void __iomem *port_base;
> + struct clk *ref_clk;/* reference clock of anolog phy */
>   u32 index;
>   u8 type;
>  };
> @@ -160,7 +161,6 @@ struct mt65xx_phy_instance {
>  struct mt65xx_u3phy {
>   struct device *dev;
>   void __iomem *sif_base; /* only shared sif */
> - struct clk *u3phya_ref; /* reference clock of usb3 anolog phy */
>   const struct mt65xx_phy_pdata *pdata;
>   struct mt65xx_phy_instance **phys;
>   int nphys;
> @@ -449,9 +449,9 @@ static int mt65xx_phy_init(struct phy *phy)
>   struct mt65xx_u3phy *u3phy = dev_get_drvdata(phy->dev.parent);
>   int ret;
>  
> - ret = clk_prepare_enable(u3phy->u3phya_ref);
> + ret = clk_prepare_enable(instance->ref_clk);
>   if (ret) {
> - dev_err(u3phy->dev, "failed to enable u3phya_ref\n");
> + dev_err(u3phy->dev, "failed to enable ref_clk\n");
>   return ret;
>   }
>  
> @@ -494,7 +494,7 @@ static int mt65xx_phy_exit(struct phy *phy)
>   if (instance->type == PHY_TYPE_USB2)
>   phy_instance_exit(u3phy, instance);
>  
> - clk_disable_unprepare(u3phy->u3phya_ref);
> + clk_disable_unprepare(instance->ref_clk);
>   return 0;
>  }
>  
> @@ -594,12 +594,6 @@ static int mt65xx_u3phy_probe(struct platform_device 
> *pdev)
>   return PTR_ERR(u3phy->sif_base);
>   }
>  
> - u3phy->u3phya_ref = devm_clk_get(dev, "u3phya_ref");
> - if (IS_ERR(u3phy->u3phya_ref)) {
> - dev_err(dev, "error to get u3phya_ref\n");
> - return PTR_ERR(u3phy->u3phya_ref);
> - }
> -
>   port = 0;
>   for_each_child_of_node(np, child_np) {
>   struct mt65xx_phy_instance *instance;
> @@ -634,6 +628,13 @@ static int mt65xx_u3phy_probe(struct platform_device 
> *pdev)
>   goto put_child;
>   }
>  
> + instance->ref_clk = devm_clk_get(&phy->dev, "ref");
> + if (IS_ERR(instance->ref_clk)) {
> + dev_err(dev, "failed to get ref_clk(id-%d)\n", port);
> + retval = PTR_ERR(instance->ref_clk);
> + goto put_child;
> + }
> +
>   instance->phy = phy;
>   instance->index = port;
>   phy_set_drvdata(phy, instance);
> 

[PATCH v2 0/8] thermal: ti-soc-thermal: Migrate slope/offset data to device tree

[Keerthy]

Currently the slope and offset values for calculating the
hot spot temperature of a particular thermal zone is part
of driver data. Pass them here instead and obtain the values
while of node parsing.

Tested for the slope and constant values on DRA7-EVM, OMAP3-BEAGLE. 

Changes in v2:

  * Added OMAP3 changes along with DRA7/OMAP4/OMAP5.

Keerthy (8):
  arm: dts: omap3: Add cpu_thermal zone
  ARM: DRA7: Thermal: Add slope and offset values
  ARM: OMAP5: Thermal: Add slope and offset values
  ARM: OMAP443x: Thermal: Add slope and offset values
  ARM: OMAP4460: Thermal: Add slope and offset values
  thermal: ti-soc-thermal: Fetch slope and offset from DT
  thermal: ti-soc-thermal: Remove redundant constants
  thermal: ti-soc-thermal: Remove redundant code

 arch/arm/boot/dts/dra7.dtsi|  17 +++
 arch/arm/boot/dts/omap3-cpu-thermal.dtsi   |  20 +++
 arch/arm/boot/dts/omap34xx.dtsi|   8 +-
 arch/arm/boot/dts/omap36xx.dtsi|   8 +-
 arch/arm/boot/dts/omap443x.dtsi|   4 +
 arch/arm/boot/dts/omap4460.dtsi|   4 +
 arch/arm/boot/dts/omap5.dtsi   |   9 ++
 .../thermal/ti-soc-thermal/dra752-thermal-data.c   |  10 --
 .../thermal/ti-soc-thermal/omap3-thermal-data.c|   4 -
 .../thermal/ti-soc-thermal/omap4-thermal-data.c|   6 -
 .../thermal/ti-soc-thermal/omap5-thermal-data.c|   4 -
 drivers/thermal/ti-soc-thermal/ti-bandgap.h|   4 -
 drivers/thermal/ti-soc-thermal/ti-thermal-common.c | 158 +
 drivers/thermal/ti-soc-thermal/ti-thermal.h|  16 ---
 14 files changed, 71 insertions(+), 201 deletions(-)
 create mode 100644 arch/arm/boot/dts/omap3-cpu-thermal.dtsi

-- 
1.9.1

[PATCH v2 4/8] ARM: OMAP443x: Thermal: Add slope and offset values

[Keerthy]

Currently the slope and offset values for calculating the
hot spot temperature of a particular thermal zone is part
of driver data. Pass them here instead and obtain the values
while of node parsing.

Signed-off-by: Keerthy 
---
 arch/arm/boot/dts/omap443x.dtsi | 4 
 1 file changed, 4 insertions(+)

diff --git a/arch/arm/boot/dts/omap443x.dtsi b/arch/arm/boot/dts/omap443x.dtsi
index fc6a861..03c8ad9 100644
--- a/arch/arm/boot/dts/omap443x.dtsi
+++ b/arch/arm/boot/dts/omap443x.dtsi
@@ -71,4 +71,8 @@
 
 };
 
+&cpu_thermal {
+   coefficients = <0 2>;
+};
+
 /include/ "omap443x-clocks.dtsi"
-- 
1.9.1

Re: phy-qcom-usb-hs.c:undefined reference to `extcon_unregister_notifier'

[Kishon Vijay Abraham I]

On Tuesday 07 March 2017 09:31 PM, Stephen Boyd wrote:
> Quoting kbuild test robot (2017-03-06 09:19:50)
>> Hi Stephen,
>>
>> FYI, the error/warning still remains.
>>
>> tree:   https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git 
>> master
>> head:   c1ae3cfa0e89fa1a7ecc4c99031f5e9ae99d9201
>> commit: e2427b09ba929c2b9d02556b74a85161a7364792 phy: Add support for 
>> Qualcomm's USB HS phy
>> date:   5 weeks ago
>> config: i386-randconfig-x019-03061728 (attached as .config)
>> compiler: gcc-6 (Debian 6.2.0-3) 6.2.0 20160901
>> reproduce:
>> git checkout e2427b09ba929c2b9d02556b74a85161a7364792
>> # save the attached .config to linux build tree
>> make ARCH=i386 
>>
>> All errors (new ones prefixed by >>):
>>
>>drivers/built-in.o: In function `qcom_usb_hs_phy_power_off':
 phy-qcom-usb-hs.c:(.text+0x1248): undefined reference to 
 `extcon_unregister_notifier'
>>drivers/built-in.o: In function `qcom_usb_hs_phy_power_on':
 phy-qcom-usb-hs.c:(.text+0x1389): undefined reference to `extcon_get_state'
 phy-qcom-usb-hs.c:(.text+0x13a4): undefined reference to 
 `extcon_register_notifier'
>>drivers/built-in.o: In function `qcom_usb_hs_phy_probe':
 phy-qcom-usb-hs.c:(.text+0x1551): undefined reference to 
 `extcon_get_edev_by_phandle'
> 
> Agreed. The same fix is required:
> 
> 8<-
> From: Stephen Boyd 
> Subject: [PATCH] phy: qcom-usb-hs: Add depends on EXTCON
> 
> We get the following compile errors if EXTCON is enabled as a
> module but this driver is builtin:
> 
> drivers/built-in.o: In function `qcom_usb_hs_phy_power_off':
> phy-qcom-usb-hs.c:(.text+0x1089): undefined reference to 
> `extcon_unregister_notifier'
> drivers/built-in.o: In function `qcom_usb_hs_phy_probe':
> phy-qcom-usb-hs.c:(.text+0x11b5): undefined reference to 
> `extcon_get_edev_by_phandle'
> drivers/built-in.o: In function `qcom_usb_hs_phy_power_on':
> phy-qcom-usb-hs.c:(.text+0x128e): undefined reference to `extcon_get_state'
> phy-qcom-usb-hs.c:(.text+0x12a9): undefined reference to 
> `extcon_register_notifier'
> 
> so let's mark this as needing to follow the modular status of
> the extcon framework.
> 
> Fixes: 9994a33865f4 e2427b09ba929c2b9 (phy: Add support for Qualcomm's USB HS 
> phy")
> Signed-off-by: Stephen Boyd 

merged, thanks.

-Kishon

> ---
>  drivers/phy/Kconfig | 1 +
>  1 file changed, 1 insertion(+)
> 
> diff --git a/drivers/phy/Kconfig b/drivers/phy/Kconfig
> index 61a22e985831..0386534892c5 100644
> --- a/drivers/phy/Kconfig
> +++ b/drivers/phy/Kconfig
> @@ -440,6 +440,7 @@ config PHY_QCOM_UFS
>  config PHY_QCOM_USB_HS
>   tristate "Qualcomm USB HS PHY module"
>   depends on USB_ULPI_BUS
> + depends on EXTCON || !EXTCON # if EXTCON=m, this cannot be built-in
>   select GENERIC_PHY
>   help
> Support for the USB high-speed ULPI compliant phy on Qualcomm
> 

Re: [PATCH 1/4] s390: get rid of superfluous __GFP_REPEAT

[Heiko Carstens]

On Wed, Mar 08, 2017 at 03:11:10PM +0100, Michal Hocko wrote:
> On Wed 08-03-17 09:23:40, Heiko Carstens wrote:
> > On Tue, Mar 07, 2017 at 04:48:40PM +0100, Michal Hocko wrote:
> > > From: Michal Hocko 
> > > 
> > > __GFP_REPEAT has a rather weak semantic but since it has been introduced
> > > around 2.6.12 it has been ignored for low order allocations.
> > > 
> > > page_table_alloc then uses the flag for a single page allocation. This
> > > means that this flag has never been actually useful here because it has
> > > always been used only for PAGE_ALLOC_COSTLY requests.
> > > 
> > > An earlier attempt to remove the flag 10d58bf297e2 ("s390: get rid of
> > > superfluous __GFP_REPEAT") has missed this one but the situation is very
> > > same here.
> > > 
> > > Cc: Heiko Carstens 
> > > Signed-off-by: Michal Hocko 
> > > ---
> > >  arch/s390/mm/pgalloc.c | 2 +-
> > >  1 file changed, 1 insertion(+), 1 deletion(-)
> > 
> > FWIW:
> > Acked-by: Heiko Carstens 
> 
> Thanks
> 
> > If you want, this can be routed via the s390 tree, whatever you prefer.
> 
> Yes, that would be great. I suspect the rest will take longer to get
> merged or land to a conclusion.

Ok, applied. Thanks! :)

Re: linux-4.11-rc1/drivers/gpu/drm/exynos/exynos5433_drm_decon.c:681: suspicious mask ?

[Andrzej Hajda]

On 09.03.2017 08:34, Inki Dae wrote:
> Hello David,
>
> Thanks for report.
>
> 2017년 03월 06일 19:05에 David Binderman 이(가) 쓴 글:
>> Hello there,
>>
>> linux-4.11-rc1/drivers/gpu/drm/exynos/exynos5433_drm_decon.c:681]: (warning) 
>> Result of operator '|' is always true if one operand is non-zero. Did you 
>> intend to use '&'?
>>
> Right. this is known issue and below patch fixes this,
> http://www.spinics.net/lists/dri-devel/msg132589.html
>
> This patch will go to -fixes.
>
>> Source code is
>>
>> if (ctx->out_type | I80_HW_TRG) {
>>
>> Also in the same file:
>>
>> [drivers/gpu/drm/exynos/exynos5433_drm_decon.c:131]: (style) Same expression 
>> on both sides of '|'.
>>
>> Source code is
>>
>>writel(TRIGCON_TE_AUTO_MASK | TRIGCON_SWTRIGEN
>>| TRIGCON_TE_AUTO_MASK | TRIGCON_SWTRIGEN,
> In this case, only problem is two flags are set in duplicate. This should be 
> cleaned up. Thanks. :)

Wrong copy/paste removed two other flags and duplicated these above. It
did not hurt to much as it affects only software trigger which is not
used atm.
Fix sent yesterday [1].

[1]: http://www.spinics.net/lists/dri-devel/msg134877.html

Regards
Andrzej

>
>> Regards
>>
>> David Binderman
>>
>>
> ___
> dri-devel mailing list
> dri-de...@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/dri-devel

[PATCH] cpufreq: qoriq: enhance bus frequency calculation

[YuanTian Tang]

From: Tang Yuantian 

On some platforms, property device-type may be missed in soc node
in dts which caused the bus-frequency can not be obtained correctly.

This patch enhanced the bus-frequency calculation. When property
device-type is missed in dts, bus-frequency will be obtained by
looking up clock table to get platform clock and hence get its
frequency.

Signed-off-by: Tang Yuantian 
---
 drivers/cpufreq/qoriq-cpufreq.c | 24 +---
 1 file changed, 17 insertions(+), 7 deletions(-)

diff --git a/drivers/cpufreq/qoriq-cpufreq.c b/drivers/cpufreq/qoriq-cpufreq.c
index bfec1bc..0f22e40 100644
--- a/drivers/cpufreq/qoriq-cpufreq.c
+++ b/drivers/cpufreq/qoriq-cpufreq.c
@@ -52,17 +52,27 @@ static u32 get_bus_freq(void)
 {
struct device_node *soc;
u32 sysfreq;
+   struct clk *pltclk;
+   int ret;
 
+   /* get platform freq by searching bus-frequency property */
soc = of_find_node_by_type(NULL, "soc");
-   if (!soc)
-   return 0;
-
-   if (of_property_read_u32(soc, "bus-frequency", &sysfreq))
-   sysfreq = 0;
+   if (soc) {
+   ret = of_property_read_u32(soc, "bus-frequency", &sysfreq);
+   of_node_put(soc);
+   if (!ret)
+   return sysfreq;
+   }
 
-   of_node_put(soc);
+   /* get platform freq by its clock name */
+   pltclk = clk_get(NULL, "cg-pll0-div1");
+   if (IS_ERR(pltclk)) {
+   pr_err("%s: can't get bus frequency %ld\n",
+   __func__, PTR_ERR(pltclk));
+   return PTR_ERR(pltclk);
+   }
 
-   return sysfreq;
+   return clk_get_rate(pltclk);
 }
 
 static struct clk *cpu_to_clk(int cpu)
-- 
2.1.0.27.g96db324

[PATCH] selftests: firmware/config: add FW_LOADER_USER_HELPER_FALLBACK

[Li Zhijian]

fw_fallback.sh requires FW_LOADER_USER_HELPER_FALLBACK

Signed-off-by: Li Zhijian 
---
 tools/testing/selftests/firmware/config | 1 +
 1 file changed, 1 insertion(+)

diff --git a/tools/testing/selftests/firmware/config 
b/tools/testing/selftests/firmware/config
index c8137f7..965ed11 100644
--- a/tools/testing/selftests/firmware/config
+++ b/tools/testing/selftests/firmware/config
@@ -1 +1,2 @@
 CONFIG_TEST_FIRMWARE=y
+FW_LOADER_USER_HELPER_FALLBACK=y
-- 
2.7.4

Re: [PATCH] edac i5000, i5400: fix use of MTR_DRAM_WIDTH macro

[Borislav Petkov]

On Wed, Mar 08, 2017 at 08:18:09PM -0500, Jérémy Lefaure wrote:
> The MTR_DRAM_WIDTH macro returns the data width. It is sometimes used as
> if it returned a boolean true if the width if 8. This patch fixes the
> tests where MTR_DRAM_WIDTH is misused.
> 
> Signed-off-by: Jérémy Lefaure 
> ---
>  drivers/edac/i5000_edac.c | 2 +-
>  drivers/edac/i5400_edac.c | 5 +++--
>  2 files changed, 4 insertions(+), 3 deletions(-)

Applied, thanks.

-- 
Regards/Gruss,
Boris.

Good mailing practices for 400: avoid top-posting and trim the reply.

Re: [RESEND PATCH] arm: assabet_defconfig: disable IDE subsystem

[Sekhar Nori]

Hi Bartlomiej,

On Wednesday 08 March 2017 08:30 PM, Sekhar Nori wrote:

>> It took a while to get to it but here is the draft driver patch
>> against v4.11-rc1.  Please test.
> 
> I tested this on DM6446 EVM. I was able to mount existing partitions on 
> the hard disk and see that the directory listing looks good[1]. I will do 
> more tests (including comparing performance with old driver) tomorrow. I 

I completed the tests I wanted to, including some read/write/data 
integrity tests. Performance is same as before too.

Tested-by: Sekhar Nori 

Here are the additional changes I did. These changes do not clash with 
what I have already queued for v4.12. That said, its probably better if 
I carry the platform pieces through my tree. Let me know how you want 
to proceed.

Thanks,
Sekhar

---8<---
diff --git a/arch/arm/configs/davinci_all_defconfig 
b/arch/arm/configs/davinci_all_defconfig
index b9a7cb98ffda..67db82999c06 100644
--- a/arch/arm/configs/davinci_all_defconfig
+++ b/arch/arm/configs/davinci_all_defconfig
@@ -74,12 +74,10 @@ CONFIG_BLK_DEV_RAM=y
 CONFIG_BLK_DEV_RAM_COUNT=1
 CONFIG_BLK_DEV_RAM_SIZE=32768
 CONFIG_EEPROM_AT24=y
-CONFIG_IDE=m
-CONFIG_BLK_DEV_PALMCHIP_BK3710=m
-CONFIG_SCSI=m
 CONFIG_BLK_DEV_SD=m
 CONFIG_ATA=m
 CONFIG_AHCI_DA850=m
+CONFIG_PATA_BK3710=m
 CONFIG_NETDEVICES=y
 CONFIG_NETCONSOLE=y
 CONFIG_TUN=m
diff --git a/arch/arm/mach-davinci/board-dm644x-evm.c 
b/arch/arm/mach-davinci/board-dm644x-evm.c
index 023480b75244..60a1f23890cd 100644
--- a/arch/arm/mach-davinci/board-dm644x-evm.c
+++ b/arch/arm/mach-davinci/board-dm644x-evm.c
@@ -744,7 +744,7 @@ static int davinci_phy_fixup(struct phy_device *phydev)
return 0;
 }
 
-#define HAS_ATAIS_ENABLED(CONFIG_BLK_DEV_PALMCHIP_BK3710)
+#define HAS_ATAIS_ENABLED(CONFIG_PATA_BK3710)
 
 #define HAS_NORIS_ENABLED(CONFIG_MTD_PHYSMAP)
 
diff --git a/arch/arm/mach-davinci/board-dm646x-evm.c 
b/arch/arm/mach-davinci/board-dm646x-evm.c
index f702d4fc8eb8..589f3c33c4a0 100644
--- a/arch/arm/mach-davinci/board-dm646x-evm.c
+++ b/arch/arm/mach-davinci/board-dm646x-evm.c
@@ -119,7 +119,7 @@ static struct platform_device davinci_nand_device = {
},
 };
 
-#define HAS_ATAIS_ENABLED(CONFIG_BLK_DEV_PALMCHIP_BK3710)
+#define HAS_ATAIS_ENABLED(CONFIG_PATA_BK3710)
 
 #ifdef CONFIG_I2C
 /* CPLD Register 0 bits to control ATA */
diff --git a/arch/arm/mach-davinci/board-neuros-osd2.c 
b/arch/arm/mach-davinci/board-neuros-osd2.c
index 0a7838852649..075e304ce7be 100644
--- a/arch/arm/mach-davinci/board-neuros-osd2.c
+++ b/arch/arm/mach-davinci/board-neuros-osd2.c
@@ -163,7 +163,7 @@ static struct davinci_mmc_config davinci_ntosd2_mmc_config 
= {
.wires  = 4,
 };
 
-#define HAS_ATAIS_ENABLED(CONFIG_BLK_DEV_PALMCHIP_BK3710)
+#define HAS_ATAIS_ENABLED(CONFIG_PATA_BK3710)
 
 #define HAS_NAND   IS_ENABLED(CONFIG_MTD_NAND_DAVINCI)
 

Re: [PATCH 1/1] HID: clamp input to logical range if no null state

[Benjamin Tissoires]

On Mar 08 2017 or thereabouts, Tomasz Kramkowski wrote:
> This patch fixes an issue in drivers/hid/hid-input.c where values
> outside of the logical range are not clamped when "null state" bit of
> the input control is not set.
> 
> This was discussed on the lists [1] and this change stems from the fact
> due to the ambiguity of the HID specification it might be appropriate to
> follow Microsoft's own interpretation of the specification. As noted in
> Microsoft's documentation [2] in the section titled "Required HID usages
> for digitizers" it is noted that values reported outside the logical
> range "will be considered as invalid data and the value will be changed
> to the nearest boundary value (logical min/max)."
> 
> This patch fixes an issue where the (1292:4745) Innomedia INNEX
> GENESIS/ATARI reports out of range values for its X and Y axis of the
> DPad which, due to the null state bit being unset, are forwarded to
> userspace as is. Now these values will get clamped to the logical range
> before being forwarded to userspace. This device was also used to test
> this patch.
> 
> This patch expands on commit 3f3752705dbd ("HID: reject input outside
> logical range only if null state is set").
> 
> [1]: http://lkml.kernel.org/r/20170307131036.GA853@gaia.local
> [2]: 
> https://msdn.microsoft.com/en-us/library/windows/hardware/dn672278(v=vs.85).asp
> 
> Signed-off-by: Tomasz Kramkowski 
> ---
>  drivers/hid/hid-input.c | 9 ++---
>  1 file changed, 6 insertions(+), 3 deletions(-)
> 
> diff --git a/drivers/hid/hid-input.c b/drivers/hid/hid-input.c
> index cf8256aac2bd..cf38ff79cfe9 100644
> --- a/drivers/hid/hid-input.c
> +++ b/drivers/hid/hid-input.c
> @@ -1157,12 +1157,15 @@ void hidinput_hid_event(struct hid_device *hid, 
> struct hid_field *field, struct
>* don't specify logical min and max.
>*/
>   if ((field->flags & HID_MAIN_ITEM_VARIABLE) &&
> - (field->flags & HID_MAIN_ITEM_NULL_STATE) &&
>   (field->logical_minimum < field->logical_maximum) &&
>   (value < field->logical_minimum ||
>value > field->logical_maximum)) {
> - dbg_hid("Ignoring out-of-range value %x\n", value);
> - return;
> + if (field->flags & HID_MAIN_ITEM_NULL_STATE) {
> + dbg_hid("Ignoring out-of-range value %x\n", value);
> + return;
> + }
> + value = value < field->logical_minimum ?
> + field->logical_minimum : field->logical_maximum;

We have a "clamp()" function in the kernel that does the job directly
and which is more readable. Also, this makes testing the out of range
values twice.

How about:

diff --git a/drivers/hid/hid-input.c b/drivers/hid/hid-input.c
index cf8256a..781f400 100644
--- a/drivers/hid/hid-input.c
+++ b/drivers/hid/hid-input.c
@@ -1150,19 +1150,26 @@ void hidinput_hid_event(struct hid_device *hid, struct 
hid_field *field, struct
 
/*
 * Ignore out-of-range values as per HID specification,
-* section 5.10 and 6.2.25.
+* section 5.10 and 6.2.25, when NULL state bit is present.
+* When it's not, clamp the value to match Microsoft's input
+* driver as mentioned in "Required HID usages for digitizers":
+* 
https://msdn.microsoft.com/en-us/library/windows/hardware/dn672278(v=vs.85).asp
 *
 * The logical_minimum < logical_maximum check is done so that we
 * don't unintentionally discard values sent by devices which
 * don't specify logical min and max.
 */
if ((field->flags & HID_MAIN_ITEM_VARIABLE) &&
-   (field->flags & HID_MAIN_ITEM_NULL_STATE) &&
-   (field->logical_minimum < field->logical_maximum) &&
-   (value < field->logical_minimum ||
-value > field->logical_maximum)) {
-   dbg_hid("Ignoring out-of-range value %x\n", value);
-   return;
+   (field->logical_minimum < field->logical_maximum)) {
+   if (!(field->flags & HID_MAIN_ITEM_NULL_STATE)) {
+   value = clamp(value,
+ field->logical_minimum,
+ field->logical_maximum);
+   } else if (value < field->logical_minimum ||
+  value > field->logical_maximum) {
+   dbg_hid("Ignoring out-of-range value %x\n", value);
+   return;
+   }
}
 
/*
---

Cheers,
Benjamin

>   }
>  
>   /*
> -- 
> 2.12.0
> 

Re: [RESEND PATCH v3 4/8] phy: phy-mt65xx-usb3: move clock from phy node into port nodes

[Chunfeng Yun]

On Thu, 2017-03-09 at 13:51 +0530, Kishon Vijay Abraham I wrote:
> Hi,
> 
> On Monday 06 March 2017 07:19 PM, Chunfeng Yun wrote:
> > the reference clock of HighSpeed port is 48M which comes from PLL;
> > the reference clock of SuperSpeed port is 26M which usually comes
> > from 26M oscillator directly, but some SoCs are not, add it for
> > compatibility, and put them into port node for flexibility.
> 
> Won't this break the old dt compatiblity? Making change in dt is fine as long
> as older dtb's are still supported.
Ok, I'll keep it compatible in next version

Thanks a lot
> 
> Thanks
> Kishon
> > 
> > Signed-off-by: Chunfeng Yun 
> > ---
> >  drivers/phy/phy-mt65xx-usb3.c |   21 +++--
> >  1 file changed, 11 insertions(+), 10 deletions(-)
> > 
> > diff --git a/drivers/phy/phy-mt65xx-usb3.c b/drivers/phy/phy-mt65xx-usb3.c
> > index 7fff482..f4a3505 100644
> > --- a/drivers/phy/phy-mt65xx-usb3.c
> > +++ b/drivers/phy/phy-mt65xx-usb3.c
> > @@ -153,6 +153,7 @@ struct mt65xx_phy_pdata {
> >  struct mt65xx_phy_instance {
> > struct phy *phy;
> > void __iomem *port_base;
> > +   struct clk *ref_clk;/* reference clock of anolog phy */
> > u32 index;
> > u8 type;
> >  };
> > @@ -160,7 +161,6 @@ struct mt65xx_phy_instance {
> >  struct mt65xx_u3phy {
> > struct device *dev;
> > void __iomem *sif_base; /* only shared sif */
> > -   struct clk *u3phya_ref; /* reference clock of usb3 anolog phy */
> > const struct mt65xx_phy_pdata *pdata;
> > struct mt65xx_phy_instance **phys;
> > int nphys;
> > @@ -449,9 +449,9 @@ static int mt65xx_phy_init(struct phy *phy)
> > struct mt65xx_u3phy *u3phy = dev_get_drvdata(phy->dev.parent);
> > int ret;
> >  
> > -   ret = clk_prepare_enable(u3phy->u3phya_ref);
> > +   ret = clk_prepare_enable(instance->ref_clk);
> > if (ret) {
> > -   dev_err(u3phy->dev, "failed to enable u3phya_ref\n");
> > +   dev_err(u3phy->dev, "failed to enable ref_clk\n");
> > return ret;
> > }
> >  
> > @@ -494,7 +494,7 @@ static int mt65xx_phy_exit(struct phy *phy)
> > if (instance->type == PHY_TYPE_USB2)
> > phy_instance_exit(u3phy, instance);
> >  
> > -   clk_disable_unprepare(u3phy->u3phya_ref);
> > +   clk_disable_unprepare(instance->ref_clk);
> > return 0;
> >  }
> >  
> > @@ -594,12 +594,6 @@ static int mt65xx_u3phy_probe(struct platform_device 
> > *pdev)
> > return PTR_ERR(u3phy->sif_base);
> > }
> >  
> > -   u3phy->u3phya_ref = devm_clk_get(dev, "u3phya_ref");
> > -   if (IS_ERR(u3phy->u3phya_ref)) {
> > -   dev_err(dev, "error to get u3phya_ref\n");
> > -   return PTR_ERR(u3phy->u3phya_ref);
> > -   }
> > -
> > port = 0;
> > for_each_child_of_node(np, child_np) {
> > struct mt65xx_phy_instance *instance;
> > @@ -634,6 +628,13 @@ static int mt65xx_u3phy_probe(struct platform_device 
> > *pdev)
> > goto put_child;
> > }
> >  
> > +   instance->ref_clk = devm_clk_get(&phy->dev, "ref");
> > +   if (IS_ERR(instance->ref_clk)) {
> > +   dev_err(dev, "failed to get ref_clk(id-%d)\n", port);
> > +   retval = PTR_ERR(instance->ref_clk);
> > +   goto put_child;
> > +   }
> > +
> > instance->phy = phy;
> > instance->index = port;
> > phy_set_drvdata(phy, instance);
> > 

Re: [PATCH v2 6/9] arm, arm64: factorize common cpu capacity default code

[Juri Lelli]

Hi Greg,

did you have a chance to have a look at my replies below?

It would be really helpful to understand from you how to move forward
with this set.

Best Regards,

- Juri

On 13/02/17 15:09, Juri Lelli wrote:
> Hi Greg,
> 
> On 10/02/17 15:28, Greg KH wrote:
> > On Thu, Feb 09, 2017 at 09:25:22AM +, Juri Lelli wrote:
> > > arm and arm64 share lot of code relative to parsing CPU capacity
> > > information from DT, using that information for appropriate scaling and
> > > exposing a sysfs interface for chaging such values at runtime.
> > > 
> > > Factorize such code in a common place (driver/base/arch_topology.c) in
> > > preparation for further additions.
> > > 
> > > Suggested-by: Will Deacon 
> > > Suggested-by: Mark Rutland 
> > > Suggested-by: Catalin Marinas 
> > > Cc: Russell King 
> > > Cc: Catalin Marinas 
> > > Cc: Will Deacon 
> > > Cc: Greg Kroah-Hartman 
> > > Signed-off-by: Juri Lelli 
> > > ---
> > > 
> > > Changes from v1:
> > >  - keep the original GPLv2 header
> > > ---
> > >  arch/arm/Kconfig |   1 +
> > >  arch/arm/kernel/topology.c   | 213 ++
> > >  arch/arm64/Kconfig   |   1 +
> > >  arch/arm64/kernel/topology.c | 219 
> > > +--
> > >  drivers/base/Kconfig |   8 ++
> > >  drivers/base/Makefile|   1 +
> > >  drivers/base/arch_topology.c | 237 
> > > +++
> > >  7 files changed, 257 insertions(+), 423 deletions(-)
> > >  create mode 100644 drivers/base/arch_topology.c
> > 
> > Ah, so you want _me_ to maintain this, ok, I better review it...
> > 
> 
> This has been suggested as a possible way to stop replicating code between arm
> and arm64 (and possibly other archs in the future). Are you in principle OK
> with it?
> 
> Thanks a lot for your comments, please find my answers below.
> 
> > > --- a/drivers/base/Kconfig
> > > +++ b/drivers/base/Kconfig
> > > @@ -339,4 +339,12 @@ config CMA_ALIGNMENT
> > >  
> > >  endif
> > >  
> > > +config GENERIC_ARCH_TOPOLOGY
> > > + bool
> > > + help
> > > +   Enable support for architectures common topology code: e.g., parsing
> > > +   CPU capacity information from DT, usage of such information for
> > > +   appropriate scaling, sysfs interface for changing capacity values at
> > > +  runtime.
> > 
> > Mix of spaces and tabs :(
> > 
> 
> Argh. :(
> 
> > > +
> > >  endmenu
> > > diff --git a/drivers/base/Makefile b/drivers/base/Makefile
> > > index f2816f6ff76a..397e5c344e6a 100644
> > > --- a/drivers/base/Makefile
> > > +++ b/drivers/base/Makefile
> > > @@ -23,6 +23,7 @@ obj-$(CONFIG_SOC_BUS) += soc.o
> > >  obj-$(CONFIG_PINCTRL) += pinctrl.o
> > >  obj-$(CONFIG_DEV_COREDUMP) += devcoredump.o
> > >  obj-$(CONFIG_GENERIC_MSI_IRQ_DOMAIN) += platform-msi.o
> > > +obj-$(CONFIG_GENERIC_ARCH_TOPOLOGY) += arch_topology.o
> > >  
> > >  obj-y+= test/
> > >  
> > > diff --git a/drivers/base/arch_topology.c b/drivers/base/arch_topology.c
> > > new file mode 100644
> > > index ..c1dd430adad2
> > > --- /dev/null
> > > +++ b/drivers/base/arch_topology.c
> > > @@ -0,0 +1,237 @@
> > > +/*
> > > + * driver/base/arch_topology.c - Arch specific cpu topology information
> > 
> > No need to keep the filename in the file, you know what it is called :)
> > 
> 
> OK, removed.
> 
> > > + *
> > > + * Copyright (C) 2016, ARM Ltd.
> > > + * Written by: Juri Lelli, ARM Ltd.
> > > + *
> > > + * This file is subject to the terms and conditions of the GNU General 
> > > Public
> > > + * License.  See the file "COPYING" in the main directory of this archive
> > > + * for more details.
> > 
> > So, v2 only?  Please be specific.  Even better yet, use a SPDX header if
> > you want to, those are always nice.
> > 
> 
> Yes, v2 only.
> 
>   * for more details. 
>   
>  
> + *   
>   
>  
> + * Released under the GPLv2 only.
>   
>  
> + * SPDX-License-Identifier: GPL-2.0 
> 
> Would do, right?
> 
> > > + */
> > > +
> > > +#include 
> > > +#include 
> > > +#include 
> > > +#include 
> > > +#include 
> > > +#include 
> > > +#include 
> > > +#include 
> > > +
> > > +static DEFINE_MUTEX(cpu_scale_mutex);
> > > +static DEFINE_PER_CPU(unsigned long, cpu_scale) = SCHED_CAPACITY_SCALE;
> > > +
> > > +unsigned long arch_scale_cpu_capacity(struct sched_domain *sd, int cpu)
> > 
> > Why do yo

Re: [sched] 1827adb11a BUG kmalloc-128 (Not tainted): Poison overwritten

[Dmitry Vyukov]

On Thu, Mar 9, 2017 at 4:01 AM, Fengguang Wu  wrote:
> Hi Ingo,
>
> FYI this also shows up in next-20170308 and tip/master 7f27de49
> ("Merge branch 'WIP.sched/core'"). The attached reproduce-* script may
> help, however note that this bug may not show up in every boot.


This is not KASAN-detected bug, this is slub debug or something.
The crash looks like the issue that I fixed here few days ago:
https://groups.google.com/d/msg/syzkaller/dpZ6ou1WOiI/7zfgSe1QEAAJ



> https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git master
>
> commit 1827adb11ad26b2290dc9fe2aaf54976b2439865
> Merge: 7876991 5eca1c1
> Author: Linus Torvalds 
> AuthorDate: Fri Mar 3 10:16:38 2017 -0800
> Commit: Linus Torvalds 
> CommitDate: Fri Mar 3 10:16:38 2017 -0800
>
>  Merge branch 'WIP.sched-core-for-linus' of 
> git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip
>
>  Pull sched.h split-up from Ingo Molnar:
>   "The point of these changes is to significantly reduce the
> header footprint, to speed up the kernel build and to
>have a cleaner header structure.
>
>After these changes the new 's typical preprocessed
>size goes down from a previous ~0.68 MB (~22K lines) to ~0.45 MB (~15K
>lines), which is around 40% faster to build on typical configs.
>
>Not much changed from the last version (-v2) posted three weeks ago: I
>eliminated quirks, backmerged fixes plus I rebased it to an upstream
>SHA1 from yesterday that includes most changes queued up in -next plus
>all sched.h changes that were pending from Andrew.
>
>I've re-tested the series both on x86 and on cross-arch defconfigs,
>and did a bisectability test at a number of random points.
>
>I tried to test as many build configurations as possible, but some
>build breakage is probably still left - but it should be mostly
>limited to architectures that have no cross-compiler binaries
>available on kernel.org, and non-default configurations"
>
>  * 'WIP.sched-core-for-linus' of 
> git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip: (146 commits)
>sched/headers: Clean up 
>sched/headers: Remove #ifdefs from 
>sched/headers: Remove the  include from 
> 
>sched/headers, hrtimer: Remove the  include from 
> 
>sched/headers, x86/apic: Remove the  header inclusion from 
> 
>sched/headers, timers: Remove the  include from 
> 
>sched/headers: Remove  from 
>sched/headers: Remove  from 
>sched/core: Remove unused prefetch_stack()
>sched/headers: Remove  from 
>sched/headers: Remove the 'init_pid_ns' prototype from 
>sched/headers: Remove  from 
>sched/headers: Remove  from 
>sched/headers: Remove the runqueue_is_locked() prototype
>sched/headers: Remove  from 
>sched/headers: Remove  from 
>sched/headers: Remove  from 
>sched/headers: Remove  from 
>sched/headers: Remove the  include from 
>sched/headers: Remove  from 
>...
>
> 78769912f6  Merge tag 'linux-kselftest-4.11-rc1-urgent_fix' of 
> git://git.kernel.org/pub/scm/linux/kernel/git/shuah/linux-kselftest
> 5eca1c10cb  sched/headers: Clean up 
> 1827adb11a  Merge branch 'WIP.sched-core-for-linus' of 
> git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip
> +---++++
> |   | 78769912f6 | 5eca1c10cb | 
> 1827adb11a |
> +---++++
> | boot_successes| 69 | 32 | 
> 166|
> | boot_failures | 0  | 0  | 2 
>  |
> | BUG_kmalloc-#(Not_tainted):Poison_overwritten | 0  | 0  | 2 
>  |
> | INFO:#-#.First_byte#instead_of| 0  | 0  | 2 
>  |
> | INFO:Allocated_in_ida_pre_get_age=#cpu=#pid=  | 0  | 0  | 2 
>  |
> | INFO:Freed_in_ida_pre_get_age=#cpu=#pid=  | 0  | 0  | 2 
>  |
> | INFO:Slab#objects=#used=#fp=0x(null)flags=| 0  | 0  | 2 
>  |
> | INFO:Object#@offset=#fp=  | 0  | 0  | 2 
>  |
> +---++++
>
> [2.792346]  done.
> [2.793824] Using IPI No-Shortcut mode
> [2.806241] Key type trusted registered
> [2.807779] ima: No TPM chip found, activating TPM-bypass! (rc=-19)
> [2.810445] 
> =
> [2.813344] BUG kmalloc-128 (Not tainted): Poison overwritten
> [2.813344] 
> 

Re: [PATCH 22/29] drivers, scsi: convert iscsi_task.refcount from atomic_t to refcount_t

[Johannes Thumshirn]

On 03/09/2017 08:18 AM, Reshetova, Elena wrote:
>> On Mon, Mar 06, 2017 at 04:21:09PM +0200, Elena Reshetova wrote:
>>> refcount_t type and corresponding API should be
>>> used instead of atomic_t when the variable is used as
>>> a reference counter. This allows to avoid accidental
>>> refcounter overflows that might lead to use-after-free
>>> situations.
>>>
>>> Signed-off-by: Elena Reshetova 
>>> Signed-off-by: Hans Liljestrand 
>>> Signed-off-by: Kees Cook 
>>> Signed-off-by: David Windsor 
>>
>> This looks OK to me.
>>
>> Acked-by: Chris Leech 
> 
> Thank you for review! Do you have a tree that can take this change? 

Hi Elena,

iscsi like fcoe should go via the SCSI tree.

Byte,
Johannes

-- 
Johannes Thumshirn  Storage
jthumsh...@suse.de+49 911 74053 689
SUSE LINUX GmbH, Maxfeldstr. 5, 90409 Nürnberg
GF: Felix Imendörffer, Jane Smithard, Graham Norton
HRB 21284 (AG Nürnberg)
Key fingerprint = EC38 9CAB C2C4 F25D 8600 D0D0 0393 969D 2D76 0850

RE: [PATCH 1/2] dt-bindings: qoriq-clock: Add coreclk

[Y.T. Tang]

Hi Michael and Stephen,

This patch set was acked by Rob Herring. Do you have any comments on them?

BTW:  Scott should stay in author, do I need to resend them with author changed 
or you can change it when applying?

Regards,
Yuantian

> -Original Message-
> From: Rob Herring [mailto:r...@kernel.org]
> Sent: Tuesday, February 28, 2017 1:19 AM
> To: Y.T. Tang
> Cc: mturque...@baylibre.com; sb...@codeaurora.org;
> mark.rutl...@arm.com; linux-...@vger.kernel.org;
> devicet...@vger.kernel.org; linux-kernel@vger.kernel.org; linux-arm-
> ker...@lists.infradead.org; Scott Wood
> Subject: Re: [PATCH 1/2] dt-bindings: qoriq-clock: Add coreclk
> 
> On Wed, Feb 15, 2017 at 01:47:35PM +0800, yuantian.t...@nxp.com wrote:
> > From: Tang Yuantian 
> >
> > ls1012a has separate input root clocks for core PLLs versus the
> > platform PLL, with the latter described as sysclk in the hw docs.
> > Update the qoriq-clock binding to allow a second input clock, named
> > "coreclk".  If present, this clock will be used for the core PLLs.
> >
> > Signed-off-by: Scott Wood 
> > Signed-off-by: Tang Yuantian 
> > ---
> >  Documentation/devicetree/bindings/clock/qoriq-clock.txt | 6 ++
> >  1 file changed, 6 insertions(+)
> 
> The change looks fine, but sounds like Scott should remain the author (or
> agree he shouldn't be).
> 
> >
> > diff --git a/Documentation/devicetree/bindings/clock/qoriq-clock.txt
> > b/Documentation/devicetree/bindings/clock/qoriq-clock.txt
> > index df9cb5a..97a9666 100644
> > --- a/Documentation/devicetree/bindings/clock/qoriq-clock.txt
> > +++ b/Documentation/devicetree/bindings/clock/qoriq-clock.txt
> > @@ -55,6 +55,11 @@ Optional properties:
> >  - clocks: If clock-frequency is not specified, sysclk may be provided
> > as an input clock.  Either clock-frequency or clocks must be
> > provided.
> > +   A second input clock, called "coreclk", may be provided if
> > +   core PLLs are based on a different input clock from the
> > +   platform PLL.
> > +- clock-names: Required if a coreclk is present.  Valid names are
> > +   "sysclk" and "coreclk".
> >
> >  2. Clock Provider
> >
> > @@ -71,6 +76,7 @@ second cell is the clock index for the specified type.
> > 2   hwaccel index (n in CLKCGnHWACSR)
> > 3   fman0 for fm1, 1 for fm2
> > 4   platform pll0=pll, 1=pll/2, 2=pll/3, 3=pll/4
> > +   5   coreclk must be 0
> >
> >  3. Example
> >
> > --
> > 2.1.0.27.g96db324
> >

[PATCH] usb: xhci: bInterval quirk for TI TUSB73x0

[Roger Quadros]

As per [1] issue #4,
"The periodic EP scheduler always tries to schedule the EPs
that have large intervals (interval equal to or greater than
128 microframes) into different microframes. So it maintains
an internal counter and increments for each large interval
EP added. When the counter is greater than 128, the scheduler
rejects the new EP. So when the hub re-enumerated 128 times,
it trigged this condition."

This results in Bandwidth error when devices with periodic
endpoints (ISO/INT) having bInterval > 7 are plugged an
unplugged several times on a TUSB73x0 xhci host.

Workaround this issue by limiting the bInterval to 7
(i.e. interval to 6) for High-speed or faster periodic endpoints.

[1] - http://www.ti.com/lit/er/sllz076/sllz076.pdf

Signed-off-by: Roger Quadros 
---
 drivers/usb/host/xhci-mem.c | 11 +++
 drivers/usb/host/xhci-pci.c |  3 +++
 drivers/usb/host/xhci.h |  1 +
 3 files changed, 15 insertions(+)

diff --git a/drivers/usb/host/xhci-mem.c b/drivers/usb/host/xhci-mem.c
index ba1853f4..05fb3f6 100644
--- a/drivers/usb/host/xhci-mem.c
+++ b/drivers/usb/host/xhci-mem.c
@@ -1502,6 +1502,17 @@ int xhci_endpoint_init(struct xhci_hcd *xhci,
 */
max_esit_payload = xhci_get_max_esit_payload(udev, ep);
interval = xhci_get_endpoint_interval(udev, ep);
+
+   /* Periodic endpoint bInterval limit quirk */
+   if (usb_endpoint_xfer_int(&ep->desc) ||
+   usb_endpoint_xfer_isoc(&ep->desc)) {
+   if ((xhci->quirks & XHCI_LIMIT_ENDPOINT_INTERVAL_7) &&
+   udev->speed >= USB_SPEED_HIGH &&
+   interval >= 7) {
+   interval = 6;
+   }
+   }
+
mult = xhci_get_endpoint_mult(udev, ep);
max_packet = usb_endpoint_maxp(&ep->desc);
max_burst = xhci_get_endpoint_max_burst(udev, ep);
diff --git a/drivers/usb/host/xhci-pci.c b/drivers/usb/host/xhci-pci.c
index fc99f51..7b86508 100644
--- a/drivers/usb/host/xhci-pci.c
+++ b/drivers/usb/host/xhci-pci.c
@@ -199,6 +199,9 @@ static void xhci_pci_quirks(struct device *dev, struct 
xhci_hcd *xhci)
pdev->device == 0x1042)
xhci->quirks |= XHCI_BROKEN_STREAMS;
 
+   if (pdev->vendor == PCI_VENDOR_ID_TI && pdev->device == 0x8241)
+   xhci->quirks |= XHCI_LIMIT_ENDPOINT_INTERVAL_7;
+
if (xhci->quirks & XHCI_RESET_ON_RESUME)
xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
"QUIRK: Resetting on resume");
diff --git a/drivers/usb/host/xhci.h b/drivers/usb/host/xhci.h
index da3eb69..2496bd6 100644
--- a/drivers/usb/host/xhci.h
+++ b/drivers/usb/host/xhci.h
@@ -1818,6 +1818,7 @@ struct xhci_hcd {
 #define XHCI_MISSING_CAS   (1 << 24)
 /* For controller with a broken Port Disable implementation */
 #define XHCI_BROKEN_PORT_PED   (1 << 25)
+#define XHCI_LIMIT_ENDPOINT_INTERVAL_7 (1 << 26)
 
unsigned intnum_active_eps;
unsigned intlimit_active_eps;
-- 
2.7.4

[PATCH v1 4/4] mfd: rk808: Add RK805 support

[Elaine Zhang]

The RK805 chip is a Power Management IC (PMIC) for multimedia and handheld
devices. It contains the following components:

- Regulators
- RTC
- Clocking

Both RK808 and RK805 chips are using a similar register map,
so we can reuse the RTC and Clocking functionality.

Signed-off-by: Elaine Zhang 
---
 drivers/clk/Kconfig |   4 +-
 drivers/mfd/Kconfig |   4 +-
 drivers/mfd/rk808.c | 109 
 drivers/rtc/Kconfig |   4 +-
 4 files changed, 115 insertions(+), 6 deletions(-)

diff --git a/drivers/clk/Kconfig b/drivers/clk/Kconfig
index 9356ab4b7d76..7ca8f02a1232 100644
--- a/drivers/clk/Kconfig
+++ b/drivers/clk/Kconfig
@@ -39,10 +39,10 @@ config COMMON_CLK_MAX77686
  clock.
 
 config COMMON_CLK_RK808
-   tristate "Clock driver for RK808/RK818"
+   tristate "Clock driver for RK805/RK808/RK818"
depends on MFD_RK808
---help---
- This driver supports RK808 and RK818 crystal oscillator clock. These
+ This driver supports RK805, RK808 and RK818 crystal oscillator clock. 
These
  multi-function devices have two fixed-rate oscillators,
  clocked at 32KHz each. Clkout1 is always on, Clkout2 can off
  by control register.
diff --git a/drivers/mfd/Kconfig b/drivers/mfd/Kconfig
index 55ecdfb74d31..b410a348b756 100644
--- a/drivers/mfd/Kconfig
+++ b/drivers/mfd/Kconfig
@@ -892,13 +892,13 @@ config MFD_RC5T583
  different functionality of the device.
 
 config MFD_RK808
-   tristate "Rockchip RK808/RK818 Power Management Chip"
+   tristate "Rockchip RK805/RK808/RK818 Power Management Chip"
depends on I2C && OF
select MFD_CORE
select REGMAP_I2C
select REGMAP_IRQ
help
- If you say yes here you get support for the RK808 and RK818
+ If you say yes here you get support for the RK805, RK808 and RK818
  Power Management chips.
  This driver provides common support for accessing the device
  through I2C interface. The device supports multiple sub-devices
diff --git a/drivers/mfd/rk808.c b/drivers/mfd/rk808.c
index 3334a2a7f3fb..97fd4c0a811d 100644
--- a/drivers/mfd/rk808.c
+++ b/drivers/mfd/rk808.c
@@ -70,6 +70,14 @@ static bool rk808_is_volatile_reg(struct device *dev, 
unsigned int reg)
.volatile_reg = rk808_is_volatile_reg,
 };
 
+static const struct regmap_config rk805_regmap_config = {
+   .reg_bits = 8,
+   .val_bits = 8,
+   .max_register = RK805_OFF_SOURCE_REG,
+   .cache_type = REGCACHE_RBTREE,
+   .volatile_reg = rk808_is_volatile_reg,
+};
+
 static const struct regmap_config rk808_regmap_config = {
.reg_bits = 8,
.val_bits = 8,
@@ -86,6 +94,16 @@ static bool rk808_is_volatile_reg(struct device *dev, 
unsigned int reg)
}
 };
 
+static const struct mfd_cell rk805s[] = {
+   { .name = "rk808-clkout", },
+   { .name = "rk808-regulator", },
+   {
+   .name = "rk808-rtc",
+   .num_resources = ARRAY_SIZE(rtc_resources),
+   .resources = &rtc_resources[0],
+   },
+};
+
 static const struct mfd_cell rk808s[] = {
{ .name = "rk808-clkout", },
{ .name = "rk808-regulator", },
@@ -106,6 +124,12 @@ static bool rk808_is_volatile_reg(struct device *dev, 
unsigned int reg)
},
 };
 
+static const struct rk808_reg_data rk805_pre_init_reg[] = {
+   {RK805_BUCK4_CONFIG_REG, BUCK_ILMIN_MASK, BUCK_ILMIN_400MA},
+   {RK805_GPIO_IO_POL_REG, SLP_SD_MSK, SLEEP_FUN},
+   {RK805_THERMAL_REG, TEMP_HOTDIE_MSK, TEMP115C},
+};
+
 static const struct rk808_reg_data rk808_pre_init_reg[] = {
{ RK808_BUCK3_CONFIG_REG, BUCK_ILMIN_MASK,  BUCK_ILMIN_150MA },
{ RK808_BUCK4_CONFIG_REG, BUCK_ILMIN_MASK,  BUCK_ILMIN_200MA },
@@ -135,6 +159,41 @@ static bool rk808_is_volatile_reg(struct device *dev, 
unsigned int reg)
VB_LO_SEL_3500MV },
 };
 
+static const struct regmap_irq rk805_irqs[] = {
+   [RK805_IRQ_PWRON_RISE] = {
+   .mask = RK805_IRQ_PWRON_RISE_MSK,
+   .reg_offset = 0,
+   },
+   [RK805_IRQ_VB_LOW] = {
+   .mask = RK805_IRQ_VB_LOW_MSK,
+   .reg_offset = 0,
+   },
+   [RK805_IRQ_PWRON] = {
+   .mask = RK805_IRQ_PWRON_MSK,
+   .reg_offset = 0,
+   },
+   [RK805_IRQ_PWRON_LP] = {
+   .mask = RK805_IRQ_PWRON_LP_MSK,
+   .reg_offset = 0,
+   },
+   [RK805_IRQ_HOTDIE] = {
+   .mask = RK805_IRQ_HOTDIE_MSK,
+   .reg_offset = 0,
+   },
+   [RK805_IRQ_RTC_ALARM] = {
+   .mask = RK805_IRQ_RTC_ALARM_MSK,
+   .reg_offset = 0,
+   },
+   [RK805_IRQ_RTC_PERIOD] = {
+   .mask = RK805_IRQ_RTC_PERIOD_MSK,
+   .reg_offset = 0,
+   },
+   [RK805_IRQ_PWRON_FALL] = {
+   .mask = RK805_IRQ_PWRON_FALL_MSK,
+

[PATCH v1 3/4] regulator: rk808: Add regulator driver for RK805

[Elaine Zhang]

Add support for the rk805 regulator. The regulator module consists
of 4 DCDCs, 3 LDOs.

The output voltages are configurable and are meant to supply power
to the main processor and other components.

Signed-off-by: Elaine Zhang 
---
 drivers/regulator/Kconfig   |  4 +--
 drivers/regulator/rk808-regulator.c | 66 +
 2 files changed, 68 insertions(+), 2 deletions(-)

diff --git a/drivers/regulator/Kconfig b/drivers/regulator/Kconfig
index be06eb29c681..285e28051219 100644
--- a/drivers/regulator/Kconfig
+++ b/drivers/regulator/Kconfig
@@ -650,11 +650,11 @@ config REGULATOR_RC5T583
  outputs which can be controlled by i2c communication.
 
 config REGULATOR_RK808
-   tristate "Rockchip RK808/RK818 Power regulators"
+   tristate "Rockchip RK805/RK808/RK818 Power regulators"
depends on MFD_RK808
help
  Select this option to enable the power regulator of ROCKCHIP
- PMIC RK808 and RK818.
+ PMIC RK805,RK808 and RK818.
  This driver supports the control of different power rails of device
  through regulator interface. The device supports multiple DCDC/LDO
  outputs which can be controlled by i2c communication.
diff --git a/drivers/regulator/rk808-regulator.c 
b/drivers/regulator/rk808-regulator.c
index fb44d5215e30..78c969c19428 100644
--- a/drivers/regulator/rk808-regulator.c
+++ b/drivers/regulator/rk808-regulator.c
@@ -369,6 +369,68 @@ static int rk808_set_suspend_disable(struct regulator_dev 
*rdev)
.set_suspend_disable= rk808_set_suspend_disable,
 };
 
+static const struct regulator_desc rk805_reg[] = {
+   {
+   .name = "DCDC_REG1",
+   .supply_name = "vcc1",
+   .of_match = of_match_ptr("DCDC_REG1"),
+   .regulators_node = of_match_ptr("regulators"),
+   .id = RK805_ID_DCDC1,
+   .ops = &rk808_reg_ops,
+   .type = REGULATOR_VOLTAGE,
+   .min_uV = 712500,
+   .uV_step = 12500,
+   .n_voltages = 64,
+   .vsel_reg = RK805_BUCK1_ON_VSEL_REG,
+   .vsel_mask = RK818_BUCK_VSEL_MASK,
+   .enable_reg = RK805_DCDC_EN_REG,
+   .enable_mask = BIT(0),
+   .owner = THIS_MODULE,
+   }, {
+   .name = "DCDC_REG2",
+   .supply_name = "vcc2",
+   .of_match = of_match_ptr("DCDC_REG2"),
+   .regulators_node = of_match_ptr("regulators"),
+   .id = RK805_ID_DCDC2,
+   .ops = &rk808_reg_ops,
+   .type = REGULATOR_VOLTAGE,
+   .min_uV = 712500,
+   .uV_step = 12500,
+   .n_voltages = 64,
+   .vsel_reg = RK805_BUCK2_ON_VSEL_REG,
+   .vsel_mask = RK818_BUCK_VSEL_MASK,
+   .enable_reg = RK805_DCDC_EN_REG,
+   .enable_mask = BIT(1),
+   .owner = THIS_MODULE,
+   }, {
+   .name = "DCDC_REG3",
+   .supply_name = "vcc3",
+   .of_match = of_match_ptr("DCDC_REG3"),
+   .regulators_node = of_match_ptr("regulators"),
+   .id = RK805_ID_DCDC3,
+   .ops = &rk808_switch_ops,
+   .type = REGULATOR_VOLTAGE,
+   .n_voltages = 1,
+   .enable_reg = RK805_DCDC_EN_REG,
+   .enable_mask = BIT(2),
+   .owner = THIS_MODULE,
+   },
+
+   RK8XX_DESC(RK805_ID_DCDC4, "DCDC_REG4", "vcc4", 800, 3400, 100,
+   RK805_BUCK4_ON_VSEL_REG, RK818_BUCK4_VSEL_MASK,
+   RK805_DCDC_EN_REG, BIT(3), 0),
+
+   RK8XX_DESC(RK805_ID_LDO1, "LDO_REG1", "vcc5", 800, 3400, 100,
+   RK805_LDO1_ON_VSEL_REG, RK818_LDO_VSEL_MASK, RK805_LDO_EN_REG,
+   BIT(0), 400),
+   RK8XX_DESC(RK805_ID_LDO2, "LDO_REG2", "vcc5", 800, 3400, 100,
+   RK805_LDO2_ON_VSEL_REG, RK818_LDO_VSEL_MASK, RK805_LDO_EN_REG,
+   BIT(1), 400),
+   RK8XX_DESC(RK805_ID_LDO3, "LDO_REG3", "vcc6", 800, 3400, 100,
+   RK805_LDO3_ON_VSEL_REG, RK818_LDO_VSEL_MASK, RK805_LDO_EN_REG,
+   BIT(2), 400),
+};
+
 static const struct regulator_desc rk808_reg[] = {
{
.name = "DCDC_REG1",
@@ -625,6 +687,10 @@ static int rk808_regulator_probe(struct platform_device 
*pdev)
platform_set_drvdata(pdev, pdata);
 
switch (rk808->variant) {
+   case RK805_ID:
+   regulators = rk805_reg;
+   nregulators = RK805_NUM_REGULATORS;
+   break;
case RK808_ID:
regulators = rk808_reg;
nregulators = RK808_NUM_REGULATORS;
-- 
1.9.1

Re: "mm: fix lazyfree BUG_ON check in try_to_unmap_one()" build error

[Michal Hocko]

On Thu 09-03-17 15:02:26, Minchan Kim wrote:
[...]
> >From 38b10e560d066c2cef8f9d028e14008cefdaa3e0 Mon Sep 17 00:00:00 2001
> From: Minchan Kim 
> Date: Thu, 9 Mar 2017 14:58:23 +0900
> Subject: [PATCH] mm: do not use VM_WARN_ON_ONCE as if condition
> 
> Sergey reported VM_WARN_ON_ONCE returns void with !CONFIG_DEBUG_VM
> so we cannot use it as if's condition unlike WARN_ON.

I would swear I've seen WARN_ON_ONCE there when looking at the previous
patch! Btw. could have simply s@VM_@@ 

> This patch fixes it.
> 
> Signed-off-by: Minchan Kim 

Acked-by: Michal Hocko 

> ---
>  mm/rmap.c | 5 ++---
>  1 file changed, 2 insertions(+), 3 deletions(-)
> 
> diff --git a/mm/rmap.c b/mm/rmap.c
> index 1d82057144ba..7d24bb93445b 100644
> --- a/mm/rmap.c
> +++ b/mm/rmap.c
> @@ -1413,12 +1413,11 @@ static int try_to_unmap_one(struct page *page, struct 
> vm_area_struct *vma,
>* Store the swap location in the pte.
>* See handle_pte_fault() ...
>*/
> - if (VM_WARN_ON_ONCE(PageSwapBacked(page) !=
> - PageSwapCache(page))) {
> + if (unlikely(PageSwapBacked(page) != 
> PageSwapCache(page))) {
> + WARN_ON_ONCE(1);
>   ret = SWAP_FAIL;
>   page_vma_mapped_walk_done(&pvmw);
>   break;
> -
>   }
>  
>   /* MADV_FREE page check */
> -- 
> 2.7.4

-- 
Michal Hocko
SUSE Labs

Re: [f2fs-dev] [PATCH 1/4] f2fs: fix wrong error injection for evict_inode

[Chao Yu]

Hi Jaegeuk,

On 2017/3/8 6:13, Jaegeuk Kim wrote:
> The previous one was not a proper location to inject an error, since there
> is no point to get errors. Instead, we can emulate EIO during truncation,
> and the below logic should handle it correctly.
> 
> Signed-off-by: Jaegeuk Kim 
> ---
>  fs/f2fs/inode.c | 13 ++---
>  1 file changed, 6 insertions(+), 7 deletions(-)
> 
> diff --git a/fs/f2fs/inode.c b/fs/f2fs/inode.c
> index ef8610bf950f..2520fa72b23f 100644
> --- a/fs/f2fs/inode.c
> +++ b/fs/f2fs/inode.c
> @@ -372,13 +372,6 @@ void f2fs_evict_inode(struct inode *inode)
>   if (inode->i_nlink || is_bad_inode(inode))
>   goto no_delete;
>  
> -#ifdef CONFIG_F2FS_FAULT_INJECTION
> - if (time_to_inject(sbi, FAULT_EVICT_INODE)) {
> - f2fs_show_injection_info(FAULT_EVICT_INODE);
> - goto no_delete;
> - }
> -#endif
> -
>   remove_ino_entry(sbi, inode->i_ino, APPEND_INO);
>   remove_ino_entry(sbi, inode->i_ino, UPDATE_INO);
>  
> @@ -389,6 +382,12 @@ void f2fs_evict_inode(struct inode *inode)
>   if (F2FS_HAS_BLOCKS(inode))

In addition, how about add below code to emulate error came from f2fs_truncate?

if (F2FS_HAS_BLOCKS(inode)) {
#ifdef CONFIG_F2FS_FAULT_INJECTION
if (time_to_inject(sbi, FAULT_EVICT_INODE)) {
f2fs_show_injection_info(FAULT_EVICT_INODE);
err = -EIO;
}
#endif
if (!err)
err = f2fs_truncate(inode);
}

Thanks,

>   err = f2fs_truncate(inode);
>  
> +#ifdef CONFIG_F2FS_FAULT_INJECTION
> + if (time_to_inject(sbi, FAULT_EVICT_INODE)) {
> + f2fs_show_injection_info(FAULT_EVICT_INODE);
> + err = -EIO;
> + }
> +#endif
>   if (!err) {
>   f2fs_lock_op(sbi);
>   err = remove_inode_page(inode);
> 

Re: [PATCH 5/5] staging/lustre: Use generic range rwlock

[kbuild test robot]

Hi Davidlohr,

[auto build test WARNING on staging/staging-testing]
[also build test WARNING on v4.11-rc1 next-20170309]
[if your patch is applied to the wrong git tree, please drop us a note to help 
improve the system]

url:
https://github.com/0day-ci/linux/commits/Davidlohr-Bueso/locking-Introduce-range-reader-writer-lock/20170309-140444
config: i386-allmodconfig (attached as .config)
compiler: gcc-6 (Debian 6.2.0-3) 6.2.0 20160901
reproduce:
# save the attached .config to linux build tree
make ARCH=i386 

All warnings (new ones prefixed by >>):

   In file included from 
drivers/staging/lustre/lustre/llite/../include/lustre/lustre_idl.h:76:0,
from 
drivers/staging/lustre/lustre/llite/../include/lustre_lib.h:49,
from 
drivers/staging/lustre/lustre/llite/../include/lustre_dlm.h:47,
from drivers/staging/lustre/lustre/llite/file.c:40:
   drivers/staging/lustre/lustre/llite/file.c: In function 'll_file_io_generic':
>> drivers/staging/lustre/lustre/llite/../include/lustre/lustre_user.h:78:20: 
>> warning: large integer implicitly truncated to unsigned type [-Woverflow]
#define LUSTRE_EOF 0xULL
   ^
>> drivers/staging/lustre/lustre/llite/file.c:1072:33: note: in expansion of 
>> macro 'LUSTRE_EOF'
   range_rwlock_init(&range, 0, LUSTRE_EOF);
^~

vim +78 drivers/staging/lustre/lustre/llite/../include/lustre/lustre_user.h

23ec6607e9 John L. Hammond 2016-09-18  62   * are co-existing.
23ec6607e9 John L. Hammond 2016-09-18  63   */
23ec6607e9 John L. Hammond 2016-09-18  64  #if __BITS_PER_LONG != 64 || 
defined(__ARCH_WANT_STAT64)
23ec6607e9 John L. Hammond 2016-09-18  65  typedef struct stat64   lstat_t;
23ec6607e9 John L. Hammond 2016-09-18  66  #define lstat_f  lstat64
f0cf21abcc John L. Hammond 2016-10-02  67  #define fstat_f  fstat64
f0cf21abcc John L. Hammond 2016-10-02  68  #define fstatat_ffstatat64
23ec6607e9 John L. Hammond 2016-09-18  69  #else
23ec6607e9 John L. Hammond 2016-09-18  70  typedef struct stat lstat_t;
23ec6607e9 John L. Hammond 2016-09-18  71  #define lstat_f  lstat
f0cf21abcc John L. Hammond 2016-10-02  72  #define fstat_f  fstat
f0cf21abcc John L. Hammond 2016-10-02  73  #define fstatat_ffstatat
23ec6607e9 John L. Hammond 2016-09-18  74  #endif
23ec6607e9 John L. Hammond 2016-09-18  75  
23ec6607e9 John L. Hammond 2016-09-18  76  #define HAVE_LOV_USER_MDS_DATA
d7e09d0397 Peng Tao2013-05-02  77  
00c0a6aea0 John L. Hammond 2016-08-16 @78  #define LUSTRE_EOF 
0xULL
00c0a6aea0 John L. Hammond 2016-08-16  79  
d7e09d0397 Peng Tao2013-05-02  80  /* for statfs() */
d7e09d0397 Peng Tao2013-05-02  81  #define LL_SUPER_MAGIC 0x0BD00BD0
d7e09d0397 Peng Tao2013-05-02  82  
d7e09d0397 Peng Tao2013-05-02  83  #ifndef FSFILT_IOC_GETFLAGS
d7e09d0397 Peng Tao2013-05-02  84  #define FSFILT_IOC_GETFLAGS 
_IOR('f', 1, long)
d7e09d0397 Peng Tao2013-05-02  85  #define FSFILT_IOC_SETFLAGS 
_IOW('f', 2, long)
d7e09d0397 Peng Tao2013-05-02  86  #define FSFILT_IOC_GETVERSION
 _IOR('f', 3, long)

:: The code at line 78 was first introduced by commit
:: 00c0a6aea0d0ab2c11594616244d787ad7bf64dc staging: lustre: uapi: reduce 
scope of lustre_idl.h

:: TO: John L. Hammond 
:: CC: Greg Kroah-Hartman 

---
0-DAY kernel test infrastructureOpen Source Technology Center
https://lists.01.org/pipermail/kbuild-all   Intel Corporation


.config.gz
Description: application/gzip

[PATCH v3 13/23] dt-bindings: PCI: dra7xx: Add dt bindings for pci dra7xx EP mode

[Kishon Vijay Abraham I]

Add device tree binding documentation for pci dra7xx EP mode.

Acked-by: Rob Herring 
Signed-off-by: Kishon Vijay Abraham I 
---
 Documentation/devicetree/bindings/pci/ti-pci.txt |   37 ++
 1 file changed, 30 insertions(+), 7 deletions(-)

diff --git a/Documentation/devicetree/bindings/pci/ti-pci.txt 
b/Documentation/devicetree/bindings/pci/ti-pci.txt
index 60e2516..190828a 100644
--- a/Documentation/devicetree/bindings/pci/ti-pci.txt
+++ b/Documentation/devicetree/bindings/pci/ti-pci.txt
@@ -1,17 +1,22 @@
 TI PCI Controllers
 
 PCIe Designware Controller
- - compatible: Should be "ti,dra7-pcie""
- - reg : Two register ranges as listed in the reg-names property
- - reg-names : The first entry must be "ti-conf" for the TI specific registers
-  The second entry must be "rc-dbics" for the designware pcie
-  registers
-  The third entry must be "config" for the PCIe configuration space
+ - compatible: Should be "ti,dra7-pcie" for RC
+  Should be "ti,dra7-pcie-ep" for EP
  - phys : list of PHY specifiers (used by generic PHY framework)
  - phy-names : must be "pcie-phy0", "pcie-phy1", "pcie-phyN".. based on the
   number of PHYs as specified in *phys* property.
  - ti,hwmods : Name of the hwmod associated to the pcie, "pcie",
   where  is the instance number of the pcie from the HW spec.
+ - num-lanes as specified in ../designware-pcie.txt
+
+HOST MODE
+=
+ - reg : Two register ranges as listed in the reg-names property
+ - reg-names : The first entry must be "ti-conf" for the TI specific registers
+  The second entry must be "rc-dbics" for the designware pcie
+  registers
+  The third entry must be "config" for the PCIe configuration space
  - interrupts : Two interrupt entries must be specified. The first one is for
main interrupt line and the second for MSI interrupt line.
  - #address-cells,
@@ -19,13 +24,31 @@ PCIe Designware Controller
#interrupt-cells,
device_type,
ranges,
-   num-lanes,
interrupt-map-mask,
interrupt-map : as specified in ../designware-pcie.txt
 
+DEVICE MODE
+===
+ - reg : Four register ranges as listed in the reg-names property
+ - reg-names : "ti-conf" for the TI specific registers
+  "ep_dbics" for the standard configuration registers as
+   they are locally accessed within the DIF CS space
+  "ep_dbics2" for the standard configuration registers as
+   they are locally accessed within the DIF CS2 space
+  "addr_space" used to map remote RC address space
+ - interrupts : one interrupt entries must be specified for main interrupt.
+ - num-ib-windows : number of inbound address translation windows
+ - num-ob-windows : number of outbound address translation windows
+
 Optional Property:
  - gpios : Should be added if a gpio line is required to drive PERST# line
 
+NOTE: Two dt nodes may be added for each PCI controller; one for host
+mode and another for device mode. So in order for PCI to
+work in host mode, EP mode dt node should be disabled and in order to PCI to
+work in EP mode, host mode dt node should be disabled. And host mode and EP
+mode are mutually exclusive.
+
 Example:
 axi {
compatible = "simple-bus";
-- 
1.7.9.5

Re: [PATCH 1/3] PCI: rockchip: fix sign issues for current limits

[Shawn Lin]

On 2017/3/9 7:37, Brian Norris wrote:

The regulator framework can return negative error codes via
regulator_get_current_limit() for regulators that don't provide current
information. The subsequent check for postive values isn't very useful,
if the variable is unsigned.

Let's just match the signedness of the return value.

Prevents error messages like this, seen on Samsung Chromebook Plus:

[1.069372] rockchip-pcie f800.pcie: invalid power supply



For this patch,

Acked-by: Shawn Lin 

And I think patch 2 is not so urgent so we could just wait for your
non-WIP patch 3?


Fixes: 4816c4c7b82b ("PCI: rockchip: Provide captured slot power limit and 
scale")
Signed-off-by: Brian Norris 
---
v4.11 candidate?

 drivers/pci/host/pcie-rockchip.c | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/drivers/pci/host/pcie-rockchip.c b/drivers/pci/host/pcie-rockchip.c
index 26ddd3535272..d785f64ec03b 100644
--- a/drivers/pci/host/pcie-rockchip.c
+++ b/drivers/pci/host/pcie-rockchip.c
@@ -425,7 +425,8 @@ static struct pci_ops rockchip_pcie_ops = {

 static void rockchip_pcie_set_power_limit(struct rockchip_pcie *rockchip)
 {
-   u32 status, curr, scale, power;
+   int curr;
+   u32 status, scale, power;

if (IS_ERR(rockchip->vpcie3v3))
return;




--
Best Regards
Shawn Lin

Re: [PATCH 3/4] phy: rockchip-typec: support DP phy switch

[Heiko Stübner]

Hi Brian,

Am Mittwoch, 8. März 2017, 19:10:50 CET schrieb Brian Norris:
> On Thu, Mar 09, 2017 at 02:02:54AM +0100, Heiko Stuebner wrote:
> > Am Mittwoch, 8. März 2017, 16:39:23 CET schrieb Brian Norris:
> > > On Fri, Feb 10, 2017 at 03:44:13PM +0800, Chris Zhong wrote:
> > > > There are 2 Type-c PHYs in RK3399, but only one DP controller. Hence
> > > > only one PHY can connect to DP controller at one time, the other
> > > > should
> > > > be disconnected. The GRF_SOC_CON26 register has a switch bit to do it,
> > > > set this bit means enable PHY 1, clear this bit means enable PHY 0.
> > > > 
> > > > Signed-off-by: Chris Zhong 
> > > > ---
> > > > 
> > > >  drivers/phy/phy-rockchip-typec.c | 9 +
> > > >  1 file changed, 9 insertions(+)
> > > > 
> > > > diff --git a/drivers/phy/phy-rockchip-typec.c
> > > > b/drivers/phy/phy-rockchip-typec.c index 7cfb0f8..1604aaa 100644
> > > > --- a/drivers/phy/phy-rockchip-typec.c
> > > > +++ b/drivers/phy/phy-rockchip-typec.c
> 
> ...
> 
> > > > @@ -869,6 +873,11 @@ static int tcphy_parse_dt(struct
> > > > rockchip_typec_phy
> > > > *tcphy,>
> > > > 
> > > > if (ret)
> > > > 
> > > > return ret;
> > > > 
> > > > +   ret = tcphy_get_param(dev, &cfg->uphy_dp_sel,
> > > > + "rockchip,uphy-dp-sel");
> > > > +   if (ret)
> > > > +   return ret;
> > > 
> > > What about existing device trees? You're essentially adding this
> > > new property and requiring it at the same time.
> > > 
> > > Or are we considering no RK3399 DP stable at the moment? I guess we
> > > haven't actually merged any device trees that support this yet, no?
> > 
> > An interesting situation we're in here. On the one hand, you're right this
> > breaks "backwards compatiblity".
> > 
> > But on the other hand, the type-c phy is currently very much unused. The
> > only current board rk3399-evb.dts does not enable them (so they're
> > disabled everywhere) and we have neither dwc3 nor dp nodes in any rk3399
> > devicetrees so far. Also Rob was ok with the binding change :-) .
> > 
> > So from my pov, I'd say it _should_ be ok, as nothing is using the phys at
> > all yet and thus there is nothing that could get broken.
> 
> Yeah, I guess it's OK... but BTW out-of-tree DTs are perfectly
> legit, once the bindings are accepted.
> 
> Another random point of contention (not worth too much, as the pattern
> is already set), but why do these deserve DT properties at all? The
> device already has a "rk3399" compatible property, so can't we derive
> GRF offsets from that?

I'm definitly with you in this regard.

But it seems like there is some sort of current trend of moving more stuff 
into the dt again. I vaguely remember phy and (or) dt-maintainers preferring 
to have these definitions in the dt for the typec-phy.

See also the recent mail from Olof concerning the grf initialization and maybe 
not having per-soc definitions in the driver, where I'm trying to keep things 
out of the dt a bit more strongly :-) .

So yes, personally I would definitly prefer not having to much GRF-stuff leak 
into the dt. Simply because the GRF has always been very unstable over time 
[=you always find one more bit that needs tuning] and to not cause things like 
the above. But as you said I guess we're to late for the typec-phy.


Heiko

Re: NULL pointer dereference in cgroup

[Luis Henriques]

On Wed, Mar 08, 2017 at 05:30:29PM -0600, Eric W. Biederman wrote:
> Luis Henriques  writes:
> 
> > Hi,
> >
> > I've seen this only once, and can't reproduce it.  But here it is anyway:
> >
> > https://postimg.org/image/pn94k1yov
> >
> > (Not sure png files are accepted on LKML.)
> >
> > This occurred in a VM while booting 4.11.0-rc1
> 
> Any idea what was happening when you triggered this?  A little context
> usually helps quite a bit when tracking things like this down.

Sorry, but I don't have more details.  As I said, I just booted a VM with
this kernel and when I looked again I saw this.  I assumed this happen
during boot.  I had used this kernel in this VM before without problems,
and I still use it -- only saw this once.

I'll keep an eye on it and see if I can gather more info if it happens
again.

Cheers,
--
Luís

[PATCH v5 0/4] phy: USB and PCIe phy drivers for Qcom chipsets

[Vivek Gautam]

This patch series adds couple of PHY drivers for Qualcomm chipsets.
a) qcom-qusb2 phy driver: that provides High Speed USB functionality.
b) qcom-qmp phy driver: that is a combo phy providing support for
   USB3, PCIe, UFS and few other controllers.

The patches are based on next branch of linux-phy tree.

These patches have been tested on Dragon board db820c hardware with
required set of dt patches and the patches to get rpm up on msm8996.
Couple of other patches [1, 2] fixing DMA config for XHCI are also
pulled in for testing.
The complete branch is available in github [3].

Changes since v4:
 - Addressed comment to add child nodes for qmp phy driver. Each phy lane
   now has a separate child node under the main qmp node.
 - Modified the clock and reset initialization and enable methods.
   Different phys - pcie, usb and later ufs, have varying number of clocks
   and resets that are mandatory. So adding provision for clocks and reset
   lists helps in requesting all mandatory resources for individual phys
   and handle their failure cases accordingly.

Changes since v3:
 - Addressed review comments given by Rob and Stephen for qusb2 phy
   and qmp phy bindings respectively.
 - Addressed review comments given by Stephen and Bjorn for qmp phy driver.

Changes since v2:
 - Addressed review comments given by Rob and Stephen for bindings.
 - Addressed the review comments given by Stephen for the qusb2 and qmp
   phy drivers.

Changes since v1:
 - Moved device tree binding documentation to separate patches, as suggested
   by Rob.
 - Addressed review comment regarding qfprom accesses by qusb2 phy driver,
   given by Rob.
 - Addressed review comments from Kishon.
 - Addressed review comments from Srinivas for QMP phy driver.
 - Addressed kbuild warning.

Please see individual patches for detailed changelogs.

[1] https://patchwork.kernel.org/patch/9567767/
[2] https://patchwork.kernel.org/patch/9567779/
[3] https://github.com/vivekgautam1/linux/tree/linux-v4.11-rc1-qmp-phy-db820c

Vivek Gautam (4):
  dt-bindings: phy: Add support for QUSB2 phy
  phy: qcom-qusb2: New driver for QUSB2 PHY on Qcom chips
  dt-bindings: phy: Add support for QMP phy
  phy: qcom-qmp: new qmp phy driver for qcom-chipsets

 .../devicetree/bindings/phy/qcom-qmp-phy.txt   |  106 ++
 .../devicetree/bindings/phy/qcom-qusb2-phy.txt |   45 +
 drivers/phy/Kconfig|   18 +
 drivers/phy/Makefile   |2 +
 drivers/phy/phy-qcom-qmp.c | 1191 
 drivers/phy/phy-qcom-qusb2.c   |  539 +
 6 files changed, 1901 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/phy/qcom-qmp-phy.txt
 create mode 100644 Documentation/devicetree/bindings/phy/qcom-qusb2-phy.txt
 create mode 100644 drivers/phy/phy-qcom-qmp.c
 create mode 100644 drivers/phy/phy-qcom-qusb2.c

-- 
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
a Linux Foundation Collaborative Project

[PATCH v5 1/4] dt-bindings: phy: Add support for QUSB2 phy

[Vivek Gautam]

Qualcomm chipsets have QUSB2 phy controller that provides
HighSpeed functionality for DWC3 controller.
Adding dt binding information for the same.

Signed-off-by: Vivek Gautam 
Acked-by: Rob Herring 
---

Changes since v4:
 - None.

Changes since v3:
 - Added 'Acked-by' from Rob.
 - Removed 'reset-names' and 'nvmem-cell-names' from the bindings
   since we use only one cell.

Changes since v2:
 - Removed binding for "ref_clk_src" since we don't request this
   clock in the driver.
 - Addressed s/vdda-phy-dpdm/vdda-phy-dpdm-supply.
 - Addressed s/ref_clk/ref. Don't need to add '_clk' suffix to clock names.
 - Addressed s/tune2_hstx_trim_efuse/tune2_hstx_trim. Don't need to add
   'efuse' suffix to nvmem cell.
 - Addressed s/qusb2phy/phy for the node name.

Changes since v1:
 - New patch, forked out of the original driver patch:
   "phy: qcom-qusb2: New driver for QUSB2 PHY on Qcom chips"
 - Updated dt bindings to remove 'hstx-trim-bit-offset' and
   'hstx-trim-bit-len' bindings.

 .../devicetree/bindings/phy/qcom-qusb2-phy.txt | 45 ++
 1 file changed, 45 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/phy/qcom-qusb2-phy.txt

diff --git a/Documentation/devicetree/bindings/phy/qcom-qusb2-phy.txt 
b/Documentation/devicetree/bindings/phy/qcom-qusb2-phy.txt
new file mode 100644
index ..218595fe8824
--- /dev/null
+++ b/Documentation/devicetree/bindings/phy/qcom-qusb2-phy.txt
@@ -0,0 +1,45 @@
+Qualcomm QUSB2 phy controller
+=
+
+QUSB2 controller supports LS/FS/HS usb connectivity on Qualcomm chipsets.
+
+Required properties:
+ - compatible: compatible list, contains "qcom,msm8996-qusb2-phy".
+ - reg: offset and length of the PHY register set.
+ - #phy-cells: must be 0.
+
+ - clocks: a list of phandles and clock-specifier pairs,
+  one for each entry in clock-names.
+ - clock-names: must be "cfg_ahb" for phy config clock,
+   "ref" for 19.2 MHz ref clk,
+   "iface" for phy interface clock (Optional).
+
+ - vdd-phy-supply: Phandle to a regulator supply to PHY core block.
+ - vdda-pll-supply: Phandle to 1.8V regulator supply to PHY refclk pll block.
+ - vdda-phy-dpdm-supply: Phandle to 3.1V regulator supply to Dp/Dm port 
signals.
+
+ - resets: Phandle to reset to phy block.
+
+Optional properties:
+ - nvmem-cells: Phandle to nvmem cell that contains 'HS Tx trim'
+   tuning parameter value for qusb2 phy.
+
+ - qcom,tcsr-syscon: Phandle to TCSR syscon register region.
+
+Example:
+   hsusb_phy: phy@7411000 {
+   compatible = "qcom,msm8996-qusb2-phy";
+   reg = <0x07411000 0x180>;
+   #phy-cells = <0>;
+
+   clocks = <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>,
+   <&gcc GCC_RX1_USB2_CLKREF_CLK>,
+   clock-names = "cfg_ahb", "ref";
+
+   vdd-phy-supply = <&pm8994_s2>;
+   vdda-pll-supply = <&pm8994_l12>;
+   vdda-phy-dpdm-supply = <&pm8994_l24>;
+
+   resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>;
+   nvmem-cells = <&qusb2p_hstx_trim>;
+};
-- 
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
a Linux Foundation Collaborative Project

[PATCH v5 2/4] phy: qcom-qusb2: New driver for QUSB2 PHY on Qcom chips

[Vivek Gautam]

PHY transceiver driver for QUSB2 phy controller that provides
HighSpeed functionality for DWC3 controller present on
Qualcomm chipsets.

Signed-off-by: Vivek Gautam 
Reviewed-by: Stephen Boyd 
---

Changes since v4:
 - Updated the copyright year to 2017.
 - Removed unnecessary of_match_ptr() cast for the match table,
   since the driver is compiled for CONFIG_OF.

Changes since v3:
 - Added 'Reviewed-by' from Stephen.
 - Fixed debug message for qusb2_phy_set_tune2_param().
 - Replaced devm_reset_control_get() with devm_reset_control_get_by_index()
   since we are requesting only one reset.
 - Updated devm_nvmem_cell_get() with a NULL cell id.
 - Made error labels more idiomatic.
 - Refactored qusb2_setbits() and qusb2_clrbits() a little bit to accept
   base address and register offset as two separate arguments.

Changes since v2:
 - Removed selecting 'RESET_CONTROLLER' config.
 - Added error handling for clk_prepare_enable paths.
 - Removed explicitly setting ref_clk rate to 19.2 MHz. Don't need to
   do that since 'xo' is modeled as parent to this clock.
 - Removed 'ref_clk_src' handling. Driver doesn't need to request and
   handle this clock.
 - Moved nvmem_cell_get() to probe function.
 - Simplified phy pll status handling.
 - Using of_device_get_match_data() to get match data.
 - Uniformly using lowercase for hex numbers.
 - Fixed sparse warnings.
 - Using shorter variable names in structure and in functions.
 - Handling various comment style shortcomings.

Changes since v1:
 - removed reference to clk_enabled/pwr_enabled.
 - moved clock and regulator enable code to phy_power_on/off() callbacks.
 - fixed return on EPROBE_DEFER in qusb2_phy_probe().
 - fixed phy create and phy register ordering.
 - removed references to non-lkml links from commit message.
 - took care of other minor nits.
 - Fixed coccinelle warnings -
   'PTR_ERR applied after initialization to constant'
 - Addressed review comment, regarding qfprom access for tune2 param value.
   This driver is now based on qfprom patch[1] that allows byte access now.

 drivers/phy/Kconfig  |  10 +
 drivers/phy/Makefile |   1 +
 drivers/phy/phy-qcom-qusb2.c | 539 +++
 3 files changed, 550 insertions(+)
 create mode 100644 drivers/phy/phy-qcom-qusb2.c

diff --git a/drivers/phy/Kconfig b/drivers/phy/Kconfig
index dc5277ad1b5a..ccc9178e32cd 100644
--- a/drivers/phy/Kconfig
+++ b/drivers/phy/Kconfig
@@ -439,6 +439,16 @@ config PHY_STIH407_USB
  Enable this support to enable the picoPHY device used by USB2
  and USB3 controllers on STMicroelectronics STiH407 SoC families.
 
+config PHY_QCOM_QUSB2
+   tristate "Qualcomm QUSB2 PHY Driver"
+   depends on OF && (ARCH_QCOM || COMPILE_TEST)
+   select GENERIC_PHY
+   help
+ Enable this to support the HighSpeed QUSB2 PHY transceiver for USB
+ controllers on Qualcomm chips. This driver supports the high-speed
+ PHY which is usually paired with either the ChipIdea or Synopsys DWC3
+ USB IPs on MSM SOCs.
+
 config PHY_QCOM_UFS
tristate "Qualcomm UFS PHY driver"
depends on OF && ARCH_QCOM
diff --git a/drivers/phy/Makefile b/drivers/phy/Makefile
index e7b0feb1e125..bf16deff2a7b 100644
--- a/drivers/phy/Makefile
+++ b/drivers/phy/Makefile
@@ -50,6 +50,7 @@ obj-$(CONFIG_PHY_ST_SPEAR1310_MIPHY)  += phy-spear1310-miphy.o
 obj-$(CONFIG_PHY_ST_SPEAR1340_MIPHY)   += phy-spear1340-miphy.o
 obj-$(CONFIG_PHY_XGENE)+= phy-xgene.o
 obj-$(CONFIG_PHY_STIH407_USB)  += phy-stih407-usb.o
+obj-$(CONFIG_PHY_QCOM_QUSB2)   += phy-qcom-qusb2.o
 obj-$(CONFIG_PHY_QCOM_UFS) += phy-qcom-ufs.o
 obj-$(CONFIG_PHY_QCOM_UFS) += phy-qcom-ufs-qmp-20nm.o
 obj-$(CONFIG_PHY_QCOM_UFS) += phy-qcom-ufs-qmp-14nm.o
diff --git a/drivers/phy/phy-qcom-qusb2.c b/drivers/phy/phy-qcom-qusb2.c
new file mode 100644
index ..2879949ab1cd
--- /dev/null
+++ b/drivers/phy/phy-qcom-qusb2.c
@@ -0,0 +1,539 @@
+/*
+ * Copyright (c) 2017, The Linux Foundation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+#define QUSB2PHY_PLL_TEST  0x04
+#define CLK_REF_SELBIT(7)
+
+#define QUSB2PHY_PLL_TUNE  0x08
+#define QUSB2PHY_PLL_USER_CTL1 0x0c
+#define QUSB2PHY_PLL_USER_CTL2 0x10
+#define QUSB2PHY_PLL_AUTOPGM_CTL1  

[PATCH v5 3/4] dt-bindings: phy: Add support for QMP phy

[Vivek Gautam]

Qualcomm chipsets have QMP phy controller that provides
support to a number of controller, viz. PCIe, UFS, and USB.
Adding dt binding information for the same.

Signed-off-by: Vivek Gautam 
Cc: Rob Herring 
---

Hi Rob,
I have removed your Acked-by tag because of the change in bindings.
Please consider adding your Ack again if you are fine with these
updated bindings.

Changes since v4:
 - Added bindings for child nodes. Each phy lane is represented by child
   node with its own register space (for tx, rx and pcs blocks), and clocks
   and resets for power control facility.
 - Removed register space and lane offsets for tx, rx and pcs blocks from
   qmp phy node.
 - #phy-cells is now part of each child node and thus must be 0.
 - Added information on list of mandatory clocks and resets for each phy.

Changes since v3:
 - Added #clock-cells = <1>, indicating that phy is a clock provider.

Changes since v2:
 - Removed binding for "ref_clk_src" since we don't request this
   clock in the driver.
 - Addressed s/ref_clk/ref. Don't need to add '_clk' suffix to clock names.
 - Using 'phy' for the node name.

Changes since v1:
 - New patch, forked out of the original driver patch:
   "phy: qcom-qmp: new qmp phy driver for qcom-chipsets"
 - Added 'Acked-by' from Rob.
 - Updated bindings to include mem resource as a list of
   offset - length pair for serdes block and for each lane.
 - Added a new binding for 'lane-offsets' that contains offsets
   to tx, rx and pcs blocks from each lane base address.

 .../devicetree/bindings/phy/qcom-qmp-phy.txt   | 106 +
 1 file changed, 106 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/phy/qcom-qmp-phy.txt

diff --git a/Documentation/devicetree/bindings/phy/qcom-qmp-phy.txt 
b/Documentation/devicetree/bindings/phy/qcom-qmp-phy.txt
new file mode 100644
index ..5595c3fabe0a
--- /dev/null
+++ b/Documentation/devicetree/bindings/phy/qcom-qmp-phy.txt
@@ -0,0 +1,106 @@
+Qualcomm QMP PHY controller
+===
+
+QMP phy controller supports physical layer functionality for a number of
+controllers on Qualcomm chipsets, such as, PCIe, UFS, and USB.
+
+Required properties:
+ - compatible: compatible list, contains:
+  "qcom,msm8996-qmp-pcie-phy" for 14nm PCIe phy on msm8996,
+  "qcom,msm8996-qmp-usb3-phy" for 14nm USB3 phy on msm8996.
+
+ - reg: offset and length of register set for PHY's common serdes block.
+
+ - #clock-cells: must be 1
+- Phy pll outputs a bunch of clocks for Tx, Rx and Pipe
+  interface (for pipe based PHYs). These clock are then gate-controlled
+  by gcc.
+ - #address-cells: must be 1
+ - #size-cells: must be 1
+ - ranges: must be present
+
+ - clocks: a list of phandles and clock-specifier pairs,
+  one for each entry in clock-names.
+ - clock-names: "cfg_ahb" for phy config clock,
+   "aux" for phy aux clock,
+   "ref" for 19.2 MHz ref clk,
+   For "qcom,msm8996-qmp-pcie-phy" must contain:
+   "aux", "cfg_ahb", "ref".
+   For "qcom,msm8996-qmp-usb3-phy" must contain:
+   "aux", "cfg_ahb", "ref".
+
+ - resets: a list of phandles and reset controller specifier pairs,
+  one for each entry in reset-names.
+ - reset-names: "phy" for reset of phy block,
+   "common" for phy common block reset,
+   "cfg" for phy's ahb cfg block reset (Optional).
+   For "qcom,msm8996-qmp-pcie-phy" must contain:
+"phy", "common", "cfg".
+   For "qcom,msm8996-qmp-usb3-phy" must contain
+"phy", "common".
+
+ - vdda-phy-supply: Phandle to a regulator supply to PHY core block.
+ - vdda-pll-supply: Phandle to 1.8V regulator supply to PHY refclk pll block.
+
+Optional properties:
+ - vddp-ref-clk-supply: Phandle to a regulator supply to any specific refclk
+   pll block.
+
+Required nodes:
+ - Each device node of QMP phy is required to have as many child nodes as
+   the number of lanes the PHY has.
+
+Required properties for child node:
+ - reg: list of offset and length pairs of register sets for PHY blocks -
+   tx, rx and pcs.
+
+ - #phy-cells: must be 0
+
+ - clocks: a list of phandles and clock-specifier pairs,
+  one for each entry in clock-names.
+ - clock-names: Must contain following for pcie and usb qmp phys:
+"pipe" for pipe clock specific to each lane.
+
+ - resets: a list of phandles and reset controller specifier pairs,
+  one for each entry in reset-names.
+ - reset-names: Must contain following for pcie qmp phys:
+"lane" for reset specific to each lane.
+
+Example:
+   phy@34000 {
+   compatible = "qcom,msm8996-qmp-pcie-phy";
+   reg = <0x034000 0x488>;
+   #clock-cells = <1>;
+   #address-cells = <1>;
+   #size-cells = <1>;
+   ranges;
+
+  

[PATCH v5 4/4] phy: qcom-qmp: new qmp phy driver for qcom-chipsets

[Vivek Gautam]

Qualcomm SOCs have QMP phy controller that provides support
to a number of controller, viz. PCIe, UFS, and USB.
Add a new driver, based on generic phy framework, for this
phy controller.

Signed-off-by: Vivek Gautam 
Tested-by: Srinivas Kandagatla 
---

Changes since v4:
 - Added provision for child nodes representing each phy lane.
   Each of these nodes have their own register space for tx, rx and pcs
   blocks. Added provision in qcom_qmp_phy_create() to iomap these
   address spaces.
 - Added list of clocks and resets that are mandatory for each phy.
   qcom_qmp_phy_clk_init(), and qcom_qmp_phy_reset_init() methods
   request this list and maintains it with qmp.
   The clocks and resets are then enabled/de-asserted based on this list.
   This list is also updated in the binding documentation.
 - Removed qcom_qmp_phy_xlate() method as we don't need it with
   #phy-cells 0.
 - Removed unnecessary of_match_ptr() cast for the match table,
   since the driver is compiled for CONFIG_OF.
 - Updated copyright year to 2017.

Changes since v3:
 - Renamed 'struct qcom_qmp_phy' to 'struct qcom_qmp' and
   'struct qmp_phy_desc' to 'struct qmp_phy' to avoid any confusion
   in distinguishing between QMP phy block and per-lane phy which is
   the actual phy in Linux eyes (suggested by Bjorn Andersson).
 - Made error labels more idiomatic.
 - Modified status checking for phy pcs.
 - Fixed power_down_delay check.
 - Refactored phy_pipe_clk_register() to register the pipe clock source
   using devm_clk_hw_register() (suggested by Stephen).
 - qcom_qmp_phy_xlate() function:
   - Removed unnecessary 'for loop'.
   - Added additional check for '0' or -ve args_count.
 - Fixed the mixed tabs and spaces in pipe_clk_src diagram.
 - Removed instances of memset() since we use snprintf() for the
   buffers.
 - Refactored qphy_setbits() and qphy_clrbits() a little bit to accept
   base address and register offset as two separate arguments.

Changes since v2:
 - Removed selecting 'RESET_CONTROLLER' config.
 - Added error handling for clk_prepare_enable paths.
 - Removed 'ref_clk_src' handling. Driver doesn't need to request and
   handle this clock.
 - Using readl_poll_timeout() to simplify pcs ready status polling.
   Also fixed the polling condition for pcs block ready status:
   'Common block ready status bit is set on phy init completion, while
   PCS block ready status bit (PHYSTATUS) is reset on phy init
   completion.'
 - Moved out the per-lane phy creation from probe() to separate
   function.
 - Registering pipe clock source as a fixed rate clock that comes
   out of the PLL block of QMP phy. These source clocks serve as
   parent to 'pipe_clks' that are requested by pcie or usb3 phys.
 - Using of_device_get_match_data() to get match data.
 - Fixed sparse warnings for 'static' and 'const'.
 - Using shorter variable names in structure and in functions.
 - Handling various comment style shortcomings.

Changes since v1:
 - Fixed missing mutex_unlock() calls in error cases, reported by
   Julia Lawall.
 - Selecting CONFIG_RESET_CONTROLLER when this driver is enabled.
 - Added a boolean property to check if the phy has individual lane
   reset available.
 - Took care or EPROBE_DEFER, dev_vdbg() and other minor nits.
 - Removed references to non-lkml links from commit message.
 - Moved to use separate iomem resources for each lanes.
   Tx, Rx and PCS offsets per lane can now come from dt bindings.

 drivers/phy/Kconfig|8 +
 drivers/phy/Makefile   |1 +
 drivers/phy/phy-qcom-qmp.c | 1191 
 3 files changed, 1200 insertions(+)
 create mode 100644 drivers/phy/phy-qcom-qmp.c

diff --git a/drivers/phy/Kconfig b/drivers/phy/Kconfig
index ccc9178e32cd..bb8140355608 100644
--- a/drivers/phy/Kconfig
+++ b/drivers/phy/Kconfig
@@ -439,6 +439,14 @@ config PHY_STIH407_USB
  Enable this support to enable the picoPHY device used by USB2
  and USB3 controllers on STMicroelectronics STiH407 SoC families.
 
+config PHY_QCOM_QMP
+   tristate "Qualcomm QMP PHY Driver"
+   depends on OF && (ARCH_QCOM || COMPILE_TEST)
+   select GENERIC_PHY
+   help
+ Enable this to support the QMP PHY transceiver that is used
+ with controllers such as PCIe, UFS, and USB on Qualcomm chips.
+
 config PHY_QCOM_QUSB2
tristate "Qualcomm QUSB2 PHY Driver"
depends on OF && (ARCH_QCOM || COMPILE_TEST)
diff --git a/drivers/phy/Makefile b/drivers/phy/Makefile
index bf16deff2a7b..b44650585113 100644
--- a/drivers/phy/Makefile
+++ b/drivers/phy/Makefile
@@ -51,6 +51,7 @@ obj-$(CONFIG_PHY_ST_SPEAR1340_MIPHY)  += phy-spear1340-miphy.o
 obj-$(CONFIG_PHY_XGENE)+= phy-xgene.o
 obj-$(CONFIG_PHY_STIH407_USB)  += phy-stih407-usb.o
 obj-$(CONFIG_PHY_QCOM_QUSB2)   += phy-qcom-qusb2.o
+obj-$(CONFIG_PHY_QCOM_QMP) += phy-qcom-qmp.o
 obj-$(CONFIG_PHY_QCOM_UFS) += phy-qcom-ufs.o
 obj-$(CONFIG_PHY_QCOM_UFS) += phy-qcom-ufs-qm

[PATCH 5/6] mm/migrate: Add new migration flag MPOL_MF_MOVE_MT for syscalls

[Anshuman Khandual]

From: Zi Yan 

This change adds a new mode flag MPOL_MF_MOVE_MT for migration system
calls like move_pages() and mbind() which indicates request for using
the multi threaded copy method.

Signed-off-by: Zi Yan 
Signed-off-by: Anshuman Khandual 
---
* Updated include/linux/migrate_mode.h comment as per Naoya

 include/uapi/linux/mempolicy.h |  4 +++-
 mm/mempolicy.c |  7 ++-
 mm/migrate.c   | 14 ++
 3 files changed, 19 insertions(+), 6 deletions(-)

diff --git a/include/uapi/linux/mempolicy.h b/include/uapi/linux/mempolicy.h
index 9cd8b21..8f1db2e 100644
--- a/include/uapi/linux/mempolicy.h
+++ b/include/uapi/linux/mempolicy.h
@@ -53,10 +53,12 @@ enum mpol_rebind_step {
 #define MPOL_MF_MOVE_ALL (1<<2)/* Move every page to conform to policy 
*/
 #define MPOL_MF_LAZY(1<<3) /* Modifies '_MOVE:  lazy migrate on fault */
 #define MPOL_MF_INTERNAL (1<<4)/* Internal flags start here */
+#define MPOL_MF_MOVE_MT  (1<<6)/* Use multi-threaded page copy routine 
*/
 
 #define MPOL_MF_VALID  (MPOL_MF_STRICT   | \
 MPOL_MF_MOVE | \
-MPOL_MF_MOVE_ALL)
+MPOL_MF_MOVE_ALL | \
+MPOL_MF_MOVE_MT)
 
 /*
  * Internal flags that share the struct mempolicy flags word with
diff --git a/mm/mempolicy.c b/mm/mempolicy.c
index d880dc6..2d06ee2 100644
--- a/mm/mempolicy.c
+++ b/mm/mempolicy.c
@@ -1300,9 +1300,14 @@ static long do_mbind(unsigned long start, unsigned long 
len,
int nr_failed = 0;
 
if (!list_empty(&pagelist)) {
+   enum migrate_mode mode = MIGRATE_SYNC;
+
+   if (flags & MPOL_MF_MOVE_MT)
+   mode |= MIGRATE_MT;
+
WARN_ON_ONCE(flags & MPOL_MF_LAZY);
nr_failed = migrate_pages(&pagelist, new_page, NULL,
-   start, MIGRATE_SYNC, MR_MEMPOLICY_MBIND);
+   start, mode, MR_MEMPOLICY_MBIND);
if (nr_failed)
putback_movable_pages(&pagelist);
}
diff --git a/mm/migrate.c b/mm/migrate.c
index 187065e..7449f7d 100644
--- a/mm/migrate.c
+++ b/mm/migrate.c
@@ -1481,11 +1481,16 @@ static struct page *new_page_node(struct page *p, 
unsigned long private,
  */
 static int do_move_page_to_node_array(struct mm_struct *mm,
  struct page_to_node *pm,
- int migrate_all)
+ int migrate_all,
+ int migrate_use_mt)
 {
int err;
struct page_to_node *pp;
LIST_HEAD(pagelist);
+   enum migrate_mode mode = MIGRATE_SYNC;
+
+   if (migrate_use_mt)
+   mode |= MIGRATE_MT;
 
down_read(&mm->mmap_sem);
 
@@ -1562,7 +1567,7 @@ static int do_move_page_to_node_array(struct mm_struct 
*mm,
err = 0;
if (!list_empty(&pagelist)) {
err = migrate_pages(&pagelist, new_page_node, NULL,
-   (unsigned long)pm, MIGRATE_SYNC, MR_SYSCALL);
+   (unsigned long)pm, mode, MR_SYSCALL);
if (err)
putback_movable_pages(&pagelist);
}
@@ -1639,7 +1644,8 @@ static int do_pages_move(struct mm_struct *mm, nodemask_t 
task_nodes,
 
/* Migrate this chunk */
err = do_move_page_to_node_array(mm, pm,
-flags & MPOL_MF_MOVE_ALL);
+flags & MPOL_MF_MOVE_ALL,
+flags & MPOL_MF_MOVE_MT);
if (err < 0)
goto out_pm;
 
@@ -1746,7 +1752,7 @@ SYSCALL_DEFINE6(move_pages, pid_t, pid, unsigned long, 
nr_pages,
nodemask_t task_nodes;
 
/* Check flags */
-   if (flags & ~(MPOL_MF_MOVE|MPOL_MF_MOVE_ALL))
+   if (flags & ~(MPOL_MF_MOVE|MPOL_MF_MOVE_ALL|MPOL_MF_MOVE_MT))
return -EINVAL;
 
if ((flags & MPOL_MF_MOVE_ALL) && !capable(CAP_SYS_NICE))
-- 
2.1.4

Re: [f2fs-dev] [PATCH 2/4] f2fs: build stat_info before orphan inode recovery

[Chao Yu]

On 2017/3/8 6:13, Jaegeuk Kim wrote:
> f2fs_sync_fs() -> write_checkpoint() calls stat_inc_cp_count(sbi->stat_info),
> which needs stat_info allocation.
> Otherwise, we can hit:
> 
> [254042.598623]  ? count_shadow_nodes+0xa0/0xa0
> [254042.598633]  f2fs_sync_fs+0x65/0xd0 [f2fs]
> [254042.598645]  f2fs_balance_fs_bg+0xe4/0x1c0 [f2fs]
> [254042.598657]  f2fs_write_node_pages+0x34/0x1a0 [f2fs]
> [254042.598664]  ? pagevec_lookup_entries+0x1e/0x30
> [254042.598673]  do_writepages+0x1e/0x30
> [254042.598682]  __writeback_single_inode+0x45/0x330
> [254042.598688]  writeback_single_inode+0xd7/0x190
> [254042.598694]  write_inode_now+0x86/0xa0
> [254042.598699]  iput+0x122/0x200
> [254042.598709]  f2fs_fill_super+0xd4a/0x14d0 [f2fs]
> [254042.598717]  mount_bdev+0x184/0x1c0
> [254042.598934]  ? f2fs_commit_super+0x100/0x100 [f2fs]
> [254042.599142]  f2fs_mount+0x15/0x20 [f2fs]
> [254042.599349]  mount_fs+0x39/0x160
> [254042.599554]  ? __alloc_percpu+0x15/0x20
> [254042.599759]  vfs_kern_mount+0x67/0x110
> [254042.599972]  do_mount+0x1bb/0xc80
> [254042.600175]  ? memdup_user+0x42/0x60
> [254042.600380]  SyS_mount+0x83/0xd0
> [254042.600583]  entry_SYSCALL_64_fastpath+0x1e/0xad
> 
> Signed-off-by: Jaegeuk Kim 
> ---
>  fs/f2fs/super.c | 10 +-
>  1 file changed, 5 insertions(+), 5 deletions(-)
> 
> diff --git a/fs/f2fs/super.c b/fs/f2fs/super.c
> index 96fe8ed73100..cfb40d3fd875 100644
> --- a/fs/f2fs/super.c
> +++ b/fs/f2fs/super.c
> @@ -2022,6 +2022,10 @@ static int f2fs_fill_super(struct super_block *sb, 
> void *data, int silent)
>  
>   f2fs_join_shrinker(sbi);
>  
> + err = f2fs_build_stats(sbi);
> + if (err)
> + goto free_nm;

Both node_inode and shrinker need to be released and detached.

How about relocate f2fs_build_stats in front of build_segment_manager?

Thanks,

> +
>   /* if there are nt orphan nodes free them */
>   err = recover_orphan_inodes(sbi);
>   if (err)
> @@ -2046,10 +2050,6 @@ static int f2fs_fill_super(struct super_block *sb, 
> void *data, int silent)
>   goto free_root_inode;
>   }
>  
> - err = f2fs_build_stats(sbi);
> - if (err)
> - goto free_root_inode;
> -
>   if (f2fs_proc_root)
>   sbi->s_proc = proc_mkdir(sb->s_id, f2fs_proc_root);
>  
> @@ -2143,7 +2143,6 @@ static int f2fs_fill_super(struct super_block *sb, void 
> *data, int silent)
>   remove_proc_entry("segment_bits", sbi->s_proc);
>   remove_proc_entry(sb->s_id, f2fs_proc_root);
>   }
> - f2fs_destroy_stats(sbi);
>  free_root_inode:
>   dput(sb->s_root);
>   sb->s_root = NULL;
> @@ -2161,6 +2160,7 @@ static int f2fs_fill_super(struct super_block *sb, void 
> *data, int silent)
>   truncate_inode_pages_final(META_MAPPING(sbi));
>   iput(sbi->node_inode);
>   mutex_unlock(&sbi->umount_mutex);
> + f2fs_destroy_stats(sbi);
>  free_nm:
>   destroy_node_manager(sbi);
>  free_sm:
> 

Re: [PATCH] mm,hugetlb: compute page_size_log properly

[Michal Hocko]

On Wed 08-03-17 09:06:01, Davidlohr Bueso wrote:
> The SHM_HUGE_* stuff  was introduced in:
> 
>42d7395feb5 (mm: support more pagesizes for MAP_HUGETLB/SHM_HUGETLB)
> 
> It unnecessarily adds another layer, specific to sysv shm, without
> anything special about it: the macros are identical to the MAP_HUGE_*
> stuff, which in turn does correctly describe the hugepage subsystem.
> 
> One example of the problems with extra layers what this patch fixes:
> mmap_pgoff() should never be using SHM_HUGE_* logic. This was
> introduced by:
> 
>091d0d55b28 (shm: fix null pointer deref when userspace specifies invalid 
> hugepage size)
> 
> It is obviously harmless but lets just rip out the whole thing --
> the shmget.2 manpage will need updating, as it should not be
> describing kernel internals.

Yes, I agree the additional layer just adds confusion and as it turned
out it is error prone. As this has never been exported to the userspace
properly without anybody complaining I would strongly suspect it is not
really needed so just get rid of it.

> Signed-off-by: Davidlohr Bueso 

Acked-by: Michal Hocko 

Thanks!

> ---
>  include/linux/shm.h| 13 -
>  ipc/shm.c  |  6 +++---
>  mm/mmap.c  |  2 +-
>  tools/testing/selftests/vm/thuge-gen.c |  8 +---
>  4 files changed, 5 insertions(+), 24 deletions(-)
> 
> diff --git a/include/linux/shm.h b/include/linux/shm.h
> index 429c1995d756..98fc25f9db8a 100644
> --- a/include/linux/shm.h
> +++ b/include/linux/shm.h
> @@ -31,19 +31,6 @@ struct shmid_kernel /* private to the kernel */
>  
>  /* Bits [26:31] are reserved */
>  
> -/*
> - * When SHM_HUGETLB is set bits [26:31] encode the log2 of the huge page 
> size.
> - * This gives us 6 bits, which is enough until someone invents 128 bit 
> address
> - * spaces.
> - *
> - * Assume these are all power of twos.
> - * When 0 use the default page size.
> - */
> -#define SHM_HUGE_SHIFT  26
> -#define SHM_HUGE_MASK   0x3f
> -#define SHM_HUGE_2MB(21 << SHM_HUGE_SHIFT)
> -#define SHM_HUGE_1GB(30 << SHM_HUGE_SHIFT)
> -
>  #ifdef CONFIG_SYSVIPC
>  long do_shmat(int shmid, char __user *shmaddr, int shmflg, unsigned long 
> *addr,
> unsigned long shmlba);
> diff --git a/ipc/shm.c b/ipc/shm.c
> index 7e199fa1960f..f21a2338ee39 100644
> --- a/ipc/shm.c
> +++ b/ipc/shm.c
> @@ -491,8 +491,8 @@ static int newseg(struct ipc_namespace *ns, struct 
> ipc_params *params)
>  
>   sprintf (name, "SYSV%08x", key);
>   if (shmflg & SHM_HUGETLB) {
> - struct hstate *hs = hstate_sizelog((shmflg >> SHM_HUGE_SHIFT)
> - & SHM_HUGE_MASK);
> + struct hstate *hs = hstate_sizelog((shmflg >> MAP_HUGE_SHIFT)
> +& MAP_HUGE_MASK);
>   size_t hugesize;
>  
>   if (!hs) {
> @@ -506,7 +506,7 @@ static int newseg(struct ipc_namespace *ns, struct 
> ipc_params *params)
>   acctflag = VM_NORESERVE;
>   file = hugetlb_file_setup(name, hugesize, acctflag,
> &shp->mlock_user, HUGETLB_SHMFS_INODE,
> - (shmflg >> SHM_HUGE_SHIFT) & SHM_HUGE_MASK);
> + (shmflg >> MAP_HUGE_SHIFT) & MAP_HUGE_MASK);
>   } else {
>   /*
>* Do not allow no accounting for OVERCOMMIT_NEVER, even
> diff --git a/mm/mmap.c b/mm/mmap.c
> index 0718c175db8f..a1c4cefc5a38 100644
> --- a/mm/mmap.c
> +++ b/mm/mmap.c
> @@ -1369,7 +1369,7 @@ SYSCALL_DEFINE6(mmap_pgoff, unsigned long, addr, 
> unsigned long, len,
>   } else if (flags & MAP_HUGETLB) {
>   struct user_struct *user = NULL;
>   struct hstate *hs = hstate_sizelog((flags >> MAP_HUGE_SHIFT) &
> -SHM_HUGE_MASK);
> +MAP_HUGE_MASK);
>  
>   if (!hs)
>   return -EINVAL;
> diff --git a/tools/testing/selftests/vm/thuge-gen.c 
> b/tools/testing/selftests/vm/thuge-gen.c
> index c87957295f74..4479015ec96a 100644
> --- a/tools/testing/selftests/vm/thuge-gen.c
> +++ b/tools/testing/selftests/vm/thuge-gen.c
> @@ -32,12 +32,6 @@
>  #define MAP_HUGE_MASK   0x3f
>  #define MAP_HUGETLB  0x4
>  
> -#define SHM_HUGETLB 04000   /* segment will use huge TLB pages */
> -#define SHM_HUGE_SHIFT  26
> -#define SHM_HUGE_MASK   0x3f
> -#define SHM_HUGE_2MB(21 << SHM_HUGE_SHIFT)
> -#define SHM_HUGE_1GB(30 << SHM_HUGE_SHIFT)
> -
>  #define NUM_PAGESIZES   5
>  
>  #define NUM_PAGES 4
> @@ -243,7 +237,7 @@ int main(void)
>  
>   for (i = 0; i < num_page_sizes; i++) {
>   unsigned long ps = page_sizes[i];
> - int arg = ilog2(ps) << SHM_HUGE_SHIFT;
> + int arg = ilog2(ps) << MAP_HUGE_SHIFT;
>   printf("Testing %luMB shmget with shift %x\n", ps >> 20, arg)

Re: [PATCH 3/3] Documentation: cpu-freq: cpu-drivers: Fix repetition of word 'to'

[Viresh Kumar]

On Thu, Mar 9, 2017 at 12:24 PM, sayli karnik  wrote:
> The patch replaces 'to to' with 'to' in the documentation.
>
> Signed-off-by: sayli karnik 
> ---
>  Documentation/cpu-freq/cpu-drivers.txt | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)

Acked-by: Viresh Kumar 

Re: [PATCH] staging, android: remove lowmemory killer from the tree

[Michal Hocko]

Greg, do you see any obstacle to have this merged. The discussion so far
shown that a) vendors are not using the code as is b) there seems to be
an agreement that something else than we have in the kernel is really
needed.

On Wed 22-02-17 13:01:21, Michal Hocko wrote:
> From: Michal Hocko 
> 
> Lowmemory killer is sitting in the staging tree since 2008 without any
> serious interest for fixing issues brought up by the MM folks. The main
> objection is that the implementation is basically broken by design:
>   - it hooks into slab shrinker API which is not suitable for this
> purpose. lowmem_count implementation just shows this nicely.
> There is no scaling based on the memory pressure and no
> feedback to the generic shrinker infrastructure.
> Moreover lowmem_scan is called way too often for the heavy
> work it performs.
>   - it is not reclaim context aware - no NUMA and/or memcg
> awareness.
> 
> As the code stands right now it just adds a maintenance overhead when
> core MM changes have to update lowmemorykiller.c as well. It also seems
> that the alternative LMK implementation will be solely in the userspace
> so this code has no perspective it seems. The staging tree is supposed
> to be for a code which needs to be put in shape before it can be merged
> which is not the case here obviously.
> 
> Signed-off-by: Michal Hocko 
> ---
>  drivers/staging/android/Kconfig   |  10 --
>  drivers/staging/android/Makefile  |   1 -
>  drivers/staging/android/lowmemorykiller.c | 212 
> --
>  include/linux/sched.h |   4 -
>  4 files changed, 227 deletions(-)
>  delete mode 100644 drivers/staging/android/lowmemorykiller.c
> 
> diff --git a/drivers/staging/android/Kconfig b/drivers/staging/android/Kconfig
> index 6c00d6f765c6..71a50b99caff 100644
> --- a/drivers/staging/android/Kconfig
> +++ b/drivers/staging/android/Kconfig
> @@ -14,16 +14,6 @@ config ASHMEM
> It is, in theory, a good memory allocator for low-memory devices,
> because it can discard shared memory units when under memory pressure.
>  
> -config ANDROID_LOW_MEMORY_KILLER
> - bool "Android Low Memory Killer"
> - ---help---
> -   Registers processes to be killed when low memory conditions, this is 
> useful
> -   as there is no particular swap space on android.
> -
> -   The registered process will kill according to the priorities in 
> android init
> -   scripts (/init.rc), and it defines priority values with minimum free 
> memory size
> -   for each priority.
> -
>  source "drivers/staging/android/ion/Kconfig"
>  
>  endif # if ANDROID
> diff --git a/drivers/staging/android/Makefile 
> b/drivers/staging/android/Makefile
> index 7ed1be798909..7cf1564a49a5 100644
> --- a/drivers/staging/android/Makefile
> +++ b/drivers/staging/android/Makefile
> @@ -3,4 +3,3 @@ ccflags-y += -I$(src) # needed for trace 
> events
>  obj-y+= ion/
>  
>  obj-$(CONFIG_ASHMEM) += ashmem.o
> -obj-$(CONFIG_ANDROID_LOW_MEMORY_KILLER)  += lowmemorykiller.o
> diff --git a/drivers/staging/android/lowmemorykiller.c 
> b/drivers/staging/android/lowmemorykiller.c
> deleted file mode 100644
> index ec3b66561412..
> --- a/drivers/staging/android/lowmemorykiller.c
> +++ /dev/null
> @@ -1,212 +0,0 @@
> -/* drivers/misc/lowmemorykiller.c
> - *
> - * The lowmemorykiller driver lets user-space specify a set of memory 
> thresholds
> - * where processes with a range of oom_score_adj values will get killed. 
> Specify
> - * the minimum oom_score_adj values in
> - * /sys/module/lowmemorykiller/parameters/adj and the number of free pages in
> - * /sys/module/lowmemorykiller/parameters/minfree. Both files take a comma
> - * separated list of numbers in ascending order.
> - *
> - * For example, write "0,8" to /sys/module/lowmemorykiller/parameters/adj and
> - * "1024,4096" to /sys/module/lowmemorykiller/parameters/minfree to kill
> - * processes with a oom_score_adj value of 8 or higher when the free memory
> - * drops below 4096 pages and kill processes with a oom_score_adj value of 0 
> or
> - * higher when the free memory drops below 1024 pages.
> - *
> - * The driver considers memory used for caches to be free, but if a large
> - * percentage of the cached memory is locked this can be very inaccurate
> - * and processes may not get killed until the normal oom killer is triggered.
> - *
> - * Copyright (C) 2007-2008 Google, Inc.
> - *
> - * This software is licensed under the terms of the GNU General Public
> - * License version 2, as published by the Free Software Foundation, and
> - * may be copied, distributed, and modified under those terms.
> - *
> - * This program is distributed in the hope that it will be useful,
> - * but WITHOUT ANY WARRANTY; without even the implied warranty of
> - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. 

Re: [PATCH v2] arm64: kvm: Use has_vhe() instead of hyp_alternate_select()

[Christoffer Dall]

Hi Shanker,

On Sun, Mar 05, 2017 at 08:33:18PM -0600, Shanker Donthineni wrote:
> Now all the cpu_hwcaps features have their own static keys. We don't
> need a separate function hyp_alternate_select() to patch the vhe/nvhe
> code. We can achieve the same functionality by using has_vhe(). It
> improves the code readability, uses the jump label instructions, and
> also compiler generates the better code with a fewer instructions.
> 
> Signed-off-by: Shanker Donthineni 

I have no objections against this patch as such, but I have a number of
more substantial changes which will get rid of most of the
hyp_alternate_select later, and since there's no immediate need to merge
this patch, and there's the risk that it may slow down some things on
certain platforms with older compilers, I'd like to hold off on merging
this patch until the next merge window and revisit this issue at that
point.

Thanks,
-Christoffer

> ---
> v2: removed 'Change-Id: Ia8084189833f2081ff13c392deb5070c46a64038' from commit
> 
>  arch/arm64/kvm/hyp/debug-sr.c  | 12 ++
>  arch/arm64/kvm/hyp/switch.c| 50 
> +++---
>  arch/arm64/kvm/hyp/sysreg-sr.c | 23 +--
>  3 files changed, 43 insertions(+), 42 deletions(-)
> 
> diff --git a/arch/arm64/kvm/hyp/debug-sr.c b/arch/arm64/kvm/hyp/debug-sr.c
> index f5154ed..e5642c2 100644
> --- a/arch/arm64/kvm/hyp/debug-sr.c
> +++ b/arch/arm64/kvm/hyp/debug-sr.c
> @@ -109,9 +109,13 @@ static void __hyp_text __debug_save_spe_nvhe(u64 
> *pmscr_el1)
>   dsb(nsh);
>  }
>  
> -static hyp_alternate_select(__debug_save_spe,
> - __debug_save_spe_nvhe, __debug_save_spe_vhe,
> - ARM64_HAS_VIRT_HOST_EXTN);
> +static void __hyp_text __debug_save_spe(u64 *pmscr_el1)
> +{
> + if (has_vhe())
> + __debug_save_spe_vhe(pmscr_el1);
> + else
> + __debug_save_spe_nvhe(pmscr_el1);
> +}
>  
>  static void __hyp_text __debug_restore_spe(u64 pmscr_el1)
>  {
> @@ -180,7 +184,7 @@ void __hyp_text __debug_cond_save_host_state(struct 
> kvm_vcpu *vcpu)
>  
>   __debug_save_state(vcpu, &vcpu->arch.host_debug_state.regs,
>  kern_hyp_va(vcpu->arch.host_cpu_context));
> - __debug_save_spe()(&vcpu->arch.host_debug_state.pmscr_el1);
> + __debug_save_spe(&vcpu->arch.host_debug_state.pmscr_el1);
>  }
>  
>  void __hyp_text __debug_cond_restore_host_state(struct kvm_vcpu *vcpu)
> diff --git a/arch/arm64/kvm/hyp/switch.c b/arch/arm64/kvm/hyp/switch.c
> index aede165..c5c77b8 100644
> --- a/arch/arm64/kvm/hyp/switch.c
> +++ b/arch/arm64/kvm/hyp/switch.c
> @@ -33,13 +33,9 @@ static bool __hyp_text __fpsimd_enabled_vhe(void)
>   return !!(read_sysreg(cpacr_el1) & CPACR_EL1_FPEN);
>  }
>  
> -static hyp_alternate_select(__fpsimd_is_enabled,
> - __fpsimd_enabled_nvhe, __fpsimd_enabled_vhe,
> - ARM64_HAS_VIRT_HOST_EXTN);
> -
>  bool __hyp_text __fpsimd_enabled(void)
>  {
> - return __fpsimd_is_enabled()();
> + return has_vhe() ? __fpsimd_enabled_vhe() : __fpsimd_enabled_nvhe();
>  }
>  
>  static void __hyp_text __activate_traps_vhe(void)
> @@ -63,9 +59,10 @@ static void __hyp_text __activate_traps_nvhe(void)
>   write_sysreg(val, cptr_el2);
>  }
>  
> -static hyp_alternate_select(__activate_traps_arch,
> - __activate_traps_nvhe, __activate_traps_vhe,
> - ARM64_HAS_VIRT_HOST_EXTN);
> +static void __hyp_text __activate_traps_arch(void)
> +{
> + has_vhe() ? __activate_traps_vhe() : __activate_traps_nvhe();
> +}
>  
>  static void __hyp_text __activate_traps(struct kvm_vcpu *vcpu)
>  {
> @@ -97,7 +94,7 @@ static void __hyp_text __activate_traps(struct kvm_vcpu 
> *vcpu)
>   write_sysreg(0, pmselr_el0);
>   write_sysreg(ARMV8_PMU_USERENR_MASK, pmuserenr_el0);
>   write_sysreg(vcpu->arch.mdcr_el2, mdcr_el2);
> - __activate_traps_arch()();
> + __activate_traps_arch();
>  }
>  
>  static void __hyp_text __deactivate_traps_vhe(void)
> @@ -127,9 +124,10 @@ static void __hyp_text __deactivate_traps_nvhe(void)
>   write_sysreg(CPTR_EL2_DEFAULT, cptr_el2);
>  }
>  
> -static hyp_alternate_select(__deactivate_traps_arch,
> - __deactivate_traps_nvhe, __deactivate_traps_vhe,
> - ARM64_HAS_VIRT_HOST_EXTN);
> +static void __hyp_text __deactivate_traps_arch(void)
> +{
> + has_vhe() ? __deactivate_traps_vhe() : __deactivate_traps_nvhe();
> +}
>  
>  static void __hyp_text __deactivate_traps(struct kvm_vcpu *vcpu)
>  {
> @@ -142,7 +140,7 @@ static void __hyp_text __deactivate_traps(struct kvm_vcpu 
> *vcpu)
>   if (vcpu->arch.hcr_el2 & HCR_VSE)
>   vcpu->arch.hcr_el2 = read_sysreg(hcr_el2);
>  
> - __deactivate_traps_arch()();
> + __deactivate_traps_arch();
>   write_sysreg(0, hstr_el2);
>   write_sysreg(0, pmuserenr_el0);
>  }
> @@ -183,20 +181,14 @@ static void __hyp_te

Re: [RFC PATCH 3/4] xfs: map KM_MAYFAIL to __GFP_RETRY_MAYFAIL

[Michal Hocko]

On Wed 08-03-17 07:06:59, Christoph Hellwig wrote:
> On Tue, Mar 07, 2017 at 04:48:42PM +0100, Michal Hocko wrote:
> > From: Michal Hocko 
> > 
> > KM_MAYFAIL didn't have any suitable GFP_FOO counterpart until recently
> > so it relied on the default page allocator behavior for the given set
> > of flags. This means that small allocations actually never failed.
> > 
> > Now that we have __GFP_RETRY_MAYFAIL flag which works independently on the
> > allocation request size we can map KM_MAYFAIL to it. The allocator will
> > try as hard as it can to fulfill the request but fails eventually if
> > the progress cannot be made.
> 
> I don't think we really need this - KM_MAYFAIL is basically just
> a flag to not require the retry loop around kmalloc for those places
> in XFS that can deal with allocation failures.  But if the default
> behavior is to not fail we'll happily take that.

Does that mean that you are happy to go OOM and trigger the OOM killer
even when you know that the failure can be handled gracefully?

-- 
Michal Hocko
SUSE Labs

Re: [PATCH 0/3] Add RTC support on STM32F746

[Alexandre Torgue]

Hi Amélie,

On 01/19/2017 02:45 PM, Amelie Delaunay wrote:

This patchset enables STM32 RTC on STM32F746 MCU.

Amelie Delaunay (3):
  ARM: dts: stm32: set HSE_RTC clock frequency to 1 MHz on stm32f746
  ARM: dts: stm32: Add RTC support for STM32F746 MCU
  ARM: dts: stm32: enable RTC on stm32746g-eval



Can you please rebase this series on 4.11-rc1 and resend ?

Thanks in advance



 arch/arm/boot/dts/stm32746g-eval.dts |  4 
 arch/arm/boot/dts/stm32f746.dtsi | 16 
 2 files changed, 20 insertions(+)

Re: [Question] devm_kmalloc() for DMA ?

[Russell King - ARM Linux]

On Thu, Mar 09, 2017 at 12:25:07PM +0900, Masahiro Yamada wrote:
> (c) Use kmalloc() and kfree().   (be careful for memory leak)

This is quite simple.  For the first one, it doesn't seem that it's
DMA'd into, so there's no need to use GFP_DMA.

-   /* allocate a temporary buffer for nand_scan_ident() */
-   denali->buf.buf = devm_kzalloc(denali->dev, PAGE_SIZE,
-   GFP_DMA | GFP_KERNEL);
-   if (!denali->buf.buf)
-   return -ENOMEM;

...

+   denali->buf.buf = kzalloc(PAGE_SIZE, GFP_KERNEL);
+   if (!denali->buf.buf)
+   return -ENOMEM;
+
/*
 * scan for NAND devices attached to the controller
 * this is the first stage in a two step process to register
 * with the nand subsystem
 */
ret = nand_scan_ident(mtd, denali->max_banks, NULL);
+   kfree(denali->buf.buf);
+
if (ret)
goto failed_req_irq;

-   /* allocate the right size buffer now */
-   devm_kfree(denali->dev, denali->buf.buf);

For the second one, I think the first thing to do is to move the
dma_set_mask() to the very beginning of the probe function - if that
fails, then we can't use DMA, and it's not something that requires
any cleanup.

With that gone, convert the other devm_kzalloc() there for buf.buf to
kzalloc(), and ensure that it's appropriately freed.  Note that this
driver is _already_ buggy in that if:

} else if (mtd->oobsize < (denali->bbtskipbytes +
ECC_8BITS * (mtd->writesize /
ECC_SECTOR_SIZE))) {
pr_err("Your NAND chip OOB is not large enough to contain 8bit 
ECC correction codes");
goto failed_req_irq;

fails, or these:

ret = nand_scan_tail(mtd);
if (ret)
goto failed_req_irq;

ret = mtd_device_register(mtd, NULL, 0);
if (ret) {
dev_err(denali->dev, "Failed to register MTD: %d\n", ret);
goto failed_req_irq;
}

it doesn't unmap the buffer.  So, the driver is already broken.

-- 
RMK's Patch system: http://www.armlinux.org.uk/developer/patches/
FTTC broadband for 0.8mile line: currently at 9.6Mbps down 400kbps up
according to speedtest.net.

Re: [PATCH] mm, vmscan: do not loop on too_many_isolated for ever

[Michal Hocko]

On Wed 08-03-17 10:54:57, Rik van Riel wrote:
> On Wed, 2017-03-08 at 10:21 +0100, Michal Hocko wrote:
> 
> > > Could that create problems if we have many concurrent
> > > reclaimers?
> > 
> > As the changelog mentions it might cause a premature oom killer
> > invocation theoretically. We could easily see that from the oom
> > report
> > by checking isolated counters. My testing didn't trigger that though
> > and I was hammering the page allocator path from many threads.
> > 
> > I suspect some artificial tests can trigger that, I am not so sure
> > about
> > reasonabel workloads. If we see this happening though then the fix
> > would
> > be to resurrect my previous attempt to track NR_ISOLATED* per zone
> > and
> > use them in the allocator retry logic.
> 
> I am not sure the workload in question is "artificial".
> A heavily forking (or multi-threaded) server running out
> of physical memory could easily get hundreds of tasks
> doing direct reclaim simultaneously.

Yes, some of my OOM tests (fork many short lived processes while there
is a strong memory pressure and a lot of IO going on) are doing this and
I haven't hit a premature OOM yet. It is hard to tune those tests for almost
OOM but not yet there, though. Usually you either find a steady state or
really run out of memory.

> In fact, false OOM kills with that kind of workload is
> how we ended up getting the "too many isolated" logic
> in the first place.

Right, but the retry logic was considerably different than what we
have these days. should_reclaim_retry considers amount of reclaimable
memory. As I've said earlier if we see a report where the oom hits
prematurely with many NR_ISOLATED* we know how to fix that.

> I am perfectly fine with moving the retry logic up like
> you did, but think it may make sense to check the number
> of reclaimable pages if we have too many isolated pages,
> instead of risking a too-early OOM kill.

Actually that was my initial attempt but for that we would need per-zone
NR_ISOLATED* counters but Mel was against and wanted to start with
simpler approach if it works reasonably well which it seems it does from
my experience so far (but the reallity can surprise as I've seen so many
times already).
-- 
Michal Hocko
SUSE Labs

Re: [PATCH 0/3] mm/fs: get PG_error out of the writeback reporting business

[Jan Kara]

On Wed 08-03-17 21:57:25, Ted Tso wrote:
> On Tue, Mar 07, 2017 at 11:26:22AM +0100, Jan Kara wrote:
> > On a more general note (DAX is actually fine here), I find the current
> > practice of clearing page dirty bits on error and reporting it just once
> > problematic. It keeps the system running but data is lost and possibly
> > without getting the error anywhere where it is useful. We get away with
> > this because it is a rare event but it seems like a problematic behavior.
> > But this is more for the discussion at LSF.
> 
> I'm actually running into this in the last day or two because some MM
> folks at $WORK have been trying to push hard for GFP_NOFS removal in
> ext4 (at least when we are holding some mutex/semaphore like
> i_data_sem) because otherwise it's possible for the OOM killer to be
> unable to kill processes because they are holding on to locks that
> ext4 is holding.
> 
> I've done some initial investigation, and while it's not that hard to
> remove GFP_NOFS from certain parts of the writepages() codepath (which
> is where we had been are running into problems), a really, REALLY big
> problem is if any_filesystem->writepages() returns ENOMEM, it causes
> silent data loss, because the pages are marked clean, and so data
> written using buffered writeback goes *poof*.
> 
> I confirmed this by creating a test kernel with a simple patch such
> that if the ext4 file system is mounted with -o debug, there was a 1
> in 16 chance that ext4_writepages will immediately return with ENOMEM
> (and printk the inode number, so I knew which inodes had gotten the
> ENOMEM treatment).  The result was **NOT** pretty.
> 
> What I think we should strongly consider is at the very least, special
> case ENOMEM being returned by writepages() during background
> writeback, and *not* mark the pages clean, and make sure the inode
> stays on the dirty inode list, so we can retry the write later.  This
> is especially important since the process that issued the write may
> have gone away, so there might not even be a userspace process to
> complain to.  By converting certain page allocations (most notably in
> ext4_mb_load_buddy) from GFP_NOFS to GFP_KMALLOC, this allows us to
> release the i_data_sem lock and return an error.  This should allow
> allow the OOM killer to do its dirty deed, and hopefully we can retry
> the writepages() for that inode later.

Yeah, so if we can hope the error is transient, keeping pages dirty and
retrying the write is definitely better option. For start we can say that
ENOMEM, EINTR, EAGAIN, ENOSPC errors are transient, anything else means
there's no hope of getting data to disk and so we just discard them. It
will be somewhat rough distinction but probably better than what we have
now.

Honza
-- 
Jan Kara 
SUSE Labs, CR

Re: [PATCH] usb: host: xhci-plat: Fix timeout on removal of hot pluggable xhci controllers

[Mathias Nyman]

On 08.03.2017 21:49, Guenter Roeck wrote:

Upstream commit 98d74f9ceaef ("xhci: fix 10 second timeout on removal of
PCI hotpluggable xhci controllers") fixes a problem with hot pluggable PCI
xhci controllers which can result in excessive timeouts, to the point where
the system reports a deadlock.

The same problem is seen with hot pluggable xhci controllers using the
xhci-plat driver, such as the driver used for Type-C ports on rk3399.
Similar to hot-pluggable PCI controllers, the driver for this chip
removes the xhci controller from the system when the Type-C cable is
disconnected.

The solution for PCI devices works just as well for non-PCI devices
and avoids the problem.

Signed-off-by: Guenter Roeck 
---



Thanks, adding to queue

-Mathias

Re: cgroup: WARNING in cgroup_kill_sb

[Zefan Li]

On 2017/3/3 3:15, Dmitry Vyukov wrote:
> Hello,
> 
> The following program triggers WARNING in cgroup_kill_sb:
> https://gist.githubusercontent.com/dvyukov/47a37d3b899ece1f57e512dc6c90bca6/raw/250894f3d6e2954eed01bac39e4c3b7ec59a9c31/gistfile1.txt
> 
> 
> WARNING: CPU: 2 PID: 3092 at lib/percpu-refcount.c:317
> percpu_ref_kill_and_confirm+0x3ff/0x4f0 lib/percpu-refcount.c:316
> percpu_ref_kill_and_confirm called more than once on css_release!
> Kernel panic - not syncing: panic_on_warn set ...
> 
> CPU: 2 PID: 3092 Comm: a.out Not tainted 4.10.0+ #260
> Hardware name: QEMU Standard PC (i440FX + PIIX, 1996), BIOS Bochs 01/01/2011
> Call Trace:
>  __dump_stack lib/dump_stack.c:15 [inline]
>  dump_stack+0x2ee/0x3ef lib/dump_stack.c:51
>  panic+0x1fb/0x412 kernel/panic.c:179
>  __warn+0x1c4/0x1e0 kernel/panic.c:540
>  warn_slowpath_fmt+0xc5/0x100 kernel/panic.c:563
>  percpu_ref_kill_and_confirm+0x3ff/0x4f0 lib/percpu-refcount.c:316
>  percpu_ref_kill include/linux/percpu-refcount.h:119 [inline]
>  cgroup_kill_sb+0x188/0x530 kernel/cgroup/cgroup.c:1833
>  deactivate_locked_super+0x88/0xd0 fs/super.c:309
>  deactivate_super+0x155/0x1b0 fs/super.c:340
>  cleanup_mnt+0xb2/0x160 fs/namespace.c:1112
>  __cleanup_mnt+0x16/0x20 fs/namespace.c:1119
>  task_work_run+0x18a/0x260 kernel/task_work.c:116
>  tracehook_notify_resume include/linux/tracehook.h:191 [inline]
>  exit_to_usermode_loop+0x23b/0x2a0 arch/x86/entry/common.c:160
>  prepare_exit_to_usermode arch/x86/entry/common.c:190 [inline]
>  syscall_return_slowpath+0x4d3/0x570 arch/x86/entry/common.c:259
>  entry_SYSCALL_64_fastpath+0xc0/0xc2
> RIP: 0033:0x440b39
> RSP: 002b:7f3e8bd0cdb8 EFLAGS: 0202 ORIG_RAX: 00a5
> RAX: ffec RBX:  RCX: 00440b39
> RDX: 004a0f3b RSI: 004a0f34 RDI: 004a0f34
> RBP: 7f3e8bd0cdd0 R08:  R09: 
> R10: 0005 R11: 0202 R12: 
> R13:  R14: 7f3e8bd0d9c0 R15: 7f3e8bd0d700
> 
> On commit 4977ab6e92e267afe9d8f78438c3db330ca8434c
> .

could you share your kernel config? I can't reproduce this bug.

[PATCH v1 0/4] rk808: Add RK805 support

[Elaine Zhang]

Elaine Zhang (4):
  mfd: rk808: fix up the chip id get failed
  linux: mfd: rk808: add rk805 regs addr and ID
  regulator: rk808: Add regulator driver for RK805
  mfd: rk808: Add RK805 support

 drivers/clk/Kconfig |   4 +-
 drivers/mfd/Kconfig |   4 +-
 drivers/mfd/rk808.c | 130 ++--
 drivers/regulator/Kconfig   |   4 +-
 drivers/regulator/rk808-regulator.c |  66 ++
 drivers/rtc/Kconfig |   4 +-
 include/linux/mfd/rk808.h   |  92 +
 7 files changed, 290 insertions(+), 14 deletions(-)

-- 
1.9.1

RE: [PATCH 22/29] drivers, scsi: convert iscsi_task.refcount from atomic_t to refcount_t

[Reshetova, Elena]

> On 03/09/2017 08:18 AM, Reshetova, Elena wrote:
> >> On Mon, Mar 06, 2017 at 04:21:09PM +0200, Elena Reshetova wrote:
> >>> refcount_t type and corresponding API should be
> >>> used instead of atomic_t when the variable is used as
> >>> a reference counter. This allows to avoid accidental
> >>> refcounter overflows that might lead to use-after-free
> >>> situations.
> >>>
> >>> Signed-off-by: Elena Reshetova 
> >>> Signed-off-by: Hans Liljestrand 
> >>> Signed-off-by: Kees Cook 
> >>> Signed-off-by: David Windsor 
> >>
> >> This looks OK to me.
> >>
> >> Acked-by: Chris Leech 
> >
> > Thank you for review! Do you have a tree that can take this change?
> 
> Hi Elena,
> 
> iscsi like fcoe should go via the SCSI tree.

Thanks Johannes! Should I resend with "Acked-by" added in order for it to be 
picked up? 

Best Regards,
Elena.


> 
> Byte,
>   Johannes
> 
> --
> Johannes Thumshirn  Storage
> jthumsh...@suse.de+49 911 74053 689
> SUSE LINUX GmbH, Maxfeldstr. 5, 90409 Nürnberg
> GF: Felix Imendörffer, Jane Smithard, Graham Norton
> HRB 21284 (AG Nürnberg)
> Key fingerprint = EC38 9CAB C2C4 F25D 8600 D0D0 0393 969D 2D76 0850

[PATCH RESEND 4/4] mfd: arizona: Use regmap_read_poll_timeout instead of hard coding it

[Charles Keepax]

arizona_poll_reg essentially hard-codes regmap_read_poll_timeout, this
patch updates the implementation to use regmap_read_poll_timeout. We
still keep arizona_poll_reg around as regmap_read_poll_timeout is a
macro so rather than expand this for each caller keep it wrapped in
arizona_poll_reg.

Whilst we are doing this make the timeouts a little more generous as the
previous system had a bit more slack as it was done as a delay per
iteration of the loop whereas regmap_read_poll_timeout compares ktime's.

Signed-off-by: Charles Keepax 
---
 drivers/mfd/arizona-core.c | 38 ++
 1 file changed, 14 insertions(+), 24 deletions(-)

diff --git a/drivers/mfd/arizona-core.c b/drivers/mfd/arizona-core.c
index 09d48ed..75488e6 100644
--- a/drivers/mfd/arizona-core.c
+++ b/drivers/mfd/arizona-core.c
@@ -235,35 +235,25 @@ static irqreturn_t arizona_overclocked(int irq, void 
*data)
return IRQ_HANDLED;
 }
 
-#define ARIZONA_REG_POLL_DELAY_MS 5
-#define ARIZONA_REG_POLL_DELAY_US (ARIZONA_REG_POLL_DELAY_MS * 1000)
+#define ARIZONA_REG_POLL_DELAY_US 7500
 
 static int arizona_poll_reg(struct arizona *arizona,
int timeout_ms, unsigned int reg,
unsigned int mask, unsigned int target)
 {
-   unsigned int npolls = (timeout_ms + ARIZONA_REG_POLL_DELAY_MS - 1) /
- ARIZONA_REG_POLL_DELAY_MS;
unsigned int val = 0;
-   int ret, i;
-
-   for (i = 0; i < npolls; i++) {
-   ret = regmap_read(arizona->regmap, reg, &val);
-   if (ret != 0) {
-   dev_err(arizona->dev, "Failed to read reg 0x%x: %d\n",
-   reg, ret);
-   continue;
-   }
-
-   if ((val & mask) == target)
-   return 0;
+   int ret;
 
-   usleep_range(ARIZONA_REG_POLL_DELAY_US,
-ARIZONA_REG_POLL_DELAY_US * 2);
-   }
+   ret = regmap_read_poll_timeout(arizona->regmap,
+  ARIZONA_INTERRUPT_RAW_STATUS_5, val,
+  ((val & mask) == target),
+  ARIZONA_REG_POLL_DELAY_US,
+  timeout_ms * 1000);
+   if (ret)
+   dev_err(arizona->dev, "Polling reg 0x%x timed out: %x\n",
+   reg, val);
 
-   dev_err(arizona->dev, "Polling reg 0x%x timed out: %x\n", reg, val);
-   return -ETIMEDOUT;
+   return ret;
 }
 
 static int arizona_wait_for_boot(struct arizona *arizona)
@@ -275,7 +265,7 @@ static int arizona_wait_for_boot(struct arizona *arizona)
 * we won't race with the interrupt handler as it'll be blocked on
 * runtime resume.
 */
-   ret = arizona_poll_reg(arizona, 25, ARIZONA_INTERRUPT_RAW_STATUS_5,
+   ret = arizona_poll_reg(arizona, 30, ARIZONA_INTERRUPT_RAW_STATUS_5,
   ARIZONA_BOOT_DONE_STS, ARIZONA_BOOT_DONE_STS);
 
if (!ret)
@@ -345,7 +335,7 @@ static int arizona_enable_freerun_sysclk(struct arizona 
*arizona,
ret);
return ret;
}
-   ret = arizona_poll_reg(arizona, 125, ARIZONA_INTERRUPT_RAW_STATUS_5,
+   ret = arizona_poll_reg(arizona, 180, ARIZONA_INTERRUPT_RAW_STATUS_5,
   ARIZONA_FLL1_CLOCK_OK_STS,
   ARIZONA_FLL1_CLOCK_OK_STS);
if (ret)
@@ -409,7 +399,7 @@ static int wm5102_apply_hardware_patch(struct arizona 
*arizona)
goto err;
}
 
-   ret = arizona_poll_reg(arizona, 25, ARIZONA_WRITE_SEQUENCER_CTRL_1,
+   ret = arizona_poll_reg(arizona, 30, ARIZONA_WRITE_SEQUENCER_CTRL_1,
   ARIZONA_WSEQ_BUSY, 0);
if (ret)
regmap_write(arizona->regmap, ARIZONA_WRITE_SEQUENCER_CTRL_0,
-- 
2.1.4

[PATCH v1 1/4] mfd: rk808: fix up the chip id get failed

[Elaine Zhang]

the rk8xx chip id is:
((MSB << 8) | LSB) & 0xfff0

Signed-off-by: Elaine Zhang 
---
 drivers/mfd/rk808.c   | 21 +++--
 include/linux/mfd/rk808.h |  1 +
 2 files changed, 16 insertions(+), 6 deletions(-)

diff --git a/drivers/mfd/rk808.c b/drivers/mfd/rk808.c
index fd087cbb0bde..3334a2a7f3fb 100644
--- a/drivers/mfd/rk808.c
+++ b/drivers/mfd/rk808.c
@@ -325,7 +325,7 @@ static int rk808_probe(struct i2c_client *client,
void (*pm_pwroff_fn)(void);
int nr_pre_init_regs;
int nr_cells;
-   int pm_off = 0;
+   int pm_off = 0, msb, lsb;
int ret;
int i;
 
@@ -333,14 +333,23 @@ static int rk808_probe(struct i2c_client *client,
if (!rk808)
return -ENOMEM;
 
-   rk808->variant = i2c_smbus_read_word_data(client, RK808_ID_MSB);
-   if (rk808->variant < 0) {
-   dev_err(&client->dev, "Failed to read the chip id at 0x%02x\n",
+   /* read Chip variant */
+   msb = i2c_smbus_read_byte_data(client, RK808_ID_MSB);
+   if (msb < 0) {
+   dev_err(&client->dev, "failed to read the chip id at 0x%x\n",
RK808_ID_MSB);
-   return rk808->variant;
+   return msb;
}
 
-   dev_dbg(&client->dev, "Chip id: 0x%x\n", (unsigned int)rk808->variant);
+   lsb = i2c_smbus_read_byte_data(client, RK808_ID_LSB);
+   if (lsb < 0) {
+   dev_err(&client->dev, "failed to read the chip id at 0x%x\n",
+   RK808_ID_LSB);
+   return lsb;
+   }
+
+   rk808->variant = ((msb << 8) | lsb) & RK8XX_ID_MSK;
+   dev_info(&client->dev, "Chip id: 0x%x\n", (unsigned int)rk808->variant);
 
switch (rk808->variant) {
case RK808_ID:
diff --git a/include/linux/mfd/rk808.h b/include/linux/mfd/rk808.h
index 83701ef7d3c7..54feb140c210 100644
--- a/include/linux/mfd/rk808.h
+++ b/include/linux/mfd/rk808.h
@@ -298,6 +298,7 @@ enum rk818_reg {
 #define VOUT_LO_INTBIT(0)
 #define CLK32KOUT2_EN  BIT(0)
 
+#define RK8XX_ID_MSK   0xfff0
 enum {
BUCK_ILMIN_50MA,
BUCK_ILMIN_100MA,
-- 
1.9.1

Re: [PATCH 5/6] KVM: VMX: add missing exit reasons

[David Hildenbrand]

Am 08.03.2017 um 19:03 schrieb Paolo Bonzini:
> In order to simplify adding exit reasons in the future,
> the array of exit reason names is now also sorted by
> exit reason code.
> 
> Signed-off-by: Paolo Bonzini 

Reviewed-by: David Hildenbrand 

-- 
Thanks,

David

[PATCH v1 2/4] linux: mfd: rk808: add rk805 regs addr and ID

[Elaine Zhang]

Signed-off-by: Elaine Zhang 
---
 include/linux/mfd/rk808.h | 91 +++
 1 file changed, 91 insertions(+)

diff --git a/include/linux/mfd/rk808.h b/include/linux/mfd/rk808.h
index 54feb140c210..7f4bab38c1d6 100644
--- a/include/linux/mfd/rk808.h
+++ b/include/linux/mfd/rk808.h
@@ -206,6 +206,89 @@ enum rk818_reg {
 #define RK818_USB_ILMIN_2000MA 0x7
 #define RK818_USB_CHG_SD_VSEL_MASK 0x70
 
+/* RK805 */
+enum rk805_reg {
+   RK805_ID_DCDC1,
+   RK805_ID_DCDC2,
+   RK805_ID_DCDC3,
+   RK805_ID_DCDC4,
+   RK805_ID_LDO1,
+   RK805_ID_LDO2,
+   RK805_ID_LDO3,
+};
+
+/* INTERRUPT REGISTER */
+#define RK805_INT_STS_REG  0x4C
+#define RK805_INT_STS_MSK_REG  0x4D
+#define RK805_GPIO_IO_POL_REG  0x50
+#define RK805_OUT_REG  0x52
+#define RK805_ON_SOURCE_REG0xAE
+#define RK805_OFF_SOURCE_REG   0xAF
+
+/* POWER CHANNELS ENABLE REGISTER */
+#define RK805_DCDC_EN_REG  0x23
+#define RK805_SLP_DCDC_EN_REG  0x25
+#define RK805_SLP_LDO_EN_REG   0x26
+#define RK805_LDO_EN_REG   0x27
+
+/* CONFIG REGISTER */
+#define RK805_THERMAL_REG  0x22
+
+/* BUCK AND LDO CONFIG REGISTER */
+#define RK805_BUCK_LDO_SLP_LP_EN_REG   0x2A
+#define RK805_BUCK1_CONFIG_REG 0x2E
+#define RK805_BUCK1_ON_VSEL_REG0x2F
+#define RK805_BUCK1_SLP_VSEL_REG   0x30
+#define RK805_BUCK2_CONFIG_REG 0x32
+#define RK805_BUCK2_ON_VSEL_REG0x33
+#define RK805_BUCK2_SLP_VSEL_REG   0x34
+#define RK805_BUCK3_CONFIG_REG 0x36
+#define RK805_BUCK4_CONFIG_REG 0x37
+#define RK805_BUCK4_ON_VSEL_REG0x38
+#define RK805_BUCK4_SLP_VSEL_REG   0x39
+#define RK805_LDO1_ON_VSEL_REG 0x3B
+#define RK805_LDO1_SLP_VSEL_REG0x3C
+#define RK805_LDO2_ON_VSEL_REG 0x3D
+#define RK805_LDO2_SLP_VSEL_REG0x3E
+#define RK805_LDO3_ON_VSEL_REG 0x3F
+#define RK805_LDO3_SLP_VSEL_REG0x40
+#define RK805_OUT_REG  0x52
+#define RK805_ON_SOURCE_REG0xAE
+#define RK805_OFF_SOURCE_REG   0xAF
+
+#define RK805_NUM_REGULATORS   7
+
+#define RK805_PWRON_FALL_RISE_INT_EN   0x0
+#define RK805_PWRON_FALL_RISE_INT_MSK  0x81
+
+/* RK805 IRQ Definitions */
+#define RK805_IRQ_PWRON_RISE   0
+#define RK805_IRQ_VB_LOW   1
+#define RK805_IRQ_PWRON2
+#define RK805_IRQ_PWRON_LP 3
+#define RK805_IRQ_HOTDIE   4
+#define RK805_IRQ_RTC_ALARM5
+#define RK805_IRQ_RTC_PERIOD   6
+#define RK805_IRQ_PWRON_FALL   7
+
+#define RK805_IRQ_PWRON_RISE_MSK   BIT(0)
+#define RK805_IRQ_VB_LOW_MSK   BIT(1)
+#define RK805_IRQ_PWRON_MSKBIT(2)
+#define RK805_IRQ_PWRON_LP_MSK BIT(3)
+#define RK805_IRQ_HOTDIE_MSK   BIT(4)
+#define RK805_IRQ_RTC_ALARM_MSKBIT(5)
+#define RK805_IRQ_RTC_PERIOD_MSK   BIT(6)
+#define RK805_IRQ_PWRON_FALL_MSK   BIT(7)
+
+#define RK805_PWR_RISE_INT_STATUS  BIT(0)
+#define RK805_VB_LOW_INT_STATUSBIT(1)
+#define RK805_PWRON_INT_STATUS BIT(2)
+#define RK805_PWRON_LP_INT_STATUS  BIT(3)
+#define RK805_HOTDIE_INT_STATUSBIT(4)
+#define RK805_ALARM_INT_STATUS BIT(5)
+#define RK805_PERIOD_INT_STATUSBIT(6)
+#define RK805_PWR_FALL_INT_STATUS  BIT(7)
+
 /* RK808 IRQ Definitions */
 #define RK808_IRQ_VOUT_LO  0
 #define RK808_IRQ_VB_LO1
@@ -298,7 +381,14 @@ enum rk818_reg {
 #define VOUT_LO_INTBIT(0)
 #define CLK32KOUT2_EN  BIT(0)
 
+#define TEMP115C   0x0c
+#define TEMP_HOTDIE_MSK0x0c
+#define SLP_SD_MSK (0x3 << 2)
+#define SHUTDOWN_FUN   (0x2 << 2)
+#define SLEEP_FUN  (0x1 << 2)
 #define RK8XX_ID_MSK   0xfff0
+#define FPWM_MODE  BIT(7)
+
 enum {
BUCK_ILMIN_50MA,
BUCK_ILMIN_100MA,
@@ -322,6 +412,7 @@ enum {
 };
 
 enum {
+   RK805_ID = 0x8050,
RK808_ID = 0x,
RK818_ID = 0x8181,
 };
-- 
1.9.1

[PATCH RESEND 1/4] mfd: arizona: Remove duplicate set of ret variable

[Charles Keepax]

arizona_poll_reg already returns ETIMEDOUT if we don't see the expected
register changes before the time out, so remove pointless local setting of
ETIMEDOUT.

Signed-off-by: Charles Keepax 
---
 drivers/mfd/arizona-core.c | 8 ++--
 1 file changed, 2 insertions(+), 6 deletions(-)

diff --git a/drivers/mfd/arizona-core.c b/drivers/mfd/arizona-core.c
index b6d4bc6..e00f577 100644
--- a/drivers/mfd/arizona-core.c
+++ b/drivers/mfd/arizona-core.c
@@ -342,10 +342,8 @@ static int arizona_enable_freerun_sysclk(struct arizona 
*arizona,
ret = arizona_poll_reg(arizona, 25, ARIZONA_INTERRUPT_RAW_STATUS_5,
   ARIZONA_FLL1_CLOCK_OK_STS,
   ARIZONA_FLL1_CLOCK_OK_STS);
-   if (ret) {
-   ret = -ETIMEDOUT;
+   if (ret)
goto err_fll;
-   }
 
ret = regmap_write(arizona->regmap, ARIZONA_SYSTEM_CLOCK_1, 0x0144);
if (ret) {
@@ -407,11 +405,9 @@ static int wm5102_apply_hardware_patch(struct arizona 
*arizona)
 
ret = arizona_poll_reg(arizona, 5, ARIZONA_WRITE_SEQUENCER_CTRL_1,
   ARIZONA_WSEQ_BUSY, 0);
-   if (ret) {
+   if (ret)
regmap_write(arizona->regmap, ARIZONA_WRITE_SEQUENCER_CTRL_0,
 ARIZONA_WSEQ_ABORT);
-   ret = -ETIMEDOUT;
-   }
 
 err:
err = arizona_disable_freerun_sysclk(arizona, &state);
-- 
2.1.4

[PATCH] ahci: qoriq: correct the sata ecc setting error

[Yuantian Tang]

Sata ecc is controlled by only 1 bit which is 24bit in big-endian
in ecc register. So only setting 24bit to disable sata ecc prevents
other bits from being overwritten in ecc register.

Signed-off-by: Tang Yuantian 
---
 drivers/ata/ahci_qoriq.c | 6 --
 1 file changed, 4 insertions(+), 2 deletions(-)

diff --git a/drivers/ata/ahci_qoriq.c b/drivers/ata/ahci_qoriq.c
index 85d8332..4c96f3a 100644
--- a/drivers/ata/ahci_qoriq.c
+++ b/drivers/ata/ahci_qoriq.c
@@ -177,7 +177,8 @@ static int ahci_qoriq_phy_init(struct ahci_host_priv *hpriv)
case AHCI_LS1043A:
if (!qpriv->ecc_addr)
return -EINVAL;
-   writel(ECC_DIS_ARMV8_CH2, qpriv->ecc_addr);
+   writel(readl(qpriv->ecc_addr) | ECC_DIS_ARMV8_CH2,
+   qpriv->ecc_addr);
writel(AHCI_PORT_PHY_1_CFG, reg_base + PORT_PHY1);
writel(AHCI_PORT_TRANS_CFG, reg_base + PORT_TRANS);
if (qpriv->is_dmacoherent)
@@ -194,7 +195,8 @@ static int ahci_qoriq_phy_init(struct ahci_host_priv *hpriv)
case AHCI_LS1046A:
if (!qpriv->ecc_addr)
return -EINVAL;
-   writel(ECC_DIS_ARMV8_CH2, qpriv->ecc_addr);
+   writel(readl(qpriv->ecc_addr) | ECC_DIS_ARMV8_CH2,
+   qpriv->ecc_addr);
writel(AHCI_PORT_PHY_1_CFG, reg_base + PORT_PHY1);
writel(AHCI_PORT_TRANS_CFG, reg_base + PORT_TRANS);
if (qpriv->is_dmacoherent)
-- 
2.1.0.27.g96db324

[PATCH RESEND 3/4] mfd: arizona: Update arizona_poll_reg to take a timeout in milliseconds

[Charles Keepax]

Currently, we specify the timeout in terms of the number of polls but it
is more clear from a user of the functions perspective to specify the
timeout directly in milliseconds, as such update the function to these new
semantics.

Signed-off-by: Charles Keepax 
---
 drivers/mfd/arizona-core.c | 18 --
 1 file changed, 12 insertions(+), 6 deletions(-)

diff --git a/drivers/mfd/arizona-core.c b/drivers/mfd/arizona-core.c
index 4cb34c3..09d48ed 100644
--- a/drivers/mfd/arizona-core.c
+++ b/drivers/mfd/arizona-core.c
@@ -235,14 +235,19 @@ static irqreturn_t arizona_overclocked(int irq, void 
*data)
return IRQ_HANDLED;
 }
 
+#define ARIZONA_REG_POLL_DELAY_MS 5
+#define ARIZONA_REG_POLL_DELAY_US (ARIZONA_REG_POLL_DELAY_MS * 1000)
+
 static int arizona_poll_reg(struct arizona *arizona,
-   int timeout, unsigned int reg,
+   int timeout_ms, unsigned int reg,
unsigned int mask, unsigned int target)
 {
+   unsigned int npolls = (timeout_ms + ARIZONA_REG_POLL_DELAY_MS - 1) /
+ ARIZONA_REG_POLL_DELAY_MS;
unsigned int val = 0;
int ret, i;
 
-   for (i = 0; i < timeout; i++) {
+   for (i = 0; i < npolls; i++) {
ret = regmap_read(arizona->regmap, reg, &val);
if (ret != 0) {
dev_err(arizona->dev, "Failed to read reg 0x%x: %d\n",
@@ -253,7 +258,8 @@ static int arizona_poll_reg(struct arizona *arizona,
if ((val & mask) == target)
return 0;
 
-   usleep_range(1000, 5000);
+   usleep_range(ARIZONA_REG_POLL_DELAY_US,
+ARIZONA_REG_POLL_DELAY_US * 2);
}
 
dev_err(arizona->dev, "Polling reg 0x%x timed out: %x\n", reg, val);
@@ -269,7 +275,7 @@ static int arizona_wait_for_boot(struct arizona *arizona)
 * we won't race with the interrupt handler as it'll be blocked on
 * runtime resume.
 */
-   ret = arizona_poll_reg(arizona, 5, ARIZONA_INTERRUPT_RAW_STATUS_5,
+   ret = arizona_poll_reg(arizona, 25, ARIZONA_INTERRUPT_RAW_STATUS_5,
   ARIZONA_BOOT_DONE_STS, ARIZONA_BOOT_DONE_STS);
 
if (!ret)
@@ -339,7 +345,7 @@ static int arizona_enable_freerun_sysclk(struct arizona 
*arizona,
ret);
return ret;
}
-   ret = arizona_poll_reg(arizona, 25, ARIZONA_INTERRUPT_RAW_STATUS_5,
+   ret = arizona_poll_reg(arizona, 125, ARIZONA_INTERRUPT_RAW_STATUS_5,
   ARIZONA_FLL1_CLOCK_OK_STS,
   ARIZONA_FLL1_CLOCK_OK_STS);
if (ret)
@@ -403,7 +409,7 @@ static int wm5102_apply_hardware_patch(struct arizona 
*arizona)
goto err;
}
 
-   ret = arizona_poll_reg(arizona, 5, ARIZONA_WRITE_SEQUENCER_CTRL_1,
+   ret = arizona_poll_reg(arizona, 25, ARIZONA_WRITE_SEQUENCER_CTRL_1,
   ARIZONA_WSEQ_BUSY, 0);
if (ret)
regmap_write(arizona->regmap, ARIZONA_WRITE_SEQUENCER_CTRL_0,
-- 
2.1.4