[Intel-gfx] [PATCH] drm/i915: Don't wait for vblank for sprite plane flips
Since the sprite planes are using synchronized MMIO based flip, no need
to wait for vblank. Removing this wait allows us to get a nice
performance boost to both 3D & media workloads based on sprite (~60 fps
from ~20 fps)
Signed-off-by: Vijay Purushothaman
Signed-off-by: Gary Smith
---
drivers/gpu/drm/i915/intel_sprite.c | 14 +-
1 file changed, 1 insertion(+), 13 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_sprite.c
b/drivers/gpu/drm/i915/intel_sprite.c
index 1fa5612..1d14fc0 100644
--- a/drivers/gpu/drm/i915/intel_sprite.c
+++ b/drivers/gpu/drm/i915/intel_sprite.c
@@ -828,20 +828,8 @@ intel_update_plane(struct drm_plane *plane, struct
drm_crtc *crtc,
intel_disable_primary(crtc);
/* Unpin old obj after new one is active to avoid ugliness */
- if (old_obj) {
- /*
-* It's fairly common to simply update the position of
-* an existing object. In that case, we don't need to
-* wait for vblank to avoid ugliness, we only need to
-* do the pin & ref bookkeeping.
-*/
- if (old_obj != obj) {
- mutex_unlock(&dev->struct_mutex);
- intel_wait_for_vblank(dev, to_intel_crtc(crtc)->pipe);
- mutex_lock(&dev->struct_mutex);
- }
+ if (old_obj)
intel_unpin_fb_obj(old_obj);
- }
out_unlock:
mutex_unlock(&dev->struct_mutex);
--
1.7.9.5
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Re: [Intel-gfx] [PATCH] drm/i915: Don't wait for vblank for sprite plane flips
On 6/28/2013 7:54 PM, Ville Syrjälä wrote:
On Fri, Jun 28, 2013 at 07:45:31PM +0530, Vijay Purushothaman wrote:
Since the sprite planes are using synchronized MMIO based flip, no need
to wait for vblank. Removing this wait allows us to get a nice
performance boost to both 3D & media workloads based on sprite (~60 fps
from ~20 fps)
Nak. We can't unpin the buffer until the hardware has finished reading
from it.
Thanks much for the review feedback. We have removed this check in our
android production branch so far we have not seen any side effect or
artifact. Is this a conservative check or do we have any use case which
will fail without this piece of code?
Apparently the windows driver team have been using MMIO flips for Sprite
and the windows driver also didn't wait for vblank for such flips all along.
Could you please help me understand this a bit better? This wait reduces
the perf to ~20 fps and thus prevent us from using sprite for any OGL
layer mapping in hwcomposer and we are losing significant amount of
power. For video content playback the problem is not that bad.
The proper fix is to do the unpin asynchronously after the flip has
completed. That's one part of the bigger atomic pageflip story.
Any idea when are we planning to merge this atomic flip in d-i-n-q?
Thanks,
Vijay
Signed-off-by: Vijay Purushothaman
Signed-off-by: Gary Smith
---
drivers/gpu/drm/i915/intel_sprite.c | 14 +-
1 file changed, 1 insertion(+), 13 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_sprite.c
b/drivers/gpu/drm/i915/intel_sprite.c
index 1fa5612..1d14fc0 100644
--- a/drivers/gpu/drm/i915/intel_sprite.c
+++ b/drivers/gpu/drm/i915/intel_sprite.c
@@ -828,20 +828,8 @@ intel_update_plane(struct drm_plane *plane, struct
drm_crtc *crtc,
intel_disable_primary(crtc);
/* Unpin old obj after new one is active to avoid ugliness */
- if (old_obj) {
- /*
-* It's fairly common to simply update the position of
-* an existing object. In that case, we don't need to
-* wait for vblank to avoid ugliness, we only need to
-* do the pin & ref bookkeeping.
-*/
- if (old_obj != obj) {
- mutex_unlock(&dev->struct_mutex);
- intel_wait_for_vblank(dev, to_intel_crtc(crtc)->pipe);
- mutex_lock(&dev->struct_mutex);
- }
+ if (old_obj)
intel_unpin_fb_obj(old_obj);
- }
out_unlock:
mutex_unlock(&dev->struct_mutex);
--
1.7.9.5
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Re: [Intel-gfx] [PATCH] drm/i915: Don't wait for vblank for sprite plane flips
On 6/28/2013 9:35 PM, Chris Wilson wrote: On Fri, Jun 28, 2013 at 05:24:50PM +0300, Ville Syrjälä wrote: On Fri, Jun 28, 2013 at 07:45:31PM +0530, Vijay Purushothaman wrote: Since the sprite planes are using synchronized MMIO based flip, no need to wait for vblank. Removing this wait allows us to get a nice performance boost to both 3D & media workloads based on sprite (~60 fps from ~20 fps) Nak. We can't unpin the buffer until the hardware has finished reading from it. The proper fix is to do the unpin asynchronously after the flip has completed. That's one part of the bigger atomic pageflip story. The interested reader is invited to review the patches to do async unpinning here and in set-base sent many, many moons ago. -Chris Thanks Chris. I will try to dig for those patches. In case if you have the pointers handy, would you mind pointing me to the patch series? Thanks, Vijay ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH 10/11] drm/i915: Improve PSR debugfs status.
On 5/16/2014 5:43 AM, Rodrigo Vivi wrote: Now we have the active/inactive state for exit and this actually changes the HW enable bit the status was a bit confusing for users. So let's provide more info. Signed-off-by: Rodrigo Vivi --- drivers/gpu/drm/i915/i915_debugfs.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c index 6636ca2..0ca9376 100644 --- a/drivers/gpu/drm/i915/i915_debugfs.c +++ b/drivers/gpu/drm/i915/i915_debugfs.c @@ -1975,10 +1975,12 @@ static int i915_edp_psr_status(struct seq_file *m, void *data) seq_printf(m, "Sink_Support: %s\n", yesno(dev_priv->psr.sink_support)); seq_printf(m, "Source_OK: %s\n", yesno(dev_priv->psr.source_ok)); + seq_printf(m, "Enabled: %s\n", yesno(dev_priv->psr.enabled)); + seq_printf(m, "Active: %s\n", yesno(dev_priv->psr.active)); enabled = HAS_PSR(dev) && I915_READ(EDP_PSR_CTL(dev)) & EDP_PSR_ENABLE; - seq_printf(m, "Enabled: %s\n", yesno(enabled)); + seq_printf(m, "HW Enabled & Active bit: %s\n", yesno(enabled)); if (HAS_PSR(dev)) psrperf = I915_READ(EDP_PSR_PERF_CNT(dev)) & Please remove all references to PSR performance counter. This register is primarily meant as a debug register and its implementation is broken in the h/w. Whenever the cdclk is gated to save power, the performance counter is stopped. But when the clk is re-enabled it doesn't reset the counter. This unnecessarily confuses the end users.. When the system goes through suspend / resume cycle the performance counter most likely will transition from a non-zero value to zero.. I already received few queries from our customers related to this performance customer and they refuse to believe me when i tell them PSR is still functional when the performance counter reports 0 :-) AFAIK this register definition is missing in open source HSW B spec as well.. Thanks, Vijay ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH 03/11] drm/i915: Use HAS_PSR to avoid unecessary interactions.
On 5/16/2014 5:43 AM, Rodrigo Vivi wrote:
Let's be more conservative and protect platforms that don't
support PSR from unecessary interactions.
Signed-off-by: Rodrigo Vivi
---
drivers/gpu/drm/i915/intel_dp.c | 13 -
1 file changed, 8 insertions(+), 5 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index 34e8f7a..58537b7 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -1739,11 +1739,6 @@ static bool intel_edp_psr_match_conditions(struct
intel_dp *intel_dp)
dev_priv->psr.source_ok = false;
- if (!HAS_PSR(dev)) {
- DRM_DEBUG_KMS("PSR not supported on this platform\n");
- return false;
- }
-
if ((intel_encoder->type != INTEL_OUTPUT_EDP) ||
(dig_port->port != PORT_A)) {
DRM_DEBUG_KMS("HSW ties PSR to DDI A (eDP)\n");
@@ -1816,6 +1811,11 @@ void intel_edp_psr_enable(struct intel_dp *intel_dp)
{
struct drm_device *dev = intel_dp_to_dev(intel_dp);
+ if (!HAS_PSR(dev)) {
+ DRM_DEBUG_KMS("PSR not supported on this platform\n");
+ return;
+ }
+
if (intel_edp_psr_match_conditions(intel_dp) &&
!intel_edp_is_psr_enabled(dev))
intel_edp_psr_do_enable(intel_dp);
@@ -1843,6 +1843,9 @@ void intel_edp_psr_update(struct drm_device *dev)
struct intel_encoder *encoder;
struct intel_dp *intel_dp = NULL;
+ if (!HAS_PSR(dev))
+ return;
+
list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head)
if (encoder->type == INTEL_OUTPUT_EDP) {
intel_dp = enc_to_intel_dp(&encoder->base);
Reviewed-by: Vijay Purushothaman
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Re: [Intel-gfx] [PATCH 04/11] drm/i915: Don't let update_psr function actually enable PSR.
On 5/16/2014 5:43 AM, Rodrigo Vivi wrote:
Being more conservative by enabling PSR only on psr_enable function.
Signed-off-by: Rodrigo Vivi
---
drivers/gpu/drm/i915/intel_dp.c | 10 +++---
1 file changed, 7 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index 58537b7..fe28eb7 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -1797,9 +1797,6 @@ static void intel_edp_psr_do_enable(struct intel_dp
*intel_dp)
intel_edp_is_psr_enabled(dev))
return;
- /* Setup PSR once */
- intel_edp_psr_setup(intel_dp);
-
/* Enable PSR on the panel */
intel_edp_psr_enable_sink(intel_dp);
@@ -1816,6 +1813,9 @@ void intel_edp_psr_enable(struct intel_dp *intel_dp)
return;
}
+ /* Setup PSR once */
+ intel_edp_psr_setup(intel_dp);
+
if (intel_edp_psr_match_conditions(intel_dp) &&
!intel_edp_is_psr_enabled(dev))
intel_edp_psr_do_enable(intel_dp);
@@ -1840,12 +1840,16 @@ void intel_edp_psr_disable(struct intel_dp *intel_dp)
void intel_edp_psr_update(struct drm_device *dev)
{
+ struct drm_i915_private *dev_priv = dev->dev_private;
struct intel_encoder *encoder;
struct intel_dp *intel_dp = NULL;
if (!HAS_PSR(dev))
return;
+ if (!dev_priv->psr.setup_done)
+ return;
+
list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head)
if (encoder->type == INTEL_OUTPUT_EDP) {
intel_dp = enc_to_intel_dp(&encoder->base);
Reviewed-by: Vijay Purushothaman
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Re: [Intel-gfx] [PATCH 06/11] drm/i915: Force PSR exit by inactivating it.
On 5/16/2014 10:12 PM, Rodrigo Vivi wrote: On Fri, May 16, 2014 at 3:23 AM, Chris Wilson mailto:ch...@chris-wilson.co.uk>> wrote: On Thu, May 15, 2014 at 08:13:05PM -0400, Rodrigo Vivi wrote: > The perfect solution for psr_exit is the hardware tracking the changes and > doing the psr exit by itself. This scenario works for HSW and BDW with some > environments like Gnome and Wayland. > > However there are many other scenarios that this isn't true. Mainly one right > now is KDE users on HSW and BDW with PSR on. User would miss many screen > updates. For instances any key typed could be seen only when mouse cursor is > moved. So this patch introduces the ability of trigger PSR exit on kernel side > on some common cases that. You know that userspace has been waiting for a PSR flag for over a year now so that it can use the more efficient rendering paths when it makes sense. yeah... this item is lingering on my to do list... but reaching a point where I won't be able to continue postponing it ;) What happened to the front buffer tracking? What front buffer tracking? hehe I'm wondering about this since I started looking to fbc and psr and could never find a reliable way. FBC should cover most of the scenarios except cursor planes.. When ever cursor planes are enabled you can fall back to s/w controlled exit path. If you can elaborate on the exact issue that you are facing with FBC and PSR may be i can help.. Thanks, Vijay -Chris -- Chris Wilson, Intel Open Source Technology Centre -- Rodrigo Vivi Blog: http://blog.vivi.eng.br ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH 08/11] drm/i915: BDW PSR: Remove limitations that aren't valid for BDW.
On 5/16/2014 5:43 AM, Rodrigo Vivi wrote:
Signed-off-by: Rodrigo Vivi
---
drivers/gpu/drm/i915/intel_dp.c | 5 +
1 file changed, 5 insertions(+)
diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index 28144d3..9421b0b 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -1768,6 +1768,10 @@ static bool intel_edp_psr_match_conditions(struct
intel_dp *intel_dp)
return false;
}
+ /* Below limitations aren't valid for Broadwell */
+ if (IS_BROADWELL(dev))
+ goto out;
I couldn't figure out any sprite related restrictions for HSW as well.
Is this because FBC logic doesn't track sprites in HSW?
Thanks,
Vijay
+
if (I915_READ(SPRCTL(intel_crtc->pipe)) & SPRITE_ENABLE) {
DRM_DEBUG_KMS("PSR condition failed: Sprite is Enabled\n");
return false;
@@ -1784,6 +1788,7 @@ static bool intel_edp_psr_match_conditions(struct
intel_dp *intel_dp)
return false;
}
+ out:
dev_priv->psr.source_ok = true;
return true;
}
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Re: [Intel-gfx] [PATCH 10/11] drm/i915: Improve PSR debugfs status.
On 6/3/2014 1:10 PM, Daniel Vetter wrote: On Mon, Jun 02, 2014 at 11:54:10PM +0530, Vijay Purushothaman wrote: On 5/16/2014 5:43 AM, Rodrigo Vivi wrote: Now we have the active/inactive state for exit and this actually changes the HW enable bit the status was a bit confusing for users. So let's provide more info. Signed-off-by: Rodrigo Vivi --- drivers/gpu/drm/i915/i915_debugfs.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c index 6636ca2..0ca9376 100644 --- a/drivers/gpu/drm/i915/i915_debugfs.c +++ b/drivers/gpu/drm/i915/i915_debugfs.c @@ -1975,10 +1975,12 @@ static int i915_edp_psr_status(struct seq_file *m, void *data) seq_printf(m, "Sink_Support: %s\n", yesno(dev_priv->psr.sink_support)); seq_printf(m, "Source_OK: %s\n", yesno(dev_priv->psr.source_ok)); + seq_printf(m, "Enabled: %s\n", yesno(dev_priv->psr.enabled)); + seq_printf(m, "Active: %s\n", yesno(dev_priv->psr.active)); enabled = HAS_PSR(dev) && I915_READ(EDP_PSR_CTL(dev)) & EDP_PSR_ENABLE; - seq_printf(m, "Enabled: %s\n", yesno(enabled)); + seq_printf(m, "HW Enabled & Active bit: %s\n", yesno(enabled)); if (HAS_PSR(dev)) psrperf = I915_READ(EDP_PSR_PERF_CNT(dev)) & Please remove all references to PSR performance counter. This register is primarily meant as a debug register and its implementation is broken in the h/w. Whenever the cdclk is gated to save power, the performance counter is stopped. But when the clk is re-enabled it doesn't reset the counter. This unnecessarily confuses the end users.. When the system goes through suspend / resume cycle the performance counter most likely will transition from a non-zero value to zero.. I already received few queries from our customers related to this performance customer and they refuse to believe me when i tell them PSR is still functional when the performance counter reports 0 :-) We expose other such perf registers and imo this is handy for debugging. Also we have a big push to expose all this perf stuff recently ... Imo we should keep this, if we can. If confused customers noodle around in debugfs without clue, maybe they shouldn't. -Daniel In that case here is my Reviewed-by: Vijay Purushothaman Thanks, Vijay ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH 11/11] drm/i915: PSR HSW: update after enabling sprite.
On 5/16/2014 5:43 AM, Rodrigo Vivi wrote: On the current structure HSW doesn't support PSR with sprites enabled but sprites can be enabled after PSR was enabled what would cause user to miss screen updates. Could you please explain this a bit more? Did you get a confirmation from h/w team that this is not possible? AFAIK, HSW should be able to support PSR with sprites enabled. Thanks, Vijay v2: move it to update_plane. Cc: Ville Syrjälä Signed-off-by: Rodrigo Vivi --- drivers/gpu/drm/i915/intel_sprite.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/gpu/drm/i915/intel_sprite.c b/drivers/gpu/drm/i915/intel_sprite.c index 213cd58..4b85400 100644 --- a/drivers/gpu/drm/i915/intel_sprite.c +++ b/drivers/gpu/drm/i915/intel_sprite.c @@ -1051,6 +1051,8 @@ intel_update_plane(struct drm_plane *plane, struct drm_crtc *crtc, mutex_unlock(&dev->struct_mutex); } + intel_edp_psr_update(dev); + return 0; } ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH 00/11] HSW/BDW PSR.
On 5/16/2014 5:42 AM, Rodrigo Vivi wrote: MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Hi All, This series introduces fixes for PSR on HSW and on BDW and "new features" for PSR on BDW. The biggest thing on this serie is the introduction of the psr_exit infrastructure that was actually created for PSR on Baytrail. However since on Baytrail the HW cannot track absolutelly no screen update lets put it first to work on HSW and BDW. This brings more reliability to PSR and make it possible to use even on non GL userspace environments like KDE. Without this psr_exit infrastructure we will never be able to enable psr by default because this breaks the userspace for all KDE users. I understand the possible limitations of this infrastructure, but this is the best we can do for now. Other possibilities to solve this issue is let the full control to userspace over ioctl. I'm thinking about a next rework where userspace could dinamically switch over some possible PSR levels like: 1 - Full HW control - that works good enough on Gnome HSW and extract the best residency time. 2 - PSR-exit by inactivating - That would be for KDE users 3 - Full SW control - where userspace would control PSR exit/entry flow over\ ioctls. On BDW "new features" there are basically the intorducion of a single frame update support what in theory improve residency time and also remove limitations that only affect HSW like DDI only on PORT_A and PSR off when sprites are in use. Please help me to get this merged with good suggestions of improvements. Please do not say just: "that is not good". I know that already. Please provide good ideas along with the comments. Thanks in advance, Rodrigo. Rodrigo Vivi (11): drm/i915: move psr_setup_done to psr struct drm/i915: Update PSR on resume. drm/i915: Use HAS_PSR to avoid unecessary interactions. drm/i915: Don't let update_psr function actually enable PSR. drm/i915: Do not try to enable PSR when Panel doesn't suport it. drm/i915: Force PSR exit by inactivating it. drm/i915: BDW PSR: Add single frame update support. drm/i915: BDW PSR: Remove limitations that aren't valid for BDW. drm/i915: BDW PSR: Remove DDIA limitation for Broadwell. drm/i915: Improve PSR debugfs status. drm/i915: PSR HSW: update after enabling sprite. drivers/gpu/drm/i915/i915_debugfs.c | 4 +- drivers/gpu/drm/i915/i915_drv.h | 4 + drivers/gpu/drm/i915/i915_gem.c | 6 ++ drivers/gpu/drm/i915/i915_reg.h | 1 + drivers/gpu/drm/i915/i915_suspend.c | 3 + drivers/gpu/drm/i915/intel_display.c | 20 - drivers/gpu/drm/i915/intel_dp.c | 153 --- drivers/gpu/drm/i915/intel_drv.h | 4 +- drivers/gpu/drm/i915/intel_sprite.c | 2 + 9 files changed, 165 insertions(+), 32 deletions(-) Thanks for sharing the PM enabling guide document. After going through that document, things are clear for me. For the series, Reviewed-by: Vijay Purushothaman Thanks, Vijay ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] Request for feedback - Sprite flip notification support
Hello, In our current driver implementation we support flip notifications only for primary plane. So, in a full screen video playback scenario where only one sprite plane is active, the user space is forced to rely on primary plane flip notification even though there is no real need for this plane to be active. Ideally we should be able to support flip notifications for any given plane. Switching off the primary plane (when not used) will help in better memory self refresh & decent power savings.. We do have a hack in android product trees which supports flip notifications for one sprite plane. unfortunately this hack in its current form cannot be considered for up streaming... My current thinking is to have an array of unpin_work items to match the number of planes. Is anyone working on this or thought about this scenario in detail? Any pointers / restrictions that needs to considered for a generic implementation of this feature? *Thanks, Vijay * ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] Request for feedback - Sprite flip notification support
On 2/5/2014 8:43 PM, Ville Syrjälä wrote: On Wed, Feb 05, 2014 at 08:35:11PM +0530, Vijay Purushothaman wrote: Hello, In our current driver implementation we support flip notifications only for primary plane. So, in a full screen video playback scenario where only one sprite plane is active, the user space is forced to rely on primary plane flip notification even though there is no real need for this plane to be active. Ideally we should be able to support flip notifications for any given plane. Switching off the primary plane (when not used) will help in better memory self refresh & decent power savings.. We do have a hack in android product trees which supports flip notifications for one sprite plane. unfortunately this hack in its current form cannot be considered for up streaming... My current thinking is to have an array of unpin_work items to match the number of planes. Is anyone working on this or thought about this scenario in detail? Any pointers / restrictions that needs to considered for a generic implementation of this feature? The plan is to implement the nuclear page flip which will take care of all planes in the same way. Thanks Ville. If the nuclear page flip is part of your bigger atomic mode set framework, is there a way you can split this into smaller sets for merge? Multiple product trees will benefit from the nuclear page flip. Is there anything that i can help with? Like testing your patches with android user space? Thanks, Vijay ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] Request for feedback - Sprite flip notification support
On 2/5/2014 10:18 PM, Ville Syrjälä wrote: On Wed, Feb 05, 2014 at 09:25:36PM +0530, Vijay Purushothaman wrote: On 2/5/2014 8:43 PM, Ville Syrjälä wrote: On Wed, Feb 05, 2014 at 08:35:11PM +0530, Vijay Purushothaman wrote: Hello, In our current driver implementation we support flip notifications only for primary plane. So, in a full screen video playback scenario where only one sprite plane is active, the user space is forced to rely on primary plane flip notification even though there is no real need for this plane to be active. Ideally we should be able to support flip notifications for any given plane. Switching off the primary plane (when not used) will help in better memory self refresh & decent power savings.. We do have a hack in android product trees which supports flip notifications for one sprite plane. unfortunately this hack in its current form cannot be considered for up streaming... My current thinking is to have an array of unpin_work items to match the number of planes. Is anyone working on this or thought about this scenario in detail? Any pointers / restrictions that needs to considered for a generic implementation of this feature? The plan is to implement the nuclear page flip which will take care of all planes in the same way. Thanks Ville. If the nuclear page flip is part of your bigger atomic mode set framework, is there a way you can split this into smaller sets for merge? Multiple product trees will benefit from the nuclear page flip. I've split things up already somewhat. Some has landed some has not. Currently I have my minimal "atomic update of sprite+primary during setplane" series I need to get in. It shouldn't need major work anymore, just some minor tweaks. But I realized I need to limit this to just pch platforms for now. Making it work reliably on gmch platforms require some extra interrupt related work. The main thing here is that it adds the mechanism to do the update atomically for the entire pipe. After that I need to post the last bits of my watermark update saga. This too will initially be limited to pch platforms only. Obviously watermarks need to updated correctly to avoid underruns when planes get shuffled around. Is there anything that i can help with? Like testing your patches with android user space? There's nothing to test at this point unless you want to test my old branch from year ago or something. What needs to be done: - review the latest atomic framework patches from Rob Clark - expose primary/cursor planes as drm_planes * this could in theory be skipped, but it'll lead to cruft in the API we need to maintain until the end of time. Also I think restructing stuff internally to this direction will be a good idea anyway to make the nuclear flip code neater. This more or less involves collecting the plane state to some plane_config type of structure, and being able to pre-compute that - try to collect the necessary missing bits from my last atomic branch to implement the nuclear flip * the flip helper thing to update an arbitrary collection of planes atomically, maybe could be simplified a bit * mechanism to queue nuclear flips and make them wait for the GPU to finish writing to all the relevant buffers before issuing the actual flips/updates - finally hook up the atomic ioctl to do the nuclear flip * pre-pin all buffers, pre-compute plane configs, pre-compute watermarks, check everything, wait for the GPU, and finally do the update For the atomic modeset side some of that's the same really. There too we also need to pre-compute the plane configs and pre-pin buffers. Most of the rest we already pre-compute via the pipe config. One major thing left out of the pipe config pre-compute currently is PLLs. We compute that stuff way too late still. We also need to massage the modeset code some more to make it capable of modesetting multiple pipes at once. Thanks for the detailed answer. This should solve most of the display issues in the product trees.. considering the amount of work involved this looks more like a long term solution. Would it be okay if we submit a short term solution for sprite flip notifications? This would help us to force a standard approach across multiple android product kernels. We can revert this fix once the atomic mode set / nuclear page flip is ready. Thanks, Vijay ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] Request for feedback - Sprite flip notification support
On 2/6/2014 12:28 PM, Vijay Purushothaman wrote: On 2/5/2014 10:18 PM, Ville Syrjälä wrote: On Wed, Feb 05, 2014 at 09:25:36PM +0530, Vijay Purushothaman wrote: On 2/5/2014 8:43 PM, Ville Syrjälä wrote: On Wed, Feb 05, 2014 at 08:35:11PM +0530, Vijay Purushothaman wrote: Hello, In our current driver implementation we support flip notifications only for primary plane. So, in a full screen video playback scenario where only one sprite plane is active, the user space is forced to rely on primary plane flip notification even though there is no real need for this plane to be active. Ideally we should be able to support flip notifications for any given plane. Switching off the primary plane (when not used) will help in better memory self refresh & decent power savings.. We do have a hack in android product trees which supports flip notifications for one sprite plane. unfortunately this hack in its current form cannot be considered for up streaming... My current thinking is to have an array of unpin_work items to match the number of planes. Is anyone working on this or thought about this scenario in detail? Any pointers / restrictions that needs to considered for a generic implementation of this feature? The plan is to implement the nuclear page flip which will take care of all planes in the same way. Thanks Ville. If the nuclear page flip is part of your bigger atomic mode set framework, is there a way you can split this into smaller sets for merge? Multiple product trees will benefit from the nuclear page flip. I've split things up already somewhat. Some has landed some has not. Currently I have my minimal "atomic update of sprite+primary during setplane" series I need to get in. It shouldn't need major work anymore, just some minor tweaks. But I realized I need to limit this to just pch platforms for now. Making it work reliably on gmch platforms require some extra interrupt related work. The main thing here is that it adds the mechanism to do the update atomically for the entire pipe. After that I need to post the last bits of my watermark update saga. This too will initially be limited to pch platforms only. Obviously watermarks need to updated correctly to avoid underruns when planes get shuffled around. Is there anything that i can help with? Like testing your patches with android user space? There's nothing to test at this point unless you want to test my old branch from year ago or something. What needs to be done: - review the latest atomic framework patches from Rob Clark - expose primary/cursor planes as drm_planes * this could in theory be skipped, but it'll lead to cruft in the API we need to maintain until the end of time. Also I think restructing stuff internally to this direction will be a good idea anyway to make the nuclear flip code neater. This more or less involves collecting the plane state to some plane_config type of structure, and being able to pre-compute that - try to collect the necessary missing bits from my last atomic branch to implement the nuclear flip * the flip helper thing to update an arbitrary collection of planes atomically, maybe could be simplified a bit * mechanism to queue nuclear flips and make them wait for the GPU to finish writing to all the relevant buffers before issuing the actual flips/updates - finally hook up the atomic ioctl to do the nuclear flip * pre-pin all buffers, pre-compute plane configs, pre-compute watermarks, check everything, wait for the GPU, and finally do the update For the atomic modeset side some of that's the same really. There too we also need to pre-compute the plane configs and pre-pin buffers. Most of the rest we already pre-compute via the pipe config. One major thing left out of the pipe config pre-compute currently is PLLs. We compute that stuff way too late still. We also need to massage the modeset code some more to make it capable of modesetting multiple pipes at once. Thanks for the detailed answer. This should solve most of the display issues in the product trees.. considering the amount of work involved this looks more like a long term solution. Would it be okay if we submit a short term solution for sprite flip notifications? This would help us to force a standard approach across multiple android product kernels. We can revert this fix once the atomic mode set / nuclear page flip is ready. Ville / Daniel, Ping.. Could you please suggest whether this is okay? If you think this is not worth or if nuclear page flip is on the horizon i will focus on display self refresh patches.. Thanks, Vijay ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH] drm/i915: Fix correct FIFO size for Baytrail
B-spec says the FIFO total size is 512. So fix this to 512. Signed-off-by: Vijay Purushothaman --- drivers/gpu/drm/i915/i915_reg.h |2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index cc3ea04..fb73031 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -3395,7 +3395,7 @@ #define I915_FIFO_LINE_SIZE64 #define I830_FIFO_LINE_SIZE32 -#define VALLEYVIEW_FIFO_SIZE 255 +#define VALLEYVIEW_FIFO_SIZE 511 #define G4X_FIFO_SIZE 127 #define I965_FIFO_SIZE 512 #define I945_FIFO_SIZE 127 -- 1.7.9.5 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH] drm/i915: Fix correct FIFO size for Baytrail
On 2/7/2014 9:28 PM, Ville Syrjälä wrote: On Fri, Feb 07, 2014 at 08:43:12PM +0530, Vijay Purushothaman wrote: B-spec says the FIFO total size is 512. So fix this to 512. Signed-off-by: Vijay Purushothaman --- drivers/gpu/drm/i915/i915_reg.h |2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index cc3ea04..fb73031 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -3395,7 +3395,7 @@ #define I915_FIFO_LINE_SIZE 64 #define I830_FIFO_LINE_SIZE 32 -#define VALLEYVIEW_FIFO_SIZE 255 +#define VALLEYVIEW_FIFO_SIZE 511 #define G4X_FIFO_SIZE 127 #define I965_FIFO_SIZE512 #define I945_FIFO_SIZE127 Reviewed-by: Ville Syrjälä Thanks for the review. Not that we actually use the value anywhere at the moment. This value is used when the display controller is configured in Max FIFO mode. This is working fine in the android tree. At this moment i am rewriting some logic related to this Max FIFO, memory arbiter credits and drain latency handling for the sprite planes. I should have the patches ready over the week end, will test it on monday once i get to office. As a side note the FIFO sizing for gmch platforms seems to be a place where the documentation is rather poor. It kind of looks like there are off by one errors in the text, and yet when I was playing around with this stuff on gen2/gen4 machines it kind of looks like the hardware has the same off by one issues too. IIRC my conlusion was that the last cacheline in the FIFO can't actually be used. So specifying 511 matches with my conclusion. I agree.. I was thrown off by this oddity as well and it took some time for me to understand this completely. The display block in Baytrail is a mix and match of features from gen4 & gen5 (Cantiga, Crestline and Ironlake). No wonder this chip has the same h/w issues.. One other thing I did notice now that I look at our g4x/vlv watermark code. We seem to assume the watermarks for g4x/vlv work the same way as pch platforms. Ie. you specify the minimum level of data left in the FIFO before it needs to start fetching more. But the documentation suggests that it's the other way around, where you specify the max amount of free space allowed in the FIFO before more data needs to be fetched. We use the latter logic for gen2-gen4. I wonder if the spec is wrong, or if your code is wrong. I guess I just need to verify it on real hardware at some point... I think this is implemented correctly in the android kernel.. On a high level the split is something like 32 KB FIFO per pipe - 16 KB for primary plane and 8 KB for each sprite. When we are in single display mode we can configure the entire 64KB FIFO for the same pipe. There is another trick to enable trickle feed.. With all these tricks i am seeing good memory self refresh numbers - almost on par with the theoretical target. I should be able to post the patch series on monday once i do some sanity testing.. Thanks, Vijay ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 0/2] Valleyview PLL fix and cleanup
Fixed the wrong p2 PLL values and replaced all hardcoded numbers in best PLL calculation. These two patches should be applied on top of Jesse's Jun 14 Valleyview patch set. Tried to refactor the code to avoid so many nested loops but ended up messing other VLV code. Any help with code refactoring, most welcome! Thanks, Vijay Vijay Purushothaman (2): drm/i915 : fix incorrect p2 values for Valleyview drm/i915: cleanup Valleyview PLL calculation drivers/gpu/drm/i915/intel_display.c | 58 ++ 1 files changed, 24 insertions(+), 34 deletions(-) -- 1.7.5.4 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 1/2] drm/i915 : fix incorrect p2 values for Valleyview
Signed-off-by: Vijay Purushothaman
---
drivers/gpu/drm/i915/intel_display.c |6 +++---
1 files changed, 3 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_display.c
b/drivers/gpu/drm/i915/intel_display.c
index 157dcb0a..0707b7a 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -374,7 +374,7 @@ static const intel_limit_t intel_limits_vlv_dac = {
.p = { .min = 10, .max = 30 },
.p1 = { .min = 2, .max = 3 },
.p2 = { .dot_limit = 27,
- .p2_slow = 10, .p2_fast = 5 },
+ .p2_slow = 2, .p2_fast = 20 },
.find_pll = intel_vlv_find_best_pll,
};
@@ -388,7 +388,7 @@ static const intel_limit_t intel_limits_vlv_hdmi = {
.p = { .min = 10, .max = 30 },
.p1 = { .min = 2, .max = 3 },
.p2 = { .dot_limit = 27,
- .p2_slow = 10, .p2_fast = 5 },
+ .p2_slow = 2, .p2_fast = 20 },
.find_pll = intel_vlv_find_best_pll,
};
@@ -402,7 +402,7 @@ static const intel_limit_t intel_limits_vlv_dp = {
.p = { .min = 10, .max = 30 },
.p1 = { .min = 2, .max = 3 },
.p2 = { .dot_limit = 27,
- .p2_slow = 10, .p2_fast = 5 },
+ .p2_slow = 2, .p2_fast = 20 },
.find_pll = intel_vlv_find_best_pll,
};
--
1.7.5.4
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 2/2] drm/i915: cleanup Valleyview PLL calculation
replaced hardcoded numbers with valid PLL limit values
Signed-off-by: Vijay Purushothaman
---
drivers/gpu/drm/i915/intel_display.c | 52 +
1 files changed, 21 insertions(+), 31 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_display.c
b/drivers/gpu/drm/i915/intel_display.c
index 0707b7a..e2d23a3 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -865,69 +865,59 @@ intel_vlv_find_best_pll(const intel_limit_t *limit,
struct drm_crtc *crtc,
intel_clock_t *best_clock)
{
u32 p1, p2, m1, m2, vco, bestn, bestm1, bestm2, bestp1, bestp2;
- u32 m, n, fastclk, minvco, maxvco;
+ u32 m, n, fastclk;
u32 updrate, minupdate, fracbits, p;
unsigned long bestppm, ppm, absppm;
- int dotclk;
+ int dotclk, flag;
dotclk = target * 1000;
-
bestppm = 100;
- ppm = 0;
- absppm = 0;
-
+ ppm = absppm = 0;
fastclk = dotclk / (2*100);
- minvco = limit->vco.min;
- maxvco = limit->vco.max;
updrate = 0;
minupdate = 19200;
fracbits = 1;
-
n = p = p1 = p2 = m = m1 = m2 = vco = bestn = 0;
bestm1 = bestm2 = bestp1 = bestp2 = 0;
- for(n = 1; n <= ((refclk) / minupdate); n++) {
+ /* based on hardware requirement, prefer smaller n to precision */
+ for (n = limit->n.min; n <= ((refclk) / minupdate); n++) {
updrate = refclk / n;
- for (p1 = 3; p1 > 1; p1--) {
- for (p2 = 21; p2 > 0; p2--) {
+ for (p1 = limit->p1.max; p1 > limit->p1.min; p1--) {
+ for (p2 = limit->p2.p2_fast+1; p2 > 0; p2--) {
if (p2 > 10)
p2 = p2 - 1;
p = p1 * p2;
-
- for( m1=2; m1 <= 3; m1++) {
+ /* based on hardware requirement, prefer bigger
m1,m2 values */
+ for (m1 = limit->m1.min; m1 <= limit->m1.max;
m1++) {
m2 = (((2*(fastclk * p * n / m1 )) +
refclk) / (2*refclk));
m = m1 * m2;
vco = updrate * m;
- if(vco >= minvco && vco < maxvco) {
- ppm = 100 *((vco / p) -
- fastclk) /
- fastclk;
- absppm = (ppm > 0)? ppm: (-ppm);
- if (absppm < 100 &&
- ((p1 * p2) >
-(bestp1 * bestp2))) {
+ if (vco >= limit->vco.min && vco <
limit->vco.max) {
+ ppm = 100 * ((vco / p) -
fastclk) / fastclk;
+ absppm = (ppm > 0) ? ppm :
(-ppm);
+ if (absppm < 100 && ((p1 * p2)
> (bestp1 * bestp2))) {
bestppm = 0;
- bestn = n;
- bestm1 = m1;
- bestm2 = m2;
- bestp1 = p1;
- bestp2 = p2;
+ flag = 1;
}
if (absppm < bestppm - 10) {
bestppm = absppm;
+ flag = 1;
+ }
+ if (flag) {
bestn = n;
bestm1 = m1;
bestm2 = m2;
bestp1 = p1;
bestp2 = p2;
+ flag = 0;
}
}
}
- } /* Next p2 */
- } /* Next p1 */
- }/* Next n */
-
+ }
+
[Intel-gfx] [PATCH intel-gpu-tools] tools: Added intel_dpio_read and intel_dpio_write
In Valleyview the DPLL and lane control registers are accessible only
through side band fabric called DPIO. Added two tools to read and write
registers residing in this space.
Signed-off-by: Vijay Purushothaman
---
tools/Makefile.am|2 +
tools/intel_dpio_read.c | 105 ++
tools/intel_dpio_write.c | 103 +
3 files changed, 210 insertions(+)
create mode 100644 tools/intel_dpio_read.c
create mode 100644 tools/intel_dpio_write.c
diff --git a/tools/Makefile.am b/tools/Makefile.am
index d461f38..71fb087 100644
--- a/tools/Makefile.am
+++ b/tools/Makefile.am
@@ -15,6 +15,8 @@ bin_PROGRAMS =\
intel_reg_write \
intel_reg_read \
intel_forcewaked\
+ intel_dpio_read \
+ intel_dpio_write\
intel_l3_parity
noinst_PROGRAMS = \
diff --git a/tools/intel_dpio_read.c b/tools/intel_dpio_read.c
new file mode 100644
index 000..8b924fd
--- /dev/null
+++ b/tools/intel_dpio_read.c
@@ -0,0 +1,105 @@
+/*
+ * Copyright © 2012 Intel Corporation
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the next
+ * paragraph) shall be included in all copies or substantial portions of the
+ * Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ *
+ * Authors:
+ * Vijay Purushothaman
+ *
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include "intel_gpu_tools.h"
+
+#define VLV_DISPLAY_BASE 0x18
+#define DPIO_PKT 0x2100
+#define DPIO_RID (0 << 24)
+#define DPIO_OP_WRITE (1 << 16)
+#define DPIO_OP_READ (0 << 16)
+#define DPIO_PORTID (0x12 << 8)
+#define DPIO_BYTE (0xf << 4)
+#define DPIO_BUSY (1 << 0)
+#define DPIO_DATA 0x2104
+#define DPIO_REG 0x2108
+
+static uint32_t vlv_display_reg_read(uint32_t reg)
+{
+ reg += VLV_DISPLAY_BASE;
+ return (*(volatile uint32_t *)((volatile char*)mmio + reg));
+}
+
+static void vlv_display_reg_write(uint32_t reg, uint32_t val)
+{
+ volatile uint32_t *ptr;
+
+ reg += VLV_DISPLAY_BASE;
+ ptr = (volatile uint32_t *)((volatile char *) mmio + reg);
+ *ptr = val;
+}
+
+static void usage(char *cmdname)
+{
+ printf("Warning : This program will work only on Valleyview\n");
+ printf("Usage: %s [addr]\n", cmdname);
+ printf("\t addr : in 0x format\n");
+}
+
+int main(int argc, char** argv)
+{
+ int ret = 0;
+ uint32_t reg, val;
+ char *cmdname = strdup(argv[0]);
+
+ if (argc != 2) {
+ usage(cmdname);
+ ret = 1;
+ goto out;
+ }
+
+ sscanf(argv[1], "0x%x", ®);
+
+ intel_register_access_init(intel_get_pci_device(), 0);
+
+ /* Check whether the side band fabric is ready to accept commands */
+ do {
+ usleep(1);
+ } while (vlv_display_reg_read(DPIO_PKT) & DPIO_BUSY);
+
+ vlv_display_reg_write(DPIO_REG, reg);
+ vlv_display_reg_write(DPIO_PKT, DPIO_RID | DPIO_OP_READ | DPIO_PORTID |
+ DPIO_BYTE);
+ do {
+ usleep(1);
+ } while (vlv_display_reg_read(DPIO_PKT) & DPIO_BUSY);
+
+ val = vlv_display_reg_read(DPIO_DATA);
+
+ printf("Read DPIO register: 0x%x - Value : 0x%x\n", reg, val);
+
+ intel_register_access_fini();
+
+out:
+ free(cmdname);
+ return ret;
+}
diff --git a/tools/intel_dpio_write.c b/tools/intel_dpio_write.c
new file mode 100644
index 000..96b72dd
--- /dev/null
+++ b/tools/intel_dpio_write.c
@@ -0,0 +1,103 @@
+/*
+ * Copyrig
Re: [Intel-gfx] [PATCH intel-gpu-tools] tools: Added intel_dpio_read and intel_dpio_write
On Thu, 2 Aug 2012 09:06:48 -0700
Ben Widawsky wrote:
> On 2012-08-02 05:07, Vijay Purushothaman wrote:
> > In Valleyview the DPLL and lane control registers are accessible
> > only through side band fabric called DPIO. Added two tools to read
> > and write
> > registers residing in this space.
>
> Could I convince you to use the centralized read/write mmio functions?
> Otherwise, everything seems fine to me here.
>
Sure. I will move these read, write functions to intel_reg_read &
intel_reg_write.
Thanks,
Vijay
> >
> > Signed-off-by: Vijay Purushothaman
> > ---
> > tools/Makefile.am|2 +
> > tools/intel_dpio_read.c | 105
> > ++
> > tools/intel_dpio_write.c | 103
> > +
> > 3 files changed, 210 insertions(+)
> > create mode 100644 tools/intel_dpio_read.c
> > create mode 100644 tools/intel_dpio_write.c
> >
> > diff --git a/tools/Makefile.am b/tools/Makefile.am
> > index d461f38..71fb087 100644
> > --- a/tools/Makefile.am
> > +++ b/tools/Makefile.am
> > @@ -15,6 +15,8 @@ bin_PROGRAMS =\
> > intel_reg_write \
> > intel_reg_read \
> > intel_forcewaked\
> > + intel_dpio_read \
> > + intel_dpio_write\
> > intel_l3_parity
> >
> > noinst_PROGRAMS = \
> > diff --git a/tools/intel_dpio_read.c b/tools/intel_dpio_read.c
> > new file mode 100644
> > index 000..8b924fd
> > --- /dev/null
> > +++ b/tools/intel_dpio_read.c
> > @@ -0,0 +1,105 @@
> > +/*
> > + * Copyright © 2012 Intel Corporation
> > + *
> > + * Permission is hereby granted, free of charge, to any person
> > obtaining a
> > + * copy of this software and associated documentation files (the
> > "Software"),
> > + * to deal in the Software without restriction, including without
> > limitation
> > + * the rights to use, copy, modify, merge, publish, distribute,
> > sublicense,
> > + * and/or sell copies of the Software, and to permit persons to
> > whom the
> > + * Software is furnished to do so, subject to the following
> > conditions:
> > + *
> > + * The above copyright notice and this permission notice
> > (including the next
> > + * paragraph) shall be included in all copies or substantial
> > portions of the
> > + * Software.
> > + *
> > + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
> > EXPRESS OR
> > + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
> > MERCHANTABILITY,
> > + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO
> > EVENT SHALL
> > + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM,
> > DAMAGES OR OTHER
> > + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
> > ARISING
> > + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
> > OTHER
> > + * DEALINGS IN THE SOFTWARE.
> > + *
> > + * Authors:
> > + * Vijay Purushothaman
> >
> > + *
> > + */
> > +
> > +#include
> > +#include
> > +#include
> > +#include
> > +#include
> > +#include "intel_gpu_tools.h"
> > +
> > +#define VLV_DISPLAY_BASE 0x18
> > +#define DPIO_PKT 0x2100
> > +#define DPIO_RID (0 << 24)
> > +#define DPIO_OP_WRITE (1 << 16)
> > +#define DPIO_OP_READ (0 << 16)
> > +#define DPIO_PORTID (0x12 << 8)
> > +#define DPIO_BYTE (0xf << 4)
> > +#define DPIO_BUSY (1 << 0)
> > +#define DPIO_DATA 0x2104
> > +#define DPIO_REG 0x2108
> > +
> > +static uint32_t vlv_display_reg_read(uint32_t reg)
> > +{
> > + reg += VLV_DISPLAY_BASE;
> > + return (*(volatile uint32_t *)((volatile char*)mmio +
> > reg)); +}
> > +
> > +static void vlv_display_reg_write(uint32_t reg, uint32_t val)
> > +{
> > + volatile uint32_t *ptr;
> > +
> > + reg += VLV_DISPLAY_BASE;
> > + ptr = (volatile uint32_t *)((volatile char *) mmio + reg);
> > + *ptr = val;
> > +}
> > +
> > +static void usage(char *cmdname)
> > +{
> > + printf("Warning
Re: [Intel-gfx] [PATCH intel-gpu-tools] tools: Added intel_dpio_read and intel_dpio_write
On Fri, 3 Aug 2012 10:05:41 +0300 Jani Nikula wrote: > On Thu, 02 Aug 2012, Ben Widawsky wrote: > > On 2012-08-02 05:07, Vijay Purushothaman wrote: > >> In Valleyview the DPLL and lane control registers are accessible > >> only through side band fabric called DPIO. Added two tools to read > >> and write > >> registers residing in this space. > > > > Could I convince you to use the centralized read/write mmio > > functions? Otherwise, everything seems fine to me here. > > The introduced intel_dpio_read.c and intel_dpio_write.c files are > almost the same. They could share most of the code instead of > duplication, IMO. > > BR, > Jani. > I would still prefer separate dpio read and write functions more along the lines of intel_reg_read and intel_reg_write. I will move these functions to intel_reg_read.c and intel_reg_write.c based on Ben's feedback. Thanks, Vijay > > > > >> > >> Signed-off-by: Vijay Purushothaman > >> --- > >> tools/Makefile.am|2 + > >> tools/intel_dpio_read.c | 105 > >> ++ > >> tools/intel_dpio_write.c | 103 > >> + > >> 3 files changed, 210 insertions(+) > >> create mode 100644 tools/intel_dpio_read.c > >> create mode 100644 tools/intel_dpio_write.c > >> > >> diff --git a/tools/Makefile.am b/tools/Makefile.am > >> index d461f38..71fb087 100644 > >> --- a/tools/Makefile.am > >> +++ b/tools/Makefile.am > >> @@ -15,6 +15,8 @@ bin_PROGRAMS = \ > >>intel_reg_write \ > >>intel_reg_read \ > >>intel_forcewaked\ > >> + intel_dpio_read \ > >> + intel_dpio_write\ > >>intel_l3_parity > >> > >> noinst_PROGRAMS = \ > >> diff --git a/tools/intel_dpio_read.c b/tools/intel_dpio_read.c > >> new file mode 100644 > >> index 000..8b924fd > >> --- /dev/null > >> +++ b/tools/intel_dpio_read.c > >> @@ -0,0 +1,105 @@ > >> +/* > >> + * Copyright © 2012 Intel Corporation > >> + * > >> + * Permission is hereby granted, free of charge, to any person > >> obtaining a > >> + * copy of this software and associated documentation files (the > >> "Software"), > >> + * to deal in the Software without restriction, including without > >> limitation > >> + * the rights to use, copy, modify, merge, publish, distribute, > >> sublicense, > >> + * and/or sell copies of the Software, and to permit persons to > >> whom the > >> + * Software is furnished to do so, subject to the following > >> conditions: > >> + * > >> + * The above copyright notice and this permission notice > >> (including the next > >> + * paragraph) shall be included in all copies or substantial > >> portions of the > >> + * Software. > >> + * > >> + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, > >> EXPRESS OR > >> + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF > >> MERCHANTABILITY, > >> + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO > >> EVENT SHALL > >> + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, > >> DAMAGES OR OTHER > >> + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR > >> OTHERWISE, ARISING > >> + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR > >> OTHER > >> + * DEALINGS IN THE SOFTWARE. > >> + * > >> + * Authors: > >> + *Vijay Purushothaman > >> > >> + * > >> + */ > >> + > >> +#include > >> +#include > >> +#include > >> +#include > >> +#include > >> +#include "intel_gpu_tools.h" > >> + > >> +#define VLV_DISPLAY_BASE 0x18 > >> +#define DPIO_PKT 0x2100 > >> +#define DPIO_RID (0 << 24) > >> +#define DPIO_OP_WRITE(1 << 16) > >> +#define DPIO_OP_READ (0 << 16) > >> +#define DPIO_PORTID (0x12 << 8) > >> +#define DPIO_BYTE(0xf << 4) > >> +#define DPIO_BUSY
[Intel-gfx] [PATCH intel-gpu-tools] tools: Added intel_dpio_read and intel_dpio_write
In Valleyview the DPLL and lane control registers are accessible only
through side band fabric called DPIO. Added two tools to read and write
registers residing in this space.
v2: Moved the core read/write functions to lib/intel_dpio.c based on
Ben's feedback
Signed-off-by: Vijay Purushothaman
---
lib/Makefile.am |1 +
lib/intel_chipset.h |2 +
lib/intel_dpio.c | 94 ++
lib/intel_gpu_tools.h|3 ++
lib/intel_reg.h | 13 +++
tools/Makefile.am|2 +
tools/intel_dpio_read.c | 68 +
tools/intel_dpio_write.c | 67 +
8 files changed, 250 insertions(+)
create mode 100644 lib/intel_dpio.c
create mode 100644 tools/intel_dpio_read.c
create mode 100644 tools/intel_dpio_write.c
diff --git a/lib/Makefile.am b/lib/Makefile.am
index 88290cb..d8f081f 100644
--- a/lib/Makefile.am
+++ b/lib/Makefile.am
@@ -29,6 +29,7 @@ libintel_tools_la_SOURCES = \
rendercopy_gen7.c \
rendercopy.h\
intel_reg_map.c \
+ intel_dpio.c\
$(NULL)
LDADD = $(CAIRO_LIBS)
diff --git a/lib/intel_chipset.h b/lib/intel_chipset.h
index a229ea1..9dd4c94 100755
--- a/lib/intel_chipset.h
+++ b/lib/intel_chipset.h
@@ -196,6 +196,8 @@
dev == PCI_CHIP_IVYBRIDGE_S_GT2 || \
dev == PCI_CHIP_VALLEYVIEW_PO)
+#define IS_VALLEYVIEW(devid) (devid == PCI_CHIP_VALLEYVIEW_PO)
+
#define IS_HSW_GT1(devid) (devid == PCI_CHIP_HASWELL_GT1 || \
devid == PCI_CHIP_HASWELL_M_GT1 || \
devid == PCI_CHIP_HASWELL_S_GT1 || \
diff --git a/lib/intel_dpio.c b/lib/intel_dpio.c
new file mode 100644
index 000..acfd201
--- /dev/null
+++ b/lib/intel_dpio.c
@@ -0,0 +1,94 @@
+/*
+ * Copyright © 2008 Intel Corporation
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the next
+ * paragraph) shall be included in all copies or substantial portions of the
+ * Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ *
+ * Authors:
+ *Vijay Purushothaman
+ *
+ */
+#include
+#include
+#include
+#include
+#include "intel_gpu_tools.h"
+
+static uint32_t intel_display_reg_read(uint32_t reg)
+{
+ struct pci_device *dev = intel_get_pci_device();
+
+ if (IS_VALLEYVIEW(dev->device_id))
+ reg += VLV_DISPLAY_BASE;
+ return (*(volatile uint32_t*)((volatile char*)mmio + reg));
+}
+
+static void intel_display_reg_write(uint32_t reg, uint32_t val)
+{
+ volatile uint32_t *ptr;
+ struct pci_device *dev = intel_get_pci_device();
+
+ if (IS_VALLEYVIEW(dev->device_id))
+ reg += VLV_DISPLAY_BASE;
+ ptr = (volatile uint32_t*)((volatile char*)mmio + reg);
+ *ptr = val;
+}
+
+/*
+ * In SoCs like Valleyview some of the PLL & Lane control registers
+ * can be accessed only through IO side band fabric called DPIO
+ */
+uint32_t
+intel_dpio_reg_read(uint32_t reg)
+{
+ /* Check whether the side band fabric is ready to accept commands */
+ do {
+ usleep(1);
+ } while (intel_display_reg_read(DPIO_PKT) & DPIO_BUSY);
+
+ intel_display_reg_write(DPIO_REG, reg);
+ intel_display_reg_write(DPIO_PKT, DPIO_RID |
+ DPIO_OP_READ | DPIO_PORTID |
DPIO_BYTE);
+ do {
+ usleep(1);
+ } while (intel_display_reg_read(DPIO_PKT) & DPIO_BUSY);
+
+ return intel_display_reg_read(DPIO_DATA);
+}
+
+/*
+ * In SoCs like Valleyview some of the PLL & Lane control registers
+ * can be accessed only through IO side band fabric called DPIO
+ */
+void
+intel_dpio_reg_write(uint32_t reg, uint32_t val)
+{
+ /* Check whether the side band fabric is ready to accept commands */
+ do {
+ usleep(1);
+ } while (intel_display_reg_read(DPIO_PKT) &
[Intel-gfx] [PATCH] drm/i915: fix color order for BGR formats on IVB
This is already fixed for ILK and SNB but somehow IVB is missed.
Signed-off-by: Vijay Purushothaman
Signed-off-by: Ben Lin
---
drivers/gpu/drm/i915/intel_sprite.c |6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_sprite.c
b/drivers/gpu/drm/i915/intel_sprite.c
index cc8df4d..6045a01 100644
--- a/drivers/gpu/drm/i915/intel_sprite.c
+++ b/drivers/gpu/drm/i915/intel_sprite.c
@@ -54,17 +54,17 @@ ivb_update_plane(struct drm_plane *plane, struct
drm_framebuffer *fb,
/* Mask out pixel format bits in case we change it */
sprctl &= ~SPRITE_PIXFORMAT_MASK;
- sprctl &= ~SPRITE_RGB_ORDER_RGBX;
+ sprctl &= ~SPRITE_RGB_ORDER_XBGR;
sprctl &= ~SPRITE_YUV_BYTE_ORDER_MASK;
sprctl &= ~SPRITE_TILED;
switch (fb->pixel_format) {
case DRM_FORMAT_XBGR:
- sprctl |= SPRITE_FORMAT_RGBX888;
+ sprctl |= SPRITE_FORMAT_RGBX888 | SPRITE_RGB_ORDER_RGBX;
pixel_size = 4;
break;
case DRM_FORMAT_XRGB:
- sprctl |= SPRITE_FORMAT_RGBX888 | SPRITE_RGB_ORDER_RGBX;
+ sprctl |= SPRITE_FORMAT_RGBX888;
pixel_size = 4;
break;
case DRM_FORMAT_YUYV:
--
1.7.9.5
___
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[Intel-gfx] [PATCH v2] drm/i915: fix color order for BGR formats on IVB
This is already fixed for ILK and SNB in the below commit but somehow
IVB is missed.
commit ab2f9df10dd955f1fc0a8650e377588c98f1c029
Author: Jesse Barnes
Date: Mon Feb 27 12:40:10 2012 -0800
drm/i915: fix color order for BGR formats on SNB
Had the wrong bits and field definitions.
Signed-off-by: Vijay Purushothaman
Signed-off-by: Ben Lin
---
drivers/gpu/drm/i915/intel_sprite.c |6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_sprite.c
b/drivers/gpu/drm/i915/intel_sprite.c
index cc8df4d..6045a01 100644
--- a/drivers/gpu/drm/i915/intel_sprite.c
+++ b/drivers/gpu/drm/i915/intel_sprite.c
@@ -54,17 +54,17 @@ ivb_update_plane(struct drm_plane *plane, struct
drm_framebuffer *fb,
/* Mask out pixel format bits in case we change it */
sprctl &= ~SPRITE_PIXFORMAT_MASK;
- sprctl &= ~SPRITE_RGB_ORDER_RGBX;
+ sprctl &= ~SPRITE_RGB_ORDER_XBGR;
sprctl &= ~SPRITE_YUV_BYTE_ORDER_MASK;
sprctl &= ~SPRITE_TILED;
switch (fb->pixel_format) {
case DRM_FORMAT_XBGR:
- sprctl |= SPRITE_FORMAT_RGBX888;
+ sprctl |= SPRITE_FORMAT_RGBX888 | SPRITE_RGB_ORDER_RGBX;
pixel_size = 4;
break;
case DRM_FORMAT_XRGB:
- sprctl |= SPRITE_FORMAT_RGBX888 | SPRITE_RGB_ORDER_RGBX;
+ sprctl |= SPRITE_FORMAT_RGBX888;
pixel_size = 4;
break;
case DRM_FORMAT_YUYV:
--
1.7.9.5
___
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Re: [Intel-gfx] [PATCH] drm/i915: fix color order for BGR formats on IVB
On 8/22/2012 1:19 PM, Paul Menzel wrote: Dear Vijay, Am Mittwoch, den 22.08.2012, 11:47 +0530 schrieb Vijay Purushothaman: This is already fixed for ILK and SNB … in what commits? Added the previous commit number which solved this problem on Sandybridge and description in the second version of the patch. Thanks much for the review. Thanks, Vijay but somehow IVB is missed. Signed-off-by: Vijay Purushothaman Signed-off-by: Ben Lin --- drivers/gpu/drm/i915/intel_sprite.c |6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) […] Please resend as [PATCH v2] with the updated commit message [1]. Thanks, Paul [1] http://wireless.kernel.org/en/developers/Documentation/git-guide#Annotating_new_revision ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH v2] drm/i915: fix color order for BGR formats on IVB
On 8/22/2012 6:30 PM, Antti Koskipää wrote:
Hi,
On 08/22/12 12:17, Vijay Purushothaman wrote:
This is already fixed for ILK and SNB in the below commit but somehow
IVB is missed.
commit ab2f9df10dd955f1fc0a8650e377588c98f1c029
Author: Jesse Barnes
Date: Mon Feb 27 12:40:10 2012 -0800
drm/i915: fix color order for BGR formats on SNB
Had the wrong bits and field definitions.
Signed-off-by: Vijay Purushothaman
Signed-off-by: Ben Lin
---
drivers/gpu/drm/i915/intel_sprite.c |6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_sprite.c
b/drivers/gpu/drm/i915/intel_sprite.c
index cc8df4d..6045a01 100644
--- a/drivers/gpu/drm/i915/intel_sprite.c
+++ b/drivers/gpu/drm/i915/intel_sprite.c
@@ -54,17 +54,17 @@ ivb_update_plane(struct drm_plane *plane, struct
drm_framebuffer *fb,
/* Mask out pixel format bits in case we change it */
sprctl &= ~SPRITE_PIXFORMAT_MASK;
- sprctl &= ~SPRITE_RGB_ORDER_RGBX;
+ sprctl &= ~SPRITE_RGB_ORDER_XBGR;
Are you sure about this? Where is the #define for _XBGR?
Thanks for the catch. I assumed SPRITE_RGB_ORDER_XBGR as defined similar
to DVS_RGB_ORDER_XBGR for SNB. The original code snippet is correct.
sprctl &= ~SPRITE_YUV_BYTE_ORDER_MASK;
sprctl &= ~SPRITE_TILED;
switch (fb->pixel_format) {
case DRM_FORMAT_XBGR:
- sprctl |= SPRITE_FORMAT_RGBX888;
+ sprctl |= SPRITE_FORMAT_RGBX888 | SPRITE_RGB_ORDER_RGBX;
pixel_size = 4;
break;
case DRM_FORMAT_XRGB:
- sprctl |= SPRITE_FORMAT_RGBX888 | SPRITE_RGB_ORDER_RGBX;
+ sprctl |= SPRITE_FORMAT_RGBX888;
pixel_size = 4;
break;
case DRM_FORMAT_YUYV:
___
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[Intel-gfx] [PATCH v3] drm/i915: fix color order for BGR formats on IVB
This is already fixed for ILK and SNB in the below commit but somehow
IVB is missed.
commit ab2f9df10dd955f1fc0a8650e377588c98f1c029
Author: Jesse Barnes
Date: Mon Feb 27 12:40:10 2012 -0800
drm/i915: fix color order for BGR formats on SNB
Had the wrong bits and field definitions.
Signed-off-by: Vijay Purushothaman
---
drivers/gpu/drm/i915/intel_sprite.c |4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_sprite.c
b/drivers/gpu/drm/i915/intel_sprite.c
index cc8df4d..7644f31 100644
--- a/drivers/gpu/drm/i915/intel_sprite.c
+++ b/drivers/gpu/drm/i915/intel_sprite.c
@@ -60,11 +60,11 @@ ivb_update_plane(struct drm_plane *plane, struct
drm_framebuffer *fb,
switch (fb->pixel_format) {
case DRM_FORMAT_XBGR:
- sprctl |= SPRITE_FORMAT_RGBX888;
+ sprctl |= SPRITE_FORMAT_RGBX888 | SPRITE_RGB_ORDER_RGBX;
pixel_size = 4;
break;
case DRM_FORMAT_XRGB:
- sprctl |= SPRITE_FORMAT_RGBX888 | SPRITE_RGB_ORDER_RGBX;
+ sprctl |= SPRITE_FORMAT_RGBX888;
pixel_size = 4;
break;
case DRM_FORMAT_YUYV:
--
1.7.9.5
___
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Re: [Intel-gfx] [PATCH 00/58] modeset-rework, the basic conversion
On 8/20/2012 12:42 AM, Daniel Vetter wrote: Hi all, Changes since last time around: - The prep patches are all merged now. - I've left out the actual DP fixes/cleanups, I think we should merge those in a separte step. - A few bugfixes (thanks to Paulo, Jani and Chris). - I've also applied a few bikesheds for naming that Paulo suggested (but I'm not sure whether I've sent those out already in a previous patchbomb). Essentially this is just the core rework, which addes the new get_hw_state code, refactors all the encoders to use the new functions and finally reworks the modeset logic to disable/enable entire pipes, always (and with a deterministic order). For merging to -next, I plan to pull in everything with a real merge commit. For that reason I've put up a modeset-rework-base branch onto my private fdo repo[1]. That way I can put a short documentation for the new modeset design into the merge commit (stichted together from the previous patchbomb cover letters), documenting my folly assumptions for eternity. I'll also plan to put tags for the entire series in the merge commit, so if you have tested this on a few machines, read through and agree with the new designs, please reply with your tested-by/acked-by/reviewed-by tags. Flames, comments and test reports highly welcome. Cheers, Daniel [1] http://cgit.freedesktop.org/~danvet/drm/log/?h=modeset-rework-base Tested Valleyview X0 eDP, DP, HDMI and VGA before the rebase. Dual display is still work in progress for Valleyview. So, i did not test the combinations like VGA+HDMI or VGA+DP. Tested-by: Vijay Purushothaman Acked-by: Vijay Purushothaman Thanks, Vijay Daniel Vetter (58): drm/i915: add crtc->enable/disable vfuncs insted of dpms drm/i915: rip out crtc prepare/commit indirection drm/i915: add direct encoder disable/enable infrastructure drm/i915/hdmi: convert to encoder->disable/enable drm/i915/tv: convert to encoder enable/disable drm/i915/lvds: convert to encoder disable/enable drm/i915/dp: convert to encoder disable/enable drm/i915/crt: convert to encoder disable/enable drm/i915/sdvo: convert to encoder disable/enable drm/i915/dvo: convert to encoder disable/enable drm/i915: convert dpms functions of dvo/sdvo/crt drm/i915: rip out encoder->disable/enable checks drm/i915: clean up encoder_prepare/commit drm/i915: copy&paste drm_crtc_helper_set_config drm/i915: call set_base directly drm/i915: inline intel_best_encoder drm/i915: copy&paste drm_crtc_helper_set_mode drm/i915: simplify intel_crtc_prepare_encoders drm/i915: rip out encoder->prepare/commit drm/i915: call crtc functions directly drm/i915: WARN when trying to enabled an unused crtc drm/i915: Add interfaces to read out encoder/connector hw state drm/i915/dp: implement get_hw_state drm/i915/hdmi: implement get_hw_state drm/i915/tv: implement get_hw_state drm/i915/lvds: implement get_hw_state drm/i915/crt: implement get_hw_state drm/i915/sdvo: implement get_hw_state drm/i915/dvo: implement get_hw_state drm/i915: read out the modeset hw state at load and resume time drm/i915: check connector hw/sw state drm/i915: rip out intel_crtc->dpms_mode drm/i915: rip out intel_dp->dpms_mode drm/i915: ensure the force pipe A quirk is actually followed drm/i915: introduce struct intel_set_config drm/i915: extract modeset config save/restore code drm/i915: extract intel_set_config_compute_mode_changes drm/i915: extract intel_set_config_update_output_state drm/i915: implement crtc helper semantics relied upon by the fb helper drm/i915: don't update the fb base if there is no fb drm/i915: convert pointless error checks in set_config to BUGs drm/i915: don't save all the encoder/crtc state in set_config drm/i915: stage modeset output changes drm/i915: push crtc->fb update into pipe_set_base drm/i915: remove crtc disabling special case drm/i915: move output commit and crtc disabling into set_mode drm/i915: extract adjusted mode computation drm/i915: use staged outuput config in tv->mode_fixup drm/i915: use staged outuput config in lvds->mode_fixup drm/i915: compute masks of crtcs affected in set_mode drm/i915: implement new set_mode code flow drm/i915: push commit_output_state past crtc disabling drm/i915: s/intel_encoder_disable/intel_encoder_noop drm/i915: WARN if the pipe won't turn off drm/i915: switch the load detect code to the staged modeset config drm/i915: push commit_output_state past the crtc/encoder preparing drm/i915: disable all crtcs at suspend time drm/i915: add tons of modeset state checks drivers/gpu/drm/i915/dvo.h |6 + drivers/gpu/drm/i915/dvo_ch7017.c| 13 + drivers/gpu/drm/i915/dvo_ch7xxx.c| 13 + drivers/gpu/drm/i915/dvo_ivch.c | 15 + drivers/gpu/drm/i915/dvo_ns2501
[Intel-gfx] [PATCH 0/9] Enable all display interfaces in Valleyview
This patch set enables all supported display interfaces like HDMI, DisplayPort and eDP for Valleyview. This also enables support for multi-display configurations. Jesse, Ben : Since this patch set was reviewed in internal mailing lists, could you please add your reviewed-by & tested-by tags? Bhat, Gajanan (1): drm/i915: Enable multi display support in VLV Vijay Purushothaman (8): drm/i915: Set aux clk to 100MHz for Valleyview drm/i915: Fix SDVO IER and status bits for Valleyview drm/i915: Add Valleyview lane control definitions drm/i915: Program correct m n tu register for Valleyview drm/i915: Fix lanecontrol, vswing, preemp for Valleyview DisplayPort drm/i915: Add eDP support for Valleyview drm/i915: panel power sequencing for VLV eDP drm/i915: Reverse min,max vco limits for VLV HDMI drivers/gpu/drm/i915/i915_irq.c |6 +- drivers/gpu/drm/i915/i915_reg.h | 15 +++- drivers/gpu/drm/i915/intel_crt.c |7 ++ drivers/gpu/drm/i915/intel_display.c | 103 --- drivers/gpu/drm/i915/intel_dp.c | 148 -- 5 files changed, 200 insertions(+), 79 deletions(-) -- 1.7.9.5 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 2/9] drm/i915: Fix SDVO IER and status bits for Valleyview
Fixed SDVOB and SDVOC bit definitions for Valleyview.
Signed-off-by: Vijay Purushothaman
Signed-off-by: Ben Widawsky
---
drivers/gpu/drm/i915/i915_irq.c |6 ++
1 file changed, 2 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index d915126..1a974d9 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -2020,7 +2020,6 @@ static int valleyview_irq_postinstall(struct drm_device
*dev)
#endif
I915_WRITE(VLV_MASTER_IER, MASTER_INTERRUPT_ENABLE);
-#if 0 /* FIXME: check register definitions; some have moved */
/* Note HDMI and DP share bits */
if (dev_priv->hotplug_supported_mask & HDMIB_HOTPLUG_INT_STATUS)
hotplug_en |= HDMIB_HOTPLUG_INT_EN;
@@ -2028,15 +2027,14 @@ static int valleyview_irq_postinstall(struct drm_device
*dev)
hotplug_en |= HDMIC_HOTPLUG_INT_EN;
if (dev_priv->hotplug_supported_mask & HDMID_HOTPLUG_INT_STATUS)
hotplug_en |= HDMID_HOTPLUG_INT_EN;
- if (dev_priv->hotplug_supported_mask & SDVOC_HOTPLUG_INT_STATUS)
+ if (dev_priv->hotplug_supported_mask & SDVOC_HOTPLUG_INT_STATUS_I915)
hotplug_en |= SDVOC_HOTPLUG_INT_EN;
- if (dev_priv->hotplug_supported_mask & SDVOB_HOTPLUG_INT_STATUS)
+ if (dev_priv->hotplug_supported_mask & SDVOB_HOTPLUG_INT_STATUS_I915)
hotplug_en |= SDVOB_HOTPLUG_INT_EN;
if (dev_priv->hotplug_supported_mask & CRT_HOTPLUG_INT_STATUS) {
hotplug_en |= CRT_HOTPLUG_INT_EN;
hotplug_en |= CRT_HOTPLUG_VOLTAGE_COMPARE_50;
}
-#endif
I915_WRITE(PORT_HOTPLUG_EN, hotplug_en);
--
1.7.9.5
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[Intel-gfx] [PATCH 1/9] drm/i915: Set aux clk to 100MHz for Valleyview
Set hrawclk to 200 MHz and aux divider clock to 100 MHz for Valleyview.
This enables the aux transactions in Valleyview.
Signed-off-by: Vijay Purushothaman
Signed-off-by: Ben Widawsky
---
drivers/gpu/drm/i915/intel_dp.c |8 +++-
1 file changed, 7 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index a69d9a2..de8092a 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -285,6 +285,10 @@ intel_hrawclk(struct drm_device *dev)
struct drm_i915_private *dev_priv = dev->dev_private;
uint32_t clkcfg;
+ /* There is no CLKCFG reg in Valleyview. VLV hrawclk is 200 MHz */
+ if (IS_VALLEYVIEW(dev))
+ return 200;
+
clkcfg = I915_READ(CLKCFG);
switch (clkcfg & CLKCFG_FSB_MASK) {
case CLKCFG_FSB_400:
@@ -365,7 +369,9 @@ intel_dp_aux_ch(struct intel_dp *intel_dp,
* clock divider.
*/
if (is_cpu_edp(intel_dp)) {
- if (IS_GEN6(dev) || IS_GEN7(dev))
+ if (IS_VALLEYVIEW(dev))
+ aux_clock_divider = 100;
+ else if (IS_GEN6(dev) || IS_GEN7(dev))
aux_clock_divider = 200; /* SNB & IVB eDP input clock
at 400Mhz */
else
aux_clock_divider = 225; /* eDP input clock at 450Mhz */
--
1.7.9.5
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[Intel-gfx] [PATCH 3/9] drm/i915: Add Valleyview lane control definitions
Added DPIO data lane register definitions for Valleyview Signed-off-by: Vijay Purushothaman Signed-off-by: Ben Widawsky --- drivers/gpu/drm/i915/i915_reg.h |8 1 file changed, 8 insertions(+) diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index a828e90..3f75ee6 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -369,6 +369,7 @@ #define DPIO_PLL_MODESEL_SHIFT 24 /* 3 bits */ #define DPIO_BIAS_CURRENT_CTL_SHIFT 21 /* 3 bits, always 0x7 */ #define DPIO_PLL_REFCLK_SEL_SHIFT16 /* 2 bits */ +#define DPIO_PLL_REFCLK_SEL_MASK 3 #define DPIO_DRIVER_CTL_SHIFT12 /* always set to 0x8 */ #define DPIO_CLK_BIAS_CTL_SHIFT 8 /* always set to 0x5 */ #define _DPIO_REFSFR_B 0x8034 @@ -384,6 +385,13 @@ #define DPIO_FASTCLK_DISABLE 0x8100 +#define _DPIO_DATA_LANE0 0x0220 +#define _DPIO_DATA_LANE1 0x0420 +#define _DPIO_DATA_LANE2 0x2620 +#define _DPIO_DATA_LANE3 0x2820 +#define DPIO_DATA_LANE_A(pipe) _PIPE(pipe, _DPIO_DATA_LANE0, _DPIO_DATA_LANE2) +#define DPIO_DATA_LANE_B(pipe) _PIPE(pipe, _DPIO_DATA_LANE1, _DPIO_DATA_LANE3) + /* * Fence registers */ -- 1.7.9.5 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 5/9] drm/i915: Fix lanecontrol, vswing, preemp for Valleyview DisplayPort
In Valleyview voltage swing, pre-emphasis and lane control registers can
be programmed only through the h/w side band fabric. Also use
i9xx_update_pll to program the correct DPLL sequence.
Signed-off-by: Vijay Purushothaman
Signed-off-by: Gajanan Bhat
Signed-off-by: Ben Widawsky
---
drivers/gpu/drm/i915/intel_crt.c |7 ++
drivers/gpu/drm/i915/intel_display.c | 44 --
2 files changed, 44 insertions(+), 7 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_crt.c b/drivers/gpu/drm/i915/intel_crt.c
index c42b980..bd23bdf 100644
--- a/drivers/gpu/drm/i915/intel_crt.c
+++ b/drivers/gpu/drm/i915/intel_crt.c
@@ -308,6 +308,13 @@ static bool valleyview_crt_detect_hotplug(struct
drm_connector *connector)
bool ret;
u32 save_adpa;
+ /*
+* Disable crt detect hotplug for VLV X0. spurious hot plug
+* detect calls crashes the X0 system
+*/
+ if (IS_VALLEYVIEW(dev))
+ return false;
+
save_adpa = adpa = I915_READ(ADPA);
DRM_DEBUG_KMS("trigger hotplug detect cycle: adpa=0x%x\n", adpa);
diff --git a/drivers/gpu/drm/i915/intel_display.c
b/drivers/gpu/drm/i915/intel_display.c
index 68828e7..a8a81d1 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -3944,6 +3944,10 @@ static void i9xx_update_pll_dividers(struct drm_crtc
*crtc,
int pipe = intel_crtc->pipe;
u32 fp, fp2 = 0;
+ /* Disable FP0 register programming for VLV X0 */
+ if (IS_VALLEYVIEW(dev))
+ return;
+
if (IS_PINEVIEW(dev)) {
fp = (1 << clock->n) << 16 | clock->m1 << 8 | clock->m2;
if (reduced_clock)
@@ -4051,12 +4055,13 @@ static void vlv_update_pll(struct drm_crtc *crtc,
intel_dpio_write(dev_priv, DPIO_CORE_CLK(pipe), 0x0100);
- pdiv = DPIO_REFSEL_OVERRIDE | (5 << DPIO_PLL_MODESEL_SHIFT) |
+ pdiv = (1 << DPIO_REFSEL_OVERRIDE) | (5 << DPIO_PLL_MODESEL_SHIFT) |
(3 << DPIO_BIAS_CURRENT_CTL_SHIFT) | (1<<20) |
- (8 << DPIO_DRIVER_CTL_SHIFT) | (5 << DPIO_CLK_BIAS_CTL_SHIFT);
+ (7 << DPIO_PLL_REFCLK_SEL_SHIFT) | (8 << DPIO_DRIVER_CTL_SHIFT)
|
+ (5 << DPIO_CLK_BIAS_CTL_SHIFT);
intel_dpio_write(dev_priv, DPIO_REFSFR(pipe), pdiv);
- intel_dpio_write(dev_priv, DPIO_LFP_COEFF(pipe), 0x009f0051);
+ intel_dpio_write(dev_priv, DPIO_LFP_COEFF(pipe), 0x005f003b);
dpll |= DPLL_VCO_ENABLE;
I915_WRITE(DPLL(pipe), dpll);
@@ -4076,7 +4081,7 @@ static void vlv_update_pll(struct drm_crtc *crtc,
POSTING_READ(DPLL_MD(pipe));
}
- intel_dpio_write(dev_priv, DPIO_FASTCLK_DISABLE, 0x641); /* ??? */
+ intel_dpio_write(dev_priv, DPIO_FASTCLK_DISABLE, 0x620);
}
static void i9xx_update_pll(struct drm_crtc *crtc,
@@ -4112,6 +4117,12 @@ static void i9xx_update_pll(struct drm_crtc *crtc,
if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT))
dpll |= DPLL_DVO_HIGH_SPEED;
+ if (IS_VALLEYVIEW(dev)) {
+ dpll |= DPLL_EXT_BUFFER_ENABLE_VLV;
+ dpll |= DPLL_REFA_CLK_ENABLE_VLV;
+ dpll |= DPLL_INTEGRATED_CLOCK_VLV;
+ }
+
/* compute bitmask from p1 value */
if (IS_PINEVIEW(dev))
dpll |= (1 << (clock->p1 - 1)) <<
DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW;
@@ -4152,6 +4163,17 @@ static void i9xx_update_pll(struct drm_crtc *crtc,
dpll |= DPLL_VCO_ENABLE;
I915_WRITE(DPLL(pipe), dpll & ~DPLL_VCO_ENABLE);
POSTING_READ(DPLL(pipe));
+
+ /*
+* In Valleyview PLL and program lane counter registes are exposed
+* through DPIO interface
+*/
+ if (IS_VALLEYVIEW(dev)) {
+ int refclk;
+ refclk = i9xx_get_refclk(crtc, num_connectors);
+ vlv_update_pll(crtc, mode, adjusted_mode, clock, NULL, refclk,
+ num_connectors);
+ }
udelay(150);
/* The LVDS pin pair needs to be on before the DPLLs are enabled.
@@ -4170,6 +4192,17 @@ static void i9xx_update_pll(struct drm_crtc *crtc,
POSTING_READ(DPLL(pipe));
udelay(150);
+ /* Now program lane control registers for Valleyview */
+ if (IS_VALLEYVIEW(dev)) {
+ u32 temp = 0;
+ temp = intel_dpio_read(dev_priv, DPIO_DATA_LANE_A(pipe));
+ temp |= (1 << 20);
+ intel_dpio_write(dev_priv, DPIO_DATA_LANE_A(pipe), temp);
+ temp = intel_dpio_read(dev_priv, DPIO_DATA_LANE_B(pipe));
+ temp |= (1 << 20);
+ intel_dpio_write(dev_priv, DPIO_DATA_LANE_B(pipe), temp);
+ }
+
if (INTEL_INFO(dev)->gen >= 4) {
u32 temp
[Intel-gfx] [PATCH 4/9] drm/i915: Program correct m n tu register for Valleyview
m n tu register offset has changed in Valleyview. Also fixed DP limit
frequencies.
Signed-off-by: Vijay Purushothaman
Signed-off-by: Ben Widawsky
---
drivers/gpu/drm/i915/intel_display.c |6 +++---
drivers/gpu/drm/i915/intel_dp.c |5 +
2 files changed, 8 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_display.c
b/drivers/gpu/drm/i915/intel_display.c
index 947c97d..68828e7 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -393,10 +393,10 @@ static const intel_limit_t intel_limits_vlv_hdmi = {
};
static const intel_limit_t intel_limits_vlv_dp = {
- .dot = { .min = 162000, .max = 27 },
- .vco = { .min = 5994000, .max = 400 },
+ .dot = { .min = 25000, .max = 27 },
+ .vco = { .min = 400, .max = 600 },
.n = { .min = 1, .max = 7 },
- .m = { .min = 60, .max = 300 }, /* guess */
+ .m = { .min = 22, .max = 450 },
.m1 = { .min = 2, .max = 3 },
.m2 = { .min = 11, .max = 156 },
.p = { .min = 10, .max = 30 },
diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index de8092a..c111c3f 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -804,6 +804,11 @@ intel_dp_set_m_n(struct drm_crtc *crtc, struct
drm_display_mode *mode,
I915_WRITE(TRANSDATA_N1(pipe), m_n.gmch_n);
I915_WRITE(TRANSDPLINK_M1(pipe), m_n.link_m);
I915_WRITE(TRANSDPLINK_N1(pipe), m_n.link_n);
+ } else if (IS_VALLEYVIEW(dev)) {
+ I915_WRITE(PIPE_DATA_M1(pipe), TU_SIZE(m_n.tu) | m_n.gmch_m);
+ I915_WRITE(PIPE_DATA_N1(pipe), m_n.gmch_n);
+ I915_WRITE(PIPE_LINK_M1(pipe), m_n.link_m);
+ I915_WRITE(PIPE_LINK_N1(pipe), m_n.link_n);
} else {
I915_WRITE(PIPE_GMCH_DATA_M(pipe),
((m_n.tu - 1) << PIPE_GMCH_DATA_M_TU_SIZE_SHIFT) |
--
1.7.9.5
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[Intel-gfx] [PATCH 7/9] drm/i915: panel power sequencing for VLV eDP
PPS register offsets have changed in Valleyview.
Signed-off-by: Gajanan Bhat
Signed-off-by: Vijay Purushothaman
Signed-off-by: Ben Widawsky
---
drivers/gpu/drm/i915/i915_reg.h |9 +++
drivers/gpu/drm/i915/intel_dp.c | 122 +++
2 files changed, 93 insertions(+), 38 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 3f75ee6..e421847 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -3981,6 +3981,15 @@
#define PIPEB_PP_ON_DELAYS 0x61308
#define PIPEB_PP_OFF_DELAYS 0x6130c
#define PIPEB_PP_DIVISOR0x61310
+#define VLV_PIPE_PP_STATUS(pipe) _PIPE(pipe, PIPEA_PP_STATUS, PIPEB_PP_STATUS)
+#define VLV_PIPE_PP_CONTROL(pipe) _PIPE(pipe, PIPEA_PP_CONTROL,
PIPEB_PP_CONTROL)
+#define VLV_PIPE_PP_ON_DELAYS(pipe) \
+ _PIPE(pipe, PIPEA_PP_ON_DELAYS, PIPEB_PP_ON_DELAYS)
+#define VLV_PIPE_PP_OFF_DELAYS(pipe) \
+ _PIPE(pipe, PIPEA_PP_OFF_DELAYS, PIPEB_PP_OFF_DELAYS)
+#define VLV_PIPE_PP_DIVISOR(pipe) \
+ _PIPE(pipe, PIPEA_PP_DIVISOR, PIPEB_PP_DIVISOR)
+
#define PCH_PP_STATUS 0xc7200
#define PCH_PP_CONTROL 0xc7204
diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index af57027..b944529 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -316,16 +316,20 @@ static bool ironlake_edp_have_panel_power(struct intel_dp
*intel_dp)
{
struct drm_device *dev = intel_dp->base.base.dev;
struct drm_i915_private *dev_priv = dev->dev_private;
+ u32 pp_stat_reg;
- return (I915_READ(PCH_PP_STATUS) & PP_ON) != 0;
+ pp_stat_reg = IS_VALLEYVIEW(dev) ? PIPEA_PP_STATUS : PCH_PP_STATUS;
+ return (I915_READ(pp_stat_reg) & PP_ON) != 0;
}
static bool ironlake_edp_have_panel_vdd(struct intel_dp *intel_dp)
{
struct drm_device *dev = intel_dp->base.base.dev;
struct drm_i915_private *dev_priv = dev->dev_private;
+ u32 pp_ctrl_reg;
- return (I915_READ(PCH_PP_CONTROL) & EDP_FORCE_VDD) != 0;
+ pp_ctrl_reg = IS_VALLEYVIEW(dev) ? PIPEA_PP_CONTROL : PCH_PP_CONTROL;
+ return (I915_READ(pp_ctrl_reg) & EDP_FORCE_VDD) != 0;
}
static void
@@ -333,14 +337,19 @@ intel_dp_check_edp(struct intel_dp *intel_dp)
{
struct drm_device *dev = intel_dp->base.base.dev;
struct drm_i915_private *dev_priv = dev->dev_private;
+ u32 pp_stat_reg, pp_ctrl_reg;
if (!is_edp(intel_dp))
return;
+
+ pp_stat_reg = IS_VALLEYVIEW(dev) ? PIPEA_PP_STATUS : PCH_PP_STATUS;
+ pp_ctrl_reg = IS_VALLEYVIEW(dev) ? PIPEA_PP_CONTROL : PCH_PP_CONTROL;
+
if (!ironlake_edp_have_panel_power(intel_dp) &&
!ironlake_edp_have_panel_vdd(intel_dp)) {
WARN(1, "eDP powered off while attempting aux channel
communication.\n");
DRM_DEBUG_KMS("Status 0x%08x Control 0x%08x\n",
- I915_READ(PCH_PP_STATUS),
- I915_READ(PCH_PP_CONTROL));
+ I915_READ(pp_stat_reg),
+ I915_READ(pp_ctrl_reg));
}
}
@@ -944,16 +953,20 @@ static void ironlake_wait_panel_status(struct intel_dp
*intel_dp,
{
struct drm_device *dev = intel_dp->base.base.dev;
struct drm_i915_private *dev_priv = dev->dev_private;
+ u32 pp_stat_reg, pp_ctrl_reg;
+
+ pp_stat_reg = IS_VALLEYVIEW(dev) ? PIPEA_PP_STATUS : PCH_PP_STATUS;
+ pp_ctrl_reg = IS_VALLEYVIEW(dev) ? PIPEA_PP_CONTROL : PCH_PP_CONTROL;
DRM_DEBUG_KMS("mask %08x value %08x status %08x control %08x\n",
- mask, value,
- I915_READ(PCH_PP_STATUS),
- I915_READ(PCH_PP_CONTROL));
+ mask, value,
+ I915_READ(pp_stat_reg),
+ I915_READ(pp_ctrl_reg));
- if (_wait_for((I915_READ(PCH_PP_STATUS) & mask) == value, 5000, 10)) {
+ if (_wait_for((I915_READ(pp_stat_reg) & mask) == value, 5000, 10)) {
DRM_ERROR("Panel status timeout: status %08x control %08x\n",
- I915_READ(PCH_PP_STATUS),
- I915_READ(PCH_PP_CONTROL));
+ I915_READ(pp_stat_reg),
+ I915_READ(pp_ctrl_reg));
}
}
@@ -980,9 +993,15 @@ static void ironlake_wait_panel_power_cycle(struct
intel_dp *intel_dp)
* is locked
*/
-static u32 ironlake_get_pp_control(struct drm_i915_private *dev_priv)
+static u32 ironlake_get_pp_control(struct intel_dp *intel_dp)
{
- u32 control = I915_READ(PCH_PP_CONTROL);
+ struct drm_device *dev = intel_dp->base.base.dev;
+ struct drm_i915_private *dev_priv = dev->dev_private;
+ u32 control;
+
[Intel-gfx] [PATCH 6/9] drm/i915: Add eDP support for Valleyview
Eventhough Valleyview display block is derived from Cantiga, VLV
supports eDP. So, added eDP checks in i9xx_crtc_mode_set path.
v2: use different DPIO_DIVISOR values for VGA, DP and eDP
v3: fix DPIO value calculation to use same values for all display
interfaces
Signed-off-by: Gajanan Bhat
Signed-off-by: Vijay Purushothaman
Signed-off-by: Ben Widawsky
---
drivers/gpu/drm/i915/intel_display.c |6 ++
drivers/gpu/drm/i915/intel_dp.c | 13 -
2 files changed, 14 insertions(+), 5 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_display.c
b/drivers/gpu/drm/i915/intel_display.c
index a8a81d1..aee6151 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -4405,6 +4405,12 @@ static int i9xx_crtc_mode_set(struct drm_crtc *crtc,
}
}
+ if (IS_VALLEYVIEW(dev) && intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP)) {
+ pipeconf |= PIPECONF_BPP_6 |
+ PIPECONF_ENABLE |
+ I965_PIPECONF_ACTIVE;
+ }
+
DRM_DEBUG_KMS("Mode for pipe %c:\n", pipe == 0 ? 'A' : 'B');
drm_mode_debug_printmodeline(mode);
diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index c111c3f..af57027 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -885,7 +885,7 @@ intel_dp_mode_set(struct drm_encoder *encoder, struct
drm_display_mode *mode,
/* Split out the IBX/CPU vs CPT settings */
- if (is_cpu_edp(intel_dp) && IS_GEN7(dev)) {
+ if (is_cpu_edp(intel_dp) && IS_GEN7(dev) && !IS_VALLEYVIEW(dev)) {
if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
intel_dp->DP |= DP_SYNC_HS_HIGH;
if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
@@ -1474,7 +1474,7 @@ intel_dp_pre_emphasis_max(struct intel_dp *intel_dp,
uint8_t voltage_swing)
{
struct drm_device *dev = intel_dp->base.base.dev;
- if (IS_GEN7(dev) && is_cpu_edp(intel_dp)) {
+ if (IS_GEN7(dev) && is_cpu_edp(intel_dp) && !IS_VALLEYVIEW(dev)) {
switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
case DP_TRAIN_VOLTAGE_SWING_400:
return DP_TRAIN_PRE_EMPHASIS_6;
@@ -1773,7 +1773,7 @@ intel_dp_start_link_train(struct intel_dp *intel_dp)
uint32_tsignal_levels;
- if (IS_GEN7(dev) && is_cpu_edp(intel_dp)) {
+ if (IS_GEN7(dev) && is_cpu_edp(intel_dp) &&
!IS_VALLEYVIEW(dev)) {
signal_levels =
intel_gen7_edp_signal_levels(intel_dp->train_set[0]);
DP = (DP & ~EDP_LINK_TRAIN_VOL_EMP_MASK_IVB) |
signal_levels;
} else if (IS_GEN6(dev) && is_cpu_edp(intel_dp)) {
@@ -1859,7 +1859,7 @@ intel_dp_complete_link_train(struct intel_dp *intel_dp)
break;
}
- if (IS_GEN7(dev) && is_cpu_edp(intel_dp)) {
+ if (IS_GEN7(dev) && is_cpu_edp(intel_dp) &&
!IS_VALLEYVIEW(dev)) {
signal_levels =
intel_gen7_edp_signal_levels(intel_dp->train_set[0]);
DP = (DP & ~EDP_LINK_TRAIN_VOL_EMP_MASK_IVB) |
signal_levels;
} else if (IS_GEN6(dev) && is_cpu_edp(intel_dp)) {
@@ -2471,7 +2471,10 @@ intel_dp_init(struct drm_device *dev, int output_reg,
enum port port)
if (intel_dpd_is_edp(dev))
intel_dp->is_pch_edp = true;
- if (output_reg == DP_A || is_pch_edp(intel_dp)) {
+ if (IS_VALLEYVIEW(dev) && output_reg == DP_C) {
+ type = DRM_MODE_CONNECTOR_eDP;
+ intel_encoder->type = INTEL_OUTPUT_EDP;
+ } else if (output_reg == DP_A || is_pch_edp(intel_dp)) {
type = DRM_MODE_CONNECTOR_eDP;
intel_encoder->type = INTEL_OUTPUT_EDP;
} else {
--
1.7.9.5
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[Intel-gfx] [PATCH 8/9] drm/i915: Reverse min, max vco limits for VLV HDMI
Fixed min, max vco limits for VLV HDMI. Also fixed correct register
offset for VLV_VIDEO_DIP_CTL_A
Signed-off-by: Vijay Purushothaman
Signed-off-by: Gajanan Bhat
Signed-off-by: Ben Widawsky
---
drivers/gpu/drm/i915/i915_reg.h |2 +-
drivers/gpu/drm/i915/intel_display.c |2 +-
2 files changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index e421847..d4ed30e 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -3687,7 +3687,7 @@
#define TVIDEO_DIP_DATA(pipe) _PIPE(pipe, _VIDEO_DIP_DATA_A, _VIDEO_DIP_DATA_B)
#define TVIDEO_DIP_GCP(pipe) _PIPE(pipe, _VIDEO_DIP_GCP_A, _VIDEO_DIP_GCP_B)
-#define VLV_VIDEO_DIP_CTL_A0x60220
+#define VLV_VIDEO_DIP_CTL_A0x60200
#define VLV_VIDEO_DIP_DATA_A 0x60208
#define VLV_VIDEO_DIP_GDCP_PAYLOAD_A 0x60210
diff --git a/drivers/gpu/drm/i915/intel_display.c
b/drivers/gpu/drm/i915/intel_display.c
index aee6151..647e311 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -380,7 +380,7 @@ static const intel_limit_t intel_limits_vlv_dac = {
static const intel_limit_t intel_limits_vlv_hdmi = {
.dot = { .min = 2, .max = 165000 },
- .vco = { .min = 5994000, .max = 400 },
+ .vco = { .min = 400, .max = 5994000},
.n = { .min = 1, .max = 7 },
.m = { .min = 60, .max = 300 }, /* guess */
.m1 = { .min = 2, .max = 3 },
--
1.7.9.5
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[Intel-gfx] [PATCH 9/9] drm/i915: Enable multi display support in VLV
From: "Bhat, Gajanan"
Clened up DPLL calculations for Valleyview. Moved DPLL register and DPIO
programming to vlv_update_pll function. With all the changes multi
display (clone, extended desktop) should work for VLV.
Signed-off-by: Gajanan Bhat
---
drivers/gpu/drm/i915/i915_reg.h |8 +--
drivers/gpu/drm/i915/intel_display.c | 105 ++
2 files changed, 58 insertions(+), 55 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index d4ed30e..71aa0a7 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -385,12 +385,8 @@
#define DPIO_FASTCLK_DISABLE 0x8100
-#define _DPIO_DATA_LANE0 0x0220
-#define _DPIO_DATA_LANE1 0x0420
-#define _DPIO_DATA_LANE2 0x2620
-#define _DPIO_DATA_LANE3 0x2820
-#define DPIO_DATA_LANE_A(pipe) _PIPE(pipe, _DPIO_DATA_LANE0, _DPIO_DATA_LANE2)
-#define DPIO_DATA_LANE_B(pipe) _PIPE(pipe, _DPIO_DATA_LANE1, _DPIO_DATA_LANE3)
+#define DPIO_DATA_CHANNEL1 0x8220
+#define DPIO_DATA_CHANNEL2 0x8420
/*
* Fence registers
diff --git a/drivers/gpu/drm/i915/intel_display.c
b/drivers/gpu/drm/i915/intel_display.c
index 647e311..e933031 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -4018,10 +4018,10 @@ static void intel_update_lvds(struct drm_crtc *crtc,
intel_clock_t *clock,
}
static void vlv_update_pll(struct drm_crtc *crtc,
- struct drm_display_mode *mode,
- struct drm_display_mode *adjusted_mode,
- intel_clock_t *clock, intel_clock_t *reduced_clock,
- int refclk, int num_connectors)
+ struct drm_display_mode *mode,
+ struct drm_display_mode *adjusted_mode,
+ intel_clock_t *clock, intel_clock_t *reduced_clock,
+ int num_connectors)
{
struct drm_device *dev = crtc->dev;
struct drm_i915_private *dev_priv = dev->dev_private;
@@ -4029,9 +4029,19 @@ static void vlv_update_pll(struct drm_crtc *crtc,
int pipe = intel_crtc->pipe;
u32 dpll, mdiv, pdiv;
u32 bestn, bestm1, bestm2, bestp1, bestp2;
- bool is_hdmi;
+ bool is_sdvo;
+ u32 temp;
- is_hdmi = intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI);
+ is_sdvo = intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO) ||
+ intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI);
+
+ dpll = DPLL_VGA_MODE_DIS;
+ dpll |= DPLL_EXT_BUFFER_ENABLE_VLV;
+ dpll |= DPLL_REFA_CLK_ENABLE_VLV;
+ dpll |= DPLL_INTEGRATED_CLOCK_VLV;
+
+ I915_WRITE(DPLL(pipe), dpll);
+ POSTING_READ(DPLL(pipe));
bestn = clock->n;
bestm1 = clock->m1;
@@ -4039,12 +4049,10 @@ static void vlv_update_pll(struct drm_crtc *crtc,
bestp1 = clock->p1;
bestp2 = clock->p2;
- /* Enable DPIO clock input */
- dpll = DPLL_EXT_BUFFER_ENABLE_VLV | DPLL_REFA_CLK_ENABLE_VLV |
- DPLL_VGA_MODE_DIS | DPLL_INTEGRATED_CLOCK_VLV;
- I915_WRITE(DPLL(pipe), dpll);
- POSTING_READ(DPLL(pipe));
-
+ /*
+* In Valleyview PLL and program lane counter registes are exposed
+* through DPIO interface
+*/
mdiv = ((bestm1 << DPIO_M1DIV_SHIFT) | (bestm2 & DPIO_M2DIV_MASK));
mdiv |= ((bestp1 << DPIO_P1_SHIFT) | (bestp2 << DPIO_P2_SHIFT));
mdiv |= ((bestn << DPIO_N_SHIFT));
@@ -4069,21 +4077,47 @@ static void vlv_update_pll(struct drm_crtc *crtc,
if (wait_for(((I915_READ(DPLL(pipe)) & DPLL_LOCK_VLV) ==
DPLL_LOCK_VLV), 1))
DRM_ERROR("DPLL %d failed to lock\n", pipe);
- if (is_hdmi) {
- u32 temp = intel_mode_get_pixel_multiplier(adjusted_mode);
+ intel_dpio_write(dev_priv, DPIO_FASTCLK_DISABLE, 0x620);
+
+ if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT))
+ intel_dp_set_m_n(crtc, mode, adjusted_mode);
+
+ I915_WRITE(DPLL(pipe), dpll);
+
+ /* Wait for the clocks to stabilize. */
+ POSTING_READ(DPLL(pipe));
+ udelay(150);
+ temp = 0;
+ if (is_sdvo) {
+ temp = intel_mode_get_pixel_multiplier(adjusted_mode);
if (temp > 1)
temp = (temp - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT;
else
temp = 0;
-
- I915_WRITE(DPLL_MD(pipe), temp);
- POSTING_READ(DPLL_MD(pipe));
}
+ I915_WRITE(DPLL_MD(pipe), temp);
+ POSTING_READ(DPLL_MD(pipe));
- intel_dpio_write(dev_priv, DPIO_FASTCLK_DISABLE, 0x620);
+ /* Now program lane control registers */
+ if(intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)
+ || intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI))
+ {
+ temp = 0x10
Re: [Intel-gfx] [PATCH 5/9] drm/i915: Fix lanecontrol, vswing, preemp for Valleyview DisplayPort
On 9/26/2012 7:54 PM, Daniel Vetter wrote:
On Wed, Sep 26, 2012 at 07:07:34PM +0530, Vijay Purushothaman wrote:
In Valleyview voltage swing, pre-emphasis and lane control registers can
be programmed only through the h/w side band fabric. Also use
i9xx_update_pll to program the correct DPLL sequence.
Signed-off-by: Vijay Purushothaman
Signed-off-by: Gajanan Bhat
Signed-off-by: Ben Widawsky
---
drivers/gpu/drm/i915/intel_crt.c |7 ++
drivers/gpu/drm/i915/intel_display.c | 44 --
2 files changed, 44 insertions(+), 7 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_crt.c b/drivers/gpu/drm/i915/intel_crt.c
index c42b980..bd23bdf 100644
--- a/drivers/gpu/drm/i915/intel_crt.c
+++ b/drivers/gpu/drm/i915/intel_crt.c
@@ -308,6 +308,13 @@ static bool valleyview_crt_detect_hotplug(struct
drm_connector *connector)
bool ret;
u32 save_adpa;
+ /*
+* Disable crt detect hotplug for VLV X0. spurious hot plug
+* detect calls crashes the X0 system
+*/
+ if (IS_VALLEYVIEW(dev))
+ return false;
This hunk here belongs into a different patch.
Sure. I will move this hunk as a separate patch.
+
save_adpa = adpa = I915_READ(ADPA);
DRM_DEBUG_KMS("trigger hotplug detect cycle: adpa=0x%x\n", adpa);
diff --git a/drivers/gpu/drm/i915/intel_display.c
b/drivers/gpu/drm/i915/intel_display.c
index 68828e7..a8a81d1 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -3944,6 +3944,10 @@ static void i9xx_update_pll_dividers(struct drm_crtc
*crtc,
int pipe = intel_crtc->pipe;
u32 fp, fp2 = 0;
+ /* Disable FP0 register programming for VLV X0 */
+ if (IS_VALLEYVIEW(dev))
+ return;
This patch folds back the vlv_update_pll function into the i9xx_update_pll
function, which is imo the wrong approach (since you add quite some if
(IS_VLV) blocks). Better would be to move the i9xx_update_pll_dividers
into i8xx_update_pll and i9xx_update_pll and then keep the vlv_update_pll
(and only apply the necessary fixes there.
-Daniel
)
Done.
+
if (IS_PINEVIEW(dev)) {
fp = (1 << clock->n) << 16 | clock->m1 << 8 | clock->m2;
if (reduced_clock)
@@ -4051,12 +4055,13 @@ static void vlv_update_pll(struct drm_crtc *crtc,
intel_dpio_write(dev_priv, DPIO_CORE_CLK(pipe), 0x0100);
- pdiv = DPIO_REFSEL_OVERRIDE | (5 << DPIO_PLL_MODESEL_SHIFT) |
+ pdiv = (1 << DPIO_REFSEL_OVERRIDE) | (5 << DPIO_PLL_MODESEL_SHIFT) |
(3 << DPIO_BIAS_CURRENT_CTL_SHIFT) | (1<<20) |
- (8 << DPIO_DRIVER_CTL_SHIFT) | (5 << DPIO_CLK_BIAS_CTL_SHIFT);
+ (7 << DPIO_PLL_REFCLK_SEL_SHIFT) | (8 << DPIO_DRIVER_CTL_SHIFT)
|
+ (5 << DPIO_CLK_BIAS_CTL_SHIFT);
intel_dpio_write(dev_priv, DPIO_REFSFR(pipe), pdiv);
- intel_dpio_write(dev_priv, DPIO_LFP_COEFF(pipe), 0x009f0051);
+ intel_dpio_write(dev_priv, DPIO_LFP_COEFF(pipe), 0x005f003b);
dpll |= DPLL_VCO_ENABLE;
I915_WRITE(DPLL(pipe), dpll);
@@ -4076,7 +4081,7 @@ static void vlv_update_pll(struct drm_crtc *crtc,
POSTING_READ(DPLL_MD(pipe));
}
- intel_dpio_write(dev_priv, DPIO_FASTCLK_DISABLE, 0x641); /* ??? */
+ intel_dpio_write(dev_priv, DPIO_FASTCLK_DISABLE, 0x620);
}
static void i9xx_update_pll(struct drm_crtc *crtc,
@@ -4112,6 +4117,12 @@ static void i9xx_update_pll(struct drm_crtc *crtc,
if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT))
dpll |= DPLL_DVO_HIGH_SPEED;
+ if (IS_VALLEYVIEW(dev)) {
+ dpll |= DPLL_EXT_BUFFER_ENABLE_VLV;
+ dpll |= DPLL_REFA_CLK_ENABLE_VLV;
+ dpll |= DPLL_INTEGRATED_CLOCK_VLV;
+ }
+
/* compute bitmask from p1 value */
if (IS_PINEVIEW(dev))
dpll |= (1 << (clock->p1 - 1)) <<
DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW;
@@ -4152,6 +4163,17 @@ static void i9xx_update_pll(struct drm_crtc *crtc,
dpll |= DPLL_VCO_ENABLE;
I915_WRITE(DPLL(pipe), dpll & ~DPLL_VCO_ENABLE);
POSTING_READ(DPLL(pipe));
+
+ /*
+* In Valleyview PLL and program lane counter registes are exposed
+* through DPIO interface
+*/
+ if (IS_VALLEYVIEW(dev)) {
+ int refclk;
+ refclk = i9xx_get_refclk(crtc, num_connectors);
+ vlv_update_pll(crtc, mode, adjusted_mode, clock, NULL, refclk,
+ num_connectors);
+ }
udelay(150);
/* The LVDS pin pair needs to be on before the DPLLs are enabled.
@@ -4170,6 +4192,17 @@ static void i9xx_update_pll(struct drm_crtc *crtc,
POSTING_READ(DPLL(pipe));
udelay(150);
+ /* Now program lane c
Re: [Intel-gfx] [PATCH 8/9] drm/i915: Reverse min, max vco limits for VLV HDMI
On 9/26/2012 8:08 PM, Daniel Vetter wrote:
On Wed, Sep 26, 2012 at 07:07:37PM +0530, Vijay Purushothaman wrote:
Fixed min, max vco limits for VLV HDMI. Also fixed correct register
offset for VLV_VIDEO_DIP_CTL_A
Signed-off-by: Vijay Purushothaman
Signed-off-by: Gajanan Bhat
Signed-off-by: Ben Widawsky
Patch splitup bikeshed: Either split up the dip reg fix into its own
patch, or make the commit headline more generic (e.g "fixup HDMI output on
vlv") with the details of the fix ("fixup vco limits and dip ctl reg") in
the commit message. I'll bikeshed the headline when applying.
-Daniel
I will change the commit headline. Thanks.
---
drivers/gpu/drm/i915/i915_reg.h |2 +-
drivers/gpu/drm/i915/intel_display.c |2 +-
2 files changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index e421847..d4ed30e 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -3687,7 +3687,7 @@
#define TVIDEO_DIP_DATA(pipe) _PIPE(pipe, _VIDEO_DIP_DATA_A,
_VIDEO_DIP_DATA_B)
#define TVIDEO_DIP_GCP(pipe) _PIPE(pipe, _VIDEO_DIP_GCP_A, _VIDEO_DIP_GCP_B)
-#define VLV_VIDEO_DIP_CTL_A0x60220
+#define VLV_VIDEO_DIP_CTL_A0x60200
#define VLV_VIDEO_DIP_DATA_A 0x60208
#define VLV_VIDEO_DIP_GDCP_PAYLOAD_A 0x60210
diff --git a/drivers/gpu/drm/i915/intel_display.c
b/drivers/gpu/drm/i915/intel_display.c
index aee6151..647e311 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -380,7 +380,7 @@ static const intel_limit_t intel_limits_vlv_dac = {
static const intel_limit_t intel_limits_vlv_hdmi = {
.dot = { .min = 2, .max = 165000 },
- .vco = { .min = 5994000, .max = 400 },
+ .vco = { .min = 400, .max = 5994000},
.n = { .min = 1, .max = 7 },
.m = { .min = 60, .max = 300 }, /* guess */
.m1 = { .min = 2, .max = 3 },
--
1.7.9.5
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Re: [Intel-gfx] [PATCH 9/9] drm/i915: Enable multi display support in VLV
On 9/26/2012 8:10 PM, Daniel Vetter wrote:
On Wed, Sep 26, 2012 at 07:07:38PM +0530, Vijay Purushothaman wrote:
From: "Bhat, Gajanan"
Clened up DPLL calculations for Valleyview. Moved DPLL register and DPIO
programming to vlv_update_pll function. With all the changes multi
display (clone, extended desktop) should work for VLV.
Signed-off-by: Gajanan Bhat
I guess this patch will look much better once we don't disable the
vlv_update_pll function in between (and apply my other suggestion to move
i9xx_update_pll_divisors into the !vlv pll functions).
-Daniel
I've merged patch 5 and 9 and took care of your suggestions.
Thanks,
Vijay
---
drivers/gpu/drm/i915/i915_reg.h |8 +--
drivers/gpu/drm/i915/intel_display.c | 105 ++
2 files changed, 58 insertions(+), 55 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index d4ed30e..71aa0a7 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -385,12 +385,8 @@
#define DPIO_FASTCLK_DISABLE 0x8100
-#define _DPIO_DATA_LANE0 0x0220
-#define _DPIO_DATA_LANE1 0x0420
-#define _DPIO_DATA_LANE2 0x2620
-#define _DPIO_DATA_LANE3 0x2820
-#define DPIO_DATA_LANE_A(pipe) _PIPE(pipe, _DPIO_DATA_LANE0, _DPIO_DATA_LANE2)
-#define DPIO_DATA_LANE_B(pipe) _PIPE(pipe, _DPIO_DATA_LANE1, _DPIO_DATA_LANE3)
+#define DPIO_DATA_CHANNEL1 0x8220
+#define DPIO_DATA_CHANNEL2 0x8420
/*
* Fence registers
diff --git a/drivers/gpu/drm/i915/intel_display.c
b/drivers/gpu/drm/i915/intel_display.c
index 647e311..e933031 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -4018,10 +4018,10 @@ static void intel_update_lvds(struct drm_crtc *crtc,
intel_clock_t *clock,
}
static void vlv_update_pll(struct drm_crtc *crtc,
- struct drm_display_mode *mode,
- struct drm_display_mode *adjusted_mode,
- intel_clock_t *clock, intel_clock_t *reduced_clock,
- int refclk, int num_connectors)
+ struct drm_display_mode *mode,
+ struct drm_display_mode *adjusted_mode,
+ intel_clock_t *clock, intel_clock_t *reduced_clock,
+ int num_connectors)
{
struct drm_device *dev = crtc->dev;
struct drm_i915_private *dev_priv = dev->dev_private;
@@ -4029,9 +4029,19 @@ static void vlv_update_pll(struct drm_crtc *crtc,
int pipe = intel_crtc->pipe;
u32 dpll, mdiv, pdiv;
u32 bestn, bestm1, bestm2, bestp1, bestp2;
- bool is_hdmi;
+ bool is_sdvo;
+ u32 temp;
- is_hdmi = intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI);
+ is_sdvo = intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO) ||
+ intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI);
+
+ dpll = DPLL_VGA_MODE_DIS;
+ dpll |= DPLL_EXT_BUFFER_ENABLE_VLV;
+ dpll |= DPLL_REFA_CLK_ENABLE_VLV;
+ dpll |= DPLL_INTEGRATED_CLOCK_VLV;
+
+ I915_WRITE(DPLL(pipe), dpll);
+ POSTING_READ(DPLL(pipe));
bestn = clock->n;
bestm1 = clock->m1;
@@ -4039,12 +4049,10 @@ static void vlv_update_pll(struct drm_crtc *crtc,
bestp1 = clock->p1;
bestp2 = clock->p2;
- /* Enable DPIO clock input */
- dpll = DPLL_EXT_BUFFER_ENABLE_VLV | DPLL_REFA_CLK_ENABLE_VLV |
- DPLL_VGA_MODE_DIS | DPLL_INTEGRATED_CLOCK_VLV;
- I915_WRITE(DPLL(pipe), dpll);
- POSTING_READ(DPLL(pipe));
-
+ /*
+* In Valleyview PLL and program lane counter registes are exposed
+* through DPIO interface
+*/
mdiv = ((bestm1 << DPIO_M1DIV_SHIFT) | (bestm2 & DPIO_M2DIV_MASK));
mdiv |= ((bestp1 << DPIO_P1_SHIFT) | (bestp2 << DPIO_P2_SHIFT));
mdiv |= ((bestn << DPIO_N_SHIFT));
@@ -4069,21 +4077,47 @@ static void vlv_update_pll(struct drm_crtc *crtc,
if (wait_for(((I915_READ(DPLL(pipe)) & DPLL_LOCK_VLV) ==
DPLL_LOCK_VLV), 1))
DRM_ERROR("DPLL %d failed to lock\n", pipe);
- if (is_hdmi) {
- u32 temp = intel_mode_get_pixel_multiplier(adjusted_mode);
+ intel_dpio_write(dev_priv, DPIO_FASTCLK_DISABLE, 0x620);
+
+ if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT))
+ intel_dp_set_m_n(crtc, mode, adjusted_mode);
+
+ I915_WRITE(DPLL(pipe), dpll);
+
+ /* Wait for the clocks to stabilize. */
+ POSTING_READ(DPLL(pipe));
+ udelay(150);
+ temp = 0;
+ if (is_sdvo) {
+ temp = intel_mode_get_pixel_multiplier(adjusted_mode);
if (temp > 1)
temp = (temp - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT;
Re: [Intel-gfx] [PATCH 6/9] drm/i915: Add eDP support for Valleyview
On 9/26/2012 8:19 PM, Daniel Vetter wrote:
On Wed, Sep 26, 2012 at 04:31:46PM +0200, Daniel Vetter wrote:
On Wed, Sep 26, 2012 at 07:07:35PM +0530, Vijay Purushothaman wrote:
Eventhough Valleyview display block is derived from Cantiga, VLV
supports eDP. So, added eDP checks in i9xx_crtc_mode_set path.
v2: use different DPIO_DIVISOR values for VGA, DP and eDP
v3: fix DPIO value calculation to use same values for all display
interfaces
Signed-off-by: Gajanan Bhat
Signed-off-by: Vijay Purushothaman
Signed-off-by: Ben Widawsky
---
drivers/gpu/drm/i915/intel_display.c |6 ++
drivers/gpu/drm/i915/intel_dp.c | 13 -
2 files changed, 14 insertions(+), 5 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_display.c
b/drivers/gpu/drm/i915/intel_display.c
index a8a81d1..aee6151 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -4405,6 +4405,12 @@ static int i9xx_crtc_mode_set(struct drm_crtc *crtc,
}
}
+ if (IS_VALLEYVIEW(dev) && intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP)) {
+ pipeconf |= PIPECONF_BPP_6 |
+ PIPECONF_ENABLE |
+ I965_PIPECONF_ACTIVE;
+ }
No.
Jani Nikula and me just figured out that we have a giant mess with 6bpc
dithering on DP outputs, but unconditionally enabling 6bpc on vlv eDP only
papers over issues.
Forgotten to put Jani on cc.
-Daniel
Thanks for the catch. I've removed this unconditional enabling of 6bpc
for VLV eDP. For long term i believe, eDP handling in i9xx_crtc_mode_set
should be changed along the lines of ironlake_crtc_mode_set for cleaner
code. For now, this should unblock others with VLV enabling.
+
DRM_DEBUG_KMS("Mode for pipe %c:\n", pipe == 0 ? 'A' : 'B');
drm_mode_debug_printmodeline(mode);
diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index c111c3f..af57027 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -885,7 +885,7 @@ intel_dp_mode_set(struct drm_encoder *encoder, struct
drm_display_mode *mode,
/* Split out the IBX/CPU vs CPT settings */
- if (is_cpu_edp(intel_dp) && IS_GEN7(dev)) {
+ if (is_cpu_edp(intel_dp) && IS_GEN7(dev) && !IS_VALLEYVIEW(dev)) {
if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
intel_dp->DP |= DP_SYNC_HS_HIGH;
if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
@@ -1474,7 +1474,7 @@ intel_dp_pre_emphasis_max(struct intel_dp *intel_dp,
uint8_t voltage_swing)
{
struct drm_device *dev = intel_dp->base.base.dev;
- if (IS_GEN7(dev) && is_cpu_edp(intel_dp)) {
+ if (IS_GEN7(dev) && is_cpu_edp(intel_dp) && !IS_VALLEYVIEW(dev)) {
switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
case DP_TRAIN_VOLTAGE_SWING_400:
return DP_TRAIN_PRE_EMPHASIS_6;
@@ -1773,7 +1773,7 @@ intel_dp_start_link_train(struct intel_dp *intel_dp)
uint32_tsignal_levels;
- if (IS_GEN7(dev) && is_cpu_edp(intel_dp)) {
+ if (IS_GEN7(dev) && is_cpu_edp(intel_dp) &&
!IS_VALLEYVIEW(dev)) {
signal_levels =
intel_gen7_edp_signal_levels(intel_dp->train_set[0]);
DP = (DP & ~EDP_LINK_TRAIN_VOL_EMP_MASK_IVB) |
signal_levels;
} else if (IS_GEN6(dev) && is_cpu_edp(intel_dp)) {
@@ -1859,7 +1859,7 @@ intel_dp_complete_link_train(struct intel_dp *intel_dp)
break;
}
- if (IS_GEN7(dev) && is_cpu_edp(intel_dp)) {
+ if (IS_GEN7(dev) && is_cpu_edp(intel_dp) &&
!IS_VALLEYVIEW(dev)) {
signal_levels =
intel_gen7_edp_signal_levels(intel_dp->train_set[0]);
DP = (DP & ~EDP_LINK_TRAIN_VOL_EMP_MASK_IVB) |
signal_levels;
} else if (IS_GEN6(dev) && is_cpu_edp(intel_dp)) {
@@ -2471,7 +2471,10 @@ intel_dp_init(struct drm_device *dev, int output_reg,
enum port port)
if (intel_dpd_is_edp(dev))
intel_dp->is_pch_edp = true;
- if (output_reg == DP_A || is_pch_edp(intel_dp)) {
+ if (IS_VALLEYVIEW(dev) && output_reg == DP_C) {
+ type = DRM_MODE_CONNECTOR_eDP;
+ intel_encoder->type = INTEL_OUTPUT_EDP;
You need to be a notch more careful, since since
commit cb0953d734348e8862d6d7edc666cfb3bf6d8fae
Author: Adam Jackson
Date: Fri Jul 16 14:46:29 2010 -0400
drm/i915: Initialize LVDS and eDP outputs before anything else
We initialize built-in panels before external outputs. Hence you need to
adjust intel_setup_outputs for vlv eDP, too, so that t
Re: [Intel-gfx] [PATCH 6/9] drm/i915: Add eDP support for Valleyview
On 9/27/2012 12:48 PM, Jani Nikula wrote:
On Wed, 26 Sep 2012, Daniel Vetter wrote:
On Wed, Sep 26, 2012 at 07:07:35PM +0530, Vijay Purushothaman wrote:
diff --git a/drivers/gpu/drm/i915/intel_display.c
b/drivers/gpu/drm/i915/intel_display.c
index a8a81d1..aee6151 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -4405,6 +4405,12 @@ static int i9xx_crtc_mode_set(struct drm_crtc *crtc,
}
}
+ if (IS_VALLEYVIEW(dev) && intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP)) {
+ pipeconf |= PIPECONF_BPP_6 |
+ PIPECONF_ENABLE |
+ I965_PIPECONF_ACTIVE;
+ }
No.
Jani Nikula and me just figured out that we have a giant mess with 6bpc
dithering on DP outputs, but unconditionally enabling 6bpc on vlv eDP only
papers over issues.
Vijay, please check commit 0c96c65b in drm-intel-fixes.
BR,
Jani.
Thanks Jani & Daniel for your review. I will send out the v2 of the
patch set.
Thanks,
Vijay
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[Intel-gfx] [PATCH v2 0/9] Enable all display interfaces in Valleyview
This patch set enables all supported display interfaces like HDMI, DisplayPort and eDP for Valleyview. This also enables support for multi-display configurations. v2: Addressed review comments from Daniel and Jani Nikula. Gajanan Bhat (1): drm/i915: Add eDP support for Valleyview Vijay Purushothaman (8): drm/i915: Set aux clk to 100MHz for Valleyview drm/i915: Fix SDVO IER and status bits for Valleyview drm/i915: Add Valleyview lane control definitions drm/i915: Program correct m n tu register for Valleyview drm/i915: Disable CRT hotplug detection for valleyview drm/i915: Enable DisplayPort in Valleyview drm/i915: panel power sequencing for VLV eDP drm/i915: Fixup HDMI output on Valleyview drivers/gpu/drm/i915/i915_irq.c |6 +- drivers/gpu/drm/i915/i915_reg.h | 15 +++- drivers/gpu/drm/i915/intel_crt.c |7 ++ drivers/gpu/drm/i915/intel_display.c | 113 + drivers/gpu/drm/i915/intel_dp.c | 152 -- 5 files changed, 211 insertions(+), 82 deletions(-) -- 1.7.9.5 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH v2 1/9] drm/i915: Set aux clk to 100MHz for Valleyview
Set hrawclk to 200 MHz and aux divider clock to 100 MHz for Valleyview.
This enables the aux transactions in Valleyview.
Signed-off-by: Vijay Purushothaman
Signed-off-by: Ben Widawsky
---
drivers/gpu/drm/i915/intel_dp.c |8 +++-
1 file changed, 7 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index a69d9a2..de8092a 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -285,6 +285,10 @@ intel_hrawclk(struct drm_device *dev)
struct drm_i915_private *dev_priv = dev->dev_private;
uint32_t clkcfg;
+ /* There is no CLKCFG reg in Valleyview. VLV hrawclk is 200 MHz */
+ if (IS_VALLEYVIEW(dev))
+ return 200;
+
clkcfg = I915_READ(CLKCFG);
switch (clkcfg & CLKCFG_FSB_MASK) {
case CLKCFG_FSB_400:
@@ -365,7 +369,9 @@ intel_dp_aux_ch(struct intel_dp *intel_dp,
* clock divider.
*/
if (is_cpu_edp(intel_dp)) {
- if (IS_GEN6(dev) || IS_GEN7(dev))
+ if (IS_VALLEYVIEW(dev))
+ aux_clock_divider = 100;
+ else if (IS_GEN6(dev) || IS_GEN7(dev))
aux_clock_divider = 200; /* SNB & IVB eDP input clock
at 400Mhz */
else
aux_clock_divider = 225; /* eDP input clock at 450Mhz */
--
1.7.9.5
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[Intel-gfx] [PATCH v2 2/9] drm/i915: Fix SDVO IER and status bits for Valleyview
Fixed SDVOB and SDVOC bit definitions for Valleyview.
Signed-off-by: Vijay Purushothaman
Signed-off-by: Ben Widawsky
---
drivers/gpu/drm/i915/i915_irq.c |6 ++
1 file changed, 2 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index d915126..1a974d9 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -2020,7 +2020,6 @@ static int valleyview_irq_postinstall(struct drm_device
*dev)
#endif
I915_WRITE(VLV_MASTER_IER, MASTER_INTERRUPT_ENABLE);
-#if 0 /* FIXME: check register definitions; some have moved */
/* Note HDMI and DP share bits */
if (dev_priv->hotplug_supported_mask & HDMIB_HOTPLUG_INT_STATUS)
hotplug_en |= HDMIB_HOTPLUG_INT_EN;
@@ -2028,15 +2027,14 @@ static int valleyview_irq_postinstall(struct drm_device
*dev)
hotplug_en |= HDMIC_HOTPLUG_INT_EN;
if (dev_priv->hotplug_supported_mask & HDMID_HOTPLUG_INT_STATUS)
hotplug_en |= HDMID_HOTPLUG_INT_EN;
- if (dev_priv->hotplug_supported_mask & SDVOC_HOTPLUG_INT_STATUS)
+ if (dev_priv->hotplug_supported_mask & SDVOC_HOTPLUG_INT_STATUS_I915)
hotplug_en |= SDVOC_HOTPLUG_INT_EN;
- if (dev_priv->hotplug_supported_mask & SDVOB_HOTPLUG_INT_STATUS)
+ if (dev_priv->hotplug_supported_mask & SDVOB_HOTPLUG_INT_STATUS_I915)
hotplug_en |= SDVOB_HOTPLUG_INT_EN;
if (dev_priv->hotplug_supported_mask & CRT_HOTPLUG_INT_STATUS) {
hotplug_en |= CRT_HOTPLUG_INT_EN;
hotplug_en |= CRT_HOTPLUG_VOLTAGE_COMPARE_50;
}
-#endif
I915_WRITE(PORT_HOTPLUG_EN, hotplug_en);
--
1.7.9.5
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[Intel-gfx] [PATCH v2 4/9] drm/i915: Program correct m n tu register for Valleyview
m n tu register offset has changed in Valleyview. Also fixed DP limit
frequencies.
Signed-off-by: Vijay Purushothaman
Signed-off-by: Ben Widawsky
---
drivers/gpu/drm/i915/intel_display.c |6 +++---
drivers/gpu/drm/i915/intel_dp.c |5 +
2 files changed, 8 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_display.c
b/drivers/gpu/drm/i915/intel_display.c
index 947c97d..68828e7 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -393,10 +393,10 @@ static const intel_limit_t intel_limits_vlv_hdmi = {
};
static const intel_limit_t intel_limits_vlv_dp = {
- .dot = { .min = 162000, .max = 27 },
- .vco = { .min = 5994000, .max = 400 },
+ .dot = { .min = 25000, .max = 27 },
+ .vco = { .min = 400, .max = 600 },
.n = { .min = 1, .max = 7 },
- .m = { .min = 60, .max = 300 }, /* guess */
+ .m = { .min = 22, .max = 450 },
.m1 = { .min = 2, .max = 3 },
.m2 = { .min = 11, .max = 156 },
.p = { .min = 10, .max = 30 },
diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index de8092a..c111c3f 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -804,6 +804,11 @@ intel_dp_set_m_n(struct drm_crtc *crtc, struct
drm_display_mode *mode,
I915_WRITE(TRANSDATA_N1(pipe), m_n.gmch_n);
I915_WRITE(TRANSDPLINK_M1(pipe), m_n.link_m);
I915_WRITE(TRANSDPLINK_N1(pipe), m_n.link_n);
+ } else if (IS_VALLEYVIEW(dev)) {
+ I915_WRITE(PIPE_DATA_M1(pipe), TU_SIZE(m_n.tu) | m_n.gmch_m);
+ I915_WRITE(PIPE_DATA_N1(pipe), m_n.gmch_n);
+ I915_WRITE(PIPE_LINK_M1(pipe), m_n.link_m);
+ I915_WRITE(PIPE_LINK_N1(pipe), m_n.link_n);
} else {
I915_WRITE(PIPE_GMCH_DATA_M(pipe),
((m_n.tu - 1) << PIPE_GMCH_DATA_M_TU_SIZE_SHIFT) |
--
1.7.9.5
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[Intel-gfx] [PATCH v2 3/9] drm/i915: Add Valleyview lane control definitions
Added DPIO data lane register definitions for Valleyview Signed-off-by: Vijay Purushothaman Signed-off-by: Ben Widawsky --- drivers/gpu/drm/i915/i915_reg.h |8 1 file changed, 8 insertions(+) diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index a828e90..3f75ee6 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -369,6 +369,7 @@ #define DPIO_PLL_MODESEL_SHIFT 24 /* 3 bits */ #define DPIO_BIAS_CURRENT_CTL_SHIFT 21 /* 3 bits, always 0x7 */ #define DPIO_PLL_REFCLK_SEL_SHIFT16 /* 2 bits */ +#define DPIO_PLL_REFCLK_SEL_MASK 3 #define DPIO_DRIVER_CTL_SHIFT12 /* always set to 0x8 */ #define DPIO_CLK_BIAS_CTL_SHIFT 8 /* always set to 0x5 */ #define _DPIO_REFSFR_B 0x8034 @@ -384,6 +385,13 @@ #define DPIO_FASTCLK_DISABLE 0x8100 +#define _DPIO_DATA_LANE0 0x0220 +#define _DPIO_DATA_LANE1 0x0420 +#define _DPIO_DATA_LANE2 0x2620 +#define _DPIO_DATA_LANE3 0x2820 +#define DPIO_DATA_LANE_A(pipe) _PIPE(pipe, _DPIO_DATA_LANE0, _DPIO_DATA_LANE2) +#define DPIO_DATA_LANE_B(pipe) _PIPE(pipe, _DPIO_DATA_LANE1, _DPIO_DATA_LANE3) + /* * Fence registers */ -- 1.7.9.5 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH v2 6/9] drm/i915: Enable DisplayPort in Valleyview
In valleyview voltageswing, pre-emphasis and lane control registers can
be programmed only through the h/w side band fabric.
Cleaned up DPLL calculations for Valleyview to support multi display
configurations.
v2: Based on Daniel's feedbacak, moved crt hotplug detect work around as
separate
patch. Also moved i9xx_update_pll_dividers to i8xx_update_pll and
i9xx_update_pll.
Signed-off-by: Vijay Purushothaman
Signed-off-by: Gajanan Bhat
---
drivers/gpu/drm/i915/i915_reg.h |8 +--
drivers/gpu/drm/i915/intel_display.c | 90 --
2 files changed, 66 insertions(+), 32 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 3f75ee6..0fe4aad 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -385,12 +385,8 @@
#define DPIO_FASTCLK_DISABLE 0x8100
-#define _DPIO_DATA_LANE0 0x0220
-#define _DPIO_DATA_LANE1 0x0420
-#define _DPIO_DATA_LANE2 0x2620
-#define _DPIO_DATA_LANE3 0x2820
-#define DPIO_DATA_LANE_A(pipe) _PIPE(pipe, _DPIO_DATA_LANE0, _DPIO_DATA_LANE2)
-#define DPIO_DATA_LANE_B(pipe) _PIPE(pipe, _DPIO_DATA_LANE1, _DPIO_DATA_LANE3)
+#define DPIO_DATA_CHANNEL1 0x8220
+#define DPIO_DATA_CHANNEL2 0x8420
/*
* Fence registers
diff --git a/drivers/gpu/drm/i915/intel_display.c
b/drivers/gpu/drm/i915/intel_display.c
index 68828e7..ed749c4 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -4017,7 +4017,7 @@ static void vlv_update_pll(struct drm_crtc *crtc,
struct drm_display_mode *mode,
struct drm_display_mode *adjusted_mode,
intel_clock_t *clock, intel_clock_t *reduced_clock,
- int refclk, int num_connectors)
+ int num_connectors)
{
struct drm_device *dev = crtc->dev;
struct drm_i915_private *dev_priv = dev->dev_private;
@@ -4025,9 +4025,19 @@ static void vlv_update_pll(struct drm_crtc *crtc,
int pipe = intel_crtc->pipe;
u32 dpll, mdiv, pdiv;
u32 bestn, bestm1, bestm2, bestp1, bestp2;
- bool is_hdmi;
+ bool is_sdvo;
+ u32 temp;
+
+ is_sdvo = intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO) ||
+ intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI);
- is_hdmi = intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI);
+ dpll = DPLL_VGA_MODE_DIS;
+ dpll |= DPLL_EXT_BUFFER_ENABLE_VLV;
+ dpll |= DPLL_REFA_CLK_ENABLE_VLV;
+ dpll |= DPLL_INTEGRATED_CLOCK_VLV;
+
+ I915_WRITE(DPLL(pipe), dpll);
+ POSTING_READ(DPLL(pipe));
bestn = clock->n;
bestm1 = clock->m1;
@@ -4035,12 +4045,10 @@ static void vlv_update_pll(struct drm_crtc *crtc,
bestp1 = clock->p1;
bestp2 = clock->p2;
- /* Enable DPIO clock input */
- dpll = DPLL_EXT_BUFFER_ENABLE_VLV | DPLL_REFA_CLK_ENABLE_VLV |
- DPLL_VGA_MODE_DIS | DPLL_INTEGRATED_CLOCK_VLV;
- I915_WRITE(DPLL(pipe), dpll);
- POSTING_READ(DPLL(pipe));
-
+ /*
+* In Valleyview PLL and program lane counter registers are exposed
+* through DPIO interface
+*/
mdiv = ((bestm1 << DPIO_M1DIV_SHIFT) | (bestm2 & DPIO_M2DIV_MASK));
mdiv |= ((bestp1 << DPIO_P1_SHIFT) | (bestp2 << DPIO_P2_SHIFT));
mdiv |= ((bestn << DPIO_N_SHIFT));
@@ -4051,12 +4059,13 @@ static void vlv_update_pll(struct drm_crtc *crtc,
intel_dpio_write(dev_priv, DPIO_CORE_CLK(pipe), 0x0100);
- pdiv = DPIO_REFSEL_OVERRIDE | (5 << DPIO_PLL_MODESEL_SHIFT) |
+ pdiv = (1 << DPIO_REFSEL_OVERRIDE) | (5 << DPIO_PLL_MODESEL_SHIFT) |
(3 << DPIO_BIAS_CURRENT_CTL_SHIFT) | (1<<20) |
- (8 << DPIO_DRIVER_CTL_SHIFT) | (5 << DPIO_CLK_BIAS_CTL_SHIFT);
+ (7 << DPIO_PLL_REFCLK_SEL_SHIFT) | (8 << DPIO_DRIVER_CTL_SHIFT)
|
+ (5 << DPIO_CLK_BIAS_CTL_SHIFT);
intel_dpio_write(dev_priv, DPIO_REFSFR(pipe), pdiv);
- intel_dpio_write(dev_priv, DPIO_LFP_COEFF(pipe), 0x009f0051);
+ intel_dpio_write(dev_priv, DPIO_LFP_COEFF(pipe), 0x005f003b);
dpll |= DPLL_VCO_ENABLE;
I915_WRITE(DPLL(pipe), dpll);
@@ -4064,21 +4073,47 @@ static void vlv_update_pll(struct drm_crtc *crtc,
if (wait_for(((I915_READ(DPLL(pipe)) & DPLL_LOCK_VLV) ==
DPLL_LOCK_VLV), 1))
DRM_ERROR("DPLL %d failed to lock\n", pipe);
- if (is_hdmi) {
- u32 temp = intel_mode_get_pixel_multiplier(adjusted_mode);
+ intel_dpio_write(dev_priv, DPIO_FASTCLK_DISABLE, 0x620);
+
+ if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT))
+ intel_dp_set_m_n(crtc, mode, adjusted_mode);
+
+ I915
[Intel-gfx] [PATCH v2 5/9] drm/i915: Disable CRT hotplug detection for valleyview
Temporary work around to avoid spurious crt hotplug interrupts.
Signed-off-by: Vijay Purushothaman
Signed-off-by: Gajanan Bhat
---
drivers/gpu/drm/i915/intel_crt.c |7 +++
1 file changed, 7 insertions(+)
diff --git a/drivers/gpu/drm/i915/intel_crt.c b/drivers/gpu/drm/i915/intel_crt.c
index c42b980..5f30364 100644
--- a/drivers/gpu/drm/i915/intel_crt.c
+++ b/drivers/gpu/drm/i915/intel_crt.c
@@ -308,6 +308,13 @@ static bool valleyview_crt_detect_hotplug(struct
drm_connector *connector)
bool ret;
u32 save_adpa;
+ /*
+* Disable crt detect hotplug for VLV X0. Spurious hot plug
+* detect calls crashses the X0 system
+*/
+ if (IS_VALLEYVIEW(dev))
+ return false;
+
save_adpa = adpa = I915_READ(ADPA);
DRM_DEBUG_KMS("trigger hotplug detect cycle: adpa=0x%x\n", adpa);
--
1.7.9.5
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[Intel-gfx] [PATCH v2 7/9] drm/i915: Add eDP support for Valleyview
From: Gajanan Bhat
Eventhough Valleyview display block is derived from Cantiga, VLV
supports eDP. So, added eDP checks in i9xx_crtc_mode_set path.
v2: use different DPIO_DIVISOR values for VGA, DP and eDP
v3: fix DPIO value calculation to use same values for all display
interfaces
v4: removed unconditional enabling of 6bpc dithering based on comments
from Daniel & Jani Nikula. Also changed the display enabling order to
force eDP detection first.
Signed-off-by: Gajanan Bhat
Signed-off-by: Vijay Purushothaman
---
drivers/gpu/drm/i915/intel_display.c | 15 ---
drivers/gpu/drm/i915/intel_dp.c | 17 -
2 files changed, 24 insertions(+), 8 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_display.c
b/drivers/gpu/drm/i915/intel_display.c
index ed749c4..0362c80 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -4413,6 +4413,14 @@ static int i9xx_crtc_mode_set(struct drm_crtc *crtc,
}
}
+ if (IS_VALLEYVIEW(dev) && intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP)) {
+ if (adjusted_mode->private_flags & INTEL_MODE_DP_FORCE_6BPC) {
+ pipeconf |= PIPECONF_BPP_6 |
+ PIPECONF_ENABLE |
+ I965_PIPECONF_ACTIVE;
+ }
+ }
+
DRM_DEBUG_KMS("Mode for pipe %c:\n", pipe == 0 ? 'A' : 'B');
drm_mode_debug_printmodeline(mode);
@@ -7623,6 +7631,10 @@ static void intel_setup_outputs(struct drm_device *dev)
} else if (IS_VALLEYVIEW(dev)) {
int found;
+ /* Check for built-in panel first. Shares lanes with HDMI on
SDVOC */
+ if (I915_READ(DP_C) & DP_DETECTED)
+ intel_dp_init(dev, DP_C, PORT_C);
+
if (I915_READ(SDVOB) & PORT_DETECTED) {
/* SDVOB multiplex with HDMIB */
found = intel_sdvo_init(dev, SDVOB, true);
@@ -7635,9 +7647,6 @@ static void intel_setup_outputs(struct drm_device *dev)
if (I915_READ(SDVOC) & PORT_DETECTED)
intel_hdmi_init(dev, SDVOC, PORT_C);
- /* Shares lanes with HDMI on SDVOC */
- if (I915_READ(DP_C) & DP_DETECTED)
- intel_dp_init(dev, DP_C, PORT_C);
} else if (SUPPORTS_DIGITAL_OUTPUTS(dev)) {
bool found = false;
diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index c111c3f..867c568 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -885,7 +885,7 @@ intel_dp_mode_set(struct drm_encoder *encoder, struct
drm_display_mode *mode,
/* Split out the IBX/CPU vs CPT settings */
- if (is_cpu_edp(intel_dp) && IS_GEN7(dev)) {
+ if (is_cpu_edp(intel_dp) && IS_GEN7(dev) && !IS_VALLEYVIEW(dev)) {
if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
intel_dp->DP |= DP_SYNC_HS_HIGH;
if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
@@ -1474,7 +1474,7 @@ intel_dp_pre_emphasis_max(struct intel_dp *intel_dp,
uint8_t voltage_swing)
{
struct drm_device *dev = intel_dp->base.base.dev;
- if (IS_GEN7(dev) && is_cpu_edp(intel_dp)) {
+ if (IS_GEN7(dev) && is_cpu_edp(intel_dp) && !IS_VALLEYVIEW(dev)) {
switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
case DP_TRAIN_VOLTAGE_SWING_400:
return DP_TRAIN_PRE_EMPHASIS_6;
@@ -1773,7 +1773,7 @@ intel_dp_start_link_train(struct intel_dp *intel_dp)
uint32_tsignal_levels;
- if (IS_GEN7(dev) && is_cpu_edp(intel_dp)) {
+ if (IS_GEN7(dev) && is_cpu_edp(intel_dp) &&
!IS_VALLEYVIEW(dev)) {
signal_levels =
intel_gen7_edp_signal_levels(intel_dp->train_set[0]);
DP = (DP & ~EDP_LINK_TRAIN_VOL_EMP_MASK_IVB) |
signal_levels;
} else if (IS_GEN6(dev) && is_cpu_edp(intel_dp)) {
@@ -1859,7 +1859,7 @@ intel_dp_complete_link_train(struct intel_dp *intel_dp)
break;
}
- if (IS_GEN7(dev) && is_cpu_edp(intel_dp)) {
+ if (IS_GEN7(dev) && is_cpu_edp(intel_dp) &&
!IS_VALLEYVIEW(dev)) {
signal_levels =
intel_gen7_edp_signal_levels(intel_dp->train_set[0]);
DP = (DP & ~EDP_LINK_TRAIN_VOL_EMP_MASK_IVB) |
signal_levels;
} else if (IS_GEN6(dev) && is_cpu_edp(intel_dp)) {
@@ -2471,7 +2471,14 @@ intel_dp_init(struct drm_device *dev, int output_reg,
enum port port)
if (intel_dpd_is_edp(dev))
i
[Intel-gfx] [PATCH v2 9/9] drm/i915: Fixup HDMI output on Valleyview
Fixed correct min, max vco limits and dip ctl reg
Signed-off-by: Vijay Purushothaman
Signed-off-by: Gajanan Bhat
Signed-off-by: Ben Widawsky
---
drivers/gpu/drm/i915/i915_reg.h |2 +-
drivers/gpu/drm/i915/intel_display.c |2 +-
2 files changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 0e6258a..71aa0a7 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -3683,7 +3683,7 @@
#define TVIDEO_DIP_DATA(pipe) _PIPE(pipe, _VIDEO_DIP_DATA_A, _VIDEO_DIP_DATA_B)
#define TVIDEO_DIP_GCP(pipe) _PIPE(pipe, _VIDEO_DIP_GCP_A, _VIDEO_DIP_GCP_B)
-#define VLV_VIDEO_DIP_CTL_A0x60220
+#define VLV_VIDEO_DIP_CTL_A0x60200
#define VLV_VIDEO_DIP_DATA_A 0x60208
#define VLV_VIDEO_DIP_GDCP_PAYLOAD_A 0x60210
diff --git a/drivers/gpu/drm/i915/intel_display.c
b/drivers/gpu/drm/i915/intel_display.c
index 0362c80..64c94ca 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -380,7 +380,7 @@ static const intel_limit_t intel_limits_vlv_dac = {
static const intel_limit_t intel_limits_vlv_hdmi = {
.dot = { .min = 2, .max = 165000 },
- .vco = { .min = 5994000, .max = 400 },
+ .vco = { .min = 400, .max = 5994000},
.n = { .min = 1, .max = 7 },
.m = { .min = 60, .max = 300 }, /* guess */
.m1 = { .min = 2, .max = 3 },
--
1.7.9.5
___
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[Intel-gfx] [PATCH v2 8/9] drm/i915: panel power sequencing for VLV eDP
PPS register offsets have changed in Valleyview.
Signed-off-by: Gajanan Bhat
Signed-off-by: Vijay Purushothaman
Signed-off-by: Ben Widawsky
---
drivers/gpu/drm/i915/i915_reg.h |9 +++
drivers/gpu/drm/i915/intel_dp.c | 122 +++
2 files changed, 93 insertions(+), 38 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 0fe4aad..0e6258a 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -3977,6 +3977,15 @@
#define PIPEB_PP_ON_DELAYS 0x61308
#define PIPEB_PP_OFF_DELAYS 0x6130c
#define PIPEB_PP_DIVISOR0x61310
+#define VLV_PIPE_PP_STATUS(pipe) _PIPE(pipe, PIPEA_PP_STATUS, PIPEB_PP_STATUS)
+#define VLV_PIPE_PP_CONTROL(pipe) _PIPE(pipe, PIPEA_PP_CONTROL,
PIPEB_PP_CONTROL)
+#define VLV_PIPE_PP_ON_DELAYS(pipe) \
+ _PIPE(pipe, PIPEA_PP_ON_DELAYS, PIPEB_PP_ON_DELAYS)
+#define VLV_PIPE_PP_OFF_DELAYS(pipe) \
+ _PIPE(pipe, PIPEA_PP_OFF_DELAYS, PIPEB_PP_OFF_DELAYS)
+#define VLV_PIPE_PP_DIVISOR(pipe) \
+ _PIPE(pipe, PIPEA_PP_DIVISOR, PIPEB_PP_DIVISOR)
+
#define PCH_PP_STATUS 0xc7200
#define PCH_PP_CONTROL 0xc7204
diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index 867c568..c58535b 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -316,16 +316,20 @@ static bool ironlake_edp_have_panel_power(struct intel_dp
*intel_dp)
{
struct drm_device *dev = intel_dp->base.base.dev;
struct drm_i915_private *dev_priv = dev->dev_private;
+ u32 pp_stat_reg;
- return (I915_READ(PCH_PP_STATUS) & PP_ON) != 0;
+ pp_stat_reg = IS_VALLEYVIEW(dev) ? PIPEA_PP_STATUS : PCH_PP_STATUS;
+ return (I915_READ(pp_stat_reg) & PP_ON) != 0;
}
static bool ironlake_edp_have_panel_vdd(struct intel_dp *intel_dp)
{
struct drm_device *dev = intel_dp->base.base.dev;
struct drm_i915_private *dev_priv = dev->dev_private;
+ u32 pp_ctrl_reg;
- return (I915_READ(PCH_PP_CONTROL) & EDP_FORCE_VDD) != 0;
+ pp_ctrl_reg = IS_VALLEYVIEW(dev) ? PIPEA_PP_CONTROL : PCH_PP_CONTROL;
+ return (I915_READ(pp_ctrl_reg) & EDP_FORCE_VDD) != 0;
}
static void
@@ -333,14 +337,19 @@ intel_dp_check_edp(struct intel_dp *intel_dp)
{
struct drm_device *dev = intel_dp->base.base.dev;
struct drm_i915_private *dev_priv = dev->dev_private;
+ u32 pp_stat_reg, pp_ctrl_reg;
if (!is_edp(intel_dp))
return;
+
+ pp_stat_reg = IS_VALLEYVIEW(dev) ? PIPEA_PP_STATUS : PCH_PP_STATUS;
+ pp_ctrl_reg = IS_VALLEYVIEW(dev) ? PIPEA_PP_CONTROL : PCH_PP_CONTROL;
+
if (!ironlake_edp_have_panel_power(intel_dp) &&
!ironlake_edp_have_panel_vdd(intel_dp)) {
WARN(1, "eDP powered off while attempting aux channel
communication.\n");
DRM_DEBUG_KMS("Status 0x%08x Control 0x%08x\n",
- I915_READ(PCH_PP_STATUS),
- I915_READ(PCH_PP_CONTROL));
+ I915_READ(pp_stat_reg),
+ I915_READ(pp_ctrl_reg));
}
}
@@ -944,16 +953,20 @@ static void ironlake_wait_panel_status(struct intel_dp
*intel_dp,
{
struct drm_device *dev = intel_dp->base.base.dev;
struct drm_i915_private *dev_priv = dev->dev_private;
+ u32 pp_stat_reg, pp_ctrl_reg;
+
+ pp_stat_reg = IS_VALLEYVIEW(dev) ? PIPEA_PP_STATUS : PCH_PP_STATUS;
+ pp_ctrl_reg = IS_VALLEYVIEW(dev) ? PIPEA_PP_CONTROL : PCH_PP_CONTROL;
DRM_DEBUG_KMS("mask %08x value %08x status %08x control %08x\n",
- mask, value,
- I915_READ(PCH_PP_STATUS),
- I915_READ(PCH_PP_CONTROL));
+ mask, value,
+ I915_READ(pp_stat_reg),
+ I915_READ(pp_ctrl_reg));
- if (_wait_for((I915_READ(PCH_PP_STATUS) & mask) == value, 5000, 10)) {
+ if (_wait_for((I915_READ(pp_stat_reg) & mask) == value, 5000, 10)) {
DRM_ERROR("Panel status timeout: status %08x control %08x\n",
- I915_READ(PCH_PP_STATUS),
- I915_READ(PCH_PP_CONTROL));
+ I915_READ(pp_stat_reg),
+ I915_READ(pp_ctrl_reg));
}
}
@@ -980,9 +993,15 @@ static void ironlake_wait_panel_power_cycle(struct
intel_dp *intel_dp)
* is locked
*/
-static u32 ironlake_get_pp_control(struct drm_i915_private *dev_priv)
+static u32 ironlake_get_pp_control(struct intel_dp *intel_dp)
{
- u32 control = I915_READ(PCH_PP_CONTROL);
+ struct drm_device *dev = intel_dp->base.base.dev;
+ struct drm_i915_private *dev_priv = dev->dev_private;
+ u32 control;
+
[Intel-gfx] [PATCH 1/3] drm/i915: Disable M2 frac division for integer case
v2 : Handle M2 frac division for both M2 frac and int cases
v3 : Addressed Ville's review comments. Cleared the old bits for RMW
Signed-off-by: Vijay Purushothaman
---
drivers/gpu/drm/i915/i915_reg.h |1 +
drivers/gpu/drm/i915/intel_display.c | 24 ++--
2 files changed, 19 insertions(+), 6 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 55143cb..8200e98 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -1029,6 +1029,7 @@ enum skl_disp_power_wells {
#define DPIO_CHV_FIRST_MOD(0 << 8)
#define DPIO_CHV_SECOND_MOD (1 << 8)
#define DPIO_CHV_FEEDFWD_GAIN_SHIFT 0
+#define DPIO_CHV_FEEDFWD_GAIN_MASK(0xF << 0)
#define CHV_PLL_DW3(ch) _PIPE(ch, _CHV_PLL_DW3_CH0, _CHV_PLL_DW3_CH1)
#define _CHV_PLL_DW6_CH0 0x8018
diff --git a/drivers/gpu/drm/i915/intel_display.c
b/drivers/gpu/drm/i915/intel_display.c
index 7298796..15904a8 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -6131,6 +6131,7 @@ static void chv_prepare_pll(struct intel_crtc *crtc,
enum dpio_channel port = vlv_pipe_to_channel(pipe);
u32 loopfilter, intcoeff;
u32 bestn, bestm1, bestm2, bestp1, bestp2, bestm2_frac;
+ u32 dpio_val;
int refclk;
bestn = pipe_config->dpll.n;
@@ -6139,6 +6140,7 @@ static void chv_prepare_pll(struct intel_crtc *crtc,
bestm2 = pipe_config->dpll.m2 >> 22;
bestp1 = pipe_config->dpll.p1;
bestp2 = pipe_config->dpll.p2;
+ dpio_val = 0;
/*
* Enable Refclk and SSC
@@ -6163,13 +6165,23 @@ static void chv_prepare_pll(struct intel_crtc *crtc,
DPIO_CHV_M1_DIV_BY_2 |
1 << DPIO_CHV_N_DIV_SHIFT);
- /* M2 fraction division */
- vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW2(port), bestm2_frac);
+ if (bestm2_frac) {
+ /* M2 fraction division */
+ vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW2(port), bestm2_frac);
- /* M2 fraction division enable */
- vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW3(port),
- DPIO_CHV_FRAC_DIV_EN |
- (2 << DPIO_CHV_FEEDFWD_GAIN_SHIFT));
+ /* M2 fraction division enable */
+ dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW3(port));
+ dpio_val |= DPIO_CHV_FRAC_DIV_EN;
+ dpio_val &= ~DPIO_CHV_FEEDFWD_GAIN_MASK;
+ dpio_val |= (2 << DPIO_CHV_FEEDFWD_GAIN_SHIFT);
+ vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW3(port), dpio_val);
+
+ } else {
+ /* M2 fraction division disable */
+ dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW3(port));
+ dpio_val &= ~DPIO_CHV_FRAC_DIV_EN;
+ vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW3(port), dpio_val);
+ }
/* Loop filter */
refclk = i9xx_get_refclk(crtc, 0);
--
1.7.9.5
___
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[Intel-gfx] [PATCH 3/3] drm/i915: Update prop, int co-eff and gain threshold for CHV
This patch implements latest PHY changes in Gain, prop and int co-efficients
based on the vco freq.
v2: Split the original changes into multiple smaller patches based on
review by Ville
v3: Addressed Ville's review comments. Fixed the error introduced in v2.
Clear the old bits before we modify those bits as part of RMW.
Signed-off-by: Vijay Purushothaman
---
drivers/gpu/drm/i915/i915_reg.h |2 ++
drivers/gpu/drm/i915/intel_display.c | 43 --
2 files changed, 33 insertions(+), 12 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 1a0f94e..5000184 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -1041,6 +1041,8 @@ enum skl_disp_power_wells {
#define _CHV_PLL_DW8_CH0 0x8020
#define _CHV_PLL_DW8_CH1 0x81A0
+#define DPIO_CHV_TDC_TARGET_CNT_SHIFT 0
+#define DPIO_CHV_TDC_TARGET_CNT_MASK (0xFF << 0)
#define CHV_PLL_DW8(ch) _PIPE(ch, _CHV_PLL_DW8_CH0, _CHV_PLL_DW8_CH1)
#define _CHV_PLL_DW9_CH0 0x8024
diff --git a/drivers/gpu/drm/i915/intel_display.c
b/drivers/gpu/drm/i915/intel_display.c
index a6b5786..4e08a14 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -6129,10 +6129,10 @@ static void chv_prepare_pll(struct intel_crtc *crtc,
int pipe = crtc->pipe;
int dpll_reg = DPLL(crtc->pipe);
enum dpio_channel port = vlv_pipe_to_channel(pipe);
- u32 loopfilter, intcoeff;
+ u32 loopfilter, tribuf_calcntr;
u32 bestn, bestm1, bestm2, bestp1, bestp2, bestm2_frac;
u32 dpio_val;
- int refclk;
+ int vco;
bestn = pipe_config->dpll.n;
bestm2_frac = pipe_config->dpll.m2 & 0x3f;
@@ -6140,7 +6140,9 @@ static void chv_prepare_pll(struct intel_crtc *crtc,
bestm2 = pipe_config->dpll.m2 >> 22;
bestp1 = pipe_config->dpll.p1;
bestp2 = pipe_config->dpll.p2;
+ vco = pipe_config->dpll.vco;
dpio_val = 0;
+ loopfilter = 0;
/*
* Enable Refclk and SSC
@@ -6197,18 +6199,35 @@ static void chv_prepare_pll(struct intel_crtc *crtc,
}
/* Loop filter */
- refclk = i9xx_get_refclk(crtc, 0);
- loopfilter = 5 << DPIO_CHV_PROP_COEFF_SHIFT |
- 2 << DPIO_CHV_GAIN_CTRL_SHIFT;
- if (refclk == 10)
- intcoeff = 11;
- else if (refclk == 38400)
- intcoeff = 10;
- else
- intcoeff = 9;
- loopfilter |= intcoeff << DPIO_CHV_INT_COEFF_SHIFT;
+ if (vco == 540) {
+ loopfilter |= (0x3 << DPIO_CHV_PROP_COEFF_SHIFT);
+ loopfilter |= (0x8 << DPIO_CHV_INT_COEFF_SHIFT);
+ loopfilter |= (0x1 << DPIO_CHV_GAIN_CTRL_SHIFT);
+ tribuf_calcntr = 9;
+ } else if (vco <= 620) {
+ loopfilter |= (0x5 << DPIO_CHV_PROP_COEFF_SHIFT);
+ loopfilter |= (0xB << DPIO_CHV_INT_COEFF_SHIFT);
+ loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT);
+ tribuf_calcntr = 0x9;
+ } else if (vco <= 648) {
+ loopfilter |= (0x4 << DPIO_CHV_PROP_COEFF_SHIFT);
+ loopfilter |= (0x9 << DPIO_CHV_INT_COEFF_SHIFT);
+ loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT);
+ tribuf_calcntr = 0x8;
+ } else {
+ /* Not supported. Apply the same limits as in the max case */
+ loopfilter |= (0x4 << DPIO_CHV_PROP_COEFF_SHIFT);
+ loopfilter |= (0x9 << DPIO_CHV_INT_COEFF_SHIFT);
+ loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT);
+ tribuf_calcntr = 0;
+ }
vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW6(port), loopfilter);
+ dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW8(pipe));
+ dpio_val &= ~DPIO_CHV_TDC_TARGET_CNT_MASK;
+ dpio_val |= (tribuf_calcntr << DPIO_CHV_TDC_TARGET_CNT_SHIFT);
+ vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW8(port), dpio_val);
+
/* AFC Recal */
vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port),
vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port)) |
--
1.7.9.5
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[Intel-gfx] [PATCH 2/3] drm/i915: Initialize CHV digital lock detect threshold
Initialize lock detect threshold and select coarse threshold for the
case where M2 fraction division is disabled.
v2: Split the changes into multiple smaller patches based on review by
Ville
v3: Addressed rest of the review comments. Clear out the old bits before
we modify those bits as part of RMW
Signed-off-by: Vijay Purushothaman
---
drivers/gpu/drm/i915/i915_reg.h |1 +
drivers/gpu/drm/i915/intel_display.c | 13 +
2 files changed, 14 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 8200e98..1a0f94e 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -1046,6 +1046,7 @@ enum skl_disp_power_wells {
#define _CHV_PLL_DW9_CH0 0x8024
#define _CHV_PLL_DW9_CH1 0x81A4
#define DPIO_CHV_INT_LOCK_THRESHOLD_SHIFT 1 /* 3 bits */
+#define DPIO_CHV_INT_LOCK_THRESHOLD_MASK (7 << 1)
#define DPIO_CHV_INT_LOCK_THRESHOLD_SEL_COARSE1 /* 1: coarse & 0 :
fine */
#define CHV_PLL_DW9(ch) _PIPE(ch, _CHV_PLL_DW9_CH0, _CHV_PLL_DW9_CH1)
diff --git a/drivers/gpu/drm/i915/intel_display.c
b/drivers/gpu/drm/i915/intel_display.c
index 15904a8..a6b5786 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -6176,11 +6176,24 @@ static void chv_prepare_pll(struct intel_crtc *crtc,
dpio_val |= (2 << DPIO_CHV_FEEDFWD_GAIN_SHIFT);
vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW3(port), dpio_val);
+ /* Program digital lock detect threshold */
+ dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW9(port));
+ dpio_val &= ~DPIO_CHV_INT_LOCK_THRESHOLD_MASK;
+ dpio_val |= (0x5 << DPIO_CHV_INT_LOCK_THRESHOLD_SHIFT);
+ vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW9(port), dpio_val);
+
} else {
/* M2 fraction division disable */
dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW3(port));
dpio_val &= ~DPIO_CHV_FRAC_DIV_EN;
vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW3(port), dpio_val);
+
+ /* Program digital lock detect threshold */
+ dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW9(port));
+ dpio_val &= ~DPIO_CHV_INT_LOCK_THRESHOLD_MASK;
+ dpio_val |= (0x5 << DPIO_CHV_INT_LOCK_THRESHOLD_SHIFT);
+ dpio_val |= DPIO_CHV_INT_LOCK_THRESHOLD_SEL_COARSE;
+ vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW9(port), dpio_val);
}
/* Loop filter */
--
1.7.9.5
___
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[Intel-gfx] [PATCH 1/3] drm/i915: Disable M2 frac division for integer case
v2 : Handle M2 frac division for both M2 frac and int cases
v3 : Addressed Ville's review comments. Cleared the old bits for RMW
v4 : Fix feedfwd gain (Ville)
Signed-off-by: Vijay Purushothaman
Signed-off-by: Ville Syrjala
---
drivers/gpu/drm/i915/i915_reg.h |1 +
drivers/gpu/drm/i915/intel_display.c | 14 ++
2 files changed, 11 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 55143cb..8200e98 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -1029,6 +1029,7 @@ enum skl_disp_power_wells {
#define DPIO_CHV_FIRST_MOD(0 << 8)
#define DPIO_CHV_SECOND_MOD (1 << 8)
#define DPIO_CHV_FEEDFWD_GAIN_SHIFT 0
+#define DPIO_CHV_FEEDFWD_GAIN_MASK(0xF << 0)
#define CHV_PLL_DW3(ch) _PIPE(ch, _CHV_PLL_DW3_CH0, _CHV_PLL_DW3_CH1)
#define _CHV_PLL_DW6_CH0 0x8018
diff --git a/drivers/gpu/drm/i915/intel_display.c
b/drivers/gpu/drm/i915/intel_display.c
index 7298796..c5a8725 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -6131,6 +6131,7 @@ static void chv_prepare_pll(struct intel_crtc *crtc,
enum dpio_channel port = vlv_pipe_to_channel(pipe);
u32 loopfilter, intcoeff;
u32 bestn, bestm1, bestm2, bestp1, bestp2, bestm2_frac;
+ u32 dpio_val;
int refclk;
bestn = pipe_config->dpll.n;
@@ -6139,6 +6140,7 @@ static void chv_prepare_pll(struct intel_crtc *crtc,
bestm2 = pipe_config->dpll.m2 >> 22;
bestp1 = pipe_config->dpll.p1;
bestp2 = pipe_config->dpll.p2;
+ dpio_val = 0;
/*
* Enable Refclk and SSC
@@ -6164,12 +6166,16 @@ static void chv_prepare_pll(struct intel_crtc *crtc,
1 << DPIO_CHV_N_DIV_SHIFT);
/* M2 fraction division */
- vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW2(port), bestm2_frac);
+ if (bestm2_frac)
+ vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW2(port), bestm2_frac);
/* M2 fraction division enable */
- vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW3(port),
- DPIO_CHV_FRAC_DIV_EN |
- (2 << DPIO_CHV_FEEDFWD_GAIN_SHIFT));
+ dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW3(port));
+ dpio_val &= ~(DPIO_CHV_FEEDFWD_GAIN_MASK | DPIO_CHV_FRAC_DIV_EN);
+ dpio_val |= (2 << DPIO_CHV_FEEDFWD_GAIN_SHIFT);
+ if (bestm2_frac)
+ dpio_val |= DPIO_CHV_FRAC_DIV_EN;
+ vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW3(port), dpio_val);
/* Loop filter */
refclk = i9xx_get_refclk(crtc, 0);
--
1.7.9.5
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[Intel-gfx] [PATCH 2/3] drm/i915: Initialize CHV digital lock detect threshold
Initialize lock detect threshold and select coarse threshold for the
case where M2 fraction division is disabled.
v2: Split the changes into multiple smaller patches (Ville)
v3: Clear out the old bits before we modify those bits as RMW (Ville)
v4: Reset coarse threshold when M2 fraction is enabled (Ville)
Signed-off-by: Vijay Purushothaman
Signed-off-by: Ville Syrjala
---
drivers/gpu/drm/i915/i915_reg.h |1 +
drivers/gpu/drm/i915/intel_display.c |9 +
2 files changed, 10 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 8200e98..1a0f94e 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -1046,6 +1046,7 @@ enum skl_disp_power_wells {
#define _CHV_PLL_DW9_CH0 0x8024
#define _CHV_PLL_DW9_CH1 0x81A4
#define DPIO_CHV_INT_LOCK_THRESHOLD_SHIFT 1 /* 3 bits */
+#define DPIO_CHV_INT_LOCK_THRESHOLD_MASK (7 << 1)
#define DPIO_CHV_INT_LOCK_THRESHOLD_SEL_COARSE1 /* 1: coarse & 0 :
fine */
#define CHV_PLL_DW9(ch) _PIPE(ch, _CHV_PLL_DW9_CH0, _CHV_PLL_DW9_CH1)
diff --git a/drivers/gpu/drm/i915/intel_display.c
b/drivers/gpu/drm/i915/intel_display.c
index c5a8725..6c5a5a9 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -6177,6 +6177,15 @@ static void chv_prepare_pll(struct intel_crtc *crtc,
dpio_val |= DPIO_CHV_FRAC_DIV_EN;
vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW3(port), dpio_val);
+ /* Program digital lock detect threshold */
+ dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW9(port));
+ dpio_val &= ~(DPIO_CHV_INT_LOCK_THRESHOLD_MASK |
+ DPIO_CHV_INT_LOCK_THRESHOLD_SEL_COARSE);
+ dpio_val |= (0x5 << DPIO_CHV_INT_LOCK_THRESHOLD_SHIFT);
+ if (!bestm2_frac)
+ dpio_val |= DPIO_CHV_INT_LOCK_THRESHOLD_SEL_COARSE;
+ vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW9(port), dpio_val);
+
/* Loop filter */
refclk = i9xx_get_refclk(crtc, 0);
loopfilter = 5 << DPIO_CHV_PROP_COEFF_SHIFT |
--
1.7.9.5
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[Intel-gfx] [PATCH 3/3] drm/i915: Update prop, int co-eff and gain threshold for CHV
This patch implements latest PHY changes in Gain, prop and int co-efficients
based on the vco freq.
v2: Split the original changes into multiple smaller patches based on
review by Ville
v3: Addressed Ville's review comments. Fixed the error introduced in v2.
Clear the old bits before we modify those bits as part of RMW.
v4: TDC target cnt is 10 bits and not 8 bits (Ville)
Signed-off-by: Vijay Purushothaman
---
drivers/gpu/drm/i915/i915_reg.h |2 ++
drivers/gpu/drm/i915/intel_display.c | 43 --
2 files changed, 33 insertions(+), 12 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 1a0f94e..14b560b 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -1041,6 +1041,8 @@ enum skl_disp_power_wells {
#define _CHV_PLL_DW8_CH0 0x8020
#define _CHV_PLL_DW8_CH1 0x81A0
+#define DPIO_CHV_TDC_TARGET_CNT_SHIFT 0
+#define DPIO_CHV_TDC_TARGET_CNT_MASK (0x3FF << 0)
#define CHV_PLL_DW8(ch) _PIPE(ch, _CHV_PLL_DW8_CH0, _CHV_PLL_DW8_CH1)
#define _CHV_PLL_DW9_CH0 0x8024
diff --git a/drivers/gpu/drm/i915/intel_display.c
b/drivers/gpu/drm/i915/intel_display.c
index 6c5a5a9..3eb0946 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -6129,10 +6129,10 @@ static void chv_prepare_pll(struct intel_crtc *crtc,
int pipe = crtc->pipe;
int dpll_reg = DPLL(crtc->pipe);
enum dpio_channel port = vlv_pipe_to_channel(pipe);
- u32 loopfilter, intcoeff;
+ u32 loopfilter, tribuf_calcntr;
u32 bestn, bestm1, bestm2, bestp1, bestp2, bestm2_frac;
u32 dpio_val;
- int refclk;
+ int vco;
bestn = pipe_config->dpll.n;
bestm2_frac = pipe_config->dpll.m2 & 0x3f;
@@ -6140,7 +6140,9 @@ static void chv_prepare_pll(struct intel_crtc *crtc,
bestm2 = pipe_config->dpll.m2 >> 22;
bestp1 = pipe_config->dpll.p1;
bestp2 = pipe_config->dpll.p2;
+ vco = pipe_config->dpll.vco;
dpio_val = 0;
+ loopfilter = 0;
/*
* Enable Refclk and SSC
@@ -6187,18 +6189,35 @@ static void chv_prepare_pll(struct intel_crtc *crtc,
vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW9(port), dpio_val);
/* Loop filter */
- refclk = i9xx_get_refclk(crtc, 0);
- loopfilter = 5 << DPIO_CHV_PROP_COEFF_SHIFT |
- 2 << DPIO_CHV_GAIN_CTRL_SHIFT;
- if (refclk == 10)
- intcoeff = 11;
- else if (refclk == 38400)
- intcoeff = 10;
- else
- intcoeff = 9;
- loopfilter |= intcoeff << DPIO_CHV_INT_COEFF_SHIFT;
+ if (vco == 540) {
+ loopfilter |= (0x3 << DPIO_CHV_PROP_COEFF_SHIFT);
+ loopfilter |= (0x8 << DPIO_CHV_INT_COEFF_SHIFT);
+ loopfilter |= (0x1 << DPIO_CHV_GAIN_CTRL_SHIFT);
+ tribuf_calcntr = 0x9;
+ } else if (vco <= 620) {
+ loopfilter |= (0x5 << DPIO_CHV_PROP_COEFF_SHIFT);
+ loopfilter |= (0xB << DPIO_CHV_INT_COEFF_SHIFT);
+ loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT);
+ tribuf_calcntr = 0x9;
+ } else if (vco <= 648) {
+ loopfilter |= (0x4 << DPIO_CHV_PROP_COEFF_SHIFT);
+ loopfilter |= (0x9 << DPIO_CHV_INT_COEFF_SHIFT);
+ loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT);
+ tribuf_calcntr = 0x8;
+ } else {
+ /* Not supported. Apply the same limits as in the max case */
+ loopfilter |= (0x4 << DPIO_CHV_PROP_COEFF_SHIFT);
+ loopfilter |= (0x9 << DPIO_CHV_INT_COEFF_SHIFT);
+ loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT);
+ tribuf_calcntr = 0;
+ }
vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW6(port), loopfilter);
+ dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW8(pipe));
+ dpio_val &= ~DPIO_CHV_TDC_TARGET_CNT_MASK;
+ dpio_val |= (tribuf_calcntr << DPIO_CHV_TDC_TARGET_CNT_SHIFT);
+ vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW8(port), dpio_val);
+
/* AFC Recal */
vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port),
vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port)) |
--
1.7.9.5
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Re: [Intel-gfx] [PATCH v2 2/3] drm/i915: gmch: set SR WMs to valid values before enabling them
On 6/13/2014 5:24 PM, Imre Deak wrote:
Atm it's possible that we enable the memory self-refresh mode before the
watermark levels used by this mode are programmed with valid values. So
move the enabling after we programmed the WM levels.
Signed-off-by: Imre Deak
---
drivers/gpu/drm/i915/intel_pm.c | 21 ++---
1 file changed, 18 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index e55622e..c9ee1aa 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -1332,6 +1332,7 @@ static void valleyview_update_wm(struct drm_crtc *crtc)
int plane_sr, cursor_sr;
int ignore_plane_sr, ignore_cursor_sr;
unsigned int enabled = 0;
+ bool cxsr_enabled;
vlv_update_drain_latency(dev);
@@ -1358,8 +1359,9 @@ static void valleyview_update_wm(struct drm_crtc *crtc)
&valleyview_wm_info,
&valleyview_cursor_wm_info,
&ignore_plane_sr, &cursor_sr)) {
- intel_set_memory_cxsr(dev_priv, true);
+ cxsr_enabled = true;
} else {
+ cxsr_enabled = false;
intel_set_memory_cxsr(dev_priv, false);
plane_sr = cursor_sr = 0;
}
@@ -1380,6 +1382,9 @@ static void valleyview_update_wm(struct drm_crtc *crtc)
I915_WRITE(DSPFW3,
(I915_READ(DSPFW3) & ~DSPFW_CURSOR_SR_MASK) |
(cursor_sr << DSPFW_CURSOR_SR_SHIFT));
+
+ if (cxsr_enabled)
+ intel_set_memory_cxsr(dev_priv, true);
}
static void g4x_update_wm(struct drm_crtc *crtc)
@@ -1390,6 +1395,7 @@ static void g4x_update_wm(struct drm_crtc *crtc)
int planea_wm, planeb_wm, cursora_wm, cursorb_wm;
int plane_sr, cursor_sr;
unsigned int enabled = 0;
+ bool cxsr_enabled;
if (g4x_compute_wm0(dev, PIPE_A,
&g4x_wm_info, latency_ns,
@@ -1409,8 +1415,9 @@ static void g4x_update_wm(struct drm_crtc *crtc)
&g4x_wm_info,
&g4x_cursor_wm_info,
&plane_sr, &cursor_sr)) {
- intel_set_memory_cxsr(dev_priv, true);
+ cxsr_enabled = true;
} else {
+ cxsr_enabled = false;
intel_set_memory_cxsr(dev_priv, false);
plane_sr = cursor_sr = 0;
}
@@ -1432,6 +1439,9 @@ static void g4x_update_wm(struct drm_crtc *crtc)
I915_WRITE(DSPFW3,
(I915_READ(DSPFW3) & ~(DSPFW_HPLL_SR_EN |
DSPFW_CURSOR_SR_MASK)) |
(cursor_sr << DSPFW_CURSOR_SR_SHIFT));
+
+ if (cxsr_enabled)
+ intel_set_memory_cxsr(dev_priv, true);
}
static void i965_update_wm(struct drm_crtc *unused_crtc)
@@ -1441,6 +1451,7 @@ static void i965_update_wm(struct drm_crtc *unused_crtc)
struct drm_crtc *crtc;
int srwm = 1;
int cursor_sr = 16;
+ bool cxsr_enabled;
/* Calc sr entries for one plane configs */
crtc = single_enabled_crtc(dev);
@@ -1482,8 +1493,9 @@ static void i965_update_wm(struct drm_crtc *unused_crtc)
DRM_DEBUG_KMS("self-refresh watermark: display plane %d "
"cursor %d\n", srwm, cursor_sr);
- intel_set_memory_cxsr(dev_priv, true);
+ cxsr_enabled = true;
} else {
+ cxsr_enabled = false;
/* Turn off self refresh if both pipes are enabled */
intel_set_memory_cxsr(dev_priv, false);
}
@@ -1497,6 +1509,9 @@ static void i965_update_wm(struct drm_crtc *unused_crtc)
I915_WRITE(DSPFW2, (8 << 8) | (8 << 0));
/* update cursor SR watermark */
I915_WRITE(DSPFW3, (cursor_sr << DSPFW_CURSOR_SR_SHIFT));
+
+ if (cxsr_enabled)
+ intel_set_memory_cxsr(dev_priv, true);
}
static void i9xx_update_wm(struct drm_crtc *unused_crtc)
Reviewed-by: Vijay Purushothaman
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Re: [Intel-gfx] [PATCH v2 3/3] drm/i915: gmch: fix stuck primary plane due to memory self-refresh mode
On 6/13/2014 5:24 PM, Imre Deak wrote: Blanking/unblanking the console in a loop on an Asus T100 sometimes leaves the console blank. After some digging I found that applying commit 61bc95c1fbbb6a08b55bbe161fdf1ea5493fc595 Author: Egbert Eich Date: Mon Mar 4 09:24:38 2013 -0500 DRM/i915: On G45 enable cursor plane briefly after enabling the display plane. fixed VLV too. In my case the problem seemed to happen already during the previous crtc disabling and went away if I disabled self-refresh mode before disabling the primary plane. The root cause for this is that updates from the shadow to live plane control register are blocked at vblank time if the memory self-refresh mode (aka max-fifo mode on VLV) is active at that moment. The controller checks at frame start time if the CPU is in C0 and the self-refresh mode enable bit is set and if so activates self-reresh mode, otherwise deactivates it. So to make sure that the plane truly gets disabled before pipe-off we have to: 1. disable memory self-refresh mode 2. disable plane 3. wait for vblank 4. disable pipe 5. wait for pipe-off v2: - add explanation for the root cause from HW team (Cesar Mancini et al) - remove note about the CPU C7S state, in my latest tests disabling it alone didn't make a difference - add vblank between disabling plane and pipe (Ville) - apply the same workaround for all gmch platforms (Ville) Signed-off-by: Imre Deak --- drivers/gpu/drm/i915/intel_display.c | 15 +-- 1 file changed, 13 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c index b9251c8..5eb8afe 100644 --- a/drivers/gpu/drm/i915/intel_display.c +++ b/drivers/gpu/drm/i915/intel_display.c @@ -4799,6 +4799,16 @@ static void i9xx_crtc_disable(struct drm_crtc *crtc) if (IS_GEN2(dev)) intel_set_cpu_fifo_underrun_reporting(dev, pipe, false); + /* +* Vblank time updates from the shadow to live plane control register +* are blocked if the memory self-refresh mode is active at that +* moment. So to make sure the plane gets truly disabled, disable +* first the self-refresh mode. The self-refresh enable bit in turn +* will be checked/applied by the HW only at the next frame start +* event which is after the vblank start event, so we need to have a +* wait-for-vblank between disabling the plane and the pipe. +*/ + intel_set_memory_cxsr(dev_priv, false); intel_crtc_disable_planes(crtc); for_each_encoder_on_crtc(dev, crtc, encoder) @@ -4807,9 +4817,10 @@ static void i9xx_crtc_disable(struct drm_crtc *crtc) /* * On gen2 planes are double buffered but the pipe isn't, so we must * wait for planes to fully turn off before disabling the pipe. +* We also need to wait on all gmch platforms because of the +* self-refresh mode constraint explained above. */ - if (IS_GEN2(dev)) - intel_wait_for_vblank(dev, pipe); + intel_wait_for_vblank(dev, pipe); intel_disable_pipe(dev_priv, pipe); Reviewed-by: Vijay Purushothaman ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH] drm/i915: More DPIO magic for CHV HDMI & DP
This patch implements latest changes in Gain, lock threshold and integer
co-efficient values using sideband r/w. Without these changes there will
be signal integrity issues for both HDMI and DP.
Change-Id: I7b7151b5ab3a52c4c912cf10602c69a7d1a70222
Signed-off-by: Vijay Purushothaman
Tested-by: Hong Liu
---
drivers/gpu/drm/i915/i915_reg.h | 31
drivers/gpu/drm/i915/intel_display.c | 67 --
2 files changed, 79 insertions(+), 19 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 137c5e0..2b3f065 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -1049,6 +1049,37 @@ enum punit_power_well {
#define DPIO_CHV_PROP_COEFF_SHIFT0
#define CHV_PLL_DW6(ch) _PIPE(ch, _CHV_PLL_DW6_CH0, _CHV_PLL_DW6_CH1)
+#define _CHV_PLL_DW7_CH0 0x801c
+#define _CHV_PLL_DW7_CH1 0x803c
+#define CHV_PLL_DW7(ch) _PIPE(ch, _CHV_PLL_DW7_CH0, _CHV_PLL_DW7_CH1)
+
+#define _CHV_PLL_DW8_CH0 0x8020
+#define _CHV_PLL_DW8_CH1 0x81A0
+#define CHV_PLL_DW8(ch) _PIPE(ch, _CHV_PLL_DW8_CH0, _CHV_PLL_DW8_CH1)
+
+#define _CHV_PLL_DW9_CH0 0x8024
+#define _CHV_PLL_DW9_CH1 0x81A4
+#define DPIO_CHV_INT_LOCK_THRESHOLD_SHIFT 1 /* 3 bits */
+#define DPIO_CHV_INT_LOCK_THRESHOLD_SEL_COARSE1 /* 1: coarse & 0 :
fine */
+#define CHV_PLL_DW9(ch) _PIPE(ch, _CHV_PLL_DW9_CH0, _CHV_PLL_DW9_CH1)
+
+#define _CHV_PLL_DW10_CH0 0x8040
+#define _CHV_PLL_DW10_CH1 0x8060
+#define CHV_PLL_DW10(ch) _PIPE(ch, _CHV_PLL_DW10_CH0, _CHV_PLL_DW10_CH1)
+
+#define _CHV_PLL_DW11_BCAST0xC044
+#define _CHV_PLL_DW11_CH0 0x8044
+#define _CHV_PLL_DW11_CH1 0x8064
+#define CHV_PLL_DW11(ch) _PIPE(ch, _CHV_PLL_DW11_CH0, _CHV_PLL_DW11_CH1)
+
+#define _CHV_PLL_DW12_CH0 0x8048
+#define _CHV_PLL_DW12_CH1 0x8068
+#define CHV_PLL_DW12(ch) _PIPE(ch, _CHV_PLL_DW12_CH0, _CHV_PLL_DW12_CH1)
+
+#define _CHV_PLL_DW13_CH0 0x804C
+#define _CHV_PLL_DW13_CH1 0x806C
+#define CHV_PLL_DW13(ch) _PIPE(ch, _CHV_PLL_DW13_CH0, _CHV_PLL_DW13_CH1)
+
#define _CHV_CMN_DW5_CH0 0x8114
#define CHV_BUFRIGHTENA1_DISABLE (0 << 20)
#define CHV_BUFRIGHTENA1_NORMAL (1 << 20)
diff --git a/drivers/gpu/drm/i915/intel_display.c
b/drivers/gpu/drm/i915/intel_display.c
index c362d11e..fb27faf 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -6576,9 +6576,9 @@ static void chv_update_pll(struct intel_crtc *crtc)
int pipe = crtc->pipe;
int dpll_reg = DPLL(crtc->pipe);
enum dpio_channel port = vlv_pipe_to_channel(pipe);
- u32 loopfilter, intcoeff;
+ u32 loopfilter, tribuf_calcntr;
u32 bestn, bestm1, bestm2, bestp1, bestp2, bestm2_frac;
- int refclk;
+ int vco;
crtc->config.dpll_hw_state.dpll = DPLL_SSC_REF_CLOCK_CHV |
DPLL_REFA_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS |
@@ -6595,6 +6595,7 @@ static void chv_update_pll(struct intel_crtc *crtc)
bestm2 = crtc->config.dpll.m2 >> 22;
bestp1 = crtc->config.dpll.p1;
bestp2 = crtc->config.dpll.p2;
+ vco = crtc->config.dpll.vco;
/*
* Enable Refclk and SSC
@@ -6619,31 +6620,59 @@ static void chv_update_pll(struct intel_crtc *crtc)
DPIO_CHV_M1_DIV_BY_2 |
1 << DPIO_CHV_N_DIV_SHIFT);
- /* M2 fraction division */
- vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW2(port), bestm2_frac);
+ if (bestm2_frac) {
+ /* M2 fraction division */
+ vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW2(port), bestm2_frac);
+
+ /* M2 fraction division enable */
+ vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW3(port),
+ vlv_dpio_read(dev_priv, pipe,
CHV_PLL_DW3(port)) &
+ DPIO_CHV_FRAC_DIV_EN);
+
+ /* Program digital lock detect threshold */
+ vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW9(port),
+ vlv_dpio_read(dev_priv, pipe,
CHV_PLL_DW9(port)) |
+ (0x5 << DPIO_CHV_INT_LOCK_THRESHOLD_SHIFT));
+ } else {
+ /* M2 fraction division disable */
+ vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW3(port),
+ vlv_dpio_read(dev_priv, pipe,
CHV_PLL_DW3(port)) &
+ ~(DPIO_CHV_FRAC_DIV_EN));
- /* M2 fraction division enable */
- vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW3(port),
- DPIO_CHV_FRAC_DIV_EN |
- (2 << DPIO_CHV_FEEDFWD_GAIN_SHIFT));
+ /* Program digital lock detect thresho
[Intel-gfx] [v2 1/5] drm/i915: Add new PHY reg definitions for lock threshold
Added new PHY register definitions to control TDC buffer calibration and
digital lock threshold.
Signed-off-by: Vijay Purushothaman
---
drivers/gpu/drm/i915/i915_reg.h | 10 ++
1 file changed, 10 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 1dc91de..5814f67 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -1025,6 +1025,16 @@ enum skl_disp_power_wells {
#define DPIO_CHV_PROP_COEFF_SHIFT0
#define CHV_PLL_DW6(ch) _PIPE(ch, _CHV_PLL_DW6_CH0, _CHV_PLL_DW6_CH1)
+#define _CHV_PLL_DW8_CH0 0x8020
+#define _CHV_PLL_DW8_CH1 0x81A0
+#define CHV_PLL_DW8(ch) _PIPE(ch, _CHV_PLL_DW8_CH0, _CHV_PLL_DW8_CH1)
+
+#define _CHV_PLL_DW9_CH0 0x8024
+#define _CHV_PLL_DW9_CH1 0x81A4
+#define DPIO_CHV_INT_LOCK_THRESHOLD_SHIFT 1 /* 3 bits */
+#define DPIO_CHV_INT_LOCK_THRESHOLD_SEL_COARSE1 /* 1: coarse & 0 :
fine */
+#define CHV_PLL_DW9(ch) _PIPE(ch, _CHV_PLL_DW9_CH0, _CHV_PLL_DW9_CH1)
+
#define _CHV_CMN_DW5_CH0 0x8114
#define CHV_BUFRIGHTENA1_DISABLE (0 << 20)
#define CHV_BUFRIGHTENA1_NORMAL (1 << 20)
--
1.7.9.5
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[Intel-gfx] [v2 0/5] More DPIO magic for CHV HDMI & DP
Changes since version 1: Addressed Ville's review comments Decoded the magic numbers as much as possible Split the single patch into logical patch set Dropped the DPIO_CLK_EN changes Vijay Purushothaman (5): drm/i915: Add new PHY reg definitions for lock threshold drm/i915: Limit max VCO supported in CHV to 6.48GHz drm/i915: Disable M2 frac division for integer case drm/i915: Initialize CHV digital lock detect threshold drm/i915: Update prop, int co-eff and gain threshold for CHV drivers/gpu/drm/i915/i915_reg.h | 11 + drivers/gpu/drm/i915/intel_display.c | 78 +- 2 files changed, 70 insertions(+), 19 deletions(-) -- 1.7.9.5 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [v2 3/5] drm/i915: Disable M2 frac division for integer case
Handle M2 frac division for both M2 frac and int cases
Signed-off-by: Vijay Purushothaman
---
drivers/gpu/drm/i915/intel_display.c | 23 +--
1 file changed, 17 insertions(+), 6 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_display.c
b/drivers/gpu/drm/i915/intel_display.c
index 4e710f6..87d1721 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -6041,6 +6041,7 @@ static void chv_prepare_pll(struct intel_crtc *crtc,
enum dpio_channel port = vlv_pipe_to_channel(pipe);
u32 loopfilter, intcoeff;
u32 bestn, bestm1, bestm2, bestp1, bestp2, bestm2_frac;
+ u32 dpio_val;
int refclk;
bestn = pipe_config->dpll.n;
@@ -6049,6 +6050,7 @@ static void chv_prepare_pll(struct intel_crtc *crtc,
bestm2 = pipe_config->dpll.m2 >> 22;
bestp1 = pipe_config->dpll.p1;
bestp2 = pipe_config->dpll.p2;
+ dpio_val = 0;
/*
* Enable Refclk and SSC
@@ -6073,13 +6075,22 @@ static void chv_prepare_pll(struct intel_crtc *crtc,
DPIO_CHV_M1_DIV_BY_2 |
1 << DPIO_CHV_N_DIV_SHIFT);
- /* M2 fraction division */
- vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW2(port), bestm2_frac);
+ if (bestm2_frac) {
+ /* M2 fraction division */
+ vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW2(port), bestm2_frac);
- /* M2 fraction division enable */
- vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW3(port),
- DPIO_CHV_FRAC_DIV_EN |
- (2 << DPIO_CHV_FEEDFWD_GAIN_SHIFT));
+ /* M2 fraction division enable */
+ dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW3(port));
+ dpio_val |= DPIO_CHV_FRAC_DIV_EN;
+ dpio_val |= (2 << DPIO_CHV_FEEDFWD_GAIN_SHIFT);
+ vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW3(port), dpio_val);
+
+ } else {
+ /* M2 fraction division disable */
+ dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW3(port));
+ dpio_val &= ~(DPIO_CHV_FRAC_DIV_EN);
+ vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW3(port), dpio_val);
+ }
/* Loop filter */
refclk = i9xx_get_refclk(crtc, 0);
--
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[Intel-gfx] [v2 4/5] drm/i915: Initialize CHV digital lock detect threshold
Initialize lock detect threshold and select coarse threshold if M2 is
zero
Signed-off-by: Vijay Purushothaman
---
drivers/gpu/drm/i915/intel_display.c | 11 +++
1 file changed, 11 insertions(+)
diff --git a/drivers/gpu/drm/i915/intel_display.c
b/drivers/gpu/drm/i915/intel_display.c
index 87d1721..ae2a77f 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -6085,11 +6085,22 @@ static void chv_prepare_pll(struct intel_crtc *crtc,
dpio_val |= (2 << DPIO_CHV_FEEDFWD_GAIN_SHIFT);
vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW3(port), dpio_val);
+ /* Program digital lock detect threshold */
+ dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW9(port));
+ dpio_val |= (0x5 << DPIO_CHV_INT_LOCK_THRESHOLD_SHIFT);
+ vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW9(port), dpio_val);
+
} else {
/* M2 fraction division disable */
dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW3(port));
dpio_val &= ~(DPIO_CHV_FRAC_DIV_EN);
vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW3(port), dpio_val);
+
+ /* Program digital lock detect threshold */
+ dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW9(port));
+ dpio_val |= (0x5 << DPIO_CHV_INT_LOCK_THRESHOLD_SHIFT);
+ dpio_val |= DPIO_CHV_INT_LOCK_THRESHOLD_SEL_COARSE;
+ vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW9(port), dpio_val);
}
/* Loop filter */
--
1.7.9.5
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[Intel-gfx] [v2 5/5] drm/i915: Update prop, int co-eff and gain threshold for CHV
This patch implements latest PHY changes in Gain, prop and int co-efficients
based on the vco freq.
Signed-off-by: Vijay Purushothaman
---
drivers/gpu/drm/i915/i915_reg.h |1 +
drivers/gpu/drm/i915/intel_display.c | 42 --
2 files changed, 31 insertions(+), 12 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 5814f67..b5bce4e 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -1027,6 +1027,7 @@ enum skl_disp_power_wells {
#define _CHV_PLL_DW8_CH0 0x8020
#define _CHV_PLL_DW8_CH1 0x81A0
+#define DPIO_CHV_TDC_TARGET_CNT_SHIFT 0
#define CHV_PLL_DW8(ch) _PIPE(ch, _CHV_PLL_DW8_CH0, _CHV_PLL_DW8_CH1)
#define _CHV_PLL_DW9_CH0 0x8024
diff --git a/drivers/gpu/drm/i915/intel_display.c
b/drivers/gpu/drm/i915/intel_display.c
index ae2a77f..ca02cf7 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -6039,10 +6039,10 @@ static void chv_prepare_pll(struct intel_crtc *crtc,
int pipe = crtc->pipe;
int dpll_reg = DPLL(crtc->pipe);
enum dpio_channel port = vlv_pipe_to_channel(pipe);
- u32 loopfilter, intcoeff;
+ u32 loopfilter, tribuf_calcntr;
u32 bestn, bestm1, bestm2, bestp1, bestp2, bestm2_frac;
u32 dpio_val;
- int refclk;
+ int vco;
bestn = pipe_config->dpll.n;
bestm2_frac = pipe_config->dpll.m2 & 0x3f;
@@ -6050,7 +6050,9 @@ static void chv_prepare_pll(struct intel_crtc *crtc,
bestm2 = pipe_config->dpll.m2 >> 22;
bestp1 = pipe_config->dpll.p1;
bestp2 = pipe_config->dpll.p2;
+ vco = pipe_config->dpll.vco;
dpio_val = 0;
+ loopfilter = 0;
/*
* Enable Refclk and SSC
@@ -6104,18 +6106,34 @@ static void chv_prepare_pll(struct intel_crtc *crtc,
}
/* Loop filter */
- refclk = i9xx_get_refclk(crtc, 0);
- loopfilter = 5 << DPIO_CHV_PROP_COEFF_SHIFT |
- 2 << DPIO_CHV_GAIN_CTRL_SHIFT;
- if (refclk == 10)
- intcoeff = 11;
- else if (refclk == 38400)
- intcoeff = 10;
- else
- intcoeff = 9;
- loopfilter |= intcoeff << DPIO_CHV_INT_COEFF_SHIFT;
+ if (vco == 540) {
+ loopfilter |= (0x3 << DPIO_CHV_PROP_COEFF_SHIFT);
+ loopfilter |= (0x8 << DPIO_CHV_INT_COEFF_SHIFT);
+ loopfilter |= (0x1 << DPIO_CHV_GAIN_CTRL_SHIFT);
+ tribuf_calcntr = 0;
+ } else if (vco <= 620) {
+ loopfilter |= (0x5 << DPIO_CHV_PROP_COEFF_SHIFT);
+ loopfilter |= (0xB << DPIO_CHV_INT_COEFF_SHIFT);
+ loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT);
+ tribuf_calcntr = 0x9;
+ } else if (vco <= 648) {
+ loopfilter |= (0x4 << DPIO_CHV_PROP_COEFF_SHIFT);
+ loopfilter |= (0x9 << DPIO_CHV_INT_COEFF_SHIFT);
+ loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT);
+ tribuf_calcntr = 0x8;
+ } else {
+ /* Not supported. Apply the same limits as in the max case */
+ loopfilter |= (0x4 << DPIO_CHV_PROP_COEFF_SHIFT);
+ loopfilter |= (0x9 << DPIO_CHV_INT_COEFF_SHIFT);
+ loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT);
+ tribuf_calcntr = 0;
+ }
vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW6(port), loopfilter);
+ dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW8(pipe));
+ dpio_val |= (tribuf_calcntr << DPIO_CHV_TDC_TARGET_CNT_SHIFT);
+ vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW8(port), dpio_val);
+
/* AFC Recal */
vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port),
vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port)) |
--
1.7.9.5
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[Intel-gfx] [v2 2/5] drm/i915: Limit max VCO supported in CHV to 6.48GHz
As per the recommendation from PHY team, limit the max vco supported in CHV to
6.48 GHz
Signed-off-by: Vijay Purushothaman
---
drivers/gpu/drm/i915/intel_display.c |2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/intel_display.c
b/drivers/gpu/drm/i915/intel_display.c
index 3b0fe9f..4e710f6 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -390,7 +390,7 @@ static const intel_limit_t intel_limits_chv = {
* them would make no difference.
*/
.dot = { .min = 25000 * 5, .max = 54 * 5},
- .vco = { .min = 486, .max = 670 },
+ .vco = { .min = 486, .max = 648 },
.n = { .min = 1, .max = 1 },
.m1 = { .min = 2, .max = 2 },
.m2 = { .min = 24 << 22, .max = 175 << 22 },
--
1.7.9.5
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