Re: [Intel-gfx] [PATCH v2 09/20] drm/i915: Remove references to struct drm_device.pdev
On Tue, 08 Dec 2020, Thomas Zimmermann wrote: > ping for a review of the i915 patches What did you have in mind regarding merging the series? Should we just pick the patches up? BR, Jani. -- Jani Nikula, Intel Open Source Graphics Center ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH 5/6] drm/i915/bios: fill in DSC rc_model_size from VBT
On Tue, 08 Dec 2020, "Navare, Manasi" wrote: > On Tue, Dec 08, 2020 at 02:33:54PM +0200, Jani Nikula wrote: >> The VBT fields match the DPCD data, so use the same helper. >> >> Cc: Manasi Navare >> Cc: Vandita Kulkarni >> Signed-off-by: Jani Nikula > > Only for DSI so far right? Yes. We'll still need a patch to start using the rc_model_size from DPCD for DP. > In that case looks good > > Reviewed-by: Manasi Navare Thanks for the reviews. Pushed up to and including this one to drm-intel-next. The last patch in the series still to be reviewed. BR, Jani. > > Manasi > >> --- >> drivers/gpu/drm/i915/display/intel_bios.c | 11 +++ >> 1 file changed, 3 insertions(+), 8 deletions(-) >> >> diff --git a/drivers/gpu/drm/i915/display/intel_bios.c >> b/drivers/gpu/drm/i915/display/intel_bios.c >> index 4cc949b228f2..06c3310446a2 100644 >> --- a/drivers/gpu/drm/i915/display/intel_bios.c >> +++ b/drivers/gpu/drm/i915/display/intel_bios.c >> @@ -2555,16 +2555,11 @@ static void fill_dsc(struct intel_crtc_state >> *crtc_state, >>crtc_state->dsc.slice_count); >> >> /* >> - * FIXME: Use VBT rc_buffer_block_size and rc_buffer_size for the >> - * implementation specific physical rate buffer size. Currently we use >> - * the required rate buffer model size calculated in >> - * drm_dsc_compute_rc_parameters() according to VESA DSC Annex E. >> - * >> * The VBT rc_buffer_block_size and rc_buffer_size definitions >> - * correspond to DP 1.4 DPCD offsets 0x62 and 0x63. The DP DSC >> - * implementation should also use the DPCD (or perhaps VBT for eDP) >> - * provided value for the buffer size. >> + * correspond to DP 1.4 DPCD offsets 0x62 and 0x63. >> */ >> +vdsc_cfg->rc_model_size = >> drm_dsc_dp_rc_buffer_size(dsc->rc_buffer_block_size, >> + >> dsc->rc_buffer_size); >> >> /* FIXME: DSI spec says bpc + 1 for this one */ >> vdsc_cfg->line_buf_depth = >> VBT_DSC_LINE_BUFFER_DEPTH(dsc->line_buffer_depth); >> -- >> 2.20.1 >> -- Jani Nikula, Intel Open Source Graphics Center ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH 4/9] drm/i915: refactor cursor code out of i915_display.c
On Thu, 10 Dec 2020, Ville Syrjälä wrote:
> On Thu, Dec 10, 2020 at 02:17:50PM +1000, Dave Airlie wrote:
>> From: Dave Airlie
>>
>> This file is a monster, let's start simple, the cursor plane code
>> seems pretty standalone, and splits out easily enough.
>>
>> Signed-off-by: Dave Airlie
>> ---
>> drivers/gpu/drm/i915/Makefile| 1 +
>> drivers/gpu/drm/i915/display/intel_cursor.c | 805 +++
>> drivers/gpu/drm/i915/display/intel_display.c | 796 +-
>> drivers/gpu/drm/i915/display/intel_display.h | 12 +
>
> I would just add the intel_cursor.h for this. intel_display.h is an
> even bigger mess than intel_display.c, and causing no end of redundant
> rebuilds. The smaller we can make it the better IMO.
Separate header for each .c is where we've been heading since we started
refactoring the driver to multiple subdirs instead of the flat
structure, and started chopping up files as a consequence.
Also, please prefix the functions in intel_foo.[ch] with
intel_foo_. This is also where we've been heading for a while now.
BR,
Jani.
>
> Looks like a mechanical move, and seems to match my attempt at it so
> Reviewed-by: Ville Syrjälä
>
>> 4 files changed, 824 insertions(+), 790 deletions(-)
>> create mode 100644 drivers/gpu/drm/i915/display/intel_cursor.c
>>
>> diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makefile
>> index e5574e506a5c..98a35b939052 100644
>> --- a/drivers/gpu/drm/i915/Makefile
>> +++ b/drivers/gpu/drm/i915/Makefile
>> @@ -197,6 +197,7 @@ i915-y += \
>> display/intel_combo_phy.o \
>> display/intel_connector.o \
>> display/intel_csr.o \
>> +display/intel_cursor.o \
>> display/intel_display.o \
>> display/intel_display_power.o \
>> display/intel_dpio_phy.o \
>> diff --git a/drivers/gpu/drm/i915/display/intel_cursor.c
>> b/drivers/gpu/drm/i915/display/intel_cursor.c
>> new file mode 100644
>> index ..87a7a74a25ac
>> --- /dev/null
>> +++ b/drivers/gpu/drm/i915/display/intel_cursor.c
>> @@ -0,0 +1,805 @@
>> +// SPDX-License-Identifier: MIT
>> +/*
>> + * Copyright © 2020 Intel Corporation
>> + */
>> +#include
>> +
>> +#include
>> +#include
>> +#include
>> +#include
>> +#include
>> +
>> +#include "intel_atomic.h"
>> +#include "intel_atomic_plane.h"
>> +#include "intel_display_types.h"
>> +#include "intel_display.h"
>> +
>> +#include "intel_frontbuffer.h"
>> +#include "intel_pm.h"
>> +#include "intel_psr.h"
>> +#include "intel_sprite.h"
>> +
>> +/* Cursor formats */
>> +static const u32 intel_cursor_formats[] = {
>> +DRM_FORMAT_ARGB,
>> +};
>> +
>> +static const u64 cursor_format_modifiers[] = {
>> +DRM_FORMAT_MOD_LINEAR,
>> +DRM_FORMAT_MOD_INVALID
>> +};
>> +
>> +static u32 intel_cursor_base(const struct intel_plane_state *plane_state)
>> +{
>> +struct drm_i915_private *dev_priv =
>> +to_i915(plane_state->uapi.plane->dev);
>> +const struct drm_framebuffer *fb = plane_state->hw.fb;
>> +const struct drm_i915_gem_object *obj = intel_fb_obj(fb);
>> +u32 base;
>> +
>> +if (INTEL_INFO(dev_priv)->display.cursor_needs_physical)
>> +base = sg_dma_address(obj->mm.pages->sgl);
>> +else
>> +base = intel_plane_ggtt_offset(plane_state);
>> +
>> +return base + plane_state->color_plane[0].offset;
>> +}
>> +
>> +static u32 intel_cursor_position(const struct intel_plane_state
>> *plane_state)
>> +{
>> +int x = plane_state->uapi.dst.x1;
>> +int y = plane_state->uapi.dst.y1;
>> +u32 pos = 0;
>> +
>> +if (x < 0) {
>> +pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT;
>> +x = -x;
>> +}
>> +pos |= x << CURSOR_X_SHIFT;
>> +
>> +if (y < 0) {
>> +pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT;
>> +y = -y;
>> +}
>> +pos |= y << CURSOR_Y_SHIFT;
>> +
>> +return pos;
>> +}
>> +
>> +static bool intel_cursor_size_ok(const struct intel_plane_state
>> *plane_state)
>> +{
>> +const struct drm_mode_config *config =
>> +&plane_state->uapi.plane->dev->mode_config;
>> +int width = drm_rect_width(&plane_state->uapi.dst);
>> +int height = drm_rect_height(&plane_state->uapi.dst);
>> +
>> +return width > 0 && width <= config->cursor_width &&
>> +height > 0 && height <= config->cursor_height;
>> +}
>> +
>> +static int intel_cursor_check_surface(struct intel_plane_state *plane_state)
>> +{
>> +struct drm_i915_private *dev_priv =
>> +to_i915(plane_state->uapi.plane->dev);
>> +unsigned int rotation = plane_state->hw.rotation;
>> +int src_x, src_y;
>> +u32 offset;
>> +int ret;
>> +
>> +ret = intel_plane_compute_gtt(plane_state);
>> +if (ret)
>> +return ret;
>> +
>> +if (!plane_state->uapi.visible)
>> +return 0;
>> +
>> +src_x = plane_state->uapi.src.x1 >> 16;
>> +src_y = plane_state->uapi.src.y1 >> 16;
>> +
>> +intel_add_fb_offsets(&src_x, &src_y,
Re: [Intel-gfx] [PATCH] drm/i915/debugfs : PM_REQ and PM_RES register debugfs
[Stripped "--cc=" from Cc: addresses]
On Thu, 10 Dec 2020, Saichandana S wrote:
> From: Saichandana
>
> PM_REQ register provides the value of the last PM request from PCU to
> Display Engine.PM_RES register provides the value of the last PM response from
> Display Engine to PCU.
> This debugfs will be used by DC9 IGT test to know about "DC9 Ready"
> status.
> B.Spec : 49501, 49502
>
> Signed-off-by: Saichandana
> ---
> .../drm/i915/display/intel_display_debugfs.c | 24 +++
> drivers/gpu/drm/i915/i915_reg.h | 5
> 2 files changed, 29 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_display_debugfs.c
> b/drivers/gpu/drm/i915/display/intel_display_debugfs.c
> index cd7e5519ee7d..09e734e54032 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_debugfs.c
> +++ b/drivers/gpu/drm/i915/display/intel_display_debugfs.c
> @@ -559,6 +559,29 @@ static int i915_dmc_info(struct seq_file *m, void
> *unused)
> return 0;
> }
>
> +static int i915_pm_req_res_info(struct seq_file *m, void *unused)
> +{
> +struct drm_i915_private *dev_priv = node_to_i915(m->private);
> +struct intel_csr *csr = &dev_priv->csr;
> +
> +if (!HAS_CSR(dev_priv))
> +return -ENODEV;
> +
> +if (!csr->dmc_payload)
> +return 0;
> +
> +seq_printf(m, "PM debug request 0 (0x45284) : 0x%x\n",
> +intel_de_read(dev_priv, PM_REQ_DBG_0));
> +seq_printf(m, "PM debug request 1 (0x45288) : 0x%x\n",
> +intel_de_read(dev_priv, PM_REQ_DBG_1));
> +seq_printf(m, "PM debug response 0 (0x4528C) : 0x%x\n",
> +intel_de_read(dev_priv, PM_RSP_DBG_0));
> +seq_printf(m, "PM debug response 1 (0x45290) : 0x%x\n",
> +intel_de_read(dev_priv, PM_RSP_DBG_1));
IMO there is no point in providing a debugfs interface for reading and
dumping platform specific registers. Instead, you should provide a more
generic interface that parses the relevant information. Look at *all*
the other register reads in the i915_debugfs.c file. None of them output
the registers as-is.
BR,
Jani.
> +
> +return 0;
> +}
> +
> static void intel_seq_print_mode(struct seq_file *m, int tabs,
>const struct drm_display_mode *mode)
> {
> @@ -2100,6 +2123,7 @@ static const struct drm_info_list
> intel_display_debugfs_list[] = {
> {"i915_edp_psr_status", i915_edp_psr_status, 0},
> {"i915_power_domain_info", i915_power_domain_info, 0},
> {"i915_dmc_info", i915_dmc_info, 0},
> + {"i915_pm_req_res_info", i915_pm_req_res_info, 0},
> {"i915_display_info", i915_display_info, 0},
> {"i915_shared_dplls_info", i915_shared_dplls_info, 0},
> {"i915_dp_mst_info", i915_dp_mst_info, 0},
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 0023c023f472..b477a1f7b1bd 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -371,6 +371,11 @@ static inline bool i915_mmio_reg_valid(i915_reg_t reg)
> #define VLV_G3DCTL _MMIO(0x9024)
> #define VLV_GSCKGCTL _MMIO(0x9028)
>
> +#define PM_REQ_DBG_0 _MMIO(0x45284)
> +#define PM_REQ_DBG_1 _MMIO(0x45288)
> +#define PM_RSP_DBG_0 _MMIO(0x4528C)
> +#define PM_RSP_DBG_1 _MMIO(0x45290)
> +
> #define GEN6_MBCTL _MMIO(0x0907c)
> #define GEN6_MBCTL_ENABLE_BOOT_FETCH (1 << 4)
> #define GEN6_MBCTL_CTX_FETCH_NEEDED(1 << 3)
--
Jani Nikula, Intel Open Source Graphics Center
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915/debugfs : PM_REQ and PM_RES register debugfs
CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis > #37: FILE: drivers/gpu/drm/i915/display/intel_display_debugfs.c:576: > +seq_printf(m, "PM debug request 1 (0x45288) : 0x%x\n", > +intel_de_read(dev_priv, PM_REQ_DBG_1)); > > -:37: WARNING:LEADING_SPACE: please, no spaces at the start of a line > #37: FILE: drivers/gpu/drm/i915/display/intel_display_debugfs.c:576: > +intel_de_read(dev_priv, PM_REQ_DBG_1));$ > > -:38: ERROR:CODE_INDENT: code indent should use tabs where possible > #38: FILE: drivers/gpu/drm/i915/display/intel_display_debugfs.c:577: > +seq_printf(m, "PM debug response 0 (0x4528C) : 0x%x\n",$ > > -:38: WARNING:LEADING_SPACE: please, no spaces at the start of a line > #38: FILE: drivers/gpu/drm/i915/display/intel_display_debugfs.c:577: > +seq_printf(m, "PM debug response 0 (0x4528C) : 0x%x\n",$ > > -:39: ERROR:CODE_INDENT: code indent should use tabs where possible > #39: FILE: drivers/gpu/drm/i915/display/intel_display_debugfs.c:578: > +intel_de_read(dev_priv, PM_RSP_DBG_0));$ > > -:39: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis > #39: FILE: drivers/gpu/drm/i915/display/intel_display_debugfs.c:578: > +seq_printf(m, "PM debug response 0 (0x4528C) : 0x%x\n", > +intel_de_read(dev_priv, PM_RSP_DBG_0)); > > -:39: WARNING:LEADING_SPACE: please, no spaces at the start of a line > #39: FILE: drivers/gpu/drm/i915/display/intel_display_debugfs.c:578: > +intel_de_read(dev_priv, PM_RSP_DBG_0));$ > > -:40: ERROR:CODE_INDENT: code indent should use tabs where possible > #40: FILE: drivers/gpu/drm/i915/display/intel_display_debugfs.c:579: > +seq_printf(m, "PM debug response 1 (0x45290) : 0x%x\n",$ > > -:40: WARNING:LEADING_SPACE: please, no spaces at the start of a line > #40: FILE: drivers/gpu/drm/i915/display/intel_display_debugfs.c:579: > +seq_printf(m, "PM debug response 1 (0x45290) : 0x%x\n",$ > > -:41: ERROR:CODE_INDENT: code indent should use tabs where possible > #41: FILE: drivers/gpu/drm/i915/display/intel_display_debugfs.c:580: > +intel_de_read(dev_priv, PM_RSP_DBG_1));$ > > -:41: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis > #41: FILE: drivers/gpu/drm/i915/display/intel_display_debugfs.c:580: > +seq_printf(m, "PM debug response 1 (0x45290) : 0x%x\n", > +intel_de_read(dev_priv, PM_RSP_DBG_1)); > > -:41: WARNING:LEADING_SPACE: please, no spaces at the start of a line > #41: FILE: drivers/gpu/drm/i915/display/intel_display_debugfs.c:580: > +intel_de_read(dev_priv, PM_RSP_DBG_1));$ > > -:43: ERROR:CODE_INDENT: code indent should use tabs where possible > #43: FILE: drivers/gpu/drm/i915/display/intel_display_debugfs.c:582: > +return 0;$ > > -:43: WARNING:LEADING_SPACE: please, no spaces at the start of a line > #43: FILE: drivers/gpu/drm/i915/display/intel_display_debugfs.c:582: > +return 0;$ > > -:66: WARNING:SPACE_BEFORE_TAB: please, no space before tabs > #66: FILE: drivers/gpu/drm/i915/i915_reg.h:375: > +#define PM_REQ_DBG_1 ^I^I_MMIO(0x45288)$ > > -:67: WARNING:SPACE_BEFORE_TAB: please, no space before tabs > #67: FILE: drivers/gpu/drm/i915/i915_reg.h:376: > +#define PM_RSP_DBG_0 ^I^I_MMIO(0x4528C)$ > > -:68: WARNING:SPACE_BEFORE_TAB: please, no space before tabs > #68: FILE: drivers/gpu/drm/i915/i915_reg.h:377: > +#define PM_RSP_DBG_1 ^I^I_MMIO(0x45290)$ > > total: 15 errors, 19 warnings, 4 checks, 47 lines checked > > > ___ > Intel-gfx mailing list > Intel-gfx@lists.freedesktop.org > https://lists.freedesktop.org/mailman/listinfo/intel-gfx -- Jani Nikula, Intel Open Source Graphics Center ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [RFC-v3 01/13] drm/i915/pxp: Introduce Intel PXP component
pxp_uninit(>->pxp);
> intel_gt_pm_fini(gt);
> intel_gt_fini_scratch(gt);
> intel_gt_fini_buffer_pool(gt);
> diff --git a/drivers/gpu/drm/i915/gt/intel_gt_types.h
> b/drivers/gpu/drm/i915/gt/intel_gt_types.h
> index 6d39a4a11bf3..05255632c2c0 100644
> --- a/drivers/gpu/drm/i915/gt/intel_gt_types.h
> +++ b/drivers/gpu/drm/i915/gt/intel_gt_types.h
> @@ -23,6 +23,7 @@
> #include "intel_rc6_types.h"
> #include "intel_rps_types.h"
> #include "intel_wakeref.h"
> +#include "pxp/intel_pxp.h"
>
> struct drm_i915_private;
> struct i915_ggtt;
> @@ -120,6 +121,8 @@ struct intel_gt {
> /* Slice/subslice/EU info */
> struct sseu_dev_info sseu;
> } info;
> +
> + struct intel_pxp pxp;
> };
>
> enum intel_gt_scratch_field {
> diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp.c
> b/drivers/gpu/drm/i915/pxp/intel_pxp.c
> new file mode 100644
> index ..ba43b2c923c7
> --- /dev/null
> +++ b/drivers/gpu/drm/i915/pxp/intel_pxp.c
> @@ -0,0 +1,27 @@
> +// SPDX-License-Identifier: MIT
> +/*
> + * Copyright(c) 2020 Intel Corporation.
> + */
> +#include "i915_drv.h"
> +#include "intel_pxp.h"
> +#include "intel_pxp_context.h"
> +
> +int intel_pxp_init(struct intel_pxp *pxp)
> +{
> + struct intel_gt *gt = container_of(pxp, struct intel_gt, pxp);
> +
> + /* PXP only available for GEN12+ */
> + if (INTEL_GEN(gt->i915) < 12)
> + return -ENODEV;
> +
> + intel_pxp_ctx_init(&pxp->ctx);
> +
> + drm_info(>->i915->drm, "Protected Xe Path (PXP) protected content
> support initialized\n");
> +
> + return 0;
> +}
> +
> +void intel_pxp_uninit(struct intel_pxp *pxp)
> +{
> + intel_pxp_ctx_fini(&pxp->ctx);
> +}
> diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp.h
> b/drivers/gpu/drm/i915/pxp/intel_pxp.h
> new file mode 100644
> index ..7c3d49a6a3ab
> --- /dev/null
> +++ b/drivers/gpu/drm/i915/pxp/intel_pxp.h
> @@ -0,0 +1,29 @@
> +/* SPDX-License-Identifier: MIT */
> +/*
> + * Copyright(c) 2020, Intel Corporation. All rights reserved.
> + */
> +
> +#ifndef __INTEL_PXP_H__
> +#define __INTEL_PXP_H__
> +
> +#include "intel_pxp_context.h"
> +
> +struct intel_pxp {
> + struct pxp_context ctx;
> +};
> +
> +#ifdef CONFIG_DRM_I915_PXP
> +int intel_pxp_init(struct intel_pxp *pxp);
> +void intel_pxp_uninit(struct intel_pxp *pxp);
> +#else
> +static inline int intel_pxp_init(struct intel_pxp *pxp)
> +{
> + return 0;
> +}
> +
> +static inline void intel_pxp_uninit(struct intel_pxp *pxp)
> +{
> +}
> +#endif
> +
> +#endif /* __INTEL_PXP_PM_H__ */
> diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp_context.c
> b/drivers/gpu/drm/i915/pxp/intel_pxp_context.c
> new file mode 100644
> index ..5ffaf55dc7df
> --- /dev/null
> +++ b/drivers/gpu/drm/i915/pxp/intel_pxp_context.c
> @@ -0,0 +1,27 @@
> +// SPDX-License-Identifier: MIT
> +/*
> + * Copyright(c) 2020, Intel Corporation. All rights reserved.
> + */
> +
> +#include "intel_pxp_context.h"
> +#include
> +
> +/**
> + * intel_pxp_ctx_init - To init a pxp context.
> + * @ctx: pointer to ctx structure.
> + */
> +void intel_pxp_ctx_init(struct pxp_context *ctx)
> +{
> + get_random_bytes(&ctx->id, sizeof(ctx->id));
> +
> + mutex_init(&ctx->mutex);
> +}
> +
> +/**
> + * intel_pxp_ctx_fini - To finish the pxp context.
> + * @ctx: pointer to ctx structure.
> + */
> +void intel_pxp_ctx_fini(struct pxp_context *ctx)
> +{
> + ctx->id = 0;
> +}
> diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp_context.h
> b/drivers/gpu/drm/i915/pxp/intel_pxp_context.h
> new file mode 100644
> index ..953a2e700931
> --- /dev/null
> +++ b/drivers/gpu/drm/i915/pxp/intel_pxp_context.h
> @@ -0,0 +1,22 @@
> +/* SPDX-License-Identifier: MIT */
> +/*
> + * Copyright(c) 2020, Intel Corporation. All rights reserved.
> + */
> +
> +#ifndef __INTEL_PXP_CONTEXT_H__
> +#define __INTEL_PXP_CONTEXT_H__
> +
> +#include
> +
> +/* struct pxp_context - Represents combined view of driver and logical HW
> states. */
> +struct pxp_context {
> + /** @mutex: mutex to protect the pxp context */
> + struct mutex mutex;
> +
> + int id;
> +};
> +
> +void intel_pxp_ctx_init(struct pxp_context *ctx);
> +void intel_pxp_ctx_fini(struct pxp_context *ctx);
> +
> +#endif /* __INTEL_PXP_CONTEXT_H__ */
--
Jani Nikula, Intel Open Source Graphics Center
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [RFC-v3 02/13] drm/i915/pxp: set KCR reg init during the boot time
On Tue, 08 Dec 2020, "Huang, Sean Z" wrote:
> Set the KCR init during the boot time, which is
> required by hardware, to allow us doing further
> protection operation such as sending commands to
> GPU or TEE.
>
> Signed-off-by: Huang, Sean Z
> ---
> drivers/gpu/drm/i915/pxp/intel_pxp.c | 8
> drivers/gpu/drm/i915/pxp/intel_pxp.h | 6 ++
> 2 files changed, 14 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp.c
> b/drivers/gpu/drm/i915/pxp/intel_pxp.c
> index ba43b2c923c7..c4815950567d 100644
> --- a/drivers/gpu/drm/i915/pxp/intel_pxp.c
> +++ b/drivers/gpu/drm/i915/pxp/intel_pxp.c
> @@ -6,6 +6,12 @@
> #include "intel_pxp.h"
> #include "intel_pxp_context.h"
>
> +/* KCR register definitions */
> +#define KCR_INIT_MMIO(0x320f0)
> +#define KCR_INIT_MASK_SHIFT (16)
> +/* Setting KCR Init bit is required after system boot */
> +#define KCR_INIT_ALLOW_DISPLAY_ME_WRITES (BIT(14) | (BIT(14) <<
> KCR_INIT_MASK_SHIFT))
> +
Why here instead of i915_reg.h?
Please at least follow the style described at the top of that file.
BR,
Jani.
> int intel_pxp_init(struct intel_pxp *pxp)
> {
> struct intel_gt *gt = container_of(pxp, struct intel_gt, pxp);
> @@ -16,6 +22,8 @@ int intel_pxp_init(struct intel_pxp *pxp)
>
> intel_pxp_ctx_init(&pxp->ctx);
>
> + intel_uncore_write(gt->uncore, KCR_INIT,
> KCR_INIT_ALLOW_DISPLAY_ME_WRITES);
> +
> drm_info(>->i915->drm, "Protected Xe Path (PXP) protected content
> support initialized\n");
>
> return 0;
> diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp.h
> b/drivers/gpu/drm/i915/pxp/intel_pxp.h
> index 7c3d49a6a3ab..b906bf7dea90 100644
> --- a/drivers/gpu/drm/i915/pxp/intel_pxp.h
> +++ b/drivers/gpu/drm/i915/pxp/intel_pxp.h
> @@ -15,6 +15,7 @@ struct intel_pxp {
> #ifdef CONFIG_DRM_I915_PXP
> int intel_pxp_init(struct intel_pxp *pxp);
> void intel_pxp_uninit(struct intel_pxp *pxp);
> +int intel_pxp_reg_read(struct intel_pxp *pxp, u32 offset, u32 *regval);
> #else
> static inline int intel_pxp_init(struct intel_pxp *pxp)
> {
> @@ -24,6 +25,11 @@ static inline int intel_pxp_init(struct intel_pxp *pxp)
> static inline void intel_pxp_uninit(struct intel_pxp *pxp)
> {
> }
> +
> +static inline int intel_pxp_reg_read(struct intel_pxp *pxp, u32 offset, u32
> *regval)
> +{
> + return 0;
> +}
> #endif
>
> #endif /* __INTEL_PXP_PM_H__ */
--
Jani Nikula, Intel Open Source Graphics Center
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [RFC-v3 03/13] drm/i915/pxp: Implement funcs to create the TEE channel
ee.h
> new file mode 100644
> index ..4b5e3edb1d9b
> --- /dev/null
> +++ b/drivers/gpu/drm/i915/pxp/intel_pxp_tee.h
> @@ -0,0 +1,14 @@
> +/* SPDX-License-Identifier: MIT */
> +/*
> + * Copyright(c) 2020, Intel Corporation. All rights reserved.
> + */
> +
> +#ifndef __INTEL_PXP_TEE_H__
> +#define __INTEL_PXP_TEE_H__
> +
> +#include "intel_pxp.h"
> +
> +void intel_pxp_tee_component_init(struct intel_pxp *pxp);
> +void intel_pxp_tee_component_fini(struct intel_pxp *pxp);
> +
> +#endif /* __INTEL_PXP_TEE_H__ */
> diff --git a/include/drm/i915_component.h b/include/drm/i915_component.h
> index 55c3b123581b..c1e2a43d2d1e 100644
> --- a/include/drm/i915_component.h
> +++ b/include/drm/i915_component.h
> @@ -29,6 +29,7 @@
> enum i915_component_type {
> I915_COMPONENT_AUDIO = 1,
> I915_COMPONENT_HDCP,
> + I915_COMPONENT_PXP
> };
>
> /* MAX_PORT is the number of port
> diff --git a/include/drm/i915_pxp_tee_interface.h
> b/include/drm/i915_pxp_tee_interface.h
> new file mode 100644
> index ..3999e255e145
> --- /dev/null
> +++ b/include/drm/i915_pxp_tee_interface.h
> @@ -0,0 +1,45 @@
> +/* SPDX-License-Identifier: MIT */
> +/*
> + * Copyright © 2020 Intel Corporation
> + *
> + * Authors:
> + * Vitaly Lubart
Do we need the author lines? I'd prefer phasing them all out, because
it'll be stale almost immediately after merging. Also, it's just 40
lines of definitions.
BR,
Jani.
> + */
> +
> +#ifndef _I915_PXP_TEE_INTERFACE_H_
> +#define _I915_PXP_TEE_INTERFACE_H_
> +
> +#include
> +#include
> +
> +/**
> + * struct i915_pxp_component_ops - ops for PXP services.
> + * @owner: Module providing the ops
> + * @send: sends data to PXP
> + * @receive: receives data from PXP
> + */
> +struct i915_pxp_component_ops {
> + /**
> + * @owner: owner of the module provding the ops
> + */
> + struct module *owner;
> +
> + int (*send)(struct device *dev, const void *message, size_t size);
> + int (*receive)(struct device *dev, void *buffer, size_t size);
> +};
> +
> +/**
> + * struct i915_pxp_component_master - Used for communication between i915
> + * and TEE drivers for the PXP services
> + * @tee_dev: device that provide the PXP service from TEE Bus.
> + * @pxp_ops: Ops implemented by TEE driver, used by i915 driver.
> + */
> +struct i915_pxp_comp_master {
> + struct device *tee_dev;
> + const struct i915_pxp_component_ops *ops;
> +
> + /* To protect the above members. */
> + struct mutex mutex;
> +};
> +
> +#endif /* _I915_TEE_PXP_INTERFACE_H_ */
--
Jani Nikula, Intel Open Source Graphics Center
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [RFC-v3 05/13] drm/i915/pxp: Func to send hardware session termination
drm_err(>->i915->drm, "Failed to
> intel_pxp_cmd_get_batch()\n");
> + goto end;
> + }
> +
> + err = i915_vma_pin(batch, 0, 0, PIN_USER);
> + if (err) {
> + drm_err(>->i915->drm, "Failed to i915_vma_pin()\n");
> + goto end;
> + }
> + is_batch_vma_pin = true;
> +
> + rq = intel_context_create_request(ce);
> + if (IS_ERR(rq)) {
> + drm_err(>->i915->drm, "Failed to
> intel_context_create_request()\n");
> + goto end;
> + }
> + is_skip_req_on_err = true;
> +
> + err = intel_gt_buffer_pool_mark_active(pool, rq);
> + if (err) {
> + drm_err(>->i915->drm, "Failed to
> intel_engine_pool_mark_active()\n");
> + goto end;
> + }
> +
> + i915_vma_lock(batch);
> + err = i915_request_await_object(rq, batch->obj, false);
> + if (!err)
> + err = i915_vma_move_to_active(batch, rq, 0);
> + i915_vma_unlock(batch);
> + if (err) {
> + drm_err(>->i915->drm, "Failed to
> i915_request_await_object()\n");
> + goto end;
> + }
> +
> + if (ce->engine->emit_init_breadcrumb) {
> + err = ce->engine->emit_init_breadcrumb(rq);
> + if (err) {
> + drm_err(>->i915->drm, "Failed to
> emit_init_breadcrumb()\n");
> + goto end;
> + }
> + }
> +
> + err = ce->engine->emit_bb_start(rq, batch->node.start,
> + batch->node.size, 0);
> + if (err) {
> + drm_err(>->i915->drm, "Failed to emit_bb_start()\n");
> + goto end;
> + }
> +
> + i915_request_add(rq);
> +
> +end:
> + if (unlikely(err) && is_skip_req_on_err)
Please avoid using likely/unlikely unless performance really matters
*and* you know it matters.
Usually error handling is done via labels where you goto, not via a
plethora of booleans.
BR,
Jani.
> + i915_request_set_error_once(rq, err);
> +
> + if (is_batch_vma_pin)
> + i915_vma_unpin(batch);
> +
> + if (is_engine_get_pool)
> + intel_gt_buffer_pool_put(pool);
> +
> + if (is_engine_pm_get)
> + intel_engine_pm_put(ce->engine);
> +
> + return err;
> +}
> diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp_cmd.h
> b/drivers/gpu/drm/i915/pxp/intel_pxp_cmd.h
> new file mode 100644
> index ..d04463962421
> --- /dev/null
> +++ b/drivers/gpu/drm/i915/pxp/intel_pxp_cmd.h
> @@ -0,0 +1,18 @@
> +/* SPDX-License-Identifier: MIT */
> +/*
> + * Copyright(c) 2020, Intel Corporation. All rights reserved.
> + */
> +
> +#ifndef __INTEL_PXP_CMD_H__
> +#define __INTEL_PXP_CMD_H__
> +
> +#include "gt/intel_gt_buffer_pool.h"
> +#include "intel_pxp.h"
> +
> +struct i915_vma *intel_pxp_cmd_get_batch(struct intel_pxp *pxp,
> + struct intel_context *ce,
> + struct intel_gt_buffer_pool_node *pool,
> + u32 *cmd_buf, int cmd_size_in_dw);
> +
> +int intel_pxp_cmd_submit(struct intel_pxp *pxp, u32 *cmd, int
> cmd_size_in_dw);
> +#endif /* __INTEL_PXP_SM_H__ */
--
Jani Nikula, Intel Open Source Graphics Center
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [RFC-v3 06/13] drm/i915/pxp: Enable PXP irq worker and callback stub
n_unlock_irq(>->irq_lock);
> +
> + if (events & PXP_IRQ_VECTOR_DISPLAY_PXP_STATE_TERMINATED ||
> + events & PXP_IRQ_VECTOR_DISPLAY_APP_TERM_PER_FW_REQ)
> + intel_pxp_teardown_required_callback(pxp);
> +
> + if (events & PXP_IRQ_VECTOR_PXP_DISP_STATE_RESET_COMPLETE)
> + intel_pxp_global_terminate_complete_callback(pxp);
> +
> + spin_lock_irq(>->irq_lock);
> + intel_pxp_write_irq_mask_reg(gt, 0);
> + spin_unlock_irq(>->irq_lock);
> +}
> +
> int intel_pxp_init(struct intel_pxp *pxp)
> {
> struct intel_gt *gt = container_of(pxp, struct intel_gt, pxp);
> @@ -28,6 +92,12 @@ int intel_pxp_init(struct intel_pxp *pxp)
>
> intel_pxp_tee_component_init(pxp);
>
> + INIT_WORK(&pxp->irq_work, intel_pxp_irq_work);
> +
> + pxp->handled_irr = (PXP_IRQ_VECTOR_DISPLAY_PXP_STATE_TERMINATED |
> + PXP_IRQ_VECTOR_DISPLAY_APP_TERM_PER_FW_REQ |
> + PXP_IRQ_VECTOR_PXP_DISP_STATE_RESET_COMPLETE);
> +
> drm_info(>->i915->drm, "Protected Xe Path (PXP) protected content
> support initialized\n");
>
> return 0;
> @@ -39,3 +109,34 @@ void intel_pxp_uninit(struct intel_pxp *pxp)
>
> intel_pxp_ctx_fini(&pxp->ctx);
> }
> +
> +/**
> + * intel_pxp_irq_handler - Proxies KCR interrupts to PXP.
> + * @pxp: pointer to pxp struct
> + * @iir: GT interrupt vector associated with the interrupt
> + *
> + * Dispatches each vector element into an IRQ to PXP.
> + */
> +void intel_pxp_irq_handler(struct intel_pxp *pxp, u16 iir)
> +{
> + struct drm_i915_private *i915;
> + const u32 events = iir & pxp->handled_irr;
> + struct intel_gt *gt = container_of(pxp, typeof(*gt), pxp);
> +
> + if (!gt || !gt->i915 || INTEL_GEN(i915) < 12)
> + return;
> +
> + i915 = gt->i915;
> +
> + lockdep_assert_held(>->irq_lock);
> +
> + if (unlikely(!events)) {
> + drm_err(&i915->drm, "%s returned due to iir=[0x%04x]\n",
> __func__, iir);
> + return;
> + }
> +
> + intel_pxp_write_irq_mask_reg(gt, pxp->handled_irr);
> +
> + pxp->current_events |= events;
> + schedule_work(&pxp->irq_work);
> +}
> diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp.h
> b/drivers/gpu/drm/i915/pxp/intel_pxp.h
> index 406d35f402a6..c8c580cee5bc 100644
> --- a/drivers/gpu/drm/i915/pxp/intel_pxp.h
> +++ b/drivers/gpu/drm/i915/pxp/intel_pxp.h
> @@ -6,8 +6,13 @@
> #ifndef __INTEL_PXP_H__
> #define __INTEL_PXP_H__
>
> +#include
> #include "intel_pxp_context.h"
>
> +#define PXP_IRQ_VECTOR_DISPLAY_PXP_STATE_TERMINATED BIT(1)
> +#define PXP_IRQ_VECTOR_DISPLAY_APP_TERM_PER_FW_REQ BIT(2)
> +#define PXP_IRQ_VECTOR_PXP_DISP_STATE_RESET_COMPLETE BIT(3)
> +
> enum pxp_session_types {
> SESSION_TYPE_TYPE0 = 0,
> SESSION_TYPE_TYPE1 = 1,
> @@ -25,14 +30,36 @@ enum pxp_protection_modes {
> };
>
> struct intel_pxp {
> + struct work_struct irq_work;
> + u32 handled_irr;
> + u32 current_events;
> +
> struct pxp_context ctx;
> };
>
> #ifdef CONFIG_DRM_I915_PXP
> +void intel_pxp_irq_handler(struct intel_pxp *pxp, u16 iir);
> +int i915_pxp_teardown_required_callback(struct intel_pxp *pxp);
> +int i915_pxp_global_terminate_complete_callback(struct intel_pxp *pxp);
> +
> int intel_pxp_init(struct intel_pxp *pxp);
> void intel_pxp_uninit(struct intel_pxp *pxp);
> int intel_pxp_reg_read(struct intel_pxp *pxp, u32 offset, u32 *regval);
> #else
> +static inline void intel_pxp_irq_handler(struct intel_pxp *pxp, u16 iir)
> +{
> +}
> +
> +static inline int i915_pxp_teardown_required_callback(struct intel_pxp *pxp)
> +{
> + return 0;
> +}
> +
> +static inline int i915_pxp_global_terminate_complete_callback(struct
> intel_pxp *pxp)
> +{
> + return 0;
> +}
> +
> static inline int intel_pxp_init(struct intel_pxp *pxp)
> {
> return 0;
> diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp_context.c
> b/drivers/gpu/drm/i915/pxp/intel_pxp_context.c
> index 5ffaf55dc7df..d00f4e0b88ba 100644
> --- a/drivers/gpu/drm/i915/pxp/intel_pxp_context.c
> +++ b/drivers/gpu/drm/i915/pxp/intel_pxp_context.c
> @@ -14,6 +14,8 @@ void intel_pxp_ctx_init(struct pxp_context *ctx)
> {
> get_random_bytes(&ctx->id, sizeof(ctx->id));
>
> + ctx->global_state_attacked = false;
> +
> mutex_init(&ctx->mutex);
> }
>
> diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp_context.h
> b/drivers/gpu/drm/i915/pxp/intel_pxp_context.h
> index e37125ed7434..62a2504b33bf 100644
> --- a/drivers/gpu/drm/i915/pxp/intel_pxp_context.h
> +++ b/drivers/gpu/drm/i915/pxp/intel_pxp_context.h
> @@ -18,6 +18,7 @@ struct pxp_context {
>
> int id;
>
> + bool global_state_attacked;
> bool flag_display_hm_surface_keys;
> };
--
Jani Nikula, Intel Open Source Graphics Center
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [patch 13/30] drm/i915/lpe_audio: Remove pointless irq_to_desc() usage
On Thu, 10 Dec 2020, Ville Syrjälä wrote:
> On Thu, Dec 10, 2020 at 08:25:49PM +0100, Thomas Gleixner wrote:
>> Nothing uses the result and nothing should ever use it in driver code.
>>
>> Signed-off-by: Thomas Gleixner
>> Cc: Jani Nikula
>> Cc: Joonas Lahtinen
>> Cc: Rodrigo Vivi
>> Cc: David Airlie
>> Cc: Daniel Vetter
>> Cc: Pankaj Bharadiya
>> Cc: Chris Wilson
>> Cc: Wambui Karuga
>> Cc: intel-gfx@lists.freedesktop.org
>> Cc: dri-de...@lists.freedesktop.org
>
> Reviewed-by: Ville Syrjälä
Thomas, I presume you want to merge this series as a whole.
Acked-by: Jani Nikula
for merging via whichever tree makes most sense. Please let us know if
you want us to pick this up via drm-intel instead.
>
>> ---
>> drivers/gpu/drm/i915/display/intel_lpe_audio.c |4
>> 1 file changed, 4 deletions(-)
>>
>> --- a/drivers/gpu/drm/i915/display/intel_lpe_audio.c
>> +++ b/drivers/gpu/drm/i915/display/intel_lpe_audio.c
>> @@ -297,13 +297,9 @@ int intel_lpe_audio_init(struct drm_i915
>> */
>> void intel_lpe_audio_teardown(struct drm_i915_private *dev_priv)
>> {
>> -struct irq_desc *desc;
>> -
>> if (!HAS_LPE_AUDIO(dev_priv))
>> return;
>>
>> -desc = irq_to_desc(dev_priv->lpe_audio.irq);
>> -
>> lpe_audio_platdev_destroy(dev_priv);
>>
>> irq_free_desc(dev_priv->lpe_audio.irq);
>>
>> ___
>> Intel-gfx mailing list
>> Intel-gfx@lists.freedesktop.org
>> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
--
Jani Nikula, Intel Open Source Graphics Center
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [patch 14/30] drm/i915/pmu: Replace open coded kstat_irqs() copy
On Thu, 10 Dec 2020, Thomas Gleixner wrote:
> Driver code has no business with the internals of the irq descriptor.
>
> Aside of that the count is per interrupt line and therefore takes
> interrupts from other devices into account which share the interrupt line
> and are not handled by the graphics driver.
>
> Replace it with a pmu private count which only counts interrupts which
> originate from the graphics card.
>
> To avoid atomics or heuristics of some sort make the counter field
> 'unsigned long'. That limits the count to 4e9 on 32bit which is a lot and
> postprocessing can easily deal with the occasional wraparound.
I'll let Tvrtko and Chris review the substance here, but assuming they
don't object,
Acked-by: Jani Nikula
for merging via whichever tree makes most sense.
>
> Signed-off-by: Thomas Gleixner
> Cc: Tvrtko Ursulin
> Cc: Jani Nikula
> Cc: Joonas Lahtinen
> Cc: Rodrigo Vivi
> Cc: David Airlie
> Cc: Daniel Vetter
> Cc: intel-gfx@lists.freedesktop.org
> Cc: dri-de...@lists.freedesktop.org
> ---
> drivers/gpu/drm/i915/i915_irq.c | 34 ++
> drivers/gpu/drm/i915/i915_pmu.c | 18 +-
> drivers/gpu/drm/i915/i915_pmu.h |8
> 3 files changed, 43 insertions(+), 17 deletions(-)
>
> --- a/drivers/gpu/drm/i915/i915_irq.c
> +++ b/drivers/gpu/drm/i915/i915_irq.c
> @@ -60,6 +60,24 @@
> * and related files, but that will be described in separate chapters.
> */
>
> +/*
> + * Interrupt statistic for PMU. Increments the counter only if the
> + * interrupt originated from the the GPU so interrupts from a device which
> + * shares the interrupt line are not accounted.
> + */
> +static inline void pmu_irq_stats(struct drm_i915_private *priv,
> + irqreturn_t res)
> +{
> + if (unlikely(res != IRQ_HANDLED))
> + return;
> +
> + /*
> + * A clever compiler translates that into INC. A not so clever one
> + * should at least prevent store tearing.
> + */
> + WRITE_ONCE(priv->pmu.irq_count, priv->pmu.irq_count + 1);
> +}
> +
> typedef bool (*long_pulse_detect_func)(enum hpd_pin pin, u32 val);
>
> static const u32 hpd_ilk[HPD_NUM_PINS] = {
> @@ -1599,6 +1617,8 @@ static irqreturn_t valleyview_irq_handle
> valleyview_pipestat_irq_handler(dev_priv, pipe_stats);
> } while (0);
>
> + pmu_irq_stats(dev_priv, ret);
> +
> enable_rpm_wakeref_asserts(&dev_priv->runtime_pm);
>
> return ret;
> @@ -1676,6 +1696,8 @@ static irqreturn_t cherryview_irq_handle
> valleyview_pipestat_irq_handler(dev_priv, pipe_stats);
> } while (0);
>
> + pmu_irq_stats(dev_priv, ret);
> +
> enable_rpm_wakeref_asserts(&dev_priv->runtime_pm);
>
> return ret;
> @@ -2103,6 +2125,8 @@ static irqreturn_t ilk_irq_handler(int i
> if (sde_ier)
> raw_reg_write(regs, SDEIER, sde_ier);
>
> + pmu_irq_stats(i915, ret);
> +
> /* IRQs are synced during runtime_suspend, we don't require a wakeref */
> enable_rpm_wakeref_asserts(&i915->runtime_pm);
>
> @@ -2419,6 +2443,8 @@ static irqreturn_t gen8_irq_handler(int
>
> gen8_master_intr_enable(regs);
>
> + pmu_irq_stats(dev_priv, IRQ_HANDLED);
> +
> return IRQ_HANDLED;
> }
>
> @@ -2514,6 +2540,8 @@ static __always_inline irqreturn_t
>
> gen11_gu_misc_irq_handler(gt, gu_misc_iir);
>
> + pmu_irq_stats(i915, IRQ_HANDLED);
> +
> return IRQ_HANDLED;
> }
>
> @@ -3688,6 +3716,8 @@ static irqreturn_t i8xx_irq_handler(int
> i8xx_pipestat_irq_handler(dev_priv, iir, pipe_stats);
> } while (0);
>
> + pmu_irq_stats(dev_priv, ret);
> +
> enable_rpm_wakeref_asserts(&dev_priv->runtime_pm);
>
> return ret;
> @@ -3796,6 +3826,8 @@ static irqreturn_t i915_irq_handler(int
> i915_pipestat_irq_handler(dev_priv, iir, pipe_stats);
> } while (0);
>
> + pmu_irq_stats(dev_priv, ret);
> +
> enable_rpm_wakeref_asserts(&dev_priv->runtime_pm);
>
> return ret;
> @@ -3941,6 +3973,8 @@ static irqreturn_t i965_irq_handler(int
> i965_pipestat_irq_handler(dev_priv, iir, pipe_stats);
> } while (0);
>
> + pmu_irq_stats(dev_priv, IRQ_HANDLED);
> +
> enable_rpm_wakeref_asserts(&dev_priv->runtime_pm);
>
> return ret;
> --- a/drivers/gpu/drm/i915/i915_pmu.c
> +++ b/drivers/gpu/drm/i915/i915_pmu.c
> @@ -423,22 +423,6 @@ static enum hrtimer_restart i915_sample(
>
Re: [Intel-gfx] [PATCH] drm/i915/display/tc: Only WARN once for bogus tc port flag
On Wed, 09 Dec 2020, Rodrigo Vivi wrote: > On Wed, Dec 09, 2020 at 04:16:36PM -0500, Sean Paul wrote: >> From: Sean Paul >> >> No need to spam syslog/console when we can ignore/fix the flag. > > besides that we are calling from multiple places anyway.. > >> >> Signed-off-by: Sean Paul > > > Reviewed-by: Rodrigo Vivi Thanks, pushed to din. BR, Jani. > > > >> --- >> drivers/gpu/drm/i915/display/intel_tc.c | 2 +- >> 1 file changed, 1 insertion(+), 1 deletion(-) >> >> diff --git a/drivers/gpu/drm/i915/display/intel_tc.c >> b/drivers/gpu/drm/i915/display/intel_tc.c >> index 4346bc1a747a..27dc2dad6809 100644 >> --- a/drivers/gpu/drm/i915/display/intel_tc.c >> +++ b/drivers/gpu/drm/i915/display/intel_tc.c >> @@ -262,7 +262,7 @@ static u32 tc_port_live_status_mask(struct >> intel_digital_port *dig_port) >> mask |= BIT(TC_PORT_LEGACY); >> >> /* The sink can be connected only in a single mode. */ >> -if (!drm_WARN_ON(&i915->drm, hweight32(mask) > 1)) >> +if (!drm_WARN_ON_ONCE(&i915->drm, hweight32(mask) > 1)) >> tc_port_fixup_legacy_flag(dig_port, mask); >> >> return mask; >> -- >> Sean Paul, Software Engineer, Google / Chromium OS >> >> ___ >> dri-devel mailing list >> dri-de...@lists.freedesktop.org >> https://lists.freedesktop.org/mailman/listinfo/dri-devel > ___ > Intel-gfx mailing list > Intel-gfx@lists.freedesktop.org > https://lists.freedesktop.org/mailman/listinfo/intel-gfx -- Jani Nikula, Intel Open Source Graphics Center ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH 1/1] drm/i915/dp: optimize pps_lock wherever required
On Fri, 04 Dec 2020, Anshuman Gupta wrote:
> Reading backlight status from PPS register doesn't require
> AUX power on the platform which has South Display Engine on PCH.
> It invokes a unnecessary power well enable/disable noise.
> optimize it wherever is possible.
Three aspects here:
1. What's the root cause for the glitches, really? AFAICT this is still
an open question, judging from the discussion in previous versions.
2. See why we end up here in the first place for brightness
updates. It's a long story (*), but maybe the fix isn't to optimize this
path, but to avoid calling this function for regular brightness updates
to begin with?
3. The implementation here seems like a hack, to be honest. Considering
the points above, it really has a bad vibe of papering over something
else.
BR,
Jani.
(*)
It was a Chrome OS requirement originally to be able to quickly switch
off backlight through the backlight sysfs interface, without switching
off the display through the KMS API. For whatever reason. We can't just
set the PWM to 0, because that may an invalid thing to do on some boards
out there. (On some device it ended up pulling other lanes on the eDP
connector to 0 V, but I digress.)
So the hack is we have a way to switch the eDP power sequencer backlight
bit off/on, as a substate of enabled backlight, through using the
backlight sysfs to set the brightness to 0 or using bl_power.
>
> Signed-off-by: Anshuman Gupta
> ---
> drivers/gpu/drm/i915/display/intel_dp.c | 47 +++--
> 1 file changed, 45 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_dp.c
> b/drivers/gpu/drm/i915/display/intel_dp.c
> index 2d4d5e95af84..7e18e4ff50f4 100644
> --- a/drivers/gpu/drm/i915/display/intel_dp.c
> +++ b/drivers/gpu/drm/i915/display/intel_dp.c
> @@ -892,6 +892,47 @@ pps_unlock(struct intel_dp *intel_dp, intel_wakeref_t
> wakeref)
> return 0;
> }
>
> +/*
> + * Platform with PCH based SDE doesn't require to enable AUX power
> + * for simple PPS register access like whether backlight is enabled.
> + * use pch_pps_lock()/pch_pps_unlock() wherever we don't require
> + * aux power to avoid unnecessary power well enable/disable back
> + * and forth.
> + */
> +static intel_wakeref_t
> +pch_pps_lock(struct intel_dp *intel_dp)
> +{
> + struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
> + intel_wakeref_t wakeref;
> +
> + if (!HAS_PCH_SPLIT(dev_priv))
> + wakeref = intel_display_power_get(dev_priv,
> +
> intel_aux_power_domain(dp_to_dig_port(intel_dp)));
> + else
> + wakeref = intel_runtime_pm_get(&dev_priv->runtime_pm);
> +
> + mutex_lock(&dev_priv->pps_mutex);
> +
> + return wakeref;
> +}
> +
> +static intel_wakeref_t
> +pch_pps_unlock(struct intel_dp *intel_dp, intel_wakeref_t wakeref)
> +{
> + struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
> +
> + mutex_unlock(&dev_priv->pps_mutex);
> +
> + if (!HAS_PCH_SPLIT(dev_priv))
> + intel_display_power_put(dev_priv,
> +
> intel_aux_power_domain(dp_to_dig_port(intel_dp)),
> + wakeref);
> + else
> + intel_runtime_pm_put(&dev_priv->runtime_pm, wakeref);
> +
> + return 0;
> +}
> +
> #define with_pps_lock(dp, wf) \
> for ((wf) = pps_lock(dp); (wf); (wf) = pps_unlock((dp), (wf)))
>
> @@ -3453,8 +3494,10 @@ static void intel_edp_backlight_power(struct
> intel_connector *connector,
> bool is_enabled;
>
> is_enabled = false;
> - with_pps_lock(intel_dp, wakeref)
> - is_enabled = ilk_get_pp_control(intel_dp) & EDP_BLC_ENABLE;
> + wakeref = pch_pps_lock(intel_dp);
> + is_enabled = ilk_get_pp_control(intel_dp) & EDP_BLC_ENABLE;
> + pch_pps_unlock(intel_dp, wakeref);
> +
> if (is_enabled == enable)
> return;
--
Jani Nikula, Intel Open Source Graphics Center
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [RFC 3/5] drm/i915/dp: Remove redundant AUX backlight frequency calculations
On Wed, 09 Dec 2020, Lyude Paul wrote:
> Noticed this while moving all of the VESA backlight code in i915 over to
> DRM helpers: it would appear that we calculate the frequency value we want
> to write to DP_EDP_BACKLIGHT_FREQ_SET twice even though this value never
> actually changes during runtime. So, let's simplify things by just caching
> this value in intel_panel.backlight, and re-writing it as-needed.
This isn't a full review, just something I spotted so far. Please see
inline.
BR,
Jani.
>
> Signed-off-by: Lyude Paul
> Cc: Jani Nikula
> Cc: Dave Airlie
> Cc: greg.depo...@gmail.com
> ---
> .../drm/i915/display/intel_display_types.h| 1 +
> .../drm/i915/display/intel_dp_aux_backlight.c | 64 ++-
> 2 files changed, 19 insertions(+), 46 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h
> b/drivers/gpu/drm/i915/display/intel_display_types.h
> index 5bc5bfbc4551..133c9cb742a7 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_types.h
> +++ b/drivers/gpu/drm/i915/display/intel_display_types.h
> @@ -259,6 +259,7 @@ struct intel_panel {
>
> /* DPCD backlight */
> u8 pwmgen_bit_count;
> + u8 pwm_freq_pre_divider;
>
> struct backlight_device *device;
>
> diff --git a/drivers/gpu/drm/i915/display/intel_dp_aux_backlight.c
> b/drivers/gpu/drm/i915/display/intel_dp_aux_backlight.c
> index 4fd536801b14..94ce5ca1affa 100644
> --- a/drivers/gpu/drm/i915/display/intel_dp_aux_backlight.c
> +++ b/drivers/gpu/drm/i915/display/intel_dp_aux_backlight.c
> @@ -129,50 +129,6 @@ intel_dp_aux_set_backlight(const struct
> drm_connector_state *conn_state, u32 lev
> }
> }
>
> -/*
> - * Set PWM Frequency divider to match desired frequency in vbt.
> - * The PWM Frequency is calculated as 27Mhz / (F x P).
> - * - Where F = PWM Frequency Pre-Divider value programmed by field 7:0 of the
> - * EDP_BACKLIGHT_FREQ_SET register (DPCD Address 00728h)
> - * - Where P = 2^Pn, where Pn is the value programmed by field 4:0 of the
> - * EDP_PWMGEN_BIT_COUNT register (DPCD Address 00724h)
> - */
> -static bool intel_dp_aux_set_pwm_freq(struct intel_connector *connector)
> -{
> - struct drm_i915_private *dev_priv = to_i915(connector->base.dev);
> - struct intel_dp *intel_dp = intel_attached_dp(connector);
> - const u8 pn = connector->panel.backlight.pwmgen_bit_count;
> - int freq, fxp, f, fxp_actual, fxp_min, fxp_max;
> -
> - freq = dev_priv->vbt.backlight.pwm_freq_hz;
> - if (!freq) {
> - drm_dbg_kms(&dev_priv->drm,
> - "Use panel default backlight frequency\n");
> - return false;
> - }
> -
> - fxp = DIV_ROUND_CLOSEST(KHz(DP_EDP_BACKLIGHT_FREQ_BASE_KHZ), freq);
> - f = clamp(DIV_ROUND_CLOSEST(fxp, 1 << pn), 1, 255);
> - fxp_actual = f << pn;
> -
> - /* Ensure frequency is within 25% of desired value */
> - fxp_min = DIV_ROUND_CLOSEST(fxp * 3, 4);
> - fxp_max = DIV_ROUND_CLOSEST(fxp * 5, 4);
> -
> - if (fxp_min > fxp_actual || fxp_actual > fxp_max) {
> - drm_dbg_kms(&dev_priv->drm, "Actual frequency out of range\n");
> - return false;
> - }
> -
> - if (drm_dp_dpcd_writeb(&intel_dp->aux,
> -DP_EDP_BACKLIGHT_FREQ_SET, (u8) f) < 0) {
> - drm_dbg_kms(&dev_priv->drm,
> - "Failed to write aux backlight freq\n");
> - return false;
> - }
> - return true;
> -}
> -
> static void intel_dp_aux_enable_backlight(const struct intel_crtc_state
> *crtc_state,
> const struct drm_connector_state
> *conn_state)
> {
> @@ -213,9 +169,13 @@ static void intel_dp_aux_enable_backlight(const struct
> intel_crtc_state *crtc_st
> break;
> }
>
> - if (intel_dp->edp_dpcd[2] & DP_EDP_BACKLIGHT_FREQ_AUX_SET_CAP)
> - if (intel_dp_aux_set_pwm_freq(connector))
> + if (panel->backlight.pwm_freq_pre_divider) {
> + if (drm_dp_dpcd_writeb(&intel_dp->aux,
> DP_EDP_BACKLIGHT_FREQ_SET,
> +panel->backlight.pwm_freq_pre_divider)
> == 1)
> new_dpcd_buf |= DP_EDP_BACKLIGHT_FREQ_AUX_SET_ENABLE;
> + else
> + drm_dbg_kms(&i915->drm, "Failed to write aux backlight
> frequency\n");
> + }
>
> if (new_dpcd_buf != dpcd_buf) {
> if (drm_dp_dpcd_writeb(&intel_dp
Re: [Intel-gfx] [RFC 4/5] drm/dp: Extract i915's eDP backlight code into DRM helpers
On Wed, 09 Dec 2020, Lyude Paul wrote:
> Since we're about to implement eDP backlight support in nouveau using the
> standard protocol from VESA, we might as well just take the code that's
> already written for this and move it into a set of shared DRM helpers.
>
> Note that these helpers are intended to handle DPCD related backlight
> control bits such as setting the brightness level over AUX, probing the
> backlight's TCON, enabling/disabling the backlight over AUX if supported,
> etc. Any PWM-related portions of backlight control are explicitly left up
> to the driver, as these will vary from platform to platform.
>
> The only exception to this is the calculation of the PWM frequency
> pre-divider value. This is because the only platform-specific information
> required for this is the PWM frequency of the panel, which the driver is
> expected to provide if available. The actual algorithm for calculating this
> value is standard and is defined in the eDP specification from VESA.
>
> Note that these helpers do not yet implement the full range of features
> the VESA backlight interface provides, and only provide the following
> functionality (all of which was already present in i915's DPCD backlight
> support):
>
> * Basic control of brightness levels
> * Basic probing of backlight capabilities
> * Helpers for enabling and disabling the backlight
Overall I like where this is going. Again, not a full review yet, just a
few notes below.
>
> Signed-off-by: Lyude Paul
> Cc: Jani Nikula
> Cc: Dave Airlie
> Cc: greg.depo...@gmail.com
> ---
> drivers/gpu/drm/drm_dp_helper.c | 332 ++
> .../drm/i915/display/intel_display_types.h| 5 +-
> .../drm/i915/display/intel_dp_aux_backlight.c | 304 ++--
> include/drm/drm_dp_helper.h | 48 +++
> 4 files changed, 419 insertions(+), 270 deletions(-)
>
> diff --git a/drivers/gpu/drm/drm_dp_helper.c b/drivers/gpu/drm/drm_dp_helper.c
> index 5bd0934004e3..06fdddf44e54 100644
> --- a/drivers/gpu/drm/drm_dp_helper.c
> +++ b/drivers/gpu/drm/drm_dp_helper.c
> @@ -2596,3 +2596,335 @@ void drm_dp_vsc_sdp_log(const char *level, struct
> device *dev,
> #undef DP_SDP_LOG
> }
> EXPORT_SYMBOL(drm_dp_vsc_sdp_log);
> +
> +/**
> + * drm_edp_backlight_set_level() - Set the backlight level of an eDP panel
> via AUX
> + * @aux: The DP AUX channel to use
> + * @bl: Backlight capability info from drm_edp_backlight_init()
> + * @level: The brightness level to set
> + *
> + * Sets the brightness level of an eDP panel's backlight. Note that the
> panel's backlight must
> + * already have been enabled by the driver by calling
> drm_edp_backlight_enable().
> + *
> + * Returns: %0 on success, negative error code on failure
> + */
> +int drm_edp_backlight_set_level(struct drm_dp_aux *aux, const struct
> drm_edp_backlight_info *bl,
> + u16 level)
I think I'd go for s/backlight/brightness/g function naming thoughout,
to account for OLED. "Backlight" unnecessarily underlines the
technology.
> +{
> + int ret;
> + u8 buf[2] = { 0 };
> +
> + if (bl->lsb_reg_used) {
> + buf[0] = (level & 0xFF00) >> 8;
> + buf[1] = (level & 0x00FF);
> + } else {
> + buf[0] = level;
> + }
> +
> + ret = drm_dp_dpcd_write(aux, DP_EDP_BACKLIGHT_BRIGHTNESS_MSB, buf,
> sizeof(buf));
> + if (ret != sizeof(buf)) {
> + DRM_ERROR("%s: Failed to write aux backlight level: %d\n",
> aux->name, ret);
I'd really like to have a way to get from struct drm_dp_aux to struct
drm_device to retain the device specific logging here. It'd be useful in
the lower level dpcd access functions too.
> + return ret < 0 ? ret : -EIO;
> + }
> +
> + return 0;
> +}
> +EXPORT_SYMBOL(drm_edp_backlight_set_level);
> +
> +static int
> +drm_edp_backlight_set_enable(struct drm_dp_aux *aux, const struct
> drm_edp_backlight_info *bl,
> + bool enable)
> +{
> + int ret;
> + u8 buf;
> +
> + /* The panel uses something other then DPCD for enabling it's backlight
> */
> + if (!bl->aux_enable)
> + return 0;
> +
> + ret = drm_dp_dpcd_readb(aux, DP_EDP_DISPLAY_CONTROL_REGISTER, &buf);
> + if (ret != 1) {
> + DRM_ERROR("%s: Failed to read eDP display control register:
> %d\n", aux->name, ret);
> + return ret < 0 ? ret : -EIO;
> + }
> + if (enable)
> + buf |= DP_EDP_BACKLIGHT_ENABLE;
> + else
> + buf &= ~DP_ED
Re: [Intel-gfx] [PATCH v5 1/2] drm/i915/display: Support PSR Multiple Transcoders
On Fri, 11 Dec 2020, Gwan-gyeong Mun wrote:
> It is a preliminary work for supporting multiple EDP PSR and
> DP PanelReplay. And it refactors singleton PSR to Multi Transcoder
> supportable PSR.
> And this moves and renames the i915_psr structure of drm_i915_private's to
> intel_dp's intel_psr structure.
> It also causes changes in PSR interrupt handling routine for supporting
> multiple transcoders. But it does not change the scenario and timing of
> enabling and disabling PSR.
Can we plan to throw out the psr debugfs files not attached to a
connector, please? I.e. i915_edp_psr_debug and i915_edp_psr_status would
be removed from top level altogether, and only be available under
connector debugfs.
BR,
Jani.
>
> v2: Fix indentation and add comments
> v3: Remove Blank line
> v4: Rebased
> v5: Rebased and Addressed Anshuman's review comment.
> - Move calling of intel_psr_init() to intel_dp_init_connector()
>
> Signed-off-by: Gwan-gyeong Mun
> Cc: José Roberto de Souza
> Cc: Juha-Pekka Heikkila
> Cc: Anshuman Gupta
> ---
> drivers/gpu/drm/i915/display/intel_ddi.c | 3 +
> drivers/gpu/drm/i915/display/intel_display.c | 4 -
> .../drm/i915/display/intel_display_debugfs.c | 111 ++--
> .../drm/i915/display/intel_display_types.h| 38 ++
> drivers/gpu/drm/i915/display/intel_dp.c | 23 +-
> drivers/gpu/drm/i915/display/intel_psr.c | 585 ++
> drivers/gpu/drm/i915/display/intel_psr.h | 14 +-
> drivers/gpu/drm/i915/display/intel_sprite.c | 6 +-
> drivers/gpu/drm/i915/i915_drv.h | 38 --
> drivers/gpu/drm/i915/i915_irq.c | 49 +-
> 10 files changed, 491 insertions(+), 380 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c
> b/drivers/gpu/drm/i915/display/intel_ddi.c
> index 6863236df1d0..4b87f72cb9c0 100644
> --- a/drivers/gpu/drm/i915/display/intel_ddi.c
> +++ b/drivers/gpu/drm/i915/display/intel_ddi.c
> @@ -4320,7 +4320,10 @@ static void intel_ddi_update_pipe_dp(struct
> intel_atomic_state *state,
>
> intel_ddi_set_dp_msa(crtc_state, conn_state);
>
> + //TODO: move PSR related functions into intel_psr_update()
> + intel_psr2_program_trans_man_trk_ctl(intel_dp, crtc_state);
> intel_psr_update(intel_dp, crtc_state, conn_state);
> +
> intel_dp_set_infoframes(encoder, true, crtc_state, conn_state);
> intel_edp_drrs_update(intel_dp, crtc_state);
>
> diff --git a/drivers/gpu/drm/i915/display/intel_display.c
> b/drivers/gpu/drm/i915/display/intel_display.c
> index 761be8deaa9b..f26d9bcd722c 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.c
> +++ b/drivers/gpu/drm/i915/display/intel_display.c
> @@ -15869,8 +15869,6 @@ static void commit_pipe_config(struct
> intel_atomic_state *state,
>
> if (new_crtc_state->update_pipe)
> intel_pipe_fastset(old_crtc_state, new_crtc_state);
> -
> - intel_psr2_program_trans_man_trk_ctl(new_crtc_state);
> }
>
> if (dev_priv->display.atomic_update_watermarks)
> @@ -17830,8 +17828,6 @@ static void intel_setup_outputs(struct
> drm_i915_private *dev_priv)
> intel_dvo_init(dev_priv);
> }
>
> - intel_psr_init(dev_priv);
> -
> for_each_intel_encoder(&dev_priv->drm, encoder) {
> encoder->base.possible_crtcs =
> intel_encoder_possible_crtcs(encoder);
> diff --git a/drivers/gpu/drm/i915/display/intel_display_debugfs.c
> b/drivers/gpu/drm/i915/display/intel_display_debugfs.c
> index cd7e5519ee7d..041053167d7f 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_debugfs.c
> +++ b/drivers/gpu/drm/i915/display/intel_display_debugfs.c
> @@ -249,18 +249,17 @@ static int i915_psr_sink_status_show(struct seq_file
> *m, void *data)
> "sink internal error",
> };
> struct drm_connector *connector = m->private;
> - struct drm_i915_private *dev_priv = to_i915(connector->dev);
> struct intel_dp *intel_dp =
> intel_attached_dp(to_intel_connector(connector));
> int ret;
>
> - if (!CAN_PSR(dev_priv)) {
> - seq_puts(m, "PSR Unsupported\n");
> + if (connector->status != connector_status_connected)
> return -ENODEV;
> - }
>
> - if (connector->status != connector_status_connected)
> + if (!CAN_PSR(intel_dp)) {
> + seq_puts(m, "PSR Unsupported\n");
> return -ENODEV;
> + }
>
> ret = drm_dp_dpcd_readb(&intel_dp->aux, DP_PSR_STATUS, &val);
>
> @@ -280,12 +279,13 @@ static int i915_psr_sink_status_show(struct seq_file
> *m, void *data)
> DEFINE_SHOW_ATTRIBUTE(i915_psr_sink_status);
>
> static void
> -psr_source_status(struct drm_i915_private *dev_priv, struct seq_file *m)
> +psr_source_status(struct intel_dp *intel_dp, struct seq_file *m)
> {
> u32 val, status_val;
> const char *status = "unknown";
> + struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
Re: [Intel-gfx] [PATCH v5 2/2] drm/i915/display: Support Multiple Transcoders' PSR status on debugfs
On Mon, 14 Dec 2020, Anshuman Gupta wrote:
> On 2020-12-11 at 19:14:21 +0200, Gwan-gyeong Mun wrote:
>> In order to support the PSR state of each transcoder, it adds
>> i915_psr_status to sub-directory of each transcoder.
>>
>> v2: Change using of Symbolic permissions 'S_IRUGO' to using of octal
>> permissions '0444'
>> v5: Addressed JJani Nikula's review comments
>> - Remove checking of Gen12 for i915_psr_status.
>> - Add check of HAS_PSR()
>> - Remove meaningless check routine.
>>
>> Signed-off-by: Gwan-gyeong Mun
>> Cc: José Roberto de Souza
>> Cc: Jani Nikula
>> Cc: Anshuman Gupta
>> ---
>> .../gpu/drm/i915/display/intel_display_debugfs.c | 16
>> 1 file changed, 16 insertions(+)
>>
>> diff --git a/drivers/gpu/drm/i915/display/intel_display_debugfs.c
>> b/drivers/gpu/drm/i915/display/intel_display_debugfs.c
>> index 041053167d7f..d2dd61c4ee0b 100644
>> --- a/drivers/gpu/drm/i915/display/intel_display_debugfs.c
>> +++ b/drivers/gpu/drm/i915/display/intel_display_debugfs.c
>> @@ -2224,6 +2224,16 @@ static int i915_hdcp_sink_capability_show(struct
>> seq_file *m, void *data)
>> }
>> DEFINE_SHOW_ATTRIBUTE(i915_hdcp_sink_capability);
>>
>> +static int i915_psr_status_show(struct seq_file *m, void *data)
>> +{
>> +struct drm_connector *connector = m->private;
>> +struct intel_dp *intel_dp =
>> +intel_attached_dp(to_intel_connector(connector));
>> +
>> +return intel_psr_status(m, intel_dp);
>> +}
>> +DEFINE_SHOW_ATTRIBUTE(i915_psr_status);
>> +
>> #define LPSP_CAPABLE(COND) (COND ? seq_puts(m, "LPSP: capable\n") : \
>> seq_puts(m, "LPSP: incapable\n"))
>>
>> @@ -2399,6 +2409,12 @@ int intel_connector_debugfs_add(struct drm_connector
>> *connector)
>> connector, &i915_psr_sink_status_fops);
>> }
>>
>> +if (HAS_PSR(dev_priv) &&
>> +connector->connector_type == DRM_MODE_CONNECTOR_eDP) {
>> +debugfs_create_file("i915_psr_status", 0444, root,
> Could we keep the file name as i915_edp_psr_status, as we have today?
> with that addressed.
Depends on whether the plan is to use the same file for regular DP panel
replay in the future. Then edp would be misleading.
BR,
Jani.
> Reviewed-by: Anshuman Gupta
>> +connector, &i915_psr_status_fops);
>> +}
>> +
>> if (connector->connector_type == DRM_MODE_CONNECTOR_DisplayPort ||
>> connector->connector_type == DRM_MODE_CONNECTOR_HDMIA ||
>> connector->connector_type == DRM_MODE_CONNECTOR_HDMIB) {
>> --
>> 2.25.0
>>
--
Jani Nikula, Intel Open Source Graphics Center
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH 05/11] drm/i915: refactor some crtc code out of intel display.
On Fri, 11 Dec 2020, Dave Airlie wrote:
> From: Dave Airlie
>
> There may be more crtc code that can be pulled out, but this
> is a good start.
>
> RFC: maybe call the new file something different
I checked this is just code movement. I did clean up intel_crtc.h
locally a bit though. (I'll probably re-send the series with a few fixes
to pass CI.)
I'm not averse to renaming the file later if needed, I'm more concerned
about choosing a meaningful bunch of functions to take out and put in
the new file.
Ville, I saw you had some comments about this - is this making sensible
progress or making further refactoring harder?
I'm honestly beginning to think we've had too many stalled attempts at
cleaning up the file (including at least three patch series from yours
truly) that I'm ready to just chop up the file, and clean it up more
later as needed.
BR,
Jani.
>
> Signed-off-by: Dave Airlie
> ---
> drivers/gpu/drm/i915/Makefile| 1 +
> drivers/gpu/drm/i915/display/intel_crtc.c| 953 +++
> drivers/gpu/drm/i915/display/intel_crtc.h| 20 +
> drivers/gpu/drm/i915/display/intel_display.c | 934 +-
> 4 files changed, 975 insertions(+), 933 deletions(-)
> create mode 100644 drivers/gpu/drm/i915/display/intel_crtc.c
> create mode 100644 drivers/gpu/drm/i915/display/intel_crtc.h
>
> diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makefile
> index 98a35b939052..ffec257702af 100644
> --- a/drivers/gpu/drm/i915/Makefile
> +++ b/drivers/gpu/drm/i915/Makefile
> @@ -196,6 +196,7 @@ i915-y += \
> display/intel_color.o \
> display/intel_combo_phy.o \
> display/intel_connector.o \
> + display/intel_crtc.o \
> display/intel_csr.o \
> display/intel_cursor.o \
> display/intel_display.o \
> diff --git a/drivers/gpu/drm/i915/display/intel_crtc.c
> b/drivers/gpu/drm/i915/display/intel_crtc.c
> new file mode 100644
> index ..d26beb8ad9ed
> --- /dev/null
> +++ b/drivers/gpu/drm/i915/display/intel_crtc.c
> @@ -0,0 +1,953 @@
> +// SPDX-License-Identifier: MIT
> +/*
> + * Copyright © 2020 Intel Corporation
> + */
> +#include
> +#include
> +
> +#include
> +#include
> +#include
> +#include
> +
> +#include "intel_atomic.h"
> +#include "intel_atomic_plane.h"
> +#include "intel_color.h"
> +#include "intel_crtc.h"
> +#include "intel_cursor.h"
> +#include "intel_display_debugfs.h"
> +#include "intel_display_types.h"
> +#include "intel_pipe_crc.h"
> +#include "intel_sprite.h"
> +
> +/* Primary plane formats for gen <= 3 */
> +static const u32 i8xx_primary_formats[] = {
> + DRM_FORMAT_C8,
> + DRM_FORMAT_XRGB1555,
> + DRM_FORMAT_RGB565,
> + DRM_FORMAT_XRGB,
> +};
> +
> +/* Primary plane formats for ivb (no fp16 due to hw issue) */
> +static const u32 ivb_primary_formats[] = {
> + DRM_FORMAT_C8,
> + DRM_FORMAT_RGB565,
> + DRM_FORMAT_XRGB,
> + DRM_FORMAT_XBGR,
> + DRM_FORMAT_XRGB2101010,
> + DRM_FORMAT_XBGR2101010,
> +};
> +
> +/* Primary plane formats for gen >= 4, except ivb */
> +static const u32 i965_primary_formats[] = {
> + DRM_FORMAT_C8,
> + DRM_FORMAT_RGB565,
> + DRM_FORMAT_XRGB,
> + DRM_FORMAT_XBGR,
> + DRM_FORMAT_XRGB2101010,
> + DRM_FORMAT_XBGR2101010,
> + DRM_FORMAT_XBGR16161616F,
> +};
> +
> +/* Primary plane formats for vlv/chv */
> +static const u32 vlv_primary_formats[] = {
> + DRM_FORMAT_C8,
> + DRM_FORMAT_RGB565,
> + DRM_FORMAT_XRGB,
> + DRM_FORMAT_XBGR,
> + DRM_FORMAT_ARGB,
> + DRM_FORMAT_ABGR,
> + DRM_FORMAT_XRGB2101010,
> + DRM_FORMAT_XBGR2101010,
> + DRM_FORMAT_ARGB2101010,
> + DRM_FORMAT_ABGR2101010,
> + DRM_FORMAT_XBGR16161616F,
> +};
> +
> +static const u64 i9xx_format_modifiers[] = {
> + I915_FORMAT_MOD_X_TILED,
> + DRM_FORMAT_MOD_LINEAR,
> + DRM_FORMAT_MOD_INVALID
> +};
> +
> +static bool i8xx_plane_format_mod_supported(struct drm_plane *_plane,
> + u32 format, u64 modifier)
> +{
> + switch (modifier) {
> + case DRM_FORMAT_MOD_LINEAR:
> + case I915_FORMAT_MOD_X_TILED:
> + break;
> + default:
> + return false;
> + }
> +
> + switch (format) {
> + case DRM_FORMAT_C8:
> + case DRM_FORMAT_RGB565:
> + case DRM_FORMAT_XRGB1555:
> + case DRM_FORMAT_XRGB:
> + return modifier == DRM_FORMAT_MOD_LINEAR ||
> + modifier == I915_FORMAT_MOD_X_TILED;
> + default:
> + return false;
> + }
> +}
> +
> +static bool i965_plane_format_mod_supported(struct drm_plane *_plane,
> + u32 format, u64 modifier)
> +{
> + switch (modifier) {
> + case DRM_FORMAT_MOD_LINEAR:
> + case I915_FORMAT_MOD_X_TILED:
> + break;
> + default:
> + return false;
> + }
> +
> + switch (format) {
> + case DRM_FORMAT_C8:
> + cas
Re: [Intel-gfx] [PATCH 04/11] drm/i915: refactor cursor code out of i915_display.c
On Fri, 11 Dec 2020, Dave Airlie wrote:
> From: Dave Airlie
>
> This file is a monster, let's start simple, the cursor plane code
> seems pretty standalone, and splits out easily enough.
I cleaned up intel_cursor.h a bit locally, but the code movement checks
out.
BR,
Jani.
>
> Reviewed-by: Ville Syrjälä
> Signed-off-by: Dave Airlie
> ---
> drivers/gpu/drm/i915/Makefile| 1 +
> drivers/gpu/drm/i915/display/intel_cursor.c | 806 +++
> drivers/gpu/drm/i915/display/intel_cursor.h | 18 +
> drivers/gpu/drm/i915/display/intel_display.c | 797 +-
> drivers/gpu/drm/i915/display/intel_display.h | 7 +
> 5 files changed, 839 insertions(+), 790 deletions(-)
> create mode 100644 drivers/gpu/drm/i915/display/intel_cursor.c
> create mode 100644 drivers/gpu/drm/i915/display/intel_cursor.h
>
> diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makefile
> index e5574e506a5c..98a35b939052 100644
> --- a/drivers/gpu/drm/i915/Makefile
> +++ b/drivers/gpu/drm/i915/Makefile
> @@ -197,6 +197,7 @@ i915-y += \
> display/intel_combo_phy.o \
> display/intel_connector.o \
> display/intel_csr.o \
> + display/intel_cursor.o \
> display/intel_display.o \
> display/intel_display_power.o \
> display/intel_dpio_phy.o \
> diff --git a/drivers/gpu/drm/i915/display/intel_cursor.c
> b/drivers/gpu/drm/i915/display/intel_cursor.c
> new file mode 100644
> index ..276d2bb0e2cf
> --- /dev/null
> +++ b/drivers/gpu/drm/i915/display/intel_cursor.c
> @@ -0,0 +1,806 @@
> +// SPDX-License-Identifier: MIT
> +/*
> + * Copyright © 2020 Intel Corporation
> + */
> +#include
> +
> +#include
> +#include
> +#include
> +#include
> +#include
> +
> +#include "intel_atomic.h"
> +#include "intel_atomic_plane.h"
> +#include "intel_cursor.h"
> +#include "intel_display_types.h"
> +#include "intel_display.h"
> +
> +#include "intel_frontbuffer.h"
> +#include "intel_pm.h"
> +#include "intel_psr.h"
> +#include "intel_sprite.h"
> +
> +/* Cursor formats */
> +static const u32 intel_cursor_formats[] = {
> + DRM_FORMAT_ARGB,
> +};
> +
> +static const u64 cursor_format_modifiers[] = {
> + DRM_FORMAT_MOD_LINEAR,
> + DRM_FORMAT_MOD_INVALID
> +};
> +
> +static u32 intel_cursor_base(const struct intel_plane_state *plane_state)
> +{
> + struct drm_i915_private *dev_priv =
> + to_i915(plane_state->uapi.plane->dev);
> + const struct drm_framebuffer *fb = plane_state->hw.fb;
> + const struct drm_i915_gem_object *obj = intel_fb_obj(fb);
> + u32 base;
> +
> + if (INTEL_INFO(dev_priv)->display.cursor_needs_physical)
> + base = sg_dma_address(obj->mm.pages->sgl);
> + else
> + base = intel_plane_ggtt_offset(plane_state);
> +
> + return base + plane_state->color_plane[0].offset;
> +}
> +
> +static u32 intel_cursor_position(const struct intel_plane_state *plane_state)
> +{
> + int x = plane_state->uapi.dst.x1;
> + int y = plane_state->uapi.dst.y1;
> + u32 pos = 0;
> +
> + if (x < 0) {
> + pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT;
> + x = -x;
> + }
> + pos |= x << CURSOR_X_SHIFT;
> +
> + if (y < 0) {
> + pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT;
> + y = -y;
> + }
> + pos |= y << CURSOR_Y_SHIFT;
> +
> + return pos;
> +}
> +
> +static bool intel_cursor_size_ok(const struct intel_plane_state *plane_state)
> +{
> + const struct drm_mode_config *config =
> + &plane_state->uapi.plane->dev->mode_config;
> + int width = drm_rect_width(&plane_state->uapi.dst);
> + int height = drm_rect_height(&plane_state->uapi.dst);
> +
> + return width > 0 && width <= config->cursor_width &&
> + height > 0 && height <= config->cursor_height;
> +}
> +
> +static int intel_cursor_check_surface(struct intel_plane_state *plane_state)
> +{
> + struct drm_i915_private *dev_priv =
> + to_i915(plane_state->uapi.plane->dev);
> + unsigned int rotation = plane_state->hw.rotation;
> + int src_x, src_y;
> + u32 offset;
> + int ret;
> +
> + ret = intel_plane_compute_gtt(plane_state);
> + if (ret)
> + return ret;
> +
> + if (!plane_state->uapi.visible)
> + return 0;
> +
> + src_x = plane_state->uapi.src.x1 >> 16;
> + src_y = plane_state->uapi.src.y1 >> 16;
> +
> + intel_add_fb_offsets(&src_x, &src_y, plane_state, 0);
> + offset = intel_plane_compute_aligned_offset(&src_x, &src_y,
> + plane_state, 0);
> +
> + if (src_x != 0 || src_y != 0) {
> + drm_dbg_kms(&dev_priv->drm,
> + "Arbitrary cursor panning not supported\n");
> + return -EINVAL;
> + }
> +
> + /*
> + * Put the final coordinates back so that the src
> + * coordinate checks will see the right values.
> + */
> + drm_rect_translate
Re: [Intel-gfx] [PATCH 06/11] drm/i915: refactor pll code out into intel_dpll.c
On Fri, 11 Dec 2020, Dave Airlie wrote:
> From: Dave Airlie
>
> This pulls a large chunk of the pll calculation code out of
> intel_display.c to a new file.
>
> One function makse sense to be an inline, otherwise this
> is pretty much a straight copy cover. also all the
> remaining hooks for g45 and older end up the same now.
This duplicates intel_panel_use_ssc, otherwise LGTM. Fixed up locally,
along with the intel_dpll.h fix to pass CI.
BR,
Jani.
>
> Signed-off-by: Dave Airlie
> ---
> drivers/gpu/drm/i915/Makefile |1 +
> drivers/gpu/drm/i915/display/intel_display.c | 1394 +
> drivers/gpu/drm/i915/display/intel_display.h |3 +
> .../drm/i915/display/intel_display_types.h|5 +
> drivers/gpu/drm/i915/display/intel_dpll.c | 1371
> drivers/gpu/drm/i915/display/intel_dpll.h | 22 +
> 6 files changed, 1413 insertions(+), 1383 deletions(-)
> create mode 100644 drivers/gpu/drm/i915/display/intel_dpll.c
> create mode 100644 drivers/gpu/drm/i915/display/intel_dpll.h
>
> diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makefile
> index ffec257702af..5d533de16335 100644
> --- a/drivers/gpu/drm/i915/Makefile
> +++ b/drivers/gpu/drm/i915/Makefile
> @@ -202,6 +202,7 @@ i915-y += \
> display/intel_display.o \
> display/intel_display_power.o \
> display/intel_dpio_phy.o \
> + display/intel_dpll.o \
> display/intel_dpll_mgr.o \
> display/intel_dsb.o \
> display/intel_fbc.o \
> diff --git a/drivers/gpu/drm/i915/display/intel_display.c
> b/drivers/gpu/drm/i915/display/intel_display.c
> index 5dfec950c144..a0d9cd7b4e34 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.c
> +++ b/drivers/gpu/drm/i915/display/intel_display.c
> @@ -48,6 +48,7 @@
> #include "display/intel_display_debugfs.h"
> #include "display/intel_dp.h"
> #include "display/intel_dp_mst.h"
> +#include "display/intel_dpll.h"
> #include "display/intel_dpll_mgr.h"
> #include "display/intel_dsi.h"
> #include "display/intel_dvo.h"
> @@ -114,17 +115,6 @@ static void ilk_pfit_enable(const struct
> intel_crtc_state *crtc_state);
> static void intel_modeset_setup_hw_state(struct drm_device *dev,
>struct drm_modeset_acquire_ctx *ctx);
>
> -struct intel_limit {
> - struct {
> - int min, max;
> - } dot, vco, n, m, m1, m2, p, p1;
> -
> - struct {
> - int dot_limit;
> - int p2_slow, p2_fast;
> - } p2;
> -};
> -
> /* returns HPLL frequency in kHz */
> int vlv_get_hpll_vco(struct drm_i915_private *dev_priv)
> {
> @@ -192,271 +182,6 @@ static u32 intel_fdi_link_freq(struct drm_i915_private
> *dev_priv,
> return dev_priv->fdi_pll_freq;
> }
>
> -static const struct intel_limit intel_limits_i8xx_dac = {
> - .dot = { .min = 25000, .max = 35 },
> - .vco = { .min = 908000, .max = 1512000 },
> - .n = { .min = 2, .max = 16 },
> - .m = { .min = 96, .max = 140 },
> - .m1 = { .min = 18, .max = 26 },
> - .m2 = { .min = 6, .max = 16 },
> - .p = { .min = 4, .max = 128 },
> - .p1 = { .min = 2, .max = 33 },
> - .p2 = { .dot_limit = 165000,
> - .p2_slow = 4, .p2_fast = 2 },
> -};
> -
> -static const struct intel_limit intel_limits_i8xx_dvo = {
> - .dot = { .min = 25000, .max = 35 },
> - .vco = { .min = 908000, .max = 1512000 },
> - .n = { .min = 2, .max = 16 },
> - .m = { .min = 96, .max = 140 },
> - .m1 = { .min = 18, .max = 26 },
> - .m2 = { .min = 6, .max = 16 },
> - .p = { .min = 4, .max = 128 },
> - .p1 = { .min = 2, .max = 33 },
> - .p2 = { .dot_limit = 165000,
> - .p2_slow = 4, .p2_fast = 4 },
> -};
> -
> -static const struct intel_limit intel_limits_i8xx_lvds = {
> - .dot = { .min = 25000, .max = 35 },
> - .vco = { .min = 908000, .max = 1512000 },
> - .n = { .min = 2, .max = 16 },
> - .m = { .min = 96, .max = 140 },
> - .m1 = { .min = 18, .max = 26 },
> - .m2 = { .min = 6, .max = 16 },
> - .p = { .min = 4, .max = 128 },
> - .p1 = { .min = 1, .max = 6 },
> - .p2 = { .dot_limit = 165000,
> - .p2_slow = 14, .p2_fast = 7 },
> -};
> -
> -static const struct intel_limit intel_limits_i9xx_sdvo = {
> - .dot = { .min = 2, .max = 40 },
> - .vco = { .min = 140, .max = 280 },
> - .n = { .min = 1, .max = 6 },
> - .m = { .min = 70, .max = 120 },
> - .m1 = { .min = 8, .max = 18 },
> - .m2 = { .min = 3, .max = 7 },
> - .p = { .min = 5, .max = 80 },
> - .p1 = { .min = 1, .max = 8 },
> - .p2 = { .dot_limit = 20,
> - .p2_slow = 10, .p2_fast = 5 },
> -};
> -
> -static const struct intel_limit intel_limits_i9xx_lvds = {
> - .dot = { .min = 2, .max = 40 },
> - .vco = { .min = 140, .max = 280 },
> - .n = { .min = 1, .max = 6 },
> - .m = { .min = 70, .max = 120 },
> - .m1 = { .min =
Re: [Intel-gfx] [PATCH 07/11] drm/i915: split fdi code out from intel_display.c
On Fri, 11 Dec 2020, Dave Airlie wrote:
> From: Dave Airlie
>
> This just refactors out the fdi code to a separate file.
LGTM, save for another header fix that I made locally. ;)
See CONFIG_DRM_I915_WERROR=y for what we do in CI to keep stuff clean.
BR,
Jani.
>
> Signed-off-by: Dave Airlie
> ---
> drivers/gpu/drm/i915/Makefile | 1 +
> drivers/gpu/drm/i915/display/intel_display.c | 685 +-
> .../drm/i915/display/intel_display_types.h| 9 +
> drivers/gpu/drm/i915/display/intel_fdi.c | 683 +
> drivers/gpu/drm/i915/display/intel_fdi.h | 21 +
> 5 files changed, 717 insertions(+), 682 deletions(-)
> create mode 100644 drivers/gpu/drm/i915/display/intel_fdi.c
> create mode 100644 drivers/gpu/drm/i915/display/intel_fdi.h
>
> diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makefile
> index 5d533de16335..c46c19a4e830 100644
> --- a/drivers/gpu/drm/i915/Makefile
> +++ b/drivers/gpu/drm/i915/Makefile
> @@ -206,6 +206,7 @@ i915-y += \
> display/intel_dpll_mgr.o \
> display/intel_dsb.o \
> display/intel_fbc.o \
> + display/intel_fdi.o \
> display/intel_fifo_underrun.o \
> display/intel_frontbuffer.o \
> display/intel_global_state.o \
> diff --git a/drivers/gpu/drm/i915/display/intel_display.c
> b/drivers/gpu/drm/i915/display/intel_display.c
> index a0d9cd7b4e34..b582114a9d63 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.c
> +++ b/drivers/gpu/drm/i915/display/intel_display.c
> @@ -74,6 +74,7 @@
> #include "intel_display_types.h"
> #include "intel_dp_link_training.h"
> #include "intel_fbc.h"
> +#include "intel_fdi.h"
> #include "intel_fbdev.h"
> #include "intel_fifo_underrun.h"
> #include "intel_frontbuffer.h"
> @@ -172,16 +173,6 @@ static void intel_update_czclk(struct drm_i915_private
> *dev_priv)
> dev_priv->czclk_freq);
> }
>
> -/* units of 100MHz */
> -static u32 intel_fdi_link_freq(struct drm_i915_private *dev_priv,
> -const struct intel_crtc_state *pipe_config)
> -{
> - if (HAS_DDI(dev_priv))
> - return pipe_config->port_clock; /* SPLL */
> - else
> - return dev_priv->fdi_pll_freq;
> -}
> -
> /* WA Display #0827: Gen9:all */
> static void
> skl_wa_827(struct drm_i915_private *dev_priv, enum pipe pipe, bool enable)
> @@ -3766,532 +3757,6 @@ static void icl_set_pipe_chicken(struct intel_crtc
> *crtc)
> intel_de_write(dev_priv, PIPE_CHICKEN(pipe), tmp);
> }
>
> -static void intel_fdi_normal_train(struct intel_crtc *crtc)
> -{
> - struct drm_device *dev = crtc->base.dev;
> - struct drm_i915_private *dev_priv = to_i915(dev);
> - enum pipe pipe = crtc->pipe;
> - i915_reg_t reg;
> - u32 temp;
> -
> - /* enable normal train */
> - reg = FDI_TX_CTL(pipe);
> - temp = intel_de_read(dev_priv, reg);
> - if (IS_IVYBRIDGE(dev_priv)) {
> - temp &= ~FDI_LINK_TRAIN_NONE_IVB;
> - temp |= FDI_LINK_TRAIN_NONE_IVB | FDI_TX_ENHANCE_FRAME_ENABLE;
> - } else {
> - temp &= ~FDI_LINK_TRAIN_NONE;
> - temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE;
> - }
> - intel_de_write(dev_priv, reg, temp);
> -
> - reg = FDI_RX_CTL(pipe);
> - temp = intel_de_read(dev_priv, reg);
> - if (HAS_PCH_CPT(dev_priv)) {
> - temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
> - temp |= FDI_LINK_TRAIN_NORMAL_CPT;
> - } else {
> - temp &= ~FDI_LINK_TRAIN_NONE;
> - temp |= FDI_LINK_TRAIN_NONE;
> - }
> - intel_de_write(dev_priv, reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE);
> -
> - /* wait one idle pattern time */
> - intel_de_posting_read(dev_priv, reg);
> - udelay(1000);
> -
> - /* IVB wants error correction enabled */
> - if (IS_IVYBRIDGE(dev_priv))
> - intel_de_write(dev_priv, reg,
> -intel_de_read(dev_priv, reg) |
> FDI_FS_ERRC_ENABLE | FDI_FE_ERRC_ENABLE);
> -}
> -
> -/* The FDI link training functions for ILK/Ibexpeak. */
> -static void ilk_fdi_link_train(struct intel_crtc *crtc,
> -const struct intel_crtc_state *crtc_state)
> -{
> - struct drm_device *dev = crtc->base.dev;
> - struct drm_i915_private *dev_priv = to_i915(dev);
> - enum pipe pipe = crtc->pipe;
> - i915_reg_t reg;
> - u32 temp, tries;
> -
> - /* FDI needs bits from pipe first */
> - assert_pipe_enabled(dev_priv, crtc_state->cpu_transcoder);
> -
> - /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
> -for train result */
> - reg = FDI_RX_IMR(pipe);
> - temp = intel_de_read(dev_priv, reg);
> - temp &= ~FDI_RX_SYMBOL_LOCK;
> - temp &= ~FDI_RX_BIT_LOCK;
> - intel_de_write(dev_priv, reg, temp);
> - intel_de_read(dev_priv, reg);
> - udelay(150);
> -
> - /* enable CPU FDI TX and PCH FDI RX */
> - reg = FDI_TX_CTL(pipe);
>
Re: [Intel-gfx] [PATCH 08/11] drm/i915: migrate hsw fdi code to new file.
ing_read(dev_priv, DDI_BUF_CTL(PORT_E));
> +
> + /* Disable DP_TP_CTL and FDI_RX_CTL and retry */
> + temp = intel_de_read(dev_priv, DP_TP_CTL(PORT_E));
> + temp &= ~(DP_TP_CTL_ENABLE | DP_TP_CTL_LINK_TRAIN_MASK);
> + temp |= DP_TP_CTL_LINK_TRAIN_PAT1;
> + intel_de_write(dev_priv, DP_TP_CTL(PORT_E), temp);
> + intel_de_posting_read(dev_priv, DP_TP_CTL(PORT_E));
> +
> + intel_wait_ddi_buf_idle(dev_priv, PORT_E);
> +
> + /* Reset FDI_RX_MISC pwrdn lanes */
> + temp = intel_de_read(dev_priv, FDI_RX_MISC(PIPE_A));
> + temp &= ~(FDI_RX_PWRDN_LANE1_MASK | FDI_RX_PWRDN_LANE0_MASK);
> + temp |= FDI_RX_PWRDN_LANE1_VAL(2) | FDI_RX_PWRDN_LANE0_VAL(2);
> + intel_de_write(dev_priv, FDI_RX_MISC(PIPE_A), temp);
> + intel_de_posting_read(dev_priv, FDI_RX_MISC(PIPE_A));
> + }
> +
> + /* Enable normal pixel sending for FDI */
> + intel_de_write(dev_priv, DP_TP_CTL(PORT_E),
> +DP_TP_CTL_FDI_AUTOTRAIN |
> +DP_TP_CTL_LINK_TRAIN_NORMAL |
> +DP_TP_CTL_ENHANCED_FRAME_ENABLE |
> +DP_TP_CTL_ENABLE);
> +}
> +
> void ilk_fdi_pll_enable(const struct intel_crtc_state *crtc_state)
> {
> struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->uapi.crtc);
> diff --git a/drivers/gpu/drm/i915/display/intel_fdi.h
> b/drivers/gpu/drm/i915/display/intel_fdi.h
> index 7441fb1ce370..3b8bab236bd7 100644
> --- a/drivers/gpu/drm/i915/display/intel_fdi.h
> +++ b/drivers/gpu/drm/i915/display/intel_fdi.h
> @@ -8,6 +8,7 @@
>
> struct intel_crtc;
> struct intel_crtc_state;
> +struct intel_encoder;
>
> #define I915_DISPLAY_CONFIG_RETRY 1
> int ilk_fdi_compute_config(struct intel_crtc *intel_crtc,
> @@ -17,5 +18,7 @@ void ilk_fdi_disable(struct intel_crtc *crtc);
> void ilk_fdi_pll_disable(struct intel_crtc *intel_crtc);
> void ilk_fdi_pll_enable(const struct intel_crtc_state *crtc_state);
> void intel_fdi_init_hook(struct drm_i915_private *dev_priv);
> +void hsw_fdi_link_train(struct intel_encoder *encoder,
> + const struct intel_crtc_state *crtc_state);
>
> #endif
--
Jani Nikula, Intel Open Source Graphics Center
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH v4 00/11] drm/i915: refactor intel display
This is Dave's intel_display.c refactoring series [1] with some minor issues addressed, to get CI results among other things. I've reviewed and fixed any remaining minor issues I spotted in patches 1-8. I'm aware there may be things to improve, but I think this is overall forward progress and cleanup that's long overdue. I'm prepared to merge patches 1-8 unless there are strong objections. I ran out of steam a little with patches 9-11, and haven't reviewed them. They're included here just for completeness. BR, Jani. [1] https://patchwork.freedesktop.org/series/84812/ Dave Airlie (11): drm/i915/display: move needs_modeset to an inline in header drm/i915/display: move to_intel_frontbuffer to header drm/i915/display: fix misused comma drm/i915: refactor cursor code out of i915_display.c drm/i915: refactor some crtc code out of intel display. drm/i915: refactor pll code out into intel_dpll.c drm/i915: split fdi code out from intel_display.c drm/i915: migrate hsw fdi code to new file. drm/i915: migrate skl planes code new file drm/i915: move pipe update code into crtc. drm/i915: split fb scalable checks into g4x and skl versions drivers/gpu/drm/i915/Makefile | 5 + .../gpu/drm/i915/display/intel_atomic_plane.c |76 - drivers/gpu/drm/i915/display/intel_crt.c | 1 + drivers/gpu/drm/i915/display/intel_crtc.c | 1187 + drivers/gpu/drm/i915/display/intel_crtc.h |22 + drivers/gpu/drm/i915/display/intel_cursor.c | 806 + drivers/gpu/drm/i915/display/intel_cursor.h |17 + drivers/gpu/drm/i915/display/intel_ddi.c | 197 +- drivers/gpu/drm/i915/display/intel_ddi.h |14 +- drivers/gpu/drm/i915/display/intel_display.c | 20019 ++-- drivers/gpu/drm/i915/display/intel_display.h |46 +- .../drm/i915/display/intel_display_types.h|55 + drivers/gpu/drm/i915/display/intel_dpll.c | 1363 ++ drivers/gpu/drm/i915/display/intel_dpll.h |23 + drivers/gpu/drm/i915/display/intel_fdi.c | 857 + drivers/gpu/drm/i915/display/intel_fdi.h |29 + .../gpu/drm/i915/display/intel_gen9_plane.c | 2832 +++ drivers/gpu/drm/i915/display/intel_sprite.c | 1712 +- 18 files changed, 14739 insertions(+), 14522 deletions(-) create mode 100644 drivers/gpu/drm/i915/display/intel_crtc.c create mode 100644 drivers/gpu/drm/i915/display/intel_crtc.h create mode 100644 drivers/gpu/drm/i915/display/intel_cursor.c create mode 100644 drivers/gpu/drm/i915/display/intel_cursor.h create mode 100644 drivers/gpu/drm/i915/display/intel_dpll.c create mode 100644 drivers/gpu/drm/i915/display/intel_dpll.h create mode 100644 drivers/gpu/drm/i915/display/intel_fdi.c create mode 100644 drivers/gpu/drm/i915/display/intel_fdi.h create mode 100644 drivers/gpu/drm/i915/display/intel_gen9_plane.c -- 2.20.1 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH v4 01/11] drm/i915/display: move needs_modeset to an inline in header
From: Dave Airlie
This function is going to be used in a later change, so clean it
up first before moving it.
Reviewed-by: Ville Syrjälä
Signed-off-by: Dave Airlie
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/i915/display/intel_display.c | 78 +--
.../drm/i915/display/intel_display_types.h| 6 ++
2 files changed, 42 insertions(+), 42 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display.c
b/drivers/gpu/drm/i915/display/intel_display.c
index 761be8deaa9b..2d96b0563548 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -542,12 +542,6 @@ icl_wa_scalerclkgating(struct drm_i915_private *dev_priv,
enum pipe pipe,
intel_de_read(dev_priv, CLKGATE_DIS_PSL(pipe)) &
~DPFR_GATING_DIS);
}
-static bool
-needs_modeset(const struct intel_crtc_state *state)
-{
- return drm_atomic_crtc_needs_modeset(&state->uapi);
-}
-
static bool
is_trans_port_sync_slave(const struct intel_crtc_state *crtc_state)
{
@@ -6474,7 +6468,7 @@ static bool hsw_pre_update_disable_ips(const struct
intel_crtc_state *old_crtc_s
if (!old_crtc_state->ips_enabled)
return false;
- if (needs_modeset(new_crtc_state))
+ if (intel_crtc_needs_modeset(new_crtc_state))
return true;
/*
@@ -6501,7 +6495,7 @@ static bool hsw_post_update_enable_ips(const struct
intel_crtc_state *old_crtc_s
if (!new_crtc_state->ips_enabled)
return false;
- if (needs_modeset(new_crtc_state))
+ if (intel_crtc_needs_modeset(new_crtc_state))
return true;
/*
@@ -6554,7 +6548,7 @@ static bool needs_scalerclk_wa(const struct
intel_crtc_state *crtc_state)
static bool planes_enabling(const struct intel_crtc_state *old_crtc_state,
const struct intel_crtc_state *new_crtc_state)
{
- return (!old_crtc_state->active_planes ||
needs_modeset(new_crtc_state)) &&
+ return (!old_crtc_state->active_planes ||
intel_crtc_needs_modeset(new_crtc_state)) &&
new_crtc_state->active_planes;
}
@@ -6562,7 +6556,7 @@ static bool planes_disabling(const struct
intel_crtc_state *old_crtc_state,
const struct intel_crtc_state *new_crtc_state)
{
return old_crtc_state->active_planes &&
- (!new_crtc_state->active_planes ||
needs_modeset(new_crtc_state));
+ (!new_crtc_state->active_planes ||
intel_crtc_needs_modeset(new_crtc_state));
}
static void intel_post_plane_update(struct intel_atomic_state *state,
@@ -6685,7 +6679,7 @@ static void intel_pre_plane_update(struct
intel_atomic_state *state,
* If we're doing a modeset we don't need to do any
* pre-vblank watermark programming here.
*/
- if (!needs_modeset(new_crtc_state)) {
+ if (!intel_crtc_needs_modeset(new_crtc_state)) {
/*
* For platforms that support atomic watermarks, program the
* 'intermediate' watermarks immediately. On pre-gen9
platforms, these
@@ -12046,7 +12040,7 @@ static void i9xx_update_cursor(struct intel_plane
*plane,
if (INTEL_GEN(dev_priv) >= 9)
skl_write_cursor_wm(plane, crtc_state);
- if (!needs_modeset(crtc_state))
+ if (!intel_crtc_needs_modeset(crtc_state))
intel_psr2_program_plane_sel_fetch(plane, crtc_state,
plane_state, 0);
if (plane->cursor.base != base ||
@@ -12616,7 +12610,7 @@ int intel_plane_atomic_calc_changes(const struct
intel_crtc_state *old_crtc_stat
struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane);
struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
- bool mode_changed = needs_modeset(crtc_state);
+ bool mode_changed = intel_crtc_needs_modeset(crtc_state);
bool was_crtc_enabled = old_crtc_state->hw.active;
bool is_crtc_enabled = crtc_state->hw.active;
bool turn_off, turn_on, visible, was_visible;
@@ -12980,7 +12974,7 @@ static int intel_crtc_atomic_check(struct
intel_atomic_state *state,
struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
struct intel_crtc_state *crtc_state =
intel_atomic_get_new_crtc_state(state, crtc);
- bool mode_changed = needs_modeset(crtc_state);
+ bool mode_changed = intel_crtc_needs_modeset(crtc_state);
int ret;
if (INTEL_GEN(dev_priv) < 5 && !IS_G4X(dev_priv) &&
@@ -14812,7 +14806,7 @@ intel_modeset_verify_crtc(struct intel_crtc *crtc,
struct intel_crtc_state *old_crtc_state,
struct intel_crtc_state *new_crtc_state)
{
- if (!needs_modeset(
[Intel-gfx] [PATCH v4 02/11] drm/i915/display: move to_intel_frontbuffer to header
From: Dave Airlie
This will be used for some refactoring in other files, so move it
first.
Signed-off-by: Dave Airlie
Reviewed-by: Ville Syrjälä
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/i915/display/intel_display.c | 6 --
drivers/gpu/drm/i915/display/intel_display_types.h | 6 ++
2 files changed, 6 insertions(+), 6 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display.c
b/drivers/gpu/drm/i915/display/intel_display.c
index 2d96b0563548..f3f5a7b8df9b 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -3611,12 +3611,6 @@ static void intel_plane_disable_noatomic(struct
intel_crtc *crtc,
intel_disable_plane(plane, crtc_state);
}
-static struct intel_frontbuffer *
-to_intel_frontbuffer(struct drm_framebuffer *fb)
-{
- return fb ? to_intel_framebuffer(fb)->frontbuffer : NULL;
-}
-
static void
intel_find_initial_plane_obj(struct intel_crtc *intel_crtc,
struct intel_initial_plane_config *plane_config)
diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h
b/drivers/gpu/drm/i915/display/intel_display_types.h
index a2f6b7c161a4..dfa3966e5fa1 100644
--- a/drivers/gpu/drm/i915/display/intel_display_types.h
+++ b/drivers/gpu/drm/i915/display/intel_display_types.h
@@ -1805,4 +1805,10 @@ static inline u32 intel_plane_ggtt_offset(const struct
intel_plane_state *state)
return i915_ggtt_offset(state->vma);
}
+static inline struct intel_frontbuffer *
+to_intel_frontbuffer(struct drm_framebuffer *fb)
+{
+ return fb ? to_intel_framebuffer(fb)->frontbuffer : NULL;
+}
+
#endif /* __INTEL_DISPLAY_TYPES_H__ */
--
2.20.1
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH v4 03/11] drm/i915/display: fix misused comma
From: Dave Airlie
There is no need for a comma use here.
Reviewed-by: Ville Syrjälä
Signed-off-by: Dave Airlie
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/i915/display/intel_display.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display.c
b/drivers/gpu/drm/i915/display/intel_display.c
index f3f5a7b8df9b..ef719a44d4f1 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -989,7 +989,8 @@ chv_find_best_dpll(const struct intel_limit *limit,
* set to 2. If requires to support 200Mhz refclk, we need to
* revisit this because n may not 1 anymore.
*/
- clock.n = 1, clock.m1 = 2;
+ clock.n = 1;
+ clock.m1 = 2;
target *= 5;/* fast clock */
for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) {
--
2.20.1
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH v4 04/11] drm/i915: refactor cursor code out of i915_display.c
From: Dave Airlie
This file is a monster, let's start simple, the cursor plane code
seems pretty standalone, and splits out easily enough.
Reviewed-by: Ville Syrjälä
Signed-off-by: Dave Airlie
[Jani: cleaned up intel_cursor.h a bit.]
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/i915/Makefile| 1 +
drivers/gpu/drm/i915/display/intel_cursor.c | 806 +++
drivers/gpu/drm/i915/display/intel_cursor.h | 17 +
drivers/gpu/drm/i915/display/intel_display.c | 797 +-
drivers/gpu/drm/i915/display/intel_display.h | 7 +
5 files changed, 838 insertions(+), 790 deletions(-)
create mode 100644 drivers/gpu/drm/i915/display/intel_cursor.c
create mode 100644 drivers/gpu/drm/i915/display/intel_cursor.h
diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makefile
index f9ef5199b124..b6558401691e 100644
--- a/drivers/gpu/drm/i915/Makefile
+++ b/drivers/gpu/drm/i915/Makefile
@@ -198,6 +198,7 @@ i915-y += \
display/intel_combo_phy.o \
display/intel_connector.o \
display/intel_csr.o \
+ display/intel_cursor.o \
display/intel_display.o \
display/intel_display_power.o \
display/intel_dpio_phy.o \
diff --git a/drivers/gpu/drm/i915/display/intel_cursor.c
b/drivers/gpu/drm/i915/display/intel_cursor.c
new file mode 100644
index ..276d2bb0e2cf
--- /dev/null
+++ b/drivers/gpu/drm/i915/display/intel_cursor.c
@@ -0,0 +1,806 @@
+// SPDX-License-Identifier: MIT
+/*
+ * Copyright © 2020 Intel Corporation
+ */
+#include
+
+#include
+#include
+#include
+#include
+#include
+
+#include "intel_atomic.h"
+#include "intel_atomic_plane.h"
+#include "intel_cursor.h"
+#include "intel_display_types.h"
+#include "intel_display.h"
+
+#include "intel_frontbuffer.h"
+#include "intel_pm.h"
+#include "intel_psr.h"
+#include "intel_sprite.h"
+
+/* Cursor formats */
+static const u32 intel_cursor_formats[] = {
+ DRM_FORMAT_ARGB,
+};
+
+static const u64 cursor_format_modifiers[] = {
+ DRM_FORMAT_MOD_LINEAR,
+ DRM_FORMAT_MOD_INVALID
+};
+
+static u32 intel_cursor_base(const struct intel_plane_state *plane_state)
+{
+ struct drm_i915_private *dev_priv =
+ to_i915(plane_state->uapi.plane->dev);
+ const struct drm_framebuffer *fb = plane_state->hw.fb;
+ const struct drm_i915_gem_object *obj = intel_fb_obj(fb);
+ u32 base;
+
+ if (INTEL_INFO(dev_priv)->display.cursor_needs_physical)
+ base = sg_dma_address(obj->mm.pages->sgl);
+ else
+ base = intel_plane_ggtt_offset(plane_state);
+
+ return base + plane_state->color_plane[0].offset;
+}
+
+static u32 intel_cursor_position(const struct intel_plane_state *plane_state)
+{
+ int x = plane_state->uapi.dst.x1;
+ int y = plane_state->uapi.dst.y1;
+ u32 pos = 0;
+
+ if (x < 0) {
+ pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT;
+ x = -x;
+ }
+ pos |= x << CURSOR_X_SHIFT;
+
+ if (y < 0) {
+ pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT;
+ y = -y;
+ }
+ pos |= y << CURSOR_Y_SHIFT;
+
+ return pos;
+}
+
+static bool intel_cursor_size_ok(const struct intel_plane_state *plane_state)
+{
+ const struct drm_mode_config *config =
+ &plane_state->uapi.plane->dev->mode_config;
+ int width = drm_rect_width(&plane_state->uapi.dst);
+ int height = drm_rect_height(&plane_state->uapi.dst);
+
+ return width > 0 && width <= config->cursor_width &&
+ height > 0 && height <= config->cursor_height;
+}
+
+static int intel_cursor_check_surface(struct intel_plane_state *plane_state)
+{
+ struct drm_i915_private *dev_priv =
+ to_i915(plane_state->uapi.plane->dev);
+ unsigned int rotation = plane_state->hw.rotation;
+ int src_x, src_y;
+ u32 offset;
+ int ret;
+
+ ret = intel_plane_compute_gtt(plane_state);
+ if (ret)
+ return ret;
+
+ if (!plane_state->uapi.visible)
+ return 0;
+
+ src_x = plane_state->uapi.src.x1 >> 16;
+ src_y = plane_state->uapi.src.y1 >> 16;
+
+ intel_add_fb_offsets(&src_x, &src_y, plane_state, 0);
+ offset = intel_plane_compute_aligned_offset(&src_x, &src_y,
+ plane_state, 0);
+
+ if (src_x != 0 || src_y != 0) {
+ drm_dbg_kms(&dev_priv->drm,
+ "Arbitrary cursor panning not supported\n");
+ return -EINVAL;
+ }
+
+ /*
+* Put the final coordinates back so that the src
+* coo
[Intel-gfx] [PATCH v4 05/11] drm/i915: refactor some crtc code out of intel display.
From: Dave Airlie
There may be more crtc code that can be pulled out, but this
is a good start.
Signed-off-by: Dave Airlie
[Jani: cleaned up intel_crtc.h a bit.]
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/i915/Makefile| 1 +
drivers/gpu/drm/i915/display/intel_crtc.c| 953 +++
drivers/gpu/drm/i915/display/intel_crtc.h| 22 +
drivers/gpu/drm/i915/display/intel_display.c | 934 +-
4 files changed, 977 insertions(+), 933 deletions(-)
create mode 100644 drivers/gpu/drm/i915/display/intel_crtc.c
create mode 100644 drivers/gpu/drm/i915/display/intel_crtc.h
diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makefile
index b6558401691e..f2e907333f72 100644
--- a/drivers/gpu/drm/i915/Makefile
+++ b/drivers/gpu/drm/i915/Makefile
@@ -197,6 +197,7 @@ i915-y += \
display/intel_color.o \
display/intel_combo_phy.o \
display/intel_connector.o \
+ display/intel_crtc.o \
display/intel_csr.o \
display/intel_cursor.o \
display/intel_display.o \
diff --git a/drivers/gpu/drm/i915/display/intel_crtc.c
b/drivers/gpu/drm/i915/display/intel_crtc.c
new file mode 100644
index ..d26beb8ad9ed
--- /dev/null
+++ b/drivers/gpu/drm/i915/display/intel_crtc.c
@@ -0,0 +1,953 @@
+// SPDX-License-Identifier: MIT
+/*
+ * Copyright © 2020 Intel Corporation
+ */
+#include
+#include
+
+#include
+#include
+#include
+#include
+
+#include "intel_atomic.h"
+#include "intel_atomic_plane.h"
+#include "intel_color.h"
+#include "intel_crtc.h"
+#include "intel_cursor.h"
+#include "intel_display_debugfs.h"
+#include "intel_display_types.h"
+#include "intel_pipe_crc.h"
+#include "intel_sprite.h"
+
+/* Primary plane formats for gen <= 3 */
+static const u32 i8xx_primary_formats[] = {
+ DRM_FORMAT_C8,
+ DRM_FORMAT_XRGB1555,
+ DRM_FORMAT_RGB565,
+ DRM_FORMAT_XRGB,
+};
+
+/* Primary plane formats for ivb (no fp16 due to hw issue) */
+static const u32 ivb_primary_formats[] = {
+ DRM_FORMAT_C8,
+ DRM_FORMAT_RGB565,
+ DRM_FORMAT_XRGB,
+ DRM_FORMAT_XBGR,
+ DRM_FORMAT_XRGB2101010,
+ DRM_FORMAT_XBGR2101010,
+};
+
+/* Primary plane formats for gen >= 4, except ivb */
+static const u32 i965_primary_formats[] = {
+ DRM_FORMAT_C8,
+ DRM_FORMAT_RGB565,
+ DRM_FORMAT_XRGB,
+ DRM_FORMAT_XBGR,
+ DRM_FORMAT_XRGB2101010,
+ DRM_FORMAT_XBGR2101010,
+ DRM_FORMAT_XBGR16161616F,
+};
+
+/* Primary plane formats for vlv/chv */
+static const u32 vlv_primary_formats[] = {
+ DRM_FORMAT_C8,
+ DRM_FORMAT_RGB565,
+ DRM_FORMAT_XRGB,
+ DRM_FORMAT_XBGR,
+ DRM_FORMAT_ARGB,
+ DRM_FORMAT_ABGR,
+ DRM_FORMAT_XRGB2101010,
+ DRM_FORMAT_XBGR2101010,
+ DRM_FORMAT_ARGB2101010,
+ DRM_FORMAT_ABGR2101010,
+ DRM_FORMAT_XBGR16161616F,
+};
+
+static const u64 i9xx_format_modifiers[] = {
+ I915_FORMAT_MOD_X_TILED,
+ DRM_FORMAT_MOD_LINEAR,
+ DRM_FORMAT_MOD_INVALID
+};
+
+static bool i8xx_plane_format_mod_supported(struct drm_plane *_plane,
+ u32 format, u64 modifier)
+{
+ switch (modifier) {
+ case DRM_FORMAT_MOD_LINEAR:
+ case I915_FORMAT_MOD_X_TILED:
+ break;
+ default:
+ return false;
+ }
+
+ switch (format) {
+ case DRM_FORMAT_C8:
+ case DRM_FORMAT_RGB565:
+ case DRM_FORMAT_XRGB1555:
+ case DRM_FORMAT_XRGB:
+ return modifier == DRM_FORMAT_MOD_LINEAR ||
+ modifier == I915_FORMAT_MOD_X_TILED;
+ default:
+ return false;
+ }
+}
+
+static bool i965_plane_format_mod_supported(struct drm_plane *_plane,
+ u32 format, u64 modifier)
+{
+ switch (modifier) {
+ case DRM_FORMAT_MOD_LINEAR:
+ case I915_FORMAT_MOD_X_TILED:
+ break;
+ default:
+ return false;
+ }
+
+ switch (format) {
+ case DRM_FORMAT_C8:
+ case DRM_FORMAT_RGB565:
+ case DRM_FORMAT_XRGB:
+ case DRM_FORMAT_XBGR:
+ case DRM_FORMAT_ARGB:
+ case DRM_FORMAT_ABGR:
+ case DRM_FORMAT_XRGB2101010:
+ case DRM_FORMAT_XBGR2101010:
+ case DRM_FORMAT_ARGB2101010:
+ case DRM_FORMAT_ABGR2101010:
+ case DRM_FORMAT_XBGR16161616F:
+ return modifier == DRM_FORMAT_MOD_LINEAR ||
+ modifier == I915_FORMAT_MOD_X_TILED;
+ default:
+ return false;
+ }
+}
+
+static bool i9xx_plane_has_fbc(struct drm_i915_private *dev_priv,
+ enum i9xx_plane_id i9xx_plane)
+{
+ if (!HAS_FBC(dev_priv))
+ return false;
+
+ if (IS_BROADWELL(de
[Intel-gfx] [PATCH v4 06/11] drm/i915: refactor pll code out into intel_dpll.c
From: Dave Airlie
This pulls a large chunk of the pll calculation code out of
intel_display.c to a new file.
One function makes sense to be an inline, otherwise this
is pretty much a straight copy cover. Also all the
remaining hooks for g45 and older end up the same now.
Signed-off-by: Dave Airlie
[Jani: cleaned up intel_dpll.h a bit, de-duped intel_panel_use_ssc().]
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/i915/Makefile |1 +
drivers/gpu/drm/i915/display/intel_display.c | 1402 +
drivers/gpu/drm/i915/display/intel_display.h |3 +
.../drm/i915/display/intel_display_types.h| 13 +
drivers/gpu/drm/i915/display/intel_dpll.c | 1363
drivers/gpu/drm/i915/display/intel_dpll.h | 23 +
6 files changed, 1414 insertions(+), 1391 deletions(-)
create mode 100644 drivers/gpu/drm/i915/display/intel_dpll.c
create mode 100644 drivers/gpu/drm/i915/display/intel_dpll.h
diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makefile
index f2e907333f72..f2424d67f306 100644
--- a/drivers/gpu/drm/i915/Makefile
+++ b/drivers/gpu/drm/i915/Makefile
@@ -203,6 +203,7 @@ i915-y += \
display/intel_display.o \
display/intel_display_power.o \
display/intel_dpio_phy.o \
+ display/intel_dpll.o \
display/intel_dpll_mgr.o \
display/intel_dsb.o \
display/intel_fbc.o \
diff --git a/drivers/gpu/drm/i915/display/intel_display.c
b/drivers/gpu/drm/i915/display/intel_display.c
index 530222e68ee2..a559abf602cb 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -48,6 +48,7 @@
#include "display/intel_display_debugfs.h"
#include "display/intel_dp.h"
#include "display/intel_dp_mst.h"
+#include "display/intel_dpll.h"
#include "display/intel_dpll_mgr.h"
#include "display/intel_dsi.h"
#include "display/intel_dvo.h"
@@ -114,17 +115,6 @@ static void ilk_pfit_enable(const struct intel_crtc_state
*crtc_state);
static void intel_modeset_setup_hw_state(struct drm_device *dev,
struct drm_modeset_acquire_ctx *ctx);
-struct intel_limit {
- struct {
- int min, max;
- } dot, vco, n, m, m1, m2, p, p1;
-
- struct {
- int dot_limit;
- int p2_slow, p2_fast;
- } p2;
-};
-
/* returns HPLL frequency in kHz */
int vlv_get_hpll_vco(struct drm_i915_private *dev_priv)
{
@@ -192,271 +182,6 @@ static u32 intel_fdi_link_freq(struct drm_i915_private
*dev_priv,
return dev_priv->fdi_pll_freq;
}
-static const struct intel_limit intel_limits_i8xx_dac = {
- .dot = { .min = 25000, .max = 35 },
- .vco = { .min = 908000, .max = 1512000 },
- .n = { .min = 2, .max = 16 },
- .m = { .min = 96, .max = 140 },
- .m1 = { .min = 18, .max = 26 },
- .m2 = { .min = 6, .max = 16 },
- .p = { .min = 4, .max = 128 },
- .p1 = { .min = 2, .max = 33 },
- .p2 = { .dot_limit = 165000,
- .p2_slow = 4, .p2_fast = 2 },
-};
-
-static const struct intel_limit intel_limits_i8xx_dvo = {
- .dot = { .min = 25000, .max = 35 },
- .vco = { .min = 908000, .max = 1512000 },
- .n = { .min = 2, .max = 16 },
- .m = { .min = 96, .max = 140 },
- .m1 = { .min = 18, .max = 26 },
- .m2 = { .min = 6, .max = 16 },
- .p = { .min = 4, .max = 128 },
- .p1 = { .min = 2, .max = 33 },
- .p2 = { .dot_limit = 165000,
- .p2_slow = 4, .p2_fast = 4 },
-};
-
-static const struct intel_limit intel_limits_i8xx_lvds = {
- .dot = { .min = 25000, .max = 35 },
- .vco = { .min = 908000, .max = 1512000 },
- .n = { .min = 2, .max = 16 },
- .m = { .min = 96, .max = 140 },
- .m1 = { .min = 18, .max = 26 },
- .m2 = { .min = 6, .max = 16 },
- .p = { .min = 4, .max = 128 },
- .p1 = { .min = 1, .max = 6 },
- .p2 = { .dot_limit = 165000,
- .p2_slow = 14, .p2_fast = 7 },
-};
-
-static const struct intel_limit intel_limits_i9xx_sdvo = {
- .dot = { .min = 2, .max = 40 },
- .vco = { .min = 140, .max = 280 },
- .n = { .min = 1, .max = 6 },
- .m = { .min = 70, .max = 120 },
- .m1 = { .min = 8, .max = 18 },
- .m2 = { .min = 3, .max = 7 },
- .p = { .min = 5, .max = 80 },
- .p1 = { .min = 1, .max = 8 },
- .p2 = { .dot_limit = 20,
- .p2_slow = 10, .p2_fast = 5 },
-};
-
-static const struct intel_limit intel_limits_i9xx_lvds = {
- .dot = { .min = 2, .max = 40 },
- .vco = { .min = 140, .max = 280 },
- .n = { .min = 1, .max = 6 },
- .m = { .min = 70, .max = 120 },
- .m1 = { .min = 8, .max = 18 },
- .m2 = { .min = 3, .max = 7 },
- .p = { .min = 7, .max = 98 },
- .p1 = { .min = 1, .max
[Intel-gfx] [PATCH v4 07/11] drm/i915: split fdi code out from intel_display.c
From: Dave Airlie
This just refactors out the fdi code to a separate file.
Signed-off-by: Dave Airlie
[Jani: cleaned up intel_fdi.h a bit.]
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/i915/Makefile | 1 +
drivers/gpu/drm/i915/display/intel_display.c | 685 +-
.../drm/i915/display/intel_display_types.h| 9 +
drivers/gpu/drm/i915/display/intel_fdi.c | 683 +
drivers/gpu/drm/i915/display/intel_fdi.h | 22 +
5 files changed, 718 insertions(+), 682 deletions(-)
create mode 100644 drivers/gpu/drm/i915/display/intel_fdi.c
create mode 100644 drivers/gpu/drm/i915/display/intel_fdi.h
diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makefile
index f2424d67f306..42f9c1ca3c08 100644
--- a/drivers/gpu/drm/i915/Makefile
+++ b/drivers/gpu/drm/i915/Makefile
@@ -207,6 +207,7 @@ i915-y += \
display/intel_dpll_mgr.o \
display/intel_dsb.o \
display/intel_fbc.o \
+ display/intel_fdi.o \
display/intel_fifo_underrun.o \
display/intel_frontbuffer.o \
display/intel_global_state.o \
diff --git a/drivers/gpu/drm/i915/display/intel_display.c
b/drivers/gpu/drm/i915/display/intel_display.c
index a559abf602cb..8c99df404259 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -74,6 +74,7 @@
#include "intel_display_types.h"
#include "intel_dp_link_training.h"
#include "intel_fbc.h"
+#include "intel_fdi.h"
#include "intel_fbdev.h"
#include "intel_fifo_underrun.h"
#include "intel_frontbuffer.h"
@@ -172,16 +173,6 @@ static void intel_update_czclk(struct drm_i915_private
*dev_priv)
dev_priv->czclk_freq);
}
-/* units of 100MHz */
-static u32 intel_fdi_link_freq(struct drm_i915_private *dev_priv,
- const struct intel_crtc_state *pipe_config)
-{
- if (HAS_DDI(dev_priv))
- return pipe_config->port_clock; /* SPLL */
- else
- return dev_priv->fdi_pll_freq;
-}
-
/* WA Display #0827: Gen9:all */
static void
skl_wa_827(struct drm_i915_private *dev_priv, enum pipe pipe, bool enable)
@@ -3766,532 +3757,6 @@ static void icl_set_pipe_chicken(struct intel_crtc
*crtc)
intel_de_write(dev_priv, PIPE_CHICKEN(pipe), tmp);
}
-static void intel_fdi_normal_train(struct intel_crtc *crtc)
-{
- struct drm_device *dev = crtc->base.dev;
- struct drm_i915_private *dev_priv = to_i915(dev);
- enum pipe pipe = crtc->pipe;
- i915_reg_t reg;
- u32 temp;
-
- /* enable normal train */
- reg = FDI_TX_CTL(pipe);
- temp = intel_de_read(dev_priv, reg);
- if (IS_IVYBRIDGE(dev_priv)) {
- temp &= ~FDI_LINK_TRAIN_NONE_IVB;
- temp |= FDI_LINK_TRAIN_NONE_IVB | FDI_TX_ENHANCE_FRAME_ENABLE;
- } else {
- temp &= ~FDI_LINK_TRAIN_NONE;
- temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE;
- }
- intel_de_write(dev_priv, reg, temp);
-
- reg = FDI_RX_CTL(pipe);
- temp = intel_de_read(dev_priv, reg);
- if (HAS_PCH_CPT(dev_priv)) {
- temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
- temp |= FDI_LINK_TRAIN_NORMAL_CPT;
- } else {
- temp &= ~FDI_LINK_TRAIN_NONE;
- temp |= FDI_LINK_TRAIN_NONE;
- }
- intel_de_write(dev_priv, reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE);
-
- /* wait one idle pattern time */
- intel_de_posting_read(dev_priv, reg);
- udelay(1000);
-
- /* IVB wants error correction enabled */
- if (IS_IVYBRIDGE(dev_priv))
- intel_de_write(dev_priv, reg,
- intel_de_read(dev_priv, reg) |
FDI_FS_ERRC_ENABLE | FDI_FE_ERRC_ENABLE);
-}
-
-/* The FDI link training functions for ILK/Ibexpeak. */
-static void ilk_fdi_link_train(struct intel_crtc *crtc,
- const struct intel_crtc_state *crtc_state)
-{
- struct drm_device *dev = crtc->base.dev;
- struct drm_i915_private *dev_priv = to_i915(dev);
- enum pipe pipe = crtc->pipe;
- i915_reg_t reg;
- u32 temp, tries;
-
- /* FDI needs bits from pipe first */
- assert_pipe_enabled(dev_priv, crtc_state->cpu_transcoder);
-
- /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
- for train result */
- reg = FDI_RX_IMR(pipe);
- temp = intel_de_read(dev_priv, reg);
- temp &= ~FDI_RX_SYMBOL_LOCK;
- temp &= ~FDI_RX_BIT_LOCK;
- intel_de_write(dev_priv, reg, temp);
- intel_de_read(dev_priv, reg);
- udelay(150);
-
- /* enable CPU FDI TX and PCH FDI RX */
- reg = FDI_TX_CTL(pipe);
- temp = intel_de_read(dev_priv, reg);
- temp &= ~FDI_DP_PORT_WIDTH_MASK;
- temp |
[Intel-gfx] [PATCH v4 08/11] drm/i915: migrate hsw fdi code to new file.
From: Dave Airlie
Daniel asked for this, but it's a bit messy and I'm not sure
how best to clean it up yet.
Signed-off-by: Dave Airlie
[Jani: also moved fdi buf trans to intel_fdi.c.]
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/i915/display/intel_crt.c | 1 +
drivers/gpu/drm/i915/display/intel_ddi.c | 197 +--
drivers/gpu/drm/i915/display/intel_ddi.h | 14 +-
drivers/gpu/drm/i915/display/intel_fdi.c | 174
drivers/gpu/drm/i915/display/intel_fdi.h | 7 +
5 files changed, 202 insertions(+), 191 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_crt.c
b/drivers/gpu/drm/i915/display/intel_crt.c
index 4934edd51cb0..077ebc7e6396 100644
--- a/drivers/gpu/drm/i915/display/intel_crt.c
+++ b/drivers/gpu/drm/i915/display/intel_crt.c
@@ -38,6 +38,7 @@
#include "intel_crt.h"
#include "intel_ddi.h"
#include "intel_display_types.h"
+#include "intel_fdi.h"
#include "intel_fifo_underrun.h"
#include "intel_gmbus.h"
#include "intel_hotplug.h"
diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c
b/drivers/gpu/drm/i915/display/intel_ddi.c
index 6863236df1d0..deabb1ad6045 100644
--- a/drivers/gpu/drm/i915/display/intel_ddi.c
+++ b/drivers/gpu/drm/i915/display/intel_ddi.c
@@ -35,10 +35,11 @@
#include "intel_ddi.h"
#include "intel_display_types.h"
#include "intel_dp.h"
-#include "intel_dp_mst.h"
#include "intel_dp_link_training.h"
+#include "intel_dp_mst.h"
#include "intel_dpio_phy.h"
#include "intel_dsi.h"
+#include "intel_fdi.h"
#include "intel_fifo_underrun.h"
#include "intel_gmbus.h"
#include "intel_hdcp.h"
@@ -51,12 +52,6 @@
#include "intel_tc.h"
#include "intel_vdsc.h"
-struct ddi_buf_trans {
- u32 trans1; /* balance leg enable, de-emph level */
- u32 trans2; /* vref sel, vswing */
- u8 i_boost; /* SKL: I_boost; valid: 0x0, 0x1, 0x3, 0x7 */
-};
-
static const u8 index_to_dp_signal_levels[] = {
[0] = DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_0,
[1] = DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_1,
@@ -86,18 +81,6 @@ static const struct ddi_buf_trans hsw_ddi_translations_dp[]
= {
{ 0x80D75FFF, 0x000B, 0x0 },
};
-static const struct ddi_buf_trans hsw_ddi_translations_fdi[] = {
- { 0x00FF, 0x0007000E, 0x0 },
- { 0x00D75FFF, 0x000F000A, 0x0 },
- { 0x00C30FFF, 0x00060006, 0x0 },
- { 0x00AAAFFF, 0x001E, 0x0 },
- { 0x00FF, 0x000F000A, 0x0 },
- { 0x00D75FFF, 0x00160004, 0x0 },
- { 0x00C30FFF, 0x001E, 0x0 },
- { 0x00FF, 0x00060006, 0x0 },
- { 0x00D75FFF, 0x001E, 0x0 },
-};
-
static const struct ddi_buf_trans hsw_ddi_translations_hdmi[] = {
/* Idx NT mV d T mV d db */
{ 0x00FF, 0x0006000E, 0x0 },/* 0: 400 400 0 */
@@ -138,18 +121,6 @@ static const struct ddi_buf_trans
bdw_ddi_translations_dp[] = {
{ 0x80D75FFF, 0x001B0002, 0x0 },
};
-static const struct ddi_buf_trans bdw_ddi_translations_fdi[] = {
- { 0x00FF, 0x0001000E, 0x0 },
- { 0x00D75FFF, 0x0004000A, 0x0 },
- { 0x00C30FFF, 0x00070006, 0x0 },
- { 0x00AAAFFF, 0x000C, 0x0 },
- { 0x00FF, 0x0004000A, 0x0 },
- { 0x00D75FFF, 0x00090004, 0x0 },
- { 0x00C30FFF, 0x000C, 0x0 },
- { 0x00FF, 0x00070006, 0x0 },
- { 0x00D75FFF, 0x000C, 0x0 },
-};
-
static const struct ddi_buf_trans bdw_ddi_translations_hdmi[] = {
/* Idx NT mV d T mV df db */
{ 0x00FF, 0x0007000E, 0x0 },/* 0: 400 400 0 */
@@ -929,22 +900,6 @@ intel_ddi_get_buf_trans_edp(struct intel_encoder *encoder,
int *n_entries)
return NULL;
}
-static const struct ddi_buf_trans *
-intel_ddi_get_buf_trans_fdi(struct drm_i915_private *dev_priv,
- int *n_entries)
-{
- if (IS_BROADWELL(dev_priv)) {
- *n_entries = ARRAY_SIZE(bdw_ddi_translations_fdi);
- return bdw_ddi_translations_fdi;
- } else if (IS_HASWELL(dev_priv)) {
- *n_entries = ARRAY_SIZE(hsw_ddi_translations_fdi);
- return hsw_ddi_translations_fdi;
- }
-
- *n_entries = 0;
- return NULL;
-}
-
static const struct ddi_buf_trans *
intel_ddi_get_buf_trans_hdmi(struct intel_encoder *encoder,
int *n_entries)
@@ -1398,8 +1353,8 @@ static int intel_ddi_hdmi_level(struct intel_encoder
*encoder,
* values in advance. This function programs the correct values for
* DP/eDP/FDI use cases.
*/
-static void intel_prepare_dp_ddi_buffers(struct intel_encoder *encoder,
-const struct intel_crtc_state
[Intel-gfx] [PATCH v4 10/11] drm/i915: move pipe update code into crtc.
From: Dave Airlie
Daniel suggested this should move here.
Signed-off-by: Dave Airlie
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/i915/display/intel_crtc.c | 230
drivers/gpu/drm/i915/display/intel_sprite.c | 228 ---
2 files changed, 230 insertions(+), 228 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_crtc.c
b/drivers/gpu/drm/i915/display/intel_crtc.c
index 0161e18f1a50..9010c55bbc4e 100644
--- a/drivers/gpu/drm/i915/display/intel_crtc.c
+++ b/drivers/gpu/drm/i915/display/intel_crtc.c
@@ -10,6 +10,9 @@
#include
#include
+#include "i915_trace.h"
+#include "i915_vgpu.h"
+
#include "intel_atomic.h"
#include "intel_atomic_plane.h"
#include "intel_color.h"
@@ -17,7 +20,9 @@
#include "intel_cursor.h"
#include "intel_display_debugfs.h"
#include "intel_display_types.h"
+#include "intel_dsi.h"
#include "intel_pipe_crc.h"
+#include "intel_psr.h"
#include "intel_sprite.h"
/* Primary plane formats for gen <= 3 */
@@ -955,3 +960,228 @@ int intel_crtc_init(struct drm_i915_private *dev_priv,
enum pipe pipe)
return ret;
}
+
+int intel_usecs_to_scanlines(const struct drm_display_mode *adjusted_mode,
+int usecs)
+{
+ /* paranoia */
+ if (!adjusted_mode->crtc_htotal)
+ return 1;
+
+ return DIV_ROUND_UP(usecs * adjusted_mode->crtc_clock,
+ 1000 * adjusted_mode->crtc_htotal);
+}
+
+/**
+ * intel_pipe_update_start() - start update of a set of display registers
+ * @new_crtc_state: the new crtc state
+ *
+ * Mark the start of an update to pipe registers that should be updated
+ * atomically regarding vblank. If the next vblank will happens within
+ * the next 100 us, this function waits until the vblank passes.
+ *
+ * After a successful call to this function, interrupts will be disabled
+ * until a subsequent call to intel_pipe_update_end(). That is done to
+ * avoid random delays.
+ */
+void intel_pipe_update_start(const struct intel_crtc_state *new_crtc_state)
+{
+ struct intel_crtc *crtc = to_intel_crtc(new_crtc_state->uapi.crtc);
+ struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
+ const struct drm_display_mode *adjusted_mode =
&new_crtc_state->hw.adjusted_mode;
+ long timeout = msecs_to_jiffies_timeout(1);
+ int scanline, min, max, vblank_start;
+ wait_queue_head_t *wq = drm_crtc_vblank_waitqueue(&crtc->base);
+ bool need_vlv_dsi_wa = (IS_VALLEYVIEW(dev_priv) ||
IS_CHERRYVIEW(dev_priv)) &&
+ intel_crtc_has_type(new_crtc_state, INTEL_OUTPUT_DSI);
+ DEFINE_WAIT(wait);
+ u32 psr_status;
+
+ if (new_crtc_state->uapi.async_flip)
+ return;
+
+ vblank_start = adjusted_mode->crtc_vblank_start;
+ if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE)
+ vblank_start = DIV_ROUND_UP(vblank_start, 2);
+
+ /* FIXME needs to be calibrated sensibly */
+ min = vblank_start - intel_usecs_to_scanlines(adjusted_mode,
+ VBLANK_EVASION_TIME_US);
+ max = vblank_start - 1;
+
+ if (min <= 0 || max <= 0)
+ goto irq_disable;
+
+ if (drm_WARN_ON(&dev_priv->drm, drm_crtc_vblank_get(&crtc->base)))
+ goto irq_disable;
+
+ /*
+* Wait for psr to idle out after enabling the VBL interrupts
+* VBL interrupts will start the PSR exit and prevent a PSR
+* re-entry as well.
+*/
+ if (intel_psr_wait_for_idle(new_crtc_state, &psr_status))
+ drm_err(&dev_priv->drm,
+ "PSR idle timed out 0x%x, atomic update may fail\n",
+ psr_status);
+
+ local_irq_disable();
+
+ crtc->debug.min_vbl = min;
+ crtc->debug.max_vbl = max;
+ trace_intel_pipe_update_start(crtc);
+
+ for (;;) {
+ /*
+* prepare_to_wait() has a memory barrier, which guarantees
+* other CPUs can see the task state update by the time we
+* read the scanline.
+*/
+ prepare_to_wait(wq, &wait, TASK_UNINTERRUPTIBLE);
+
+ scanline = intel_get_crtc_scanline(crtc);
+ if (scanline < min || scanline > max)
+ break;
+
+ if (!timeout) {
+ drm_err(&dev_priv->drm,
+ "Potential atomic update failure on pipe %c\n",
+ pipe_name(crtc->pipe));
+ break;
+ }
+
+ local_irq_enable();
+
+ timeout = schedule_timeout(timeout);
+
+ loca
[Intel-gfx] [PATCH v4 11/11] drm/i915: split fb scalable checks into g4x and skl versions
From: Dave Airlie
This just cleans these up a bit.
Signed-off-by: Dave Airlie
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/i915/display/intel_gen9_plane.c | 4 ++--
drivers/gpu/drm/i915/display/intel_sprite.c | 7 +++
2 files changed, 5 insertions(+), 6 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_gen9_plane.c
b/drivers/gpu/drm/i915/display/intel_gen9_plane.c
index 8549b262f095..c695ee990a82 100644
--- a/drivers/gpu/drm/i915/display/intel_gen9_plane.c
+++ b/drivers/gpu/drm/i915/display/intel_gen9_plane.c
@@ -2139,7 +2139,7 @@ static int skl_check_plane_surface(struct
intel_plane_state *plane_state)
return 0;
}
-static bool intel_fb_scalable(const struct drm_framebuffer *fb)
+static bool skl_fb_scalable(const struct drm_framebuffer *fb)
{
if (!fb)
return false;
@@ -2172,7 +2172,7 @@ static int skl_plane_check(struct intel_crtc_state
*crtc_state,
return ret;
/* use scaler when colorkey is not required */
- if (!plane_state->ckey.flags && intel_fb_scalable(fb)) {
+ if (!plane_state->ckey.flags && skl_fb_scalable(fb)) {
min_scale = 1;
max_scale = skl_plane_max_scale(dev_priv, fb);
}
diff --git a/drivers/gpu/drm/i915/display/intel_sprite.c
b/drivers/gpu/drm/i915/display/intel_sprite.c
index cc3bec42d04c..4cb6339d12be 100644
--- a/drivers/gpu/drm/i915/display/intel_sprite.c
+++ b/drivers/gpu/drm/i915/display/intel_sprite.c
@@ -1282,19 +1282,18 @@ g4x_plane_get_hw_state(struct intel_plane *plane,
return ret;
}
-static bool intel_fb_scalable(const struct drm_framebuffer *fb)
+static bool g4x_fb_scalable(const struct drm_framebuffer *fb)
{
if (!fb)
return false;
switch (fb->format->format) {
case DRM_FORMAT_C8:
- return false;
case DRM_FORMAT_XRGB16161616F:
case DRM_FORMAT_ARGB16161616F:
case DRM_FORMAT_XBGR16161616F:
case DRM_FORMAT_ABGR16161616F:
- return INTEL_GEN(to_i915(fb->dev)) >= 11;
+ return false;
default:
return true;
}
@@ -1371,7 +1370,7 @@ g4x_sprite_check(struct intel_crtc_state *crtc_state,
int max_scale = DRM_PLANE_HELPER_NO_SCALING;
int ret;
- if (intel_fb_scalable(plane_state->hw.fb)) {
+ if (g4x_fb_scalable(plane_state->hw.fb)) {
if (INTEL_GEN(dev_priv) < 7) {
min_scale = 1;
max_scale = 16 << 16;
--
2.20.1
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH 05/11] drm/i915: refactor some crtc code out of intel display.
On Wed, 16 Dec 2020, Ville Syrjälä wrote: > On Wed, Dec 16, 2020 at 12:03:37PM +0200, Jani Nikula wrote: >> On Fri, 11 Dec 2020, Dave Airlie wrote: >> > From: Dave Airlie >> > >> > There may be more crtc code that can be pulled out, but this >> > is a good start. >> > >> > RFC: maybe call the new file something different >> >> I checked this is just code movement. I did clean up intel_crtc.h >> locally a bit though. (I'll probably re-send the series with a few fixes >> to pass CI.) >> >> I'm not averse to renaming the file later if needed, I'm more concerned >> about choosing a meaningful bunch of functions to take out and put in >> the new file. >> >> Ville, I saw you had some comments about this - is this making sensible >> progress or making further refactoring harder? > > Just means we have to move 90% of the proposed intel_crtc.c > into i9xx_plane.c again. So the plane bits here are just > pointless churn IMO. Fair enough. I just don't want to stall on this again like we've stalled every time there's been proposals to clean up intel_display.c. And it's always about some things that could be moved to a different file or grouped differently or something. I'm pretty close to a point where I'll take *anything* to chop up the file, and then we'll have better clarity with smaller files when the dust settles. BR, Jani. -- Jani Nikula, Intel Open Source Graphics Center ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH v2 1/2] drm/i915/tgl: Fix REVID macros for TGL to fetch correct stepping
On Thu, 17 Dec 2020, Lucas De Marchi wrote:
> Both patches applied. Thanks!
>
> Jani, maybe now you can rebase your patch to get rid of the extern ?
Yes, thanks for the irq so I can stop polling. ;)
BR,
Jani.
>
>
> Lucas De Marchi
>
> On Wed, Dec 02, 2020 at 11:23:58PM -0800, Aditya Swarup wrote:
>>Fix TGL REVID macros to fetch correct display/gt stepping based
>>on SOC rev id from INTEL_REVID() macro. Previously, we were just
>>returning the first element of the revid array instead of using
>>the correct index based on SOC rev id.
>>
>>Fixes: ("drm/i915/tgl: Fix stepping WA matching")
>>Cc: José Roberto de Souza
>>Cc: Matt Roper
>>Cc: Lucas De Marchi
>>Cc: Jani Nikula
>>Cc: Ville Syrjälä
>>Signed-off-by: Aditya Swarup
>>Reviewed-by: Lucas De Marchi
>>---
>> drivers/gpu/drm/i915/i915_drv.h | 12 ++--
>> 1 file changed, 6 insertions(+), 6 deletions(-)
>>
>>diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
>>index fc1090c6889c..2e2149c9a2f4 100644
>>--- a/drivers/gpu/drm/i915/i915_drv.h
>>+++ b/drivers/gpu/drm/i915/i915_drv.h
>>@@ -1580,9 +1580,9 @@ static inline const struct i915_rev_steppings *
>> tgl_revids_get(struct drm_i915_private *dev_priv)
>> {
>> if (IS_TGL_U(dev_priv) || IS_TGL_Y(dev_priv))
>>- return tgl_uy_revids;
>>+ return &tgl_uy_revids[INTEL_REVID(dev_priv)];
>> else
>>- return tgl_revids;
>>+ return &tgl_revids[INTEL_REVID(dev_priv)];
>> }
>>
>> #define IS_TGL_DISP_REVID(p, since, until) \
>>@@ -1592,14 +1592,14 @@ tgl_revids_get(struct drm_i915_private *dev_priv)
>>
>> #define IS_TGL_UY_GT_REVID(p, since, until) \
>> ((IS_TGL_U(p) || IS_TGL_Y(p)) && \
>>- tgl_uy_revids->gt_stepping >= (since) && \
>>- tgl_uy_revids->gt_stepping <= (until))
>>+ tgl_uy_revids[INTEL_REVID(p)].gt_stepping >= (since) && \
>>+ tgl_uy_revids[INTEL_REVID(p)].gt_stepping <= (until))
>>
>> #define IS_TGL_GT_REVID(p, since, until) \
>> (IS_TIGERLAKE(p) && \
>> !(IS_TGL_U(p) || IS_TGL_Y(p)) && \
>>- tgl_revids->gt_stepping >= (since) && \
>>- tgl_revids->gt_stepping <= (until))
>>+ tgl_revids[INTEL_REVID(p)].gt_stepping >= (since) && \
>>+ tgl_revids[INTEL_REVID(p)].gt_stepping <= (until))
>>
>> #define RKL_REVID_A0 0x0
>> #define RKL_REVID_B0 0x1
>>--
>>2.27.0
>>
>>___
>>Intel-gfx mailing list
>>Intel-gfx@lists.freedesktop.org
>>https://lists.freedesktop.org/mailman/listinfo/intel-gfx
--
Jani Nikula, Intel Open Source Graphics Center
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH v2 1/2] drm/i915/tgl: Fix REVID macros for TGL to fetch correct stepping
On Fri, 18 Dec 2020, Jani Nikula wrote:
> On Thu, 17 Dec 2020, Lucas De Marchi wrote:
>> Both patches applied. Thanks!
>>
>> Jani, maybe now you can rebase your patch to get rid of the extern ?
>
> Yes, thanks for the irq so I can stop polling. ;)
Huh, why were these applied to drm-intel-gt-next? It's much more about
driver core code than gt.
BR,
Jani.
>
> BR,
> Jani.
>
>
>>
>>
>> Lucas De Marchi
>>
>> On Wed, Dec 02, 2020 at 11:23:58PM -0800, Aditya Swarup wrote:
>>>Fix TGL REVID macros to fetch correct display/gt stepping based
>>>on SOC rev id from INTEL_REVID() macro. Previously, we were just
>>>returning the first element of the revid array instead of using
>>>the correct index based on SOC rev id.
>>>
>>>Fixes: ("drm/i915/tgl: Fix stepping WA matching")
>>>Cc: José Roberto de Souza
>>>Cc: Matt Roper
>>>Cc: Lucas De Marchi
>>>Cc: Jani Nikula
>>>Cc: Ville Syrjälä
>>>Signed-off-by: Aditya Swarup
>>>Reviewed-by: Lucas De Marchi
>>>---
>>> drivers/gpu/drm/i915/i915_drv.h | 12 ++--
>>> 1 file changed, 6 insertions(+), 6 deletions(-)
>>>
>>>diff --git a/drivers/gpu/drm/i915/i915_drv.h
>>>b/drivers/gpu/drm/i915/i915_drv.h
>>>index fc1090c6889c..2e2149c9a2f4 100644
>>>--- a/drivers/gpu/drm/i915/i915_drv.h
>>>+++ b/drivers/gpu/drm/i915/i915_drv.h
>>>@@ -1580,9 +1580,9 @@ static inline const struct i915_rev_steppings *
>>> tgl_revids_get(struct drm_i915_private *dev_priv)
>>> {
>>> if (IS_TGL_U(dev_priv) || IS_TGL_Y(dev_priv))
>>>-return tgl_uy_revids;
>>>+return &tgl_uy_revids[INTEL_REVID(dev_priv)];
>>> else
>>>-return tgl_revids;
>>>+return &tgl_revids[INTEL_REVID(dev_priv)];
>>> }
>>>
>>> #define IS_TGL_DISP_REVID(p, since, until) \
>>>@@ -1592,14 +1592,14 @@ tgl_revids_get(struct drm_i915_private *dev_priv)
>>>
>>> #define IS_TGL_UY_GT_REVID(p, since, until) \
>>> ((IS_TGL_U(p) || IS_TGL_Y(p)) && \
>>>- tgl_uy_revids->gt_stepping >= (since) && \
>>>- tgl_uy_revids->gt_stepping <= (until))
>>>+ tgl_uy_revids[INTEL_REVID(p)].gt_stepping >= (since) && \
>>>+ tgl_uy_revids[INTEL_REVID(p)].gt_stepping <= (until))
>>>
>>> #define IS_TGL_GT_REVID(p, since, until) \
>>> (IS_TIGERLAKE(p) && \
>>> !(IS_TGL_U(p) || IS_TGL_Y(p)) && \
>>>- tgl_revids->gt_stepping >= (since) && \
>>>- tgl_revids->gt_stepping <= (until))
>>>+ tgl_revids[INTEL_REVID(p)].gt_stepping >= (since) && \
>>>+ tgl_revids[INTEL_REVID(p)].gt_stepping <= (until))
>>>
>>> #define RKL_REVID_A00x0
>>> #define RKL_REVID_B00x1
>>>--
>>>2.27.0
>>>
>>>___
>>>Intel-gfx mailing list
>>>Intel-gfx@lists.freedesktop.org
>>>https://lists.freedesktop.org/mailman/listinfo/intel-gfx
--
Jani Nikula, Intel Open Source Graphics Center
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PULL] drm-intel-next-fixes
Hi Dave & Daniel - drm-intel-next-fixes-2020-12-18: drm/i915 fixes for the merge window BR, Jani. The following changes since commit efd3043790c6e92f0bbe1fe385db9b544131c59c: Merge tag 'amd-drm-fixes-5.11-2020-12-16' of git://people.freedesktop.org/~agd5f/linux into drm-next (2020-12-16 23:25:51 +0100) are available in the Git repository at: git://anongit.freedesktop.org/drm/drm-intel tags/drm-intel-next-fixes-2020-12-18 for you to fetch changes up to 046f70d31ddb2069941aec54966fec5b7fbc7b7b: drm/i915/tgl: Fix REVID macros for TGL to fetch correct stepping (2020-12-18 12:30:10 +0200) drm/i915 fixes for the merge window Aditya Swarup (1): drm/i915/tgl: Fix REVID macros for TGL to fetch correct stepping Chris Wilson (2): Revert "drm/i915: re-order if/else ladder for hpd_irq_setup" drm/i915: Fix mismatch between misplaced vma check and vma insert Lionel Landwerlin (1): drm/i915/perf: also include Gen11 in OATAILPTR workaround drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c | 2 +- drivers/gpu/drm/i915/i915_drv.h| 12 ++-- drivers/gpu/drm/i915/i915_irq.c| 27 ++ drivers/gpu/drm/i915/i915_perf.c | 2 +- 4 files changed, 23 insertions(+), 20 deletions(-) -- Jani Nikula, Intel Open Source Graphics Center ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH v2 1/2] drm/i915/tgl: Fix REVID macros for TGL to fetch correct stepping
On Fri, 18 Dec 2020, Lucas De Marchi wrote:
> On Fri, Dec 18, 2020 at 01:13:49PM +0200, Jani Nikula wrote:
>>On Fri, 18 Dec 2020, Jani Nikula wrote:
>>> On Thu, 17 Dec 2020, Lucas De Marchi wrote:
>>>> Both patches applied. Thanks!
>>>>
>>>> Jani, maybe now you can rebase your patch to get rid of the extern ?
>>>
>>> Yes, thanks for the irq so I can stop polling. ;)
>>
>>Huh, why were these applied to drm-intel-gt-next? It's much more about
>>driver core code than gt.
>
> sigh... by mistake. At the time as was mainly thinking about the WAs
> that are affected by these and thought it would belong to gt.
>
> what now? Do we apply in to drm-intel-next as well or wait for a backmerge?
Maybe I'll do the refactoring in gt-next as well. Or wait for the
backmerge. *shrug*
Don't worry about it.
BR,
Jani.
>
> sorry,
>
> Lucas De Marchi
>
>>
>>BR,
>>Jani.
>>
>>
>>>
>>> BR,
>>> Jani.
>>>
>>>
>>>>
>>>>
>>>> Lucas De Marchi
>>>>
>>>> On Wed, Dec 02, 2020 at 11:23:58PM -0800, Aditya Swarup wrote:
>>>>>Fix TGL REVID macros to fetch correct display/gt stepping based
>>>>>on SOC rev id from INTEL_REVID() macro. Previously, we were just
>>>>>returning the first element of the revid array instead of using
>>>>>the correct index based on SOC rev id.
>>>>>
>>>>>Fixes: ("drm/i915/tgl: Fix stepping WA matching")
>>>>>Cc: José Roberto de Souza
>>>>>Cc: Matt Roper
>>>>>Cc: Lucas De Marchi
>>>>>Cc: Jani Nikula
>>>>>Cc: Ville Syrjälä
>>>>>Signed-off-by: Aditya Swarup
>>>>>Reviewed-by: Lucas De Marchi
>>>>>---
>>>>> drivers/gpu/drm/i915/i915_drv.h | 12 ++--
>>>>> 1 file changed, 6 insertions(+), 6 deletions(-)
>>>>>
>>>>>diff --git a/drivers/gpu/drm/i915/i915_drv.h
>>>>>b/drivers/gpu/drm/i915/i915_drv.h
>>>>>index fc1090c6889c..2e2149c9a2f4 100644
>>>>>--- a/drivers/gpu/drm/i915/i915_drv.h
>>>>>+++ b/drivers/gpu/drm/i915/i915_drv.h
>>>>>@@ -1580,9 +1580,9 @@ static inline const struct i915_rev_steppings *
>>>>> tgl_revids_get(struct drm_i915_private *dev_priv)
>>>>> {
>>>>> if (IS_TGL_U(dev_priv) || IS_TGL_Y(dev_priv))
>>>>>- return tgl_uy_revids;
>>>>>+ return &tgl_uy_revids[INTEL_REVID(dev_priv)];
>>>>> else
>>>>>- return tgl_revids;
>>>>>+ return &tgl_revids[INTEL_REVID(dev_priv)];
>>>>> }
>>>>>
>>>>> #define IS_TGL_DISP_REVID(p, since, until) \
>>>>>@@ -1592,14 +1592,14 @@ tgl_revids_get(struct drm_i915_private *dev_priv)
>>>>>
>>>>> #define IS_TGL_UY_GT_REVID(p, since, until) \
>>>>> ((IS_TGL_U(p) || IS_TGL_Y(p)) && \
>>>>>- tgl_uy_revids->gt_stepping >= (since) && \
>>>>>- tgl_uy_revids->gt_stepping <= (until))
>>>>>+ tgl_uy_revids[INTEL_REVID(p)].gt_stepping >= (since) && \
>>>>>+ tgl_uy_revids[INTEL_REVID(p)].gt_stepping <= (until))
>>>>>
>>>>> #define IS_TGL_GT_REVID(p, since, until) \
>>>>> (IS_TIGERLAKE(p) && \
>>>>>!(IS_TGL_U(p) || IS_TGL_Y(p)) && \
>>>>>- tgl_revids->gt_stepping >= (since) && \
>>>>>- tgl_revids->gt_stepping <= (until))
>>>>>+ tgl_revids[INTEL_REVID(p)].gt_stepping >= (since) && \
>>>>>+ tgl_revids[INTEL_REVID(p)].gt_stepping <= (until))
>>>>>
>>>>> #define RKL_REVID_A0 0x0
>>>>> #define RKL_REVID_B0 0x1
>>>>>--
>>>>>2.27.0
>>>>>
>>>>>___
>>>>>Intel-gfx mailing list
>>>>>Intel-gfx@lists.freedesktop.org
>>>>>https://lists.freedesktop.org/mailman/listinfo/intel-gfx
>>
>>--
>>Jani Nikula, Intel Open Source Graphics Center
--
Jani Nikula, Intel Open Source Graphics Center
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] ✗ Fi.CI.BUILD: failure for series starting with [01/16] drm/i915/display: move needs_modeset to an inline in header
On Mon, 21 Dec 2020, Patchwork wrote: > == Series Details == > > Series: series starting with [01/16] drm/i915/display: move needs_modeset to > an inline in header > URL : https://patchwork.freedesktop.org/series/85129/ > State : failure > > == Summary == > > Applying: drm/i915/display: move needs_modeset to an inline in header > Applying: drm/i915/display: move to_intel_frontbuffer to header > Applying: drm/i915/display: fix misused comma > Applying: drm/i915: refactor cursor code out of i915_display.c > Applying: drm/i915: refactor i915 plane code into separate file. > Applying: drm/i915: refactor some crtc code out of intel display. (v2) > error: sha1 information is lacking or useless (drivers/gpu/drm/i915/Makefile). > error: could not build fake ancestor > hint: Use 'git am --show-current-patch=diff' to see the failed patch > Patch failed at 0006 drm/i915: refactor some crtc code out of intel display. > (v2) > When you have resolved this problem, run "git am --continue". > If you prefer to skip this patch, run "git am --skip" instead. > To restore the original branch and stop patching, run "git am --abort". I wonder what gives here. The same thing has been happening for several versions of the series, including mine. I would've applied the early patches already if I'd gotten some test results. BR, Jani. > > > ___ > Intel-gfx mailing list > Intel-gfx@lists.freedesktop.org > https://lists.freedesktop.org/mailman/listinfo/intel-gfx -- Jani Nikula, Intel Open Source Graphics Center ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [CI 1/5] drm/i915/display: move needs_modeset to an inline in header
From: Dave Airlie
This function is going to be used in a later change, so clean it
up first before moving it.
Reviewed-by: Ville Syrjälä
Signed-off-by: Dave Airlie
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/i915/display/intel_display.c | 78 +--
.../drm/i915/display/intel_display_types.h| 6 ++
2 files changed, 42 insertions(+), 42 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display.c
b/drivers/gpu/drm/i915/display/intel_display.c
index 78452de5e12f..c435d90ec000 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -542,12 +542,6 @@ icl_wa_scalerclkgating(struct drm_i915_private *dev_priv,
enum pipe pipe,
intel_de_read(dev_priv, CLKGATE_DIS_PSL(pipe)) &
~DPFR_GATING_DIS);
}
-static bool
-needs_modeset(const struct intel_crtc_state *state)
-{
- return drm_atomic_crtc_needs_modeset(&state->uapi);
-}
-
static bool
is_trans_port_sync_slave(const struct intel_crtc_state *crtc_state)
{
@@ -6474,7 +6468,7 @@ static bool hsw_pre_update_disable_ips(const struct
intel_crtc_state *old_crtc_s
if (!old_crtc_state->ips_enabled)
return false;
- if (needs_modeset(new_crtc_state))
+ if (intel_crtc_needs_modeset(new_crtc_state))
return true;
/*
@@ -6501,7 +6495,7 @@ static bool hsw_post_update_enable_ips(const struct
intel_crtc_state *old_crtc_s
if (!new_crtc_state->ips_enabled)
return false;
- if (needs_modeset(new_crtc_state))
+ if (intel_crtc_needs_modeset(new_crtc_state))
return true;
/*
@@ -6554,7 +6548,7 @@ static bool needs_scalerclk_wa(const struct
intel_crtc_state *crtc_state)
static bool planes_enabling(const struct intel_crtc_state *old_crtc_state,
const struct intel_crtc_state *new_crtc_state)
{
- return (!old_crtc_state->active_planes ||
needs_modeset(new_crtc_state)) &&
+ return (!old_crtc_state->active_planes ||
intel_crtc_needs_modeset(new_crtc_state)) &&
new_crtc_state->active_planes;
}
@@ -6562,7 +6556,7 @@ static bool planes_disabling(const struct
intel_crtc_state *old_crtc_state,
const struct intel_crtc_state *new_crtc_state)
{
return old_crtc_state->active_planes &&
- (!new_crtc_state->active_planes ||
needs_modeset(new_crtc_state));
+ (!new_crtc_state->active_planes ||
intel_crtc_needs_modeset(new_crtc_state));
}
static void intel_post_plane_update(struct intel_atomic_state *state,
@@ -6685,7 +6679,7 @@ static void intel_pre_plane_update(struct
intel_atomic_state *state,
* If we're doing a modeset we don't need to do any
* pre-vblank watermark programming here.
*/
- if (!needs_modeset(new_crtc_state)) {
+ if (!intel_crtc_needs_modeset(new_crtc_state)) {
/*
* For platforms that support atomic watermarks, program the
* 'intermediate' watermarks immediately. On pre-gen9
platforms, these
@@ -12046,7 +12040,7 @@ static void i9xx_update_cursor(struct intel_plane
*plane,
if (INTEL_GEN(dev_priv) >= 9)
skl_write_cursor_wm(plane, crtc_state);
- if (!needs_modeset(crtc_state))
+ if (!intel_crtc_needs_modeset(crtc_state))
intel_psr2_program_plane_sel_fetch(plane, crtc_state,
plane_state, 0);
if (plane->cursor.base != base ||
@@ -12616,7 +12610,7 @@ int intel_plane_atomic_calc_changes(const struct
intel_crtc_state *old_crtc_stat
struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane);
struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
- bool mode_changed = needs_modeset(crtc_state);
+ bool mode_changed = intel_crtc_needs_modeset(crtc_state);
bool was_crtc_enabled = old_crtc_state->hw.active;
bool is_crtc_enabled = crtc_state->hw.active;
bool turn_off, turn_on, visible, was_visible;
@@ -12980,7 +12974,7 @@ static int intel_crtc_atomic_check(struct
intel_atomic_state *state,
struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
struct intel_crtc_state *crtc_state =
intel_atomic_get_new_crtc_state(state, crtc);
- bool mode_changed = needs_modeset(crtc_state);
+ bool mode_changed = intel_crtc_needs_modeset(crtc_state);
int ret;
if (INTEL_GEN(dev_priv) < 5 && !IS_G4X(dev_priv) &&
@@ -14812,7 +14806,7 @@ intel_modeset_verify_crtc(struct intel_crtc *crtc,
struct intel_crtc_state *old_crtc_state,
struct intel_crtc_state *new_crtc_state)
{
- if (!needs_modeset(
[Intel-gfx] [CI 2/5] drm/i915/display: move to_intel_frontbuffer to header
From: Dave Airlie
This will be used for some refactoring in other files, so move it
first.
Signed-off-by: Dave Airlie
Reviewed-by: Ville Syrjälä
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/i915/display/intel_display.c | 6 --
drivers/gpu/drm/i915/display/intel_display_types.h | 6 ++
2 files changed, 6 insertions(+), 6 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display.c
b/drivers/gpu/drm/i915/display/intel_display.c
index c435d90ec000..9063922dc073 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -3611,12 +3611,6 @@ static void intel_plane_disable_noatomic(struct
intel_crtc *crtc,
intel_disable_plane(plane, crtc_state);
}
-static struct intel_frontbuffer *
-to_intel_frontbuffer(struct drm_framebuffer *fb)
-{
- return fb ? to_intel_framebuffer(fb)->frontbuffer : NULL;
-}
-
static void
intel_find_initial_plane_obj(struct intel_crtc *intel_crtc,
struct intel_initial_plane_config *plane_config)
diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h
b/drivers/gpu/drm/i915/display/intel_display_types.h
index a2f6b7c161a4..dfa3966e5fa1 100644
--- a/drivers/gpu/drm/i915/display/intel_display_types.h
+++ b/drivers/gpu/drm/i915/display/intel_display_types.h
@@ -1805,4 +1805,10 @@ static inline u32 intel_plane_ggtt_offset(const struct
intel_plane_state *state)
return i915_ggtt_offset(state->vma);
}
+static inline struct intel_frontbuffer *
+to_intel_frontbuffer(struct drm_framebuffer *fb)
+{
+ return fb ? to_intel_framebuffer(fb)->frontbuffer : NULL;
+}
+
#endif /* __INTEL_DISPLAY_TYPES_H__ */
--
2.20.1
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [CI 3/5] drm/i915/display: fix misused comma
From: Dave Airlie
There is no need for a comma use here.
Reviewed-by: Ville Syrjälä
Signed-off-by: Dave Airlie
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/i915/display/intel_display.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display.c
b/drivers/gpu/drm/i915/display/intel_display.c
index 9063922dc073..ec9a28b69e09 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -989,7 +989,8 @@ chv_find_best_dpll(const struct intel_limit *limit,
* set to 2. If requires to support 200Mhz refclk, we need to
* revisit this because n may not 1 anymore.
*/
- clock.n = 1, clock.m1 = 2;
+ clock.n = 1;
+ clock.m1 = 2;
target *= 5;/* fast clock */
for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) {
--
2.20.1
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [CI 4/5] drm/i915: refactor cursor code out of i915_display.c
From: Dave Airlie
This file is a monster, let's start simple, the cursor plane code
seems pretty standalone, and splits out easily enough.
Reviewed-by: Ville Syrjälä
Signed-off-by: Dave Airlie
[Jani: cleaned up intel_cursor.h a bit.]
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/i915/Makefile| 1 +
drivers/gpu/drm/i915/display/intel_cursor.c | 806 +++
drivers/gpu/drm/i915/display/intel_cursor.h | 17 +
drivers/gpu/drm/i915/display/intel_display.c | 797 +-
drivers/gpu/drm/i915/display/intel_display.h | 7 +
5 files changed, 838 insertions(+), 790 deletions(-)
create mode 100644 drivers/gpu/drm/i915/display/intel_cursor.c
create mode 100644 drivers/gpu/drm/i915/display/intel_cursor.h
diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makefile
index f9ef5199b124..b6558401691e 100644
--- a/drivers/gpu/drm/i915/Makefile
+++ b/drivers/gpu/drm/i915/Makefile
@@ -198,6 +198,7 @@ i915-y += \
display/intel_combo_phy.o \
display/intel_connector.o \
display/intel_csr.o \
+ display/intel_cursor.o \
display/intel_display.o \
display/intel_display_power.o \
display/intel_dpio_phy.o \
diff --git a/drivers/gpu/drm/i915/display/intel_cursor.c
b/drivers/gpu/drm/i915/display/intel_cursor.c
new file mode 100644
index ..276d2bb0e2cf
--- /dev/null
+++ b/drivers/gpu/drm/i915/display/intel_cursor.c
@@ -0,0 +1,806 @@
+// SPDX-License-Identifier: MIT
+/*
+ * Copyright © 2020 Intel Corporation
+ */
+#include
+
+#include
+#include
+#include
+#include
+#include
+
+#include "intel_atomic.h"
+#include "intel_atomic_plane.h"
+#include "intel_cursor.h"
+#include "intel_display_types.h"
+#include "intel_display.h"
+
+#include "intel_frontbuffer.h"
+#include "intel_pm.h"
+#include "intel_psr.h"
+#include "intel_sprite.h"
+
+/* Cursor formats */
+static const u32 intel_cursor_formats[] = {
+ DRM_FORMAT_ARGB,
+};
+
+static const u64 cursor_format_modifiers[] = {
+ DRM_FORMAT_MOD_LINEAR,
+ DRM_FORMAT_MOD_INVALID
+};
+
+static u32 intel_cursor_base(const struct intel_plane_state *plane_state)
+{
+ struct drm_i915_private *dev_priv =
+ to_i915(plane_state->uapi.plane->dev);
+ const struct drm_framebuffer *fb = plane_state->hw.fb;
+ const struct drm_i915_gem_object *obj = intel_fb_obj(fb);
+ u32 base;
+
+ if (INTEL_INFO(dev_priv)->display.cursor_needs_physical)
+ base = sg_dma_address(obj->mm.pages->sgl);
+ else
+ base = intel_plane_ggtt_offset(plane_state);
+
+ return base + plane_state->color_plane[0].offset;
+}
+
+static u32 intel_cursor_position(const struct intel_plane_state *plane_state)
+{
+ int x = plane_state->uapi.dst.x1;
+ int y = plane_state->uapi.dst.y1;
+ u32 pos = 0;
+
+ if (x < 0) {
+ pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT;
+ x = -x;
+ }
+ pos |= x << CURSOR_X_SHIFT;
+
+ if (y < 0) {
+ pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT;
+ y = -y;
+ }
+ pos |= y << CURSOR_Y_SHIFT;
+
+ return pos;
+}
+
+static bool intel_cursor_size_ok(const struct intel_plane_state *plane_state)
+{
+ const struct drm_mode_config *config =
+ &plane_state->uapi.plane->dev->mode_config;
+ int width = drm_rect_width(&plane_state->uapi.dst);
+ int height = drm_rect_height(&plane_state->uapi.dst);
+
+ return width > 0 && width <= config->cursor_width &&
+ height > 0 && height <= config->cursor_height;
+}
+
+static int intel_cursor_check_surface(struct intel_plane_state *plane_state)
+{
+ struct drm_i915_private *dev_priv =
+ to_i915(plane_state->uapi.plane->dev);
+ unsigned int rotation = plane_state->hw.rotation;
+ int src_x, src_y;
+ u32 offset;
+ int ret;
+
+ ret = intel_plane_compute_gtt(plane_state);
+ if (ret)
+ return ret;
+
+ if (!plane_state->uapi.visible)
+ return 0;
+
+ src_x = plane_state->uapi.src.x1 >> 16;
+ src_y = plane_state->uapi.src.y1 >> 16;
+
+ intel_add_fb_offsets(&src_x, &src_y, plane_state, 0);
+ offset = intel_plane_compute_aligned_offset(&src_x, &src_y,
+ plane_state, 0);
+
+ if (src_x != 0 || src_y != 0) {
+ drm_dbg_kms(&dev_priv->drm,
+ "Arbitrary cursor panning not supported\n");
+ return -EINVAL;
+ }
+
+ /*
+* Put the final coordinates back so that the src
+* coo
[Intel-gfx] [CI 5/5] drm/i915: refactor i915 plane code into separate file.
From: Dave Airlie
Ville suggested this as a good idea, let's move this before moving
the crtc code.
Signed-off-by: Dave Airlie
Reviewed-by: Ville Syrjälä
---
drivers/gpu/drm/i915/Makefile| 3 +-
drivers/gpu/drm/i915/display/i9xx_plane.c| 704 +++
drivers/gpu/drm/i915/display/i9xx_plane.h| 21 +
drivers/gpu/drm/i915/display/intel_display.c | 689 +-
drivers/gpu/drm/i915/display/intel_display.h | 4 -
drivers/gpu/drm/i915/display/intel_sprite.c | 1 +
6 files changed, 729 insertions(+), 693 deletions(-)
create mode 100644 drivers/gpu/drm/i915/display/i9xx_plane.c
create mode 100644 drivers/gpu/drm/i915/display/i9xx_plane.h
diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makefile
index b6558401691e..3f674725cd1c 100644
--- a/drivers/gpu/drm/i915/Makefile
+++ b/drivers/gpu/drm/i915/Makefile
@@ -216,7 +216,8 @@ i915-y += \
display/intel_quirks.o \
display/intel_sprite.o \
display/intel_tc.o \
- display/intel_vga.o
+ display/intel_vga.o \
+ display/i9xx_plane.o
i915-$(CONFIG_ACPI) += \
display/intel_acpi.o \
display/intel_opregion.o
diff --git a/drivers/gpu/drm/i915/display/i9xx_plane.c
b/drivers/gpu/drm/i915/display/i9xx_plane.c
new file mode 100644
index ..b78985c855a5
--- /dev/null
+++ b/drivers/gpu/drm/i915/display/i9xx_plane.c
@@ -0,0 +1,704 @@
+// SPDX-License-Identifier: MIT
+/*
+ * Copyright © 2020 Intel Corporation
+ */
+#include
+
+#include
+#include
+#include
+
+#include "intel_atomic.h"
+#include "intel_atomic_plane.h"
+#include "intel_display_types.h"
+#include "intel_sprite.h"
+#include "i9xx_plane.h"
+
+/* Primary plane formats for gen <= 3 */
+static const u32 i8xx_primary_formats[] = {
+ DRM_FORMAT_C8,
+ DRM_FORMAT_XRGB1555,
+ DRM_FORMAT_RGB565,
+ DRM_FORMAT_XRGB,
+};
+
+/* Primary plane formats for ivb (no fp16 due to hw issue) */
+static const u32 ivb_primary_formats[] = {
+ DRM_FORMAT_C8,
+ DRM_FORMAT_RGB565,
+ DRM_FORMAT_XRGB,
+ DRM_FORMAT_XBGR,
+ DRM_FORMAT_XRGB2101010,
+ DRM_FORMAT_XBGR2101010,
+};
+
+/* Primary plane formats for gen >= 4, except ivb */
+static const u32 i965_primary_formats[] = {
+ DRM_FORMAT_C8,
+ DRM_FORMAT_RGB565,
+ DRM_FORMAT_XRGB,
+ DRM_FORMAT_XBGR,
+ DRM_FORMAT_XRGB2101010,
+ DRM_FORMAT_XBGR2101010,
+ DRM_FORMAT_XBGR16161616F,
+};
+
+/* Primary plane formats for vlv/chv */
+static const u32 vlv_primary_formats[] = {
+ DRM_FORMAT_C8,
+ DRM_FORMAT_RGB565,
+ DRM_FORMAT_XRGB,
+ DRM_FORMAT_XBGR,
+ DRM_FORMAT_ARGB,
+ DRM_FORMAT_ABGR,
+ DRM_FORMAT_XRGB2101010,
+ DRM_FORMAT_XBGR2101010,
+ DRM_FORMAT_ARGB2101010,
+ DRM_FORMAT_ABGR2101010,
+ DRM_FORMAT_XBGR16161616F,
+};
+
+static const u64 i9xx_format_modifiers[] = {
+ I915_FORMAT_MOD_X_TILED,
+ DRM_FORMAT_MOD_LINEAR,
+ DRM_FORMAT_MOD_INVALID
+};
+
+static bool i8xx_plane_format_mod_supported(struct drm_plane *_plane,
+ u32 format, u64 modifier)
+{
+ switch (modifier) {
+ case DRM_FORMAT_MOD_LINEAR:
+ case I915_FORMAT_MOD_X_TILED:
+ break;
+ default:
+ return false;
+ }
+
+ switch (format) {
+ case DRM_FORMAT_C8:
+ case DRM_FORMAT_RGB565:
+ case DRM_FORMAT_XRGB1555:
+ case DRM_FORMAT_XRGB:
+ return modifier == DRM_FORMAT_MOD_LINEAR ||
+ modifier == I915_FORMAT_MOD_X_TILED;
+ default:
+ return false;
+ }
+}
+
+static bool i965_plane_format_mod_supported(struct drm_plane *_plane,
+ u32 format, u64 modifier)
+{
+ switch (modifier) {
+ case DRM_FORMAT_MOD_LINEAR:
+ case I915_FORMAT_MOD_X_TILED:
+ break;
+ default:
+ return false;
+ }
+
+ switch (format) {
+ case DRM_FORMAT_C8:
+ case DRM_FORMAT_RGB565:
+ case DRM_FORMAT_XRGB:
+ case DRM_FORMAT_XBGR:
+ case DRM_FORMAT_ARGB:
+ case DRM_FORMAT_ABGR:
+ case DRM_FORMAT_XRGB2101010:
+ case DRM_FORMAT_XBGR2101010:
+ case DRM_FORMAT_ARGB2101010:
+ case DRM_FORMAT_ABGR2101010:
+ case DRM_FORMAT_XBGR16161616F:
+ return modifier == DRM_FORMAT_MOD_LINEAR ||
+ modifier == I915_FORMAT_MOD_X_TILED;
+ default:
+ return false;
+ }
+}
+
+static bool i9xx_plane_has_fbc(struct drm_i915_private *dev_priv,
+ enum i9xx_plane_id i9xx_plane)
+{
+ if (!HAS_FBC(dev_priv))
+ return false;
+
+ if (IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv))
+ return i9xx_plane == PLANE_A; /* tied to pipe A */
+ else if (IS_IVYB
[Intel-gfx] [PATCH v2] drm/i915: refactor i915 plane code into separate file.
From: Dave Airlie
Ville suggested this as a good idea, let's move this before moving
the crtc code.
Signed-off-by: Dave Airlie
Reviewed-by: Ville Syrjälä
[Jani: fixed i915xx_plane.h standalone build.]
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/i915/Makefile| 3 +-
drivers/gpu/drm/i915/display/i9xx_plane.c| 704 +++
drivers/gpu/drm/i915/display/i9xx_plane.h| 24 +
drivers/gpu/drm/i915/display/intel_display.c | 689 +-
drivers/gpu/drm/i915/display/intel_display.h | 4 -
drivers/gpu/drm/i915/display/intel_sprite.c | 1 +
6 files changed, 732 insertions(+), 693 deletions(-)
create mode 100644 drivers/gpu/drm/i915/display/i9xx_plane.c
create mode 100644 drivers/gpu/drm/i915/display/i9xx_plane.h
diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makefile
index b6558401691e..3f674725cd1c 100644
--- a/drivers/gpu/drm/i915/Makefile
+++ b/drivers/gpu/drm/i915/Makefile
@@ -216,7 +216,8 @@ i915-y += \
display/intel_quirks.o \
display/intel_sprite.o \
display/intel_tc.o \
- display/intel_vga.o
+ display/intel_vga.o \
+ display/i9xx_plane.o
i915-$(CONFIG_ACPI) += \
display/intel_acpi.o \
display/intel_opregion.o
diff --git a/drivers/gpu/drm/i915/display/i9xx_plane.c
b/drivers/gpu/drm/i915/display/i9xx_plane.c
new file mode 100644
index ..b78985c855a5
--- /dev/null
+++ b/drivers/gpu/drm/i915/display/i9xx_plane.c
@@ -0,0 +1,704 @@
+// SPDX-License-Identifier: MIT
+/*
+ * Copyright © 2020 Intel Corporation
+ */
+#include
+
+#include
+#include
+#include
+
+#include "intel_atomic.h"
+#include "intel_atomic_plane.h"
+#include "intel_display_types.h"
+#include "intel_sprite.h"
+#include "i9xx_plane.h"
+
+/* Primary plane formats for gen <= 3 */
+static const u32 i8xx_primary_formats[] = {
+ DRM_FORMAT_C8,
+ DRM_FORMAT_XRGB1555,
+ DRM_FORMAT_RGB565,
+ DRM_FORMAT_XRGB,
+};
+
+/* Primary plane formats for ivb (no fp16 due to hw issue) */
+static const u32 ivb_primary_formats[] = {
+ DRM_FORMAT_C8,
+ DRM_FORMAT_RGB565,
+ DRM_FORMAT_XRGB,
+ DRM_FORMAT_XBGR,
+ DRM_FORMAT_XRGB2101010,
+ DRM_FORMAT_XBGR2101010,
+};
+
+/* Primary plane formats for gen >= 4, except ivb */
+static const u32 i965_primary_formats[] = {
+ DRM_FORMAT_C8,
+ DRM_FORMAT_RGB565,
+ DRM_FORMAT_XRGB,
+ DRM_FORMAT_XBGR,
+ DRM_FORMAT_XRGB2101010,
+ DRM_FORMAT_XBGR2101010,
+ DRM_FORMAT_XBGR16161616F,
+};
+
+/* Primary plane formats for vlv/chv */
+static const u32 vlv_primary_formats[] = {
+ DRM_FORMAT_C8,
+ DRM_FORMAT_RGB565,
+ DRM_FORMAT_XRGB,
+ DRM_FORMAT_XBGR,
+ DRM_FORMAT_ARGB,
+ DRM_FORMAT_ABGR,
+ DRM_FORMAT_XRGB2101010,
+ DRM_FORMAT_XBGR2101010,
+ DRM_FORMAT_ARGB2101010,
+ DRM_FORMAT_ABGR2101010,
+ DRM_FORMAT_XBGR16161616F,
+};
+
+static const u64 i9xx_format_modifiers[] = {
+ I915_FORMAT_MOD_X_TILED,
+ DRM_FORMAT_MOD_LINEAR,
+ DRM_FORMAT_MOD_INVALID
+};
+
+static bool i8xx_plane_format_mod_supported(struct drm_plane *_plane,
+ u32 format, u64 modifier)
+{
+ switch (modifier) {
+ case DRM_FORMAT_MOD_LINEAR:
+ case I915_FORMAT_MOD_X_TILED:
+ break;
+ default:
+ return false;
+ }
+
+ switch (format) {
+ case DRM_FORMAT_C8:
+ case DRM_FORMAT_RGB565:
+ case DRM_FORMAT_XRGB1555:
+ case DRM_FORMAT_XRGB:
+ return modifier == DRM_FORMAT_MOD_LINEAR ||
+ modifier == I915_FORMAT_MOD_X_TILED;
+ default:
+ return false;
+ }
+}
+
+static bool i965_plane_format_mod_supported(struct drm_plane *_plane,
+ u32 format, u64 modifier)
+{
+ switch (modifier) {
+ case DRM_FORMAT_MOD_LINEAR:
+ case I915_FORMAT_MOD_X_TILED:
+ break;
+ default:
+ return false;
+ }
+
+ switch (format) {
+ case DRM_FORMAT_C8:
+ case DRM_FORMAT_RGB565:
+ case DRM_FORMAT_XRGB:
+ case DRM_FORMAT_XBGR:
+ case DRM_FORMAT_ARGB:
+ case DRM_FORMAT_ABGR:
+ case DRM_FORMAT_XRGB2101010:
+ case DRM_FORMAT_XBGR2101010:
+ case DRM_FORMAT_ARGB2101010:
+ case DRM_FORMAT_ABGR2101010:
+ case DRM_FORMAT_XBGR16161616F:
+ return modifier == DRM_FORMAT_MOD_LINEAR ||
+ modifier == I915_FORMAT_MOD_X_TILED;
+ default:
+ return false;
+ }
+}
+
+static bool i9xx_plane_has_fbc(struct drm_i915_private *dev_priv,
+ enum i9xx_plane_id i9xx_plane)
+{
+ if (!HAS_FBC(dev_priv))
+ return false
Re: [Intel-gfx] Does the intel driver support faking a connected monitor?
On Sun, 20 Dec 2020, Paul Gardiner wrote: > The debug output was sufficient to track down the problem. It turned out > that the connection was called HDMI-A-1. When I used that name your > previous suggestion worked. To get exactly the behaviour I wanted I > needed to also load EDID. This is the extra boot command string I'm using: > > drm.edid_firmware=HDMI-A-1:edid/marantz_edid.bin video=HDMI-A-1:D > > > For that to work I also had to ensure the referenced edid file was in my > initramfs. > > Thanks again for the help. I'm glad you figured it out, and thanks for letting us know! > By the way, an EDID emulator is a small USB-stick-sized device that sits > in between computer and monitor and acts like a monitor when the actual > monitor is off. Ah, thanks for the info. BR, Jani. -- Jani Nikula, Intel Open Source Graphics Center ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [RFC v6] refactor intel display a bit more
On Mon, 21 Dec 2020, Dave Airlie wrote: > Okay the first 8 patches of this should probably get landed, they have > all the tags in place. Split out the first 5 to get CI results [1] and pushed them now. Patch 6 needs a rebase and/or backmerges. BR, Jani. [1] http://patchwork.freedesktop.org/patch/msgid/20201221090449.8288-1-jani.nik...@intel.com > > The subsequent patches have seen some rework: > Added a patch to move the buf_trans to a separate file as suggested > by Ville. I reworked some of the interfaces while doing so, but only > minorly. > > The skl planes code no long moves any scaler code. > > Some more ppl moving code, and a piece of forgotten i9xx plane moved. > > Dave. > > > ___ > Intel-gfx mailing list > Intel-gfx@lists.freedesktop.org > https://lists.freedesktop.org/mailman/listinfo/intel-gfx -- Jani Nikula, Intel Open Source Graphics Center ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 00/13] drm/i915/dp: split out pps and aux
Clean up intel_dp.c pre-emptively before Dave gets here. ;)
Split out pps and aux code to intel_pps.[ch] and intel_dp_aux.[ch],
respectively.
This reduces intel_dp.c size by 2k lines:
- 8370 drivers/gpu/drm/i915/display/intel_dp.c
+ 6313 drivers/gpu/drm/i915/display/intel_dp.c
The pps code is pretty messy, so I've first done almost pure code
movement, and added interface cleanups on top in smaller bits for easier
review. The patches can be squashed together, but I figured it's easier
this way. There's still room for improvement, but it's a good start to
move the code to a separate file.
BR,
Jani.
Jani Nikula (13):
drm/i915/pps: abstract panel power sequencer from intel_dp.c
drm/i915/pps: rename pps_{,un}lock -> intel_pps_{,un}lock
drm/i915/pps: rename intel_edp_backlight_* to intel_pps_backlight_*
drm/i915/pps: rename intel_edp_panel_* to intel_pps_*
drm/i915/pps: rename edp_panel_* to intel_pps_*_unlocked
drm/i915/pps: abstract intel_pps_vdd_off_sync
drm/i915/pps: add higher level intel_pps_init() call
drm/i915/pps: abstract intel_pps_reinit()
drm/i915/pps: rename intel_dp_check_edp to
intel_pps_check_power_unlocked
drm/i915/pps: rename intel_power_sequencer_reset to
intel_pps_reset_all
drm/i915/pps: add locked intel_pps_wait_power_cycle
drm/i915/pps: rename vlv_init_panel_power_sequencer to vlv_pps_init
drm/i915/dp: split out aux functionality to intel_dp_aux.c
drivers/gpu/drm/i915/Makefile |2 +
drivers/gpu/drm/i915/display/intel_ddi.c |9 +-
.../drm/i915/display/intel_display_power.c|6 +-
drivers/gpu/drm/i915/display/intel_dp.c | 2235 +
drivers/gpu/drm/i915/display/intel_dp.h |5 +-
drivers/gpu/drm/i915/display/intel_dp_aux.c | 683 +
drivers/gpu/drm/i915/display/intel_dp_aux.h | 18 +
drivers/gpu/drm/i915/display/intel_pps.c | 1393 ++
drivers/gpu/drm/i915/display/intel_pps.h | 49 +
9 files changed, 2243 insertions(+), 2157 deletions(-)
create mode 100644 drivers/gpu/drm/i915/display/intel_dp_aux.c
create mode 100644 drivers/gpu/drm/i915/display/intel_dp_aux.h
create mode 100644 drivers/gpu/drm/i915/display/intel_pps.c
create mode 100644 drivers/gpu/drm/i915/display/intel_pps.h
--
2.20.1
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 02/13] drm/i915/pps: rename pps_{, un}lock -> intel_pps_{, un}lock
Start following the usual naming pattern for functions.
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/i915/display/intel_dp.c | 20 ++--
drivers/gpu/drm/i915/display/intel_pps.c | 21 +++--
drivers/gpu/drm/i915/display/intel_pps.h | 8
3 files changed, 25 insertions(+), 24 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c
b/drivers/gpu/drm/i915/display/intel_dp.c
index d4760c478653..0870872fb594 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -1030,7 +1030,7 @@ intel_dp_aux_xfer(struct intel_dp *intel_dp,
aux_domain = intel_aux_power_domain(dig_port);
aux_wakeref = intel_display_power_get(i915, aux_domain);
- pps_wakeref = pps_lock(intel_dp);
+ pps_wakeref = intel_pps_lock(intel_dp);
/*
* We will be called with VDD already enabled for dpcd/edid/oui reads.
@@ -1182,7 +1182,7 @@ intel_dp_aux_xfer(struct intel_dp *intel_dp,
if (vdd)
edp_panel_vdd_off(intel_dp, false);
- pps_unlock(intel_dp, pps_wakeref);
+ intel_pps_unlock(intel_dp, pps_wakeref);
intel_display_power_put_async(i915, aux_domain, aux_wakeref);
if (is_tc_port)
@@ -3153,7 +3153,7 @@ static void intel_enable_dp(struct intel_atomic_state
*state,
if (drm_WARN_ON(&dev_priv->drm, dp_reg & DP_PORT_EN))
return;
- with_pps_lock(intel_dp, wakeref) {
+ with_intel_pps_lock(intel_dp, wakeref) {
if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
vlv_init_panel_power_sequencer(encoder, pipe_config);
@@ -3719,7 +3719,7 @@ intel_dp_link_down(struct intel_encoder *encoder,
if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
intel_wakeref_t wakeref;
- with_pps_lock(intel_dp, wakeref)
+ with_intel_pps_lock(intel_dp, wakeref)
intel_dp->active_pipe = INVALID_PIPE;
}
}
@@ -5817,7 +5817,7 @@ void intel_dp_encoder_flush_work(struct drm_encoder
*encoder)
* vdd might still be enabled do to the delayed vdd off.
* Make sure vdd is actually turned off here.
*/
- with_pps_lock(intel_dp, wakeref)
+ with_intel_pps_lock(intel_dp, wakeref)
edp_panel_vdd_off_sync(intel_dp);
}
@@ -5845,7 +5845,7 @@ void intel_dp_encoder_suspend(struct intel_encoder
*intel_encoder)
* Make sure vdd is actually turned off here.
*/
cancel_delayed_work_sync(&intel_dp->panel_vdd_work);
- with_pps_lock(intel_dp, wakeref)
+ with_intel_pps_lock(intel_dp, wakeref)
edp_panel_vdd_off_sync(intel_dp);
}
@@ -5857,7 +5857,7 @@ void intel_dp_encoder_shutdown(struct intel_encoder
*intel_encoder)
if (!intel_dp_is_edp(intel_dp))
return;
- with_pps_lock(intel_dp, wakeref)
+ with_intel_pps_lock(intel_dp, wakeref)
wait_panel_power_cycle(intel_dp);
}
@@ -5889,7 +5889,7 @@ void intel_dp_encoder_reset(struct drm_encoder *encoder)
!intel_dp_is_edp(intel_dp))
return;
- with_pps_lock(intel_dp, wakeref) {
+ with_intel_pps_lock(intel_dp, wakeref) {
if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
intel_dp->active_pipe = vlv_active_pipe(intel_dp);
@@ -6628,7 +6628,7 @@ static bool intel_edp_init_connector(struct intel_dp
*intel_dp,
return false;
}
- with_pps_lock(intel_dp, wakeref) {
+ with_intel_pps_lock(intel_dp, wakeref) {
intel_dp_init_panel_power_timestamps(intel_dp);
intel_dp_pps_init(intel_dp);
intel_edp_panel_vdd_sanitize(intel_dp);
@@ -6705,7 +6705,7 @@ static bool intel_edp_init_connector(struct intel_dp
*intel_dp,
* vdd might still be enabled do to the delayed vdd off.
* Make sure vdd is actually turned off here.
*/
- with_pps_lock(intel_dp, wakeref)
+ with_intel_pps_lock(intel_dp, wakeref)
edp_panel_vdd_off_sync(intel_dp);
return false;
diff --git a/drivers/gpu/drm/i915/display/intel_pps.c
b/drivers/gpu/drm/i915/display/intel_pps.c
index cfe347076031..9b0c432552b7 100644
--- a/drivers/gpu/drm/i915/display/intel_pps.c
+++ b/drivers/gpu/drm/i915/display/intel_pps.c
@@ -16,7 +16,7 @@ static void
intel_dp_init_panel_power_sequencer_registers(struct intel_dp *intel_dp,
bool force_disable_vdd);
-intel_wakeref_t pps_lock(struct intel_dp *intel_dp)
+intel_wakeref_t intel_pps_lock(struct intel_dp *intel_dp)
{
struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
intel_wakeref_t wakeref;
@@ -33,7 +33,8 @@ intel_wakeref_t pps_lock(struct intel_dp *intel_dp
[Intel-gfx] [PATCH 03/13] drm/i915/pps: rename intel_edp_backlight_* to intel_pps_backlight_*
Follow the usual naming pattern for functions.
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/i915/display/intel_dp.c | 6 +++---
drivers/gpu/drm/i915/display/intel_pps.c | 10 +-
drivers/gpu/drm/i915/display/intel_pps.h | 6 +++---
3 files changed, 11 insertions(+), 11 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c
b/drivers/gpu/drm/i915/display/intel_dp.c
index 0870872fb594..9813fb7e109c 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -2536,7 +2536,7 @@ void intel_edp_backlight_on(const struct intel_crtc_state
*crtc_state,
drm_dbg_kms(&i915->drm, "\n");
intel_panel_enable_backlight(crtc_state, conn_state);
- _intel_edp_backlight_on(intel_dp);
+ intel_pps_backlight_on(intel_dp);
}
/* Disable backlight PP control and backlight PWM. */
@@ -2550,7 +2550,7 @@ void intel_edp_backlight_off(const struct
drm_connector_state *old_conn_state)
drm_dbg_kms(&i915->drm, "\n");
- _intel_edp_backlight_off(intel_dp);
+ intel_pps_backlight_off(intel_dp);
intel_panel_disable_backlight(old_conn_state);
}
@@ -6688,7 +6688,7 @@ static bool intel_edp_init_connector(struct intel_dp
*intel_dp,
}
intel_panel_init(&intel_connector->panel, fixed_mode, downclock_mode);
- intel_connector->panel.backlight.power = intel_edp_backlight_power;
+ intel_connector->panel.backlight.power = intel_pps_backlight_power;
intel_panel_setup_backlight(connector, pipe);
if (fixed_mode) {
diff --git a/drivers/gpu/drm/i915/display/intel_pps.c
b/drivers/gpu/drm/i915/display/intel_pps.c
index 9b0c432552b7..0edda87dee94 100644
--- a/drivers/gpu/drm/i915/display/intel_pps.c
+++ b/drivers/gpu/drm/i915/display/intel_pps.c
@@ -847,7 +847,7 @@ void intel_edp_panel_off(struct intel_dp *intel_dp)
}
/* Enable backlight in the panel power control. */
-void _intel_edp_backlight_on(struct intel_dp *intel_dp)
+void intel_pps_backlight_on(struct intel_dp *intel_dp)
{
struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
intel_wakeref_t wakeref;
@@ -873,7 +873,7 @@ void _intel_edp_backlight_on(struct intel_dp *intel_dp)
}
/* Disable backlight in the panel power control. */
-void _intel_edp_backlight_off(struct intel_dp *intel_dp)
+void intel_pps_backlight_off(struct intel_dp *intel_dp)
{
struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
intel_wakeref_t wakeref;
@@ -900,7 +900,7 @@ void _intel_edp_backlight_off(struct intel_dp *intel_dp)
* Hook for controlling the panel power control backlight through the bl_power
* sysfs attribute. Take care to handle multiple calls.
*/
-void intel_edp_backlight_power(struct intel_connector *connector, bool enable)
+void intel_pps_backlight_power(struct intel_connector *connector, bool enable)
{
struct drm_i915_private *i915 = to_i915(connector->base.dev);
struct intel_dp *intel_dp = intel_attached_dp(connector);
@@ -917,9 +917,9 @@ void intel_edp_backlight_power(struct intel_connector
*connector, bool enable)
enable ? "enable" : "disable");
if (enable)
- _intel_edp_backlight_on(intel_dp);
+ intel_pps_backlight_on(intel_dp);
else
- _intel_edp_backlight_off(intel_dp);
+ intel_pps_backlight_off(intel_dp);
}
static void vlv_detach_power_sequencer(struct intel_dp *intel_dp)
diff --git a/drivers/gpu/drm/i915/display/intel_pps.h
b/drivers/gpu/drm/i915/display/intel_pps.h
index f44e6ce9e8c1..81e4e9fc3cf5 100644
--- a/drivers/gpu/drm/i915/display/intel_pps.h
+++ b/drivers/gpu/drm/i915/display/intel_pps.h
@@ -23,9 +23,9 @@ intel_wakeref_t intel_pps_unlock(struct intel_dp *intel_dp,
intel_wakeref_t wake
for ((wf) = intel_pps_lock(dp); (wf); (wf) = intel_pps_unlock((dp),
(wf)))
void intel_dp_check_edp(struct intel_dp *intel_dp);
-void _intel_edp_backlight_on(struct intel_dp *intel_dp);
-void _intel_edp_backlight_off(struct intel_dp *intel_dp);
-void intel_edp_backlight_power(struct intel_connector *connector, bool enable);
+void intel_pps_backlight_on(struct intel_dp *intel_dp);
+void intel_pps_backlight_off(struct intel_dp *intel_dp);
+void intel_pps_backlight_power(struct intel_connector *connector, bool enable);
bool edp_panel_vdd_on(struct intel_dp *intel_dp);
void edp_panel_vdd_off(struct intel_dp *intel_dp, bool sync);
--
2.20.1
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 04/13] drm/i915/pps: rename intel_edp_panel_* to intel_pps_*
Follow the usual naming pattern for functions. We don't need to repeat
"panel" here.
Follow the usual naming pattern for functions.
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/i915/display/intel_ddi.c | 8
drivers/gpu/drm/i915/display/intel_dp.c | 10 +-
drivers/gpu/drm/i915/display/intel_pps.c | 18 +-
drivers/gpu/drm/i915/display/intel_pps.h | 11 +--
4 files changed, 23 insertions(+), 24 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c
b/drivers/gpu/drm/i915/display/intel_ddi.c
index 9ddbe8b8730b..83300ee8c3fd 100644
--- a/drivers/gpu/drm/i915/display/intel_ddi.c
+++ b/drivers/gpu/drm/i915/display/intel_ddi.c
@@ -3556,7 +3556,7 @@ static void tgl_ddi_pre_enable_dp(struct
intel_atomic_state *state,
*/
/* 2. Enable Panel Power if PPS is required */
- intel_edp_panel_on(intel_dp);
+ intel_pps_on(intel_dp);
/*
* 3. For non-TBT Type-C ports, set FIA lane count
@@ -3695,7 +3695,7 @@ static void hsw_ddi_pre_enable_dp(struct
intel_atomic_state *state,
crtc_state->port_clock,
crtc_state->lane_count);
- intel_edp_panel_on(intel_dp);
+ intel_pps_on(intel_dp);
intel_ddi_clk_select(encoder, crtc_state);
@@ -3937,8 +3937,8 @@ static void intel_ddi_post_disable_dp(struct
intel_atomic_state *state,
if (INTEL_GEN(dev_priv) >= 12)
intel_ddi_disable_pipe_clock(old_crtc_state);
- intel_edp_panel_vdd_on(intel_dp);
- intel_edp_panel_off(intel_dp);
+ intel_pps_vdd_on(intel_dp);
+ intel_pps_off(intel_dp);
if (!intel_phy_is_tc(dev_priv, phy) ||
dig_port->tc_mode != TC_PORT_TBT_ALT)
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c
b/drivers/gpu/drm/i915/display/intel_dp.c
index 9813fb7e109c..2052ee228077 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -2947,10 +2947,10 @@ static void intel_disable_dp(struct intel_atomic_state
*state,
/* Make sure the panel is off before trying to change the mode. But also
* ensure that we have vdd while we switch off the panel. */
- intel_edp_panel_vdd_on(intel_dp);
+ intel_pps_vdd_on(intel_dp);
intel_edp_backlight_off(old_conn_state);
intel_dp_set_power(intel_dp, DP_SET_POWER_D3);
- intel_edp_panel_off(intel_dp);
+ intel_pps_off(intel_dp);
}
static void g4x_disable_dp(struct intel_atomic_state *state,
@@ -5899,7 +5899,7 @@ void intel_dp_encoder_reset(struct drm_encoder *encoder)
* something nasty with it.
*/
intel_dp_pps_init(intel_dp);
- intel_edp_panel_vdd_sanitize(intel_dp);
+ intel_pps_vdd_sanitize(intel_dp);
}
}
}
@@ -6073,7 +6073,7 @@ intel_dp_hpd_pulse(struct intel_digital_port *dig_port,
bool long_hpd)
struct intel_dp *intel_dp = &dig_port->dp;
if (dig_port->base.type == INTEL_OUTPUT_EDP &&
- (long_hpd || !intel_edp_have_power(intel_dp))) {
+ (long_hpd || !intel_pps_have_power(intel_dp))) {
/*
* vdd off can generate a long/short pulse on eDP which
* would require vdd on to handle it, and thus we
@@ -6631,7 +6631,7 @@ static bool intel_edp_init_connector(struct intel_dp
*intel_dp,
with_intel_pps_lock(intel_dp, wakeref) {
intel_dp_init_panel_power_timestamps(intel_dp);
intel_dp_pps_init(intel_dp);
- intel_edp_panel_vdd_sanitize(intel_dp);
+ intel_pps_vdd_sanitize(intel_dp);
}
/* Cache DPCD and EDID for edp. */
diff --git a/drivers/gpu/drm/i915/display/intel_pps.c
b/drivers/gpu/drm/i915/display/intel_pps.c
index 0edda87dee94..1f8ea3c41440 100644
--- a/drivers/gpu/drm/i915/display/intel_pps.c
+++ b/drivers/gpu/drm/i915/display/intel_pps.c
@@ -561,7 +561,7 @@ static u32 ilk_get_pp_control(struct intel_dp *intel_dp)
/*
* Must be paired with edp_panel_vdd_off().
* Must hold pps_mutex around the whole on/off sequence.
- * Can be nested with intel_edp_panel_vdd_{on,off}() calls.
+ * Can be nested with intel_pps_vdd_{on,off}() calls.
*/
bool edp_panel_vdd_on(struct intel_dp *intel_dp)
{
@@ -619,13 +619,13 @@ bool edp_panel_vdd_on(struct intel_dp *intel_dp)
}
/*
- * Must be paired with intel_edp_panel_vdd_off() or
- * intel_edp_panel_off().
+ * Must be paired with intel_pps_vdd_off() or
+ * intel_pps_off().
* Nested calls to these functions are not allowed since
* we drop the lock. Caller must use some higher level
* locking to prevent nested calls from other threads.
*/
-void intel_edp_panel_vdd_on(struct intel_dp *intel_dp)
+void intel_pps_vdd_on(struct intel_dp *intel_dp)
{
intel_wakeref_t wakeref;
[Intel-gfx] [PATCH 06/13] drm/i915/pps: abstract intel_pps_vdd_off_sync
Add a locked version of intel_pps_vdd_off_sync_unlocked() that does
everything the callers expect it to.
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/i915/display/intel_dp.c | 31 +++-
drivers/gpu/drm/i915/display/intel_pps.c | 17 -
drivers/gpu/drm/i915/display/intel_pps.h | 2 +-
3 files changed, 20 insertions(+), 30 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c
b/drivers/gpu/drm/i915/display/intel_dp.c
index f2794cc4292a..1a34c9351c30 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -5809,17 +5809,8 @@ void intel_dp_encoder_flush_work(struct drm_encoder
*encoder)
struct intel_dp *intel_dp = &dig_port->dp;
intel_dp_mst_encoder_cleanup(dig_port);
- if (intel_dp_is_edp(intel_dp)) {
- intel_wakeref_t wakeref;
- cancel_delayed_work_sync(&intel_dp->panel_vdd_work);
- /*
-* vdd might still be enabled do to the delayed vdd off.
-* Make sure vdd is actually turned off here.
-*/
- with_intel_pps_lock(intel_dp, wakeref)
- intel_pps_vdd_off_sync_unlocked(intel_dp);
- }
+ intel_pps_vdd_off_sync(intel_dp);
intel_dp_aux_fini(intel_dp);
}
@@ -5835,18 +5826,8 @@ static void intel_dp_encoder_destroy(struct drm_encoder
*encoder)
void intel_dp_encoder_suspend(struct intel_encoder *intel_encoder)
{
struct intel_dp *intel_dp = enc_to_intel_dp(intel_encoder);
- intel_wakeref_t wakeref;
-
- if (!intel_dp_is_edp(intel_dp))
- return;
- /*
-* vdd might still be enabled do to the delayed vdd off.
-* Make sure vdd is actually turned off here.
-*/
- cancel_delayed_work_sync(&intel_dp->panel_vdd_work);
- with_intel_pps_lock(intel_dp, wakeref)
- intel_pps_vdd_off_sync_unlocked(intel_dp);
+ intel_pps_vdd_off_sync(intel_dp);
}
void intel_dp_encoder_shutdown(struct intel_encoder *intel_encoder)
@@ -6700,13 +6681,7 @@ static bool intel_edp_init_connector(struct intel_dp
*intel_dp,
return true;
out_vdd_off:
- cancel_delayed_work_sync(&intel_dp->panel_vdd_work);
- /*
-* vdd might still be enabled do to the delayed vdd off.
-* Make sure vdd is actually turned off here.
-*/
- with_intel_pps_lock(intel_dp, wakeref)
- intel_pps_vdd_off_sync_unlocked(intel_dp);
+ intel_pps_vdd_off_sync(intel_dp);
return false;
}
diff --git a/drivers/gpu/drm/i915/display/intel_pps.c
b/drivers/gpu/drm/i915/display/intel_pps.c
index 01c9e69f4e3a..acd6d0092bc6 100644
--- a/drivers/gpu/drm/i915/display/intel_pps.c
+++ b/drivers/gpu/drm/i915/display/intel_pps.c
@@ -641,7 +641,7 @@ void intel_pps_vdd_on(struct intel_dp *intel_dp)
dp_to_dig_port(intel_dp)->base.base.name);
}
-void intel_pps_vdd_off_sync_unlocked(struct intel_dp *intel_dp)
+static void intel_pps_vdd_off_sync_unlocked(struct intel_dp *intel_dp)
{
struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
struct intel_digital_port *dig_port =
@@ -682,6 +682,21 @@ void intel_pps_vdd_off_sync_unlocked(struct intel_dp
*intel_dp)
fetch_and_zero(&intel_dp->vdd_wakeref));
}
+void intel_pps_vdd_off_sync(struct intel_dp *intel_dp)
+{
+ intel_wakeref_t wakeref;
+ if (!intel_dp_is_edp(intel_dp))
+ return;
+
+ cancel_delayed_work_sync(&intel_dp->panel_vdd_work);
+ /*
+* vdd might still be enabled do to the delayed vdd off.
+* Make sure vdd is actually turned off here.
+*/
+ with_intel_pps_lock(intel_dp, wakeref)
+ intel_pps_vdd_off_sync_unlocked(intel_dp);
+}
+
void edp_panel_vdd_work(struct work_struct *__work)
{
struct intel_dp *intel_dp =
diff --git a/drivers/gpu/drm/i915/display/intel_pps.h
b/drivers/gpu/drm/i915/display/intel_pps.h
index e7f0473be9a7..3cab183658c6 100644
--- a/drivers/gpu/drm/i915/display/intel_pps.h
+++ b/drivers/gpu/drm/i915/display/intel_pps.h
@@ -29,7 +29,6 @@ void intel_pps_backlight_power(struct intel_connector
*connector, bool enable);
bool intel_pps_vdd_on_unlocked(struct intel_dp *intel_dp);
void intel_pps_vdd_off_unlocked(struct intel_dp *intel_dp, bool sync);
-void intel_pps_vdd_off_sync_unlocked(struct intel_dp *intel_dp);
void intel_pps_on_unlocked(struct intel_dp *intel_dp);
void intel_pps_off_unlocked(struct intel_dp *intel_dp);
void edp_panel_vdd_work(struct work_struct *__work);
@@ -38,6 +37,7 @@ void intel_pps_vdd_sanitize(struct intel_dp *intel_dp);
void intel_pps_vdd_on(struct intel_dp *intel_dp);
void intel_pps_on(struct intel_dp *intel_dp);
void intel_pps_off(struct intel_dp *intel_dp);
+void intel_pps_vdd_off_sync(struct intel_dp *intel_dp);
bool intel_pps_h
[Intel-gfx] [PATCH 07/13] drm/i915/pps: add higher level intel_pps_init() call
Add a new init call to be called only once, unlike some of the other
various init calls. This lets us hide more functions within intel_pps.c.
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/i915/display/intel_dp.c | 9 +
drivers/gpu/drm/i915/display/intel_pps.c | 17 +++--
drivers/gpu/drm/i915/display/intel_pps.h | 3 +--
3 files changed, 17 insertions(+), 12 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c
b/drivers/gpu/drm/i915/display/intel_dp.c
index 1a34c9351c30..de2642d5be3b 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -6586,14 +6586,11 @@ static bool intel_edp_init_connector(struct intel_dp
*intel_dp,
struct drm_display_mode *downclock_mode = NULL;
bool has_dpcd;
enum pipe pipe = INVALID_PIPE;
- intel_wakeref_t wakeref;
struct edid *edid;
if (!intel_dp_is_edp(intel_dp))
return true;
- INIT_DELAYED_WORK(&intel_dp->panel_vdd_work, edp_panel_vdd_work);
-
/*
* On IBX/CPT we may get here with LVDS already registered. Since the
* driver uses the only internal power sequencer available for both
@@ -6609,11 +6606,7 @@ static bool intel_edp_init_connector(struct intel_dp
*intel_dp,
return false;
}
- with_intel_pps_lock(intel_dp, wakeref) {
- intel_dp_init_panel_power_timestamps(intel_dp);
- intel_dp_pps_init(intel_dp);
- intel_pps_vdd_sanitize(intel_dp);
- }
+ intel_pps_init(intel_dp);
/* Cache DPCD and EDID for edp. */
has_dpcd = intel_edp_init_dpcd(intel_dp);
diff --git a/drivers/gpu/drm/i915/display/intel_pps.c
b/drivers/gpu/drm/i915/display/intel_pps.c
index acd6d0092bc6..651c79ce4bdd 100644
--- a/drivers/gpu/drm/i915/display/intel_pps.c
+++ b/drivers/gpu/drm/i915/display/intel_pps.c
@@ -697,7 +697,7 @@ void intel_pps_vdd_off_sync(struct intel_dp *intel_dp)
intel_pps_vdd_off_sync_unlocked(intel_dp);
}
-void edp_panel_vdd_work(struct work_struct *__work)
+static void edp_panel_vdd_work(struct work_struct *__work)
{
struct intel_dp *intel_dp =
container_of(to_delayed_work(__work),
@@ -1081,7 +1081,7 @@ bool intel_pps_have_power(struct intel_dp *intel_dp)
return have_power;
}
-void intel_dp_init_panel_power_timestamps(struct intel_dp *intel_dp)
+static void intel_dp_init_panel_power_timestamps(struct intel_dp *intel_dp)
{
intel_dp->panel_power_off_time = ktime_get_boottime();
intel_dp->last_power_on = jiffies;
@@ -1351,3 +1351,16 @@ void intel_dp_pps_init(struct intel_dp *intel_dp)
intel_dp_init_panel_power_sequencer_registers(intel_dp, false);
}
}
+
+void intel_pps_init(struct intel_dp *intel_dp)
+{
+ intel_wakeref_t wakeref;
+
+ INIT_DELAYED_WORK(&intel_dp->panel_vdd_work, edp_panel_vdd_work);
+
+ with_intel_pps_lock(intel_dp, wakeref) {
+ intel_dp_init_panel_power_timestamps(intel_dp);
+ intel_dp_pps_init(intel_dp);
+ intel_pps_vdd_sanitize(intel_dp);
+ }
+}
diff --git a/drivers/gpu/drm/i915/display/intel_pps.h
b/drivers/gpu/drm/i915/display/intel_pps.h
index 3cab183658c6..53c0fafd1440 100644
--- a/drivers/gpu/drm/i915/display/intel_pps.h
+++ b/drivers/gpu/drm/i915/display/intel_pps.h
@@ -31,7 +31,6 @@ bool intel_pps_vdd_on_unlocked(struct intel_dp *intel_dp);
void intel_pps_vdd_off_unlocked(struct intel_dp *intel_dp, bool sync);
void intel_pps_on_unlocked(struct intel_dp *intel_dp);
void intel_pps_off_unlocked(struct intel_dp *intel_dp);
-void edp_panel_vdd_work(struct work_struct *__work);
void intel_pps_vdd_sanitize(struct intel_dp *intel_dp);
void intel_pps_vdd_on(struct intel_dp *intel_dp);
@@ -42,9 +41,9 @@ bool intel_pps_have_power(struct intel_dp *intel_dp);
void wait_panel_power_cycle(struct intel_dp *intel_dp);
+void intel_pps_init(struct intel_dp *intel_dp);
void intel_dp_pps_init(struct intel_dp *intel_dp);
void intel_power_sequencer_reset(struct drm_i915_private *i915);
-void intel_dp_init_panel_power_timestamps(struct intel_dp *intel_dp);
void vlv_init_panel_power_sequencer(struct intel_encoder *encoder,
const struct intel_crtc_state *crtc_state);
--
2.20.1
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 09/13] drm/i915/pps: rename intel_dp_check_edp to intel_pps_check_power_unlocked
Follow the usual naming pattern for functions.
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/i915/display/intel_dp.c | 2 +-
drivers/gpu/drm/i915/display/intel_pps.c | 2 +-
drivers/gpu/drm/i915/display/intel_pps.h | 2 +-
3 files changed, 3 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c
b/drivers/gpu/drm/i915/display/intel_dp.c
index 334ba1775cd3..65406d4ccdbe 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -1046,7 +1046,7 @@ intel_dp_aux_xfer(struct intel_dp *intel_dp,
*/
cpu_latency_qos_update_request(&i915->pm_qos, 0);
- intel_dp_check_edp(intel_dp);
+ intel_pps_check_power_unlocked(intel_dp);
/* Try to wait for any previous AUX channel activity */
for (try = 0; try < 3; try++) {
diff --git a/drivers/gpu/drm/i915/display/intel_pps.c
b/drivers/gpu/drm/i915/display/intel_pps.c
index 3e62d1450682..dfd6722bc40e 100644
--- a/drivers/gpu/drm/i915/display/intel_pps.c
+++ b/drivers/gpu/drm/i915/display/intel_pps.c
@@ -431,7 +431,7 @@ static bool edp_have_panel_vdd(struct intel_dp *intel_dp)
return intel_de_read(dev_priv, _pp_ctrl_reg(intel_dp)) & EDP_FORCE_VDD;
}
-void intel_dp_check_edp(struct intel_dp *intel_dp)
+void intel_pps_check_power_unlocked(struct intel_dp *intel_dp)
{
struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
diff --git a/drivers/gpu/drm/i915/display/intel_pps.h
b/drivers/gpu/drm/i915/display/intel_pps.h
index 4780b59a59df..8dda282abd42 100644
--- a/drivers/gpu/drm/i915/display/intel_pps.h
+++ b/drivers/gpu/drm/i915/display/intel_pps.h
@@ -22,7 +22,6 @@ intel_wakeref_t intel_pps_unlock(struct intel_dp *intel_dp,
intel_wakeref_t wake
#define with_intel_pps_lock(dp, wf)
\
for ((wf) = intel_pps_lock(dp); (wf); (wf) = intel_pps_unlock((dp),
(wf)))
-void intel_dp_check_edp(struct intel_dp *intel_dp);
void intel_pps_backlight_on(struct intel_dp *intel_dp);
void intel_pps_backlight_off(struct intel_dp *intel_dp);
void intel_pps_backlight_power(struct intel_connector *connector, bool enable);
@@ -31,6 +30,7 @@ bool intel_pps_vdd_on_unlocked(struct intel_dp *intel_dp);
void intel_pps_vdd_off_unlocked(struct intel_dp *intel_dp, bool sync);
void intel_pps_on_unlocked(struct intel_dp *intel_dp);
void intel_pps_off_unlocked(struct intel_dp *intel_dp);
+void intel_pps_check_power_unlocked(struct intel_dp *intel_dp);
void intel_pps_vdd_on(struct intel_dp *intel_dp);
void intel_pps_on(struct intel_dp *intel_dp);
--
2.20.1
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 10/13] drm/i915/pps: rename intel_power_sequencer_reset to intel_pps_reset_all
Follow the usual naming pattern for functions. "reset all" because it
iterates over all DP encoders.
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/i915/display/intel_display_power.c | 4 ++--
drivers/gpu/drm/i915/display/intel_pps.c | 5 ++---
drivers/gpu/drm/i915/display/intel_pps.h | 2 +-
3 files changed, 5 insertions(+), 6 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c
b/drivers/gpu/drm/i915/display/intel_display_power.c
index a11bd8213df4..c11c37c65d86 100644
--- a/drivers/gpu/drm/i915/display/intel_display_power.c
+++ b/drivers/gpu/drm/i915/display/intel_display_power.c
@@ -936,7 +936,7 @@ static void bxt_enable_dc9(struct drm_i915_private
*dev_priv)
* because PPS registers are always on.
*/
if (!HAS_PCH_SPLIT(dev_priv))
- intel_power_sequencer_reset(dev_priv);
+ intel_pps_reset_all(dev_priv);
gen9_set_dc_state(dev_priv, DC_STATE_EN_DC9);
}
@@ -1446,7 +1446,7 @@ static void vlv_display_power_well_deinit(struct
drm_i915_private *dev_priv)
/* make sure we're done processing display irqs */
intel_synchronize_irq(dev_priv);
- intel_power_sequencer_reset(dev_priv);
+ intel_pps_reset_all(dev_priv);
/* Prevent us from re-enabling polling on accident in late suspend */
if (!dev_priv->drm.dev->power.is_suspended)
diff --git a/drivers/gpu/drm/i915/display/intel_pps.c
b/drivers/gpu/drm/i915/display/intel_pps.c
index dfd6722bc40e..ceb6de9e7aff 100644
--- a/drivers/gpu/drm/i915/display/intel_pps.c
+++ b/drivers/gpu/drm/i915/display/intel_pps.c
@@ -22,8 +22,7 @@ intel_wakeref_t intel_pps_lock(struct intel_dp *intel_dp)
intel_wakeref_t wakeref;
/*
-* See intel_power_sequencer_reset() why we need
-* a power domain reference here.
+* See intel_pps_reset_all() why we need a power domain reference here.
*/
wakeref = intel_display_power_get(dev_priv,
intel_aux_power_domain(dp_to_dig_port(intel_dp)));
@@ -316,7 +315,7 @@ vlv_initial_power_sequencer_setup(struct intel_dp *intel_dp)
intel_dp_init_panel_power_sequencer_registers(intel_dp, false);
}
-void intel_power_sequencer_reset(struct drm_i915_private *dev_priv)
+void intel_pps_reset_all(struct drm_i915_private *dev_priv)
{
struct intel_encoder *encoder;
diff --git a/drivers/gpu/drm/i915/display/intel_pps.h
b/drivers/gpu/drm/i915/display/intel_pps.h
index 8dda282abd42..451d5125b2b7 100644
--- a/drivers/gpu/drm/i915/display/intel_pps.h
+++ b/drivers/gpu/drm/i915/display/intel_pps.h
@@ -42,7 +42,7 @@ void wait_panel_power_cycle(struct intel_dp *intel_dp);
void intel_pps_init(struct intel_dp *intel_dp);
void intel_pps_reinit(struct intel_dp *intel_dp);
-void intel_power_sequencer_reset(struct drm_i915_private *i915);
+void intel_pps_reset_all(struct drm_i915_private *i915);
void vlv_init_panel_power_sequencer(struct intel_encoder *encoder,
const struct intel_crtc_state *crtc_state);
--
2.20.1
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 11/13] drm/i915/pps: add locked intel_pps_wait_power_cycle
Prefer keeping the unlocked variants hidden if possible.
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/i915/display/intel_dp.c | 7 +--
drivers/gpu/drm/i915/display/intel_pps.c | 13 -
drivers/gpu/drm/i915/display/intel_pps.h | 3 +--
3 files changed, 14 insertions(+), 9 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c
b/drivers/gpu/drm/i915/display/intel_dp.c
index 65406d4ccdbe..bc3a447f5992 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -5833,13 +5833,8 @@ void intel_dp_encoder_suspend(struct intel_encoder
*intel_encoder)
void intel_dp_encoder_shutdown(struct intel_encoder *intel_encoder)
{
struct intel_dp *intel_dp = enc_to_intel_dp(intel_encoder);
- intel_wakeref_t wakeref;
-
- if (!intel_dp_is_edp(intel_dp))
- return;
- with_intel_pps_lock(intel_dp, wakeref)
- wait_panel_power_cycle(intel_dp);
+ intel_pps_wait_power_cycle(intel_dp);
}
static enum pipe vlv_active_pipe(struct intel_dp *intel_dp)
diff --git a/drivers/gpu/drm/i915/display/intel_pps.c
b/drivers/gpu/drm/i915/display/intel_pps.c
index ceb6de9e7aff..ceb74967f2b4 100644
--- a/drivers/gpu/drm/i915/display/intel_pps.c
+++ b/drivers/gpu/drm/i915/display/intel_pps.c
@@ -503,7 +503,7 @@ static void wait_panel_off(struct intel_dp *intel_dp)
wait_panel_status(intel_dp, IDLE_OFF_MASK, IDLE_OFF_VALUE);
}
-void wait_panel_power_cycle(struct intel_dp *intel_dp)
+static void wait_panel_power_cycle(struct intel_dp *intel_dp)
{
struct drm_i915_private *i915 = dp_to_i915(intel_dp);
ktime_t panel_power_on_time;
@@ -525,6 +525,17 @@ void wait_panel_power_cycle(struct intel_dp *intel_dp)
wait_panel_status(intel_dp, IDLE_CYCLE_MASK, IDLE_CYCLE_VALUE);
}
+void intel_pps_wait_power_cycle(struct intel_dp *intel_dp)
+{
+ intel_wakeref_t wakeref;
+
+ if (!intel_dp_is_edp(intel_dp))
+ return;
+
+ with_intel_pps_lock(intel_dp, wakeref)
+ wait_panel_power_cycle(intel_dp);
+}
+
static void wait_backlight_on(struct intel_dp *intel_dp)
{
wait_remaining_ms_from_jiffies(intel_dp->last_power_on,
diff --git a/drivers/gpu/drm/i915/display/intel_pps.h
b/drivers/gpu/drm/i915/display/intel_pps.h
index 451d5125b2b7..c8766b777501 100644
--- a/drivers/gpu/drm/i915/display/intel_pps.h
+++ b/drivers/gpu/drm/i915/display/intel_pps.h
@@ -37,8 +37,7 @@ void intel_pps_on(struct intel_dp *intel_dp);
void intel_pps_off(struct intel_dp *intel_dp);
void intel_pps_vdd_off_sync(struct intel_dp *intel_dp);
bool intel_pps_have_power(struct intel_dp *intel_dp);
-
-void wait_panel_power_cycle(struct intel_dp *intel_dp);
+void intel_pps_wait_power_cycle(struct intel_dp *intel_dp);
void intel_pps_init(struct intel_dp *intel_dp);
void intel_pps_reinit(struct intel_dp *intel_dp);
--
2.20.1
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 08/13] drm/i915/pps: abstract intel_pps_reinit()
Add a "reinit" call to hide some more pps functions, and clean up the
callers. A minor functional change is not holding the pps lock across
the whole operation in intel_dp_encoder_reset, but instead doing it in
two steps.
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/i915/display/intel_dp.c | 20 +---
drivers/gpu/drm/i915/display/intel_pps.c | 21 +++--
drivers/gpu/drm/i915/display/intel_pps.h | 3 +--
3 files changed, 25 insertions(+), 19 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c
b/drivers/gpu/drm/i915/display/intel_dp.c
index de2642d5be3b..334ba1775cd3 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -5859,30 +5859,20 @@ void intel_dp_encoder_reset(struct drm_encoder *encoder)
{
struct drm_i915_private *dev_priv = to_i915(encoder->dev);
struct intel_dp *intel_dp = enc_to_intel_dp(to_intel_encoder(encoder));
- intel_wakeref_t wakeref;
if (!HAS_DDI(dev_priv))
intel_dp->DP = intel_de_read(dev_priv, intel_dp->output_reg);
intel_dp->reset_link_params = true;
- if (!IS_VALLEYVIEW(dev_priv) && !IS_CHERRYVIEW(dev_priv) &&
- !intel_dp_is_edp(intel_dp))
- return;
+ if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
+ intel_wakeref_t wakeref;
- with_intel_pps_lock(intel_dp, wakeref) {
- if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
+ with_intel_pps_lock(intel_dp, wakeref)
intel_dp->active_pipe = vlv_active_pipe(intel_dp);
-
- if (intel_dp_is_edp(intel_dp)) {
- /*
-* Reinit the power sequencer, in case BIOS did
-* something nasty with it.
-*/
- intel_dp_pps_init(intel_dp);
- intel_pps_vdd_sanitize(intel_dp);
- }
}
+
+ intel_pps_reinit(intel_dp);
}
static int intel_modeset_tile_group(struct intel_atomic_state *state,
diff --git a/drivers/gpu/drm/i915/display/intel_pps.c
b/drivers/gpu/drm/i915/display/intel_pps.c
index 651c79ce4bdd..3e62d1450682 100644
--- a/drivers/gpu/drm/i915/display/intel_pps.c
+++ b/drivers/gpu/drm/i915/display/intel_pps.c
@@ -1043,7 +1043,7 @@ void vlv_init_panel_power_sequencer(struct intel_encoder
*encoder,
intel_dp_init_panel_power_sequencer_registers(intel_dp, true);
}
-void intel_pps_vdd_sanitize(struct intel_dp *intel_dp)
+static void intel_pps_vdd_sanitize(struct intel_dp *intel_dp)
{
struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
@@ -1340,7 +1340,7 @@ intel_dp_init_panel_power_sequencer_registers(struct
intel_dp *intel_dp,
(intel_de_read(dev_priv, regs.pp_ctrl) &
BXT_POWER_CYCLE_DELAY_MASK));
}
-void intel_dp_pps_init(struct intel_dp *intel_dp)
+static void intel_dp_pps_init(struct intel_dp *intel_dp)
{
struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
@@ -1352,6 +1352,23 @@ void intel_dp_pps_init(struct intel_dp *intel_dp)
}
}
+void intel_pps_reinit(struct intel_dp *intel_dp)
+{
+ intel_wakeref_t wakeref;
+
+ if (!intel_dp_is_edp(intel_dp))
+ return;
+
+ with_intel_pps_lock(intel_dp, wakeref) {
+ /*
+* Reinit the power sequencer, in case BIOS did something nasty
+* with it.
+*/
+ intel_dp_pps_init(intel_dp);
+ intel_pps_vdd_sanitize(intel_dp);
+ }
+}
+
void intel_pps_init(struct intel_dp *intel_dp)
{
intel_wakeref_t wakeref;
diff --git a/drivers/gpu/drm/i915/display/intel_pps.h
b/drivers/gpu/drm/i915/display/intel_pps.h
index 53c0fafd1440..4780b59a59df 100644
--- a/drivers/gpu/drm/i915/display/intel_pps.h
+++ b/drivers/gpu/drm/i915/display/intel_pps.h
@@ -32,7 +32,6 @@ void intel_pps_vdd_off_unlocked(struct intel_dp *intel_dp,
bool sync);
void intel_pps_on_unlocked(struct intel_dp *intel_dp);
void intel_pps_off_unlocked(struct intel_dp *intel_dp);
-void intel_pps_vdd_sanitize(struct intel_dp *intel_dp);
void intel_pps_vdd_on(struct intel_dp *intel_dp);
void intel_pps_on(struct intel_dp *intel_dp);
void intel_pps_off(struct intel_dp *intel_dp);
@@ -42,7 +41,7 @@ bool intel_pps_have_power(struct intel_dp *intel_dp);
void wait_panel_power_cycle(struct intel_dp *intel_dp);
void intel_pps_init(struct intel_dp *intel_dp);
-void intel_dp_pps_init(struct intel_dp *intel_dp);
+void intel_pps_reinit(struct intel_dp *intel_dp);
void intel_power_sequencer_reset(struct drm_i915_private *i915);
void vlv_init_panel_power_sequencer(struct intel_encoder *encoder,
--
2.20.1
___
Intel-gfx mailing list
Intel-gfx@lists.freedesk
[Intel-gfx] [PATCH 12/13] drm/i915/pps: rename vlv_init_panel_power_sequencer to vlv_pps_init
This function is a bit of an outlier, but try to change to a name that
is more in line with the rest of the intel_pps functions.
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/i915/display/intel_dp.c | 2 +-
drivers/gpu/drm/i915/display/intel_pps.c | 4 ++--
drivers/gpu/drm/i915/display/intel_pps.h | 4 ++--
3 files changed, 5 insertions(+), 5 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c
b/drivers/gpu/drm/i915/display/intel_dp.c
index bc3a447f5992..c49ada31363b 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -3155,7 +3155,7 @@ static void intel_enable_dp(struct intel_atomic_state
*state,
with_intel_pps_lock(intel_dp, wakeref) {
if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
- vlv_init_panel_power_sequencer(encoder, pipe_config);
+ vlv_pps_init(encoder, pipe_config);
intel_dp_enable_port(intel_dp, pipe_config);
diff --git a/drivers/gpu/drm/i915/display/intel_pps.c
b/drivers/gpu/drm/i915/display/intel_pps.c
index ceb74967f2b4..492abf372167 100644
--- a/drivers/gpu/drm/i915/display/intel_pps.c
+++ b/drivers/gpu/drm/i915/display/intel_pps.c
@@ -1008,8 +1008,8 @@ static void vlv_steal_power_sequencer(struct
drm_i915_private *dev_priv,
}
}
-void vlv_init_panel_power_sequencer(struct intel_encoder *encoder,
- const struct intel_crtc_state *crtc_state)
+void vlv_pps_init(struct intel_encoder *encoder,
+ const struct intel_crtc_state *crtc_state)
{
struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
diff --git a/drivers/gpu/drm/i915/display/intel_pps.h
b/drivers/gpu/drm/i915/display/intel_pps.h
index c8766b777501..d9cd57b5b828 100644
--- a/drivers/gpu/drm/i915/display/intel_pps.h
+++ b/drivers/gpu/drm/i915/display/intel_pps.h
@@ -43,7 +43,7 @@ void intel_pps_init(struct intel_dp *intel_dp);
void intel_pps_reinit(struct intel_dp *intel_dp);
void intel_pps_reset_all(struct drm_i915_private *i915);
-void vlv_init_panel_power_sequencer(struct intel_encoder *encoder,
- const struct intel_crtc_state *crtc_state);
+void vlv_pps_init(struct intel_encoder *encoder,
+ const struct intel_crtc_state *crtc_state);
#endif /* __INTEL_PPS_H__ */
--
2.20.1
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 13/13] drm/i915/dp: split out aux functionality to intel_dp_aux.c
Split out the DP aux functionality to a new intel_dp_aux.[ch]. This is a
surprisingly clean cut.
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/i915/Makefile | 1 +
drivers/gpu/drm/i915/display/intel_dp.c | 676 +--
drivers/gpu/drm/i915/display/intel_dp_aux.c | 683
drivers/gpu/drm/i915/display/intel_dp_aux.h | 18 +
4 files changed, 703 insertions(+), 675 deletions(-)
create mode 100644 drivers/gpu/drm/i915/display/intel_dp_aux.c
create mode 100644 drivers/gpu/drm/i915/display/intel_dp_aux.h
diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makefile
index 1e26902a86e5..c5cafaea7527 100644
--- a/drivers/gpu/drm/i915/Makefile
+++ b/drivers/gpu/drm/i915/Makefile
@@ -237,6 +237,7 @@ i915-y += \
display/intel_crt.o \
display/intel_ddi.o \
display/intel_dp.o \
+ display/intel_dp_aux.o \
display/intel_dp_aux_backlight.o \
display/intel_dp_hdcp.o \
display/intel_dp_link_training.o \
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c
b/drivers/gpu/drm/i915/display/intel_dp.c
index c49ada31363b..86cb7671ebf4 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -41,13 +41,13 @@
#include "i915_debugfs.h"
#include "i915_drv.h"
-#include "i915_trace.h"
#include "intel_atomic.h"
#include "intel_audio.h"
#include "intel_connector.h"
#include "intel_ddi.h"
#include "intel_display_types.h"
#include "intel_dp.h"
+#include "intel_dp_aux.h"
#include "intel_dp_link_training.h"
#include "intel_dp_mst.h"
#include "intel_dpio_phy.h"
@@ -833,680 +833,6 @@ intel_dp_mode_valid(struct drm_connector *connector,
return intel_mode_valid_max_plane_size(dev_priv, mode, bigjoiner);
}
-u32 intel_dp_pack_aux(const u8 *src, int src_bytes)
-{
- int i;
- u32 v = 0;
-
- if (src_bytes > 4)
- src_bytes = 4;
- for (i = 0; i < src_bytes; i++)
- v |= ((u32)src[i]) << ((3 - i) * 8);
- return v;
-}
-
-static void intel_dp_unpack_aux(u32 src, u8 *dst, int dst_bytes)
-{
- int i;
- if (dst_bytes > 4)
- dst_bytes = 4;
- for (i = 0; i < dst_bytes; i++)
- dst[i] = src >> ((3-i) * 8);
-}
-
-static u32
-intel_dp_aux_wait_done(struct intel_dp *intel_dp)
-{
- struct drm_i915_private *i915 = dp_to_i915(intel_dp);
- i915_reg_t ch_ctl = intel_dp->aux_ch_ctl_reg(intel_dp);
- const unsigned int timeout_ms = 10;
- u32 status;
- bool done;
-
-#define C (((status = intel_uncore_read_notrace(&i915->uncore, ch_ctl)) &
DP_AUX_CH_CTL_SEND_BUSY) == 0)
- done = wait_event_timeout(i915->gmbus_wait_queue, C,
- msecs_to_jiffies_timeout(timeout_ms));
-
- /* just trace the final value */
- trace_i915_reg_rw(false, ch_ctl, status, sizeof(status), true);
-
- if (!done)
- drm_err(&i915->drm,
- "%s: did not complete or timeout within %ums (status
0x%08x)\n",
- intel_dp->aux.name, timeout_ms, status);
-#undef C
-
- return status;
-}
-
-static u32 g4x_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
-{
- struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
-
- if (index)
- return 0;
-
- /*
-* The clock divider is based off the hrawclk, and would like to run at
-* 2MHz. So, take the hrawclk value and divide by 2000 and use that
-*/
- return DIV_ROUND_CLOSEST(RUNTIME_INFO(dev_priv)->rawclk_freq, 2000);
-}
-
-static u32 ilk_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
-{
- struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
- struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
- u32 freq;
-
- if (index)
- return 0;
-
- /*
-* The clock divider is based off the cdclk or PCH rawclk, and would
-* like to run at 2MHz. So, take the cdclk or PCH rawclk value and
-* divide by 2000 and use that
-*/
- if (dig_port->aux_ch == AUX_CH_A)
- freq = dev_priv->cdclk.hw.cdclk;
- else
- freq = RUNTIME_INFO(dev_priv)->rawclk_freq;
- return DIV_ROUND_CLOSEST(freq, 2000);
-}
-
-static u32 hsw_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
-{
- struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
- struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
-
- if (dig_port->aux_ch != AUX_CH_A && HAS_PCH_LPT_H(dev_priv)) {
- /* Workaround for non-ULT HSW */
- switch (index) {
- case 0: return 63;
- case 1:
[Intel-gfx] [PATCH 01/13] drm/i915/pps: abstract panel power sequencer from intel_dp.c
In a long overdue refactoring, split out all panel sequencer code from
intel_dp.c to new intel_pps.[ch].
The first part is mostly just code movement as-is, without cleanups.
We need to add a vlv_get_dpll() helper to get at the vlv/chv dpll from
pps code.
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/i915/Makefile |1 +
drivers/gpu/drm/i915/display/intel_ddi.c |1 +
.../drm/i915/display/intel_display_power.c|2 +-
drivers/gpu/drm/i915/display/intel_dp.c | 1442 +
drivers/gpu/drm/i915/display/intel_dp.h |5 +-
drivers/gpu/drm/i915/display/intel_pps.c | 1337 +++
drivers/gpu/drm/i915/display/intel_pps.h | 53 +
7 files changed, 1447 insertions(+), 1394 deletions(-)
create mode 100644 drivers/gpu/drm/i915/display/intel_pps.c
create mode 100644 drivers/gpu/drm/i915/display/intel_pps.h
diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makefile
index 3a439b1d0496..1e26902a86e5 100644
--- a/drivers/gpu/drm/i915/Makefile
+++ b/drivers/gpu/drm/i915/Makefile
@@ -250,6 +250,7 @@ i915-y += \
display/intel_lspcon.o \
display/intel_lvds.o \
display/intel_panel.o \
+ display/intel_pps.o \
display/intel_sdvo.o \
display/intel_tv.o \
display/intel_vdsc.o \
diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c
b/drivers/gpu/drm/i915/display/intel_ddi.c
index 6863236df1d0..9ddbe8b8730b 100644
--- a/drivers/gpu/drm/i915/display/intel_ddi.c
+++ b/drivers/gpu/drm/i915/display/intel_ddi.c
@@ -46,6 +46,7 @@
#include "intel_hotplug.h"
#include "intel_lspcon.h"
#include "intel_panel.h"
+#include "intel_pps.h"
#include "intel_psr.h"
#include "intel_sprite.h"
#include "intel_tc.h"
diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c
b/drivers/gpu/drm/i915/display/intel_display_power.c
index d52374f01316..a11bd8213df4 100644
--- a/drivers/gpu/drm/i915/display/intel_display_power.c
+++ b/drivers/gpu/drm/i915/display/intel_display_power.c
@@ -4,7 +4,6 @@
*/
#include "display/intel_crt.h"
-#include "display/intel_dp.h"
#include "i915_drv.h"
#include "i915_irq.h"
@@ -16,6 +15,7 @@
#include "intel_dpio_phy.h"
#include "intel_hotplug.h"
#include "intel_pm.h"
+#include "intel_pps.h"
#include "intel_sideband.h"
#include "intel_tc.h"
#include "intel_vga.h"
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c
b/drivers/gpu/drm/i915/display/intel_dp.c
index b2bc0c8c39c7..d4760c478653 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -58,6 +58,7 @@
#include "intel_lspcon.h"
#include "intel_lvds.h"
#include "intel_panel.h"
+#include "intel_pps.h"
#include "intel_psr.h"
#include "intel_sideband.h"
#include "intel_tc.h"
@@ -121,6 +122,11 @@ static const struct dp_link_dpll chv_dpll[] = {
{ .p1 = 4, .p2 = 1, .n = 1, .m1 = 2, .m2 = 0x6c0 } },
};
+const struct dpll *vlv_get_dpll(struct drm_i915_private *i915)
+{
+ return IS_CHERRYVIEW(i915) ? &chv_dpll[0].dpll : &vlv_dpll[0].dpll;
+}
+
/* Constants for DP DSC configurations */
static const u8 valid_dsc_bpp[] = {6, 8, 10, 12, 15};
@@ -145,12 +151,6 @@ bool intel_dp_is_edp(struct intel_dp *intel_dp)
static void intel_dp_link_down(struct intel_encoder *encoder,
const struct intel_crtc_state *old_crtc_state);
-static bool edp_panel_vdd_on(struct intel_dp *intel_dp);
-static void edp_panel_vdd_off(struct intel_dp *intel_dp, bool sync);
-static void vlv_init_panel_power_sequencer(struct intel_encoder *encoder,
- const struct intel_crtc_state
*crtc_state);
-static void vlv_steal_power_sequencer(struct drm_i915_private *dev_priv,
- enum pipe pipe);
static void intel_dp_unset_edid(struct intel_dp *intel_dp);
/* update sink rates from dpcd */
@@ -854,451 +854,6 @@ static void intel_dp_unpack_aux(u32 src, u8 *dst, int
dst_bytes)
dst[i] = src >> ((3-i) * 8);
}
-static void
-intel_dp_init_panel_power_sequencer(struct intel_dp *intel_dp);
-static void
-intel_dp_init_panel_power_sequencer_registers(struct intel_dp *intel_dp,
- bool force_disable_vdd);
-static void
-intel_dp_pps_init(struct intel_dp *intel_dp);
-
-static intel_wakeref_t
-pps_lock(struct intel_dp *intel_dp)
-{
- struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
- intel_wakeref_t wakeref;
-
- /*
-* See intel_power_sequencer_reset() why we need
-* a power domain reference here.
-*/
- wakeref = intel_display_power_get(dev_priv,
-
[Intel-gfx] [PATCH 05/13] drm/i915/pps: rename edp_panel_* to intel_pps_*_unlocked
Follow the usual naming pattern for functions, both for the prefix and
the _unlocked suffix for functions that expect the lock to be held when
calling.
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/i915/display/intel_dp.c | 16 +++
drivers/gpu/drm/i915/display/intel_pps.c | 26
drivers/gpu/drm/i915/display/intel_pps.h | 10 -
3 files changed, 26 insertions(+), 26 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c
b/drivers/gpu/drm/i915/display/intel_dp.c
index 2052ee228077..f2794cc4292a 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -1038,7 +1038,7 @@ intel_dp_aux_xfer(struct intel_dp *intel_dp,
* to turn it off. But for eg. i2c-dev access we need to turn it on/off
* ourselves.
*/
- vdd = edp_panel_vdd_on(intel_dp);
+ vdd = intel_pps_vdd_on_unlocked(intel_dp);
/* dp aux is extremely sensitive to irq latency, hence request the
* lowest possible wakeup latency and so prevent the cpu from going into
@@ -1180,7 +1180,7 @@ intel_dp_aux_xfer(struct intel_dp *intel_dp,
cpu_latency_qos_update_request(&i915->pm_qos, PM_QOS_DEFAULT_VALUE);
if (vdd)
- edp_panel_vdd_off(intel_dp, false);
+ intel_pps_vdd_off_unlocked(intel_dp, false);
intel_pps_unlock(intel_dp, pps_wakeref);
intel_display_power_put_async(i915, aux_domain, aux_wakeref);
@@ -3159,9 +3159,9 @@ static void intel_enable_dp(struct intel_atomic_state
*state,
intel_dp_enable_port(intel_dp, pipe_config);
- edp_panel_vdd_on(intel_dp);
- edp_panel_on(intel_dp);
- edp_panel_vdd_off(intel_dp, true);
+ intel_pps_vdd_on_unlocked(intel_dp);
+ intel_pps_on_unlocked(intel_dp);
+ intel_pps_vdd_off_unlocked(intel_dp, true);
}
if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
@@ -5818,7 +5818,7 @@ void intel_dp_encoder_flush_work(struct drm_encoder
*encoder)
* Make sure vdd is actually turned off here.
*/
with_intel_pps_lock(intel_dp, wakeref)
- edp_panel_vdd_off_sync(intel_dp);
+ intel_pps_vdd_off_sync_unlocked(intel_dp);
}
intel_dp_aux_fini(intel_dp);
@@ -5846,7 +5846,7 @@ void intel_dp_encoder_suspend(struct intel_encoder
*intel_encoder)
*/
cancel_delayed_work_sync(&intel_dp->panel_vdd_work);
with_intel_pps_lock(intel_dp, wakeref)
- edp_panel_vdd_off_sync(intel_dp);
+ intel_pps_vdd_off_sync_unlocked(intel_dp);
}
void intel_dp_encoder_shutdown(struct intel_encoder *intel_encoder)
@@ -6706,7 +6706,7 @@ static bool intel_edp_init_connector(struct intel_dp
*intel_dp,
* Make sure vdd is actually turned off here.
*/
with_intel_pps_lock(intel_dp, wakeref)
- edp_panel_vdd_off_sync(intel_dp);
+ intel_pps_vdd_off_sync_unlocked(intel_dp);
return false;
}
diff --git a/drivers/gpu/drm/i915/display/intel_pps.c
b/drivers/gpu/drm/i915/display/intel_pps.c
index 1f8ea3c41440..01c9e69f4e3a 100644
--- a/drivers/gpu/drm/i915/display/intel_pps.c
+++ b/drivers/gpu/drm/i915/display/intel_pps.c
@@ -559,11 +559,11 @@ static u32 ilk_get_pp_control(struct intel_dp *intel_dp)
}
/*
- * Must be paired with edp_panel_vdd_off().
+ * Must be paired with intel_pps_vdd_off_unlocked().
* Must hold pps_mutex around the whole on/off sequence.
* Can be nested with intel_pps_vdd_{on,off}() calls.
*/
-bool edp_panel_vdd_on(struct intel_dp *intel_dp)
+bool intel_pps_vdd_on_unlocked(struct intel_dp *intel_dp)
{
struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
@@ -635,13 +635,13 @@ void intel_pps_vdd_on(struct intel_dp *intel_dp)
vdd = false;
with_intel_pps_lock(intel_dp, wakeref)
- vdd = edp_panel_vdd_on(intel_dp);
+ vdd = intel_pps_vdd_on_unlocked(intel_dp);
I915_STATE_WARN(!vdd, "[ENCODER:%d:%s] VDD already requested on\n",
dp_to_dig_port(intel_dp)->base.base.base.id,
dp_to_dig_port(intel_dp)->base.base.name);
}
-void edp_panel_vdd_off_sync(struct intel_dp *intel_dp)
+void intel_pps_vdd_off_sync_unlocked(struct intel_dp *intel_dp)
{
struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
struct intel_digital_port *dig_port =
@@ -691,7 +691,7 @@ void edp_panel_vdd_work(struct work_struct *__work)
with_intel_pps_lock(intel_dp, wakeref) {
if (!intel_dp->want_panel_vdd)
- edp_panel_vdd_off_sync(intel_dp);
+ intel_pps_vdd_off_sync_unlocked(intel_dp);
}
}
@@ -713,7 +713,7 @@ stati
Re: [Intel-gfx] [PATCH v7 00/15] Add support for DP-HDMI2.1 PCON
On Fri, 18 Dec 2020, Ankit Nautiyal wrote: > This patch series attempts to add support for a DP-HDMI2.1 Protocol > Convertor. The VESA spec for the HDMI2.1 PCON are proposed in Errata > E5 to DisplayPort_v2.0: > https://vesa.org/join-vesamemberships/member-downloads/?action=stamp&fileid=42299 > The details are mentioned in: > VESA DP-to-HDMI PCON Specification Standalone Document > https://groups.vesa.org/wg/DP/document/15651 Thanks for the patches and review. I've pushed the series to a new topic branch topic/dp-hdmi-2.1-pcon as discussed with Maarten and Daniel a while back. I've used 'git merge-base drm-misc/drm-misc-next drm-intel/drm-intel-next' as the base to allow merging to both. I'll send pull requests soon, and wait for the drm-misc-next merge before merging to i915. BR, Jani. > > This series starts with adding support for FRL (Fixed Rate Link) > Training between the PCON and HDMI2.1 sink. > As per HDMI2.1 specification, a new data-channel or lane is added in > FRL mode, by repurposing the TMDS clock Channel. Through FRL, higher > bit-rate can be supported, ie. up to 12 Gbps/lane (48 Gbps over 4 > lanes). > > With these patches, the HDMI2.1 PCON can be configured to achieve FRL > training based on the maximum FRL rate supported by the panel, source > and the PCON. > The approach is to add the support for FRL training between PCON and > HDMI2.1 sink and gradually add other blocks for supporting higher > resolutions and other HDMI2.1 features, that can be supported by pcon > for the sources that do not natively support HDMI2.1. > > This is done before the DP Link training between the source and PCON > is started. In case of FRL training is not achieved, the PCON will > work in the regular TMDS mode, without HDMI2.1 feature support. > Any interruption in FRL training between the PCON and HDMI2.1 sink is > notified through IRQ_HPD. On receiving the IRQ_HPD the concerned DPCD > registers are read and FRL training is re-attempted. > > Currently, we have tested the FRL training and are able to enable 4K > display with TGL Platform + Realtek PCON RTD2173 with HDMI2.1 supporting > panel. > > v2: Addressed review comments and re-organized patches as suggested in > comments on RFC patches. > > v3: Addressed review comments on previous version. > > v4: Added support for RGB->YCBCR conversion through PCON > > v5: Addressed review comments on previous version. > > v6: Fix typo in one of the patch. > > v7: Rebased on latest drm-tip and addressed the review comments. > > Ankit Nautiyal (11): > drm/edid: Parse DSC1.2 cap fields from HFVSDB block > drm/dp_helper: Add Helpers for FRL Link Training support for > DP-HDMI2.1 PCON > drm/dp_helper: Add support for Configuring DSC for HDMI2.1 Pcon > drm/dp_helper: Add helpers to configure PCONs RGB-YCbCr Conversion > drm/i915: Capture max frl rate for PCON in dfp cap structure > drm/i915: Add support for starting FRL training for HDMI2.1 via PCON > drm/i915: Check for FRL training before DP Link training > drm/i915: Read DSC capabilities of the HDMI2.1 PCON encoder > drm/i915: Add helper functions for calculating DSC parameters for > HDMI2.1 > drm/i915/display: Configure PCON for DSC1.1 to DSC1.2 encoding > drm/i915/display: Let PCON convert from RGB to YCbCr if it can > > Swati Sharma (4): > drm/edid: Add additional HFVSDB fields for HDMI2.1 > drm/edid: Parse MAX_FRL field from HFVSDB block > drm/dp_helper: Add support for link failure detection > drm/i915: Add support for enabling link status and recovery > > drivers/gpu/drm/drm_dp_helper.c | 566 ++ > drivers/gpu/drm/drm_edid.c| 103 > drivers/gpu/drm/i915/display/intel_ddi.c | 6 +- > .../drm/i915/display/intel_display_types.h| 10 + > drivers/gpu/drm/i915/display/intel_dp.c | 442 +- > drivers/gpu/drm/i915/display/intel_dp.h | 7 +- > drivers/gpu/drm/i915/display/intel_hdmi.c | 233 +++ > drivers/gpu/drm/i915/display/intel_hdmi.h | 7 + > include/drm/drm_connector.h | 49 ++ > include/drm/drm_dp_helper.h | 218 +++ > include/drm/drm_edid.h| 30 + > 11 files changed, 1652 insertions(+), 19 deletions(-) -- Jani Nikula, Intel Open Source Graphics Center ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for Add support for DP-HDMI2.1 PCON (rev9)
{
> +
>
> -:92: CHECK:LINE_SPACING: Please don't use multiple blank lines
> #92: FILE: drivers/gpu/drm/i915/display/intel_dp.c:4188:
> +
> +
>
> -:155: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
> #155: FILE: drivers/gpu/drm/i915/display/intel_dp.c:4251:
> + bits_per_pixel = intel_dp_pcon_dsc_enc_bpp(intel_dp, crtc_state,
> + num_slices, slice_width);
>
> total: 0 errors, 0 warnings, 3 checks, 157 lines checked
> d739034947bb drm/i915/display: Let PCON convert from RGB to YCbCr if it can
> -:104: WARNING:LONG_LINE: line length of 101 exceeds 100 columns
> #104: FILE: drivers/gpu/drm/i915/display/intel_dp.c:4368:
> +
> DP_DS_HDMI_BT2020_RGB_YCBCR_CONV);
>
> -:156: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
> #156: FILE: drivers/gpu/drm/i915/display/intel_dp.c:6922:
> + rgb_to_ycbcr = drm_dp_downstream_rgb_to_ycbcr_conversion(intel_dp->dpcd,
> +
> intel_dp->downstream_ports,
>
> total: 0 errors, 1 warnings, 1 checks, 152 lines checked
>
>
> ___
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
--
Jani Nikula, Intel Open Source Graphics Center
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PULL] topic/dp-hdmi-2.1-pcon for drm-misc-next
ning drm/i915: Read DSC capabilities of the HDMI2.1 PCON encoder drm/i915: Add helper functions for calculating DSC parameters for HDMI2.1 drm/i915/display: Configure PCON for DSC1.1 to DSC1.2 encoding drm/i915/display: Let PCON convert from RGB to YCbCr if it can Swati Sharma (4): drm/edid: Add additional HFVSDB fields for HDMI2.1 drm/edid: Parse MAX_FRL field from HFVSDB block drm/dp_helper: Add support for link failure detection drm/i915: Add support for enabling link status and recovery drivers/gpu/drm/drm_dp_helper.c| 566 + drivers/gpu/drm/drm_edid.c | 103 drivers/gpu/drm/i915/display/intel_ddi.c | 6 +- drivers/gpu/drm/i915/display/intel_display_types.h | 10 + drivers/gpu/drm/i915/display/intel_dp.c| 440 +++- drivers/gpu/drm/i915/display/intel_dp.h| 7 +- drivers/gpu/drm/i915/display/intel_hdmi.c | 233 + drivers/gpu/drm/i915/display/intel_hdmi.h | 7 + include/drm/drm_connector.h| 49 ++ include/drm/drm_dp_helper.h| 218 include/drm/drm_edid.h | 30 ++ 11 files changed, 1650 insertions(+), 19 deletions(-) -- Jani Nikula, Intel Open Source Graphics Center ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH v2] drm/i915: Try to guess PCH type even without ISA bridge
On Fri, 18 Dec 2020, Xiong Zhang wrote:
> From: Zhenyu Wang
>
> Some vmm like hyperv and crosvm don't supply any ISA bridge to their guest,
> when igd passthrough is equipped on these vmm, guest i915 display may
> couldn't work as guest i915 detects PCH_NONE pch type.
>
> When i915 runs as guest, this patch guess pch type through gpu type even
> without ISA bridge.
>
> v2: Fix CI warning
>
> Signed-off-by: Zhenyu Wang
> ---
> drivers/gpu/drm/i915/i915_drv.h | 7 +-
> drivers/gpu/drm/i915/intel_pch.c | 38 ++--
> 2 files changed, 32 insertions(+), 13 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index 5a7df5621aa3..df0b8f9268b2 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -1758,6 +1758,11 @@ tgl_revids_get(struct drm_i915_private *dev_priv)
> #define INTEL_DISPLAY_ENABLED(dev_priv) \
> (drm_WARN_ON(&(dev_priv)->drm, !HAS_DISPLAY(dev_priv)),
> !(dev_priv)->params.disable_display)
>
> +static inline bool run_as_guest(void)
> +{
> + return !hypervisor_is_type(X86_HYPER_NATIVE);
> +}
> +
> static inline bool intel_vtd_active(void)
> {
> #ifdef CONFIG_INTEL_IOMMU
> @@ -1766,7 +1771,7 @@ static inline bool intel_vtd_active(void)
> #endif
>
> /* Running as a guest, we assume the host is enforcing VT'd */
> - return !hypervisor_is_type(X86_HYPER_NATIVE);
> + return run_as_guest();
> }
>
> static inline bool intel_scanout_needs_vtd_wa(struct drm_i915_private
> *dev_priv)
> diff --git a/drivers/gpu/drm/i915/intel_pch.c
> b/drivers/gpu/drm/i915/intel_pch.c
> index f31c0dabd0cc..a73c60bf349e 100644
> --- a/drivers/gpu/drm/i915/intel_pch.c
> +++ b/drivers/gpu/drm/i915/intel_pch.c
> @@ -184,6 +184,23 @@ intel_virt_detect_pch(const struct drm_i915_private
> *dev_priv)
> return id;
> }
>
> +static void intel_detect_pch_virt(struct drm_i915_private *dev_priv)
> +{
> + unsigned short id;
> + enum intel_pch pch_type;
> +
> + id = intel_virt_detect_pch(dev_priv);
intel_detect_pch_virt() calls intel_virt_detect_pch()... the naming
should be clarified to make some difference.
> + pch_type = intel_pch_type(dev_priv, id);
> +
> + /* Sanity check virtual PCH id */
> + if (drm_WARN_ON(&dev_priv->drm,
> + id && pch_type == PCH_NONE))
> + id = 0;
> +
> + dev_priv->pch_type = pch_type;
> + dev_priv->pch_id = id;
Previously the pch type and id assignments were all done in
intel_detect_pch(), so moving this to a separate function in *some* but
not all cases reduces clarity too.
BR,
Jani.
> +}
> +
> void intel_detect_pch(struct drm_i915_private *dev_priv)
> {
> struct pci_dev *pch = NULL;
> @@ -221,16 +238,7 @@ void intel_detect_pch(struct drm_i915_private *dev_priv)
> break;
> } else if (intel_is_virt_pch(id, pch->subsystem_vendor,
>pch->subsystem_device)) {
> - id = intel_virt_detect_pch(dev_priv);
> - pch_type = intel_pch_type(dev_priv, id);
> -
> - /* Sanity check virtual PCH id */
> - if (drm_WARN_ON(&dev_priv->drm,
> - id && pch_type == PCH_NONE))
> - id = 0;
> -
> - dev_priv->pch_type = pch_type;
> - dev_priv->pch_id = id;
> + intel_detect_pch_virt(dev_priv);
> break;
> }
> }
> @@ -246,8 +254,14 @@ void intel_detect_pch(struct drm_i915_private *dev_priv)
> dev_priv->pch_id = 0;
> }
>
> - if (!pch)
> - drm_dbg_kms(&dev_priv->drm, "No PCH found.\n");
> + if (!pch) {
> + if (run_as_guest()) {
> + drm_dbg_kms(&dev_priv->drm, "No PCH found in vm, try
> guess..\n");
> + intel_detect_pch_virt(dev_priv);
> + } else {
> + drm_dbg_kms(&dev_priv->drm, "No PCH found.\n");
> + }
> + }
>
> pci_dev_put(pch);
> }
--
Jani Nikula, Intel Open Source Graphics Center
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for Add support for DP-HDMI2.1 PCON (rev9)
On Wed, 23 Dec 2020, "Sharma, Swati2" wrote: > On 23-Dec-20 12:24 PM, Shankar, Uma wrote: >> >> >>> -Original Message- >>> From: Nautiyal, Ankit K >>> Sent: Wednesday, December 23, 2020 11:27 AM >>> To: Jani Nikula ; Sharma, Swati2 >>> ; Shankar, Uma >>> Cc: intel-gfx@lists.freedesktop.org >>> Subject: Re: [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for Add support for DP- >>> HDMI2.1 PCON (rev9) >>> >>> Hi Jani, >>> >>> I apologize to miss these checkpatch errors. I mistakenly used some older >>> version >>> of checkpatch script and couldn't get these. >>> >>> Nevertheless I should have taken care of the warnings from the patchwork. I >>> fully >>> understand that onus is on the submitter of the series to fix all such >>> warnings >>> and checks, and I take full responsibility of this mistake. >>> >>> Thank you for fixing these issues this time, and I assure you that I will >>> take care >>> in future and make sure that the checkpatch warnings are addressed. >>> >>> Once again I apologize for the fault. >> >> I also should have checked this, will be more careful to ensure this remains >> the top item >> in the checklist along with CI results. >> >> Regards, >> Uma Shankar > > Apologies from my side too. > > Thanks and Regards, > Swati Hey - Don't worry about it. I mean, do pay attention going forward, but don't worry about it. ;) Also, please consider using 'dim checkpatch' as a helper for checking the commits in a branch. It'll use checkpatch from the kernel repo directly, and it'll pass useful parameters to checkpatch. One of them is --strict, which you may have missed. For example, to check the HEAD commit: $ dim checkpatch Five topmost commits in your current branch: $ dim checkpatch HEAD~5 Additionally use the "drm-intel" profile to filter out some of the more noisy warnings we don't care so much about (*): $ dim checkpatch HEAD~5 drm-intel HTH, Jani. (*) --max-line-length=100 --ignore=BIT_MACRO,SPLIT_STRING,LONG_LINE_STRING,BOOL_MEMBER >>> >>> Thanks & Regards, >>> >>> Ankit >>> >>> >>> On 12/22/2020 10:13 PM, Jani Nikula wrote: >>>> On Fri, 18 Dec 2020, Patchwork wrote: >>>>> == Series Details == >>>>> >>>>> Series: Add support for DP-HDMI2.1 PCON (rev9) >>>>> URL : https://patchwork.freedesktop.org/series/82098/ >>>>> State : warning >>>>> >>>>> == Summary == >>>>> >>>> All - >>>> >>>> I've fixed most of the checkpatch warnings (save for LONG_LINE and >>>> BIT_MACRO that we don't care so much about) while applying. It's not >>>> something I normally do, and I really don't want to find these when >>>> the series is at v7 and the same warnings have been there since >>>> September and I keep being pinged about merging. >>>> >>>> Keeping the driver nice and clean is your job too, not just mine. >>>> >>>> BR, >>>> Jani. >>>> >>>> >>>>> $ dim checkpatch origin/drm-tip >>>>> 26eb0c2f2ee1 drm/edid: Add additional HFVSDB fields for HDMI2.1 >>>>> -:61: WARNING:FROM_SIGN_OFF_MISMATCH: From:/Signed-off-by: email >>> name mismatch: 'From: Swati Sharma ' != >>> 'Signed-off- >>> by: Sharma, Swati2 ' >>>>> >>>>> total: 0 errors, 1 warnings, 0 checks, 36 lines checked 13ffe829d77e >>>>> drm/edid: Parse MAX_FRL field from HFVSDB block >>>>> -:73: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open >>>>> parenthesis >>>>> #73: FILE: drivers/gpu/drm/drm_edid.c:4948: >>>>> + drm_get_max_frl_rate(max_frl_rate, &hdmi->max_lanes, >>>>> + &hdmi->max_frl_rate_per_lane); >>>>> >>>>> -:95: WARNING:FROM_SIGN_OFF_MISMATCH: From:/Signed-off-by: email >>> name mismatch: 'From: Swati Sharma ' != >>> 'Signed-off- >>> by: Sharma, Swati2 ' >>>>> >>>>> total: 0 errors, 1 warnings, 1 checks, 68 lines checked >>>>> 89853c019e04 drm/edid: Parse DSC1.2 cap fields from HFVSDB block >>>>> -:51: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open >>>>>
Re: [Intel-gfx] [PATCH] drm/i915/display: Bitwise or the conversion colour specifier together
On Wed, 23 Dec 2020, Chris Wilson wrote:
> drivers/gpu/drm/i915/display/intel_dp.c:6922 intel_dp_update_420() warn:
> should this be a bitwise op?
> drivers/gpu/drm/i915/display/intel_dp.c:6922 intel_dp_update_420() warn:
> should this be a bitwise op?
> drivers/gpu/drm/i915/display/intel_dp.c:6923 intel_dp_update_420() warn:
> should this be a bitwise op?
>
> Inside drm_dp_downstream_rgb_to_ycbcr_conversion(), that paramter
> 'color_spc' is used as return port_cap[3] & color_spc, implying that it
> is indeed a mask and not a boolean value.
So this one belongs in topic/dp-hdmi-2.1-pcon branch.
Purely based on the context this is the right thing to do, so:
Reviewed-by: Jani Nikula
Ankit, please test the patch in case it uncovers some other
issues. It'll impact the RGB to YCbCr conversion.
BR,
Jani.
>
> Fixes: 522508b665df ("drm/i915/display: Let PCON convert from RGB to YCbCr if
> it can")
> Signed-off-by: Chris Wilson
> Cc: Uma Shankar
> Cc: Ankit Nautiyal
> Cc: Jani Nikula
> ---
> drivers/gpu/drm/i915/display/intel_dp.c | 4 ++--
> 1 file changed, 2 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_dp.c
> b/drivers/gpu/drm/i915/display/intel_dp.c
> index 8b4b2ea52859..157a850a83a7 100644
> --- a/drivers/gpu/drm/i915/display/intel_dp.c
> +++ b/drivers/gpu/drm/i915/display/intel_dp.c
> @@ -6918,8 +6918,8 @@ intel_dp_update_420(struct intel_dp *intel_dp)
>
> intel_dp->downstream_ports);
> rgb_to_ycbcr = drm_dp_downstream_rgb_to_ycbcr_conversion(intel_dp->dpcd,
>
> intel_dp->downstream_ports,
> -
> DP_DS_HDMI_BT601_RGB_YCBCR_CONV ||
> -
> DP_DS_HDMI_BT709_RGB_YCBCR_CONV ||
> +
> DP_DS_HDMI_BT601_RGB_YCBCR_CONV |
> +
> DP_DS_HDMI_BT709_RGB_YCBCR_CONV |
>
> DP_DS_HDMI_BT2020_RGB_YCBCR_CONV);
>
> if (INTEL_GEN(i915) >= 11) {
--
Jani Nikula, Intel Open Source Graphics Center
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH v3 0/9] drm/i915: Add support for Intel's eDP backlight controls
On Fri, 04 Dec 2020, Lyude Paul wrote: > A while ago we ran into issues while trying to enable the eDP backlight > control interface as defined by VESA, in order to make the DPCD > backlight controls on newer laptop panels work. The issue ended up being > much more complicated however, as we also apparently needed to add > support for an Intel-specific DPCD backlight control interface as the > VESA interface is broken on many laptop panels. For lack of a better > name, we just call this the Intel HDR backlight interface. > > While this only adds support for the SDR backlight mode (I think), this > will fix a lot of user's laptop panels that we weren't able to properly > automatically detect DPCD backlight controls on previously. > > Series-wide changes in v3: > * Pass down brightness values to enable/disable backlight callbacks in a > separate patch > * Rebase > > Lyude Paul (9): > drm/i915/dp: Program source OUI on eDP panels > drm/i915: Rename pwm_* backlight callbacks to ext_pwm_* > drm/i915: Pass down brightness values to enable/disable backlight > callbacks > drm/i915/dp: Rename eDP VESA backlight interface functions > drm/i915/dp: Add register definitions for Intel HDR backlight > interface Pushed the above patches to din to move things forward, thanks for the patches. Still looking at the below. BR, Jani. > drm/i915: Keep track of pwm-related backlight hooks separately > drm/i915/dp: Enable Intel's HDR backlight interface (only SDR for now) > drm/i915/dp: Allow forcing specific interfaces through > enable_dpcd_backlight > drm/dp: Revert "drm/dp: Introduce EDID-based quirks" > > drivers/gpu/drm/drm_dp_helper.c | 83 +--- > drivers/gpu/drm/drm_dp_mst_topology.c | 3 +- > .../drm/i915/display/intel_display_types.h| 18 +- > drivers/gpu/drm/i915/display/intel_dp.c | 42 +- > .../drm/i915/display/intel_dp_aux_backlight.c | 394 +--- > drivers/gpu/drm/i915/display/intel_dp_mst.c | 3 +- > .../i915/display/intel_dsi_dcs_backlight.c| 7 +- > drivers/gpu/drm/i915/display/intel_panel.c| 435 ++ > drivers/gpu/drm/i915/display/intel_panel.h| 4 + > drivers/gpu/drm/i915/display/intel_psr.c | 2 +- > drivers/gpu/drm/i915/i915_params.c | 2 +- > include/drm/drm_dp_helper.h | 21 +- > 12 files changed, 655 insertions(+), 359 deletions(-) -- Jani Nikula, Intel Open Source Graphics Center ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH v3 4/9] drm/i915: Keep track of pwm-related backlight hooks separately
ght,
> .disable = pch_disable_backlight,
> @@ -2068,7 +2093,7 @@ static const struct intel_panel_bl_funcs ext_pwm_funcs
> = {
> .get = ext_pwm_get_backlight,
> };
>
> -static const struct intel_panel_bl_funcs vlv_funcs = {
> +static const struct intel_panel_bl_funcs vlv_pwm_funcs = {
> .setup = vlv_setup_backlight,
> .enable = vlv_enable_backlight,
> .disable = vlv_disable_backlight,
> @@ -2077,7 +2102,7 @@ static const struct intel_panel_bl_funcs vlv_funcs = {
> .hz_to_pwm = vlv_hz_to_pwm,
> };
>
> -static const struct intel_panel_bl_funcs i965_funcs = {
> +static const struct intel_panel_bl_funcs i965_pwm_funcs = {
> .setup = i965_setup_backlight,
> .enable = i965_enable_backlight,
> .disable = i965_disable_backlight,
> @@ -2086,7 +2111,7 @@ static const struct intel_panel_bl_funcs i965_funcs = {
> .hz_to_pwm = i965_hz_to_pwm,
> };
>
> -static const struct intel_panel_bl_funcs i9xx_funcs = {
> +static const struct intel_panel_bl_funcs i9xx_pwm_funcs = {
> .setup = i9xx_setup_backlight,
> .enable = i9xx_enable_backlight,
> .disable = i9xx_disable_backlight,
> @@ -2095,6 +2120,14 @@ static const struct intel_panel_bl_funcs i9xx_funcs = {
> .hz_to_pwm = i9xx_hz_to_pwm,
> };
>
> +static const struct intel_panel_bl_funcs pwm_bl_funcs = {
> + .setup = intel_pwm_setup_backlight,
> + .enable = intel_pwm_enable_backlight,
> + .disable = intel_pwm_disable_backlight,
> + .set = intel_pwm_set_backlight,
> + .get = intel_pwm_get_backlight,
> +};
> +
> /* Set up chip specific backlight functions */
> static void
> intel_panel_init_backlight_funcs(struct intel_panel *panel)
> @@ -2103,36 +2136,39 @@ intel_panel_init_backlight_funcs(struct intel_panel
> *panel)
> container_of(panel, struct intel_connector, panel);
> struct drm_i915_private *dev_priv = to_i915(connector->base.dev);
>
> - if (connector->base.connector_type == DRM_MODE_CONNECTOR_eDP &&
> - intel_dp_aux_init_backlight_funcs(connector) == 0)
> - return;
> -
I think I'd keep this here in this patch. It helps with the
interpretation of the change here, i.e. we're not starting to utilize
the two levels just yet.
> if (connector->base.connector_type == DRM_MODE_CONNECTOR_DSI &&
> intel_dsi_dcs_init_backlight_funcs(connector) == 0)
> return;
>
> if (IS_GEN9_LP(dev_priv)) {
> - panel->backlight.funcs = &bxt_funcs;
> + panel->backlight.pwm_funcs = &bxt_pwm_funcs;
> } else if (INTEL_PCH_TYPE(dev_priv) >= PCH_CNP) {
> - panel->backlight.funcs = &cnp_funcs;
> + panel->backlight.pwm_funcs = &cnp_pwm_funcs;
> } else if (INTEL_PCH_TYPE(dev_priv) >= PCH_LPT) {
> if (HAS_PCH_LPT(dev_priv))
> - panel->backlight.funcs = &lpt_funcs;
> + panel->backlight.pwm_funcs = &lpt_pwm_funcs;
> else
> - panel->backlight.funcs = &spt_funcs;
> + panel->backlight.pwm_funcs = &spt_pwm_funcs;
> } else if (HAS_PCH_SPLIT(dev_priv)) {
> - panel->backlight.funcs = &pch_funcs;
> + panel->backlight.pwm_funcs = &pch_pwm_funcs;
> } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
> if (connector->base.connector_type == DRM_MODE_CONNECTOR_DSI) {
> - panel->backlight.funcs = &ext_pwm_funcs;
> + panel->backlight.pwm_funcs = &ext_pwm_funcs;
> } else {
> - panel->backlight.funcs = &vlv_funcs;
> + panel->backlight.pwm_funcs = &vlv_pwm_funcs;
> }
> } else if (IS_GEN(dev_priv, 4)) {
> - panel->backlight.funcs = &i965_funcs;
> + panel->backlight.pwm_funcs = &i965_pwm_funcs;
> } else {
> - panel->backlight.funcs = &i9xx_funcs;
> + panel->backlight.pwm_funcs = &i9xx_pwm_funcs;
> }
> +
> + if (connector->base.connector_type == DRM_MODE_CONNECTOR_eDP &&
> + intel_dp_aux_init_backlight_funcs(connector) == 0)
> + return;
> +
> + /* We're using a standard PWM backlight interface */
> + panel->backlight.funcs = &pwm_bl_funcs;
> }
>
> enum drm_connector_status
--
Jani Nikula, Intel Open Source Graphics Center
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH v3 7/9] drm/i915/dp: Enable Intel's HDR backlight interface (only SDR for now)
pwmgen_bit_count) < 0)
> drm_dbg_kms(&i915->drm,
> "Failed to write aux pwmgen bit count\n");
>
> @@ -364,7 +552,7 @@ static u32 intel_dp_aux_vesa_calc_max_backlight(struct
> intel_connector *connecto
> "Failed to write aux pwmgen bit count\n");
> return max_backlight;
> }
> - panel->backlight.pwmgen_bit_count = pn;
> + panel->backlight.edp.vesa.pwmgen_bit_count = pn;
>
> max_backlight = (1 << pn) - 1;
>
> @@ -405,6 +593,14 @@ intel_dp_aux_supports_vesa_backlight(struct
> intel_connector *connector)
> return false;
> }
>
> +static const struct intel_panel_bl_funcs intel_dp_hdr_bl_funcs = {
> + .setup = intel_dp_aux_hdr_setup_backlight,
> + .enable = intel_dp_aux_hdr_enable_backlight,
> + .disable = intel_dp_aux_hdr_disable_backlight,
> + .set = intel_dp_aux_hdr_set_backlight,
> + .get = intel_dp_aux_hdr_get_backlight,
> +};
> +
> static const struct intel_panel_bl_funcs intel_dp_vesa_bl_funcs = {
> .setup = intel_dp_aux_vesa_setup_backlight,
> .enable = intel_dp_aux_vesa_enable_backlight,
> @@ -413,36 +609,34 @@ static const struct intel_panel_bl_funcs
> intel_dp_vesa_bl_funcs = {
> .get = intel_dp_aux_vesa_get_backlight,
> };
>
> -int intel_dp_aux_init_backlight_funcs(struct intel_connector
> *intel_connector)
> +int intel_dp_aux_init_backlight_funcs(struct intel_connector *connector)
> {
> - struct intel_panel *panel = &intel_connector->panel;
> - struct intel_dp *intel_dp = enc_to_intel_dp(intel_connector->encoder);
> + struct drm_device *dev = connector->base.dev;
> + struct intel_panel *panel = &connector->panel;
> + struct intel_dp *intel_dp = enc_to_intel_dp(connector->encoder);
> struct drm_i915_private *i915 = dp_to_i915(intel_dp);
>
> - if (i915->params.enable_dpcd_backlight == 0 ||
> - !intel_dp_aux_supports_vesa_backlight(intel_connector))
> + if (i915->params.enable_dpcd_backlight == 0)
> return -ENODEV;
>
> /*
> - * There are a lot of machines that don't advertise the backlight
> - * control interface to use properly in their VBIOS, :\
> + * A lot of eDP panels in the wild will report supporting both the
> + * Intel proprietary backlight control interface, and the VESA
> + * backlight control interface. Many of these panels are liars though,
> + * and will only work with the Intel interface. So, always probe for
> + * that first.
>*/
> - if (i915->vbt.backlight.type !=
> - INTEL_BACKLIGHT_VESA_EDP_AUX_INTERFACE &&
I do wonder about dropping this out. I see it gets added back in the
next patch, but this just means it's, I think, necessary to merge the
two patches back to back.
Despite the nitpicks, this is the only concern I have, really. I didn't
review all the hdr hooks in detail, and if it works, it anyway trumps me
checking the code against some crappy powerpoint of a spec I got.
Overall,
Acked-by: Jani Nikula
with or without the nitpicks fixed.
> - i915->params.enable_dpcd_backlight != 1 &&
> - !drm_dp_has_quirk(&intel_dp->desc, intel_dp->edid_quirks,
> - DP_QUIRK_FORCE_DPCD_BACKLIGHT)) {
> - drm_info(&i915->drm,
> - "Panel advertises DPCD backlight support, but "
> - "VBT disagrees. If your backlight controls "
> - "don't work try booting with "
> - "i915.enable_dpcd_backlight=1. If your machine "
> - "needs this, please file a _new_ bug report on "
> - "drm/i915, see " FDO_BUG_URL " for details.\n");
> - return -ENODEV;
> + if (intel_dp_aux_supports_hdr_backlight(connector)) {
> + drm_dbg(dev, "Using Intel proprietary eDP backlight
> controls\n");
Nitpick, drm_debug_kms, ditto below.
> + panel->backlight.funcs = &intel_dp_hdr_bl_funcs;
> + return 0;
> }
>
> - panel->backlight.funcs = &intel_dp_vesa_bl_funcs;
> + if (intel_dp_aux_supports_vesa_backlight(connector)) {
> + drm_dbg(dev, "Using VESA eDP backlight controls\n");
> + panel->backlight.funcs = &intel_dp_vesa_bl_funcs;
> + return 0;
> + }
>
> - return 0;
> + return -ENODEV;
> }
> diff --git a/drivers/gpu/drm/i915
Re: [Intel-gfx] [PATCH v3 8/9] drm/i915/dp: Allow forcing specific interfaces through enable_dpcd_backlight
On Fri, 04 Dec 2020, Lyude Paul wrote:
> Since we now support controlling panel backlights through DPCD using
> both the standard VESA interface, and Intel's proprietary HDR backlight
> interface, we should allow the user to be able to explicitly choose
> between one or the other in the event that we're wrong about panels
> reliably reporting support for the Intel HDR interface.
>
> So, this commit adds support for this by introducing two new
> enable_dpcd_backlight options: 2 which forces i915 to only probe for the
> VESA interface, and 3 which forces i915 to only probe for the Intel
> backlight interface (might be useful if we find panels in the wild that
> report the VESA interface in their VBT, but actually only support the
> Intel backlight interface).
>
> v3:
> * Rebase
>
> Signed-off-by: Lyude Paul
> Cc: thay...@noraisin.net
> Cc: Vasily Khoruzhick
> ---
> .../drm/i915/display/intel_dp_aux_backlight.c | 45 +--
> drivers/gpu/drm/i915/i915_params.c| 2 +-
> 2 files changed, 43 insertions(+), 4 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_dp_aux_backlight.c
> b/drivers/gpu/drm/i915/display/intel_dp_aux_backlight.c
> index 9a3ff3ffc158..eef14ab6bddc 100644
> --- a/drivers/gpu/drm/i915/display/intel_dp_aux_backlight.c
> +++ b/drivers/gpu/drm/i915/display/intel_dp_aux_backlight.c
> @@ -609,15 +609,54 @@ static const struct intel_panel_bl_funcs
> intel_dp_vesa_bl_funcs = {
> .get = intel_dp_aux_vesa_get_backlight,
> };
>
> +enum intel_dp_aux_backlight_modparam {
> + INTEL_DP_AUX_BACKLIGHT_AUTO = -1,
> + INTEL_DP_AUX_BACKLIGHT_OFF = 0,
> + INTEL_DP_AUX_BACKLIGHT_ON = 1,
> + INTEL_DP_AUX_BACKLIGHT_FORCE_VESA = 2,
> + INTEL_DP_AUX_BACKLIGHT_FORCE_INTEL = 3,
> +};
> +
> int intel_dp_aux_init_backlight_funcs(struct intel_connector *connector)
> {
> struct drm_device *dev = connector->base.dev;
> struct intel_panel *panel = &connector->panel;
> struct intel_dp *intel_dp = enc_to_intel_dp(connector->encoder);
> struct drm_i915_private *i915 = dp_to_i915(intel_dp);
> + bool try_intel_interface = false, try_vesa_interface = false;
>
> - if (i915->params.enable_dpcd_backlight == 0)
> + /* Check the VBT and user's module parameters to figure out which
> + * interfaces to probe
> + */
> + switch (i915->params.enable_dpcd_backlight) {
> + case INTEL_DP_AUX_BACKLIGHT_OFF:
> return -ENODEV;
> + case INTEL_DP_AUX_BACKLIGHT_AUTO:
> + switch (i915->vbt.backlight.type) {
> + case INTEL_BACKLIGHT_VESA_EDP_AUX_INTERFACE:
> + try_vesa_interface = true;
> + break;
> + case INTEL_BACKLIGHT_DISPLAY_DDI:
> + try_intel_interface = true;
I take it this is what the machines report? *rolls eyes*.
> + try_vesa_interface = true;
> + break;
> + default:
> + return -ENODEV;
> + }
> + break;
> + case INTEL_DP_AUX_BACKLIGHT_ON:
> + if (i915->vbt.backlight.type !=
> INTEL_BACKLIGHT_VESA_EDP_AUX_INTERFACE)
> + try_intel_interface = true;
This could use an explanation - why not try the intel interface in this
case?
Anyway, good enough,
Reviewed-by: Jani Nikula
> +
> + try_vesa_interface = true;
> + break;
> + case INTEL_DP_AUX_BACKLIGHT_FORCE_VESA:
> + try_vesa_interface = true;
> + break;
> + case INTEL_DP_AUX_BACKLIGHT_FORCE_INTEL:
> + try_intel_interface = true;
> + break;
> + }
>
> /*
>* A lot of eDP panels in the wild will report supporting both the
> @@ -626,13 +665,13 @@ int intel_dp_aux_init_backlight_funcs(struct
> intel_connector *connector)
>* and will only work with the Intel interface. So, always probe for
>* that first.
>*/
> - if (intel_dp_aux_supports_hdr_backlight(connector)) {
> + if (try_intel_interface &&
> intel_dp_aux_supports_hdr_backlight(connector)) {
> drm_dbg(dev, "Using Intel proprietary eDP backlight
> controls\n");
> panel->backlight.funcs = &intel_dp_hdr_bl_funcs;
> return 0;
> }
>
> - if (intel_dp_aux_supports_vesa_backlight(connector)) {
> + if (try_vesa_interface &&
> intel_dp_aux_supports_vesa_backlight(connector)) {
> drm_dbg(dev, "Using VESA eDP backlight controls\n");
> panel->backlight.funcs = &
Re: [Intel-gfx] [PATCH 01/13] drm/i915/pps: abstract panel power sequencer from intel_dp.c
On Mon, 28 Dec 2020, "Gupta, Anshuman" wrote: >> -Original Message- >> From: Intel-gfx On Behalf Of Jani >> Nikula >> Sent: Tuesday, December 22, 2020 8:20 PM >> To: intel-gfx@lists.freedesktop.org >> Cc: Nikula, Jani >> Subject: [Intel-gfx] [PATCH 01/13] drm/i915/pps: abstract panel power >> sequencer from intel_dp.c >> >> In a long overdue refactoring, split out all panel sequencer code from >> intel_dp.c to new intel_pps.[ch]. >> >> The first part is mostly just code movement as-is, without cleanups. >> >> We need to add a vlv_get_dpll() helper to get at the vlv/chv dpll from >> pps code. > IMHO functions intel_dp_init_panel_power_sequencer, > intel_dp_init_panel_power_sequencer_registers, > intel_dp_pps_init suits a intel_edp_* prefix. This patch just moves code. The rename would be a separate change on top. Possibly with intel_pps prefix instead because they're not so much about dp or edp as about pps. BR, Jani. -- Jani Nikula, Intel Open Source Graphics Center ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PULL] gvt-next-fixes
On Tue, 05 Jan 2021, Zhenyu Wang wrote: > Ping... I suppose this should be merged to drm-intel-next (or drm-intel-gt-next, or both). It was too late for next-fixes, and it's really not the kind of fixes we need to queue to v5.11-rc's. Rodrigo? BR, Jani. > > On 2020.12.25 10:20:09 +0800, Zhenyu Wang wrote: >> >> Hi, >> >> Here's queued fixes from Jani for one useless inline and fix >> CONFIG_DRM_I915_WERROR for gvt headers. >> >> Thanks and Merry Christmas! >> -- >> The following changes since commit 9a3a238b3de97b4210c6de66aa88b2d7021ac086: >> >> drm/i915/gvt: treat intel_gvt_mpt as const in gvt code (2020-11-23 >> 17:14:20 +0800) >> >> are available in the Git repository at: >> >> https://github.com/intel/gvt-linux tags/gvt-next-fixes-2020-12-25 >> >> for you to fetch changes up to e056f669dbf76b8752b6cb0b8edd2f75cbdcabb1: >> >> drm/i915/gvt: make mpt.h self-contained (2020-12-22 11:41:35 +0800) >> >> >> gvt-next-fixes-2020-12-25 >> >> - Avoid one useless inline (Jani) >> - make gvt header self-contained, fix CONFIG_DRM_I915_WERROR (Jani) >> >> >> Jani Nikula (9): >> drm/i915/gvt: avoid useless use of inline >> drm/i915/gvt: make execlist.h self-contained >> drm/i915/gvt: make fb_decoder.h self-contained >> drm/i915/gvt: make gtt.h self-contained >> drm/i915/gvt: make interrupt.h self-contained >> drm/i915/gvt: make mmio_context.h self-contained >> drm/i915/gvt: make gvt.h self-contained >> drm/i915/gvt: make scheduler.h self-contained >> drm/i915/gvt: make mpt.h self-contained >> >> drivers/gpu/drm/i915/Makefile | 10 +- >> drivers/gpu/drm/i915/gvt/execlist.h | 3 --- >> drivers/gpu/drm/i915/gvt/fb_decoder.h | 6 -- >> drivers/gpu/drm/i915/gvt/gtt.h | 11 ++- >> drivers/gpu/drm/i915/gvt/gvt.h | 4 >> drivers/gpu/drm/i915/gvt/handlers.c | 3 +-- >> drivers/gpu/drm/i915/gvt/interrupt.h| 5 - >> drivers/gpu/drm/i915/gvt/mmio_context.h | 11 +++ >> drivers/gpu/drm/i915/gvt/mpt.h | 2 ++ >> drivers/gpu/drm/i915/gvt/scheduler.h| 5 +++++ >> 10 files changed, 42 insertions(+), 18 deletions(-) >> >> -- >> >> $gpg --keyserver wwwkeys.pgp.net --recv-keys 4D781827 > > > >> ___ >> Intel-gfx mailing list >> Intel-gfx@lists.freedesktop.org >> https://lists.freedesktop.org/mailman/listinfo/intel-gfx -- Jani Nikula, Intel Open Source Graphics Center ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH] drm/i915/icl: Fix initing the DSI DSC power refcount during HW readout
On Wed, 09 Dec 2020, Imre Deak wrote: > For an enabled DSC during HW readout the corresponding power reference > is taken along the CRTC power domain references in > get_crtc_power_domains(). Remove the incorrect get ref from the DSI > encoder hook. Does this fix [1] which is v5.11-rc2 on TGL DSI? Should we pick this up for fixes? BR, Jani. [1] https://intel-gfx-ci.01.org/tree/drm-intel-fixes/CI_DIF_538/fi-tgl-dsi/igt@gem_exec_susp...@basic-s0.html > > Cc: Vandita Kulkarni > Cc: Jani Nikula > Signed-off-by: Imre Deak > --- > drivers/gpu/drm/i915/display/icl_dsi.c | 4 > 1 file changed, 4 deletions(-) > > diff --git a/drivers/gpu/drm/i915/display/icl_dsi.c > b/drivers/gpu/drm/i915/display/icl_dsi.c > index a9439b415603..b3533a32f8ba 100644 > --- a/drivers/gpu/drm/i915/display/icl_dsi.c > +++ b/drivers/gpu/drm/i915/display/icl_dsi.c > @@ -1616,10 +1616,6 @@ static void gen11_dsi_get_power_domains(struct > intel_encoder *encoder, > > get_dsi_io_power_domains(i915, >enc_to_intel_dsi(encoder)); > - > - if (crtc_state->dsc.compression_enable) > - intel_display_power_get(i915, > - intel_dsc_power_domain(crtc_state)); > } > > static bool gen11_dsi_get_hw_state(struct intel_encoder *encoder, -- Jani Nikula, Intel Open Source Graphics Center ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PULL] drm-intel-fixes
Hi Dave & Daniel - Pretty quiet still, but here's some cc: stable fixes. (Well, one doesn't have the explicit stable tag, but the Fixes tag points at a commit in v3.9...) drm-intel-fixes-2021-01-07: drm/i915 fixes for v5.11-rc3: - Use per-connector PM QoS tracking for DP aux communication - GuC firmware fix for older Cometlakes - Clear the gpu reloc and shadow batches BR, Jani. The following changes since commit e71ba9452f0b5b2e8dc8aa5445198cd9214a6a62: Linux 5.11-rc2 (2021-01-03 15:55:30 -0800) are available in the Git repository at: git://anongit.freedesktop.org/drm/drm-intel tags/drm-intel-fixes-2021-01-07 for you to fetch changes up to 9397d66212cdf7a21c66523f1583e5d63a609e84: drm/i915/dp: Track pm_qos per connector (2021-01-05 10:25:03 +0200) drm/i915 fixes for v5.11-rc3: - Use per-connector PM QoS tracking for DP aux communication - GuC firmware fix for older Cometlakes - Clear the gpu reloc and shadow batches Chris Wilson (2): drm/i915/gt: Define guc firmware blob for older Cometlakes drm/i915/dp: Track pm_qos per connector Matthew Auld (2): drm/i915: clear the shadow batch drm/i915: clear the gpu reloc batch drivers/gpu/drm/i915/display/intel_display_types.h | 3 +++ drivers/gpu/drm/i915/display/intel_dp.c| 8 +-- drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c | 4 +++- drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c | 1 + drivers/gpu/drm/i915/i915_cmd_parser.c | 27 -- drivers/gpu/drm/i915/i915_drv.c| 5 drivers/gpu/drm/i915/i915_drv.h| 3 --- 7 files changed, 22 insertions(+), 29 deletions(-) -- Jani Nikula, Intel Open Source Graphics Center ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH v2] drm/i915/debugfs : PM_REQ and PM_RES registers
On Mon, 04 Jan 2021, Saichandana S wrote:
> From: Saichandana
>
> PM_REQ register provides the value of the last PM request from PCU to
> Display Engine.PM_RES register provides the value of the last PM
> response from Display Engine to PCU.This debugfs will be used by
> DC9 IGT test to know about "DC9 Ready" status.
>
> B.Spec : 49501, 49502
>
> Signed-off-by: Saichandana
> ---
> .../drm/i915/display/intel_display_debugfs.c | 30 +++
> drivers/gpu/drm/i915/i915_reg.h | 8 +
> 2 files changed, 38 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_display_debugfs.c
> b/drivers/gpu/drm/i915/display/intel_display_debugfs.c
> index cd7e5519ee7d..551fb1a90bb3 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_debugfs.c
> +++ b/drivers/gpu/drm/i915/display/intel_display_debugfs.c
> @@ -559,6 +559,36 @@ static int i915_dmc_info(struct seq_file *m, void
> *unused)
> return 0;
> }
>
> +static int i915_pm_req_res_info(struct seq_file *m, void *unused)
> +{
> + struct drm_i915_private *dev_priv = node_to_i915(m->private);
All new code should call the local variable "i915".
> + struct intel_csr *csr = &dev_priv->csr;
> + const char *status;
> +
> + if (!HAS_CSR(dev_priv))
> + return -ENODEV;
> + if (!csr->dmc_payload)
> + return 0;
> + seq_printf(m, "PM debug request 0 (0x45284): 0x%08x\n",
> +intel_de_read(dev_priv, PM_REQ_DBG_0));
> + seq_printf(m, "PM debug request 1 (0x45288): 0x%08x\n",
> +intel_de_read(dev_priv, PM_REQ_DBG_1));
> + seq_printf(m, "PM debug response 0 (0x4528C): 0x%08x\n",
> +intel_de_read(dev_priv, PM_RSP_DBG_0));
> + seq_printf(m, "PM debug response 1 (0x45290): 0x%08x\n",
> +intel_de_read(dev_priv, PM_RSP_DBG_1));
Like I said before [1], do *not* dump the registers. We have userspace
tools for dumping register contents as-is when you need that for debug
purposes. And even the userspace tool can do some register content
parsing. See tools/intel_reg in igt.
The only reason to have a debugfs file is to provide some other, added
value that a register dump can't provide.
[1] http://lore.kernel.org/r/87mtyl8vpu@intel.com
> + status = (intel_de_read(dev_priv, PM_RSP_DBG_1) & MASK_DC9_BIT) ? "yes"
> : "no";
See yesno() in i915_utils.h. You probably don't want the local variable
for the string.
> +
> + seq_printf(m, "Time to Next Fill = 0x%0x\n",
> +(intel_de_read(dev_priv, PM_RSP_DBG_0) & ~MASK_RSP_0));
> + seq_printf(m, "Time to Next VBI = 0x%0x\n",
> +((intel_de_read(dev_priv, PM_RSP_DBG_0) & MASK_RSP_0)) >>
> 16);
> + seq_printf(m, "Selective Exit Latency = 0x%0x\n",
> +(intel_de_read(dev_priv, PM_RSP_DBG_1) & MASK_RSP_1));
There's a bunch of unnecessary parenthesis around the 3rd parameter to
seq_printf.
> + seq_printf(m, "DC9 Ready = %s\n", status);
> + return 0;
> +}
> +
> static void intel_seq_print_mode(struct seq_file *m, int tabs,
>const struct drm_display_mode *mode)
> {
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 0023c023f472..3e9ed555f928 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -371,6 +371,14 @@ static inline bool i915_mmio_reg_valid(i915_reg_t reg)
> #define VLV_G3DCTL _MMIO(0x9024)
> #define VLV_GSCKGCTL _MMIO(0x9028)
>
> +#define PM_REQ_DBG_0 _MMIO(0x45284)
> +#define PM_REQ_DBG_1 _MMIO(0x45288)
> +#define PM_RSP_DBG_0 _MMIO(0x4528C)
> +#define PM_RSP_DBG_1 _MMIO(0x45290)
> +#define MASK_RSP_0 (0x << 16)
> +#define MASK_RSP_1 (7 << 0)
> +#define MASK_DC9_BIT (1 << 17)
This is a random location in i915_reg.h, out of place.
Please also read the big comment near the top of this file.
BR,
Jani.
> +
> #define GEN6_MBCTL _MMIO(0x0907c)
> #define GEN6_MBCTL_ENABLE_BOOT_FETCH (1 << 4)
> #define GEN6_MBCTL_CTX_FETCH_NEEDED(1 << 3)
--
Jani Nikula, Intel Open Source Graphics Center
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH V3] drm/i915/gen9_bc : Add TGP PCH support
_STRAP_DDIC_DETECTED)
> + if (found & SFUSE_STRAP_DDIC_DETECTED || HAS_PCH_TGP(dev_priv))
> intel_ddi_init(dev_priv, PORT_C);
> - if (found & SFUSE_STRAP_DDID_DETECTED)
> + if (found & SFUSE_STRAP_DDID_DETECTED || HAS_PCH_TGP(dev_priv))
> intel_ddi_init(dev_priv, PORT_D);
> if (found & SFUSE_STRAP_DDIF_DETECTED)
> intel_ddi_init(dev_priv, PORT_F);
> diff --git a/drivers/gpu/drm/i915/display/intel_hdmi.c
> b/drivers/gpu/drm/i915/display/intel_hdmi.c
> index c5959590562b..536b7b0d68f9 100644
> --- a/drivers/gpu/drm/i915/display/intel_hdmi.c
> +++ b/drivers/gpu/drm/i915/display/intel_hdmi.c
> @@ -3130,6 +3130,24 @@ static u8 rkl_port_to_ddc_pin(struct drm_i915_private
> *dev_priv, enum port port)
> return GMBUS_PIN_1_BXT + phy;
> }
>
> +static u8 gen9bc_port_to_ddc_pin(struct drm_i915_private *dev_priv, enum
> port port)
All new code should use i915 instead of dev_priv.
> +{
> + enum phy phy = intel_port_to_phy(dev_priv, port);
> +
> + WARN_ON(port == PORT_A);
drm_WARN_ON(&i915->drm, port == PORT_A);
> +
> + /*
> + * Pin mapping for GEN9 BC depends on which PCH is present. With TGP,
> + * final two outputs use type-c pins, even though they're actually
> + * combo outputs. With CMP, the traditional DDI A-D pins are used for
> + * all outputs.
> + */
> + if (INTEL_PCH_TYPE(dev_priv) >= PCH_TGP && phy >= PHY_C)
> + return GMBUS_PIN_9_TC1_ICP + phy - PHY_C;
> +
> + return GMBUS_PIN_1_BXT + phy;
> +}
> +
> static u8 dg1_port_to_ddc_pin(struct drm_i915_private *dev_priv, enum port
> port)
> {
> return intel_port_to_phy(dev_priv, port) + 1;
> @@ -3176,6 +3194,8 @@ static u8 intel_hdmi_ddc_pin(struct intel_encoder
> *encoder)
> ddc_pin = dg1_port_to_ddc_pin(dev_priv, port);
> else if (IS_ROCKETLAKE(dev_priv))
> ddc_pin = rkl_port_to_ddc_pin(dev_priv, port);
> + else if (IS_GEN9_BC(dev_priv) && HAS_PCH_TGP(dev_priv))
> + ddc_pin = gen9bc_port_to_ddc_pin(dev_priv, port);
> else if (HAS_PCH_MCC(dev_priv))
> ddc_pin = mcc_port_to_ddc_pin(dev_priv, port);
> else if (INTEL_PCH_TYPE(dev_priv) >= PCH_ICP)
> diff --git a/drivers/gpu/drm/i915/intel_pch.c
> b/drivers/gpu/drm/i915/intel_pch.c
> index f31c0dabd0cc..c1bc2d032360 100644
> --- a/drivers/gpu/drm/i915/intel_pch.c
> +++ b/drivers/gpu/drm/i915/intel_pch.c
> @@ -121,7 +121,8 @@ intel_pch_type(const struct drm_i915_private *dev_priv,
> unsigned short id)
> case INTEL_PCH_TGP2_DEVICE_ID_TYPE:
> drm_dbg_kms(&dev_priv->drm, "Found Tiger Lake LP PCH\n");
> drm_WARN_ON(&dev_priv->drm, !IS_TIGERLAKE(dev_priv) &&
> - !IS_ROCKETLAKE(dev_priv));
> + !IS_ROCKETLAKE(dev_priv) &&
> + !IS_GEN9_BC(dev_priv));
> return PCH_TGP;
> case INTEL_PCH_JSP_DEVICE_ID_TYPE:
> case INTEL_PCH_JSP2_DEVICE_ID_TYPE:
--
Jani Nikula, Intel Open Source Graphics Center
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH] drm/i915/pps: Reuse POWER_DOMAIN_DISPLAY_CORE in pps_{lock, unlock}
On Thu, 07 Jan 2021, Anshuman Gupta wrote:
> We need a power_domain wakeref in pps_{lock,unlock} to prevent
> a race while resetting pps state in intel_power_sequencer_reset().
>
> intel_power_sequencer_reset() need a pps_mutex to access pps_pipe
> but it can't grab pps_mutex due to deadlock with power_well
> functions are called while holding pps_mutex.
> intel_power_sequencer_reset() is called by power_well function
> associated with legacy platforms like vlv and chv therefore re-use
> the POWER_DOMAIN_DISPLAY_CORE power domain, which only used
> by vlv and chv display power domain.
>
> This will avoids the unnecessary noise of unrelated power wells
> in pps_{lock,unlock}.
>
> Cc: Jani Nikula
> Cc: Imre Deak
> Signed-off-by: Anshuman Gupta
Imre convinced me yesterday on irc that this should work.
Reviewed-by: Jani Nikula
On the surface, this reduces the need to enable/disable the aux power so
much. It's unnecessary, so it stands to reason to optimize it. We should
only grab the domain references we actually need.
However, this *also* papers over an issue we've been seeing [1]. We need
to be aware the root cause for that remains unknown, and needs to be
figured out.
I presume simply doing aux transfers won't reproduce the problem,
because that disables the power asynchronously since commit f39194a7a8b9
("drm/i915: Disable power asynchronously during DP AUX
transfers"). Perhaps we wouldn't have seen this at all if pps_unlock()
also did that as suggested in the commit message.
Anyway, I'd like to get acks or rb's from Imre and Ville before merging
this.
BR,
Jani.
[1] http://lore.kernel.org/r/20201204081845.26528-1-anshuman.gu...@intel.com
> ---
> drivers/gpu/drm/i915/display/intel_dp.c | 8 ++--
> 1 file changed, 2 insertions(+), 6 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_dp.c
> b/drivers/gpu/drm/i915/display/intel_dp.c
> index 8a00e609085f..4f190a82d4ad 100644
> --- a/drivers/gpu/drm/i915/display/intel_dp.c
> +++ b/drivers/gpu/drm/i915/display/intel_dp.c
> @@ -895,9 +895,7 @@ pps_lock(struct intel_dp *intel_dp)
>* See intel_power_sequencer_reset() why we need
>* a power domain reference here.
>*/
> - wakeref = intel_display_power_get(dev_priv,
> -
> intel_aux_power_domain(dp_to_dig_port(intel_dp)));
> -
> + wakeref = intel_display_power_get(dev_priv, POWER_DOMAIN_DISPLAY_CORE);
> mutex_lock(&dev_priv->pps_mutex);
>
> return wakeref;
> @@ -909,9 +907,7 @@ pps_unlock(struct intel_dp *intel_dp, intel_wakeref_t
> wakeref)
> struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
>
> mutex_unlock(&dev_priv->pps_mutex);
> - intel_display_power_put(dev_priv,
> -
> intel_aux_power_domain(dp_to_dig_port(intel_dp)),
> - wakeref);
> + intel_display_power_put(dev_priv, POWER_DOMAIN_DISPLAY_CORE, wakeref);
> return 0;
> }
--
Jani Nikula, Intel Open Source Graphics Center
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH 09/13] drm/i915/pps: rename intel_dp_check_edp to intel_pps_check_power_unlocked
On Tue, 29 Dec 2020, Anshuman Gupta wrote:
> On 2020-12-22 at 20:19:49 +0530, Jani Nikula wrote:
>> Follow the usual naming pattern for functions.
>>
>> Signed-off-by: Jani Nikula
>> ---
>> drivers/gpu/drm/i915/display/intel_dp.c | 2 +-
>> drivers/gpu/drm/i915/display/intel_pps.c | 2 +-
>> drivers/gpu/drm/i915/display/intel_pps.h | 2 +-
>> 3 files changed, 3 insertions(+), 3 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/i915/display/intel_dp.c
>> b/drivers/gpu/drm/i915/display/intel_dp.c
>> index 334ba1775cd3..65406d4ccdbe 100644
>> --- a/drivers/gpu/drm/i915/display/intel_dp.c
>> +++ b/drivers/gpu/drm/i915/display/intel_dp.c
>> @@ -1046,7 +1046,7 @@ intel_dp_aux_xfer(struct intel_dp *intel_dp,
>> */
>> cpu_latency_qos_update_request(&i915->pm_qos, 0);
>>
>> -intel_dp_check_edp(intel_dp);
>> +intel_pps_check_power_unlocked(intel_dp);
>>
>> /* Try to wait for any previous AUX channel activity */
>> for (try = 0; try < 3; try++) {
>> diff --git a/drivers/gpu/drm/i915/display/intel_pps.c
>> b/drivers/gpu/drm/i915/display/intel_pps.c
>> index 3e62d1450682..dfd6722bc40e 100644
>> --- a/drivers/gpu/drm/i915/display/intel_pps.c
>> +++ b/drivers/gpu/drm/i915/display/intel_pps.c
>> @@ -431,7 +431,7 @@ static bool edp_have_panel_vdd(struct intel_dp *intel_dp)
>> return intel_de_read(dev_priv, _pp_ctrl_reg(intel_dp)) & EDP_FORCE_VDD;
>> }
>>
>> -void intel_dp_check_edp(struct intel_dp *intel_dp)
>> +void intel_pps_check_power_unlocked(struct intel_dp *intel_dp)
> IMHO comment to take pps_lock would be useful here.
Part of the point of this change is to name it _unlocked to highlight it
does not take the lock, i.e. you should be aware of locking. You see
this pattern all over the kernel. It's self-documenting code.
Moreover, after the edp check, the calls here have:
lockdep_assert_held(&dev_priv->pps_mutex);
which both documents the requirement as well as ensures the proper usage
in lockdep builds. I don't think a comment adds any value.
BR,
Jani.
> Thanks,
> Anshuman.
>> {
>> struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
>>
>> diff --git a/drivers/gpu/drm/i915/display/intel_pps.h
>> b/drivers/gpu/drm/i915/display/intel_pps.h
>> index 4780b59a59df..8dda282abd42 100644
>> --- a/drivers/gpu/drm/i915/display/intel_pps.h
>> +++ b/drivers/gpu/drm/i915/display/intel_pps.h
>> @@ -22,7 +22,6 @@ intel_wakeref_t intel_pps_unlock(struct intel_dp
>> *intel_dp, intel_wakeref_t wake
>> #define with_intel_pps_lock(dp, wf)
>> \
>> for ((wf) = intel_pps_lock(dp); (wf); (wf) = intel_pps_unlock((dp),
>> (wf)))
>>
>> -void intel_dp_check_edp(struct intel_dp *intel_dp);
>> void intel_pps_backlight_on(struct intel_dp *intel_dp);
>> void intel_pps_backlight_off(struct intel_dp *intel_dp);
>> void intel_pps_backlight_power(struct intel_connector *connector, bool
>> enable);
>> @@ -31,6 +30,7 @@ bool intel_pps_vdd_on_unlocked(struct intel_dp *intel_dp);
>> void intel_pps_vdd_off_unlocked(struct intel_dp *intel_dp, bool sync);
>> void intel_pps_on_unlocked(struct intel_dp *intel_dp);
>> void intel_pps_off_unlocked(struct intel_dp *intel_dp);
>> +void intel_pps_check_power_unlocked(struct intel_dp *intel_dp);
>>
>> void intel_pps_vdd_on(struct intel_dp *intel_dp);
>> void intel_pps_on(struct intel_dp *intel_dp);
>> --
>> 2.20.1
>>
>> ___
>> Intel-gfx mailing list
>> Intel-gfx@lists.freedesktop.org
>> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
> ___
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
--
Jani Nikula, Intel Open Source Graphics Center
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH v8 4/5] drm/i915/rkl: Handle HTI
On Thu, 16 Jul 2020, Matt Roper wrote: > @@ -17903,6 +17904,13 @@ int intel_modeset_init(struct drm_i915_private *i915) > if (i915->max_cdclk_freq == 0) > intel_update_max_cdclk(i915); > > + /* > + * If the platform has HTI, we need to find out whether it has reserved > + * any display resources before we create our display outputs. > + */ > + if (INTEL_INFO(i915)->display.has_hti) > + i915->hti_state = intel_de_read(i915, HDPORT_STATE); > + Just stumbled upon this in code. This is supposed to be a high level modeset init function, and basically anything doing direct register access here is at a completely wrong abstraction layer. Please fix. BR, Jani. -- Jani Nikula, Intel Open Source Graphics Center ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH] drm/i915/display: Bitwise or the conversion colour specifier together
On Thu, 24 Dec 2020, "Nautiyal, Ankit K" wrote:
> Thanks Chris to catch this.
>
> This definitely should be bitwise Operator, as mentioned by Jani is
> right thing to do.
>
> The PCON which I had access to, had the F/W which was using 303Ch
> (previously proposed) for color conversion capability, instead of what
> is latest mentioned in the spec ie. 83h.
>
> While testing, I had to skip this line of code, and hardcoded to older
> register ie. 303Ch.
>
> I Will get this patch tested and update.
In the mean time, the topic/dp-hdmi-2.1-pcon branch has been merged to
drm-next and backmerged to drm-intel-next. So drm-intel-next is where
the fixes should now land.
BR,
Jani.
>
>
> Thanks & Regards,
>
> Ankit
>
>
> On 12/23/2020 4:21 PM, Jani Nikula wrote:
>> On Wed, 23 Dec 2020, Chris Wilson wrote:
>>> drivers/gpu/drm/i915/display/intel_dp.c:6922 intel_dp_update_420() warn:
>>> should this be a bitwise op?
>>> drivers/gpu/drm/i915/display/intel_dp.c:6922 intel_dp_update_420() warn:
>>> should this be a bitwise op?
>>> drivers/gpu/drm/i915/display/intel_dp.c:6923 intel_dp_update_420() warn:
>>> should this be a bitwise op?
>>>
>>> Inside drm_dp_downstream_rgb_to_ycbcr_conversion(), that paramter
>>> 'color_spc' is used as return port_cap[3] & color_spc, implying that it
>>> is indeed a mask and not a boolean value.
>> So this one belongs in topic/dp-hdmi-2.1-pcon branch.
>>
>> Purely based on the context this is the right thing to do, so:
>>
>> Reviewed-by: Jani Nikula
>>
>> Ankit, please test the patch in case it uncovers some other
>> issues. It'll impact the RGB to YCbCr conversion.
>>
>> BR,
>> Jani.
>>
>>
>>> Fixes: 522508b665df ("drm/i915/display: Let PCON convert from RGB to YCbCr
>>> if it can")
>>> Signed-off-by: Chris Wilson
>>> Cc: Uma Shankar
>>> Cc: Ankit Nautiyal
>>> Cc: Jani Nikula
>>> ---
>>> drivers/gpu/drm/i915/display/intel_dp.c | 4 ++--
>>> 1 file changed, 2 insertions(+), 2 deletions(-)
>>>
>>> diff --git a/drivers/gpu/drm/i915/display/intel_dp.c
>>> b/drivers/gpu/drm/i915/display/intel_dp.c
>>> index 8b4b2ea52859..157a850a83a7 100644
>>> --- a/drivers/gpu/drm/i915/display/intel_dp.c
>>> +++ b/drivers/gpu/drm/i915/display/intel_dp.c
>>> @@ -6918,8 +6918,8 @@ intel_dp_update_420(struct intel_dp *intel_dp)
>>>
>>> intel_dp->downstream_ports);
>>> rgb_to_ycbcr = drm_dp_downstream_rgb_to_ycbcr_conversion(intel_dp->dpcd,
>>>
>>> intel_dp->downstream_ports,
>>> -
>>> DP_DS_HDMI_BT601_RGB_YCBCR_CONV ||
>>> -
>>> DP_DS_HDMI_BT709_RGB_YCBCR_CONV ||
>>> +
>>> DP_DS_HDMI_BT601_RGB_YCBCR_CONV |
>>> +
>>> DP_DS_HDMI_BT709_RGB_YCBCR_CONV |
>>>
>>> DP_DS_HDMI_BT2020_RGB_YCBCR_CONV);
>>>
>>> if (INTEL_GEN(i915) >= 11) {
> ___
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
--
Jani Nikula, Intel Open Source Graphics Center
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PULL] topic/dp-hdmi-2.1-pcon for drm-misc-next
On Thu, 07 Jan 2021, Daniel Vetter wrote: > On Wed, Dec 23, 2020 at 10:14:58AM +0200, Jani Nikula wrote: >> >> Hi Maarten, Maxime, and Thomas - >> >> Here's the DP-HDMI2.1 PCON support topic pull consisting of the series >> [1]. The series is split roughly 50-50 between drm helpers and i915, so >> a topic branch seemed to be the right way to go. >> >> I'll also pull this to drm-intel-next once you've merged to >> drm-misc-next. > > I didn't see this merged into drm-misc-next, so pulled into drm-next. I'm > processing an entire batch of pulls, I'll ping you on irc when it's all > ready for backmerging. Thanks, Rodrigo covered the backmerge. BR, Jani. > > Cheers, Daniel > >> >> BR, >> Jani. >> >> >> [1] https://patchwork.freedesktop.org/series/82098/ >> >> >> topic/dp-hdmi-2.1-pcon-2020-12-23: >> Add support for DP-HDMI2.1 PCON >> >> From the series cover letter: >> >> This patch series attempts to add support for a DP-HDMI2.1 Protocol >> Convertor. The VESA spec for the HDMI2.1 PCON are proposed in Errata >> E5 to DisplayPort_v2.0: >> https://vesa.org/join-vesamemberships/member-downloads/?action=stamp&fileid=42299 >> The details are mentioned in: >> VESA DP-to-HDMI PCON Specification Standalone Document >> https://groups.vesa.org/wg/DP/document/15651 >> >> This series starts with adding support for FRL (Fixed Rate Link) >> Training between the PCON and HDMI2.1 sink. >> As per HDMI2.1 specification, a new data-channel or lane is added in >> FRL mode, by repurposing the TMDS clock Channel. Through FRL, higher >> bit-rate can be supported, ie. up to 12 Gbps/lane (48 Gbps over 4 >> lanes). >> >> With these patches, the HDMI2.1 PCON can be configured to achieve FRL >> training based on the maximum FRL rate supported by the panel, source >> and the PCON. >> The approach is to add the support for FRL training between PCON and >> HDMI2.1 sink and gradually add other blocks for supporting higher >> resolutions and other HDMI2.1 features, that can be supported by pcon >> for the sources that do not natively support HDMI2.1. >> >> This is done before the DP Link training between the source and PCON >> is started. In case of FRL training is not achieved, the PCON will >> work in the regular TMDS mode, without HDMI2.1 feature support. >> Any interruption in FRL training between the PCON and HDMI2.1 sink is >> notified through IRQ_HPD. On receiving the IRQ_HPD the concerned DPCD >> registers are read and FRL training is re-attempted. >> >> Currently, we have tested the FRL training and are able to enable 4K >> display with TGL Platform + Realtek PCON RTD2173 with HDMI2.1 supporting >> panel. >> >> The following changes since commit b3bf99daaee96a141536ce5c60a0d6dba6ec1d23: >> >> drm/i915/display: Defer initial modeset until after GGTT is initialised >> (2020-11-26 11:01:52 +) >> >> are available in the Git repository at: >> >> git://anongit.freedesktop.org/drm/drm-intel >> tags/topic/dp-hdmi-2.1-pcon-2020-12-23 >> >> for you to fetch changes up to 522508b665df3bbfdf40381d4e61777844b1703f: >> >> drm/i915/display: Let PCON convert from RGB to YCbCr if it can (2020-12-22 >> 17:59:07 +0200) >> >> >> Add support for DP-HDMI2.1 PCON >> >> From the series cover letter: >> >> This patch series attempts to add support for a DP-HDMI2.1 Protocol >> Convertor. The VESA spec for the HDMI2.1 PCON are proposed in Errata >> E5 to DisplayPort_v2.0: >> https://vesa.org/join-vesamemberships/member-downloads/?action=stamp&fileid=42299 >> The details are mentioned in: >> VESA DP-to-HDMI PCON Specification Standalone Document >> https://groups.vesa.org/wg/DP/document/15651 >> >> This series starts with adding support for FRL (Fixed Rate Link) >> Training between the PCON and HDMI2.1 sink. >> As per HDMI2.1 specification, a new data-channel or lane is added in >> FRL mode, by repurposing the TMDS clock Channel. Through FRL, higher >> bit-rate can be supported, ie. up to 12 Gbps/lane (48 Gbps over 4 >> lanes). >> >> With these patches, the HDMI2.1 PCON can be configured to achieve FRL >> training based on the maximum FRL rate supported by the panel, source >> and the PCON. >> The approach is to add the support for FRL training between PCON and >> HDMI2.1 sink and gradually add other blocks for supporting
Re: [Intel-gfx] [PATCH v5 1/4] drm/i915: Keep track of pwm-related backlight hooks separately
On Thu, 07 Jan 2021, Lyude Paul wrote:
> @@ -1628,37 +1633,32 @@ static int lpt_setup_backlight(struct intel_connector
> *connector, enum pipe unus
> panel->backlight.active_low_pwm = pch_ctl1 & BLM_PCH_POLARITY;
>
> pch_ctl2 = intel_de_read(dev_priv, BLC_PWM_PCH_CTL2);
> - panel->backlight.max = pch_ctl2 >> 16;
> + panel->backlight.pwm_level_max = pch_ctl2 >> 16;
>
> cpu_ctl2 = intel_de_read(dev_priv, BLC_PWM_CPU_CTL2);
>
> - if (!panel->backlight.max)
> - panel->backlight.max = get_backlight_max_vbt(connector);
> + if (!panel->backlight.pwm_level_max)
> + panel->backlight.pwm_level_max =
> get_backlight_max_vbt(connector);
>
> - if (!panel->backlight.max)
> + if (!panel->backlight.pwm_level_max)
> return -ENODEV;
>
> - panel->backlight.min = get_backlight_min_vbt(connector);
> + panel->backlight.pwm_level_min = get_backlight_min_vbt(connector);
>
> - panel->backlight.enabled = pch_ctl1 & BLM_PCH_PWM_ENABLE;
> + panel->backlight.pwm_enabled = pch_ctl1 & BLM_PCH_PWM_ENABLE;
>
> - cpu_mode = panel->backlight.enabled && HAS_PCH_LPT(dev_priv) &&
> + cpu_mode = panel->backlight.pwm_enabled && HAS_PCH_LPT(dev_priv) &&
> !(pch_ctl1 & BLM_PCH_OVERRIDE_ENABLE) &&
> (cpu_ctl2 & BLM_PWM_ENABLE);
> - if (cpu_mode)
> - val = pch_get_backlight(connector);
> - else
> - val = lpt_get_backlight(connector);
> - val = intel_panel_compute_brightness(connector, val);
> - panel->backlight.level = clamp(val, panel->backlight.min,
> -panel->backlight.max);
>
> if (cpu_mode) {
> + val = intel_panel_sanitize_pwm_level(connector,
> pch_get_backlight(connector));
> +
(This really is a PITA to review, not because of how you do it but
because of the hardware and the code itself. I'm just pointing out one
thing here, but I'm not finished yet.)
I think this sanitize call is wrong here. It should be called only when
converting to and from the hw register. Here, we read directly from one
hw register and write back to another hw register.
Now, looking at the history, I think it's been wrong all the way since
commit 5b1ec9ac7ab5 ("drm/i915/backlight: Fix backlight takeover on LPT,
v3."). Probably nobody noticed, because AFAIK inverted brightness
control has only ever been an issue on some gen4 platforms...
*facepalm*
BR,
Jani.
> drm_dbg_kms(&dev_priv->drm,
> "CPU backlight register was enabled, switching to
> PCH override\n");
>
> /* Write converted CPU PWM value to PCH override register */
> - lpt_set_backlight(connector->base.state,
> panel->backlight.level);
> + lpt_set_backlight(connector->base.state, val);
> intel_de_write(dev_priv, BLC_PWM_PCH_CTL1,
> pch_ctl1 | BLM_PCH_OVERRIDE_ENABLE);
>
--
Jani Nikula, Intel Open Source Graphics Center
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH] drm/i915/backlight: fix CPU mode backlight takeover on LPT
The pch_get_backlight(), lpt_get_backlight(), and lpt_set_backlight()
functions operate directly on the hardware registers. If inverting the
value is needed, using intel_panel_compute_brightness(), it should only
be done in the interface between hardware registers and
panel->backlight.level.
The CPU mode takeover code added in commit 5b1ec9ac7ab5
("drm/i915/backlight: Fix backlight takeover on LPT, v3.") reads the
hardware register and converts to panel->backlight.level correctly,
however the value written back should remain in the hardware register
"domain".
This hasn't been an issue, because GM45 machines are the only known
users of i915.invert_brightness and the brightness invert quirk, and
without one of them no conversion is made. It's likely nobody's ever hit
the problem.
Fixes: 5b1ec9ac7ab5 ("drm/i915/backlight: Fix backlight takeover on LPT, v3.")
Cc: Maarten Lankhorst
Cc: Ville Syrjälä
Cc: Lyude Paul
Cc: # v5.1+
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/i915/display/intel_panel.c | 9 +
1 file changed, 5 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_panel.c
b/drivers/gpu/drm/i915/display/intel_panel.c
index 67f81ae995c4..7a4239d1c241 100644
--- a/drivers/gpu/drm/i915/display/intel_panel.c
+++ b/drivers/gpu/drm/i915/display/intel_panel.c
@@ -1649,16 +1649,13 @@ static int lpt_setup_backlight(struct intel_connector
*connector, enum pipe unus
val = pch_get_backlight(connector);
else
val = lpt_get_backlight(connector);
- val = intel_panel_compute_brightness(connector, val);
- panel->backlight.level = clamp(val, panel->backlight.min,
- panel->backlight.max);
if (cpu_mode) {
drm_dbg_kms(&dev_priv->drm,
"CPU backlight register was enabled, switching to
PCH override\n");
/* Write converted CPU PWM value to PCH override register */
- lpt_set_backlight(connector->base.state,
panel->backlight.level);
+ lpt_set_backlight(connector->base.state, val);
intel_de_write(dev_priv, BLC_PWM_PCH_CTL1,
pch_ctl1 | BLM_PCH_OVERRIDE_ENABLE);
@@ -1666,6 +1663,10 @@ static int lpt_setup_backlight(struct intel_connector
*connector, enum pipe unus
cpu_ctl2 & ~BLM_PWM_ENABLE);
}
+ val = intel_panel_compute_brightness(connector, val);
+ panel->backlight.level = clamp(val, panel->backlight.min,
+ panel->backlight.max);
+
return 0;
}
--
2.20.1
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH] drm/i915/pps: Reuse POWER_DOMAIN_DISPLAY_CORE in pps_{lock, unlock}
On Fri, 08 Jan 2021, Imre Deak wrote:
> On Fri, Jan 08, 2021 at 11:38:04AM +0200, Jani Nikula wrote:
>> On Thu, 07 Jan 2021, Anshuman Gupta wrote:
>> > We need a power_domain wakeref in pps_{lock,unlock} to prevent
>> > a race while resetting pps state in intel_power_sequencer_reset().
>> >
>> > intel_power_sequencer_reset() need a pps_mutex to access pps_pipe
>> > but it can't grab pps_mutex due to deadlock with power_well
>> > functions are called while holding pps_mutex.
>> > intel_power_sequencer_reset() is called by power_well function
>> > associated with legacy platforms like vlv and chv therefore re-use
>> > the POWER_DOMAIN_DISPLAY_CORE power domain, which only used
>> > by vlv and chv display power domain.
>> >
>> > This will avoids the unnecessary noise of unrelated power wells
>> > in pps_{lock,unlock}.
>> >
>> > Cc: Jani Nikula
>> > Cc: Imre Deak
>> > Signed-off-by: Anshuman Gupta
>>
>> Imre convinced me yesterday on irc that this should work.
>>
>> Reviewed-by: Jani Nikula
>>
>> On the surface, this reduces the need to enable/disable the aux power so
>> much. It's unnecessary, so it stands to reason to optimize it. We should
>> only grab the domain references we actually need.
>>
>> However, this *also* papers over an issue we've been seeing [1]. We need
>> to be aware the root cause for that remains unknown, and needs to be
>> figured out.
>>
>> I presume simply doing aux transfers won't reproduce the problem,
>> because that disables the power asynchronously since commit f39194a7a8b9
>> ("drm/i915: Disable power asynchronously during DP AUX
>> transfers"). Perhaps we wouldn't have seen this at all if pps_unlock()
>> also did that as suggested in the commit message.
>>
>> Anyway, I'd like to get acks or rb's from Imre and Ville before merging
>> this.
>
> Looks ok to me:
> Acked-by: Imre Deak
Thanks, pushed to din.
BR,
Jani.
>
>>
>>
>> BR,
>> Jani.
>>
>>
>> [1] http://lore.kernel.org/r/20201204081845.26528-1-anshuman.gu...@intel.com
>>
>>
>> > ---
>> > drivers/gpu/drm/i915/display/intel_dp.c | 8 ++--
>> > 1 file changed, 2 insertions(+), 6 deletions(-)
>> >
>> > diff --git a/drivers/gpu/drm/i915/display/intel_dp.c
>> > b/drivers/gpu/drm/i915/display/intel_dp.c
>> > index 8a00e609085f..4f190a82d4ad 100644
>> > --- a/drivers/gpu/drm/i915/display/intel_dp.c
>> > +++ b/drivers/gpu/drm/i915/display/intel_dp.c
>> > @@ -895,9 +895,7 @@ pps_lock(struct intel_dp *intel_dp)
>> > * See intel_power_sequencer_reset() why we need
>> > * a power domain reference here.
>> > */
>> > - wakeref = intel_display_power_get(dev_priv,
>> > -
>> > intel_aux_power_domain(dp_to_dig_port(intel_dp)));
>> > -
>> > + wakeref = intel_display_power_get(dev_priv, POWER_DOMAIN_DISPLAY_CORE);
>> > mutex_lock(&dev_priv->pps_mutex);
>> >
>> >return wakeref;
>> > @@ -909,9 +907,7 @@ pps_unlock(struct intel_dp *intel_dp, intel_wakeref_t
>> > wakeref)
>> > struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
>> >
>> >mutex_unlock(&dev_priv->pps_mutex);
>> > - intel_display_power_put(dev_priv,
>> > -
>> > intel_aux_power_domain(dp_to_dig_port(intel_dp)),
>> > - wakeref);
>> > + intel_display_power_put(dev_priv, POWER_DOMAIN_DISPLAY_CORE, wakeref);
>> >return 0;
>> > }
>>
>> --
>> Jani Nikula, Intel Open Source Graphics Center
> ___
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
--
Jani Nikula, Intel Open Source Graphics Center
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH v2 00/17] drm/i915/dp: split out pps and aux
This is v2 of [1], with comments from Anshuman addressed, and a few additional
patches at the end.
BR,
Jani.
[1] https://patchwork.freedesktop.org/series/85167/
Jani Nikula (17):
drm/i915/pps: abstract panel power sequencer from intel_dp.c
drm/i915/pps: rename pps_{,un}lock -> intel_pps_{,un}lock
drm/i915/pps: rename intel_edp_backlight_* to intel_pps_backlight_*
drm/i915/pps: rename intel_edp_panel_* to intel_pps_*
drm/i915/pps: rename edp_panel_* to intel_pps_*_unlocked
drm/i915/pps: abstract intel_pps_vdd_off_sync
drm/i915/pps: add higher level intel_pps_init() call
drm/i915/pps: abstract intel_pps_encoder_reset()
drm/i915/pps: rename intel_dp_check_edp to
intel_pps_check_power_unlocked
drm/i915/pps: rename intel_power_sequencer_reset to
intel_pps_reset_all
drm/i915/pps: add locked intel_pps_wait_power_cycle
drm/i915/pps: rename vlv_init_panel_power_sequencer to vlv_pps_init
drm/i915/pps: rename intel_dp_init_panel_power_sequencer* functions
drm/i915/pps: refactor init abstractions
drm/i915/pps: move pps code over from intel_display.c and refactor
drm/i915/dp: abstract struct intel_dp pps members to a sub-struct
drm/i915/dp: split out aux functionality to intel_dp_aux.c
drivers/gpu/drm/i915/Makefile |2 +
drivers/gpu/drm/i915/display/intel_ddi.c |9 +-
drivers/gpu/drm/i915/display/intel_display.c | 41 +-
drivers/gpu/drm/i915/display/intel_display.h |1 -
.../drm/i915/display/intel_display_debugfs.c |8 +-
.../drm/i915/display/intel_display_power.c|6 +-
.../drm/i915/display/intel_display_types.h| 61 +-
drivers/gpu/drm/i915/display/intel_dp.c | 2249 +
drivers/gpu/drm/i915/display/intel_dp.h |5 +-
drivers/gpu/drm/i915/display/intel_dp_aux.c | 687 +
drivers/gpu/drm/i915/display/intel_dp_aux.h | 18 +
drivers/gpu/drm/i915/display/intel_pps.c | 1406 +++
drivers/gpu/drm/i915/display/intel_pps.h | 52 +
drivers/gpu/drm/i915/i915_drv.c |1 +
14 files changed, 2312 insertions(+), 2234 deletions(-)
create mode 100644 drivers/gpu/drm/i915/display/intel_dp_aux.c
create mode 100644 drivers/gpu/drm/i915/display/intel_dp_aux.h
create mode 100644 drivers/gpu/drm/i915/display/intel_pps.c
create mode 100644 drivers/gpu/drm/i915/display/intel_pps.h
--
2.20.1
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH v2 01/17] drm/i915/pps: abstract panel power sequencer from intel_dp.c
In a long overdue refactoring, split out all panel sequencer code from
intel_dp.c to new intel_pps.[ch].
The first part is mostly just code movement as-is, without cleanups or
functional changes.
We need to add a vlv_get_dpll() helper to get at the vlv/chv dpll from
pps code.
v2: Rebase.
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/i915/Makefile |1 +
drivers/gpu/drm/i915/display/intel_ddi.c |1 +
.../drm/i915/display/intel_display_power.c|2 +-
drivers/gpu/drm/i915/display/intel_dp.c | 1436 +
drivers/gpu/drm/i915/display/intel_dp.h |5 +-
drivers/gpu/drm/i915/display/intel_pps.c | 1334 +++
drivers/gpu/drm/i915/display/intel_pps.h | 53 +
7 files changed, 1443 insertions(+), 1389 deletions(-)
create mode 100644 drivers/gpu/drm/i915/display/intel_pps.c
create mode 100644 drivers/gpu/drm/i915/display/intel_pps.h
diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makefile
index 4074d8cb0d6e..8a04403a11bb 100644
--- a/drivers/gpu/drm/i915/Makefile
+++ b/drivers/gpu/drm/i915/Makefile
@@ -251,6 +251,7 @@ i915-y += \
display/intel_lspcon.o \
display/intel_lvds.o \
display/intel_panel.o \
+ display/intel_pps.o \
display/intel_sdvo.o \
display/intel_tv.o \
display/intel_vdsc.o \
diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c
b/drivers/gpu/drm/i915/display/intel_ddi.c
index 3df6913369bc..f09a597bf730 100644
--- a/drivers/gpu/drm/i915/display/intel_ddi.c
+++ b/drivers/gpu/drm/i915/display/intel_ddi.c
@@ -46,6 +46,7 @@
#include "intel_hotplug.h"
#include "intel_lspcon.h"
#include "intel_panel.h"
+#include "intel_pps.h"
#include "intel_psr.h"
#include "intel_sprite.h"
#include "intel_tc.h"
diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c
b/drivers/gpu/drm/i915/display/intel_display_power.c
index d52374f01316..a11bd8213df4 100644
--- a/drivers/gpu/drm/i915/display/intel_display_power.c
+++ b/drivers/gpu/drm/i915/display/intel_display_power.c
@@ -4,7 +4,6 @@
*/
#include "display/intel_crt.h"
-#include "display/intel_dp.h"
#include "i915_drv.h"
#include "i915_irq.h"
@@ -16,6 +15,7 @@
#include "intel_dpio_phy.h"
#include "intel_hotplug.h"
#include "intel_pm.h"
+#include "intel_pps.h"
#include "intel_sideband.h"
#include "intel_tc.h"
#include "intel_vga.h"
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c
b/drivers/gpu/drm/i915/display/intel_dp.c
index 4f190a82d4ad..07279b10812e 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -58,6 +58,7 @@
#include "intel_lspcon.h"
#include "intel_lvds.h"
#include "intel_panel.h"
+#include "intel_pps.h"
#include "intel_psr.h"
#include "intel_sideband.h"
#include "intel_tc.h"
@@ -121,6 +122,11 @@ static const struct dp_link_dpll chv_dpll[] = {
{ .p1 = 4, .p2 = 1, .n = 1, .m1 = 2, .m2 = 0x6c0 } },
};
+const struct dpll *vlv_get_dpll(struct drm_i915_private *i915)
+{
+ return IS_CHERRYVIEW(i915) ? &chv_dpll[0].dpll : &vlv_dpll[0].dpll;
+}
+
/* Constants for DP DSC configurations */
static const u8 valid_dsc_bpp[] = {6, 8, 10, 12, 15};
@@ -145,12 +151,6 @@ bool intel_dp_is_edp(struct intel_dp *intel_dp)
static void intel_dp_link_down(struct intel_encoder *encoder,
const struct intel_crtc_state *old_crtc_state);
-static bool edp_panel_vdd_on(struct intel_dp *intel_dp);
-static void edp_panel_vdd_off(struct intel_dp *intel_dp, bool sync);
-static void vlv_init_panel_power_sequencer(struct intel_encoder *encoder,
- const struct intel_crtc_state
*crtc_state);
-static void vlv_steal_power_sequencer(struct drm_i915_private *dev_priv,
- enum pipe pipe);
static void intel_dp_unset_edid(struct intel_dp *intel_dp);
/* update sink rates from dpcd */
@@ -877,447 +877,6 @@ static void intel_dp_unpack_aux(u32 src, u8 *dst, int
dst_bytes)
dst[i] = src >> ((3-i) * 8);
}
-static void
-intel_dp_init_panel_power_sequencer(struct intel_dp *intel_dp);
-static void
-intel_dp_init_panel_power_sequencer_registers(struct intel_dp *intel_dp,
- bool force_disable_vdd);
-static void
-intel_dp_pps_init(struct intel_dp *intel_dp);
-
-static intel_wakeref_t
-pps_lock(struct intel_dp *intel_dp)
-{
- struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
- intel_wakeref_t wakeref;
-
- /*
-* See intel_power_sequencer_reset() why we need
-* a power domain reference here.
-*/
- wakeref = intel_display_power_get(d
[Intel-gfx] [PATCH v2 02/17] drm/i915/pps: rename pps_{, un}lock -> intel_pps_{, un}lock
Start following the usual naming pattern for functions. No functional
changes.
Reviewed-by: Anshuman Gupta
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/i915/display/intel_dp.c | 20 ++--
drivers/gpu/drm/i915/display/intel_pps.c | 21 +++--
drivers/gpu/drm/i915/display/intel_pps.h | 8
3 files changed, 25 insertions(+), 24 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c
b/drivers/gpu/drm/i915/display/intel_dp.c
index 07279b10812e..6e9b114171be 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -1053,7 +1053,7 @@ intel_dp_aux_xfer(struct intel_dp *intel_dp,
aux_domain = intel_aux_power_domain(dig_port);
aux_wakeref = intel_display_power_get(i915, aux_domain);
- pps_wakeref = pps_lock(intel_dp);
+ pps_wakeref = intel_pps_lock(intel_dp);
/*
* We will be called with VDD already enabled for dpcd/edid/oui reads.
@@ -1205,7 +1205,7 @@ intel_dp_aux_xfer(struct intel_dp *intel_dp,
if (vdd)
edp_panel_vdd_off(intel_dp, false);
- pps_unlock(intel_dp, pps_wakeref);
+ intel_pps_unlock(intel_dp, pps_wakeref);
intel_display_power_put_async(i915, aux_domain, aux_wakeref);
if (is_tc_port)
@@ -3514,7 +3514,7 @@ static void intel_enable_dp(struct intel_atomic_state
*state,
if (drm_WARN_ON(&dev_priv->drm, dp_reg & DP_PORT_EN))
return;
- with_pps_lock(intel_dp, wakeref) {
+ with_intel_pps_lock(intel_dp, wakeref) {
if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
vlv_init_panel_power_sequencer(encoder, pipe_config);
@@ -4082,7 +4082,7 @@ intel_dp_link_down(struct intel_encoder *encoder,
if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
intel_wakeref_t wakeref;
- with_pps_lock(intel_dp, wakeref)
+ with_intel_pps_lock(intel_dp, wakeref)
intel_dp->active_pipe = INVALID_PIPE;
}
}
@@ -6257,7 +6257,7 @@ void intel_dp_encoder_flush_work(struct drm_encoder
*encoder)
* vdd might still be enabled do to the delayed vdd off.
* Make sure vdd is actually turned off here.
*/
- with_pps_lock(intel_dp, wakeref)
+ with_intel_pps_lock(intel_dp, wakeref)
edp_panel_vdd_off_sync(intel_dp);
}
@@ -6285,7 +6285,7 @@ void intel_dp_encoder_suspend(struct intel_encoder
*intel_encoder)
* Make sure vdd is actually turned off here.
*/
cancel_delayed_work_sync(&intel_dp->panel_vdd_work);
- with_pps_lock(intel_dp, wakeref)
+ with_intel_pps_lock(intel_dp, wakeref)
edp_panel_vdd_off_sync(intel_dp);
}
@@ -6297,7 +6297,7 @@ void intel_dp_encoder_shutdown(struct intel_encoder
*intel_encoder)
if (!intel_dp_is_edp(intel_dp))
return;
- with_pps_lock(intel_dp, wakeref)
+ with_intel_pps_lock(intel_dp, wakeref)
wait_panel_power_cycle(intel_dp);
}
@@ -6329,7 +6329,7 @@ void intel_dp_encoder_reset(struct drm_encoder *encoder)
!intel_dp_is_edp(intel_dp))
return;
- with_pps_lock(intel_dp, wakeref) {
+ with_intel_pps_lock(intel_dp, wakeref) {
if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
intel_dp->active_pipe = vlv_active_pipe(intel_dp);
@@ -7068,7 +7068,7 @@ static bool intel_edp_init_connector(struct intel_dp
*intel_dp,
return false;
}
- with_pps_lock(intel_dp, wakeref) {
+ with_intel_pps_lock(intel_dp, wakeref) {
intel_dp_init_panel_power_timestamps(intel_dp);
intel_dp_pps_init(intel_dp);
intel_edp_panel_vdd_sanitize(intel_dp);
@@ -7145,7 +7145,7 @@ static bool intel_edp_init_connector(struct intel_dp
*intel_dp,
* vdd might still be enabled do to the delayed vdd off.
* Make sure vdd is actually turned off here.
*/
- with_pps_lock(intel_dp, wakeref)
+ with_intel_pps_lock(intel_dp, wakeref)
edp_panel_vdd_off_sync(intel_dp);
return false;
diff --git a/drivers/gpu/drm/i915/display/intel_pps.c
b/drivers/gpu/drm/i915/display/intel_pps.c
index 83bd83b3e3c4..1a05f2c7f690 100644
--- a/drivers/gpu/drm/i915/display/intel_pps.c
+++ b/drivers/gpu/drm/i915/display/intel_pps.c
@@ -16,7 +16,7 @@ static void
intel_dp_init_panel_power_sequencer_registers(struct intel_dp *intel_dp,
bool force_disable_vdd);
-intel_wakeref_t pps_lock(struct intel_dp *intel_dp)
+intel_wakeref_t intel_pps_lock(struct intel_dp *intel_dp)
{
struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
intel_wakeref_t wakeref;
@@ -31,7 +31,8 @@ intel_wakeref_t
[Intel-gfx] [PATCH v2 03/17] drm/i915/pps: rename intel_edp_backlight_* to intel_pps_backlight_*
Follow the usual naming pattern for functions. No functional changes.
Reviewed-by: Anshuman Gupta
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/i915/display/intel_dp.c | 6 +++---
drivers/gpu/drm/i915/display/intel_pps.c | 10 +-
drivers/gpu/drm/i915/display/intel_pps.h | 6 +++---
3 files changed, 11 insertions(+), 11 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c
b/drivers/gpu/drm/i915/display/intel_dp.c
index 6e9b114171be..421e68bb436f 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -2563,7 +2563,7 @@ void intel_edp_backlight_on(const struct intel_crtc_state
*crtc_state,
drm_dbg_kms(&i915->drm, "\n");
intel_panel_enable_backlight(crtc_state, conn_state);
- _intel_edp_backlight_on(intel_dp);
+ intel_pps_backlight_on(intel_dp);
}
/* Disable backlight PP control and backlight PWM. */
@@ -2577,7 +2577,7 @@ void intel_edp_backlight_off(const struct
drm_connector_state *old_conn_state)
drm_dbg_kms(&i915->drm, "\n");
- _intel_edp_backlight_off(intel_dp);
+ intel_pps_backlight_off(intel_dp);
intel_panel_disable_backlight(old_conn_state);
}
@@ -7128,7 +7128,7 @@ static bool intel_edp_init_connector(struct intel_dp
*intel_dp,
}
intel_panel_init(&intel_connector->panel, fixed_mode, downclock_mode);
- intel_connector->panel.backlight.power = intel_edp_backlight_power;
+ intel_connector->panel.backlight.power = intel_pps_backlight_power;
intel_panel_setup_backlight(connector, pipe);
if (fixed_mode) {
diff --git a/drivers/gpu/drm/i915/display/intel_pps.c
b/drivers/gpu/drm/i915/display/intel_pps.c
index 1a05f2c7f690..36d8782d8df1 100644
--- a/drivers/gpu/drm/i915/display/intel_pps.c
+++ b/drivers/gpu/drm/i915/display/intel_pps.c
@@ -844,7 +844,7 @@ void intel_edp_panel_off(struct intel_dp *intel_dp)
}
/* Enable backlight in the panel power control. */
-void _intel_edp_backlight_on(struct intel_dp *intel_dp)
+void intel_pps_backlight_on(struct intel_dp *intel_dp)
{
struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
intel_wakeref_t wakeref;
@@ -870,7 +870,7 @@ void _intel_edp_backlight_on(struct intel_dp *intel_dp)
}
/* Disable backlight in the panel power control. */
-void _intel_edp_backlight_off(struct intel_dp *intel_dp)
+void intel_pps_backlight_off(struct intel_dp *intel_dp)
{
struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
intel_wakeref_t wakeref;
@@ -897,7 +897,7 @@ void _intel_edp_backlight_off(struct intel_dp *intel_dp)
* Hook for controlling the panel power control backlight through the bl_power
* sysfs attribute. Take care to handle multiple calls.
*/
-void intel_edp_backlight_power(struct intel_connector *connector, bool enable)
+void intel_pps_backlight_power(struct intel_connector *connector, bool enable)
{
struct drm_i915_private *i915 = to_i915(connector->base.dev);
struct intel_dp *intel_dp = intel_attached_dp(connector);
@@ -914,9 +914,9 @@ void intel_edp_backlight_power(struct intel_connector
*connector, bool enable)
enable ? "enable" : "disable");
if (enable)
- _intel_edp_backlight_on(intel_dp);
+ intel_pps_backlight_on(intel_dp);
else
- _intel_edp_backlight_off(intel_dp);
+ intel_pps_backlight_off(intel_dp);
}
static void vlv_detach_power_sequencer(struct intel_dp *intel_dp)
diff --git a/drivers/gpu/drm/i915/display/intel_pps.h
b/drivers/gpu/drm/i915/display/intel_pps.h
index f44e6ce9e8c1..81e4e9fc3cf5 100644
--- a/drivers/gpu/drm/i915/display/intel_pps.h
+++ b/drivers/gpu/drm/i915/display/intel_pps.h
@@ -23,9 +23,9 @@ intel_wakeref_t intel_pps_unlock(struct intel_dp *intel_dp,
intel_wakeref_t wake
for ((wf) = intel_pps_lock(dp); (wf); (wf) = intel_pps_unlock((dp),
(wf)))
void intel_dp_check_edp(struct intel_dp *intel_dp);
-void _intel_edp_backlight_on(struct intel_dp *intel_dp);
-void _intel_edp_backlight_off(struct intel_dp *intel_dp);
-void intel_edp_backlight_power(struct intel_connector *connector, bool enable);
+void intel_pps_backlight_on(struct intel_dp *intel_dp);
+void intel_pps_backlight_off(struct intel_dp *intel_dp);
+void intel_pps_backlight_power(struct intel_connector *connector, bool enable);
bool edp_panel_vdd_on(struct intel_dp *intel_dp);
void edp_panel_vdd_off(struct intel_dp *intel_dp, bool sync);
--
2.20.1
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH 01/13] drm/i915/pps: abstract panel power sequencer from intel_dp.c
On Mon, 04 Jan 2021, Jani Nikula wrote: > On Mon, 28 Dec 2020, "Gupta, Anshuman" wrote: >>> -Original Message- >>> From: Intel-gfx On Behalf Of Jani >>> Nikula >>> Sent: Tuesday, December 22, 2020 8:20 PM >>> To: intel-gfx@lists.freedesktop.org >>> Cc: Nikula, Jani >>> Subject: [Intel-gfx] [PATCH 01/13] drm/i915/pps: abstract panel power >>> sequencer from intel_dp.c >>> >>> In a long overdue refactoring, split out all panel sequencer code from >>> intel_dp.c to new intel_pps.[ch]. >>> >>> The first part is mostly just code movement as-is, without cleanups. >>> >>> We need to add a vlv_get_dpll() helper to get at the vlv/chv dpll from >>> pps code. >> IMHO functions intel_dp_init_panel_power_sequencer, >> intel_dp_init_panel_power_sequencer_registers, >> intel_dp_pps_init suits a intel_edp_* prefix. > > This patch just moves code. The rename would be a separate change on > top. Possibly with intel_pps prefix instead because they're not so much > about dp or edp as about pps. I've added some additional renames in v2. BR, Jani. -- Jani Nikula, Intel Open Source Graphics Center ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH v2 04/17] drm/i915/pps: rename intel_edp_panel_* to intel_pps_*
Follow the usual naming pattern for functions. We don't need to repeat
"panel" here. No functional changes.
v2: Fix comment (Anshuman)
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/i915/display/intel_ddi.c | 8
drivers/gpu/drm/i915/display/intel_dp.c | 10 +-
drivers/gpu/drm/i915/display/intel_pps.c | 17 -
drivers/gpu/drm/i915/display/intel_pps.h | 11 +--
4 files changed, 22 insertions(+), 24 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c
b/drivers/gpu/drm/i915/display/intel_ddi.c
index f09a597bf730..243ab635aa34 100644
--- a/drivers/gpu/drm/i915/display/intel_ddi.c
+++ b/drivers/gpu/drm/i915/display/intel_ddi.c
@@ -3592,7 +3592,7 @@ static void tgl_ddi_pre_enable_dp(struct
intel_atomic_state *state,
*/
/* 2. Enable Panel Power if PPS is required */
- intel_edp_panel_on(intel_dp);
+ intel_pps_on(intel_dp);
/*
* 3. For non-TBT Type-C ports, set FIA lane count
@@ -3735,7 +3735,7 @@ static void hsw_ddi_pre_enable_dp(struct
intel_atomic_state *state,
crtc_state->port_clock,
crtc_state->lane_count);
- intel_edp_panel_on(intel_dp);
+ intel_pps_on(intel_dp);
intel_ddi_clk_select(encoder, crtc_state);
@@ -3977,8 +3977,8 @@ static void intel_ddi_post_disable_dp(struct
intel_atomic_state *state,
if (INTEL_GEN(dev_priv) >= 12)
intel_ddi_disable_pipe_clock(old_crtc_state);
- intel_edp_panel_vdd_on(intel_dp);
- intel_edp_panel_off(intel_dp);
+ intel_pps_vdd_on(intel_dp);
+ intel_pps_off(intel_dp);
if (!intel_phy_is_tc(dev_priv, phy) ||
dig_port->tc_mode != TC_PORT_TBT_ALT)
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c
b/drivers/gpu/drm/i915/display/intel_dp.c
index 421e68bb436f..eac674ad91c8 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -3001,10 +3001,10 @@ static void intel_disable_dp(struct intel_atomic_state
*state,
/* Make sure the panel is off before trying to change the mode. But also
* ensure that we have vdd while we switch off the panel. */
- intel_edp_panel_vdd_on(intel_dp);
+ intel_pps_vdd_on(intel_dp);
intel_edp_backlight_off(old_conn_state);
intel_dp_set_power(intel_dp, DP_SET_POWER_D3);
- intel_edp_panel_off(intel_dp);
+ intel_pps_off(intel_dp);
intel_dp->frl.is_trained = false;
intel_dp->frl.trained_rate_gbps = 0;
}
@@ -6339,7 +6339,7 @@ void intel_dp_encoder_reset(struct drm_encoder *encoder)
* something nasty with it.
*/
intel_dp_pps_init(intel_dp);
- intel_edp_panel_vdd_sanitize(intel_dp);
+ intel_pps_vdd_sanitize(intel_dp);
}
}
}
@@ -6513,7 +6513,7 @@ intel_dp_hpd_pulse(struct intel_digital_port *dig_port,
bool long_hpd)
struct intel_dp *intel_dp = &dig_port->dp;
if (dig_port->base.type == INTEL_OUTPUT_EDP &&
- (long_hpd || !intel_edp_have_power(intel_dp))) {
+ (long_hpd || !intel_pps_have_power(intel_dp))) {
/*
* vdd off can generate a long/short pulse on eDP which
* would require vdd on to handle it, and thus we
@@ -7071,7 +7071,7 @@ static bool intel_edp_init_connector(struct intel_dp
*intel_dp,
with_intel_pps_lock(intel_dp, wakeref) {
intel_dp_init_panel_power_timestamps(intel_dp);
intel_dp_pps_init(intel_dp);
- intel_edp_panel_vdd_sanitize(intel_dp);
+ intel_pps_vdd_sanitize(intel_dp);
}
/* Cache DPCD and EDID for edp. */
diff --git a/drivers/gpu/drm/i915/display/intel_pps.c
b/drivers/gpu/drm/i915/display/intel_pps.c
index 36d8782d8df1..59215cfd7d97 100644
--- a/drivers/gpu/drm/i915/display/intel_pps.c
+++ b/drivers/gpu/drm/i915/display/intel_pps.c
@@ -558,7 +558,7 @@ static u32 ilk_get_pp_control(struct intel_dp *intel_dp)
/*
* Must be paired with edp_panel_vdd_off().
* Must hold pps_mutex around the whole on/off sequence.
- * Can be nested with intel_edp_panel_vdd_{on,off}() calls.
+ * Can be nested with intel_pps_vdd_{on,off}() calls.
*/
bool edp_panel_vdd_on(struct intel_dp *intel_dp)
{
@@ -616,13 +616,12 @@ bool edp_panel_vdd_on(struct intel_dp *intel_dp)
}
/*
- * Must be paired with intel_edp_panel_vdd_off() or
- * intel_edp_panel_off().
+ * Must be paired with intel_pps_off().
* Nested calls to these functions are not allowed since
* we drop the lock. Caller must use some higher level
* locking to prevent nested calls from other threads.
*/
-void intel_edp_panel_vdd_on(struct intel_dp *intel_dp)
+void intel_pps_vdd_on(struct intel_dp *intel_dp)
{
intel_wakeref_t wakeref
[Intel-gfx] [PATCH v2 05/17] drm/i915/pps: rename edp_panel_* to intel_pps_*_unlocked
Follow the usual naming pattern for functions, both for the prefix and
the _unlocked suffix for functions that expect the lock to be held when
calling. No functional changes.
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/i915/display/intel_dp.c | 16 +++
drivers/gpu/drm/i915/display/intel_pps.c | 26
drivers/gpu/drm/i915/display/intel_pps.h | 10 -
3 files changed, 26 insertions(+), 26 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c
b/drivers/gpu/drm/i915/display/intel_dp.c
index eac674ad91c8..1384f1d3a9cf 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -1061,7 +1061,7 @@ intel_dp_aux_xfer(struct intel_dp *intel_dp,
* to turn it off. But for eg. i2c-dev access we need to turn it on/off
* ourselves.
*/
- vdd = edp_panel_vdd_on(intel_dp);
+ vdd = intel_pps_vdd_on_unlocked(intel_dp);
/* dp aux is extremely sensitive to irq latency, hence request the
* lowest possible wakeup latency and so prevent the cpu from going into
@@ -1203,7 +1203,7 @@ intel_dp_aux_xfer(struct intel_dp *intel_dp,
cpu_latency_qos_update_request(&intel_dp->pm_qos, PM_QOS_DEFAULT_VALUE);
if (vdd)
- edp_panel_vdd_off(intel_dp, false);
+ intel_pps_vdd_off_unlocked(intel_dp, false);
intel_pps_unlock(intel_dp, pps_wakeref);
intel_display_power_put_async(i915, aux_domain, aux_wakeref);
@@ -3520,9 +3520,9 @@ static void intel_enable_dp(struct intel_atomic_state
*state,
intel_dp_enable_port(intel_dp, pipe_config);
- edp_panel_vdd_on(intel_dp);
- edp_panel_on(intel_dp);
- edp_panel_vdd_off(intel_dp, true);
+ intel_pps_vdd_on_unlocked(intel_dp);
+ intel_pps_on_unlocked(intel_dp);
+ intel_pps_vdd_off_unlocked(intel_dp, true);
}
if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
@@ -6258,7 +6258,7 @@ void intel_dp_encoder_flush_work(struct drm_encoder
*encoder)
* Make sure vdd is actually turned off here.
*/
with_intel_pps_lock(intel_dp, wakeref)
- edp_panel_vdd_off_sync(intel_dp);
+ intel_pps_vdd_off_sync_unlocked(intel_dp);
}
intel_dp_aux_fini(intel_dp);
@@ -6286,7 +6286,7 @@ void intel_dp_encoder_suspend(struct intel_encoder
*intel_encoder)
*/
cancel_delayed_work_sync(&intel_dp->panel_vdd_work);
with_intel_pps_lock(intel_dp, wakeref)
- edp_panel_vdd_off_sync(intel_dp);
+ intel_pps_vdd_off_sync_unlocked(intel_dp);
}
void intel_dp_encoder_shutdown(struct intel_encoder *intel_encoder)
@@ -7146,7 +7146,7 @@ static bool intel_edp_init_connector(struct intel_dp
*intel_dp,
* Make sure vdd is actually turned off here.
*/
with_intel_pps_lock(intel_dp, wakeref)
- edp_panel_vdd_off_sync(intel_dp);
+ intel_pps_vdd_off_sync_unlocked(intel_dp);
return false;
}
diff --git a/drivers/gpu/drm/i915/display/intel_pps.c
b/drivers/gpu/drm/i915/display/intel_pps.c
index 59215cfd7d97..fd3677948800 100644
--- a/drivers/gpu/drm/i915/display/intel_pps.c
+++ b/drivers/gpu/drm/i915/display/intel_pps.c
@@ -556,11 +556,11 @@ static u32 ilk_get_pp_control(struct intel_dp *intel_dp)
}
/*
- * Must be paired with edp_panel_vdd_off().
+ * Must be paired with intel_pps_vdd_off_unlocked().
* Must hold pps_mutex around the whole on/off sequence.
* Can be nested with intel_pps_vdd_{on,off}() calls.
*/
-bool edp_panel_vdd_on(struct intel_dp *intel_dp)
+bool intel_pps_vdd_on_unlocked(struct intel_dp *intel_dp)
{
struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
@@ -631,13 +631,13 @@ void intel_pps_vdd_on(struct intel_dp *intel_dp)
vdd = false;
with_intel_pps_lock(intel_dp, wakeref)
- vdd = edp_panel_vdd_on(intel_dp);
+ vdd = intel_pps_vdd_on_unlocked(intel_dp);
I915_STATE_WARN(!vdd, "[ENCODER:%d:%s] VDD already requested on\n",
dp_to_dig_port(intel_dp)->base.base.base.id,
dp_to_dig_port(intel_dp)->base.base.name);
}
-void edp_panel_vdd_off_sync(struct intel_dp *intel_dp)
+void intel_pps_vdd_off_sync_unlocked(struct intel_dp *intel_dp)
{
struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
struct intel_digital_port *dig_port =
@@ -687,7 +687,7 @@ void edp_panel_vdd_work(struct work_struct *__work)
with_intel_pps_lock(intel_dp, wakeref) {
if (!intel_dp->want_panel_vdd)
- edp_panel_vdd_off_sync(intel_dp);
+ intel_pps_vdd_off_sync_unlocked(intel_dp);
}
}
[Intel-gfx] [PATCH v2 06/17] drm/i915/pps: abstract intel_pps_vdd_off_sync
Add a locked version of intel_pps_vdd_off_sync_unlocked() that does
everything the callers expect it to. No functional changes.
v2: Fix typo (Anshuman)
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/i915/display/intel_dp.c | 31 +++-
drivers/gpu/drm/i915/display/intel_pps.c | 18 +-
drivers/gpu/drm/i915/display/intel_pps.h | 2 +-
3 files changed, 21 insertions(+), 30 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c
b/drivers/gpu/drm/i915/display/intel_dp.c
index 1384f1d3a9cf..bff5e735a92e 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -6249,17 +6249,8 @@ void intel_dp_encoder_flush_work(struct drm_encoder
*encoder)
struct intel_dp *intel_dp = &dig_port->dp;
intel_dp_mst_encoder_cleanup(dig_port);
- if (intel_dp_is_edp(intel_dp)) {
- intel_wakeref_t wakeref;
- cancel_delayed_work_sync(&intel_dp->panel_vdd_work);
- /*
-* vdd might still be enabled do to the delayed vdd off.
-* Make sure vdd is actually turned off here.
-*/
- with_intel_pps_lock(intel_dp, wakeref)
- intel_pps_vdd_off_sync_unlocked(intel_dp);
- }
+ intel_pps_vdd_off_sync(intel_dp);
intel_dp_aux_fini(intel_dp);
}
@@ -6275,18 +6266,8 @@ static void intel_dp_encoder_destroy(struct drm_encoder
*encoder)
void intel_dp_encoder_suspend(struct intel_encoder *intel_encoder)
{
struct intel_dp *intel_dp = enc_to_intel_dp(intel_encoder);
- intel_wakeref_t wakeref;
-
- if (!intel_dp_is_edp(intel_dp))
- return;
- /*
-* vdd might still be enabled do to the delayed vdd off.
-* Make sure vdd is actually turned off here.
-*/
- cancel_delayed_work_sync(&intel_dp->panel_vdd_work);
- with_intel_pps_lock(intel_dp, wakeref)
- intel_pps_vdd_off_sync_unlocked(intel_dp);
+ intel_pps_vdd_off_sync(intel_dp);
}
void intel_dp_encoder_shutdown(struct intel_encoder *intel_encoder)
@@ -7140,13 +7121,7 @@ static bool intel_edp_init_connector(struct intel_dp
*intel_dp,
return true;
out_vdd_off:
- cancel_delayed_work_sync(&intel_dp->panel_vdd_work);
- /*
-* vdd might still be enabled do to the delayed vdd off.
-* Make sure vdd is actually turned off here.
-*/
- with_intel_pps_lock(intel_dp, wakeref)
- intel_pps_vdd_off_sync_unlocked(intel_dp);
+ intel_pps_vdd_off_sync(intel_dp);
return false;
}
diff --git a/drivers/gpu/drm/i915/display/intel_pps.c
b/drivers/gpu/drm/i915/display/intel_pps.c
index fd3677948800..b6c07694ae9d 100644
--- a/drivers/gpu/drm/i915/display/intel_pps.c
+++ b/drivers/gpu/drm/i915/display/intel_pps.c
@@ -637,7 +637,7 @@ void intel_pps_vdd_on(struct intel_dp *intel_dp)
dp_to_dig_port(intel_dp)->base.base.name);
}
-void intel_pps_vdd_off_sync_unlocked(struct intel_dp *intel_dp)
+static void intel_pps_vdd_off_sync_unlocked(struct intel_dp *intel_dp)
{
struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
struct intel_digital_port *dig_port =
@@ -678,6 +678,22 @@ void intel_pps_vdd_off_sync_unlocked(struct intel_dp
*intel_dp)
fetch_and_zero(&intel_dp->vdd_wakeref));
}
+void intel_pps_vdd_off_sync(struct intel_dp *intel_dp)
+{
+ intel_wakeref_t wakeref;
+
+ if (!intel_dp_is_edp(intel_dp))
+ return;
+
+ cancel_delayed_work_sync(&intel_dp->panel_vdd_work);
+ /*
+* vdd might still be enabled due to the delayed vdd off.
+* Make sure vdd is actually turned off here.
+*/
+ with_intel_pps_lock(intel_dp, wakeref)
+ intel_pps_vdd_off_sync_unlocked(intel_dp);
+}
+
void edp_panel_vdd_work(struct work_struct *__work)
{
struct intel_dp *intel_dp =
diff --git a/drivers/gpu/drm/i915/display/intel_pps.h
b/drivers/gpu/drm/i915/display/intel_pps.h
index e7f0473be9a7..3cab183658c6 100644
--- a/drivers/gpu/drm/i915/display/intel_pps.h
+++ b/drivers/gpu/drm/i915/display/intel_pps.h
@@ -29,7 +29,6 @@ void intel_pps_backlight_power(struct intel_connector
*connector, bool enable);
bool intel_pps_vdd_on_unlocked(struct intel_dp *intel_dp);
void intel_pps_vdd_off_unlocked(struct intel_dp *intel_dp, bool sync);
-void intel_pps_vdd_off_sync_unlocked(struct intel_dp *intel_dp);
void intel_pps_on_unlocked(struct intel_dp *intel_dp);
void intel_pps_off_unlocked(struct intel_dp *intel_dp);
void edp_panel_vdd_work(struct work_struct *__work);
@@ -38,6 +37,7 @@ void intel_pps_vdd_sanitize(struct intel_dp *intel_dp);
void intel_pps_vdd_on(struct intel_dp *intel_dp);
void intel_pps_on(struct intel_dp *intel_dp);
void intel_pps_off(struct intel_dp *intel_dp);
+void intel_pps_vdd_off_sync(struct in
[Intel-gfx] [PATCH v2 07/17] drm/i915/pps: add higher level intel_pps_init() call
Add a new init call to be called only once, unlike some of the other
various init calls. This lets us hide more functions within
intel_pps.c. No functional changes.
Reviewed-by: Anshuman Gupta
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/i915/display/intel_dp.c | 9 +
drivers/gpu/drm/i915/display/intel_pps.c | 17 +++--
drivers/gpu/drm/i915/display/intel_pps.h | 3 +--
3 files changed, 17 insertions(+), 12 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c
b/drivers/gpu/drm/i915/display/intel_dp.c
index bff5e735a92e..31c5474f85d6 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -7026,14 +7026,11 @@ static bool intel_edp_init_connector(struct intel_dp
*intel_dp,
struct drm_display_mode *downclock_mode = NULL;
bool has_dpcd;
enum pipe pipe = INVALID_PIPE;
- intel_wakeref_t wakeref;
struct edid *edid;
if (!intel_dp_is_edp(intel_dp))
return true;
- INIT_DELAYED_WORK(&intel_dp->panel_vdd_work, edp_panel_vdd_work);
-
/*
* On IBX/CPT we may get here with LVDS already registered. Since the
* driver uses the only internal power sequencer available for both
@@ -7049,11 +7046,7 @@ static bool intel_edp_init_connector(struct intel_dp
*intel_dp,
return false;
}
- with_intel_pps_lock(intel_dp, wakeref) {
- intel_dp_init_panel_power_timestamps(intel_dp);
- intel_dp_pps_init(intel_dp);
- intel_pps_vdd_sanitize(intel_dp);
- }
+ intel_pps_init(intel_dp);
/* Cache DPCD and EDID for edp. */
has_dpcd = intel_edp_init_dpcd(intel_dp);
diff --git a/drivers/gpu/drm/i915/display/intel_pps.c
b/drivers/gpu/drm/i915/display/intel_pps.c
index b6c07694ae9d..799190fafa4f 100644
--- a/drivers/gpu/drm/i915/display/intel_pps.c
+++ b/drivers/gpu/drm/i915/display/intel_pps.c
@@ -694,7 +694,7 @@ void intel_pps_vdd_off_sync(struct intel_dp *intel_dp)
intel_pps_vdd_off_sync_unlocked(intel_dp);
}
-void edp_panel_vdd_work(struct work_struct *__work)
+static void edp_panel_vdd_work(struct work_struct *__work)
{
struct intel_dp *intel_dp =
container_of(to_delayed_work(__work),
@@ -1078,7 +1078,7 @@ bool intel_pps_have_power(struct intel_dp *intel_dp)
return have_power;
}
-void intel_dp_init_panel_power_timestamps(struct intel_dp *intel_dp)
+static void intel_dp_init_panel_power_timestamps(struct intel_dp *intel_dp)
{
intel_dp->panel_power_off_time = ktime_get_boottime();
intel_dp->last_power_on = jiffies;
@@ -1348,3 +1348,16 @@ void intel_dp_pps_init(struct intel_dp *intel_dp)
intel_dp_init_panel_power_sequencer_registers(intel_dp, false);
}
}
+
+void intel_pps_init(struct intel_dp *intel_dp)
+{
+ intel_wakeref_t wakeref;
+
+ INIT_DELAYED_WORK(&intel_dp->panel_vdd_work, edp_panel_vdd_work);
+
+ with_intel_pps_lock(intel_dp, wakeref) {
+ intel_dp_init_panel_power_timestamps(intel_dp);
+ intel_dp_pps_init(intel_dp);
+ intel_pps_vdd_sanitize(intel_dp);
+ }
+}
diff --git a/drivers/gpu/drm/i915/display/intel_pps.h
b/drivers/gpu/drm/i915/display/intel_pps.h
index 3cab183658c6..53c0fafd1440 100644
--- a/drivers/gpu/drm/i915/display/intel_pps.h
+++ b/drivers/gpu/drm/i915/display/intel_pps.h
@@ -31,7 +31,6 @@ bool intel_pps_vdd_on_unlocked(struct intel_dp *intel_dp);
void intel_pps_vdd_off_unlocked(struct intel_dp *intel_dp, bool sync);
void intel_pps_on_unlocked(struct intel_dp *intel_dp);
void intel_pps_off_unlocked(struct intel_dp *intel_dp);
-void edp_panel_vdd_work(struct work_struct *__work);
void intel_pps_vdd_sanitize(struct intel_dp *intel_dp);
void intel_pps_vdd_on(struct intel_dp *intel_dp);
@@ -42,9 +41,9 @@ bool intel_pps_have_power(struct intel_dp *intel_dp);
void wait_panel_power_cycle(struct intel_dp *intel_dp);
+void intel_pps_init(struct intel_dp *intel_dp);
void intel_dp_pps_init(struct intel_dp *intel_dp);
void intel_power_sequencer_reset(struct drm_i915_private *i915);
-void intel_dp_init_panel_power_timestamps(struct intel_dp *intel_dp);
void vlv_init_panel_power_sequencer(struct intel_encoder *encoder,
const struct intel_crtc_state *crtc_state);
--
2.20.1
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH v2 08/17] drm/i915/pps: abstract intel_pps_encoder_reset()
Add an "encoder reset" call to hide some more pps functions, and clean
up the callers. A minor functional change is not holding the pps lock
across the whole operation in intel_dp_encoder_reset, but instead doing
it in two steps.
v2: rename intel_pps_reinit to intel_pps_encoder_reset for clarity
Reviewed-by: Anshuman Gupta
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/i915/display/intel_dp.c | 20 +---
drivers/gpu/drm/i915/display/intel_pps.c | 21 +++--
drivers/gpu/drm/i915/display/intel_pps.h | 3 +--
3 files changed, 25 insertions(+), 19 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c
b/drivers/gpu/drm/i915/display/intel_dp.c
index 31c5474f85d6..cfaadeaf9f00 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -6299,30 +6299,20 @@ void intel_dp_encoder_reset(struct drm_encoder *encoder)
{
struct drm_i915_private *dev_priv = to_i915(encoder->dev);
struct intel_dp *intel_dp = enc_to_intel_dp(to_intel_encoder(encoder));
- intel_wakeref_t wakeref;
if (!HAS_DDI(dev_priv))
intel_dp->DP = intel_de_read(dev_priv, intel_dp->output_reg);
intel_dp->reset_link_params = true;
- if (!IS_VALLEYVIEW(dev_priv) && !IS_CHERRYVIEW(dev_priv) &&
- !intel_dp_is_edp(intel_dp))
- return;
+ if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
+ intel_wakeref_t wakeref;
- with_intel_pps_lock(intel_dp, wakeref) {
- if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
+ with_intel_pps_lock(intel_dp, wakeref)
intel_dp->active_pipe = vlv_active_pipe(intel_dp);
-
- if (intel_dp_is_edp(intel_dp)) {
- /*
-* Reinit the power sequencer, in case BIOS did
-* something nasty with it.
-*/
- intel_dp_pps_init(intel_dp);
- intel_pps_vdd_sanitize(intel_dp);
- }
}
+
+ intel_pps_encoder_reset(intel_dp);
}
static int intel_modeset_tile_group(struct intel_atomic_state *state,
diff --git a/drivers/gpu/drm/i915/display/intel_pps.c
b/drivers/gpu/drm/i915/display/intel_pps.c
index 799190fafa4f..3b962be4f4c0 100644
--- a/drivers/gpu/drm/i915/display/intel_pps.c
+++ b/drivers/gpu/drm/i915/display/intel_pps.c
@@ -1040,7 +1040,7 @@ void vlv_init_panel_power_sequencer(struct intel_encoder
*encoder,
intel_dp_init_panel_power_sequencer_registers(intel_dp, true);
}
-void intel_pps_vdd_sanitize(struct intel_dp *intel_dp)
+static void intel_pps_vdd_sanitize(struct intel_dp *intel_dp)
{
struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
@@ -1337,7 +1337,7 @@ intel_dp_init_panel_power_sequencer_registers(struct
intel_dp *intel_dp,
(intel_de_read(dev_priv, regs.pp_ctrl) &
BXT_POWER_CYCLE_DELAY_MASK));
}
-void intel_dp_pps_init(struct intel_dp *intel_dp)
+static void intel_dp_pps_init(struct intel_dp *intel_dp)
{
struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
@@ -1349,6 +1349,23 @@ void intel_dp_pps_init(struct intel_dp *intel_dp)
}
}
+void intel_pps_encoder_reset(struct intel_dp *intel_dp)
+{
+ intel_wakeref_t wakeref;
+
+ if (!intel_dp_is_edp(intel_dp))
+ return;
+
+ with_intel_pps_lock(intel_dp, wakeref) {
+ /*
+* Reinit the power sequencer, in case BIOS did something nasty
+* with it.
+*/
+ intel_dp_pps_init(intel_dp);
+ intel_pps_vdd_sanitize(intel_dp);
+ }
+}
+
void intel_pps_init(struct intel_dp *intel_dp)
{
intel_wakeref_t wakeref;
diff --git a/drivers/gpu/drm/i915/display/intel_pps.h
b/drivers/gpu/drm/i915/display/intel_pps.h
index 53c0fafd1440..7c3b5ea4f47b 100644
--- a/drivers/gpu/drm/i915/display/intel_pps.h
+++ b/drivers/gpu/drm/i915/display/intel_pps.h
@@ -32,7 +32,6 @@ void intel_pps_vdd_off_unlocked(struct intel_dp *intel_dp,
bool sync);
void intel_pps_on_unlocked(struct intel_dp *intel_dp);
void intel_pps_off_unlocked(struct intel_dp *intel_dp);
-void intel_pps_vdd_sanitize(struct intel_dp *intel_dp);
void intel_pps_vdd_on(struct intel_dp *intel_dp);
void intel_pps_on(struct intel_dp *intel_dp);
void intel_pps_off(struct intel_dp *intel_dp);
@@ -42,7 +41,7 @@ bool intel_pps_have_power(struct intel_dp *intel_dp);
void wait_panel_power_cycle(struct intel_dp *intel_dp);
void intel_pps_init(struct intel_dp *intel_dp);
-void intel_dp_pps_init(struct intel_dp *intel_dp);
+void intel_pps_encoder_reset(struct intel_dp *intel_dp);
void intel_power_sequencer_reset(struct drm_i915_private *i915);
void vlv_init_panel_power_sequen
[Intel-gfx] [PATCH v2 09/17] drm/i915/pps: rename intel_dp_check_edp to intel_pps_check_power_unlocked
Follow the usual naming pattern for functions. No functional changes.
Reviewed-by: Anshuman Gupta
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/i915/display/intel_dp.c | 2 +-
drivers/gpu/drm/i915/display/intel_pps.c | 2 +-
drivers/gpu/drm/i915/display/intel_pps.h | 2 +-
3 files changed, 3 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c
b/drivers/gpu/drm/i915/display/intel_dp.c
index cfaadeaf9f00..1685e48b17cd 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -1069,7 +1069,7 @@ intel_dp_aux_xfer(struct intel_dp *intel_dp,
*/
cpu_latency_qos_update_request(&intel_dp->pm_qos, 0);
- intel_dp_check_edp(intel_dp);
+ intel_pps_check_power_unlocked(intel_dp);
/* Try to wait for any previous AUX channel activity */
for (try = 0; try < 3; try++) {
diff --git a/drivers/gpu/drm/i915/display/intel_pps.c
b/drivers/gpu/drm/i915/display/intel_pps.c
index 3b962be4f4c0..9e5744578b26 100644
--- a/drivers/gpu/drm/i915/display/intel_pps.c
+++ b/drivers/gpu/drm/i915/display/intel_pps.c
@@ -428,7 +428,7 @@ static bool edp_have_panel_vdd(struct intel_dp *intel_dp)
return intel_de_read(dev_priv, _pp_ctrl_reg(intel_dp)) & EDP_FORCE_VDD;
}
-void intel_dp_check_edp(struct intel_dp *intel_dp)
+void intel_pps_check_power_unlocked(struct intel_dp *intel_dp)
{
struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
diff --git a/drivers/gpu/drm/i915/display/intel_pps.h
b/drivers/gpu/drm/i915/display/intel_pps.h
index 7c3b5ea4f47b..e0391c9c8383 100644
--- a/drivers/gpu/drm/i915/display/intel_pps.h
+++ b/drivers/gpu/drm/i915/display/intel_pps.h
@@ -22,7 +22,6 @@ intel_wakeref_t intel_pps_unlock(struct intel_dp *intel_dp,
intel_wakeref_t wake
#define with_intel_pps_lock(dp, wf)
\
for ((wf) = intel_pps_lock(dp); (wf); (wf) = intel_pps_unlock((dp),
(wf)))
-void intel_dp_check_edp(struct intel_dp *intel_dp);
void intel_pps_backlight_on(struct intel_dp *intel_dp);
void intel_pps_backlight_off(struct intel_dp *intel_dp);
void intel_pps_backlight_power(struct intel_connector *connector, bool enable);
@@ -31,6 +30,7 @@ bool intel_pps_vdd_on_unlocked(struct intel_dp *intel_dp);
void intel_pps_vdd_off_unlocked(struct intel_dp *intel_dp, bool sync);
void intel_pps_on_unlocked(struct intel_dp *intel_dp);
void intel_pps_off_unlocked(struct intel_dp *intel_dp);
+void intel_pps_check_power_unlocked(struct intel_dp *intel_dp);
void intel_pps_vdd_on(struct intel_dp *intel_dp);
void intel_pps_on(struct intel_dp *intel_dp);
--
2.20.1
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH v2 10/17] drm/i915/pps: rename intel_power_sequencer_reset to intel_pps_reset_all
Follow the usual naming pattern for functions. "reset all" because it
iterates over all DP encoders. No functional changes.
Reviewed-by: Anshuman Gupta
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/i915/display/intel_display_power.c | 4 ++--
drivers/gpu/drm/i915/display/intel_pps.c | 5 ++---
drivers/gpu/drm/i915/display/intel_pps.h | 2 +-
3 files changed, 5 insertions(+), 6 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c
b/drivers/gpu/drm/i915/display/intel_display_power.c
index a11bd8213df4..c11c37c65d86 100644
--- a/drivers/gpu/drm/i915/display/intel_display_power.c
+++ b/drivers/gpu/drm/i915/display/intel_display_power.c
@@ -936,7 +936,7 @@ static void bxt_enable_dc9(struct drm_i915_private
*dev_priv)
* because PPS registers are always on.
*/
if (!HAS_PCH_SPLIT(dev_priv))
- intel_power_sequencer_reset(dev_priv);
+ intel_pps_reset_all(dev_priv);
gen9_set_dc_state(dev_priv, DC_STATE_EN_DC9);
}
@@ -1446,7 +1446,7 @@ static void vlv_display_power_well_deinit(struct
drm_i915_private *dev_priv)
/* make sure we're done processing display irqs */
intel_synchronize_irq(dev_priv);
- intel_power_sequencer_reset(dev_priv);
+ intel_pps_reset_all(dev_priv);
/* Prevent us from re-enabling polling on accident in late suspend */
if (!dev_priv->drm.dev->power.is_suspended)
diff --git a/drivers/gpu/drm/i915/display/intel_pps.c
b/drivers/gpu/drm/i915/display/intel_pps.c
index 9e5744578b26..d396ee5f6f69 100644
--- a/drivers/gpu/drm/i915/display/intel_pps.c
+++ b/drivers/gpu/drm/i915/display/intel_pps.c
@@ -22,8 +22,7 @@ intel_wakeref_t intel_pps_lock(struct intel_dp *intel_dp)
intel_wakeref_t wakeref;
/*
-* See intel_power_sequencer_reset() why we need
-* a power domain reference here.
+* See intel_pps_reset_all() why we need a power domain reference here.
*/
wakeref = intel_display_power_get(dev_priv, POWER_DOMAIN_DISPLAY_CORE);
mutex_lock(&dev_priv->pps_mutex);
@@ -313,7 +312,7 @@ vlv_initial_power_sequencer_setup(struct intel_dp *intel_dp)
intel_dp_init_panel_power_sequencer_registers(intel_dp, false);
}
-void intel_power_sequencer_reset(struct drm_i915_private *dev_priv)
+void intel_pps_reset_all(struct drm_i915_private *dev_priv)
{
struct intel_encoder *encoder;
diff --git a/drivers/gpu/drm/i915/display/intel_pps.h
b/drivers/gpu/drm/i915/display/intel_pps.h
index e0391c9c8383..ecd9ea2a095c 100644
--- a/drivers/gpu/drm/i915/display/intel_pps.h
+++ b/drivers/gpu/drm/i915/display/intel_pps.h
@@ -42,7 +42,7 @@ void wait_panel_power_cycle(struct intel_dp *intel_dp);
void intel_pps_init(struct intel_dp *intel_dp);
void intel_pps_encoder_reset(struct intel_dp *intel_dp);
-void intel_power_sequencer_reset(struct drm_i915_private *i915);
+void intel_pps_reset_all(struct drm_i915_private *i915);
void vlv_init_panel_power_sequencer(struct intel_encoder *encoder,
const struct intel_crtc_state *crtc_state);
--
2.20.1
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH v2 11/17] drm/i915/pps: add locked intel_pps_wait_power_cycle
Prefer keeping the unlocked variants hidden if possible. No functional
changes.
Reviewed-by: Anshuman Gupta
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/i915/display/intel_dp.c | 7 +--
drivers/gpu/drm/i915/display/intel_pps.c | 13 -
drivers/gpu/drm/i915/display/intel_pps.h | 3 +--
3 files changed, 14 insertions(+), 9 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c
b/drivers/gpu/drm/i915/display/intel_dp.c
index 1685e48b17cd..ffb6f6c9b858 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -6273,13 +6273,8 @@ void intel_dp_encoder_suspend(struct intel_encoder
*intel_encoder)
void intel_dp_encoder_shutdown(struct intel_encoder *intel_encoder)
{
struct intel_dp *intel_dp = enc_to_intel_dp(intel_encoder);
- intel_wakeref_t wakeref;
-
- if (!intel_dp_is_edp(intel_dp))
- return;
- with_intel_pps_lock(intel_dp, wakeref)
- wait_panel_power_cycle(intel_dp);
+ intel_pps_wait_power_cycle(intel_dp);
}
static enum pipe vlv_active_pipe(struct intel_dp *intel_dp)
diff --git a/drivers/gpu/drm/i915/display/intel_pps.c
b/drivers/gpu/drm/i915/display/intel_pps.c
index d396ee5f6f69..79276ab20c75 100644
--- a/drivers/gpu/drm/i915/display/intel_pps.c
+++ b/drivers/gpu/drm/i915/display/intel_pps.c
@@ -500,7 +500,7 @@ static void wait_panel_off(struct intel_dp *intel_dp)
wait_panel_status(intel_dp, IDLE_OFF_MASK, IDLE_OFF_VALUE);
}
-void wait_panel_power_cycle(struct intel_dp *intel_dp)
+static void wait_panel_power_cycle(struct intel_dp *intel_dp)
{
struct drm_i915_private *i915 = dp_to_i915(intel_dp);
ktime_t panel_power_on_time;
@@ -522,6 +522,17 @@ void wait_panel_power_cycle(struct intel_dp *intel_dp)
wait_panel_status(intel_dp, IDLE_CYCLE_MASK, IDLE_CYCLE_VALUE);
}
+void intel_pps_wait_power_cycle(struct intel_dp *intel_dp)
+{
+ intel_wakeref_t wakeref;
+
+ if (!intel_dp_is_edp(intel_dp))
+ return;
+
+ with_intel_pps_lock(intel_dp, wakeref)
+ wait_panel_power_cycle(intel_dp);
+}
+
static void wait_backlight_on(struct intel_dp *intel_dp)
{
wait_remaining_ms_from_jiffies(intel_dp->last_power_on,
diff --git a/drivers/gpu/drm/i915/display/intel_pps.h
b/drivers/gpu/drm/i915/display/intel_pps.h
index ecd9ea2a095c..fdf7a17e2dfa 100644
--- a/drivers/gpu/drm/i915/display/intel_pps.h
+++ b/drivers/gpu/drm/i915/display/intel_pps.h
@@ -37,8 +37,7 @@ void intel_pps_on(struct intel_dp *intel_dp);
void intel_pps_off(struct intel_dp *intel_dp);
void intel_pps_vdd_off_sync(struct intel_dp *intel_dp);
bool intel_pps_have_power(struct intel_dp *intel_dp);
-
-void wait_panel_power_cycle(struct intel_dp *intel_dp);
+void intel_pps_wait_power_cycle(struct intel_dp *intel_dp);
void intel_pps_init(struct intel_dp *intel_dp);
void intel_pps_encoder_reset(struct intel_dp *intel_dp);
--
2.20.1
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH v2 12/17] drm/i915/pps: rename vlv_init_panel_power_sequencer to vlv_pps_init
This function is a bit of an outlier, but try to change to a name that
is more in line with the rest of the intel_pps functions. No functional
changes.
Reviewed-by: Anshuman Gupta
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/i915/display/intel_dp.c | 2 +-
drivers/gpu/drm/i915/display/intel_pps.c | 4 ++--
drivers/gpu/drm/i915/display/intel_pps.h | 4 ++--
3 files changed, 5 insertions(+), 5 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c
b/drivers/gpu/drm/i915/display/intel_dp.c
index ffb6f6c9b858..a8835e3b1ac1 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -3516,7 +3516,7 @@ static void intel_enable_dp(struct intel_atomic_state
*state,
with_intel_pps_lock(intel_dp, wakeref) {
if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
- vlv_init_panel_power_sequencer(encoder, pipe_config);
+ vlv_pps_init(encoder, pipe_config);
intel_dp_enable_port(intel_dp, pipe_config);
diff --git a/drivers/gpu/drm/i915/display/intel_pps.c
b/drivers/gpu/drm/i915/display/intel_pps.c
index 79276ab20c75..8925df55e22e 100644
--- a/drivers/gpu/drm/i915/display/intel_pps.c
+++ b/drivers/gpu/drm/i915/display/intel_pps.c
@@ -1005,8 +1005,8 @@ static void vlv_steal_power_sequencer(struct
drm_i915_private *dev_priv,
}
}
-void vlv_init_panel_power_sequencer(struct intel_encoder *encoder,
- const struct intel_crtc_state *crtc_state)
+void vlv_pps_init(struct intel_encoder *encoder,
+ const struct intel_crtc_state *crtc_state)
{
struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
diff --git a/drivers/gpu/drm/i915/display/intel_pps.h
b/drivers/gpu/drm/i915/display/intel_pps.h
index fdf7a17e2dfa..22045c5cdc86 100644
--- a/drivers/gpu/drm/i915/display/intel_pps.h
+++ b/drivers/gpu/drm/i915/display/intel_pps.h
@@ -43,7 +43,7 @@ void intel_pps_init(struct intel_dp *intel_dp);
void intel_pps_encoder_reset(struct intel_dp *intel_dp);
void intel_pps_reset_all(struct drm_i915_private *i915);
-void vlv_init_panel_power_sequencer(struct intel_encoder *encoder,
- const struct intel_crtc_state *crtc_state);
+void vlv_pps_init(struct intel_encoder *encoder,
+ const struct intel_crtc_state *crtc_state);
#endif /* __INTEL_PPS_H__ */
--
2.20.1
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
