Re: [PATCH v2] i915/selftest/igt_mmap: let mmap tests run in kthread
On 2025-03-07 at 12:31:25 GMT, Chris Wilson wrote: > Quoting Mikolaj Wasiak (2025-03-07 08:44:29) > > Hi Krzysztof, > > > > On 2025-03-05 at 17:31:49 +0100, Krzysztof Niemiec wrote: > > > Don't we run into the same issue as in V1, meaning we use an unknown > > > current->active_mm (since we run in a kthread, and cannot control it) to > > > use as the current->mm? Maybe a better approach would be to create a new > > > mm for the duration of the test, similarly to how the patch Janusz > > > mentioned does it? (51104c19d857) > > > > As per discussion with Chris, using active_mm is the correct way of > > enabling current->mm in kthread. On the other hand it may also expose > > issues with underlying tests because they didn't previously run on such > > hardware. I think potential fixes to those tests should be addressed in > > separate patch. > > We've looked at the tests, and they should all be finding unused space > in the mm and cleaning up after themselves... > If that's the case, then the patch is alright. I was mostly worried about messing with userspace memory of a random process. > If we put on our paranoia hats, the biggest problem with borrowing > userspace's mm is that it gives them temporary insight into whatever > we place into that mm. We don't expose any data, unless by error... > Not sure how much effort we want to put on making the selftests paranoia > proof, but that (and the surety of cleaning up afterwards) would be a > good argument for creating a temporary mm for our use. I don't think it's really a secret what the selftest puts in that memory anyway (assuming normal test operation). The only problem I can see with using userspace's mm at the moment (paranoia-wise) is that we only lock the mm for the vma_lookup() check [1], meaning there's a time-of-check-time-of-use situation. IFF userspace can somehow unmap the obj from its side after that check is done, this can potentially mess with kernel memory. I have no earthly idea if this can be really abused though, so it might not even be a real issue. Besides, to achieve that, a malicious process would have to win the kthread active_mm lottery so its mm is used for the selftest, then guess the address of the mmapped object (it's technically logged as debug, but the loglevel might not be set as such), and then race with the kthread so the object is unmapped before use. So a lot of stars have to align. If that is not something we consider a problem, then: Reviewed-by: Krzysztof Niemiec [1]: gem/selftests/i915_gem_mman.c:923 > -Chris Thanks Krzysztof
✓ i915.CI.BAT: success for bits: Fixed-type GENMASK()/BIT() (rev2)
== Series Details == Series: bits: Fixed-type GENMASK()/BIT() (rev2) URL : https://patchwork.freedesktop.org/series/145997/ State : success == Summary == CI Bug Log - changes from CI_DRM_16245 -> Patchwork_145997v2 Summary --- **SUCCESS** No regressions found. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_145997v2/index.html Participating hosts (44 -> 42) -- Missing(2): bat-arlh-2 fi-snb-2520m Known issues Here are the changes found in Patchwork_145997v2 that come from known issues: ### IGT changes ### Issues hit * igt@fbdev@info: - fi-kbl-8809g: NOTRUN -> [SKIP][1] ([i915#1849]) [1]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_145997v2/fi-kbl-8809g/igt@fb...@info.html * igt@gem_huc_copy@huc-copy: - fi-kbl-8809g: NOTRUN -> [SKIP][2] ([i915#2190]) [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_145997v2/fi-kbl-8809g/igt@gem_huc_c...@huc-copy.html * igt@gem_lmem_swapping@parallel-random-engines: - fi-kbl-8809g: NOTRUN -> [SKIP][3] ([i915#4613]) +3 other tests skip [3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_145997v2/fi-kbl-8809g/igt@gem_lmem_swapp...@parallel-random-engines.html * igt@i915_pm_rpm@module-reload: - bat-dg2-11: [PASS][4] -> [FAIL][5] ([i915#13633]) [4]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16245/bat-dg2-11/igt@i915_pm_...@module-reload.html [5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_145997v2/bat-dg2-11/igt@i915_pm_...@module-reload.html - bat-rpls-4: [PASS][6] -> [FAIL][7] ([i915#13633]) [6]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16245/bat-rpls-4/igt@i915_pm_...@module-reload.html [7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_145997v2/bat-rpls-4/igt@i915_pm_...@module-reload.html * igt@kms_dsc@dsc-basic: - fi-kbl-8809g: NOTRUN -> [SKIP][8] +34 other tests skip [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_145997v2/fi-kbl-8809g/igt@kms_...@dsc-basic.html * igt@kms_pipe_crc_basic@nonblocking-crc-frame-sequence: - bat-dg2-11: [PASS][9] -> [SKIP][10] ([i915#9197]) +3 other tests skip [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16245/bat-dg2-11/igt@kms_pipe_crc_ba...@nonblocking-crc-frame-sequence.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_145997v2/bat-dg2-11/igt@kms_pipe_crc_ba...@nonblocking-crc-frame-sequence.html [i915#13633]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/13633 [i915#1849]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/1849 [i915#2190]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/2190 [i915#4613]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4613 [i915#9197]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9197 Build changes - * Linux: CI_DRM_16245 -> Patchwork_145997v2 CI-20190529: 20190529 CI_DRM_16245: 066c46f28642479869d2d1dd27cc6ae476de4abc @ git://anongit.freedesktop.org/gfx-ci/linux IGT_8264: 8264 Patchwork_145997v2: 066c46f28642479869d2d1dd27cc6ae476de4abc @ git://anongit.freedesktop.org/gfx-ci/linux == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_145997v2/index.html
[PATCH 10/14] drm/i915: Extract intel_bw_check_sagv_mask()
From: Ville Syrjälä
Move the bw_state->pipe_sagv_reject computation into intel_bw.c
where it belongs.
Previously we had a complicated dance between watermarks and
sagv which required this to be computed earlier, but that was
changed in commit 5e8146251f7b ("extract intel_bw_check_sagv_mask()")
which allows the whole thing to be cleaned up quite a bit.
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/display/intel_bw.c | 40
drivers/gpu/drm/i915/display/intel_bw.h | 1 +
drivers/gpu/drm/i915/display/skl_watermark.c | 31 ++-
drivers/gpu/drm/i915/display/skl_watermark.h | 1 +
4 files changed, 46 insertions(+), 27 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_bw.c
b/drivers/gpu/drm/i915/display/intel_bw.c
index 6fd6c7b535ed..33ec9f574716 100644
--- a/drivers/gpu/drm/i915/display/intel_bw.c
+++ b/drivers/gpu/drm/i915/display/intel_bw.c
@@ -1408,6 +1408,46 @@ int intel_bw_modeset_checks(struct intel_atomic_state
*state)
return 0;
}
+int intel_bw_check_sagv_mask(struct intel_atomic_state *state)
+{
+ struct intel_display *display = to_intel_display(state);
+ struct drm_i915_private *i915 = to_i915(display->drm);
+ const struct intel_crtc_state *new_crtc_state;
+ const struct intel_bw_state *old_bw_state = NULL;
+ struct intel_bw_state *new_bw_state = NULL;
+ struct intel_crtc *crtc;
+ int ret, i;
+
+ for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) {
+ new_bw_state = intel_atomic_get_bw_state(state);
+ if (IS_ERR(new_bw_state))
+ return PTR_ERR(new_bw_state);
+
+ old_bw_state = intel_atomic_get_old_bw_state(state);
+
+ if (intel_crtc_can_enable_sagv(new_crtc_state))
+ new_bw_state->pipe_sagv_reject &= ~BIT(crtc->pipe);
+ else
+ new_bw_state->pipe_sagv_reject |= BIT(crtc->pipe);
+ }
+
+ if (!new_bw_state)
+ return 0;
+
+ if (intel_can_enable_sagv(i915, new_bw_state) !=
+ intel_can_enable_sagv(i915, old_bw_state)) {
+ ret = intel_atomic_serialize_global_state(&new_bw_state->base);
+ if (ret)
+ return ret;
+ } else if (new_bw_state->pipe_sagv_reject !=
old_bw_state->pipe_sagv_reject) {
+ ret = intel_atomic_lock_global_state(&new_bw_state->base);
+ if (ret)
+ return ret;
+ }
+
+ return 0;
+}
+
int intel_bw_atomic_check(struct intel_atomic_state *state)
{
bool changed = false;
diff --git a/drivers/gpu/drm/i915/display/intel_bw.h
b/drivers/gpu/drm/i915/display/intel_bw.h
index 0efc9858faa1..e5a0ff630438 100644
--- a/drivers/gpu/drm/i915/display/intel_bw.h
+++ b/drivers/gpu/drm/i915/display/intel_bw.h
@@ -68,6 +68,7 @@ intel_atomic_get_bw_state(struct intel_atomic_state *state);
void intel_bw_init_hw(struct drm_i915_private *dev_priv);
int intel_bw_init(struct drm_i915_private *dev_priv);
int intel_bw_modeset_checks(struct intel_atomic_state *state);
+int intel_bw_check_sagv_mask(struct intel_atomic_state *state);
int intel_bw_atomic_check(struct intel_atomic_state *state);
int icl_pcode_restrict_qgv_points(struct drm_i915_private *dev_priv,
u32 points_mask);
diff --git a/drivers/gpu/drm/i915/display/skl_watermark.c
b/drivers/gpu/drm/i915/display/skl_watermark.c
index 58ba99eacd09..80ee9f8ae230 100644
--- a/drivers/gpu/drm/i915/display/skl_watermark.c
+++ b/drivers/gpu/drm/i915/display/skl_watermark.c
@@ -423,7 +423,7 @@ static bool tgl_crtc_can_enable_sagv(const struct
intel_crtc_state *crtc_state)
return true;
}
-static bool intel_crtc_can_enable_sagv(const struct intel_crtc_state
*crtc_state)
+bool intel_crtc_can_enable_sagv(const struct intel_crtc_state *crtc_state)
{
struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
struct drm_i915_private *i915 = to_i915(crtc->base.dev);
@@ -454,20 +454,12 @@ static int intel_compute_sagv_mask(struct
intel_atomic_state *state)
int ret;
struct intel_crtc *crtc;
struct intel_crtc_state *new_crtc_state;
- struct intel_bw_state *new_bw_state = NULL;
- const struct intel_bw_state *old_bw_state = NULL;
int i;
for_each_new_intel_crtc_in_state(state, crtc,
new_crtc_state, i) {
struct skl_pipe_wm *pipe_wm = &new_crtc_state->wm.skl.optimal;
- new_bw_state = intel_atomic_get_bw_state(state);
- if (IS_ERR(new_bw_state))
- return PTR_ERR(new_bw_state);
-
- old_bw_state = intel_atomic_get_old_bw_state(state);
-
/*
* We store use_sagv_wm in the crtc state rather than relying on
* that bw state since we have no convenient way to get at the
Re: [PATCH v6 0/7] bits: Fixed-type GENMASK_U*() and BIT_U*()
On Fri, Mar 07, 2025 at 12:18:02PM -0500, Yury Norov wrote: > No rush, please allow your reviewers a week or two before submitting > a new iteration unless you want to disregard the previous version for > some reason, of course. This will not get into the upcoming merge > window, anyways. > > So, what should I do? Go through the v5 and all discussions in there, > or just jump on this? There is also question to you. Are we going to leave with U128 variants or is it subject to remove? If the latter, can you issue a formal patch? -- With Best Regards, Andy Shevchenko
✓ i915.CI.BAT: success for drm/dp_mst: Fix locking when skipping CSN before topology probing
== Series Details == Series: drm/dp_mst: Fix locking when skipping CSN before topology probing URL : https://patchwork.freedesktop.org/series/146019/ State : success == Summary == CI Bug Log - changes from CI_DRM_16246 -> Patchwork_146019v1 Summary --- **SUCCESS** No regressions found. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_146019v1/index.html Participating hosts (43 -> 43) -- Additional (1): bat-arlh-2 Missing(1): fi-snb-2520m Known issues Here are the changes found in Patchwork_146019v1 that come from known issues: ### IGT changes ### Issues hit * igt@debugfs_test@basic-hwmon: - bat-arlh-2: NOTRUN -> [SKIP][1] ([i915#11346] / [i915#9318]) [1]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_146019v1/bat-arlh-2/igt@debugfs_t...@basic-hwmon.html * igt@fbdev@eof: - bat-arlh-2: NOTRUN -> [SKIP][2] ([i915#11345] / [i915#11346]) +3 other tests skip [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_146019v1/bat-arlh-2/igt@fb...@eof.html * igt@fbdev@info: - bat-arlh-2: NOTRUN -> [SKIP][3] ([i915#11346] / [i915#1849]) [3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_146019v1/bat-arlh-2/igt@fb...@info.html - fi-kbl-8809g: NOTRUN -> [SKIP][4] ([i915#1849]) [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_146019v1/fi-kbl-8809g/igt@fb...@info.html * igt@gem_huc_copy@huc-copy: - fi-kbl-8809g: NOTRUN -> [SKIP][5] ([i915#2190]) [5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_146019v1/fi-kbl-8809g/igt@gem_huc_c...@huc-copy.html * igt@gem_lmem_swapping@basic: - bat-arlh-2: NOTRUN -> [SKIP][6] ([i915#10213] / [i915#11346] / [i915#11671]) +3 other tests skip [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_146019v1/bat-arlh-2/igt@gem_lmem_swapp...@basic.html * igt@gem_lmem_swapping@parallel-random-engines: - fi-kbl-8809g: NOTRUN -> [SKIP][7] ([i915#4613]) +3 other tests skip [7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_146019v1/fi-kbl-8809g/igt@gem_lmem_swapp...@parallel-random-engines.html * igt@gem_mmap@basic: - bat-arlh-2: NOTRUN -> [SKIP][8] ([i915#11343] / [i915#11346]) [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_146019v1/bat-arlh-2/igt@gem_m...@basic.html * igt@gem_render_tiled_blits@basic: - bat-arlh-2: NOTRUN -> [SKIP][9] ([i915#10197] / [i915#10211] / [i915#11346] / [i915#11725]) [9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_146019v1/bat-arlh-2/igt@gem_render_tiled_bl...@basic.html * igt@gem_tiled_blits@basic: - bat-arlh-2: NOTRUN -> [SKIP][10] ([i915#11346] / [i915#12637]) +4 other tests skip [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_146019v1/bat-arlh-2/igt@gem_tiled_bl...@basic.html * igt@gem_tiled_pread_basic: - bat-arlh-2: NOTRUN -> [SKIP][11] ([i915#10206] / [i915#11346] / [i915#11724]) [11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_146019v1/bat-arlh-2/igt@gem_tiled_pread_basic.html * igt@i915_pm_rpm@module-reload: - bat-adls-6: [PASS][12] -> [FAIL][13] ([i915#13633]) [12]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16246/bat-adls-6/igt@i915_pm_...@module-reload.html [13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_146019v1/bat-adls-6/igt@i915_pm_...@module-reload.html - bat-dg1-7: [PASS][14] -> [FAIL][15] ([i915#13633]) [14]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16246/bat-dg1-7/igt@i915_pm_...@module-reload.html [15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_146019v1/bat-dg1-7/igt@i915_pm_...@module-reload.html - bat-rpls-4: [PASS][16] -> [FAIL][17] ([i915#13633]) [16]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16246/bat-rpls-4/igt@i915_pm_...@module-reload.html [17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_146019v1/bat-rpls-4/igt@i915_pm_...@module-reload.html * igt@i915_pm_rps@basic-api: - bat-arlh-2: NOTRUN -> [SKIP][18] ([i915#10209] / [i915#11346] / [i915#11681]) [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_146019v1/bat-arlh-2/igt@i915_pm_...@basic-api.html * igt@i915_selftest@live: - bat-mtlp-8: [PASS][19] -> [DMESG-FAIL][20] ([i915#12061]) +1 other test dmesg-fail [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16246/bat-mtlp-8/igt@i915_selft...@live.html [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_146019v1/bat-mtlp-8/igt@i915_selft...@live.html * igt@i915_selftest@live@workarounds: - bat-arls-6: [PASS][21] -> [DMESG-FAIL][22] ([i915#12061]) +1 other test dmesg-fail [21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16246/bat-arls-6/igt@i915_selftest@l...@workarounds.html [22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_1
✓ i915.CI.BAT: success for drm/i915: sagv/bw cleanup (rev2)
== Series Details == Series: drm/i915: sagv/bw cleanup (rev2) URL : https://patchwork.freedesktop.org/series/146014/ State : success == Summary == CI Bug Log - changes from CI_DRM_16246 -> Patchwork_146014v2 Summary --- **SUCCESS** No regressions found. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_146014v2/index.html Participating hosts (43 -> 43) -- Additional (1): bat-arlh-2 Missing(1): fi-snb-2520m Known issues Here are the changes found in Patchwork_146014v2 that come from known issues: ### IGT changes ### Issues hit * igt@debugfs_test@basic-hwmon: - bat-arlh-2: NOTRUN -> [SKIP][1] ([i915#11346] / [i915#9318]) [1]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_146014v2/bat-arlh-2/igt@debugfs_t...@basic-hwmon.html * igt@dmabuf@all-tests: - bat-apl-1: [PASS][2] -> [INCOMPLETE][3] ([i915#12904]) +1 other test incomplete [2]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16246/bat-apl-1/igt@dma...@all-tests.html [3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_146014v2/bat-apl-1/igt@dma...@all-tests.html * igt@fbdev@eof: - bat-arlh-2: NOTRUN -> [SKIP][4] ([i915#11345] / [i915#11346]) +3 other tests skip [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_146014v2/bat-arlh-2/igt@fb...@eof.html * igt@fbdev@info: - bat-arlh-2: NOTRUN -> [SKIP][5] ([i915#11346] / [i915#1849]) [5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_146014v2/bat-arlh-2/igt@fb...@info.html - fi-kbl-8809g: NOTRUN -> [SKIP][6] ([i915#1849]) [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_146014v2/fi-kbl-8809g/igt@fb...@info.html * igt@gem_huc_copy@huc-copy: - fi-kbl-8809g: NOTRUN -> [SKIP][7] ([i915#2190]) [7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_146014v2/fi-kbl-8809g/igt@gem_huc_c...@huc-copy.html * igt@gem_lmem_swapping@basic: - bat-arlh-2: NOTRUN -> [SKIP][8] ([i915#10213] / [i915#11346] / [i915#11671]) +3 other tests skip [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_146014v2/bat-arlh-2/igt@gem_lmem_swapp...@basic.html * igt@gem_lmem_swapping@parallel-random-engines: - fi-kbl-8809g: NOTRUN -> [SKIP][9] ([i915#4613]) +3 other tests skip [9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_146014v2/fi-kbl-8809g/igt@gem_lmem_swapp...@parallel-random-engines.html * igt@gem_mmap@basic: - bat-arlh-2: NOTRUN -> [SKIP][10] ([i915#11343] / [i915#11346]) [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_146014v2/bat-arlh-2/igt@gem_m...@basic.html * igt@gem_render_tiled_blits@basic: - bat-arlh-2: NOTRUN -> [SKIP][11] ([i915#10197] / [i915#10211] / [i915#11346] / [i915#11725]) [11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_146014v2/bat-arlh-2/igt@gem_render_tiled_bl...@basic.html * igt@gem_tiled_blits@basic: - bat-arlh-2: NOTRUN -> [SKIP][12] ([i915#11346] / [i915#12637]) +4 other tests skip [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_146014v2/bat-arlh-2/igt@gem_tiled_bl...@basic.html * igt@gem_tiled_pread_basic: - bat-arlh-2: NOTRUN -> [SKIP][13] ([i915#10206] / [i915#11346] / [i915#11724]) [13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_146014v2/bat-arlh-2/igt@gem_tiled_pread_basic.html * igt@i915_pm_rpm@module-reload: - bat-dg2-11: [PASS][14] -> [FAIL][15] ([i915#13633]) [14]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16246/bat-dg2-11/igt@i915_pm_...@module-reload.html [15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_146014v2/bat-dg2-11/igt@i915_pm_...@module-reload.html - bat-dg1-7: [PASS][16] -> [FAIL][17] ([i915#13633]) [16]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16246/bat-dg1-7/igt@i915_pm_...@module-reload.html [17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_146014v2/bat-dg1-7/igt@i915_pm_...@module-reload.html * igt@i915_pm_rps@basic-api: - bat-arlh-2: NOTRUN -> [SKIP][18] ([i915#10209] / [i915#11346] / [i915#11681]) [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_146014v2/bat-arlh-2/igt@i915_pm_...@basic-api.html * igt@i915_selftest@live: - bat-mtlp-8: [PASS][19] -> [DMESG-FAIL][20] ([i915#12061]) +1 other test dmesg-fail [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16246/bat-mtlp-8/igt@i915_selft...@live.html [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_146014v2/bat-mtlp-8/igt@i915_selft...@live.html * igt@i915_selftest@live@workarounds: - bat-arls-6: [PASS][21] -> [DMESG-FAIL][22] ([i915#12061]) +1 other test dmesg-fail [21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16246/bat-arls-6/igt@i915_selftest@l...@workarounds.html [22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patch
Re: [PATCH] drm/i915: Increase I915_PARAM_MMAP_GTT_VERSION version to indicate support for partial mmaps
On 3/6/2025 10:08 PM, José Roberto de Souza wrote:
> Commit 255fc1703e42 ("drm/i915/gem: Calculate object page offset for partial
> memory mapping")
> was the last patch of several patches fixing multiple partial mmaps.
> But without a bump in I915_PARAM_MMAP_GTT_VERSION there is no clean
> way for UMD to know if it can do multiple partial mmaps.
>
> Fixes: 255fc1703e42 ("drm/i915/gem: Calculate object page offset for partial
> memory mapping")
> Cc: Andi Shyti
> Cc: Nirmoy Das
> Cc: Lionel Landwerlin
Reviewed-by: Nirmoy Das
> Signed-off-by: José Roberto de Souza
> ---
> drivers/gpu/drm/i915/gem/i915_gem_mman.c | 5 -
> 1 file changed, 4 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/i915/gem/i915_gem_mman.c
> b/drivers/gpu/drm/i915/gem/i915_gem_mman.c
> index 21274aa9bdddc..c3dabb8579605 100644
> --- a/drivers/gpu/drm/i915/gem/i915_gem_mman.c
> +++ b/drivers/gpu/drm/i915/gem/i915_gem_mman.c
> @@ -164,6 +164,9 @@ static unsigned int tile_row_pages(const struct
> drm_i915_gem_object *obj)
> * 4 - Support multiple fault handlers per object depending on object's
> * backing storage (a.k.a. MMAP_OFFSET).
> *
> + * 5 - Support multiple partial mmaps(mmap part of BO + unmap a offset,
> multiple
> + * times with different size and offset).
> + *
> * Restrictions:
> *
> * * snoopable objects cannot be accessed via the GTT. It can cause machine
> @@ -191,7 +194,7 @@ static unsigned int tile_row_pages(const struct
> drm_i915_gem_object *obj)
> */
> int i915_gem_mmap_gtt_version(void)
> {
> - return 4;
> + return 5;
> }
>
> static inline struct i915_gtt_view
Re: [PATCH v6 1/7] bits: split the definition of the asm and non-asm GENMASK()
On Sat, Mar 08, 2025 at 01:48:48AM +0900, Vincent Mailhol via B4 Relay wrote: > From: Vincent Mailhol > > In an upcoming change, GENMASK() and its friends will indirectly > depend on sizeof() which is not available in asm. > > Instead of adding further complexity to __GENMASK() to make it work > for both asm and non asm, just split the definition of the two > variants. ... > -/* > - * BUILD_BUG_ON_ZERO is not available in h files included from asm files, > - * disable the input check if that is the case. > - */ > +/* > + * BUILD_BUG_ON_ZERO() is not available in h files included from asm files, > so > + * no input checks in assembly. > + */ In case of a new version I would reformat this as /* * BUILD_BUG_ON_ZERO() is not available in h files included from asm files, * so no input checks in assembly. */ It makes easier to review the changes and see that the first line is kept the same. -- With Best Regards, Andy Shevchenko
[PATCH 02/14] drm/i915: s/intel_crtc_bw/intel_dbuf_bw/
From: Ville Syrjälä
Rename the intel_crtc_bw struct to intel_dbuf_bw to better
reflect what it does.
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/display/intel_bw.c | 24
1 file changed, 12 insertions(+), 12 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_bw.c
b/drivers/gpu/drm/i915/display/intel_bw.c
index 7b9ae926c5c4..2bc020690515 100644
--- a/drivers/gpu/drm/i915/display/intel_bw.c
+++ b/drivers/gpu/drm/i915/display/intel_bw.c
@@ -1124,15 +1124,15 @@ static bool intel_bw_state_changed(struct
drm_i915_private *i915,
enum pipe pipe;
for_each_pipe(i915, pipe) {
- const struct intel_dbuf_bw *old_crtc_bw =
+ const struct intel_dbuf_bw *old_dbuf_bw =
&old_bw_state->dbuf_bw[pipe];
- const struct intel_dbuf_bw *new_crtc_bw =
+ const struct intel_dbuf_bw *new_dbuf_bw =
&new_bw_state->dbuf_bw[pipe];
enum dbuf_slice slice;
for_each_dbuf_slice(i915, slice) {
- if (old_crtc_bw->max_bw[slice] !=
new_crtc_bw->max_bw[slice] ||
- old_crtc_bw->active_planes[slice] !=
new_crtc_bw->active_planes[slice])
+ if (old_dbuf_bw->max_bw[slice] !=
new_dbuf_bw->max_bw[slice] ||
+ old_dbuf_bw->active_planes[slice] !=
new_dbuf_bw->active_planes[slice])
return true;
}
@@ -1151,7 +1151,7 @@ static void skl_plane_calc_dbuf_bw(struct intel_bw_state
*bw_state,
unsigned int data_rate)
{
struct drm_i915_private *i915 = to_i915(crtc->base.dev);
- struct intel_dbuf_bw *crtc_bw = &bw_state->dbuf_bw[crtc->pipe];
+ struct intel_dbuf_bw *dbuf_bw = &bw_state->dbuf_bw[crtc->pipe];
unsigned int dbuf_mask = skl_ddb_dbuf_slice_mask(i915, ddb);
enum dbuf_slice slice;
@@ -1160,8 +1160,8 @@ static void skl_plane_calc_dbuf_bw(struct intel_bw_state
*bw_state,
* equal share of the total bw to each plane.
*/
for_each_dbuf_slice_in_mask(i915, slice, dbuf_mask) {
- crtc_bw->max_bw[slice] = max(crtc_bw->max_bw[slice], data_rate);
- crtc_bw->active_planes[slice] |= BIT(plane_id);
+ dbuf_bw->max_bw[slice] = max(dbuf_bw->max_bw[slice], data_rate);
+ dbuf_bw->active_planes[slice] |= BIT(plane_id);
}
}
@@ -1170,10 +1170,10 @@ static void skl_crtc_calc_dbuf_bw(struct intel_bw_state
*bw_state,
{
struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
struct drm_i915_private *i915 = to_i915(crtc->base.dev);
- struct intel_dbuf_bw *crtc_bw = &bw_state->dbuf_bw[crtc->pipe];
+ struct intel_dbuf_bw *dbuf_bw = &bw_state->dbuf_bw[crtc->pipe];
enum plane_id plane_id;
- memset(crtc_bw, 0, sizeof(*crtc_bw));
+ memset(dbuf_bw, 0, sizeof(*dbuf_bw));
if (!crtc_state->hw.active)
return;
@@ -1215,10 +1215,10 @@ intel_bw_dbuf_min_cdclk(struct drm_i915_private *i915,
* equal share of the total bw to each plane.
*/
for_each_pipe(i915, pipe) {
- const struct intel_dbuf_bw *crtc_bw =
&bw_state->dbuf_bw[pipe];
+ const struct intel_dbuf_bw *dbuf_bw =
&bw_state->dbuf_bw[pipe];
- max_bw = max(crtc_bw->max_bw[slice], max_bw);
- num_active_planes +=
hweight8(crtc_bw->active_planes[slice]);
+ max_bw = max(dbuf_bw->max_bw[slice], max_bw);
+ num_active_planes +=
hweight8(dbuf_bw->active_planes[slice]);
}
max_bw *= num_active_planes;
--
2.45.3
[PATCH 11/14] drm/i915: Make intel_bw_check_sagv_mask() internal to intel_bw.c
From: Ville Syrjälä
The only thing between the current intel_bw_check_sagv_mask() call
site and intel_bw_atomic_check() is skl_wm_add_affected_planes()
which no longer depends on the sagv mask, so we can make life
a lot less confusing by calling intel_bw_check_sagv_mask() from
intel_bw_atomic_check() instead.
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/display/intel_bw.c | 9 -
drivers/gpu/drm/i915/display/intel_bw.h | 1 -
drivers/gpu/drm/i915/display/skl_watermark.c | 5 -
3 files changed, 8 insertions(+), 7 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_bw.c
b/drivers/gpu/drm/i915/display/intel_bw.c
index 33ec9f574716..a39b75640b03 100644
--- a/drivers/gpu/drm/i915/display/intel_bw.c
+++ b/drivers/gpu/drm/i915/display/intel_bw.c
@@ -1408,7 +1408,7 @@ int intel_bw_modeset_checks(struct intel_atomic_state
*state)
return 0;
}
-int intel_bw_check_sagv_mask(struct intel_atomic_state *state)
+static int intel_bw_check_sagv_mask(struct intel_atomic_state *state)
{
struct intel_display *display = to_intel_display(state);
struct drm_i915_private *i915 = to_i915(display->drm);
@@ -1456,6 +1456,13 @@ int intel_bw_atomic_check(struct intel_atomic_state
*state)
const struct intel_bw_state *old_bw_state;
int ret;
+ if (DISPLAY_VER(i915) < 9)
+ return 0;
+
+ ret = intel_bw_check_sagv_mask(state);
+ if (ret)
+ return ret;
+
/* FIXME earlier gens need some checks too */
if (DISPLAY_VER(i915) < 11)
return 0;
diff --git a/drivers/gpu/drm/i915/display/intel_bw.h
b/drivers/gpu/drm/i915/display/intel_bw.h
index e5a0ff630438..0efc9858faa1 100644
--- a/drivers/gpu/drm/i915/display/intel_bw.h
+++ b/drivers/gpu/drm/i915/display/intel_bw.h
@@ -68,7 +68,6 @@ intel_atomic_get_bw_state(struct intel_atomic_state *state);
void intel_bw_init_hw(struct drm_i915_private *dev_priv);
int intel_bw_init(struct drm_i915_private *dev_priv);
int intel_bw_modeset_checks(struct intel_atomic_state *state);
-int intel_bw_check_sagv_mask(struct intel_atomic_state *state);
int intel_bw_atomic_check(struct intel_atomic_state *state);
int icl_pcode_restrict_qgv_points(struct drm_i915_private *dev_priv,
u32 points_mask);
diff --git a/drivers/gpu/drm/i915/display/skl_watermark.c
b/drivers/gpu/drm/i915/display/skl_watermark.c
index 80ee9f8ae230..019eda6e3708 100644
--- a/drivers/gpu/drm/i915/display/skl_watermark.c
+++ b/drivers/gpu/drm/i915/display/skl_watermark.c
@@ -451,7 +451,6 @@ static int intel_compute_sagv_mask(struct
intel_atomic_state *state)
{
struct intel_display *display = to_intel_display(state);
struct drm_i915_private *i915 = to_i915(state->base.dev);
- int ret;
struct intel_crtc *crtc;
struct intel_crtc_state *new_crtc_state;
int i;
@@ -482,10 +481,6 @@ static int intel_compute_sagv_mask(struct
intel_atomic_state *state)
intel_crtc_can_enable_sagv(new_crtc_state);
}
- ret = intel_bw_check_sagv_mask(state);
- if (ret)
- return ret;
-
return 0;
}
--
2.45.3
[PATCH v3 3/3] drm/i915/xe3lpd: Update bandwidth parameters
Bandwidth parameters for Xe3_LPD have been updated with respect to
previous display releases. Encode them into xe3lpd_sa_info and use that
new struct.
Bspec: 68859
Reviewed-by: Matt Roper
Signed-off-by: Gustavo Sousa
---
drivers/gpu/drm/i915/display/intel_bw.c | 11 ++-
1 file changed, 10 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/display/intel_bw.c
b/drivers/gpu/drm/i915/display/intel_bw.c
index
39644ae6932047f2b83f0ae34ed93f73a100685f..ee3e2fbd4a42a232b58f8e2344c134f6a1db1ac4
100644
--- a/drivers/gpu/drm/i915/display/intel_bw.c
+++ b/drivers/gpu/drm/i915/display/intel_bw.c
@@ -404,6 +404,13 @@ static const struct intel_sa_info xe2_hpd_sa_info = {
/* Other values not used by simplified algorithm */
};
+static const struct intel_sa_info xe3lpd_sa_info = {
+ .deburst = 32,
+ .deprogbwlimit = 65, /* GB/s */
+ .displayrtids = 256,
+ .derating = 10,
+};
+
static int icl_get_bw_info(struct intel_display *display, const struct
intel_sa_info *sa)
{
struct drm_i915_private *i915 = to_i915(display->drm);
@@ -752,7 +759,9 @@ void intel_bw_init_hw(struct intel_display *display)
if (!HAS_DISPLAY(display))
return;
- if (DISPLAY_VERx100(display) >= 1401 && display->platform.dgfx)
+ if (DISPLAY_VER(display) >= 30)
+ tgl_get_bw_info(display, &xe3lpd_sa_info);
+ else if (DISPLAY_VERx100(display) >= 1401 && display->platform.dgfx)
xe2_hpd_get_bw_info(display, &xe2_hpd_sa_info);
else if (DISPLAY_VER(display) >= 14)
tgl_get_bw_info(display, &mtl_sa_info);
--
2.48.1
✗ Fi.CI.CHECKPATCH: warning for drm/i915: Increase I915_PARAM_MMAP_GTT_VERSION version to indicate support for partial mmaps (rev4)
== Series Details ==
Series: drm/i915: Increase I915_PARAM_MMAP_GTT_VERSION version to indicate
support for partial mmaps (rev4)
URL : https://patchwork.freedesktop.org/series/145945/
State : warning
== Summary ==
Error: dim checkpatch failed
e4a5570cfc5d drm/i915: Increase I915_PARAM_MMAP_GTT_VERSION version to indicate
support for partial mmaps
-:10: WARNING:COMMIT_LOG_LONG_LINE: Prefer a maximum 75 chars per line
(possible unwrapped commit description?)
#10:
Commit 255fc1703e42 ("drm/i915/gem: Calculate object page offset for partial
memory mapping")
total: 0 errors, 1 warnings, 0 checks, 17 lines checked
✗ i915.CI.BAT: failure for drm/i915: Increase I915_PARAM_MMAP_GTT_VERSION version to indicate support for partial mmaps (rev4)
== Series Details == Series: drm/i915: Increase I915_PARAM_MMAP_GTT_VERSION version to indicate support for partial mmaps (rev4) URL : https://patchwork.freedesktop.org/series/145945/ State : failure == Summary == CI Bug Log - changes from CI_DRM_16246 -> Patchwork_145945v4 Summary --- **FAILURE** Serious unknown changes coming with Patchwork_145945v4 absolutely need to be verified manually. If you think the reported changes have nothing to do with the changes introduced in Patchwork_145945v4, please notify your bug team (i915-ci-in...@lists.freedesktop.org) to allow them to document this new failure mode, which will reduce false positives in CI. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_145945v4/index.html Participating hosts (43 -> 41) -- Missing(2): fi-glk-j4005 fi-snb-2520m Possible new issues --- Here are the unknown changes that may have been introduced in Patchwork_145945v4: ### IGT changes ### Possible regressions * igt@i915_module_load@load: - bat-adlp-6: [PASS][1] -> [DMESG-WARN][2] [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16246/bat-adlp-6/igt@i915_module_l...@load.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_145945v4/bat-adlp-6/igt@i915_module_l...@load.html Known issues Here are the changes found in Patchwork_145945v4 that come from known issues: ### IGT changes ### Issues hit * igt@dmabuf@all-tests@dma_fence_chain: - fi-bsw-nick:[PASS][3] -> [INCOMPLETE][4] ([i915#12904]) +1 other test incomplete [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16246/fi-bsw-nick/igt@dmabuf@all-tests@dma_fence_chain.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_145945v4/fi-bsw-nick/igt@dmabuf@all-tests@dma_fence_chain.html * igt@fbdev@info: - fi-kbl-8809g: NOTRUN -> [SKIP][5] ([i915#1849]) [5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_145945v4/fi-kbl-8809g/igt@fb...@info.html * igt@gem_huc_copy@huc-copy: - fi-kbl-8809g: NOTRUN -> [SKIP][6] ([i915#2190]) [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_145945v4/fi-kbl-8809g/igt@gem_huc_c...@huc-copy.html * igt@gem_lmem_swapping@parallel-random-engines: - fi-kbl-8809g: NOTRUN -> [SKIP][7] ([i915#4613]) +3 other tests skip [7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_145945v4/fi-kbl-8809g/igt@gem_lmem_swapp...@parallel-random-engines.html * igt@i915_pm_rpm@module-reload: - bat-dg2-11: [PASS][8] -> [FAIL][9] ([i915#13633]) [8]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16246/bat-dg2-11/igt@i915_pm_...@module-reload.html [9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_145945v4/bat-dg2-11/igt@i915_pm_...@module-reload.html - bat-adls-6: [PASS][10] -> [FAIL][11] ([i915#13633]) [10]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16246/bat-adls-6/igt@i915_pm_...@module-reload.html [11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_145945v4/bat-adls-6/igt@i915_pm_...@module-reload.html - bat-dg1-7: [PASS][12] -> [FAIL][13] ([i915#13633]) [12]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16246/bat-dg1-7/igt@i915_pm_...@module-reload.html [13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_145945v4/bat-dg1-7/igt@i915_pm_...@module-reload.html - bat-rpls-4: [PASS][14] -> [FAIL][15] ([i915#13633]) [14]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16246/bat-rpls-4/igt@i915_pm_...@module-reload.html [15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_145945v4/bat-rpls-4/igt@i915_pm_...@module-reload.html * igt@i915_selftest@live: - bat-jsl-3: [PASS][16] -> [INCOMPLETE][17] ([i915#12445] / [i915#13241]) [16]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16246/bat-jsl-3/igt@i915_selft...@live.html [17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_145945v4/bat-jsl-3/igt@i915_selft...@live.html * igt@kms_dsc@dsc-basic: - fi-kbl-8809g: NOTRUN -> [SKIP][18] +34 other tests skip [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_145945v4/fi-kbl-8809g/igt@kms_...@dsc-basic.html * igt@kms_pipe_crc_basic@nonblocking-crc-frame-sequence: - bat-dg2-11: [PASS][19] -> [SKIP][20] ([i915#9197]) +3 other tests skip [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16246/bat-dg2-11/igt@kms_pipe_crc_ba...@nonblocking-crc-frame-sequence.html [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_145945v4/bat-dg2-11/igt@kms_pipe_crc_ba...@nonblocking-crc-frame-sequence.html Possible fixes * igt@i915_selftest@live@workarounds: - bat-arls-5: [DMESG-FAIL][21] ([i915#12061]) -> [PASS][22] +1 other test pass [21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16246/bat-arls-5/igt@i91
Re: [PATCH v2 1/1] drm/i915/xehp: add wait on depth stall done bit handling
Quoting Juha-Pekka Heikkila (2025-02-14 16:57:11) > Add writing of WAIT_ON_DEPTH_STALL_DONE_DISABLE for gen12, this > is performance optimization. > > Bspec: 46132 > > Closes: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/12411 > Signed-off-by: Juha-Pekka Heikkila > --- > drivers/gpu/drm/i915/gt/intel_gt_regs.h | 3 +++ > drivers/gpu/drm/i915/gt/intel_workarounds.c | 6 ++ > 2 files changed, 9 insertions(+) > > diff --git a/drivers/gpu/drm/i915/gt/intel_gt_regs.h > b/drivers/gpu/drm/i915/gt/intel_gt_regs.h > index 6dba65e54cdb..a6e50af44b46 100644 > --- a/drivers/gpu/drm/i915/gt/intel_gt_regs.h > +++ b/drivers/gpu/drm/i915/gt/intel_gt_regs.h > @@ -409,6 +409,9 @@ > #define GEN7_SO_PRIM_STORAGE_NEEDED(n) _MMIO(0x5240 + (n) * 8) > #define GEN7_SO_PRIM_STORAGE_NEEDED_UDW(n) _MMIO(0x5240 + (n) * 8 + 4) > > +#define GEN8_WM_CHICKEN2 MCR_REG(0x5584) > +#define WAIT_ON_DEPTH_STALL_DONE_DISABLE REG_BIT(5) > + > #define GEN9_WM_CHICKEN3 _MMIO(0x5588) > #define GEN9_FACTOR_IN_CLR_VAL_HIZ (1 << 9) > > diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c > b/drivers/gpu/drm/i915/gt/intel_workarounds.c > index db04c3ee02e2..116683ebe074 100644 > --- a/drivers/gpu/drm/i915/gt/intel_workarounds.c > +++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c > @@ -742,6 +742,12 @@ static void gen12_ctx_workarounds_init(struct > intel_engine_cs *engine, > /* Wa_1606376872 */ > wa_masked_en(wal, COMMON_SLICE_CHICKEN4, > DISABLE_TDC_LOAD_BALANCING_CALC); > } Do we not have an "optional" tuning section? > + > + /* > +* This bit must be set to enable performance optimization for fast > +* clears. > +*/ > + wa_mcr_write_or(wal, GEN8_WM_CHICKEN2, > WAIT_ON_DEPTH_STALL_DONE_DISABLE); This should only be applied to rcs contexts, not all. -Chris
Re: [PATCH v6 3/6] drm/i915/hpd: Add support for blocking the IRQ handling on an HPD pin
On Wed, 05 Mar 2025, Imre Deak wrote:
> Add support for blocking the IRQ handling on the HPD pin of a given
> encoder, handling IRQs that arrived while in the blocked state after
> unblocking the IRQ handling. This will be used by a follow-up change,
> which blocks/unblocks the IRQ handling around DP link training.
>
> This is similar to the intel_hpd_disable/enable() functionality, by also
> handling encoders/ports with a pulse handler (i.e. also
> blocking/unblocking the short/long pulse handling) and handling the IRQs
> arrived in the blocked state after the handling is unblocked (vs. just
> dropping such IRQs).
>
> v2:
> - Handle encoders without a port assigned to them.
> - Fix clearing IRQs from intel_hotplug::short_port_mask.
> v3:
> - Rename intel_hpd_suspend/resume() to intel_hpd_block/unblock(). (Jani)
> - Refer to HPD pins as hpd_pin vs. hpd.
> - Flush dig_port_work in intel_hpd_block() if any encoder using the HPD
> pin has a pulse handler.
> v4:
> - Fix hpd_pin_has_pulse(), checking the encoder's HPD pin.
> v5:
> - Rebase on port->hpd_pin tracking. (Ville)
> v6: (Jani)
> - Add hpd_pin_is_blocked() helper.
> - Use the hpd_pin_mask term for a mask of pins instead of hpd_pins.
> - Prevent decrementing a 0 refcount in unblock_hpd_pin().
>
> Cc: Jani Nikula
> Cc: Ville Syrjälä
> Signed-off-by: Imre Deak
Reviewed-by: Jani Nikula
> ---
> .../gpu/drm/i915/display/intel_display_core.h | 1 +
> drivers/gpu/drm/i915/display/intel_hotplug.c | 210 +++---
> drivers/gpu/drm/i915/display/intel_hotplug.h | 2 +
> 3 files changed, 188 insertions(+), 25 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_display_core.h
> b/drivers/gpu/drm/i915/display/intel_display_core.h
> index d9952007635e0..fbe890775c2ab 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_core.h
> +++ b/drivers/gpu/drm/i915/display/intel_display_core.h
> @@ -159,6 +159,7 @@ struct intel_hotplug {
> struct {
> unsigned long last_jiffies;
> int count;
> + int blocked_count;
> enum {
> HPD_ENABLED = 0,
> HPD_DISABLED = 1,
> diff --git a/drivers/gpu/drm/i915/display/intel_hotplug.c
> b/drivers/gpu/drm/i915/display/intel_hotplug.c
> index 3fb5feeefa144..94b4dcf10f58c 100644
> --- a/drivers/gpu/drm/i915/display/intel_hotplug.c
> +++ b/drivers/gpu/drm/i915/display/intel_hotplug.c
> @@ -349,19 +349,62 @@ static bool intel_encoder_has_hpd_pulse(struct
> intel_encoder *encoder)
> enc_to_dig_port(encoder)->hpd_pulse != NULL;
> }
>
> +static bool hpd_pin_has_pulse(struct intel_display *display, enum hpd_pin
> pin)
> +{
> + struct intel_encoder *encoder;
> +
> + for_each_intel_encoder(display->drm, encoder) {
> + if (encoder->hpd_pin != pin)
> + continue;
> +
> + if (intel_encoder_has_hpd_pulse(encoder))
> + return true;
> + }
> +
> + return false;
> +}
> +
> +static bool hpd_pin_is_blocked(struct intel_display *display, enum hpd_pin
> pin)
> +{
> + struct drm_i915_private *i915 = to_i915(display->drm);
> +
> + lockdep_assert_held(&i915->irq_lock);
> +
> + return display->hotplug.stats[pin].blocked_count;
> +}
> +
> +static u32 get_blocked_hpd_pin_mask(struct intel_display *display)
> +{
> + enum hpd_pin pin;
> + u32 hpd_pin_mask = 0;
> +
> + for_each_hpd_pin(pin) {
> + if (hpd_pin_is_blocked(display, pin))
> + hpd_pin_mask |= BIT(pin);
> + }
> +
> + return hpd_pin_mask;
> +}
> +
> static void i915_digport_work_func(struct work_struct *work)
> {
> - struct drm_i915_private *dev_priv =
> - container_of(work, struct drm_i915_private,
> display.hotplug.dig_port_work);
> + struct intel_display *display =
> + container_of(work, struct intel_display, hotplug.dig_port_work);
> + struct drm_i915_private *dev_priv = to_i915(display->drm);
> + struct intel_hotplug *hotplug = &display->hotplug;
> u32 long_hpd_pin_mask, short_hpd_pin_mask;
> struct intel_encoder *encoder;
> + u32 blocked_hpd_pin_mask;
> u32 old_bits = 0;
>
> spin_lock_irq(&dev_priv->irq_lock);
> - long_hpd_pin_mask = dev_priv->display.hotplug.long_hpd_pin_mask;
> - dev_priv->display.hotplug.long_hpd_pin_mask = 0;
> - short_hpd_pin_mask = dev_priv->display.hotplug.short_hpd_pin_mask;
> - dev_priv->display.hotplug.short_hpd_pin_mask = 0;
> +
> + blocked_hpd_pin_mask = get_blocked_hpd_pin_mask(display);
> + long_hpd_pin_mask = hotplug->long_hpd_pin_mask & ~blocked_hpd_pin_mask;
> + hotplug->long_hpd_pin_mask &= ~long_hpd_pin_mask;
> + short_hpd_pin_mask = hotplug->short_hpd_pin_mask &
> ~blocked_hpd_pin_mask;
> + hotplug->short_hpd_pin_mask &= ~short_hpd_pin_mask;
> +
> spin_unlock_irq(&dev_priv->irq_lock);
>
> for_each_intel_encoder(&dev_priv->drm, encoder) {
> @@ -40
Re: [PATCH v5 6/6] drm/i915/crt: Use intel_hpd_block/unblock() instead of intel_hpd_disable/enable()
On Tue, 04 Mar 2025, Imre Deak wrote:
> intel_hpd_disable/enable() have the same purpose as
> intel_hpd_block/unblock(), except that disable/enable will drop any HPD
> IRQs which were triggered while the HPD was disabled, while
> block/unblock will handle such IRQs after the IRQ handling is unblocked.
> Use intel_hpd_block/unblock() for crt as well, by adding a helper to
> explicitly clear any pending IRQs before unblocking.
>
> v2:
> - Handle encoders without a port assigned to them.
> - Rebase on change in intel_hpd_suspend() documentation.
> v3:
> - Rebase on the suspend/resume -> block/unblock rename change.
> - Clear the pending events only after all encoders have unblocked the
> HPD handling.
> - Clear the short/long port events for all encoders using the given HPD
> pin.
> v4:
> - Rebase on port->hpd_pin tracking. (Ville)
>
> Cc: Ville Syrjälä
> Signed-off-by: Imre Deak
Reviewed-by: Jani Nikula
> ---
> drivers/gpu/drm/i915/display/intel_crt.c | 7 +--
> drivers/gpu/drm/i915/display/intel_hotplug.c | 60 +++-
> drivers/gpu/drm/i915/display/intel_hotplug.h | 3 +-
> 3 files changed, 35 insertions(+), 35 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_crt.c
> b/drivers/gpu/drm/i915/display/intel_crt.c
> index 76ffb3f8467c8..bca91d49cb960 100644
> --- a/drivers/gpu/drm/i915/display/intel_crt.c
> +++ b/drivers/gpu/drm/i915/display/intel_crt.c
> @@ -532,8 +532,6 @@ static bool valleyview_crt_detect_hotplug(struct
> drm_connector *connector)
> {
> struct intel_display *display = to_intel_display(connector->dev);
> struct intel_crt *crt =
> intel_attached_crt(to_intel_connector(connector));
> - struct drm_i915_private *dev_priv = to_i915(connector->dev);
> - bool reenable_hpd;
> u32 adpa;
> bool ret;
> u32 save_adpa;
> @@ -550,7 +548,7 @@ static bool valleyview_crt_detect_hotplug(struct
> drm_connector *connector)
>*
>* Just disable HPD interrupts here to prevent this
>*/
> - reenable_hpd = intel_hpd_disable(dev_priv, crt->base.hpd_pin);
> + intel_hpd_block(&crt->base);
>
> save_adpa = adpa = intel_de_read(display, crt->adpa_reg);
> drm_dbg_kms(display->drm,
> @@ -577,8 +575,7 @@ static bool valleyview_crt_detect_hotplug(struct
> drm_connector *connector)
> drm_dbg_kms(display->drm,
> "valleyview hotplug adpa=0x%x, result %d\n", adpa, ret);
>
> - if (reenable_hpd)
> - intel_hpd_enable(dev_priv, crt->base.hpd_pin);
> + intel_hpd_clear_and_unblock(&crt->base);
>
> return ret;
> }
> diff --git a/drivers/gpu/drm/i915/display/intel_hotplug.c
> b/drivers/gpu/drm/i915/display/intel_hotplug.c
> index cb4e320a1023d..423925fec73dc 100644
> --- a/drivers/gpu/drm/i915/display/intel_hotplug.c
> +++ b/drivers/gpu/drm/i915/display/intel_hotplug.c
> @@ -993,33 +993,6 @@ void intel_hpd_cancel_work(struct drm_i915_private
> *dev_priv)
> drm_dbg_kms(&dev_priv->drm, "Hotplug detection work still
> active\n");
> }
>
> -bool intel_hpd_disable(struct drm_i915_private *dev_priv, enum hpd_pin pin)
> -{
> - bool ret = false;
> -
> - if (pin == HPD_NONE)
> - return false;
> -
> - spin_lock_irq(&dev_priv->irq_lock);
> - if (dev_priv->display.hotplug.stats[pin].state == HPD_ENABLED) {
> - dev_priv->display.hotplug.stats[pin].state = HPD_DISABLED;
> - ret = true;
> - }
> - spin_unlock_irq(&dev_priv->irq_lock);
> -
> - return ret;
> -}
> -
> -void intel_hpd_enable(struct drm_i915_private *dev_priv, enum hpd_pin pin)
> -{
> - if (pin == HPD_NONE)
> - return;
> -
> - spin_lock_irq(&dev_priv->irq_lock);
> - dev_priv->display.hotplug.stats[pin].state = HPD_ENABLED;
> - spin_unlock_irq(&dev_priv->irq_lock);
> -}
> -
> static void queue_work_for_missed_irqs(struct drm_i915_private *i915)
> {
> struct intel_display *display = to_intel_display(&i915->drm);
> @@ -1096,7 +1069,8 @@ static bool unblock_hpd_pin(struct intel_display
> *display, enum hpd_pin pin)
> * drm_connector_funcs::detect()) remains allowed, for instance as part of
> * userspace connector probing, or DRM core's connector polling.
> *
> - * The call must be followed by calling intel_hpd_unblock().
> + * The call must be followed by calling intel_hpd_unblock(), or
> + * intel_hpd_clear_and_unblock().
> *
> * Note that the handling of HPD IRQs for another encoder using the same HPD
> * pin as that of @encoder will be also blocked.
> @@ -1147,6 +1121,36 @@ void intel_hpd_unblock(struct intel_encoder *encoder)
> spin_unlock_irq(&i915->irq_lock);
> }
>
> +/**
> + * intel_hpd_clear_and_unblock - Unblock handling of new HPD IRQs on an HPD
> pin
> + * @encoder: Encoder to unblock the HPD handling for
> + *
> + * Unblock the handling of HPD IRQs on the HPD pin of @encoder, which was
> + * previously blocked by intel_hpd_block(). Any HPD IRQ raised on th
✗ i915.CI.BAT: failure for drm/i915/selftests: Re-enable power gating after live_selftest (rev3)
== Series Details == Series: drm/i915/selftests: Re-enable power gating after live_selftest (rev3) URL : https://patchwork.freedesktop.org/series/145144/ State : failure == Summary == CI Bug Log - changes from CI_DRM_16245 -> Patchwork_145144v3 Summary --- **FAILURE** Serious unknown changes coming with Patchwork_145144v3 absolutely need to be verified manually. If you think the reported changes have nothing to do with the changes introduced in Patchwork_145144v3, please notify your bug team (i915-ci-in...@lists.freedesktop.org) to allow them to document this new failure mode, which will reduce false positives in CI. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_145144v3/index.html Participating hosts (44 -> 42) -- Missing(2): bat-arlh-2 fi-snb-2520m Possible new issues --- Here are the unknown changes that may have been introduced in Patchwork_145144v3: ### IGT changes ### Possible regressions * igt@kms_flip@basic-flip-vs-modeset@a-dp1: - bat-apl-1: [PASS][1] -> [DMESG-WARN][2] +1 other test dmesg-warn [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16245/bat-apl-1/igt@kms_flip@basic-flip-vs-mode...@a-dp1.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_145144v3/bat-apl-1/igt@kms_flip@basic-flip-vs-mode...@a-dp1.html Known issues Here are the changes found in Patchwork_145144v3 that come from known issues: ### IGT changes ### Issues hit * igt@fbdev@info: - fi-kbl-8809g: NOTRUN -> [SKIP][3] ([i915#1849]) [3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_145144v3/fi-kbl-8809g/igt@fb...@info.html * igt@gem_huc_copy@huc-copy: - fi-kbl-8809g: NOTRUN -> [SKIP][4] ([i915#2190]) [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_145144v3/fi-kbl-8809g/igt@gem_huc_c...@huc-copy.html * igt@gem_lmem_swapping@parallel-random-engines: - fi-kbl-8809g: NOTRUN -> [SKIP][5] ([i915#4613]) +3 other tests skip [5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_145144v3/fi-kbl-8809g/igt@gem_lmem_swapp...@parallel-random-engines.html * igt@i915_pm_rpm@module-reload: - bat-adls-6: [PASS][6] -> [FAIL][7] ([i915#13633]) [6]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16245/bat-adls-6/igt@i915_pm_...@module-reload.html [7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_145144v3/bat-adls-6/igt@i915_pm_...@module-reload.html - bat-dg1-7: [PASS][8] -> [FAIL][9] ([i915#13633]) [8]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16245/bat-dg1-7/igt@i915_pm_...@module-reload.html [9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_145144v3/bat-dg1-7/igt@i915_pm_...@module-reload.html - bat-rpls-4: [PASS][10] -> [FAIL][11] ([i915#13633]) [10]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16245/bat-rpls-4/igt@i915_pm_...@module-reload.html [11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_145144v3/bat-rpls-4/igt@i915_pm_...@module-reload.html * igt@i915_selftest@live: - bat-mtlp-8: [PASS][12] -> [DMESG-FAIL][13] ([i915#12061]) +1 other test dmesg-fail [12]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16245/bat-mtlp-8/igt@i915_selft...@live.html [13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_145144v3/bat-mtlp-8/igt@i915_selft...@live.html * igt@kms_dsc@dsc-basic: - fi-kbl-8809g: NOTRUN -> [SKIP][14] +34 other tests skip [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_145144v3/fi-kbl-8809g/igt@kms_...@dsc-basic.html * igt@kms_pipe_crc_basic@nonblocking-crc-frame-sequence: - bat-dg2-11: [PASS][15] -> [SKIP][16] ([i915#9197]) +3 other tests skip [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16245/bat-dg2-11/igt@kms_pipe_crc_ba...@nonblocking-crc-frame-sequence.html [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_145144v3/bat-dg2-11/igt@kms_pipe_crc_ba...@nonblocking-crc-frame-sequence.html [i915#12061]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/12061 [i915#13633]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/13633 [i915#1849]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/1849 [i915#2190]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/2190 [i915#4613]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4613 [i915#9197]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9197 Build changes - * Linux: CI_DRM_16245 -> Patchwork_145144v3 CI-20190529: 20190529 CI_DRM_16245: 066c46f28642479869d2d1dd27cc6ae476de4abc @ git://anongit.freedesktop.org/gfx-ci/linux IGT_8264: 8264 Patchwork_145144v3: 066c46f28642479869d2d1dd27cc6ae476de4abc @ git://anongit.freedesktop.org/gfx-ci/linux == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/
Re: [PATCH v5 7/7] test_bits: add tests for BIT_U*()
On Fri, Mar 07, 2025 at 07:11:42PM +0900, Vincent Mailhol wrote: > On 07/03/2025 at 02:55, Andy Shevchenko wrote: > > On Fri, Mar 07, 2025 at 01:08:15AM +0900, Vincent Mailhol wrote: > >> On 06/03/2025 at 22:11, Andy Shevchenko wrote: > >>> On Thu, Mar 06, 2025 at 08:29:58PM +0900, Vincent Mailhol via B4 Relay > >>> wrote: > From: Vincent Mailhol > > Add some additional tests in lib/test_bits.c to cover the expected > results of the fixed type BIT_U*() macros. > >>> > >>> Still would be good to have a small assembly test case for GENMASK*() as > >>> they > >>> went split and it will be a good regression test in case somebody decides > >>> to > >>> unify both without much thinking.. > >> > >> Let me confirm that I correctly understood your ask. Would something > >> like this meet your expectations? > > > > I believe it should be written in asm. > > I am not confident enough in my assembly skills to submit asm patches to > the kernel. So, I would rather take a pass on that one. > > Regardless, if somebody decides to unify both without much thinking as > you said, I am fully confident that the patch will get Nack-ed right As I said above "would be good", if you think it's not feasible by you, perhaps a comment (FIXME: ?) in the Kunit test cases that we lack of / need an asm test as well. -- With Best Regards, Andy Shevchenko
✗ Fi.CI.CHECKPATCH: warning for bits: Fixed-type GENMASK()/BIT() (rev2)
== Series Details == Series: bits: Fixed-type GENMASK()/BIT() (rev2) URL : https://patchwork.freedesktop.org/series/145997/ State : warning == Summary == Error: dim checkpatch failed f96fba907aff bits: fix typo 'unsigned __init128' -> 'unsigned __int128' fdc85516eb83 bits: split the definition of the asm and non-asm GENMASK() 3444ee4c6891 bits: introduce fixed-type genmasks -:71: CHECK:MACRO_ARG_REUSE: Macro argument reuse 't' - possible side-effects? #71: FILE: include/linux/bits.h:39: +#define GENMASK_t(t, h, l) \ + (GENMASK_INPUT_CHECK(h, l) +\ +(((t)~ULL(0) - ((t)1 << (l)) + 1) &\ + ((t)~ULL(0) >> (BITS_PER_TYPE(t) - 1 - (h) -:71: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'h' - possible side-effects? #71: FILE: include/linux/bits.h:39: +#define GENMASK_t(t, h, l) \ + (GENMASK_INPUT_CHECK(h, l) +\ +(((t)~ULL(0) - ((t)1 << (l)) + 1) &\ + ((t)~ULL(0) >> (BITS_PER_TYPE(t) - 1 - (h) -:71: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'l' - possible side-effects? #71: FILE: include/linux/bits.h:39: +#define GENMASK_t(t, h, l) \ + (GENMASK_INPUT_CHECK(h, l) +\ +(((t)~ULL(0) - ((t)1 << (l)) + 1) &\ + ((t)~ULL(0) >> (BITS_PER_TYPE(t) - 1 - (h) total: 0 errors, 0 warnings, 3 checks, 56 lines checked 041791be97ad bits: introduce fixed-type BIT -:32: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'b' - possible side-effects? #32: FILE: include/linux/bits.h:82: +#define BIT_U8(b) (BIT_INPUT_CHECK(u8, b) + (unsigned int)BIT(b)) -:33: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'b' - possible side-effects? #33: FILE: include/linux/bits.h:83: +#define BIT_U16(b) (BIT_INPUT_CHECK(u16, b) + (unsigned int)BIT(b)) -:34: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'b' - possible side-effects? #34: FILE: include/linux/bits.h:84: +#define BIT_U32(b) (BIT_INPUT_CHECK(u32, b) + (u32)BIT(b)) -:35: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'b' - possible side-effects? #35: FILE: include/linux/bits.h:85: +#define BIT_U64(b) (BIT_INPUT_CHECK(u64, b) + (u64)BIT_ULL(b)) total: 0 errors, 0 warnings, 4 checks, 22 lines checked a4780cb0f51e drm/i915: Convert REG_GENMASK* to fixed-width GENMASK_* 669a27a65a3a test_bits: add tests for __GENMASK() and __GENMASK_ULL() d734241f0452 test_bits: add tests for fixed-type genmasks -:26: ERROR:SPACING: spaces required around that ':' (ctx:VxW) #26: FILE: lib/test_bits.c:10: +#define assert_type(t, x) _Generic(x, t: x, default: 0) ^ -:26: ERROR:SPACING: spaces required around that ':' (ctx:VxW) #26: FILE: lib/test_bits.c:10: +#define assert_type(t, x) _Generic(x, t: x, default: 0) ^ -:26: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'x' - possible side-effects? #26: FILE: lib/test_bits.c:10: +#define assert_type(t, x) _Generic(x, t: x, default: 0) total: 2 errors, 0 warnings, 1 checks, 37 lines checked 78ae5fb1ad3d test_bits: add tests for fixed-type BIT
✗ Fi.CI.SPARSE: warning for bits: Fixed-type GENMASK()/BIT() (rev2)
== Series Details == Series: bits: Fixed-type GENMASK()/BIT() (rev2) URL : https://patchwork.freedesktop.org/series/145997/ State : warning == Summary == Error: dim sparse failed Sparse version: v0.6.2 Fast mode used, each commit won't be checked separately.
[RFC PATCH 05/11] drm/i915/psr: Write PIPEDMC_BLOCK_PKGC_SW when enabling PSR
Write PIPEDMC_BLOCK_PKGC_SW when enabling PSR as described in workaround for underrun on idle PSR HW issue (Wa_16025596647). Bspec: 74151 Signed-off-by: Jouni Högander --- drivers/gpu/drm/i915/display/intel_psr.c | 15 +++ 1 file changed, 15 insertions(+) diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c index 1415e1e7aaf2..a3946eef44f0 100644 --- a/drivers/gpu/drm/i915/display/intel_psr.c +++ b/drivers/gpu/drm/i915/display/intel_psr.c @@ -37,6 +37,7 @@ #include "intel_de.h" #include "intel_display_irq.h" #include "intel_display_types.h" +#include "intel_dmc_regs.h" #include "intel_dp.h" #include "intel_dp_aux.h" #include "intel_frontbuffer.h" @@ -1961,6 +1962,13 @@ static void intel_psr_enable_source(struct intel_dp *intel_dp, intel_de_rmw(display, CLKGATE_DIS_MISC, 0, CLKGATE_DIS_MISC_DMASC_GATING_DIS); } + + /* Wa_16025596647 */ + if ((DISPLAY_VER(display) == 20 || +IS_DISPLAY_VERx100_STEP(display, 3000, STEP_A0, STEP_B0)) && + !intel_dp->psr.panel_replay_enabled) + intel_de_rmw(display, PIPEDMC_BLOCK_PKGC_SW(intel_dp->psr.pipe), 0, +PIPEDMC_BLOCK_PKGC_SW_BLOCK_PKGC_ALWAYS); } static bool psr_interrupt_error_check(struct intel_dp *intel_dp) @@ -2186,6 +2194,13 @@ static void intel_psr_disable_locked(struct intel_dp *intel_dp) DP_RECEIVER_ALPM_CONFIG, 0); } + /* Wa_16025596647 */ + if ((DISPLAY_VER(display) == 20 || +IS_DISPLAY_VERx100_STEP(display, 3000, STEP_A0, STEP_B0)) && + !intel_dp->psr.panel_replay_enabled) + intel_de_rmw(display, PIPEDMC_BLOCK_PKGC_SW(intel_dp->psr.pipe), +PIPEDMC_BLOCK_PKGC_SW_BLOCK_PKGC_ALWAYS, 0); + intel_dp->psr.enabled = false; intel_dp->psr.panel_replay_enabled = false; intel_dp->psr.sel_update_enabled = false; -- 2.43.0
[RFC PATCH 00/11] Underrun on idle PSR workaround
This patchset is implementing workaround for underrun on idle PSR HW bug. It is adding notification mechanisms toward PSR for pipe enable/disable, vblank enable/disable and enabling disabling DC5/DC6. These notifications are used to apply/remove the workaround. Current mechanism to block DC states while vblank is enabled on Panel Replay capable system is extended to work for this new workaround as well. Jouni Högander (11): drm/i915/display: Add new interface for getting dc_state drm/i915/psr: Store enabled non-psr pipes into intel_crtc_state drm/i915/dmc: Add PIPEDMC_EVT_CTL register definition drm/i915/dmc: Add PIPEDMC_BLOCK_PKGC_SW definitions drm/i915/psr: Write PIPEDMC_BLOCK_PKGC_SW when enabling PSR drm/i915/psr: Add mechanism to notify PSR of pipe enable/disable drm/i915/psr: Add mechanism to notify PSR of DC5/6 enable disable drm/i915/psr: Add interface to notify PSR of vblank enable/disable drm/i915/psr: Apply underrun on PSR idle workaround drm/i915/display: Rename intel_psr_needs_block_dc_vblank drm/i915/display: Rename vblank DC workaround functions and variables drivers/gpu/drm/i915/display/intel_crtc.c | 6 +- drivers/gpu/drm/i915/display/intel_display.c | 4 + .../gpu/drm/i915/display/intel_display_core.h | 6 +- .../drm/i915/display/intel_display_driver.c | 3 + .../gpu/drm/i915/display/intel_display_irq.c | 27 +- .../drm/i915/display/intel_display_power.c| 29 ++ .../drm/i915/display/intel_display_power.h| 1 + .../i915/display/intel_display_power_well.c | 4 + .../drm/i915/display/intel_display_types.h| 5 +- drivers/gpu/drm/i915/display/intel_dmc_regs.h | 14 + drivers/gpu/drm/i915/display/intel_psr.c | 271 +- drivers/gpu/drm/i915/display/intel_psr.h | 8 +- 12 files changed, 348 insertions(+), 30 deletions(-) -- 2.43.0
[RFC PATCH 03/11] drm/i915/dmc: Add PIPEDMC_EVT_CTL register definition
To implement workaround for underrun on idle PSR HW issue (Wa_16025596647) we need PIPEDMC_EVT_CTL_4 register. Add PIPEDMC_EVT_CTL_4 register definitions. Bspec: 67576 Signed-off-by: Jouni Högander --- drivers/gpu/drm/i915/display/intel_dmc_regs.h | 6 ++ 1 file changed, 6 insertions(+) diff --git a/drivers/gpu/drm/i915/display/intel_dmc_regs.h b/drivers/gpu/drm/i915/display/intel_dmc_regs.h index 1bf446f96a10..2f1e3cb1a247 100644 --- a/drivers/gpu/drm/i915/display/intel_dmc_regs.h +++ b/drivers/gpu/drm/i915/display/intel_dmc_regs.h @@ -21,6 +21,12 @@ #define MTL_PIPEDMC_CONTROL_MMIO(0x45250) #define PIPEDMC_ENABLE_MTL(pipe) REG_BIT(((pipe) - PIPE_A) * 4) +#define _MTL_PIPEDMC_EVT_CTL_4_A 0x5f044 +#define _MTL_PIPEDMC_EVT_CTL_4_B 0x5f444 +#define MTL_PIPEDMC_EVT_CTL_4(pipe)_MMIO_PIPE(pipe,\ + _MTL_PIPEDMC_EVT_CTL_4_A, \ + _MTL_PIPEDMC_EVT_CTL_4_B) + #define _ADLP_PIPEDMC_REG_MMIO_BASE_A 0x5f000 #define _TGL_PIPEDMC_REG_MMIO_BASE_A 0x92000 -- 2.43.0
[RFC PATCH 01/11] drm/i915/display: Add new interface for getting dc_state
To implement workaround for underrun on idle PSR HW issue (Wa_16025596647)
we need to have current configured DC state available. Add new interface
for this purpose.
Signed-off-by: Jouni Högander
---
.../drm/i915/display/intel_display_power.c| 29 +++
.../drm/i915/display/intel_display_power.h| 1 +
2 files changed, 30 insertions(+)
diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c
b/drivers/gpu/drm/i915/display/intel_display_power.c
index f7171e6932dc..6dfe85a5528f 100644
--- a/drivers/gpu/drm/i915/display/intel_display_power.c
+++ b/drivers/gpu/drm/i915/display/intel_display_power.c
@@ -322,6 +322,35 @@ void intel_display_power_set_target_dc_state(struct
intel_display *display,
mutex_unlock(&power_domains->lock);
}
+/**
+ * intel_display_power_get_current_dc_state - Set target dc state.
+ * @display: display device
+ *
+ * This function set the "DC off" power well target_dc_state,
+ * based upon this target_dc_stste, "DC off" power well will
+ * enable desired DC state.
+ */
+u32 intel_display_power_get_current_dc_state(struct intel_display *display)
+{
+ struct i915_power_well *power_well;
+ struct i915_power_domains *power_domains = &display->power.domains;
+ u32 current_dc_state = DC_STATE_DISABLE;
+
+ mutex_lock(&power_domains->lock);
+ power_well = lookup_power_well(display, SKL_DISP_DC_OFF);
+
+ if (drm_WARN_ON(display->drm, !power_well))
+ goto unlock;
+
+ current_dc_state = intel_power_well_is_enabled(display, power_well) ?
+ DC_STATE_DISABLE : power_domains->target_dc_state;
+
+unlock:
+ mutex_unlock(&power_domains->lock);
+
+ return current_dc_state;
+}
+
static void __async_put_domains_mask(struct i915_power_domains *power_domains,
struct intel_power_domain_mask *mask)
{
diff --git a/drivers/gpu/drm/i915/display/intel_display_power.h
b/drivers/gpu/drm/i915/display/intel_display_power.h
index 1b53d67f9b60..f8813b0e16df 100644
--- a/drivers/gpu/drm/i915/display/intel_display_power.h
+++ b/drivers/gpu/drm/i915/display/intel_display_power.h
@@ -183,6 +183,7 @@ void intel_display_power_suspend(struct intel_display
*display);
void intel_display_power_resume(struct intel_display *display);
void intel_display_power_set_target_dc_state(struct intel_display *display,
u32 state);
+u32 intel_display_power_get_current_dc_state(struct intel_display *display);
bool intel_display_power_is_enabled(struct intel_display *display,
enum intel_display_power_domain domain);
--
2.43.0
[RFC PATCH 06/11] drm/i915/psr: Add mechanism to notify PSR of pipe enable/disable
We need to apply/remove workaround for underrun on idle PSR HW issue
(Wa_16025596647) when new pipe is enabled or pipe is getting disabled. This
patch implements mechanism to notify PSR about pipe enable/disable and
applies/removes the workaround using this notification.
Bspec: 74151
Signed-off-by: Jouni Högander
---
drivers/gpu/drm/i915/display/intel_psr.c | 106 +++
drivers/gpu/drm/i915/display/intel_psr.h | 2 +
2 files changed, 108 insertions(+)
diff --git a/drivers/gpu/drm/i915/display/intel_psr.c
b/drivers/gpu/drm/i915/display/intel_psr.c
index a3946eef44f0..4b62d5832cbf 100644
--- a/drivers/gpu/drm/i915/display/intel_psr.c
+++ b/drivers/gpu/drm/i915/display/intel_psr.c
@@ -26,6 +26,7 @@
#include
#include
#include
+#include
#include "i915_drv.h"
#include "i915_reg.h"
@@ -3664,6 +3665,111 @@ void intel_psr_unlock(const struct intel_crtc_state
*crtc_state)
}
}
+/* Wa_16025596647 */
+static void psr1_apply_underrun_on_idle_wa_locked(struct intel_dp *intel_dp,
+ bool dc5_dc6_blocked)
+{
+ struct intel_display *display = to_intel_display(intel_dp);
+ u32 val;
+
+ if (dc5_dc6_blocked)
+ val = DMC_EVT_CTL_ENABLE | DMC_EVT_CTL_RECURRING |
+ REG_FIELD_PREP(DMC_EVT_CTL_TYPE_MASK,
+ DMC_EVT_CTL_TYPE_EDGE_0_1) |
+ REG_FIELD_PREP(DMC_EVT_CTL_EVENT_ID_MASK,
+ DMC_EVT_CTL_EVENT_ID_VBLANK_A);
+ else
+ val = REG_FIELD_PREP(DMC_EVT_CTL_EVENT_ID_MASK,
+DMC_EVT_CTL_EVENT_ID_FALSE) |
+ REG_FIELD_PREP(DMC_EVT_CTL_TYPE_MASK,
+ DMC_EVT_CTL_TYPE_EDGE_0_1);
+
+ intel_de_write(display, MTL_PIPEDMC_EVT_CTL_4(intel_dp->psr.pipe),
+ val);
+}
+
+/* Wa_16025596647 */
+static bool is_dc5_dc6_blocked(struct intel_dp *intel_dp)
+{
+ struct intel_display *display = to_intel_display(intel_dp);
+ u32 current_dc_state =
intel_display_power_get_current_dc_state(display);
+ struct drm_vblank_crtc *vblank =
&display->drm->vblank[intel_dp->psr.pipe];
+
+ return (current_dc_state != DC_STATE_EN_UPTO_DC5 &&
+ current_dc_state != DC_STATE_EN_UPTO_DC6) ||
+ intel_dp->psr.active_non_psr_pipes ||
+ READ_ONCE(vblank->enabled);
+}
+
+/* Wa_16025596647 */
+static void intel_psr_apply_underrun_on_idle_wa_locked(struct intel_dp
*intel_dp)
+{
+ bool dc5_dc6_blocked;
+
+ if (!intel_dp->psr.active)
+ return;
+
+ dc5_dc6_blocked = is_dc5_dc6_blocked(intel_dp);
+
+ if (intel_dp->psr.sel_update_enabled)
+ psr2_program_idle_frames(intel_dp, dc5_dc6_blocked ? 0 :
+psr_compute_idle_frames(intel_dp));
+ else
+ psr1_apply_underrun_on_idle_wa_locked(intel_dp,
dc5_dc6_blocked);
+}
+
+/**
+ * intel_psr_notify_pipe_change - Notify PSR about enable/disable of a pipe
+ * @state: intel atomic state
+ * @crtc: intel crtc
+ * @enable: enable/disable
+ *
+ * This is targeted for underrun on idle PSR HW bug (Wa_16025596647) to apply
+ * remove the workaround when pipe is getting enabled/disabled
+ */
+void intel_psr_notify_pipe_change(struct intel_atomic_state *state,
+ struct intel_crtc *crtc, bool enable)
+{
+ struct intel_display *display = to_intel_display(state);
+ struct intel_encoder *encoder;
+
+ if (DISPLAY_VER(display) != 20 &&
+ !IS_DISPLAY_VERx100_STEP(display, 3000, STEP_A0, STEP_B0))
+ return;
+
+ for_each_intel_encoder_with_psr(display->drm, encoder) {
+ struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
+ u8 active_non_psr_pipes;
+
+ mutex_lock(&intel_dp->psr.lock);
+
+ if (!intel_dp->psr.enabled ||
intel_dp->psr.panel_replay_enabled)
+ goto unlock;
+
+ active_non_psr_pipes = intel_dp->psr.active_non_psr_pipes;
+
+ if (enable)
+ active_non_psr_pipes |= BIT(crtc->pipe);
+ else
+ active_non_psr_pipes &= ~BIT(crtc->pipe);
+
+ if (active_non_psr_pipes == intel_dp->psr.active_non_psr_pipes)
+ goto unlock;
+
+ if ((enable && intel_dp->psr.active_non_psr_pipes) ||
+ (!enable && !intel_dp->psr.active_non_psr_pipes)) {
+ intel_dp->psr.active_non_psr_pipes =
active_non_psr_pipes;
+ goto unlock;
+ }
+
+ intel_dp->psr.active_non_psr_pipes = active_non_psr_pipes;
+
+ intel_psr_apply_underrun_on_idle_wa_locked(intel_dp);
+unlock:
+ mutex_unlock(&intel_dp->psr.lock);
+ }
+}
+
static void
psr_sou
[RFC PATCH 08/11] drm/i915/psr: Add interface to notify PSR of vblank enable/disable
To implement Wa_16025596647 we need to get notification of vblank interrupt
enable/disable. Add new interface to PSR code for this notification.
Signed-off-by: Jouni Högander
---
drivers/gpu/drm/i915/display/intel_psr.c | 40
drivers/gpu/drm/i915/display/intel_psr.h | 2 ++
2 files changed, 42 insertions(+)
diff --git a/drivers/gpu/drm/i915/display/intel_psr.c
b/drivers/gpu/drm/i915/display/intel_psr.c
index baf6a7110a55..afb9faed7784 100644
--- a/drivers/gpu/drm/i915/display/intel_psr.c
+++ b/drivers/gpu/drm/i915/display/intel_psr.c
@@ -3820,6 +3820,46 @@ void intel_psr_notify_pipe_change(struct
intel_atomic_state *state,
}
}
+/**
+ * intel_psr_notify_vblank_enable_disable - Notify PSR about enable/disable of
vblank
+ * @display: intel display struct
+ * @enable: enable/disable
+ *
+ * This is targeted for underrun on idle PSR HW bug (Wa_16025596647) to apply
+ * remove the workaround when vblank is getting enabled/disabled
+ */
+void intel_psr_notify_vblank_enable_disable(struct intel_display *display,
+ bool enable)
+{
+ struct intel_encoder *encoder;
+
+ for_each_intel_encoder_with_psr(display->drm, encoder) {
+ struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
+
+ mutex_lock(&intel_dp->psr.lock);
+ if (intel_dp->psr.panel_replay_enabled) {
+ mutex_unlock(&intel_dp->psr.lock);
+ break;
+ }
+
+ if (intel_dp->psr.enabled)
+ intel_psr_apply_underrun_on_idle_wa_locked(intel_dp);
+
+ mutex_unlock(&intel_dp->psr.lock);
+ return;
+ }
+
+ /*
+* NOTE: intel_display_power_set_target_dc_state is used
+* only by PSR * code for DC3CO handling. DC3CO target
+* state is currently disabled in * PSR code. If DC3CO
+* is taken into use we need take that into account here
+* as well.
+*/
+ intel_display_power_set_target_dc_state(display, enable ?
DC_STATE_DISABLE :
+ DC_STATE_EN_UPTO_DC6);
+}
+
static void
psr_source_status(struct intel_dp *intel_dp, struct seq_file *m)
{
diff --git a/drivers/gpu/drm/i915/display/intel_psr.h
b/drivers/gpu/drm/i915/display/intel_psr.h
index bfe368239bc2..a914b7ee3756 100644
--- a/drivers/gpu/drm/i915/display/intel_psr.h
+++ b/drivers/gpu/drm/i915/display/intel_psr.h
@@ -64,6 +64,8 @@ void intel_psr_notify_pipe_change(struct intel_atomic_state
*state,
struct intel_crtc *crtc, bool enable);
void intel_psr_notify_dc5_dc6(struct intel_display *display);
void intel_psr_dc5_dc6_wa_init(struct intel_display *display);
+void intel_psr_notify_vblank_enable_disable(struct intel_display *display,
+ bool enable);
bool intel_psr_link_ok(struct intel_dp *intel_dp);
void intel_psr_lock(const struct intel_crtc_state *crtc_state);
--
2.43.0
[RFC PATCH 02/11] drm/i915/psr: Store enabled non-psr pipes into intel_crtc_state
To implement workaround for underrun on idle PSR HW issue (Wa_16025596647)
we need to know enabled. Figure out which non-PSR pipes we will have active
and store it into intel_crtc_state->active_non_psr_pipes. This is currently
assuming only one eDP on a time. I.e. possible secondary eDP with PSR
capable panel is not considered.
Bspec: 74151
Signed-off-by: Jouni Högander
---
.../drm/i915/display/intel_display_types.h| 3 +++
drivers/gpu/drm/i915/display/intel_psr.c | 23 +++
2 files changed, 26 insertions(+)
diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h
b/drivers/gpu/drm/i915/display/intel_display_types.h
index 99a6fd2900b9..3d203a2003f1 100644
--- a/drivers/gpu/drm/i915/display/intel_display_types.h
+++ b/drivers/gpu/drm/i915/display/intel_display_types.h
@@ -1114,6 +1114,7 @@ struct intel_crtc_state {
bool wm_level_disabled;
u32 dc3co_exitline;
u16 su_y_granularity;
+ u8 active_non_psr_pipes;
/*
* Frequency the dpll for the port should run at. Differs from the
@@ -1650,6 +1651,8 @@ struct intel_psr {
u8 entry_setup_frames;
bool link_ok;
+
+ u8 active_non_psr_pipes;
};
struct intel_dp {
diff --git a/drivers/gpu/drm/i915/display/intel_psr.c
b/drivers/gpu/drm/i915/display/intel_psr.c
index 4e938bad808c..1415e1e7aaf2 100644
--- a/drivers/gpu/drm/i915/display/intel_psr.c
+++ b/drivers/gpu/drm/i915/display/intel_psr.c
@@ -1658,6 +1658,9 @@ void intel_psr_compute_config(struct intel_dp *intel_dp,
{
struct intel_display *display = to_intel_display(intel_dp);
const struct drm_display_mode *adjusted_mode =
&crtc_state->hw.adjusted_mode;
+ struct intel_atomic_state *state =
to_intel_atomic_state(crtc_state->uapi.state);
+ struct intel_crtc *crtc;
+ u8 active_pipes = 0;
if (!psr_global_enabled(intel_dp)) {
drm_dbg_kms(display->drm, "PSR disabled by flag\n");
@@ -1711,6 +1714,24 @@ void intel_psr_compute_config(struct intel_dp *intel_dp,
drm_dbg_kms(display->drm,
"PSR disabled to workaround PSR FSM hang issue\n");
}
+
+ /* Rest is for Wa_16025596647 */
+ if (DISPLAY_VER(display) != 20 &&
+ !IS_DISPLAY_VERx100_STEP(display, 3000, STEP_A0, STEP_B0))
+ return;
+
+ /* Not needed by Panel Replay */
+ if (crtc_state->has_panel_replay)
+ return;
+
+ /* We ignore possible secondary PSR/Panel Replay capable eDP */
+ for_each_intel_crtc(display->drm, crtc)
+ active_pipes |= crtc->active ? BIT(crtc->pipe) : 0;
+
+ active_pipes = intel_calc_active_pipes(state, active_pipes);
+
+ crtc_state->active_non_psr_pipes = active_pipes &
+ ~BIT(to_intel_crtc(crtc_state->uapi.crtc)->pipe);
}
void intel_psr_get_config(struct intel_encoder *encoder,
@@ -1995,6 +2016,7 @@ static void intel_psr_enable_locked(struct intel_dp
*intel_dp,
intel_dp->psr.psr2_sel_fetch_cff_enabled = false;
intel_dp->psr.req_psr2_sdp_prior_scanline =
crtc_state->req_psr2_sdp_prior_scanline;
+ intel_dp->psr.active_non_psr_pipes = crtc_state->active_non_psr_pipes;
if (!psr_interrupt_error_check(intel_dp))
return;
@@ -2170,6 +2192,7 @@ static void intel_psr_disable_locked(struct intel_dp
*intel_dp)
intel_dp->psr.psr2_sel_fetch_enabled = false;
intel_dp->psr.su_region_et_enabled = false;
intel_dp->psr.psr2_sel_fetch_cff_enabled = false;
+ intel_dp->psr.active_non_psr_pipes = 0;
}
/**
--
2.43.0
[RFC PATCH 04/11] drm/i915/dmc: Add PIPEDMC_BLOCK_PKGC_SW definitions
We need PIPEDMC_BLOCK_PKGC_SW definitions to implement workaround for underrun on idle PSR HW issue (Wa_16025596647). Add PIPEDMC_BLOCK_PKGC_SW register definitions. Bspec: 71265 Signed-off-by: Jouni Högander --- drivers/gpu/drm/i915/display/intel_dmc_regs.h | 8 1 file changed, 8 insertions(+) diff --git a/drivers/gpu/drm/i915/display/intel_dmc_regs.h b/drivers/gpu/drm/i915/display/intel_dmc_regs.h index 2f1e3cb1a247..e16ea3f16ed8 100644 --- a/drivers/gpu/drm/i915/display/intel_dmc_regs.h +++ b/drivers/gpu/drm/i915/display/intel_dmc_regs.h @@ -27,6 +27,14 @@ _MTL_PIPEDMC_EVT_CTL_4_A, \ _MTL_PIPEDMC_EVT_CTL_4_B) +#define PIPEDMC_BLOCK_PKGC_SW_A0x5f1d0 +#define PIPEDMC_BLOCK_PKGC_SW_B0x5F5d0 +#define PIPEDMC_BLOCK_PKGC_SW(pipe) _MMIO_PIPE(pipe, \ + PIPEDMC_BLOCK_PKGC_SW_A, \ + PIPEDMC_BLOCK_PKGC_SW_B) +#define PIPEDMC_BLOCK_PKGC_SW_BLOCK_PKGC_ALWAYSBIT(31) +#define PIPEDMC_BLOCK_PKGC_SW_BLOCK_PKGC_UNTIL_NEXT_FRAMESTART BIT(15) + #define _ADLP_PIPEDMC_REG_MMIO_BASE_A 0x5f000 #define _TGL_PIPEDMC_REG_MMIO_BASE_A 0x92000 -- 2.43.0
[RFC PATCH 11/11] drm/i915/display: Rename vblank DC workaround functions and variables
We have extended using vblank DC workaround mechanism for
Wa_16025596647. Rename related functions and variables:
vblank_wa_num_pipes -> vblank_enable_count
vblank_dc_work -> vblank_notify_work
intel_display_vblank_dc_work -> intel_display_vblank_notify_work
Signed-off-by: Jouni Högander
---
drivers/gpu/drm/i915/display/intel_crtc.c | 2 +-
.../gpu/drm/i915/display/intel_display_core.h | 4 ++--
.../gpu/drm/i915/display/intel_display_irq.c | 20 +--
3 files changed, 13 insertions(+), 13 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_crtc.c
b/drivers/gpu/drm/i915/display/intel_crtc.c
index bdf30ab96396..537859630363 100644
--- a/drivers/gpu/drm/i915/display/intel_crtc.c
+++ b/drivers/gpu/drm/i915/display/intel_crtc.c
@@ -156,7 +156,7 @@ void intel_crtc_vblank_off(const struct intel_crtc_state
*crtc_state)
crtc->vblank_psr_notify = false;
- flush_work(&display->irq.vblank_dc_work);
+ flush_work(&display->irq.vblank_notify_work);
}
struct intel_crtc_state *intel_crtc_state_alloc(struct intel_crtc *crtc)
diff --git a/drivers/gpu/drm/i915/display/intel_display_core.h
b/drivers/gpu/drm/i915/display/intel_display_core.h
index b765a2ef9a6c..c93cab1266c5 100644
--- a/drivers/gpu/drm/i915/display/intel_display_core.h
+++ b/drivers/gpu/drm/i915/display/intel_display_core.h
@@ -464,9 +464,9 @@ struct intel_display {
/* For i915gm/i945gm vblank irq workaround */
u8 vblank_enabled;
- int vblank_wa_num_pipes;
+ int vblank_enable_count;
- struct work_struct vblank_dc_work;
+ struct work_struct vblank_notify_work;
u32 de_irq_mask[I915_MAX_PIPES];
u32 pipestat_irq_mask[I915_MAX_PIPES];
diff --git a/drivers/gpu/drm/i915/display/intel_display_irq.c
b/drivers/gpu/drm/i915/display/intel_display_irq.c
index 833f8227da80..22942edf5ff0 100644
--- a/drivers/gpu/drm/i915/display/intel_display_irq.c
+++ b/drivers/gpu/drm/i915/display/intel_display_irq.c
@@ -1722,13 +1722,13 @@ static bool gen11_dsi_configure_te(struct intel_crtc
*intel_crtc,
return true;
}
-static void intel_display_vblank_dc_work(struct work_struct *work)
+static void intel_display_vblank_notify_work(struct work_struct *work)
{
struct intel_display *display =
- container_of(work, typeof(*display), irq.vblank_dc_work);
- int vblank_wa_num_pipes = READ_ONCE(display->irq.vblank_wa_num_pipes);
+ container_of(work, typeof(*display), irq.vblank_notify_work);
+ int vblank_enable_count = READ_ONCE(display->irq.vblank_enable_count);
- intel_psr_notify_vblank_enable_disable(display, vblank_wa_num_pipes);
+ intel_psr_notify_vblank_enable_disable(display, vblank_enable_count);
}
int bdw_enable_vblank(struct drm_crtc *_crtc)
@@ -1742,8 +1742,8 @@ int bdw_enable_vblank(struct drm_crtc *_crtc)
if (gen11_dsi_configure_te(crtc, true))
return 0;
- if (crtc->vblank_psr_notify && display->irq.vblank_wa_num_pipes++ == 0)
- schedule_work(&display->irq.vblank_dc_work);
+ if (crtc->vblank_psr_notify && display->irq.vblank_enable_count++ == 0)
+ schedule_work(&display->irq.vblank_notify_work);
spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
bdw_enable_pipe_irq(dev_priv, pipe, GEN8_PIPE_VBLANK);
@@ -1773,8 +1773,8 @@ void bdw_disable_vblank(struct drm_crtc *_crtc)
bdw_disable_pipe_irq(dev_priv, pipe, GEN8_PIPE_VBLANK);
spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
- if (crtc->vblank_psr_notify && --display->irq.vblank_wa_num_pipes == 0)
- schedule_work(&display->irq.vblank_dc_work);
+ if (crtc->vblank_psr_notify && --display->irq.vblank_enable_count == 0)
+ schedule_work(&display->irq.vblank_notify_work);
}
static u32 vlv_dpinvgtt_pipe_fault_mask(enum pipe pipe)
@@ -2345,6 +2345,6 @@ void intel_display_irq_init(struct drm_i915_private *i915)
intel_hotplug_irq_init(i915);
- INIT_WORK(&i915->display.irq.vblank_dc_work,
- intel_display_vblank_dc_work);
+ INIT_WORK(&i915->display.irq.vblank_notify_work,
+ intel_display_vblank_notify_work);
}
--
2.43.0
RE: [PATCH v2 1/2] drm/xe/compat: refactor compat i915_drv.h
On Thu, 06 Mar 2025, "Garg, Nemesa" wrote: >> -Original Message- >> From: Intel-gfx On Behalf Of Jani >> Nikula >> @@ -0,0 +1,15 @@ >> +/* SPDX-License-Identifier: MIT */ >> +/* Copyright © 2025 Intel Corporation */ >> + >> +#ifndef __I915_GEM_OBJECT_H__ >> +#define __i915_GEM_OBJECT_H__ Exceptionally, I took the liberty of fixing this while applying. It was pure luck that I caught it with clang's -Wheader-guard [1]. [1] https://clang.llvm.org/docs/DiagnosticsReference.html#wheader-guard > Reviewed-by: Nemesa Garg Thanks for the review, series pushed to din. BR, Jani. -- Jani Nikula, Intel
Re: [PATCH v2] i915/selftest/igt_mmap: let mmap tests run in kthread
Quoting Mikolaj Wasiak (2025-03-07 08:44:29) > Hi Krzysztof, > > On 2025-03-05 at 17:31:49 +0100, Krzysztof Niemiec wrote: > > Don't we run into the same issue as in V1, meaning we use an unknown > > current->active_mm (since we run in a kthread, and cannot control it) to > > use as the current->mm? Maybe a better approach would be to create a new > > mm for the duration of the test, similarly to how the patch Janusz > > mentioned does it? (51104c19d857) > > As per discussion with Chris, using active_mm is the correct way of > enabling current->mm in kthread. On the other hand it may also expose > issues with underlying tests because they didn't previously run on such > hardware. I think potential fixes to those tests should be addressed in > separate patch. We've looked at the tests, and they should all be finding unused space in the mm and cleaning up after themselves... If we put on our paranoia hats, the biggest problem with borrowing userspace's mm is that it gives them temporary insight into whatever we place into that mm. We don't expose any data, unless by error... Not sure how much effort we want to put on making the selftests paranoia proof, but that (and the surety of cleaning up afterwards) would be a good argument for creating a temporary mm for our use. -Chris
✗ i915.CI.BAT: failure for i915/gt/selftest_lrc: Disable timestamp test
== Series Details == Series: i915/gt/selftest_lrc: Disable timestamp test URL : https://patchwork.freedesktop.org/series/145991/ State : failure == Summary == CI Bug Log - changes from CI_DRM_16245 -> Patchwork_145991v1 Summary --- **FAILURE** Serious unknown changes coming with Patchwork_145991v1 absolutely need to be verified manually. If you think the reported changes have nothing to do with the changes introduced in Patchwork_145991v1, please notify your bug team (i915-ci-in...@lists.freedesktop.org) to allow them to document this new failure mode, which will reduce false positives in CI. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_145991v1/index.html Participating hosts (44 -> 42) -- Missing(2): bat-arlh-2 fi-snb-2520m Possible new issues --- Here are the unknown changes that may have been introduced in Patchwork_145991v1: ### IGT changes ### Possible regressions * igt@kms_cursor_legacy@basic-flip-after-cursor-legacy: - bat-apl-1: [PASS][1] -> [DMESG-WARN][2] [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16245/bat-apl-1/igt@kms_cursor_leg...@basic-flip-after-cursor-legacy.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_145991v1/bat-apl-1/igt@kms_cursor_leg...@basic-flip-after-cursor-legacy.html Known issues Here are the changes found in Patchwork_145991v1 that come from known issues: ### IGT changes ### Issues hit * igt@fbdev@info: - fi-kbl-8809g: NOTRUN -> [SKIP][3] ([i915#1849]) [3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_145991v1/fi-kbl-8809g/igt@fb...@info.html * igt@gem_huc_copy@huc-copy: - fi-kbl-8809g: NOTRUN -> [SKIP][4] ([i915#2190]) [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_145991v1/fi-kbl-8809g/igt@gem_huc_c...@huc-copy.html * igt@gem_lmem_swapping@parallel-random-engines: - fi-kbl-8809g: NOTRUN -> [SKIP][5] ([i915#4613]) +3 other tests skip [5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_145991v1/fi-kbl-8809g/igt@gem_lmem_swapp...@parallel-random-engines.html * igt@i915_pm_rpm@module-reload: - bat-dg1-7: [PASS][6] -> [FAIL][7] ([i915#13633]) [6]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16245/bat-dg1-7/igt@i915_pm_...@module-reload.html [7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_145991v1/bat-dg1-7/igt@i915_pm_...@module-reload.html * igt@i915_selftest@live@workarounds: - bat-arls-6: [PASS][8] -> [DMESG-FAIL][9] ([i915#12061]) +1 other test dmesg-fail [8]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16245/bat-arls-6/igt@i915_selftest@l...@workarounds.html [9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_145991v1/bat-arls-6/igt@i915_selftest@l...@workarounds.html * igt@kms_dsc@dsc-basic: - fi-kbl-8809g: NOTRUN -> [SKIP][10] +34 other tests skip [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_145991v1/fi-kbl-8809g/igt@kms_...@dsc-basic.html * igt@kms_pipe_crc_basic@nonblocking-crc-frame-sequence: - bat-dg2-11: [PASS][11] -> [SKIP][12] ([i915#9197]) +3 other tests skip [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16245/bat-dg2-11/igt@kms_pipe_crc_ba...@nonblocking-crc-frame-sequence.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_145991v1/bat-dg2-11/igt@kms_pipe_crc_ba...@nonblocking-crc-frame-sequence.html [i915#12061]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/12061 [i915#13633]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/13633 [i915#1849]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/1849 [i915#2190]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/2190 [i915#4613]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4613 [i915#9197]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9197 Build changes - * Linux: CI_DRM_16245 -> Patchwork_145991v1 CI-20190529: 20190529 CI_DRM_16245: 066c46f28642479869d2d1dd27cc6ae476de4abc @ git://anongit.freedesktop.org/gfx-ci/linux IGT_8264: 8264 Patchwork_145991v1: 066c46f28642479869d2d1dd27cc6ae476de4abc @ git://anongit.freedesktop.org/gfx-ci/linux == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_145991v1/index.html
Re: [PATCH 15/21] drm/i915/display: Use fixed_rr timings in modeset sequence
On Fri, Mar 07, 2025 at 05:33:46PM +0530, Nautiyal, Ankit K wrote:
>
> On 3/6/2025 10:16 PM, Ville Syrjälä wrote:
> > On Thu, Mar 06, 2025 at 06:40:54PM +0530, Ankit Nautiyal wrote:
> >> During modeset enable sequence, program the fixed timings, and turn on the
> >> VRR Timing Generator (VRR TG) for platforms that always use VRR TG.
> >>
> >> For this intel_vrr_set_transcoder now always programs fixed timings.
> >> Later if vrr timings are required, vrr_enable() will switch
> >> to the real VRR timings.
> >>
> >> For platforms that will always use VRR TG, the VRR_CTL Enable bit is set
> >> and reset in the transcoder enable/disable path.
> >>
> >> v2: Update intel_vrr_set_transcoder_timings for fixed_rr.
> >> v3: Update intel_set_transcoder_timings_lrr for fixed_rr. (Ville)
> >> v4: Have separate functions to enable/disable VRR CTL
> >> v5:
> >> -For platforms that do not always have VRRTG on, do write bits other
> >> than enable bit and also use write the TRANS_VRR_PUSH register. (Ville)
> >> -Avoid writing trans_ctl_vrr if !vrr_possible().
> >> v6:
> >> -Disable VRR just before intel_ddi_disable_transcoder_func(). (Ville)
> >> -Correct the sequence of configuring PUSH and VRR Enable/Disable. (Ville)
> >>
> >> Signed-off-by: Ankit Nautiyal
> >> ---
> >> drivers/gpu/drm/i915/display/intel_ddi.c| 5 ++
> >> drivers/gpu/drm/i915/display/intel_dp_mst.c | 4 ++
> >> drivers/gpu/drm/i915/display/intel_vrr.c| 63 -
> >> drivers/gpu/drm/i915/display/intel_vrr.h| 2 +
> >> 4 files changed, 60 insertions(+), 14 deletions(-)
> >>
> >> diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c
> >> b/drivers/gpu/drm/i915/display/intel_ddi.c
> >> index 676c1826f15c..6d89a87b3419 100644
> >> --- a/drivers/gpu/drm/i915/display/intel_ddi.c
> >> +++ b/drivers/gpu/drm/i915/display/intel_ddi.c
> >> @@ -78,6 +78,7 @@
> >> #include "intel_tc.h"
> >> #include "intel_vdsc.h"
> >> #include "intel_vdsc_regs.h"
> >> +#include "intel_vrr.h"
> >> #include "skl_scaler.h"
> >> #include "skl_universal_plane.h"
> >>
> >> @@ -3248,6 +3249,8 @@ static void
> >> intel_ddi_post_disable_hdmi_or_sst(struct intel_atomic_state *state,
> >>drm_dp_dpcd_poll_act_handled(&intel_dp->aux, 0);
> >>}
> >>
> >> + intel_vrr_transcoder_disable(old_crtc_state);
> >> +
> >>intel_ddi_disable_transcoder_func(old_crtc_state);
> >>
> >>for_each_pipe_crtc_modeset_disable(display, pipe_crtc, old_crtc_state,
> >> i) {
> >> @@ -3521,6 +3524,8 @@ static void intel_ddi_enable(struct
> >> intel_atomic_state *state,
> >>
> >>intel_ddi_enable_transcoder_func(encoder, crtc_state);
> >>
> >> + intel_vrr_transcoder_enable(crtc_state);
> >> +
> >>/* Enable/Disable DP2.0 SDP split config before transcoder */
> >>intel_audio_sdp_split_update(crtc_state);
> >>
> >> diff --git a/drivers/gpu/drm/i915/display/intel_dp_mst.c
> >> b/drivers/gpu/drm/i915/display/intel_dp_mst.c
> >> index bd47cf127b4c..d2988b9a6e7b 100644
> >> --- a/drivers/gpu/drm/i915/display/intel_dp_mst.c
> >> +++ b/drivers/gpu/drm/i915/display/intel_dp_mst.c
> >> @@ -1065,6 +1065,8 @@ static void mst_stream_post_disable(struct
> >> intel_atomic_state *state,
> >>drm_dp_remove_payload_part2(&intel_dp->mst.mgr, new_mst_state,
> >>old_payload, new_payload);
> >>
> >> + intel_vrr_transcoder_disable(old_crtc_state);
> >> +
> >>intel_ddi_disable_transcoder_func(old_crtc_state);
> >>
> >>for_each_pipe_crtc_modeset_disable(display, pipe_crtc, old_crtc_state,
> >> i) {
> >> @@ -1326,6 +1328,8 @@ static void mst_stream_enable(struct
> >> intel_atomic_state *state,
> >>
> >>intel_ddi_enable_transcoder_func(encoder, pipe_config);
> >>
> >> + intel_vrr_transcoder_enable(pipe_config);
> >> +
> >>intel_ddi_clear_act_sent(encoder, pipe_config);
> >>
> >>intel_de_rmw(display, TRANS_DDI_FUNC_CTL(display, trans), 0,
> >> diff --git a/drivers/gpu/drm/i915/display/intel_vrr.c
> >> b/drivers/gpu/drm/i915/display/intel_vrr.c
> >> index f523a48e6186..d7580b6e4e37 100644
> >> --- a/drivers/gpu/drm/i915/display/intel_vrr.c
> >> +++ b/drivers/gpu/drm/i915/display/intel_vrr.c
> >> @@ -460,12 +460,6 @@ void intel_vrr_set_transcoder_timings(const struct
> >> intel_crtc_state *crtc_state)
> >>intel_de_rmw(display, CHICKEN_TRANS(display, cpu_transcoder),
> >> 0, PIPE_VBLANK_WITH_DELAY);
> >>
> >> - if (!intel_vrr_possible(crtc_state)) {
> >> - intel_de_write(display,
> >> - TRANS_VRR_CTL(display, cpu_transcoder), 0);
> >> - return;
> >> - }
> >> -
> >>if (crtc_state->cmrr.enable) {
> >>intel_de_write(display, TRANS_CMRR_M_HI(display,
> >> cpu_transcoder),
> >> upper_32_bits(crtc_state->cmrr.cmrr_m));
> >> @@ -477,14 +471,7 @@ void intel_vrr_set_transcoder_timings(const struct
> >> intel_crtc_state *crtc_state)
> >>
✗ Fi.CI.SPARSE: warning for drm/display: dp: add new DPCD access functions
== Series Details == Series: drm/display: dp: add new DPCD access functions URL : https://patchwork.freedesktop.org/series/145998/ State : warning == Summary == Error: dim sparse failed Sparse version: v0.6.2 Fast mode used, each commit won't be checked separately.
Re: [PULL] drm-xe-next
On Fri, Mar 07, 2025 at 02:02:15AM -0600, Lucas De Marchi wrote: Hi Dave and Sima, Last drm-xe-next pull request for 6.15. It comes with some big features that we have been working on for some time: EU stall sampling and SVM. The latter also touches other subsystems and provides the common parts in the drm layer. Low latency hints from userspace to improve some workloads and more events exposed via perf complete the UAPI changes for this cycle. Another cross-subsystem change is to drivers/base to improve devres handling. Fixes, workarounds and refactors also made their appearance as usual. Worth noting 2 conflicts reported by Stephen on linux-next. One is a git conflict and the other is on build: https://lore.kernel.org/intel-xe/20250307122954.1ab65...@canb.auug.org.au/ and https://lore.kernel.org/intel-xe/20250307132112.18b6c...@canb.auug.org.au/ These will probably show up when Linus merges drm. I checked the fixes on linux-next by Stephen and they look good to me. thanks Lucas De Marchi Please hold on applying this. There's one fix that I merged just after submitting the pull yesterday and today we got reports of kernel docs failing. I'm fixing it and will submit another pull request later today. Sorry for the noise. Lucas De Marchi
[RFC PATCH 09/11] drm/i915/psr: Apply underrun on PSR idle workaround
This patch is applying workaround for underrun on idle PSR HW issue (Wa_16025596647) when PSR is getting enabled. It uses vblank enable/disable status, DC5/6 enabled disabled and enabled pipes count information made available. This patch is also adding calls to dc5/dc6, vblank enable/disable and pipe enable/disable notification functions as needed. intel_psr_needs_block_dc_vblank is modified to get vblank enable/disable notification on PSR capable system. Bspec: 74151 Signed-off-by: Jouni Högander --- drivers/gpu/drm/i915/display/intel_display.c | 4 + .../drm/i915/display/intel_display_driver.c | 3 + .../gpu/drm/i915/display/intel_display_irq.c | 9 +- .../i915/display/intel_display_power_well.c | 4 + drivers/gpu/drm/i915/display/intel_psr.c | 101 +++--- 5 files changed, 74 insertions(+), 47 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c index f7cb38145e9d..109907d93cf8 100644 --- a/drivers/gpu/drm/i915/display/intel_display.c +++ b/drivers/gpu/drm/i915/display/intel_display.c @@ -6656,6 +6656,8 @@ static void intel_enable_crtc(struct intel_atomic_state *state, intel_crtc_update_active_timings(pipe_crtc_state, false); } + intel_psr_notify_pipe_change(state, crtc, true); + display->funcs.display->crtc_enable(state, crtc); /* vblanks work again, re-enable pipe CRC. */ @@ -6775,6 +6777,8 @@ static void intel_old_crtc_state_disables(struct intel_atomic_state *state, intel_crtc_joined_pipe_mask(old_crtc_state)) intel_crtc_disable_pipe_crc(pipe_crtc); + intel_psr_notify_pipe_change(state, crtc, false); + display->funcs.display->crtc_disable(state, crtc); for_each_intel_crtc_in_pipe_mask(display->drm, pipe_crtc, diff --git a/drivers/gpu/drm/i915/display/intel_display_driver.c b/drivers/gpu/drm/i915/display/intel_display_driver.c index 31740a677dd8..b4c989bbac93 100644 --- a/drivers/gpu/drm/i915/display/intel_display_driver.c +++ b/drivers/gpu/drm/i915/display/intel_display_driver.c @@ -54,6 +54,7 @@ #include "intel_plane_initial.h" #include "intel_pmdemand.h" #include "intel_pps.h" +#include "intel_psr.h" #include "intel_quirks.h" #include "intel_vga.h" #include "intel_wm.h" @@ -226,6 +227,8 @@ int intel_display_driver_probe_noirq(struct intel_display *display) if (ret) goto cleanup_bios; + intel_psr_dc5_dc6_wa_init(display); + /* FIXME: completely on the wrong abstraction layer */ ret = intel_power_domains_init(display); if (ret < 0) diff --git a/drivers/gpu/drm/i915/display/intel_display_irq.c b/drivers/gpu/drm/i915/display/intel_display_irq.c index aa23bb817805..62fbdcbb4a12 100644 --- a/drivers/gpu/drm/i915/display/intel_display_irq.c +++ b/drivers/gpu/drm/i915/display/intel_display_irq.c @@ -1728,14 +1728,7 @@ static void intel_display_vblank_dc_work(struct work_struct *work) container_of(work, typeof(*display), irq.vblank_dc_work); int vblank_wa_num_pipes = READ_ONCE(display->irq.vblank_wa_num_pipes); - /* -* NOTE: intel_display_power_set_target_dc_state is used only by PSR -* code for DC3CO handling. DC3CO target state is currently disabled in -* PSR code. If DC3CO is taken into use we need take that into account -* here as well. -*/ - intel_display_power_set_target_dc_state(display, vblank_wa_num_pipes ? DC_STATE_DISABLE : - DC_STATE_EN_UPTO_DC6); + intel_psr_notify_vblank_enable_disable(display, vblank_wa_num_pipes); } int bdw_enable_vblank(struct drm_crtc *_crtc) diff --git a/drivers/gpu/drm/i915/display/intel_display_power_well.c b/drivers/gpu/drm/i915/display/intel_display_power_well.c index 8ec87ffd87d2..510f97341893 100644 --- a/drivers/gpu/drm/i915/display/intel_display_power_well.c +++ b/drivers/gpu/drm/i915/display/intel_display_power_well.c @@ -24,6 +24,7 @@ #include "intel_hotplug.h" #include "intel_pcode.h" #include "intel_pps.h" +#include "intel_psr.h" #include "intel_tc.h" #include "intel_vga.h" #include "skl_watermark.h" @@ -762,6 +763,9 @@ void gen9_set_dc_state(struct intel_display *display, u32 state) state & ~power_domains->allowed_dc_mask)) state &= power_domains->allowed_dc_mask; + if (!power_domains->initializing) + intel_psr_notify_dc5_dc6(display); + val = intel_de_read(display, DC_STATE_EN); mask = gen9_dc_mask(display); drm_dbg_kms(display->drm, "Setting DC state from %02x to %02x\n", diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c index afb9faed7784..2782b84b0d12 100644 --- a/drivers/gpu/drm/i915/display/intel_psr.c +++ b/drivers/gpu/drm/i915/display/intel_psr.c @@ -908,6 +908,41 @@ static u
[PATCH] drm/i915/psr: Check transcoder Selective Update support for PR as well
We need to ensure transcoder is supporting Selective Update in case of
Panel Replay as well.
Signed-off-by: Jouni Högander
---
drivers/gpu/drm/i915/display/intel_psr.c | 14 +++---
1 file changed, 7 insertions(+), 7 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_psr.c
b/drivers/gpu/drm/i915/display/intel_psr.c
index 74aa7ba34fda..84e4d6f1f3a8 100644
--- a/drivers/gpu/drm/i915/display/intel_psr.c
+++ b/drivers/gpu/drm/i915/display/intel_psr.c
@@ -1491,13 +1491,6 @@ static bool intel_psr2_config_valid(struct intel_dp
*intel_dp,
return false;
}
- if (!transcoder_has_psr2(display, crtc_state->cpu_transcoder)) {
- drm_dbg_kms(display->drm,
- "PSR2 not supported in transcoder %s\n",
- transcoder_name(crtc_state->cpu_transcoder));
- return false;
- }
-
/*
* DSC and PSR2 cannot be enabled simultaneously. If a requested
* resolution requires DSC to be enabled, priority is given to DSC
@@ -1579,6 +1572,13 @@ static bool intel_sel_update_config_valid(struct
intel_dp *intel_dp,
goto unsupported;
}
+ if (!transcoder_has_psr2(display, crtc_state->cpu_transcoder)) {
+ drm_dbg_kms(display->drm,
+ "Selective update not supported in transcoder %s\n",
+ transcoder_name(crtc_state->cpu_transcoder));
+ goto unsupported;
+ }
+
if (!crtc_state->has_panel_replay && !intel_psr2_config_valid(intel_dp,
crtc_state))
goto unsupported;
--
2.43.0
✗ i915.CI.BAT: failure for Underrun on idle PSR workaround
== Series Details ==
Series: Underrun on idle PSR workaround
URL : https://patchwork.freedesktop.org/series/145986/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_16243 -> Patchwork_145986v1
Summary
---
**FAILURE**
Serious unknown changes coming with Patchwork_145986v1 absolutely need to be
verified manually.
If you think the reported changes have nothing to do with the changes
introduced in Patchwork_145986v1, please notify your bug team
(i915-ci-in...@lists.freedesktop.org) to allow them
to document this new failure mode, which will reduce false positives in CI.
External URL:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_145986v1/index.html
Participating hosts (44 -> 43)
--
Missing(1): fi-snb-2520m
Possible new issues
---
Here are the unknown changes that may have been introduced in
Patchwork_145986v1:
### IGT changes ###
Possible regressions
* igt@kms_psr@psr-primary-page-flip@edp-1:
- bat-jsl-3: [PASS][1] -> [ABORT][2] +1 other test abort
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16243/bat-jsl-3/igt@kms_psr@psr-primary-page-f...@edp-1.html
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_145986v1/bat-jsl-3/igt@kms_psr@psr-primary-page-f...@edp-1.html
Suppressed
The following results come from untrusted machines, tests, or statuses.
They do not affect the overall result.
* igt@kms_psr@psr-primary-page-flip@edp-1:
- {bat-jsl-4}:[PASS][3] -> [ABORT][4] +1 other test abort
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16243/bat-jsl-4/igt@kms_psr@psr-primary-page-f...@edp-1.html
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_145986v1/bat-jsl-4/igt@kms_psr@psr-primary-page-f...@edp-1.html
Known issues
Here are the changes found in Patchwork_145986v1 that come from known issues:
### IGT changes ###
Issues hit
* igt@dmabuf@all-tests:
- bat-apl-1: [PASS][5] -> [INCOMPLETE][6] ([i915#12904]) +1 other
test incomplete
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16243/bat-apl-1/igt@dma...@all-tests.html
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_145986v1/bat-apl-1/igt@dma...@all-tests.html
* igt@fbdev@info:
- fi-kbl-8809g: NOTRUN -> [SKIP][7] ([i915#1849])
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_145986v1/fi-kbl-8809g/igt@fb...@info.html
* igt@gem_huc_copy@huc-copy:
- fi-kbl-8809g: NOTRUN -> [SKIP][8] ([i915#2190])
[8]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_145986v1/fi-kbl-8809g/igt@gem_huc_c...@huc-copy.html
* igt@gem_lmem_swapping@parallel-random-engines:
- fi-kbl-8809g: NOTRUN -> [SKIP][9] ([i915#4613]) +3 other tests skip
[9]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_145986v1/fi-kbl-8809g/igt@gem_lmem_swapp...@parallel-random-engines.html
* igt@i915_pm_rpm@module-reload:
- bat-rpls-4: [PASS][10] -> [FAIL][11] ([i915#13633])
[10]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16243/bat-rpls-4/igt@i915_pm_...@module-reload.html
[11]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_145986v1/bat-rpls-4/igt@i915_pm_...@module-reload.html
* igt@i915_selftest@live:
- bat-mtlp-8: [PASS][12] -> [DMESG-FAIL][13] ([i915#12061]) +1
other test dmesg-fail
[12]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16243/bat-mtlp-8/igt@i915_selft...@live.html
[13]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_145986v1/bat-mtlp-8/igt@i915_selft...@live.html
- bat-arlh-2: [PASS][14] -> [DMESG-FAIL][15] ([i915#12061] /
[i915#12435])
[14]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16243/bat-arlh-2/igt@i915_selft...@live.html
[15]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_145986v1/bat-arlh-2/igt@i915_selft...@live.html
* igt@i915_selftest@live@workarounds:
- bat-arlh-2: [PASS][16] -> [DMESG-FAIL][17] ([i915#12061])
[16]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16243/bat-arlh-2/igt@i915_selftest@l...@workarounds.html
[17]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_145986v1/bat-arlh-2/igt@i915_selftest@l...@workarounds.html
* igt@kms_dsc@dsc-basic:
- fi-kbl-8809g: NOTRUN -> [SKIP][18] +34 other tests skip
[18]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_145986v1/fi-kbl-8809g/igt@kms_...@dsc-basic.html
* igt@kms_pipe_crc_basic@nonblocking-crc-frame-sequence:
- bat-dg2-11: [PASS][19] -> [SKIP][20] ([i915#9197]) +2 other tests
skip
[19]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16243/bat-dg2-11/igt@kms_pipe_crc_ba...@nonblocking-crc-frame-sequence.html
[20]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_145986v1/bat-dg2-11/igt@kms_pipe_crc_ba...@nonblocking-crc-frame-sequence.html
Possible fixes
*
RE: [PATCH 05/11] drm/i915/dpll: Move away from using shared dpll
> -Original Message-
> From: Ville Syrjälä
> Sent: Monday, 3 March 2025 14.52
> To: Kandpal, Suraj
> Cc: Jani Nikula ; intel...@lists.freedesktop.org;
> intel-gfx@lists.freedesktop.org; Syrjala, Ville ;
> Nautiyal,
> Ankit K ; Shankar, Uma ;
> Kahola, Mika
> Subject: Re: [PATCH 05/11] drm/i915/dpll: Move away from using shared dpll
>
> On Fri, Feb 28, 2025 at 03:31:39PM +, Kandpal, Suraj wrote:
> >
> >
> > > -Original Message-
> > > From: Ville Syrjälä
> > > Sent: Friday, February 28, 2025 7:57 PM
> > > To: Kandpal, Suraj
> > > Cc: Jani Nikula ;
> > > intel...@lists.freedesktop.org; intel-gfx@lists.freedesktop.org;
> > > Syrjala, Ville ; Nautiyal, Ankit K
> > > ; Shankar, Uma ;
> > > Kahola, Mika
> > > Subject: Re: [PATCH 05/11] drm/i915/dpll: Move away from using
> > > shared dpll
> > >
> > > On Thu, Feb 27, 2025 at 10:18:31AM +, Kandpal, Suraj wrote:
> > > >
> > > >
> > > > > -Original Message-
> > > > > From: Jani Nikula
> > > > > Sent: Tuesday, February 25, 2025 9:00 PM
> > > > > To: Kandpal, Suraj ;
> > > > > intel...@lists.freedesktop.org; intel-gfx@lists.freedesktop.org;
> > > > > Syrjala, Ville
> > > > > Cc: Nautiyal, Ankit K ; Shankar, Uma
> > > > > ; Kahola, Mika
> > > > > Subject: RE: [PATCH 05/11] drm/i915/dpll: Move away from using
> > > > > shared dpll
> > > > >
> > > > > On Tue, 25 Feb 2025, "Kandpal, Suraj" wrote:
> > > > > >> -Original Message-
> > > > > >> From: Kandpal, Suraj
> > > > > >> Sent: Tuesday, February 25, 2025 2:25 PM
> > > > > >> To: Jani Nikula ;
> > > > > >> intel...@lists.freedesktop.org;
> > > > > >> intel-gfx@lists.freedesktop.org
> > > > > >> Cc: Nautiyal, Ankit K ; Shankar,
> > > > > >> Uma ; Kahola, Mika
> > > > > >>
> > > > > >> Subject: RE: [PATCH 05/11] drm/i915/dpll: Move away from
> > > > > >> using shared dpll
> > > > > >>
> > > > > >>
> > > > > >>
> > > > > >> > -Original Message-
> > > > > >> > From: Jani Nikula
> > > > > >> > Sent: Tuesday, February 25, 2025 2:17 PM
> > > > > >> > To: Kandpal, Suraj ;
> > > > > >> > intel...@lists.freedesktop.org;
> > > > > >> > intel-gfx@lists.freedesktop.org
> > > > > >> > Cc: Nautiyal, Ankit K ;
> > > > > >> > Shankar, Uma ; Kahola, Mika
> > > > > >> > ; Kandpal, Suraj
> > > > > >> >
> > > > > >> > Subject: Re: [PATCH 05/11] drm/i915/dpll: Move away from
> > > > > >> > using shared dpll
> > > > > >> >
> > > > > >> > On Tue, 25 Feb 2025, Suraj Kandpal
> wrote:
> > > > > >> > > Rename functions to move away from using shared dpll in
> > > > > >> > > the dpll framework as much as possible since dpll may not
> > > > > >> > > always be
> > > shared.
> > > > > >> > >
> > > > > >> > > Signed-off-by: Suraj Kandpal
> > > > > >> >
> > > > > >> > ...
> > > > > >> >
> > > > > >> > > diff --git
> > > > > >> > > a/drivers/gpu/drm/i915/display/intel_dpll_mgr.h
> > > > > >> > > b/drivers/gpu/drm/i915/display/intel_dpll_mgr.h
> > > > > >> > > index 6edd103eda55..ef66aca5da1d 100644
> > > > > >> > > --- a/drivers/gpu/drm/i915/display/intel_dpll_mgr.h
> > > > > >> > > +++ b/drivers/gpu/drm/i915/display/intel_dpll_mgr.h
> > > > > >> > > @@ -387,24 +387,24 @@ struct intel_global_dpll { #define
> > > > > >> > > SKL_DPLL2
> > > > > >> > > 2 #define SKL_DPLL3 3
> > > > > >> > >
> > > > > >> > > -/* shared dpll functions */
> > > > > >> > > +/* global dpll functions */
> > > > > >> > > struct intel_global_dpll *
> > > > > >> > > -intel_get_shared_dpll_by_id(struct intel_display
> > > > > >> > > *display,
> > > > > >> > > +intel_get_global_dpll_by_id(struct intel_display
> > > > > >> > > +*display,
> > > > > >> > >enum intel_dpll_id id); -void
> > > > > >> > > assert_shared_dpll(struct intel_display *display,
> > > > > >> > > +void assert_global_dpll(struct intel_display *display,
> > > > > >> > >struct intel_global_dpll *pll,
> > > > > >> > >bool state);
> > > > > >> > > -#define assert_shared_dpll_enabled(d, p)
> > > > > >> > > assert_shared_dpll(d, p,
> > > > > >> > > true) -#define assert_shared_dpll_disabled(d, p)
> > > > > >> > > assert_shared_dpll(d, p, false) -int
> > > > > >> > > intel_compute_shared_dplls(struct intel_atomic_state
> > > > > >> > > *state,
> > > > > >> > > +#define assert_global_dpll_enabled(d, p)
> > > > > >> > > +assert_global_dpll(d, p,
> > > > > >> > > +true) #define assert_global_dpll_disabled(d, p)
> > > > > >> > > +assert_global_dpll(d, p, false) int
> > > > > >> > > +intel_compute_global_dplls(struct intel_atomic_state
> > > > > >> > > +*state,
> > > > > >> > > struct intel_crtc *crtc,
> > > > > >> > > struct intel_encoder *encoder);
> > > > > >> > > -int
> > > > > >> > > intel_reserve_shared_dplls(struct intel_atomic_state
> > > > > >> > > *state,
> > > > > >> > > +int intel_reserve_global_dplls(struct intel_atomic_state
> > > > > >> > > +*state,
> > > > > >> > > struct intel_crtc *cr
Re: [PATCH 15/21] drm/i915/display: Use fixed_rr timings in modeset sequence
On 3/6/2025 10:16 PM, Ville Syrjälä wrote:
On Thu, Mar 06, 2025 at 06:40:54PM +0530, Ankit Nautiyal wrote:
During modeset enable sequence, program the fixed timings, and turn on the
VRR Timing Generator (VRR TG) for platforms that always use VRR TG.
For this intel_vrr_set_transcoder now always programs fixed timings.
Later if vrr timings are required, vrr_enable() will switch
to the real VRR timings.
For platforms that will always use VRR TG, the VRR_CTL Enable bit is set
and reset in the transcoder enable/disable path.
v2: Update intel_vrr_set_transcoder_timings for fixed_rr.
v3: Update intel_set_transcoder_timings_lrr for fixed_rr. (Ville)
v4: Have separate functions to enable/disable VRR CTL
v5:
-For platforms that do not always have VRRTG on, do write bits other
than enable bit and also use write the TRANS_VRR_PUSH register. (Ville)
-Avoid writing trans_ctl_vrr if !vrr_possible().
v6:
-Disable VRR just before intel_ddi_disable_transcoder_func(). (Ville)
-Correct the sequence of configuring PUSH and VRR Enable/Disable. (Ville)
Signed-off-by: Ankit Nautiyal
---
drivers/gpu/drm/i915/display/intel_ddi.c| 5 ++
drivers/gpu/drm/i915/display/intel_dp_mst.c | 4 ++
drivers/gpu/drm/i915/display/intel_vrr.c| 63 -
drivers/gpu/drm/i915/display/intel_vrr.h| 2 +
4 files changed, 60 insertions(+), 14 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c
b/drivers/gpu/drm/i915/display/intel_ddi.c
index 676c1826f15c..6d89a87b3419 100644
--- a/drivers/gpu/drm/i915/display/intel_ddi.c
+++ b/drivers/gpu/drm/i915/display/intel_ddi.c
@@ -78,6 +78,7 @@
#include "intel_tc.h"
#include "intel_vdsc.h"
#include "intel_vdsc_regs.h"
+#include "intel_vrr.h"
#include "skl_scaler.h"
#include "skl_universal_plane.h"
@@ -3248,6 +3249,8 @@ static void intel_ddi_post_disable_hdmi_or_sst(struct intel_atomic_state *state,
drm_dp_dpcd_poll_act_handled(&intel_dp->aux, 0);
}
+ intel_vrr_transcoder_disable(old_crtc_state);
+
intel_ddi_disable_transcoder_func(old_crtc_state);
for_each_pipe_crtc_modeset_disable(display, pipe_crtc, old_crtc_state, i) {
@@ -3521,6 +3524,8 @@ static void intel_ddi_enable(struct intel_atomic_state
*state,
intel_ddi_enable_transcoder_func(encoder, crtc_state);
+ intel_vrr_transcoder_enable(crtc_state);
+
/* Enable/Disable DP2.0 SDP split config before transcoder */
intel_audio_sdp_split_update(crtc_state);
diff --git a/drivers/gpu/drm/i915/display/intel_dp_mst.c b/drivers/gpu/drm/i915/display/intel_dp_mst.c
index bd47cf127b4c..d2988b9a6e7b 100644
--- a/drivers/gpu/drm/i915/display/intel_dp_mst.c
+++ b/drivers/gpu/drm/i915/display/intel_dp_mst.c
@@ -1065,6 +1065,8 @@ static void mst_stream_post_disable(struct
intel_atomic_state *state,
drm_dp_remove_payload_part2(&intel_dp->mst.mgr, new_mst_state,
old_payload, new_payload);
+ intel_vrr_transcoder_disable(old_crtc_state);
+
intel_ddi_disable_transcoder_func(old_crtc_state);
for_each_pipe_crtc_modeset_disable(display, pipe_crtc, old_crtc_state, i) {
@@ -1326,6 +1328,8 @@ static void mst_stream_enable(struct intel_atomic_state
*state,
intel_ddi_enable_transcoder_func(encoder, pipe_config);
+ intel_vrr_transcoder_enable(pipe_config);
+
intel_ddi_clear_act_sent(encoder, pipe_config);
intel_de_rmw(display, TRANS_DDI_FUNC_CTL(display, trans), 0,
diff --git a/drivers/gpu/drm/i915/display/intel_vrr.c
b/drivers/gpu/drm/i915/display/intel_vrr.c
index f523a48e6186..d7580b6e4e37 100644
--- a/drivers/gpu/drm/i915/display/intel_vrr.c
+++ b/drivers/gpu/drm/i915/display/intel_vrr.c
@@ -460,12 +460,6 @@ void intel_vrr_set_transcoder_timings(const struct
intel_crtc_state *crtc_state)
intel_de_rmw(display, CHICKEN_TRANS(display, cpu_transcoder),
0, PIPE_VBLANK_WITH_DELAY);
- if (!intel_vrr_possible(crtc_state)) {
- intel_de_write(display,
- TRANS_VRR_CTL(display, cpu_transcoder), 0);
- return;
- }
-
if (crtc_state->cmrr.enable) {
intel_de_write(display, TRANS_CMRR_M_HI(display,
cpu_transcoder),
upper_32_bits(crtc_state->cmrr.cmrr_m));
@@ -477,14 +471,7 @@ void intel_vrr_set_transcoder_timings(const struct
intel_crtc_state *crtc_state)
lower_32_bits(crtc_state->cmrr.cmrr_n));
}
- intel_de_write(display, TRANS_VRR_VMIN(display, cpu_transcoder),
- crtc_state->vrr.vmin - 1);
- intel_de_write(display, TRANS_VRR_VMAX(display, cpu_transcoder),
- crtc_state->vrr.vmax - 1);
- intel_de_write(display, TRANS_VRR_CTL(display, cpu_transcoder),
- trans_vrr_ctl(crtc_state));
- intel_de_write(display, TRANS_VRR_FLIPLINE(display, cpu_transcoder),
- crtc_s
[PATCH v2] i915/gt/selftest_lrc: Disable timestamp test
This test was supposed to show bug in tigerlake and dg2 hardware. The bug was found and fixed in newer generations. Since we won't support any new hardware with this driver, the test should now be turned off in the CI to not polute it with random failures on previous hardware. Signed-off-by: Mikolaj Wasiak --- Sorry for the duplicate, I've sent it to wrong mailing list. Fixes: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/13697 v1 -> v2: Disabled the test instead of removing it, Change name from 'remove' to 'disable' drivers/gpu/drm/i915/gt/selftest_lrc.c | 11 +++ 1 file changed, 11 insertions(+) diff --git a/drivers/gpu/drm/i915/gt/selftest_lrc.c b/drivers/gpu/drm/i915/gt/selftest_lrc.c index 22e750108c5f..419a7cd61b65 100644 --- a/drivers/gpu/drm/i915/gt/selftest_lrc.c +++ b/drivers/gpu/drm/i915/gt/selftest_lrc.c @@ -3,6 +3,7 @@ * Copyright © 2018 Intel Corporation */ +#include "linux/kconfig.h" #include #include "gem/i915_gem_internal.h" @@ -858,6 +859,16 @@ static int live_lrc_timestamp(void *arg) U32_MAX, }; + /* +* This test was created to show existence of hardware bug. +* The bug was found and fixed in further generations but +* now this test polutes our CI on previous generations. +* +* https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/13697 +*/ + if (!IS_ENABLED(CONFIG_DRM_I915_SELFTEST_BROKEN)) + return 0; + /* * We want to verify that the timestamp is saved and restore across * context switches and is monotonic. -- 2.48.1
Re: [PATCH v5 4/8] drm/i915/lobf: Update lobf if any change in dependent parameters
On Mon, 2025-03-03 at 14:05 +0530, Animesh Manna wrote:
> For every commit the dependent condition for LOBF is checked
> and accordingly update has_lobf flag which will be used
> to update the ALPM_CTL register during commit.
>
> v1: Initial version.
> v2: Avoid reading h/w register without has_lobf check. [Jani]
>
> Signed-off-by: Animesh Manna
> ---
> drivers/gpu/drm/i915/display/intel_alpm.c | 18 ++
> drivers/gpu/drm/i915/display/intel_alpm.h | 1 +
> drivers/gpu/drm/i915/display/intel_ddi.c | 1 +
> 3 files changed, 20 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_alpm.c
> b/drivers/gpu/drm/i915/display/intel_alpm.c
> index c2862888466f..f4586c76a7b7 100644
> --- a/drivers/gpu/drm/i915/display/intel_alpm.c
> +++ b/drivers/gpu/drm/i915/display/intel_alpm.c
> @@ -312,6 +312,24 @@ void intel_alpm_lobf_compute_config(struct
> intel_dp *intel_dp,
> (first_sdp_position + waketime_in_lines);
> }
>
> +void intel_alpm_lobf_update(const struct intel_crtc_state
> *crtc_state)
> +{
> + struct intel_display *display =
> to_intel_display(crtc_state);
> + enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
> + u32 alpm_ctl;
> +
> + if (DISPLAY_VER(display) < 20)
> + return;
> +
> + if (!crtc_state->has_lobf) {
> + alpm_ctl = intel_de_read(display, ALPM_CTL(display,
> cpu_transcoder));
> + if (alpm_ctl & ALPM_CTL_LOBF_ENABLE) {
> + alpm_ctl &= ~ALPM_CTL_LOBF_ENABLE;
> + intel_de_write(display, ALPM_CTL(display,
> cpu_transcoder), alpm_ctl);
> + }
Why can't you do this in alpm_post_plane_update? Disable it there if
old_crtc_state->has_lobf && !new_crtc_state->has_lobf?
BR,
Jouni Högander
> + }
> +}
> +
> static void lnl_alpm_configure(struct intel_dp *intel_dp,
> const struct intel_crtc_state
> *crtc_state)
> {
> diff --git a/drivers/gpu/drm/i915/display/intel_alpm.h
> b/drivers/gpu/drm/i915/display/intel_alpm.h
> index 91f51fb24f98..c6efd25c2062 100644
> --- a/drivers/gpu/drm/i915/display/intel_alpm.h
> +++ b/drivers/gpu/drm/i915/display/intel_alpm.h
> @@ -23,6 +23,7 @@ void intel_alpm_lobf_compute_config(struct intel_dp
> *intel_dp,
> struct drm_connector_state
> *conn_state);
> void intel_alpm_configure(struct intel_dp *intel_dp,
> const struct intel_crtc_state
> *crtc_state);
> +void intel_alpm_lobf_update(const struct intel_crtc_state
> *crtc_state);
> void intel_alpm_post_plane_update(struct intel_atomic_state *state,
> struct intel_crtc *crtc);
> void intel_alpm_lobf_debugfs_add(struct intel_connector *connector);
> diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c
> b/drivers/gpu/drm/i915/display/intel_ddi.c
> index 9b504dcfb446..b6186e1cf804 100644
> --- a/drivers/gpu/drm/i915/display/intel_ddi.c
> +++ b/drivers/gpu/drm/i915/display/intel_ddi.c
> @@ -3620,6 +3620,7 @@ static void intel_ddi_update_pipe_dp(struct
> intel_atomic_state *state,
> intel_ddi_set_dp_msa(crtc_state, conn_state);
>
> intel_dp_set_infoframes(encoder, true, crtc_state,
> conn_state);
> + intel_alpm_lobf_update(crtc_state);
>
> intel_backlight_update(state, encoder, crtc_state,
> conn_state);
> drm_connector_update_privacy_screen(conn_state);
Re: [PATCH RFC v3 0/7] drm/display: dp: add new DPCD access functions
On Fri, Mar 07, 2025 at 06:34:42AM +0200, Dmitry Baryshkov wrote: > Existing DPCD access functions return an error code or the number of > bytes being read / write in case of partial access. However a lot of > drivers either (incorrectly) ignore partial access or mishandle error > codes. In other cases this results in a boilerplate code which compares > returned value with the size. > > As suggested by Jani implement new set of DPCD access helpers, which > ignore partial access, always return 0 or an error code. Implement > new helpers using existing functions to ensure backwards compatibility > and to assess necessity to handle incomplete reads on a global scale. > Currently only one possible place has been identified, dp-aux-dev, which > needs to handle possible holes in DPCD. > > This series targets only the DRM helpers code. If the approach is found > to be acceptable, each of the drivers should be converted on its own. > > Signed-off-by: Dmitry Baryshkov Just wanted to drop my "I like this" on your series here. Short read/writes come from unix pipes, and they're everywhere, and yes ime everyone gets them wrong. So ack or whatever that means :-) -Sima > --- > Changes in v3: > - Fixed cover letter (Jani) > - Added intel-gfx and intel-xe to get the series CI-tested (Jani) > - Link to v2: > https://lore.kernel.org/r/20250301-drm-rework-dpcd-access-v2-0-4d92602fc...@linaro.org > > Changes in v2: > - Reimplemented new helpers using old ones (Lyude) > - Reworked the drm_dp_dpcd_read_link_status() patch (Lyude) > - Dropped the dp-aux-dev patch (Jani) > - Link to v1: > https://lore.kernel.org/r/20250117-drm-rework-dpcd-access-v1-0-7fc020e04...@linaro.org > > --- > Dmitry Baryshkov (7): > drm/display: dp: implement new access helpers > drm/display: dp: change drm_dp_dpcd_read_link_status() return value > drm/display: dp: use new DCPD access helpers > drm/display: dp-aux-dev: use new DCPD access helpers > drm/display: dp-cec: use new DCPD access helpers > drm/display: dp-mst-topology: use new DCPD access helpers > drm/display: dp-tunnel: use new DCPD access helpers > > drivers/gpu/drm/amd/amdgpu/atombios_dp.c | 8 +- > .../gpu/drm/bridge/cadence/cdns-mhdp8546-core.c| 2 +- > drivers/gpu/drm/display/drm_dp_aux_dev.c | 12 +- > drivers/gpu/drm/display/drm_dp_cec.c | 37 ++- > drivers/gpu/drm/display/drm_dp_helper.c| 307 > + > drivers/gpu/drm/display/drm_dp_mst_topology.c | 105 --- > drivers/gpu/drm/display/drm_dp_tunnel.c| 20 +- > drivers/gpu/drm/hisilicon/hibmc/dp/dp_link.c | 4 +- > drivers/gpu/drm/msm/dp/dp_ctrl.c | 24 +- > drivers/gpu/drm/msm/dp/dp_link.c | 18 +- > drivers/gpu/drm/radeon/atombios_dp.c | 8 +- > include/drm/display/drm_dp_helper.h| 92 +- > 12 files changed, 322 insertions(+), 315 deletions(-) > --- > base-commit: 565351ae7e0cee80e9b5ed84452a5b13644ffc4d > change-id: 20241231-drm-rework-dpcd-access-b0fc2e47d613 > > Best regards, > -- > Dmitry Baryshkov > -- Simona Vetter Software Engineer, Intel Corporation http://blog.ffwll.ch
Re: [PATCH v5 5/8] drm/i915/lobf: Add debug interface for lobf
On Mon, 2025-03-03 at 14:05 +0530, Animesh Manna wrote:
> Add an interface in debugfs which will help in debugging LOBF
> feature.
>
> v1: Initial version.
> v2:
> - Remove FORCE_EN flag. [Jouni]
> - Change prefix from I915 to INTEL. [Jani]
> - Use u8 instead of bool for lobf-debug flag. [Jani]
> v3:
> - Use intel_connector instead of display. [Jani]
> - Remove edp connector check as it was already present
> in caller function. [Jani]
> - Remove loop of searching edp encoder which is directly
> accessible from intel_connector. [Jani]
>
> Signed-off-by: Animesh Manna
> ---
> drivers/gpu/drm/i915/display/intel_alpm.c | 32
> +++
> .../drm/i915/display/intel_display_types.h | 5 +++
> 2 files changed, 37 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_alpm.c
> b/drivers/gpu/drm/i915/display/intel_alpm.c
> index f4586c76a7b7..245364d031c1 100644
> --- a/drivers/gpu/drm/i915/display/intel_alpm.c
> +++ b/drivers/gpu/drm/i915/display/intel_alpm.c
> @@ -276,6 +276,9 @@ void intel_alpm_lobf_compute_config(struct
> intel_dp *intel_dp,
> int waketime_in_lines, first_sdp_position;
> int context_latency, guardband;
>
> + if (intel_dp->alpm_parameters.lobf_debug &
> INTEL_LOBF_DEBUG_DISABLE)
> + return;
> +
> if (!intel_dp_is_edp(intel_dp))
> return;
>
> @@ -451,6 +454,32 @@ static int i915_edp_lobf_info_show(struct
> seq_file *m, void *data)
>
> DEFINE_SHOW_ATTRIBUTE(i915_edp_lobf_info);
>
> +static int
> +i915_edp_lobf_debug_get(void *data, u64 *val)
> +{
> + struct intel_connector *connector = data;
> + struct intel_dp *intel_dp = enc_to_intel_dp(connector-
> >encoder);
> +
> + *val = READ_ONCE(intel_dp->alpm_parameters.lobf_debug);
> +
> + return 0;
> +}
> +
> +static int
> +i915_edp_lobf_debug_set(void *data, u64 val)
> +{
> + struct intel_connector *connector = data;
> + struct intel_dp *intel_dp = enc_to_intel_dp(connector-
> >encoder);
> +
> + intel_dp->alpm_parameters.lobf_debug = val;
I think you should do some sanity check with the value from user space.
> + return 0;
> +}
> +
> +DEFINE_SIMPLE_ATTRIBUTE(i915_edp_lobf_debug_fops,
> + i915_edp_lobf_debug_get,
> i915_edp_lobf_debug_set,
> + "%llu\n");
> +
> void intel_alpm_lobf_debugfs_add(struct intel_connector *connector)
> {
> struct intel_display *display = to_intel_display(connector);
> @@ -460,6 +489,9 @@ void intel_alpm_lobf_debugfs_add(struct
> intel_connector *connector)
> connector->base.connector_type !=
> DRM_MODE_CONNECTOR_eDP)
> return;
>
> + debugfs_create_file("i915_edp_lobf_debug", 0644, root,
> + connector, &i915_edp_lobf_debug_fops);
> +
> debugfs_create_file("i915_edp_lobf_info", 0444, root,
> connector, &i915_edp_lobf_info_fops);
> }
> diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h
> b/drivers/gpu/drm/i915/display/intel_display_types.h
> index b78721c451b8..b6ec9a8fadd9 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_types.h
> +++ b/drivers/gpu/drm/i915/display/intel_display_types.h
> @@ -1808,6 +1808,11 @@ struct intel_dp {
> u8 aux_less_wake_lines;
> u8 silence_period_sym_clocks;
> u8 lfps_half_cycle_num_of_syms;
> +
> +#define INTEL_LOBF_DEBUG_MODE_MASK 0x0f
0x1?
BR,
Jouni Högander
> +#define INTEL_LOBF_DEBUG_DEFAULT 0x00
> +#define INTEL_LOBF_DEBUG_DISABLE 0x01
> + u8 lobf_debug;
> } alpm_parameters;
>
> u8 alpm_dpcd;
✗ Fi.CI.BUILD: failure for Remove aops->writepage
== Series Details == Series: Remove aops->writepage URL : https://patchwork.freedesktop.org/series/145995/ State : failure == Summary == Error: patch https://patchwork.freedesktop.org/api/1.0/series/145995/revisions/1/mbox/ not applied Applying: f2fs: Remove check for ->writepage Applying: f2fs: Remove f2fs_write_data_page() Applying: f2fs: Remove f2fs_write_meta_page() Applying: f2fs: Remove f2fs_write_node_page() Applying: vboxsf: Convert to writepages Applying: migrate: Remove call to ->writepage Applying: writeback: Remove writeback_use_writepage() Applying: shmem: Add shmem_writeout() Applying: i915: Use writeback_iter() Applying: mm: Remove swap_writepage() and shmem_writepage() error: sha1 information is lacking or useless (mm/shmem.c). error: could not build fake ancestor hint: Use 'git am --show-current-patch=diff' to see the failed patch Patch failed at 0010 mm: Remove swap_writepage() and shmem_writepage() When you have resolved this problem, run "git am --continue". If you prefer to skip this patch, run "git am --skip" instead. To restore the original branch and stop patching, run "git am --abort". Build failed, no error log produced
Re: [PATCH v5 1/7] bits: split the definition of the asm and non-asm GENMASK()
On 07/03/2025 at 22:27, David Laight wrote: > On Fri, 7 Mar 2025 18:58:08 +0900 > Vincent Mailhol wrote: > >> On 07/03/2025 at 04:23, David Laight wrote: >>> On Thu, 06 Mar 2025 20:29:52 +0900 >>> Vincent Mailhol via B4 Relay >>> wrote: >>> From: Vincent Mailhol (...) +#define GENMASK(h, l) __GENMASK(h, l) +#define GENMASK_ULL(h, l) __GENMASK_ULL(h, l) >>> >>> What do those actually expand to now? >>> As I've said a few times both UL(0) and ULL(0) are just (0) for __ASSEMBLY__ >>> so the expansions of __GENMASK() and __GENMASK_ULL() contained the >>> same numeric constants. >> >> Indeed, in asm, the UL(0) and ULL(0) expands to the same thing: 0. >> >> But the two macros still expand to something different on 32 bits >> architectures: >> >> * __GENMASK: >> >> (((~(0)) << (l)) & (~(0) >> (32 - 1 - (h >> >> * __GENMASK_ULL: >> >> (((~(0)) << (l)) & (~(0) >> (64 - 1 - (h >> >> On 64 bits architecture these are the same. > > If the assembler is naive and uses the cpu shift instruction for the >> > then a lot of cpu (including all x86 since the 286) mask off the high bits. > So __GENMASK_ULL() may well generate the expected pattern - provided it > is 32bits wide. "If", "may", that's still a lot of conditionals in your sentence :) I do not have enough knowledge to prove or disprove this, but what I am sure of is that this uncertainty tells me that this is not something I want to touch myself. I picked up this stalled fixed width patch series and re-spinned it because I had confidence here. I do not want to extend this series with some asm clean-up which looks uncertain to me. I am not telling you are wrong but just that I will happily delegate this to whoever has more confidence than me! >>> This means they should be generating the same values. >>> I don't know the correct 'sizeof (int_type)' for the shift right of ~0. >>> My suspicion is that a 32bit assembler used 32bit signed integers and a >>> 64bit one 64bit signed integers (but a 32bit asm on a 64bit host might >>> be 64bit). >>> So the asm versions need to avoid the right shift and only do left shifts. >>> >>> Which probably means they need to be enirely separate from the C versions. >>> And then the C ones can have all the ULL() removed. >> >> In this v5, I already have the ULL() removed from the non-uapi C >> version. And we are left with two distinct variants: >> >> - the uapi C & asm >> - the non-uapi C (including fix width) >> >> For the uapi ones, I do not think we can modify it without a risk of >> breaking some random userland. At least, this is not a risk I will take. >> And if we have to keep the __GENMASK() and __GENMASK_ULL(), then I would >> rather just reuse these for the asm variant instead of splitting further >> more and finding ourselves with three variants: >> >> - the uapi C >> - the asm >> - the non-uapi C (including fix width) >> >> If __GENMASK() and __GENMASK_ULL() were not in the uapi, I would have >> agreed with you. >> >> If you believe that the risk of modifying the uapi GENMASK*() is low >> enough, then you can submit a patch. But I will definitely not touch >> these myself. > > I don't think you'll break userspace by stopping the uapi .h working > for asm files (with __ASSEMBLER__ defined). > > But someone else might have a different opinion. How do you know that there isn't someone somewhere who is using the uapi __GENMASK*() in their userland asm code? Wouldn't such code break? You may argue that the uapi is not meant to be used that way, but at the end, we are not supposed to make assumptions on how the uapi code will be used. Once it is exposed, if something break because the uapi was not used in the intended way, it is still the kernel fault, not the userland. Yours sincerely, Vincent Mailhol
[PATCH 02/11] f2fs: Remove f2fs_write_data_page()
Mappings which implement writepages should not implement writepage
as it can only harm writeback patterns.
Signed-off-by: Matthew Wilcox (Oracle)
---
fs/f2fs/data.c | 24
1 file changed, 24 deletions(-)
diff --git a/fs/f2fs/data.c b/fs/f2fs/data.c
index a80d5ef9acbb..cdd63e8ad42e 100644
--- a/fs/f2fs/data.c
+++ b/fs/f2fs/data.c
@@ -2935,29 +2935,6 @@ int f2fs_write_single_data_page(struct folio *folio, int
*submitted,
return err;
}
-static int f2fs_write_data_page(struct page *page,
- struct writeback_control *wbc)
-{
- struct folio *folio = page_folio(page);
-#ifdef CONFIG_F2FS_FS_COMPRESSION
- struct inode *inode = folio->mapping->host;
-
- if (unlikely(f2fs_cp_error(F2FS_I_SB(inode
- goto out;
-
- if (f2fs_compressed_file(inode)) {
- if (f2fs_is_compressed_cluster(inode, folio->index)) {
- folio_redirty_for_writepage(wbc, folio);
- return AOP_WRITEPAGE_ACTIVATE;
- }
- }
-out:
-#endif
-
- return f2fs_write_single_data_page(folio, NULL, NULL, NULL,
- wbc, FS_DATA_IO, 0, true);
-}
-
/*
* This function was copied from write_cache_pages from mm/page-writeback.c.
* The major change is making write step of cold data page separately from
@@ -4111,7 +4088,6 @@ static void f2fs_swap_deactivate(struct file *file)
const struct address_space_operations f2fs_dblock_aops = {
.read_folio = f2fs_read_data_folio,
.readahead = f2fs_readahead,
- .writepage = f2fs_write_data_page,
.writepages = f2fs_write_data_pages,
.write_begin= f2fs_write_begin,
.write_end = f2fs_write_end,
--
2.47.2
Re: [PATCH v5 6/8] drm/i915/lobf: Check for sink error and disable LOBF
On Mon, 2025-03-03 at 14:05 +0530, Animesh Manna wrote:
> Disable LOBF/ALPM for any erroneous condition from sink side.
>
> v1: Initial version.
> v2: Add centralized alpm error handling. [Jouni]
>
> Signed-off-by: Animesh Manna
> ---
> drivers/gpu/drm/i915/display/intel_alpm.c | 25
> +++
> drivers/gpu/drm/i915/display/intel_alpm.h | 1 +
> drivers/gpu/drm/i915/display/intel_dp.c | 3 +++
> drivers/gpu/drm/i915/display/intel_psr.c | 15 ++
> 4 files changed, 31 insertions(+), 13 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_alpm.c
> b/drivers/gpu/drm/i915/display/intel_alpm.c
> index 245364d031c1..c3d13d93c779 100644
> --- a/drivers/gpu/drm/i915/display/intel_alpm.c
> +++ b/drivers/gpu/drm/i915/display/intel_alpm.c
> @@ -512,3 +512,28 @@ void intel_alpm_disable(struct intel_dp
> *intel_dp)
> PORT_ALPM_CTL(cpu_transcoder),
> PORT_ALPM_CTL_ALPM_AUX_LESS_ENABLE, 0);
> }
> +
> +bool intel_alpm_get_error(struct intel_dp *intel_dp)
> +{
> + struct intel_display *display = to_intel_display(intel_dp);
> + struct drm_dp_aux *aux = &intel_dp->aux;
> + u8 val;
> + int r;
> +
> + r = drm_dp_dpcd_readb(aux, DP_RECEIVER_ALPM_STATUS, &val);
> + if (r != 1) {
> + drm_err(display->drm, "Error reading ALPM
> status\n");
> + return true;
> + }
> +
> + if (val & DP_ALPM_LOCK_TIMEOUT_ERROR) {
> + drm_dbg_kms(display->drm,
> + "ALPM lock timeout error, disabling
> ALPM\n");
I think you should remove ", disabling ALPM" from here. You could add
it into intel_alpm_disable. Also having drm_dbg about enabling LOBF in
lnl_alpm_configure would make sense.
> +
> + /* Clearing error */
> + drm_dp_dpcd_writeb(aux, DP_RECEIVER_ALPM_STATUS,
> val);
> + return true;
> + }
> +
> + return false;
> +}
> diff --git a/drivers/gpu/drm/i915/display/intel_alpm.h
> b/drivers/gpu/drm/i915/display/intel_alpm.h
> index c6efd25c2062..22469fd4cba5 100644
> --- a/drivers/gpu/drm/i915/display/intel_alpm.h
> +++ b/drivers/gpu/drm/i915/display/intel_alpm.h
> @@ -30,4 +30,5 @@ void intel_alpm_lobf_debugfs_add(struct
> intel_connector *connector);
> bool intel_alpm_aux_wake_supported(struct intel_dp *intel_dp);
> bool intel_alpm_aux_less_wake_supported(struct intel_dp *intel_dp);
> void intel_alpm_disable(struct intel_dp *intel_dp);
> +bool intel_alpm_get_error(struct intel_dp *intel_dp);
> #endif
> diff --git a/drivers/gpu/drm/i915/display/intel_dp.c
> b/drivers/gpu/drm/i915/display/intel_dp.c
> index 4d0166f17357..3aa3c4ab97d1 100644
> --- a/drivers/gpu/drm/i915/display/intel_dp.c
> +++ b/drivers/gpu/drm/i915/display/intel_dp.c
> @@ -5359,6 +5359,9 @@ intel_dp_short_pulse(struct intel_dp *intel_dp)
>
> intel_psr_short_pulse(intel_dp);
>
> + if (intel_alpm_get_error(intel_dp))
> + intel_alpm_disable(intel_dp);
> +
> if (intel_dp_test_short_pulse(intel_dp))
> reprobe_needed = true;
>
> diff --git a/drivers/gpu/drm/i915/display/intel_psr.c
> b/drivers/gpu/drm/i915/display/intel_psr.c
> index 1d202f2eb356..fde9463d5ec9 100644
> --- a/drivers/gpu/drm/i915/display/intel_psr.c
> +++ b/drivers/gpu/drm/i915/display/intel_psr.c
> @@ -3406,28 +3406,17 @@ static int
> psr_get_status_and_error_status(struct intel_dp *intel_dp,
> static void psr_alpm_check(struct intel_dp *intel_dp)
> {
> struct intel_display *display = to_intel_display(intel_dp);
> - struct drm_dp_aux *aux = &intel_dp->aux;
> struct intel_psr *psr = &intel_dp->psr;
> - u8 val;
> - int r;
>
> if (!psr->sel_update_enabled)
> return;
>
> - r = drm_dp_dpcd_readb(aux, DP_RECEIVER_ALPM_STATUS, &val);
> - if (r != 1) {
> - drm_err(display->drm, "Error reading ALPM
> status\n");
> - return;
> - }
> -
> - if (val & DP_ALPM_LOCK_TIMEOUT_ERROR) {
> + if (intel_alpm_get_error(intel_dp)) {
> intel_psr_disable_locked(intel_dp);
> psr->sink_not_reliable = true;
> + intel_alpm_disable(intel_dp);
> drm_dbg_kms(display->drm,
> "ALPM lock timeout error, disabling
> PSR\n");
You can remove this printout or change it as "ALPM error, disabling
PSR". ALPM lock timeout is already dumped out by intel_alpm_get_error
and intel_psr_disable_locked dumps Disabling PSR.
BR,
Jouni Högander
> -
> - /* Clearing error */
> - drm_dp_dpcd_writeb(aux, DP_RECEIVER_ALPM_STATUS,
> val);
> }
> }
>
Re: [PATCH v5 2/7] bits: introduce fixed-type genmasks
On 06/03/2025 à 22:08, Andy Shevchenko wrote: > On Thu, Mar 06, 2025 at 08:29:53PM +0900, Vincent Mailhol via B4 Relay wrote: >> From: Yury Norov >> >> Add GENMASK_TYPE() which generalizes __GENMASK() to support different >> types, and implement fixed-types versions of GENMASK() based on it. >> The fixed-type version allows more strict checks to the min/max values >> accepted, which is useful for defining registers like implemented by >> i915 and xe drivers with their REG_GENMASK*() macros. >> >> The strict checks rely on shift-count-overflow compiler check to fail >> the build if a number outside of the range allowed is passed. >> Example: >> >> #define FOO_MASK GENMASK_U32(33, 4) >> >> will generate a warning like: >> >> include/linux/bits.h:51:27: error: right shift count >= width of type >> [-Werror=shift-count-overflow] >> 51 | type_max(t) >> (BITS_PER_TYPE(t) - 1 - (h) >> | ^~ > > Code LGTM Does this mean I get your Reviewed-by tag? Or will you wait the v6 to formally give it? > but just to be sure: you prepared your series using histogram > diff algo, right? No, I never used the histogram diff. My git config is extremely boring. Mostly vanilla. I remember that Linus even commented on this: https://lore.kernel.org/all/CAHk-=wiuxm-nz1si8dxwvttj9n3c+1srtc0v+lk7hoe4bdv...@mail.gmail.com/ But he made it clear this was *not* a requirement, so I just left the diff algorithm to the default. Or did I miss any communication that contributors should now use histogram diff? Regardless, I do not mind activating it. I just did a: git config diff.algorithm histogram The v6 will have histogram diffs. Yours sincerely, Vincent Mailhol
[PATCH RFC v3 3/7] drm/display: dp: use new DCPD access helpers
From: Dmitry Baryshkov
Switch drm_dp_helper.c to use new set of DPCD read / write helpers.
Reviewed-by: Lyude Paul
Acked-by: Jani Nikula
Signed-off-by: Dmitry Baryshkov
---
drivers/gpu/drm/display/drm_dp_helper.c | 296 +---
1 file changed, 116 insertions(+), 180 deletions(-)
diff --git a/drivers/gpu/drm/display/drm_dp_helper.c
b/drivers/gpu/drm/display/drm_dp_helper.c
index
410be0be233ad94702af423262a7d98e21afbfeb..e2439c8a7fefe116b04aaa689b557e2387b05540
100644
--- a/drivers/gpu/drm/display/drm_dp_helper.c
+++ b/drivers/gpu/drm/display/drm_dp_helper.c
@@ -327,7 +327,7 @@ static int __read_delay(struct drm_dp_aux *aux, const u8
dpcd[DP_RECEIVER_CAP_SI
if (offset < DP_RECEIVER_CAP_SIZE) {
rd_interval = dpcd[offset];
} else {
- if (drm_dp_dpcd_readb(aux, offset, &rd_interval) != 1) {
+ if (drm_dp_dpcd_read_byte(aux, offset, &rd_interval) < 0) {
drm_dbg_kms(aux->drm_dev, "%s: failed rd interval
read\n",
aux->name);
/* arbitrary default delay */
@@ -358,7 +358,7 @@ int drm_dp_128b132b_read_aux_rd_interval(struct drm_dp_aux
*aux)
int unit;
u8 val;
- if (drm_dp_dpcd_readb(aux, DP_128B132B_TRAINING_AUX_RD_INTERVAL, &val)
!= 1) {
+ if (drm_dp_dpcd_read_byte(aux, DP_128B132B_TRAINING_AUX_RD_INTERVAL,
&val) < 0) {
drm_err(aux->drm_dev, "%s: failed rd interval read\n",
aux->name);
/* default to max */
@@ -807,30 +807,20 @@ int drm_dp_dpcd_read_phy_link_status(struct drm_dp_aux
*aux,
{
int ret;
- if (dp_phy == DP_PHY_DPRX) {
- ret = drm_dp_dpcd_read(aux,
- DP_LANE0_1_STATUS,
- link_status,
- DP_LINK_STATUS_SIZE);
-
- if (ret < 0)
- return ret;
+ if (dp_phy == DP_PHY_DPRX)
+ return drm_dp_dpcd_read_data(aux,
+DP_LANE0_1_STATUS,
+link_status,
+DP_LINK_STATUS_SIZE);
- WARN_ON(ret != DP_LINK_STATUS_SIZE);
-
- return 0;
- }
-
- ret = drm_dp_dpcd_read(aux,
- DP_LANE0_1_STATUS_PHY_REPEATER(dp_phy),
- link_status,
- DP_LINK_STATUS_SIZE - 1);
+ ret = drm_dp_dpcd_read_data(aux,
+ DP_LANE0_1_STATUS_PHY_REPEATER(dp_phy),
+ link_status,
+ DP_LINK_STATUS_SIZE - 1);
if (ret < 0)
return ret;
- WARN_ON(ret != DP_LINK_STATUS_SIZE - 1);
-
/* Convert the LTTPR to the sink PHY link status layout */
memmove(&link_status[DP_SINK_STATUS - DP_LANE0_1_STATUS + 1],
&link_status[DP_SINK_STATUS - DP_LANE0_1_STATUS],
@@ -846,7 +836,7 @@ static int read_payload_update_status(struct drm_dp_aux
*aux)
int ret;
u8 status;
- ret = drm_dp_dpcd_readb(aux, DP_PAYLOAD_TABLE_UPDATE_STATUS, &status);
+ ret = drm_dp_dpcd_read_byte(aux, DP_PAYLOAD_TABLE_UPDATE_STATUS,
&status);
if (ret < 0)
return ret;
@@ -873,21 +863,21 @@ int drm_dp_dpcd_write_payload(struct drm_dp_aux *aux,
int ret;
int retries = 0;
- drm_dp_dpcd_writeb(aux, DP_PAYLOAD_TABLE_UPDATE_STATUS,
- DP_PAYLOAD_TABLE_UPDATED);
+ drm_dp_dpcd_write_byte(aux, DP_PAYLOAD_TABLE_UPDATE_STATUS,
+ DP_PAYLOAD_TABLE_UPDATED);
payload_alloc[0] = vcpid;
payload_alloc[1] = start_time_slot;
payload_alloc[2] = time_slot_count;
- ret = drm_dp_dpcd_write(aux, DP_PAYLOAD_ALLOCATE_SET, payload_alloc, 3);
- if (ret != 3) {
+ ret = drm_dp_dpcd_write_data(aux, DP_PAYLOAD_ALLOCATE_SET,
payload_alloc, 3);
+ if (ret < 0) {
drm_dbg_kms(aux->drm_dev, "failed to write payload allocation
%d\n", ret);
goto fail;
}
retry:
- ret = drm_dp_dpcd_readb(aux, DP_PAYLOAD_TABLE_UPDATE_STATUS, &status);
+ ret = drm_dp_dpcd_read_byte(aux, DP_PAYLOAD_TABLE_UPDATE_STATUS,
&status);
if (ret < 0) {
drm_dbg_kms(aux->drm_dev, "failed to read payload table status
%d\n", ret);
goto fail;
@@ -1043,15 +1033,15 @@ bool drm_dp_send_real_edid_checksum(struct drm_dp_aux
*aux,
{
u8 link_edid_read = 0, auto_test_req = 0, test_resp = 0;
- if (drm_dp_dpcd_read(aux, DP_DEVICE_SERVICE_IRQ_VECTOR,
-&auto_test_req, 1) < 1) {
+ if (drm_dp_dpcd_read_byte(aux, DP_DEVICE_SERVICE_IRQ_VECTOR,
+ &auto_test_re
[PATCH v4 7/8] test_bits: add tests for fixed-type genmasks
From: Lucas De Marchi
Add some additional tests in lib/test_bits.c to cover the
expected/non-expected values of the fixed-type genmasks.
Also check that the result value matches the expected type. Since
those are known at build time, use static_assert() instead of normal
kunit tests.
Signed-off-by: Lucas De Marchi
Signed-off-by: Vincent Mailhol
---
Changelog:
v3 -> v4:
- Adjust the type of GENMASK_U8()/GENMASK_U16() from u8/u16 to
unsigned int.
- Reorder the tests to match the order in which the macros are
declared in bits.h.
---
lib/test_bits.c | 19 +++
1 file changed, 19 insertions(+)
diff --git a/lib/test_bits.c b/lib/test_bits.c
index
dc93ded9fdb201e0d44b3c1cd71e233fd62258a5..c3a40995a2577322252371eb10ada0c33fb5d9b4
100644
--- a/lib/test_bits.c
+++ b/lib/test_bits.c
@@ -5,7 +5,16 @@
#include
#include
+#include
+#define assert_type(t, x) _Generic(x, t: x, default: 0)
+
+static_assert(assert_type(unsigned long, GENMASK(31, 0)) == U32_MAX);
+static_assert(assert_type(unsigned long long, GENMASK_ULL(63, 0)) == U64_MAX);
+static_assert(assert_type(unsigned int, GENMASK_U8(7, 0)) == U8_MAX);
+static_assert(assert_type(unsigned int, GENMASK_U16(15, 0)) == U16_MAX);
+static_assert(assert_type(u32, GENMASK_U32(31, 0)) == U32_MAX);
+static_assert(assert_type(u64, GENMASK_U64(63, 0)) == U64_MAX);
static void __genmask_test(struct kunit *test)
{
@@ -30,11 +39,21 @@ static void genmask_test(struct kunit *test)
KUNIT_EXPECT_EQ(test, 6ul, GENMASK(2, 1));
KUNIT_EXPECT_EQ(test, 0xul, GENMASK(31, 0));
+ KUNIT_EXPECT_EQ(test, 1u, GENMASK_U8(0, 0));
+ KUNIT_EXPECT_EQ(test, 3u, GENMASK_U16(1, 0));
+ KUNIT_EXPECT_EQ(test, 0x1, GENMASK_U32(16, 16));
+
#ifdef TEST_GENMASK_FAILURES
/* these should fail compilation */
GENMASK(0, 1);
GENMASK(0, 10);
GENMASK(9, 10);
+
+ GENMASK_U32(0, 31);
+ GENMASK_U64(64, 0);
+ GENMASK_U32(32, 0);
+ GENMASK_U16(16, 0);
+ GENMASK_U8(8, 0);
#endif
--
2.45.3
Re: [PATCH v4 4/8] bits: introduce fixed-type BIT
On 05/03/2025 at 23:33, Andy Shevchenko wrote: > On Wed, Mar 05, 2025 at 10:00:16PM +0900, Vincent Mailhol via B4 Relay wrote: >> From: Lucas De Marchi >> >> Implement fixed-type BIT to help drivers add stricter checks, like was > > Here and in the Subject I would use BIT_Uxx(). > >> done for GENMASK(). > > ... > >> +/* >> + * Fixed-type variants of BIT(), with additional checks like GENMASK_t(). >> The > > GENMASK_t() is not a well named macro. Ack. I will rename to GENMASK_TYPE(). >> + * following examples generate compiler warnings due to >> shift-count-overflow: >> + * >> + * - BIT_U8(8) >> + * - BIT_U32(-1) >> + * - BIT_U32(40) >> + */ >> +#define BIT_INPUT_CHECK(type, b) \ >> +BUILD_BUG_ON_ZERO(const_true((b) >= BITS_PER_TYPE(type))) >> + >> +#define BIT_U8(b) (BIT_INPUT_CHECK(u8, b) + (unsigned int)BIT(b)) >> +#define BIT_U16(b) (BIT_INPUT_CHECK(u16, b) + (unsigned int)BIT(b)) > > Why not u8 and u16? This inconsistency needs to be well justified. Because of the C integer promotion rules, if casted to u8 or u16, the expression will immediately become a signed integer as soon as it is get used. For example, if casted to u8 BIT_U8(0) + BIT_U8(1) would be a signed integer. And that may surprise people. David also pointed this in the v3: https://lore.kernel.org/intel-xe/d42dc197a15649e69d459362849a3...@acums.aculab.com/ and I agree with his comment. I explained this in the changelog below the --- cutter, but it is probably better to make the explanation more visible. I will add a comment in the code to explain this. >> +#define BIT_U32(b) (BIT_INPUT_CHECK(u32, b) + (u32)BIT(b)) >> +#define BIT_U64(b) (BIT_INPUT_CHECK(u64, b) + (u64)BIT_ULL(b)) > > Can you also use a TAB between the parentheses for better readability? > E.g., > > #define BIT_U64(b)r (BIT_INPUT_CHECK(u64, b) + (u64)BIT_ULL(b)) Sure. I prefer it with space, but no strong opinion. I will put tab in v5. Yours sincerely, Vincent Mailhol
Re: [PATCH v4 1/8] bits: fix typo 'unsigned __init128' -> 'unsigned __int128'
Hi Vincent! On Wed, Mar 05, 2025 at 10:00:13PM +0900, Vincent Mailhol via B4 Relay wrote: > From: Vincent Mailhol > > "int" was misspelled as "init" in GENMASK_U128() comments. Fix the typo. > > Signed-off-by: Vincent Mailhol Thanks for respinning the series. I'll take this fix in bitmap-for-next, so if you need v2, you'll not have to bear this thing too. Thanks, Yury > --- > include/linux/bits.h | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > > diff --git a/include/linux/bits.h b/include/linux/bits.h > index > 61a75d3f294bfa96267383b5e2fd2a5d4593fcee..14fd0ca9a6cd17339dd2f69e449558312a8a001b > 100644 > --- a/include/linux/bits.h > +++ b/include/linux/bits.h > @@ -40,7 +40,7 @@ > * Missing asm support > * > * __GENMASK_U128() depends on _BIT128() which would not work > - * in the asm code, as it shifts an 'unsigned __init128' data > + * in the asm code, as it shifts an 'unsigned __int128' data > * type instead of direct representation of 128 bit constants > * such as long and unsigned long. The fundamental problem is > * that a 128 bit constant will get silently truncated by the > > -- > 2.45.3 >
Re: [PATCH 07/11] drm/i915/dpll: Change argument for enable hook in intel_global_dpll_funcs
On Tue, Feb 25, 2025 at 01:39:23PM +0530, Suraj Kandpal wrote:
> Change the arguments for enable hook in intel_global_dpll_funcs to only
> accept crtc_state. This is because we really don't need those extra
> arguments everything can be derived from crtc_state and we need
> intel_encoder for PLL enablement when DISPLAY_VER() >= 14.
>
> Signed-off-by: Suraj Kandpal
> ---
> drivers/gpu/drm/i915/display/intel_dpll_mgr.c | 100 ++
> 1 file changed, 54 insertions(+), 46 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
> b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
> index bd623fdddfdc..c39f7d73a89f 100644
> --- a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
> +++ b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
> @@ -66,9 +66,8 @@ struct intel_global_dpll_funcs {
>* Hook for enabling the pll, called from intel_enable_global_dpll() if
>* the pll is not already enabled.
>*/
> - void (*enable)(struct intel_display *display,
> -struct intel_global_dpll *pll,
> -const struct intel_dpll_hw_state *dpll_hw_state);
> + void (*enable)(const struct intel_crtc_state *state,
This feels like the wrong direction. We want the plls to be
independent of crtcs. The crtc_state should only be necessary
to compute a plls's state.
--
Ville Syrjälä
Intel
[PATCH v4 1/8] bits: fix typo 'unsigned __init128' -> 'unsigned __int128'
From: Vincent Mailhol "int" was misspelled as "init" in GENMASK_U128() comments. Fix the typo. Signed-off-by: Vincent Mailhol --- include/linux/bits.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/include/linux/bits.h b/include/linux/bits.h index 61a75d3f294bfa96267383b5e2fd2a5d4593fcee..14fd0ca9a6cd17339dd2f69e449558312a8a001b 100644 --- a/include/linux/bits.h +++ b/include/linux/bits.h @@ -40,7 +40,7 @@ * Missing asm support * * __GENMASK_U128() depends on _BIT128() which would not work - * in the asm code, as it shifts an 'unsigned __init128' data + * in the asm code, as it shifts an 'unsigned __int128' data * type instead of direct representation of 128 bit constants * such as long and unsigned long. The fundamental problem is * that a 128 bit constant will get silently truncated by the -- 2.45.3
✓ i915.CI.BAT: success for drm/i915/psr: Check transcoder Selective Update support for PR as well
== Series Details == Series: drm/i915/psr: Check transcoder Selective Update support for PR as well URL : https://patchwork.freedesktop.org/series/145989/ State : success == Summary == CI Bug Log - changes from CI_DRM_16245 -> Patchwork_145989v1 Summary --- **SUCCESS** No regressions found. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_145989v1/index.html Participating hosts (44 -> 43) -- Missing(1): fi-snb-2520m Known issues Here are the changes found in Patchwork_145989v1 that come from known issues: ### IGT changes ### Issues hit * igt@dmabuf@all-tests: - bat-apl-1: [PASS][1] -> [INCOMPLETE][2] ([i915#12904]) +1 other test incomplete [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16245/bat-apl-1/igt@dma...@all-tests.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_145989v1/bat-apl-1/igt@dma...@all-tests.html * igt@fbdev@info: - fi-kbl-8809g: NOTRUN -> [SKIP][3] ([i915#1849]) [3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_145989v1/fi-kbl-8809g/igt@fb...@info.html * igt@gem_huc_copy@huc-copy: - fi-kbl-8809g: NOTRUN -> [SKIP][4] ([i915#2190]) [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_145989v1/fi-kbl-8809g/igt@gem_huc_c...@huc-copy.html * igt@gem_lmem_swapping@parallel-random-engines: - fi-kbl-8809g: NOTRUN -> [SKIP][5] ([i915#4613]) +3 other tests skip [5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_145989v1/fi-kbl-8809g/igt@gem_lmem_swapp...@parallel-random-engines.html * igt@i915_pm_rpm@module-reload: - bat-dg2-11: [PASS][6] -> [FAIL][7] ([i915#13633]) [6]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16245/bat-dg2-11/igt@i915_pm_...@module-reload.html [7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_145989v1/bat-dg2-11/igt@i915_pm_...@module-reload.html - fi-tgl-1115g4: [PASS][8] -> [FAIL][9] ([i915#13633]) [8]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16245/fi-tgl-1115g4/igt@i915_pm_...@module-reload.html [9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_145989v1/fi-tgl-1115g4/igt@i915_pm_...@module-reload.html * igt@i915_selftest@live@workarounds: - bat-mtlp-6: [PASS][10] -> [DMESG-FAIL][11] ([i915#12061]) +1 other test dmesg-fail [10]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16245/bat-mtlp-6/igt@i915_selftest@l...@workarounds.html [11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_145989v1/bat-mtlp-6/igt@i915_selftest@l...@workarounds.html * igt@kms_dsc@dsc-basic: - fi-kbl-8809g: NOTRUN -> [SKIP][12] +34 other tests skip [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_145989v1/fi-kbl-8809g/igt@kms_...@dsc-basic.html * igt@kms_pipe_crc_basic@nonblocking-crc-frame-sequence: - bat-dg2-11: [PASS][13] -> [SKIP][14] ([i915#9197]) +3 other tests skip [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16245/bat-dg2-11/igt@kms_pipe_crc_ba...@nonblocking-crc-frame-sequence.html [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_145989v1/bat-dg2-11/igt@kms_pipe_crc_ba...@nonblocking-crc-frame-sequence.html [i915#12061]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/12061 [i915#12904]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/12904 [i915#13633]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/13633 [i915#1849]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/1849 [i915#2190]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/2190 [i915#4613]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4613 [i915#9197]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9197 Build changes - * Linux: CI_DRM_16245 -> Patchwork_145989v1 CI-20190529: 20190529 CI_DRM_16245: 066c46f28642479869d2d1dd27cc6ae476de4abc @ git://anongit.freedesktop.org/gfx-ci/linux IGT_8264: 8264 Patchwork_145989v1: 066c46f28642479869d2d1dd27cc6ae476de4abc @ git://anongit.freedesktop.org/gfx-ci/linux == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_145989v1/index.html
Re: [PATCH v2] i915/selftest/igt_mmap: let mmap tests run in kthread
On 2025-03-07 at 12:31:25 +0100, Chris Wilson wrote: > Quoting Mikolaj Wasiak (2025-03-07 08:44:29) > > Hi Krzysztof, > > > > On 2025-03-05 at 17:31:49 +0100, Krzysztof Niemiec wrote: > > > Don't we run into the same issue as in V1, meaning we use an unknown > > > current->active_mm (since we run in a kthread, and cannot control it) to > > > use as the current->mm? Maybe a better approach would be to create a new > > > mm for the duration of the test, similarly to how the patch Janusz > > > mentioned does it? (51104c19d857) > > > > As per discussion with Chris, using active_mm is the correct way of > > enabling current->mm in kthread. On the other hand it may also expose > > issues with underlying tests because they didn't previously run on such > > hardware. I think potential fixes to those tests should be addressed in > > separate patch. > > We've looked at the tests, and they should all be finding unused space > in the mm and cleaning up after themselves... > > If we put on our paranoia hats, the biggest problem with borrowing > userspace's mm is that it gives them temporary insight into whatever > we place into that mm. We don't expose any data, unless by error... > Not sure how much effort we want to put on making the selftests paranoia > proof, but that (and the surety of cleaning up afterwards) would be a > good argument for creating a temporary mm for our use. > -Chris I still don't know if it would be feasible to use methods that are exposed only to kunit to run our selftest. Do you think we should go that way? Mikołaj
[RFC PATCH 07/11] drm/i915/psr: Add mechanism to notify PSR of DC5/6 enable disable
We need to apply/remove workaround for underrun on idle PSR HW issue
(Wa_16025596647) when DC5/6 is enabled/disabled. This patch implements
mechanism to notify PSR about DC5/6 enable/disable and applies/removes the
workaround using this notification.
Bspec: 74115
Signed-off-by: Jouni Högander
---
.../gpu/drm/i915/display/intel_display_core.h | 2 +
drivers/gpu/drm/i915/display/intel_psr.c | 50 +++
drivers/gpu/drm/i915/display/intel_psr.h | 2 +
3 files changed, 54 insertions(+)
diff --git a/drivers/gpu/drm/i915/display/intel_display_core.h
b/drivers/gpu/drm/i915/display/intel_display_core.h
index 7360ad39b1cc..b765a2ef9a6c 100644
--- a/drivers/gpu/drm/i915/display/intel_display_core.h
+++ b/drivers/gpu/drm/i915/display/intel_display_core.h
@@ -573,6 +573,8 @@ struct intel_display {
struct intel_vbt_data vbt;
struct intel_dmc_wl wl;
struct intel_wm wm;
+
+ struct work_struct psr_dc5_dc6_wa_work;
};
#endif /* __INTEL_DISPLAY_CORE_H__ */
diff --git a/drivers/gpu/drm/i915/display/intel_psr.c
b/drivers/gpu/drm/i915/display/intel_psr.c
index 4b62d5832cbf..baf6a7110a55 100644
--- a/drivers/gpu/drm/i915/display/intel_psr.c
+++ b/drivers/gpu/drm/i915/display/intel_psr.c
@@ -3718,6 +3718,56 @@ static void
intel_psr_apply_underrun_on_idle_wa_locked(struct intel_dp *intel_dp
psr1_apply_underrun_on_idle_wa_locked(intel_dp,
dc5_dc6_blocked);
}
+static void psr_dc5_dc6_wa_work(struct work_struct *work)
+{
+ struct intel_display *display = container_of(work, typeof(*display),
+psr_dc5_dc6_wa_work);
+ struct intel_encoder *encoder;
+
+ for_each_intel_encoder_with_psr(display->drm, encoder) {
+ struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
+
+ mutex_lock(&intel_dp->psr.lock);
+
+ if (intel_dp->psr.enabled &&
!intel_dp->psr.panel_replay_enabled)
+ intel_psr_apply_underrun_on_idle_wa_locked(intel_dp);
+
+ mutex_unlock(&intel_dp->psr.lock);
+ }
+}
+
+/**
+ * intel_psr_notify_dc5_dc6 - Notify PSR about enable/disable dc5/dc6
+ * @display: intel atomic state
+ *
+ * This is targeted for underrun on idle PSR HW bug (Wa_16025596647) to
schedule
+ * psr_dc5_dc6_wa_work used for applying/removing the workaround.
+ */
+void intel_psr_notify_dc5_dc6(struct intel_display *display)
+{
+ if (DISPLAY_VER(display) != 20 &&
+ !IS_DISPLAY_VERx100_STEP(display, 3000, STEP_A0, STEP_B0))
+ return;
+
+ schedule_work(&display->psr_dc5_dc6_wa_work);
+}
+
+/**
+ * intel_psr_dc5_dc6_wa_init - Init work for underrun on idle PSR HW bug wa
+ * @display: intel atomic state
+ *
+ * This is targeted for underrun on idle PSR HW bug (Wa_16025596647) to init
+ * psr_dc5_dc6_wa_work used for applying the workaround.
+ */
+void intel_psr_dc5_dc6_wa_init(struct intel_display *display)
+{
+ if (DISPLAY_VER(display) != 20 &&
+ !IS_DISPLAY_VERx100_STEP(display, 3000, STEP_A0, STEP_B0))
+ return;
+
+ INIT_WORK(&display->psr_dc5_dc6_wa_work, psr_dc5_dc6_wa_work);
+}
+
/**
* intel_psr_notify_pipe_change - Notify PSR about enable/disable of a pipe
* @state: intel atomic state
diff --git a/drivers/gpu/drm/i915/display/intel_psr.h
b/drivers/gpu/drm/i915/display/intel_psr.h
index 273e70a50915..bfe368239bc2 100644
--- a/drivers/gpu/drm/i915/display/intel_psr.h
+++ b/drivers/gpu/drm/i915/display/intel_psr.h
@@ -62,6 +62,8 @@ void intel_psr_resume(struct intel_dp *intel_dp);
bool intel_psr_needs_block_dc_vblank(const struct intel_crtc_state
*crtc_state);
void intel_psr_notify_pipe_change(struct intel_atomic_state *state,
struct intel_crtc *crtc, bool enable);
+void intel_psr_notify_dc5_dc6(struct intel_display *display);
+void intel_psr_dc5_dc6_wa_init(struct intel_display *display);
bool intel_psr_link_ok(struct intel_dp *intel_dp);
void intel_psr_lock(const struct intel_crtc_state *crtc_state);
--
2.43.0
[RFC PATCH 10/11] drm/i915/display: Rename intel_psr_needs_block_dc_vblank
Scope of intel_psr_needs_block_dc_vblank has changed now. Rename it as
intel_psr_needs_vblank_notification. Also rename
intel_crtc::block_dc_for_vblank as intel_crtc:vblank_psr_notify
Signed-off-by: Jouni Högander
---
drivers/gpu/drm/i915/display/intel_crtc.c | 4 ++--
drivers/gpu/drm/i915/display/intel_display_irq.c | 4 ++--
drivers/gpu/drm/i915/display/intel_display_types.h | 2 +-
drivers/gpu/drm/i915/display/intel_psr.c | 8 +---
drivers/gpu/drm/i915/display/intel_psr.h | 2 +-
5 files changed, 11 insertions(+), 9 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_crtc.c
b/drivers/gpu/drm/i915/display/intel_crtc.c
index 5b2603ef2ff7..bdf30ab96396 100644
--- a/drivers/gpu/drm/i915/display/intel_crtc.c
+++ b/drivers/gpu/drm/i915/display/intel_crtc.c
@@ -124,7 +124,7 @@ void intel_crtc_vblank_on(const struct intel_crtc_state
*crtc_state)
{
struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
- crtc->block_dc_for_vblank = intel_psr_needs_block_dc_vblank(crtc_state);
+ crtc->vblank_psr_notify =
intel_psr_needs_vblank_notification(crtc_state);
assert_vblank_disabled(&crtc->base);
drm_crtc_set_max_vblank_count(&crtc->base,
@@ -154,7 +154,7 @@ void intel_crtc_vblank_off(const struct intel_crtc_state
*crtc_state)
drm_crtc_vblank_off(&crtc->base);
assert_vblank_disabled(&crtc->base);
- crtc->block_dc_for_vblank = false;
+ crtc->vblank_psr_notify = false;
flush_work(&display->irq.vblank_dc_work);
}
diff --git a/drivers/gpu/drm/i915/display/intel_display_irq.c
b/drivers/gpu/drm/i915/display/intel_display_irq.c
index 62fbdcbb4a12..833f8227da80 100644
--- a/drivers/gpu/drm/i915/display/intel_display_irq.c
+++ b/drivers/gpu/drm/i915/display/intel_display_irq.c
@@ -1742,7 +1742,7 @@ int bdw_enable_vblank(struct drm_crtc *_crtc)
if (gen11_dsi_configure_te(crtc, true))
return 0;
- if (crtc->block_dc_for_vblank && display->irq.vblank_wa_num_pipes++ ==
0)
+ if (crtc->vblank_psr_notify && display->irq.vblank_wa_num_pipes++ == 0)
schedule_work(&display->irq.vblank_dc_work);
spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
@@ -1773,7 +1773,7 @@ void bdw_disable_vblank(struct drm_crtc *_crtc)
bdw_disable_pipe_irq(dev_priv, pipe, GEN8_PIPE_VBLANK);
spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
- if (crtc->block_dc_for_vblank && --display->irq.vblank_wa_num_pipes ==
0)
+ if (crtc->vblank_psr_notify && --display->irq.vblank_wa_num_pipes == 0)
schedule_work(&display->irq.vblank_dc_work);
}
diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h
b/drivers/gpu/drm/i915/display/intel_display_types.h
index 3d203a2003f1..4f3fdfacbc1b 100644
--- a/drivers/gpu/drm/i915/display/intel_display_types.h
+++ b/drivers/gpu/drm/i915/display/intel_display_types.h
@@ -1440,7 +1440,7 @@ struct intel_crtc {
struct intel_pipe_crc pipe_crc;
#endif
- bool block_dc_for_vblank;
+ bool vblank_psr_notify;
};
struct intel_plane_error {
diff --git a/drivers/gpu/drm/i915/display/intel_psr.c
b/drivers/gpu/drm/i915/display/intel_psr.c
index 2782b84b0d12..74aa7ba34fda 100644
--- a/drivers/gpu/drm/i915/display/intel_psr.c
+++ b/drivers/gpu/drm/i915/display/intel_psr.c
@@ -2352,15 +2352,17 @@ void intel_psr_resume(struct intel_dp *intel_dp)
}
/**
- * intel_psr_needs_block_dc_vblank - Check if block dc entry is needed
+ * intel_psr_needs_vblank_notification - Check if PSR need vblank
enable/disable
+ * notification.
* @crtc_state: CRTC status
*
* We need to block DC6 entry in case of Panel Replay as enabling VBI doesn't
* prevent it in case of Panel Replay. Panel Replay switches main link off on
* DC entry. This means vblank interrupts are not fired and is a problem if
- * user-space is polling for vblank events.
+ * user-space is polling for vblank events. Also Wa_16025596647 needs
+ * information when vblank is enabled/disabled.
*/
-bool intel_psr_needs_block_dc_vblank(const struct intel_crtc_state *crtc_state)
+bool intel_psr_needs_vblank_notification(const struct intel_crtc_state
*crtc_state)
{
struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
struct intel_display *display = to_intel_display(crtc_state);
diff --git a/drivers/gpu/drm/i915/display/intel_psr.h
b/drivers/gpu/drm/i915/display/intel_psr.h
index a914b7ee3756..c61384bb7382 100644
--- a/drivers/gpu/drm/i915/display/intel_psr.h
+++ b/drivers/gpu/drm/i915/display/intel_psr.h
@@ -59,7 +59,7 @@ void intel_psr2_program_trans_man_trk_ctl(struct intel_dsb
*dsb,
const struct intel_crtc_state
*crtc_state);
void intel_psr_pause(struct intel_dp *intel_dp);
void intel_psr_resume(struct intel_dp *intel_dp);
-bool intel_psr_needs_block_dc_vblank(const struct intel_crtc_state
*crtc_state);
+bool intel_psr_needs_vblank
[PATCH 08/11] shmem: Add shmem_writeout()
This will be the replacement for shmem_writepage().
Signed-off-by: Matthew Wilcox (Oracle)
---
include/linux/shmem_fs.h | 7 ---
mm/shmem.c | 20 ++--
2 files changed, 18 insertions(+), 9 deletions(-)
diff --git a/include/linux/shmem_fs.h b/include/linux/shmem_fs.h
index 0b273a7b9f01..5f03a39a26f7 100644
--- a/include/linux/shmem_fs.h
+++ b/include/linux/shmem_fs.h
@@ -104,10 +104,11 @@ static inline bool shmem_mapping(struct address_space
*mapping)
return false;
}
#endif /* CONFIG_SHMEM */
-extern void shmem_unlock_mapping(struct address_space *mapping);
-extern struct page *shmem_read_mapping_page_gfp(struct address_space *mapping,
+void shmem_unlock_mapping(struct address_space *mapping);
+struct page *shmem_read_mapping_page_gfp(struct address_space *mapping,
pgoff_t index, gfp_t gfp_mask);
-extern void shmem_truncate_range(struct inode *inode, loff_t start, loff_t
end);
+int shmem_writeout(struct folio *folio, struct writeback_control *wbc);
+void shmem_truncate_range(struct inode *inode, loff_t start, loff_t end);
int shmem_unuse(unsigned int type);
#ifdef CONFIG_TRANSPARENT_HUGEPAGE
diff --git a/mm/shmem.c b/mm/shmem.c
index ba162e991285..427b7f70fffb 100644
--- a/mm/shmem.c
+++ b/mm/shmem.c
@@ -1536,12 +1536,20 @@ int shmem_unuse(unsigned int type)
return error;
}
-/*
- * Move the page from the page cache to the swap cache.
- */
static int shmem_writepage(struct page *page, struct writeback_control *wbc)
{
- struct folio *folio = page_folio(page);
+ return shmem_writeout(page_folio(page), wbc);
+}
+
+/**
+ * shmem_writeout - Write the folio to swap
+ * @folio: The folio to write
+ * @wbc: How writeback is to be done
+ *
+ * Move the folio from the page cache to the swap cache.
+ */
+int shmem_writeout(struct folio *folio, struct writeback_control *wbc)
+{
struct address_space *mapping = folio->mapping;
struct inode *inode = mapping->host;
struct shmem_inode_info *info = SHMEM_I(inode);
@@ -1586,9 +1594,8 @@ static int shmem_writepage(struct page *page, struct
writeback_control *wbc)
try_split:
/* Ensure the subpages are still dirty */
folio_test_set_dirty(folio);
- if (split_huge_page_to_list_to_order(page, wbc->list, 0))
+ if (split_folio_to_list(folio, wbc->list))
goto redirty;
- folio = page_folio(page);
folio_clear_dirty(folio);
}
@@ -1660,6 +1667,7 @@ static int shmem_writepage(struct page *page, struct
writeback_control *wbc)
folio_unlock(folio);
return 0;
}
+EXPORT_SYMBOL_GPL(shmem_writeout);
#if defined(CONFIG_NUMA) && defined(CONFIG_TMPFS)
static void shmem_show_mpol(struct seq_file *seq, struct mempolicy *mpol)
--
2.47.2
[PATCH 01/11] f2fs: Remove check for ->writepage
We're almost able to remove a_ops->writepage. This check is unnecessary as we'll never call into __f2fs_write_data_pages() for character devices. Signed-off-by: Matthew Wilcox (Oracle) --- fs/f2fs/data.c | 4 1 file changed, 4 deletions(-) diff --git a/fs/f2fs/data.c b/fs/f2fs/data.c index c82d949709f4..a80d5ef9acbb 100644 --- a/fs/f2fs/data.c +++ b/fs/f2fs/data.c @@ -3280,10 +3280,6 @@ static int __f2fs_write_data_pages(struct address_space *mapping, int ret; bool locked = false; - /* deal with chardevs and other special file */ - if (!mapping->a_ops->writepage) - return 0; - /* skip writing if there is no dirty page in this inode */ if (!get_dirty_pages(inode) && wbc->sync_mode == WB_SYNC_NONE) return 0; -- 2.47.2
[PATCH 00/11] Remove aops->writepage
I was preparing for LSFMM and noticed that actually we're almost done with the writepage conversion. This patchset finishes it off. Something changed in my test environment and now it crashes before even starting a run, so this is only build tested. The first five patches (f2fs and vboxsf) are uninteresting. I'll try and get those into linux-next for the imminent merge window. I think the migrate and writeback patches are good, but maybe I've missed something. Then we come to i915 needing to tell shmem to do writeout, so I added a module-accessible function to do that. I also removed the setting/clearing of reclaim, which would be easy to bring back if it's really needed. Patch 10 is probably the exciting one where pageout() calls swap or shmem directly. And then patch 11 really just removes the op itself and the documentation for it. I may have over-trimmed here, but some of the documentation was so out of date it was hard to tell what was worth preserving. Anyway, let's see what the bots make of this. This is against next-20250307. Matthew Wilcox (Oracle) (11): f2fs: Remove check for ->writepage f2fs: Remove f2fs_write_data_page() f2fs: Remove f2fs_write_meta_page() f2fs: Remove f2fs_write_node_page() vboxsf: Convert to writepages migrate: Remove call to ->writepage writeback: Remove writeback_use_writepage() shmem: Add shmem_writeout() i915: Use writeback_iter() mm: Remove swap_writepage() and shmem_writepage() fs: Remove aops->writepage Documentation/admin-guide/cgroup-v2.rst | 2 +- Documentation/filesystems/fscrypt.rst | 2 +- Documentation/filesystems/locking.rst | 54 + Documentation/filesystems/vfs.rst | 39 block/blk-wbt.c | 2 +- drivers/gpu/drm/i915/gem/i915_gem_shmem.c | 32 - fs/buffer.c | 4 +- fs/f2fs/checkpoint.c | 7 --- fs/f2fs/data.c| 28 --- fs/f2fs/node.c| 8 fs/vboxsf/file.c | 47 ++- include/linux/fs.h| 1 - include/linux/shmem_fs.h | 7 +-- mm/migrate.c | 57 ++- mm/page-writeback.c | 28 +-- mm/page_io.c | 3 +- mm/shmem.c| 33 ++--- mm/swap.h | 4 +- mm/swap_state.c | 1 - mm/swapfile.c | 2 +- mm/vmscan.c | 29 ++-- 21 files changed, 93 insertions(+), 297 deletions(-) -- 2.47.2
[PATCH 07/11] writeback: Remove writeback_use_writepage()
The ->writepage operation is going away. Remove this alternative to
calling ->writepages.
Signed-off-by: Matthew Wilcox (Oracle)
---
mm/page-writeback.c | 28 ++--
1 file changed, 2 insertions(+), 26 deletions(-)
diff --git a/mm/page-writeback.c b/mm/page-writeback.c
index 18456ddd463b..3cf7ae45be58 100644
--- a/mm/page-writeback.c
+++ b/mm/page-writeback.c
@@ -2621,27 +2621,6 @@ int write_cache_pages(struct address_space *mapping,
}
EXPORT_SYMBOL(write_cache_pages);
-static int writeback_use_writepage(struct address_space *mapping,
- struct writeback_control *wbc)
-{
- struct folio *folio = NULL;
- struct blk_plug plug;
- int err;
-
- blk_start_plug(&plug);
- while ((folio = writeback_iter(mapping, wbc, folio, &err))) {
- err = mapping->a_ops->writepage(&folio->page, wbc);
- if (err == AOP_WRITEPAGE_ACTIVATE) {
- folio_unlock(folio);
- err = 0;
- }
- mapping_set_error(mapping, err);
- }
- blk_finish_plug(&plug);
-
- return err;
-}
-
int do_writepages(struct address_space *mapping, struct writeback_control *wbc)
{
int ret;
@@ -2652,14 +2631,11 @@ int do_writepages(struct address_space *mapping, struct
writeback_control *wbc)
wb = inode_to_wb_wbc(mapping->host, wbc);
wb_bandwidth_estimate_start(wb);
while (1) {
- if (mapping->a_ops->writepages) {
+ if (mapping->a_ops->writepages)
ret = mapping->a_ops->writepages(mapping, wbc);
- } else if (mapping->a_ops->writepage) {
- ret = writeback_use_writepage(mapping, wbc);
- } else {
+ else
/* deal with chardevs and other special files */
ret = 0;
- }
if (ret != -ENOMEM || wbc->sync_mode != WB_SYNC_ALL)
break;
--
2.47.2
RE: [PATCH 05/11] drm/i915/dpll: Move away from using shared dpll
> -Original Message-
> From: Ville Syrjälä
> Sent: Friday, 7 March 2025 15.07
> To: Kahola, Mika
> Cc: Kandpal, Suraj ; Jani Nikula
> ; intel...@lists.freedesktop.org; intel-
> g...@lists.freedesktop.org; Syrjala, Ville ;
> Nautiyal, Ankit
> K ; Shankar, Uma
> Subject: Re: [PATCH 05/11] drm/i915/dpll: Move away from using shared dpll
>
> On Fri, Mar 07, 2025 at 12:02:09PM +, Kahola, Mika wrote:
> > > -Original Message-
> > > From: Ville Syrjälä
> > > Sent: Monday, 3 March 2025 14.52
> > > To: Kandpal, Suraj
> > > Cc: Jani Nikula ;
> > > intel...@lists.freedesktop.org; intel-gfx@lists.freedesktop.org;
> > > Syrjala, Ville ; Nautiyal, Ankit K
> > > ; Shankar, Uma ;
> > > Kahola, Mika
> > > Subject: Re: [PATCH 05/11] drm/i915/dpll: Move away from using
> > > shared dpll
> > >
> > > On Fri, Feb 28, 2025 at 03:31:39PM +, Kandpal, Suraj wrote:
> > > >
> > > >
> > > > > -Original Message-
> > > > > From: Ville Syrjälä
> > > > > Sent: Friday, February 28, 2025 7:57 PM
> > > > > To: Kandpal, Suraj
> > > > > Cc: Jani Nikula ;
> > > > > intel...@lists.freedesktop.org; intel-gfx@lists.freedesktop.org;
> > > > > Syrjala, Ville ; Nautiyal, Ankit K
> > > > > ; Shankar, Uma
> > > > > ; Kahola, Mika
> > > > > Subject: Re: [PATCH 05/11] drm/i915/dpll: Move away from using
> > > > > shared dpll
> > > > >
> > > > > On Thu, Feb 27, 2025 at 10:18:31AM +, Kandpal, Suraj wrote:
> > > > > >
> > > > > >
> > > > > > > -Original Message-
> > > > > > > From: Jani Nikula
> > > > > > > Sent: Tuesday, February 25, 2025 9:00 PM
> > > > > > > To: Kandpal, Suraj ;
> > > > > > > intel...@lists.freedesktop.org;
> > > > > > > intel-gfx@lists.freedesktop.org; Syrjala, Ville
> > > > > > >
> > > > > > > Cc: Nautiyal, Ankit K ; Shankar,
> > > > > > > Uma ; Kahola, Mika
> > > > > > >
> > > > > > > Subject: RE: [PATCH 05/11] drm/i915/dpll: Move away from
> > > > > > > using shared dpll
> > > > > > >
> > > > > > > On Tue, 25 Feb 2025, "Kandpal, Suraj"
> wrote:
> > > > > > > >> -Original Message-
> > > > > > > >> From: Kandpal, Suraj
> > > > > > > >> Sent: Tuesday, February 25, 2025 2:25 PM
> > > > > > > >> To: Jani Nikula ;
> > > > > > > >> intel...@lists.freedesktop.org;
> > > > > > > >> intel-gfx@lists.freedesktop.org
> > > > > > > >> Cc: Nautiyal, Ankit K ;
> > > > > > > >> Shankar, Uma ; Kahola, Mika
> > > > > > > >>
> > > > > > > >> Subject: RE: [PATCH 05/11] drm/i915/dpll: Move away from
> > > > > > > >> using shared dpll
> > > > > > > >>
> > > > > > > >>
> > > > > > > >>
> > > > > > > >> > -Original Message-
> > > > > > > >> > From: Jani Nikula
> > > > > > > >> > Sent: Tuesday, February 25, 2025 2:17 PM
> > > > > > > >> > To: Kandpal, Suraj ;
> > > > > > > >> > intel...@lists.freedesktop.org;
> > > > > > > >> > intel-gfx@lists.freedesktop.org
> > > > > > > >> > Cc: Nautiyal, Ankit K ;
> > > > > > > >> > Shankar, Uma ; Kahola, Mika
> > > > > > > >> > ; Kandpal, Suraj
> > > > > > > >> >
> > > > > > > >> > Subject: Re: [PATCH 05/11] drm/i915/dpll: Move away
> > > > > > > >> > from using shared dpll
> > > > > > > >> >
> > > > > > > >> > On Tue, 25 Feb 2025, Suraj Kandpal
> > > > > > > >> >
> > > wrote:
> > > > > > > >> > > Rename functions to move away from using shared dpll
> > > > > > > >> > > in the dpll framework as much as possible since dpll
> > > > > > > >> > > may not always be
> > > > > shared.
> > > > > > > >> > >
> > > > > > > >> > > Signed-off-by: Suraj Kandpal
> > > > > > > >> > >
> > > > > > > >> >
> > > > > > > >> > ...
> > > > > > > >> >
> > > > > > > >> > > diff --git
> > > > > > > >> > > a/drivers/gpu/drm/i915/display/intel_dpll_mgr.h
> > > > > > > >> > > b/drivers/gpu/drm/i915/display/intel_dpll_mgr.h
> > > > > > > >> > > index 6edd103eda55..ef66aca5da1d 100644
> > > > > > > >> > > --- a/drivers/gpu/drm/i915/display/intel_dpll_mgr.h
> > > > > > > >> > > +++ b/drivers/gpu/drm/i915/display/intel_dpll_mgr.h
> > > > > > > >> > > @@ -387,24 +387,24 @@ struct intel_global_dpll {
> > > > > > > >> > > #define
> > > > > > > >> > > SKL_DPLL2
> > > > > > > >> > > 2 #define SKL_DPLL3 3
> > > > > > > >> > >
> > > > > > > >> > > -/* shared dpll functions */
> > > > > > > >> > > +/* global dpll functions */
> > > > > > > >> > > struct intel_global_dpll *
> > > > > > > >> > > -intel_get_shared_dpll_by_id(struct intel_display
> > > > > > > >> > > *display,
> > > > > > > >> > > +intel_get_global_dpll_by_id(struct intel_display
> > > > > > > >> > > +*display,
> > > > > > > >> > >enum intel_dpll_id id); -void
> > > > > > > >> > > assert_shared_dpll(struct intel_display *display,
> > > > > > > >> > > +void assert_global_dpll(struct intel_display
> > > > > > > >> > > +*display,
> > > > > > > >> > >struct intel_global_dpll *pll,
> > > > > > > >> > >bool state);
> > > > > > > >> > > -#define assert_shared_dpll_enabled(d, p)
> > > > > > > >> > > assert_shared_dpll(d, p,
> > > > > > > >> > > true) -#define asser
[PATCH 05/11] vboxsf: Convert to writepages
If we add a migrate_folio operation, we can convert the writepage
operation to writepages. Further, this lets us optimise by using
the same write handle for multiple folios. The large folio support here
is illusory; we would need to kmap each page in turn for proper support.
But we do remove a few hidden calls to compound_head().
Signed-off-by: Matthew Wilcox (Oracle)
---
fs/vboxsf/file.c | 47 +--
1 file changed, 25 insertions(+), 22 deletions(-)
diff --git a/fs/vboxsf/file.c b/fs/vboxsf/file.c
index b780deb81b02..b492794f8e9a 100644
--- a/fs/vboxsf/file.c
+++ b/fs/vboxsf/file.c
@@ -262,40 +262,42 @@ static struct vboxsf_handle
*vboxsf_get_write_handle(struct vboxsf_inode *sf_i)
return sf_handle;
}
-static int vboxsf_writepage(struct page *page, struct writeback_control *wbc)
+static int vboxsf_writepages(struct address_space *mapping,
+ struct writeback_control *wbc)
{
- struct inode *inode = page->mapping->host;
+ struct inode *inode = mapping->host;
+ struct folio *folio = NULL;
struct vboxsf_inode *sf_i = VBOXSF_I(inode);
struct vboxsf_handle *sf_handle;
- loff_t off = page_offset(page);
loff_t size = i_size_read(inode);
- u32 nwrite = PAGE_SIZE;
- u8 *buf;
- int err;
-
- if (off + PAGE_SIZE > size)
- nwrite = size & ~PAGE_MASK;
+ int error;
sf_handle = vboxsf_get_write_handle(sf_i);
if (!sf_handle)
return -EBADF;
- buf = kmap(page);
- err = vboxsf_write(sf_handle->root, sf_handle->handle,
- off, &nwrite, buf);
- kunmap(page);
+ while ((folio = writeback_iter(mapping, wbc, folio, &error))) {
+ loff_t off = folio_pos(folio);
+ u32 nwrite = folio_size(folio);
+ u8 *buf;
- kref_put(&sf_handle->refcount, vboxsf_handle_release);
+ if (nwrite > size - off)
+ nwrite = size - off;
- if (err == 0) {
- /* mtime changed */
- sf_i->force_restat = 1;
- } else {
- ClearPageUptodate(page);
+ buf = kmap_local_folio(folio, 0);
+ error = vboxsf_write(sf_handle->root, sf_handle->handle,
+ off, &nwrite, buf);
+ kunmap_local(buf);
+
+ folio_unlock(folio);
}
- unlock_page(page);
- return err;
+ kref_put(&sf_handle->refcount, vboxsf_handle_release);
+
+ /* mtime changed */
+ if (error == 0)
+ sf_i->force_restat = 1;
+ return error;
}
static int vboxsf_write_end(struct file *file, struct address_space *mapping,
@@ -347,10 +349,11 @@ static int vboxsf_write_end(struct file *file, struct
address_space *mapping,
*/
const struct address_space_operations vboxsf_reg_aops = {
.read_folio = vboxsf_read_folio,
- .writepage = vboxsf_writepage,
+ .writepages = vboxsf_writepages,
.dirty_folio = filemap_dirty_folio,
.write_begin = simple_write_begin,
.write_end = vboxsf_write_end,
+ .migrate_folio = filemap_migrate_folio,
};
static const char *vboxsf_get_link(struct dentry *dentry, struct inode *inode,
--
2.47.2
[PATCH 04/11] f2fs: Remove f2fs_write_node_page()
Mappings which implement writepages should not implement writepage
as it can only harm writeback patterns.
Signed-off-by: Matthew Wilcox (Oracle)
---
fs/f2fs/node.c | 8
1 file changed, 8 deletions(-)
diff --git a/fs/f2fs/node.c b/fs/f2fs/node.c
index 36614a1c2590..b78c1f95bc04 100644
--- a/fs/f2fs/node.c
+++ b/fs/f2fs/node.c
@@ -1784,13 +1784,6 @@ int f2fs_move_node_page(struct page *node_page, int
gc_type)
return err;
}
-static int f2fs_write_node_page(struct page *page,
- struct writeback_control *wbc)
-{
- return __write_node_page(page, false, NULL, wbc, false,
- FS_NODE_IO, NULL);
-}
-
int f2fs_fsync_node_pages(struct f2fs_sb_info *sbi, struct inode *inode,
struct writeback_control *wbc, bool atomic,
unsigned int *seq_id)
@@ -2217,7 +2210,6 @@ static bool f2fs_dirty_node_folio(struct address_space
*mapping,
* Structure of the f2fs node operations
*/
const struct address_space_operations f2fs_node_aops = {
- .writepage = f2fs_write_node_page,
.writepages = f2fs_write_node_pages,
.dirty_folio= f2fs_dirty_node_folio,
.invalidate_folio = f2fs_invalidate_folio,
--
2.47.2
[PATCH 06/11] migrate: Remove call to ->writepage
The writepage callback is going away; filesystems must implement
migrate_folio or else dirty folios will not be migratable.
Signed-off-by: Matthew Wilcox (Oracle)
---
mm/migrate.c | 57
1 file changed, 4 insertions(+), 53 deletions(-)
diff --git a/mm/migrate.c b/mm/migrate.c
index c0adea67cd62..3d1d9d49fb8e 100644
--- a/mm/migrate.c
+++ b/mm/migrate.c
@@ -944,67 +944,18 @@ int filemap_migrate_folio(struct address_space *mapping,
}
EXPORT_SYMBOL_GPL(filemap_migrate_folio);
-/*
- * Writeback a folio to clean the dirty state
- */
-static int writeout(struct address_space *mapping, struct folio *folio)
-{
- struct writeback_control wbc = {
- .sync_mode = WB_SYNC_NONE,
- .nr_to_write = 1,
- .range_start = 0,
- .range_end = LLONG_MAX,
- .for_reclaim = 1
- };
- int rc;
-
- if (!mapping->a_ops->writepage)
- /* No write method for the address space */
- return -EINVAL;
-
- if (!folio_clear_dirty_for_io(folio))
- /* Someone else already triggered a write */
- return -EAGAIN;
-
- /*
-* A dirty folio may imply that the underlying filesystem has
-* the folio on some queue. So the folio must be clean for
-* migration. Writeout may mean we lose the lock and the
-* folio state is no longer what we checked for earlier.
-* At this point we know that the migration attempt cannot
-* be successful.
-*/
- remove_migration_ptes(folio, folio, 0);
-
- rc = mapping->a_ops->writepage(&folio->page, &wbc);
-
- if (rc != AOP_WRITEPAGE_ACTIVATE)
- /* unlocked. Relock */
- folio_lock(folio);
-
- return (rc < 0) ? -EIO : -EAGAIN;
-}
-
/*
* Default handling if a filesystem does not provide a migration function.
*/
static int fallback_migrate_folio(struct address_space *mapping,
struct folio *dst, struct folio *src, enum migrate_mode mode)
{
- if (folio_test_dirty(src)) {
- /* Only writeback folios in full synchronous migration */
- switch (mode) {
- case MIGRATE_SYNC:
- break;
- default:
- return -EBUSY;
- }
- return writeout(mapping, src);
- }
+ if (folio_test_dirty(src))
+ return -EBUSY;
/*
-* Buffers may be managed in a filesystem specific way.
-* We must have no buffers or drop them.
+* Filesystem may have private data at folio->private that we
+* can't migrate automatically.
*/
if (!filemap_release_folio(src, GFP_KERNEL))
return mode == MIGRATE_SYNC ? -EAGAIN : -EBUSY;
--
2.47.2
[PATCH 10/11] mm: Remove swap_writepage() and shmem_writepage()
Call swap_writeout() and shmem_writeout() from pageout() instead.
Signed-off-by: Matthew Wilcox (Oracle)
---
block/blk-wbt.c | 2 +-
mm/page_io.c| 3 +--
mm/shmem.c | 23 +--
mm/swap.h | 4 ++--
mm/swap_state.c | 1 -
mm/swapfile.c | 2 +-
mm/vmscan.c | 28
7 files changed, 26 insertions(+), 37 deletions(-)
diff --git a/block/blk-wbt.c b/block/blk-wbt.c
index f1754d07f7e0..60885731e8ab 100644
--- a/block/blk-wbt.c
+++ b/block/blk-wbt.c
@@ -37,7 +37,7 @@
enum wbt_flags {
WBT_TRACKED = 1,/* write, tracked for throttling */
WBT_READ= 2,/* read */
- WBT_SWAP= 4,/* write, from swap_writepage() */
+ WBT_SWAP= 4,/* write, from swap_writeout() */
WBT_DISCARD = 8,/* discard */
WBT_NR_BITS = 4,/* number of bits */
diff --git a/mm/page_io.c b/mm/page_io.c
index 9b983de351f9..e9151952c514 100644
--- a/mm/page_io.c
+++ b/mm/page_io.c
@@ -237,9 +237,8 @@ static void swap_zeromap_folio_clear(struct folio *folio)
* We may have stale swap cache pages in memory: notice
* them here and get rid of the unnecessary final write.
*/
-int swap_writepage(struct page *page, struct writeback_control *wbc)
+int swap_writeout(struct folio *folio, struct writeback_control *wbc)
{
- struct folio *folio = page_folio(page);
int ret;
if (folio_free_swap(folio)) {
diff --git a/mm/shmem.c b/mm/shmem.c
index 427b7f70fffb..a786b94a468a 100644
--- a/mm/shmem.c
+++ b/mm/shmem.c
@@ -98,7 +98,7 @@ static struct vfsmount *shm_mnt __ro_after_init;
#define SHORT_SYMLINK_LEN 128
/*
- * shmem_fallocate communicates with shmem_fault or shmem_writepage via
+ * shmem_fallocate communicates with shmem_fault or shmem_writeout via
* inode->i_private (with i_rwsem making sure that it has only one user at
* a time): we would prefer not to enlarge the shmem inode just for that.
*/
@@ -107,7 +107,7 @@ struct shmem_falloc {
pgoff_t start; /* start of range currently being fallocated */
pgoff_t next; /* the next page offset to be fallocated */
pgoff_t nr_falloced;/* how many new pages have been fallocated */
- pgoff_t nr_unswapped; /* how often writepage refused to swap out */
+ pgoff_t nr_unswapped; /* how often writeout refused to swap out */
};
struct shmem_options {
@@ -446,7 +446,7 @@ static void shmem_recalc_inode(struct inode *inode, long
alloced, long swapped)
/*
* Special case: whereas normally shmem_recalc_inode() is called
* after i_mapping->nrpages has already been adjusted (up or down),
-* shmem_writepage() has to raise swapped before nrpages is lowered -
+* shmem_writeout() has to raise swapped before nrpages is lowered -
* to stop a racing shmem_recalc_inode() from thinking that a page has
* been freed. Compensate here, to avoid the need for a followup call.
*/
@@ -1536,11 +1536,6 @@ int shmem_unuse(unsigned int type)
return error;
}
-static int shmem_writepage(struct page *page, struct writeback_control *wbc)
-{
- return shmem_writeout(page_folio(page), wbc);
-}
-
/**
* shmem_writeout - Write the folio to swap
* @folio: The folio to write
@@ -1558,13 +1553,6 @@ int shmem_writeout(struct folio *folio, struct
writeback_control *wbc)
int nr_pages;
bool split = false;
- /*
-* Our capabilities prevent regular writeback or sync from ever calling
-* shmem_writepage; but a stacking filesystem might use ->writepage of
-* its underlying filesystem, in which case tmpfs should write out to
-* swap only in response to memory pressure, and not for the writeback
-* threads or sync.
-*/
if (WARN_ON_ONCE(!wbc->for_reclaim))
goto redirty;
@@ -1653,7 +1641,7 @@ int shmem_writeout(struct folio *folio, struct
writeback_control *wbc)
mutex_unlock(&shmem_swaplist_mutex);
BUG_ON(folio_mapped(folio));
- return swap_writepage(&folio->page, wbc);
+ return swap_writeout(folio, wbc);
}
list_del_init(&info->swaplist);
@@ -3780,7 +3768,7 @@ static long shmem_fallocate(struct file *file, int mode,
loff_t offset,
index--;
/*
-* Inform shmem_writepage() how far we have reached.
+* Inform shmem_writeout() how far we have reached.
* No need for lock or barrier: we have the page lock.
*/
if (!folio_test_uptodate(folio))
@@ -5203,7 +5191,6 @@ static int shmem_error_remove_folio(struct address_space
*mapping,
}
static const struct address_space_operations shmem_aops = {
- .writepage = shmem_writepage,
.dirty_folio= noop_dirty_folio,
[PATCH 09/11] i915: Use writeback_iter()
Convert from an inefficient loop to the standard writeback iterator.
Signed-off-by: Matthew Wilcox (Oracle)
---
drivers/gpu/drm/i915/gem/i915_gem_shmem.c | 32 ++-
1 file changed, 8 insertions(+), 24 deletions(-)
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_shmem.c
b/drivers/gpu/drm/i915/gem/i915_gem_shmem.c
index ae3343c81a64..5e784db9f315 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_shmem.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_shmem.c
@@ -305,36 +305,20 @@ void __shmem_writeback(size_t size, struct address_space
*mapping)
.range_end = LLONG_MAX,
.for_reclaim = 1,
};
- unsigned long i;
+ struct folio *folio = NULL;
+ int error = 0;
/*
* Leave mmapings intact (GTT will have been revoked on unbinding,
-* leaving only CPU mmapings around) and add those pages to the LRU
+* leaving only CPU mmapings around) and add those folios to the LRU
* instead of invoking writeback so they are aged and paged out
* as normal.
*/
-
- /* Begin writeback on each dirty page */
- for (i = 0; i < size >> PAGE_SHIFT; i++) {
- struct page *page;
-
- page = find_lock_page(mapping, i);
- if (!page)
- continue;
-
- if (!page_mapped(page) && clear_page_dirty_for_io(page)) {
- int ret;
-
- SetPageReclaim(page);
- ret = mapping->a_ops->writepage(page, &wbc);
- if (!PageWriteback(page))
- ClearPageReclaim(page);
- if (!ret)
- goto put;
- }
- unlock_page(page);
-put:
- put_page(page);
+ while ((folio = writeback_iter(mapping, &wbc, folio, &error))) {
+ if (folio_mapped(folio))
+ folio_redirty_for_writepage(&wbc, folio);
+ else
+ error = shmem_writeout(folio, &wbc);
}
}
--
2.47.2
[PATCH 03/11] f2fs: Remove f2fs_write_meta_page()
Mappings which implement writepages should not implement writepage
as it can only harm writeback patterns.
Signed-off-by: Matthew Wilcox (Oracle)
---
fs/f2fs/checkpoint.c | 7 ---
1 file changed, 7 deletions(-)
diff --git a/fs/f2fs/checkpoint.c b/fs/f2fs/checkpoint.c
index a35595f8d3f5..412282f50cbb 100644
--- a/fs/f2fs/checkpoint.c
+++ b/fs/f2fs/checkpoint.c
@@ -381,12 +381,6 @@ static int __f2fs_write_meta_page(struct page *page,
return AOP_WRITEPAGE_ACTIVATE;
}
-static int f2fs_write_meta_page(struct page *page,
- struct writeback_control *wbc)
-{
- return __f2fs_write_meta_page(page, wbc, FS_META_IO);
-}
-
static int f2fs_write_meta_pages(struct address_space *mapping,
struct writeback_control *wbc)
{
@@ -507,7 +501,6 @@ static bool f2fs_dirty_meta_folio(struct address_space
*mapping,
}
const struct address_space_operations f2fs_meta_aops = {
- .writepage = f2fs_write_meta_page,
.writepages = f2fs_write_meta_pages,
.dirty_folio= f2fs_dirty_meta_folio,
.invalidate_folio = f2fs_invalidate_folio,
--
2.47.2
Re: [PATCH v4 3/8] bits: introduce fixed-type genmasks
+ Anshuman Khandual Anshuman, I merged your GENMASK_U128() because you said it's important for your projects, and that it will get used in the kernel soon. Now it's in the kernel for more than 6 month, but no users were added. Can you clarify if you still need it, and if so why it's not used? As you see, people add another fixed-types GENMASK() macros, and their implementation differ from GENMASK_U128(). My second concern is that __GENMASK_U128() is declared in uapi, while the general understanding for other fixed-type genmasks is that they are not exported to users. Do you need this macro to be exported to userspace? Can you show how and where it is used there? Thanks, Yury On Wed, Mar 05, 2025 at 10:00:15PM +0900, Vincent Mailhol via B4 Relay wrote: > From: Yury Norov > > Add __GENMASK_t() which generalizes __GENMASK() to support different > types, and implement fixed-types versions of GENMASK() based on it. > The fixed-type version allows more strict checks to the min/max values > accepted, which is useful for defining registers like implemented by > i915 and xe drivers with their REG_GENMASK*() macros. > > The strict checks rely on shift-count-overflow compiler check to fail > the build if a number outside of the range allowed is passed. > Example: > > #define FOO_MASK GENMASK_U32(33, 4) > > will generate a warning like: > > ../include/linux/bits.h:41:31: error: left shift count >= width of type > [-Werror=shift-count-overflow] > 41 | (((t)~0ULL - ((t)(1) << (l)) + 1) & \ > | ^~ > > Signed-off-by: Yury Norov > Signed-off-by: Lucas De Marchi > Acked-by: Jani Nikula > Signed-off-by: Vincent Mailhol > --- > Changelog: > > v3 -> v4: > > - The v3 is one year old. Meanwhile people started using > __GENMASK() directly. So instead of generalizing __GENMASK() to > support different types, add a new GENMASK_t(). > > - replace ~0ULL by ~_ULL(0). Otherwise, __GENMASK_t() would fail > in asm code. > > - Make GENMASK_U8() and GENMASK_U16() return an unsigned int. In > v3, due to the integer promotion rules, these were returning a > signed integer. By casting these to unsigned int, at least the > signedness is kept. > --- > include/linux/bitops.h | 1 - > include/linux/bits.h | 33 + > 2 files changed, 29 insertions(+), 5 deletions(-) > > diff --git a/include/linux/bitops.h b/include/linux/bitops.h > index > c1cb53cf2f0f8662ed3e324578f74330e63f935d..9be2d50da09a417966b3d11c84092bb2f4cd0bef > 100644 > --- a/include/linux/bitops.h > +++ b/include/linux/bitops.h > @@ -8,7 +8,6 @@ > > #include > > -#define BITS_PER_TYPE(type) (sizeof(type) * BITS_PER_BYTE) > #define BITS_TO_LONGS(nr)__KERNEL_DIV_ROUND_UP(nr, BITS_PER_TYPE(long)) > #define BITS_TO_U64(nr) __KERNEL_DIV_ROUND_UP(nr, > BITS_PER_TYPE(u64)) > #define BITS_TO_U32(nr) __KERNEL_DIV_ROUND_UP(nr, > BITS_PER_TYPE(u32)) > diff --git a/include/linux/bits.h b/include/linux/bits.h > index > 5f68980a1b98d771426872c74d7b5c0f79e5e802..f202e46d2f4b7899c16d975120f3fa3ae41556ae > 100644 > --- a/include/linux/bits.h > +++ b/include/linux/bits.h > @@ -12,6 +12,7 @@ > #define BIT_ULL_MASK(nr) (ULL(1) << ((nr) % BITS_PER_LONG_LONG)) > #define BIT_ULL_WORD(nr) ((nr) / BITS_PER_LONG_LONG) > #define BITS_PER_BYTE8 > +#define BITS_PER_TYPE(type) (sizeof(type) * BITS_PER_BYTE) > > /* > * Create a contiguous bitmask starting at bit position @l and ending at > @@ -25,14 +26,38 @@ > > #define GENMASK_INPUT_CHECK(h, l) BUILD_BUG_ON_ZERO(const_true((l) > (h))) > > -#define GENMASK(h, l) \ > - (GENMASK_INPUT_CHECK(h, l) + __GENMASK(h, l)) > -#define GENMASK_ULL(h, l) \ > - (GENMASK_INPUT_CHECK(h, l) + __GENMASK_ULL(h, l)) > +/* > + * Generate a mask for the specified type @t. Additional checks are made to > + * guarantee the value returned fits in that type, relying on > + * shift-count-overflow compiler check to detect incompatible arguments. > + * For example, all these create build errors or warnings: > + * > + * - GENMASK(15, 20): wrong argument order > + * - GENMASK(72, 15): doesn't fit unsigned long > + * - GENMASK_U32(33, 15): doesn't fit in a u32 > + */ > +#define GENMASK_t(t, h, l) \ > + (GENMASK_INPUT_CHECK(h, l) +\ > + (((t)~ULL(0) - ((t)1 << (l)) + 1) &\ > + ((t)~ULL(0) >> (BITS_PER_TYPE(t) - 1 - (h) > + > +#define GENMASK(h, l) GENMASK_t(unsigned long, h, l) > +#define GENMASK_ULL(h, l) GENMASK_t(unsigned long long, h, l) > > /* > * Missing asm support > * > + * __GENMASK_U*() depends on BITS_PER_TYPE() which would not work in the asm > + * code as BITS_PER_TYPE() relies on sizeof(), something not available in > + * asm. Nethertheless, the concept of fixed width integers is a C thing which > + * does not apply to assembly c
[PATCH v4 3/8] bits: introduce fixed-type genmasks
From: Yury Norov Add __GENMASK_t() which generalizes __GENMASK() to support different types, and implement fixed-types versions of GENMASK() based on it. The fixed-type version allows more strict checks to the min/max values accepted, which is useful for defining registers like implemented by i915 and xe drivers with their REG_GENMASK*() macros. The strict checks rely on shift-count-overflow compiler check to fail the build if a number outside of the range allowed is passed. Example: #define FOO_MASK GENMASK_U32(33, 4) will generate a warning like: ../include/linux/bits.h:41:31: error: left shift count >= width of type [-Werror=shift-count-overflow] 41 | (((t)~0ULL - ((t)(1) << (l)) + 1) & \ | ^~ Signed-off-by: Yury Norov Signed-off-by: Lucas De Marchi Acked-by: Jani Nikula Signed-off-by: Vincent Mailhol --- Changelog: v3 -> v4: - The v3 is one year old. Meanwhile people started using __GENMASK() directly. So instead of generalizing __GENMASK() to support different types, add a new GENMASK_t(). - replace ~0ULL by ~_ULL(0). Otherwise, __GENMASK_t() would fail in asm code. - Make GENMASK_U8() and GENMASK_U16() return an unsigned int. In v3, due to the integer promotion rules, these were returning a signed integer. By casting these to unsigned int, at least the signedness is kept. --- include/linux/bitops.h | 1 - include/linux/bits.h | 33 + 2 files changed, 29 insertions(+), 5 deletions(-) diff --git a/include/linux/bitops.h b/include/linux/bitops.h index c1cb53cf2f0f8662ed3e324578f74330e63f935d..9be2d50da09a417966b3d11c84092bb2f4cd0bef 100644 --- a/include/linux/bitops.h +++ b/include/linux/bitops.h @@ -8,7 +8,6 @@ #include -#define BITS_PER_TYPE(type)(sizeof(type) * BITS_PER_BYTE) #define BITS_TO_LONGS(nr) __KERNEL_DIV_ROUND_UP(nr, BITS_PER_TYPE(long)) #define BITS_TO_U64(nr)__KERNEL_DIV_ROUND_UP(nr, BITS_PER_TYPE(u64)) #define BITS_TO_U32(nr)__KERNEL_DIV_ROUND_UP(nr, BITS_PER_TYPE(u32)) diff --git a/include/linux/bits.h b/include/linux/bits.h index 5f68980a1b98d771426872c74d7b5c0f79e5e802..f202e46d2f4b7899c16d975120f3fa3ae41556ae 100644 --- a/include/linux/bits.h +++ b/include/linux/bits.h @@ -12,6 +12,7 @@ #define BIT_ULL_MASK(nr) (ULL(1) << ((nr) % BITS_PER_LONG_LONG)) #define BIT_ULL_WORD(nr) ((nr) / BITS_PER_LONG_LONG) #define BITS_PER_BYTE 8 +#define BITS_PER_TYPE(type)(sizeof(type) * BITS_PER_BYTE) /* * Create a contiguous bitmask starting at bit position @l and ending at @@ -25,14 +26,38 @@ #define GENMASK_INPUT_CHECK(h, l) BUILD_BUG_ON_ZERO(const_true((l) > (h))) -#define GENMASK(h, l) \ - (GENMASK_INPUT_CHECK(h, l) + __GENMASK(h, l)) -#define GENMASK_ULL(h, l) \ - (GENMASK_INPUT_CHECK(h, l) + __GENMASK_ULL(h, l)) +/* + * Generate a mask for the specified type @t. Additional checks are made to + * guarantee the value returned fits in that type, relying on + * shift-count-overflow compiler check to detect incompatible arguments. + * For example, all these create build errors or warnings: + * + * - GENMASK(15, 20): wrong argument order + * - GENMASK(72, 15): doesn't fit unsigned long + * - GENMASK_U32(33, 15): doesn't fit in a u32 + */ +#define GENMASK_t(t, h, l) \ + (GENMASK_INPUT_CHECK(h, l) +\ +(((t)~ULL(0) - ((t)1 << (l)) + 1) &\ + ((t)~ULL(0) >> (BITS_PER_TYPE(t) - 1 - (h) + +#define GENMASK(h, l) GENMASK_t(unsigned long, h, l) +#define GENMASK_ULL(h, l) GENMASK_t(unsigned long long, h, l) /* * Missing asm support * + * __GENMASK_U*() depends on BITS_PER_TYPE() which would not work in the asm + * code as BITS_PER_TYPE() relies on sizeof(), something not available in + * asm. Nethertheless, the concept of fixed width integers is a C thing which + * does not apply to assembly code. + */ +#define GENMASK_U8(h, l) ((unsigned int)GENMASK_t(u8, h, l)) +#define GENMASK_U16(h, l) ((unsigned int)GENMASK_t(u16, h, l)) +#define GENMASK_U32(h, l) GENMASK_t(u32, h, l) +#define GENMASK_U64(h, l) GENMASK_t(u64, h, l) + +/* * __GENMASK_U128() depends on _BIT128() which would not work * in the asm code, as it shifts an 'unsigned __int128' data * type instead of direct representation of 128 bit constants -- 2.45.3
[PATCH v4 6/8] test_bits: add tests for __GENMASK() and __GENMASK_ULL()
From: Vincent Mailhol
The definitions of GENMASK() and GENMASK_ULL() do not depend any more
on __GENMASK() and __GENMASK_ULL(). Duplicate the existing unit tests
so that __GENMASK{,ULL}() is still covered.
Signed-off-by: Vincent Mailhol
---
lib/test_bits.c | 18 ++
1 file changed, 18 insertions(+)
diff --git a/lib/test_bits.c b/lib/test_bits.c
index
c7b38d91e1f16d42b7ca92e62fbd6c19b37e76a0..dc93ded9fdb201e0d44b3c1cd71e233fd62258a5
100644
--- a/lib/test_bits.c
+++ b/lib/test_bits.c
@@ -7,6 +7,22 @@
#include
+static void __genmask_test(struct kunit *test)
+{
+ KUNIT_EXPECT_EQ(test, 1ul, __GENMASK(0, 0));
+ KUNIT_EXPECT_EQ(test, 3ul, __GENMASK(1, 0));
+ KUNIT_EXPECT_EQ(test, 6ul, __GENMASK(2, 1));
+ KUNIT_EXPECT_EQ(test, 0xul, __GENMASK(31, 0));
+}
+
+static void __genmask_ull_test(struct kunit *test)
+{
+ KUNIT_EXPECT_EQ(test, 1ull, __GENMASK_ULL(0, 0));
+ KUNIT_EXPECT_EQ(test, 3ull, __GENMASK_ULL(1, 0));
+ KUNIT_EXPECT_EQ(test, 0x00e0ull, __GENMASK_ULL(39, 21));
+ KUNIT_EXPECT_EQ(test, 0xull, __GENMASK_ULL(63, 0));
+}
+
static void genmask_test(struct kunit *test)
{
KUNIT_EXPECT_EQ(test, 1ul, GENMASK(0, 0));
@@ -93,6 +109,8 @@ static void genmask_input_check_test(struct kunit *test)
static struct kunit_case bits_test_cases[] = {
+ KUNIT_CASE(__genmask_test),
+ KUNIT_CASE(__genmask_ull_test),
KUNIT_CASE(genmask_test),
KUNIT_CASE(genmask_ull_test),
KUNIT_CASE(genmask_u128_test),
--
2.45.3
Re: [PATCH v5 7/7] test_bits: add tests for BIT_U*()
On 07/03/2025 at 02:55, Andy Shevchenko wrote: > On Fri, Mar 07, 2025 at 01:08:15AM +0900, Vincent Mailhol wrote: >> On 06/03/2025 at 22:11, Andy Shevchenko wrote: >>> On Thu, Mar 06, 2025 at 08:29:58PM +0900, Vincent Mailhol via B4 Relay >>> wrote: From: Vincent Mailhol Add some additional tests in lib/test_bits.c to cover the expected results of the fixed type BIT_U*() macros. >>> >>> Still would be good to have a small assembly test case for GENMASK*() as >>> they >>> went split and it will be a good regression test in case somebody decides to >>> unify both without much thinking.. >> >> Let me confirm that I correctly understood your ask. Would something >> like this meet your expectations? > > I believe it should be written in asm. I am not confident enough in my assembly skills to submit asm patches to the kernel. So, I would rather take a pass on that one. Regardless, if somebody decides to unify both without much thinking as you said, I am fully confident that the patch will get Nack-ed right away. So, I do not have any concerns. Yours sincerely, Vincent Mailhol
[PATCH v5 0/7] bits: Fixed-type GENMASK()/BIT()
Introduce some fixed width variant of the GENMASK() and the BIT() macros in bits.h. Note that the main goal is not to get the correct type, but rather to enforce more checks at compile time. For example: GENMASK_U16(16, 0) will raise a build bug. This series is a continuation of: https://lore.kernel.org/intel-xe/20240208074521.577076-1-lucas.demar...@intel.com from Lucas De Marchi. Above series is one year old. I really think that this was a good idea and I do not want this series to die. So I am volunteering to revive it. Meanwhile, many changes occurred in bits.h. The most significant change is that __GENMASK() was moved to the uapi headers. In v4 an onward, I introduce one big change: split the definition of the asm and non-asm GENMASK(). I think this is controversial. Especially, Yury commented that he did not want such split. So I initially implemented a first draft in which both the asm and non-asm version would rely on the same helper macro, i.e. adding this: #define __GENMASK_t(t, w, h, l) \ (((t)~_ULL(0) - ((t)1 << (l)) + 1) &\ ((t)~_ULL(0) >> (w - 1 - (h to uapi/bits.h. And then, the different GENMASK()s would look like this: #define __GENMASK(h, l) __GENMASK_t(unsigned long, __BITS_PER_LONG, h, l) and so on. I implemented it, and the final result looks quite ugly. Not only do we need to manually provide the width each time, the biggest concern is that adding this to the uapi is asking for trouble. Who knows how people are going to use this? And once it is in the uapi, there is virtually no way back. Finally, I do not think it makes sense to expose the fixed width variants to the asm. The fixed width integers type are a C concept. For asm, the long and long long variants seems sufficient. And so, after implementing both, the asm and non-asm split seems way more clean and I think this is the best compromise. Let me know what you think :) As requested, here are the bloat-o-meter stats: $ ./scripts/bloat-o-meter vmlinux_before.o vmlinux_after.o add/remove: 0/0 grow/shrink: 4/2 up/down: 5/-4 (1) Function old new delta intel_psr_invalidate 666 668 +2 mst_stream_compute_config 16521653 +1 intel_psr_flush 977 978 +1 intel_dp_compute_link_config13271328 +1 cfg80211_inform_bss_data51095108 -1 intel_drrs_activate 379 376 -3 Total: Before=22723481, After=22723482, chg +0.00% (done with GCC 12.4.1 on a defconfig) -- 2.43.0 --- Changes from v4: - Rebase on https://github.com/norov/linux/tree/bitmap-for-next - Rename GENMASK_t() to GENMASK_TYPE() - First patch of v4 (the typo fix 'init128' -> 'int128') is removed because it was resent separately in: https://lore.kernel.org/all/20250305-fix_init128_typo-v1-1-cbe5b8e54...@wanadoo.fr - Replace the (t)~ULL(0) by type_max(t). This way, GENMASK_TYPE() can now be used to generate GENMASK_U128(). - Get rid of the unsigned int cast for the U8 and U16 variants. - Add the BIT_TYPE() helper macro. - Link to v4: https://lore.kernel.org/r/20250305-fixed-type-genmasks-v4-0-1873dcdf6...@wanadoo.fr Changes from v3: - Rebase on v6.14-rc5 - Fix a typo in GENMASK_U128() comment. - Split the asm and non-asm definition of - Replace ~0ULL by ~ULL(0) - Since v3, __GENMASK() was moved to the uapi and people started using directly. Introduce GENMASK_t() instead. - Link to v3: https://lore.kernel.org/intel-xe/20240208074521.577076-1-lucas.demar...@intel.com Changes from v2: - Document both in commit message and code about the strict type checking and give examples how it´d break with invalid params. - Link to v2: https://lore.kernel.org/intel-xe/20240124050205.3646390-1-lucas.demar...@intel.com Link to v1: https://lore.kernel.org/intel-xe/20230509051403.2748545-1-lucas.demar...@intel.com --- Lucas De Marchi (3): bits: introduce fixed-type BIT_U*() drm/i915: Convert REG_GENMASK*() to fixed-width GENMASK_U*() test_bits: add tests for GENMASK_U*() Vincent Mailhol (3): bits: split the definition of the asm and non-asm GENMASK() test_bits: add tests for __GENMASK() and __GENMASK_ULL() test_bits: add tests for BIT_U*() Yury Norov (1): bits: introduce fixed-type genmasks drivers/gpu/drm/i915/i915_reg_defs.h | 108 --- include/linux/bitops.h | 1 - include/linux/bits.h | 77 ++--- lib/test_bits.c | 47 +++ 4 files changed, 113 insertions(+), 120 deletions(-) --- base-commit: 0312e94abe484b9ee58c32d2f8ba177e04955b35 change-id: 20250228-fixed-type-genmasks-8d1a555f34e8 Best regards, -- Vincent Mailhol
Re: [PATCH v4 3/8] bits: introduce fixed-type genmasks
On 06/03/2025 at 04:45, Andy Shevchenko wrote: >>> But GENMASK_U128() becomes a special case now. >>> The 128-bit GENMASK is unsued, but it's exported in uapi. Is there any >>> simple way to end up with a common implementation for all fixed-type >>> GENMASKs? >> >> What bothers me is that the 128 bit types are not something available on >> all architectures, c.f. the CONFIG_ARCH_SUPPORTS_INT128. So, I would >> need a U128() equivalent to the ULL() but which does not break on >> architectures which do not support 128 bits integers. >> >> This is where I am stuck. If someone can guide me on how to write a >> robust U128() macro, then I think the common implementation could be >> feasible. > > I think we may leave that U128 stuff alone for now. I found the solution! The trick is to use type_max() from overflow.h. With this, GENMASK_TYPE() becomes: #define GENMASK_TYPE(t, h, l) \ ((t)(GENMASK_INPUT_CHECK(h, l) +\ (type_max(t) << (l) & \ type_max(t) >> (BITS_PER_TYPE(t) - 1 - (h) and works with all the GENMASK variants, including the U128 one! The unit tests under lib/test_bits.c are all green. Of course, this does *not* work in assembly. But as explained before, GENMASK_TYPE() is guarded by a #if !defined(__ASSEMBLY__), so all good! The question raised by Yury on whether or not we should keep __GENMASK_U128() in the uapi still remains. And in full honesty, I will not touch that one. This is not in the scope of this series. Yours sincerely, Vincent Mailhol
[PATCH v4 0/8] bits: Fixed-type GENMASK()/BIT()
Introduce some fixed width variant of the GENMASK() and the BIT() macros in bits.h. Note that the main goal is not to get the correct type, but rather to enforce more checks at compile time. For example: GENMASK_U16(16, 0) will raise a build bug. This series is a continuation of: https://lore.kernel.org/intel-xe/20240208074521.577076-1-lucas.demar...@intel.com from Lucas De Marchi. Above series is one year old. I really think that this was a good idea and I do not want this series to die. So I am volunteering to revive it. Meanwhile, many changes occurred in bits.h. The most significant change is that __GENMASK() was moved to the uapi headers. In this v4, I introduce one big change: split the definition of the asm and non-asm GENMASK(). I think this is controversial. Especially, Yuri commented that he did not want such split. So I initially implemented a first draft in which both the asm and non-asm version would rely on the same helper macro, i.e. adding this: #define __GENMASK_t(t, w, h, l) \ (((t)~_ULL(0) - ((t)1 << (l)) + 1) &\ ((t)~_ULL(0) >> (w - 1 - (h to uapi/bits.h. And then, the different GENMASK()s would look like this: #define __GENMASK(h, l) __GENMASK_t(unsigned long, __BITS_PER_LONG, h, l) and so on. I implemented it, and the final result looks quite ugly. Not only do we need to manually provide the width each time, the biggest concern is that adding this to the uapi is asking for trouble. Who knows how people are going to use this? And once it is in the uapi, there is virtually no way back. Finally, I do not think it makes sense to expose the fixed width variants to the asm. The fixed width integers type are a C concept. For asm, the long and long long variants seems sufficient. And so, after implementing both, the asm and non-asm split seems way more clean and I think this is the best compromise. Let me know what you think :) Changes from v3: - Rebase on v6.14-rc5 - Fix a typo in GENMASK_U128() comment. - Split the asm and non-asm definition of - Replace ~0ULL by ~ULL(0) - Since v3, __GENMASK() was moved to the uapi and people started using directly. Introduce GENMASK_t() instead. v3: https://lore.kernel.org/intel-xe/20240208074521.577076-1-lucas.demar...@intel.com Changes from v2: - Document both in commit message and code about the strict type checking and give examples how it´d break with invalid params. v2: https://lore.kernel.org/intel-xe/20240124050205.3646390-1-lucas.demar...@intel.com v1: https://lore.kernel.org/intel-xe/20230509051403.2748545-1-lucas.demar...@intel.com -- 2.43.0 --- Lucas De Marchi (3): bits: introduce fixed-type BIT drm/i915: Convert REG_GENMASK* to fixed-width GENMASK_* test_bits: add tests for fixed-type genmasks Vincent Mailhol (4): bits: fix typo 'unsigned __init128' -> 'unsigned __int128' bits: split the definition of the asm and non-asm GENMASK() test_bits: add tests for __GENMASK() and __GENMASK_ULL() test_bits: add tests for fixed-type BIT Yury Norov (1): bits: introduce fixed-type genmasks drivers/gpu/drm/i915/i915_reg_defs.h | 108 --- include/linux/bitops.h | 1 - include/linux/bits.h | 65 + lib/test_bits.c | 47 +++ 4 files changed, 111 insertions(+), 110 deletions(-) --- base-commit: 7eb172143d5508b4da468ed59ee857c6e5e01da6 change-id: 20250228-fixed-type-genmasks-8d1a555f34e8 Best regards, -- Vincent Mailhol
[PATCH RFC v3 5/7] drm/display: dp-cec: use new DCPD access helpers
From: Dmitry Baryshkov
Switch drm_dp_cec.c to use new set of DPCD read / write helpers.
Reviewed-by: Lyude Paul
Acked-by: Jani Nikula
Signed-off-by: Dmitry Baryshkov
---
drivers/gpu/drm/display/drm_dp_cec.c | 37 ++--
1 file changed, 18 insertions(+), 19 deletions(-)
diff --git a/drivers/gpu/drm/display/drm_dp_cec.c
b/drivers/gpu/drm/display/drm_dp_cec.c
index
56a4965e518cc237c992a2e31b9f6de05c14766a..ed31471bd0e28826254ecedac48c5c126729d470
100644
--- a/drivers/gpu/drm/display/drm_dp_cec.c
+++ b/drivers/gpu/drm/display/drm_dp_cec.c
@@ -96,7 +96,7 @@ static int drm_dp_cec_adap_enable(struct cec_adapter *adap,
bool enable)
u32 val = enable ? DP_CEC_TUNNELING_ENABLE : 0;
ssize_t err = 0;
- err = drm_dp_dpcd_writeb(aux, DP_CEC_TUNNELING_CONTROL, val);
+ err = drm_dp_dpcd_write_byte(aux, DP_CEC_TUNNELING_CONTROL, val);
return (enable && err < 0) ? err : 0;
}
@@ -112,7 +112,7 @@ static int drm_dp_cec_adap_log_addr(struct cec_adapter
*adap, u8 addr)
la_mask |= adap->log_addrs.log_addr_mask | (1 << addr);
mask[0] = la_mask & 0xff;
mask[1] = la_mask >> 8;
- err = drm_dp_dpcd_write(aux, DP_CEC_LOGICAL_ADDRESS_MASK, mask, 2);
+ err = drm_dp_dpcd_write_data(aux, DP_CEC_LOGICAL_ADDRESS_MASK, mask, 2);
return (addr != CEC_LOG_ADDR_INVALID && err < 0) ? err : 0;
}
@@ -123,15 +123,14 @@ static int drm_dp_cec_adap_transmit(struct cec_adapter
*adap, u8 attempts,
unsigned int retries = min(5, attempts - 1);
ssize_t err;
- err = drm_dp_dpcd_write(aux, DP_CEC_TX_MESSAGE_BUFFER,
- msg->msg, msg->len);
+ err = drm_dp_dpcd_write_data(aux, DP_CEC_TX_MESSAGE_BUFFER,
+msg->msg, msg->len);
if (err < 0)
return err;
- err = drm_dp_dpcd_writeb(aux, DP_CEC_TX_MESSAGE_INFO,
-(msg->len - 1) | (retries << 4) |
-DP_CEC_TX_MESSAGE_SEND);
- return err < 0 ? err : 0;
+ return drm_dp_dpcd_write_byte(aux, DP_CEC_TX_MESSAGE_INFO,
+ (msg->len - 1) | (retries << 4) |
+ DP_CEC_TX_MESSAGE_SEND);
}
static int drm_dp_cec_adap_monitor_all_enable(struct cec_adapter *adap,
@@ -144,13 +143,13 @@ static int drm_dp_cec_adap_monitor_all_enable(struct
cec_adapter *adap,
if (!(adap->capabilities & CEC_CAP_MONITOR_ALL))
return 0;
- err = drm_dp_dpcd_readb(aux, DP_CEC_TUNNELING_CONTROL, &val);
- if (err >= 0) {
+ err = drm_dp_dpcd_read_byte(aux, DP_CEC_TUNNELING_CONTROL, &val);
+ if (!err) {
if (enable)
val |= DP_CEC_SNOOPING_ENABLE;
else
val &= ~DP_CEC_SNOOPING_ENABLE;
- err = drm_dp_dpcd_writeb(aux, DP_CEC_TUNNELING_CONTROL, val);
+ err = drm_dp_dpcd_write_byte(aux, DP_CEC_TUNNELING_CONTROL,
val);
}
return (enable && err < 0) ? err : 0;
}
@@ -194,7 +193,7 @@ static int drm_dp_cec_received(struct drm_dp_aux *aux)
u8 rx_msg_info;
ssize_t err;
- err = drm_dp_dpcd_readb(aux, DP_CEC_RX_MESSAGE_INFO, &rx_msg_info);
+ err = drm_dp_dpcd_read_byte(aux, DP_CEC_RX_MESSAGE_INFO, &rx_msg_info);
if (err < 0)
return err;
@@ -202,7 +201,7 @@ static int drm_dp_cec_received(struct drm_dp_aux *aux)
return 0;
msg.len = (rx_msg_info & DP_CEC_RX_MESSAGE_LEN_MASK) + 1;
- err = drm_dp_dpcd_read(aux, DP_CEC_RX_MESSAGE_BUFFER, msg.msg, msg.len);
+ err = drm_dp_dpcd_read_data(aux, DP_CEC_RX_MESSAGE_BUFFER, msg.msg,
msg.len);
if (err < 0)
return err;
@@ -215,7 +214,7 @@ static void drm_dp_cec_handle_irq(struct drm_dp_aux *aux)
struct cec_adapter *adap = aux->cec.adap;
u8 flags;
- if (drm_dp_dpcd_readb(aux, DP_CEC_TUNNELING_IRQ_FLAGS, &flags) < 0)
+ if (drm_dp_dpcd_read_byte(aux, DP_CEC_TUNNELING_IRQ_FLAGS, &flags) < 0)
return;
if (flags & DP_CEC_RX_MESSAGE_INFO_VALID)
@@ -230,7 +229,7 @@ static void drm_dp_cec_handle_irq(struct drm_dp_aux *aux)
(DP_CEC_TX_ADDRESS_NACK_ERROR | DP_CEC_TX_DATA_NACK_ERROR))
cec_transmit_attempt_done(adap, CEC_TX_STATUS_NACK |
CEC_TX_STATUS_MAX_RETRIES);
- drm_dp_dpcd_writeb(aux, DP_CEC_TUNNELING_IRQ_FLAGS, flags);
+ drm_dp_dpcd_write_byte(aux, DP_CEC_TUNNELING_IRQ_FLAGS, flags);
}
/**
@@ -253,13 +252,13 @@ void drm_dp_cec_irq(struct drm_dp_aux *aux)
if (!aux->cec.adap)
goto unlock;
- ret = drm_dp_dpcd_readb(aux, DP_DEVICE_SERVICE_IRQ_VECTOR_ESI1,
- &cec_irq);
+ ret = drm_dp_dpcd_read_byte(aux, DP_DEVICE_SERVICE_IRQ_VECTOR_ESI1,
+
[PATCH RFC v3 4/7] drm/display: dp-aux-dev: use new DCPD access helpers
From: Dmitry Baryshkov
Switch drm_dp_aux_dev.c to use new set of DPCD read / write helpers.
Acked-by: Jani Nikula
Signed-off-by: Dmitry Baryshkov
---
drivers/gpu/drm/display/drm_dp_aux_dev.c | 12 +---
1 file changed, 5 insertions(+), 7 deletions(-)
diff --git a/drivers/gpu/drm/display/drm_dp_aux_dev.c
b/drivers/gpu/drm/display/drm_dp_aux_dev.c
index
29555b9f03c8c42681c17c4a01e74a966cf8611f..a31ab3f41efb71fd5f936c24ba5c3b8ebea68a5e
100644
--- a/drivers/gpu/drm/display/drm_dp_aux_dev.c
+++ b/drivers/gpu/drm/display/drm_dp_aux_dev.c
@@ -163,17 +163,16 @@ static ssize_t auxdev_read_iter(struct kiocb *iocb,
struct iov_iter *to)
break;
}
- res = drm_dp_dpcd_read(aux_dev->aux, pos, buf, todo);
-
+ res = drm_dp_dpcd_read_data(aux_dev->aux, pos, buf, todo);
if (res <= 0)
break;
- if (copy_to_iter(buf, res, to) != res) {
+ if (copy_to_iter(buf, todo, to) != todo) {
res = -EFAULT;
break;
}
- pos += res;
+ pos += todo;
}
if (pos != iocb->ki_pos)
@@ -211,12 +210,11 @@ static ssize_t auxdev_write_iter(struct kiocb *iocb,
struct iov_iter *from)
break;
}
- res = drm_dp_dpcd_write(aux_dev->aux, pos, buf, todo);
-
+ res = drm_dp_dpcd_write_data(aux_dev->aux, pos, buf, todo);
if (res <= 0)
break;
- pos += res;
+ pos += todo;
}
if (pos != iocb->ki_pos)
--
2.39.5
[PATCH v5 5/7] test_bits: add tests for __GENMASK() and __GENMASK_ULL()
From: Vincent Mailhol
The definitions of GENMASK() and GENMASK_ULL() do not depend any more
on __GENMASK() and __GENMASK_ULL(). Duplicate the existing unit tests
so that __GENMASK{,ULL}() is still covered.
Signed-off-by: Vincent Mailhol
---
lib/test_bits.c | 18 ++
1 file changed, 18 insertions(+)
diff --git a/lib/test_bits.c b/lib/test_bits.c
index
c7b38d91e1f16d42b7ca92e62fbd6c19b37e76a0..dc93ded9fdb201e0d44b3c1cd71e233fd62258a5
100644
--- a/lib/test_bits.c
+++ b/lib/test_bits.c
@@ -7,6 +7,22 @@
#include
+static void __genmask_test(struct kunit *test)
+{
+ KUNIT_EXPECT_EQ(test, 1ul, __GENMASK(0, 0));
+ KUNIT_EXPECT_EQ(test, 3ul, __GENMASK(1, 0));
+ KUNIT_EXPECT_EQ(test, 6ul, __GENMASK(2, 1));
+ KUNIT_EXPECT_EQ(test, 0xul, __GENMASK(31, 0));
+}
+
+static void __genmask_ull_test(struct kunit *test)
+{
+ KUNIT_EXPECT_EQ(test, 1ull, __GENMASK_ULL(0, 0));
+ KUNIT_EXPECT_EQ(test, 3ull, __GENMASK_ULL(1, 0));
+ KUNIT_EXPECT_EQ(test, 0x00e0ull, __GENMASK_ULL(39, 21));
+ KUNIT_EXPECT_EQ(test, 0xull, __GENMASK_ULL(63, 0));
+}
+
static void genmask_test(struct kunit *test)
{
KUNIT_EXPECT_EQ(test, 1ul, GENMASK(0, 0));
@@ -93,6 +109,8 @@ static void genmask_input_check_test(struct kunit *test)
static struct kunit_case bits_test_cases[] = {
+ KUNIT_CASE(__genmask_test),
+ KUNIT_CASE(__genmask_ull_test),
KUNIT_CASE(genmask_test),
KUNIT_CASE(genmask_ull_test),
KUNIT_CASE(genmask_u128_test),
--
2.45.3
[PATCH v5 2/7] bits: introduce fixed-type genmasks
From: Yury Norov Add GENMASK_TYPE() which generalizes __GENMASK() to support different types, and implement fixed-types versions of GENMASK() based on it. The fixed-type version allows more strict checks to the min/max values accepted, which is useful for defining registers like implemented by i915 and xe drivers with their REG_GENMASK*() macros. The strict checks rely on shift-count-overflow compiler check to fail the build if a number outside of the range allowed is passed. Example: #define FOO_MASK GENMASK_U32(33, 4) will generate a warning like: include/linux/bits.h:51:27: error: right shift count >= width of type [-Werror=shift-count-overflow] 51 | type_max(t) >> (BITS_PER_TYPE(t) - 1 - (h) | ^~ Signed-off-by: Yury Norov Signed-off-by: Lucas De Marchi Acked-by: Jani Nikula Co-developed-by: Vincent Mailhol Signed-off-by: Vincent Mailhol --- Changelog: v4 -> v5: - Rename GENMASK_t() to GENMASK_TYPE(). - Fix typo in patch description. - Use tab indentations instead of single space to separate the macro name from its body. - s/__GENMASK_U*()/GENMASK_U*()/g in the comment. - Add a tag to credit myself as Co-developer. Keep Yury as the main author. - Modify GENMASK_TYPE() to match the changes made to __GENMASK() in: https://github.com/norov/linux/commit/1e7933a575ed - Replace (t)~_ULL(0) with type_max(t). This is OK because GENMASK_TYPE() is not available in asm. - linux/const.h and asm/bitsperlong.h are not used anymore. Remove them. - Apply GENMASK_TYPE() to GENMASK_U128(). - Remove the unsigned int cast for the U8 and U16 variants. Cast to the target type instead. Do that cast directly in GENMASK_TYPE(). v3 -> v4: - The v3 is one year old. Meanwhile people started using __GENMASK() directly. So instead of generalizing __GENMASK() to support different types, add a new GENMASK_t(). - replace ~0ULL by ~_ULL(0). Otherwise, GENMASK_t() would fail in asm code. - Make GENMASK_U8() and GENMASK_U16() return an unsigned int. In v3, due to the integer promotion rules, these were returning a signed integer. By casting these to unsigned int, at least the signedness is kept. --- include/linux/bitops.h | 1 - include/linux/bits.h | 47 +++ 2 files changed, 31 insertions(+), 17 deletions(-) diff --git a/include/linux/bitops.h b/include/linux/bitops.h index c1cb53cf2f0f8662ed3e324578f74330e63f935d..9be2d50da09a417966b3d11c84092bb2f4cd0bef 100644 --- a/include/linux/bitops.h +++ b/include/linux/bitops.h @@ -8,7 +8,6 @@ #include -#define BITS_PER_TYPE(type)(sizeof(type) * BITS_PER_BYTE) #define BITS_TO_LONGS(nr) __KERNEL_DIV_ROUND_UP(nr, BITS_PER_TYPE(long)) #define BITS_TO_U64(nr)__KERNEL_DIV_ROUND_UP(nr, BITS_PER_TYPE(u64)) #define BITS_TO_U32(nr)__KERNEL_DIV_ROUND_UP(nr, BITS_PER_TYPE(u32)) diff --git a/include/linux/bits.h b/include/linux/bits.h index 4819cbe7bd48fbae796fc6005c9f92b1c93a034c..74219521a56e2639ccff7fdc899d6805ee355a0c 100644 --- a/include/linux/bits.h +++ b/include/linux/bits.h @@ -2,16 +2,15 @@ #ifndef __LINUX_BITS_H #define __LINUX_BITS_H -#include #include #include -#include #define BIT_MASK(nr) (UL(1) << ((nr) % BITS_PER_LONG)) #define BIT_WORD(nr) ((nr) / BITS_PER_LONG) #define BIT_ULL_MASK(nr) (ULL(1) << ((nr) % BITS_PER_LONG_LONG)) #define BIT_ULL_WORD(nr) ((nr) / BITS_PER_LONG_LONG) #define BITS_PER_BYTE 8 +#define BITS_PER_TYPE(type)(sizeof(type) * BITS_PER_BYTE) /* * Create a contiguous bitmask starting at bit position @l and ending at @@ -20,28 +19,44 @@ */ #if !defined(__ASSEMBLY__) +/* + * Missing asm support + * + * GENMASK_U*() depends on BITS_PER_TYPE() which relies on sizeof(), + * something not available in asm. Nethertheless, fixed width integers + * is a C concept. Assembly code can rely on the long and long long + * versions instead. + */ + #include #include +#include #define GENMASK_INPUT_CHECK(h, l) BUILD_BUG_ON_ZERO(const_true((l) > (h))) -#define GENMASK(h, l) \ - (GENMASK_INPUT_CHECK(h, l) + __GENMASK(h, l)) -#define GENMASK_ULL(h, l) \ - (GENMASK_INPUT_CHECK(h, l) + __GENMASK_ULL(h, l)) - /* - * Missing asm support + * Generate a mask for the specified type @t. Additional checks are made to + * guarantee the value returned fits in that type, relying on + * shift-count-overflow compiler check to detect incompatible arguments. + * For example, all these create build errors or warnings: * - * __GENMASK_U128() depends on _BIT128() which would not work - * in the asm code, as it shifts an 'unsigned __int128' data - * type instead of direct representation of 128 bit constants - * such as long and unsigned long. The fundamental problem is - * that a 128 bit constant w
[PATCH v5 7/7] test_bits: add tests for BIT_U*()
From: Vincent Mailhol Add some additional tests in lib/test_bits.c to cover the expected results of the fixed type BIT_U*() macros. Signed-off-by: Vincent Mailhol --- Changelog v4 -> v5: - BIT_U8()/BIT_U16() are now back to u8/u16. v3 -> v4: - New patch. --- lib/test_bits.c | 10 ++ 1 file changed, 10 insertions(+) diff --git a/lib/test_bits.c b/lib/test_bits.c index 91968227687bb11b7d1361b153c27eb851c6c1c2..72984fae7b815031bb6eb2892c772ffcc409cf78 100644 --- a/lib/test_bits.c +++ b/lib/test_bits.c @@ -9,6 +9,16 @@ #define assert_type(t, x) _Generic(x, t: x, default: 0) +static_assert(assert_type(u8, BIT_U8(0)) == 1u); +static_assert(assert_type(u16, BIT_U16(0)) == 1u); +static_assert(assert_type(u32, BIT_U32(0)) == 1u); +static_assert(assert_type(u64, BIT_U64(0)) == 1ull); + +static_assert(assert_type(u8, BIT_U8(7)) == 0x80u); +static_assert(assert_type(u16, BIT_U16(15)) == 0x8000u); +static_assert(assert_type(u32, BIT_U32(31)) == 0x8000u); +static_assert(assert_type(u64, BIT_U64(63)) == 0x8000ull); + static_assert(assert_type(unsigned long, GENMASK(31, 0)) == U32_MAX); static_assert(assert_type(unsigned long long, GENMASK_ULL(63, 0)) == U64_MAX); static_assert(assert_type(u8, GENMASK_U8(7, 0)) == U8_MAX); -- 2.45.3
[PATCH RFC v3 7/7] drm/display: dp-tunnel: use new DCPD access helpers
From: Dmitry Baryshkov
Switch drm_dp_tunnel.c to use new set of DPCD read / write helpers.
Reviewed-by: Lyude Paul
Acked-by: Jani Nikula
Signed-off-by: Dmitry Baryshkov
---
drivers/gpu/drm/display/drm_dp_tunnel.c | 20 ++--
1 file changed, 10 insertions(+), 10 deletions(-)
diff --git a/drivers/gpu/drm/display/drm_dp_tunnel.c
b/drivers/gpu/drm/display/drm_dp_tunnel.c
index
90fe07a89260e21e78f2db7f57a90602be921a11..076edf1610480275c62395334ab0536befa42f15
100644
--- a/drivers/gpu/drm/display/drm_dp_tunnel.c
+++ b/drivers/gpu/drm/display/drm_dp_tunnel.c
@@ -222,7 +222,7 @@ static int read_tunnel_regs(struct drm_dp_aux *aux, struct
drm_dp_tunnel_regs *r
while ((len = next_reg_area(&offset))) {
int address = DP_TUNNELING_BASE + offset;
- if (drm_dp_dpcd_read(aux, address, tunnel_reg_ptr(regs,
address), len) < 0)
+ if (drm_dp_dpcd_read_data(aux, address, tunnel_reg_ptr(regs,
address), len) < 0)
return -EIO;
offset += len;
@@ -913,7 +913,7 @@ static int set_bw_alloc_mode(struct drm_dp_tunnel *tunnel,
bool enable)
u8 mask = DP_DISPLAY_DRIVER_BW_ALLOCATION_MODE_ENABLE |
DP_UNMASK_BW_ALLOCATION_IRQ;
u8 val;
- if (drm_dp_dpcd_readb(tunnel->aux, DP_DPTX_BW_ALLOCATION_MODE_CONTROL,
&val) < 0)
+ if (drm_dp_dpcd_read_byte(tunnel->aux,
DP_DPTX_BW_ALLOCATION_MODE_CONTROL, &val) < 0)
goto out_err;
if (enable)
@@ -921,7 +921,7 @@ static int set_bw_alloc_mode(struct drm_dp_tunnel *tunnel,
bool enable)
else
val &= ~mask;
- if (drm_dp_dpcd_writeb(tunnel->aux, DP_DPTX_BW_ALLOCATION_MODE_CONTROL,
val) < 0)
+ if (drm_dp_dpcd_write_byte(tunnel->aux,
DP_DPTX_BW_ALLOCATION_MODE_CONTROL, val) < 0)
goto out_err;
tunnel->bw_alloc_enabled = enable;
@@ -1039,7 +1039,7 @@ static int clear_bw_req_state(struct drm_dp_aux *aux)
{
u8 bw_req_mask = DP_BW_REQUEST_SUCCEEDED | DP_BW_REQUEST_FAILED;
- if (drm_dp_dpcd_writeb(aux, DP_TUNNELING_STATUS, bw_req_mask) < 0)
+ if (drm_dp_dpcd_write_byte(aux, DP_TUNNELING_STATUS, bw_req_mask) < 0)
return -EIO;
return 0;
@@ -1052,7 +1052,7 @@ static int bw_req_complete(struct drm_dp_aux *aux, bool
*status_changed)
u8 val;
int err;
- if (drm_dp_dpcd_readb(aux, DP_TUNNELING_STATUS, &val) < 0)
+ if (drm_dp_dpcd_read_byte(aux, DP_TUNNELING_STATUS, &val) < 0)
return -EIO;
*status_changed = val & status_change_mask;
@@ -1095,7 +1095,7 @@ static int allocate_tunnel_bw(struct drm_dp_tunnel
*tunnel, int bw)
if (err)
goto out;
- if (drm_dp_dpcd_writeb(tunnel->aux, DP_REQUEST_BW, request_bw) < 0) {
+ if (drm_dp_dpcd_write_byte(tunnel->aux, DP_REQUEST_BW, request_bw) < 0)
{
err = -EIO;
goto out;
}
@@ -1196,13 +1196,13 @@ static int check_and_clear_status_change(struct
drm_dp_tunnel *tunnel)
u8 mask = DP_BW_ALLOCATION_CAPABILITY_CHANGED | DP_ESTIMATED_BW_CHANGED;
u8 val;
- if (drm_dp_dpcd_readb(tunnel->aux, DP_TUNNELING_STATUS, &val) < 0)
+ if (drm_dp_dpcd_read_byte(tunnel->aux, DP_TUNNELING_STATUS, &val) < 0)
goto out_err;
val &= mask;
if (val) {
- if (drm_dp_dpcd_writeb(tunnel->aux, DP_TUNNELING_STATUS, val) <
0)
+ if (drm_dp_dpcd_write_byte(tunnel->aux, DP_TUNNELING_STATUS,
val) < 0)
goto out_err;
return 1;
@@ -1215,7 +1215,7 @@ static int check_and_clear_status_change(struct
drm_dp_tunnel *tunnel)
* Check for estimated BW changes explicitly to account for lost
* BW change notifications.
*/
- if (drm_dp_dpcd_readb(tunnel->aux, DP_ESTIMATED_BW, &val) < 0)
+ if (drm_dp_dpcd_read_byte(tunnel->aux, DP_ESTIMATED_BW, &val) < 0)
goto out_err;
if (val * tunnel->bw_granularity != tunnel->estimated_bw)
@@ -1300,7 +1300,7 @@ int drm_dp_tunnel_handle_irq(struct drm_dp_tunnel_mgr
*mgr, struct drm_dp_aux *a
{
u8 val;
- if (drm_dp_dpcd_readb(aux, DP_TUNNELING_STATUS, &val) < 0)
+ if (drm_dp_dpcd_read_byte(aux, DP_TUNNELING_STATUS, &val) < 0)
return -EIO;
if (val & (DP_BW_REQUEST_SUCCEEDED | DP_BW_REQUEST_FAILED))
--
2.39.5
Re: [PATCH v4 3/8] bits: introduce fixed-type genmasks
On Wed, Mar 05, 2025 at 10:00:15PM +0900, Vincent Mailhol via B4 Relay wrote: > From: Yury Norov > > Add __GENMASK_t() which generalizes __GENMASK() to support different > types, and implement fixed-types versions of GENMASK() based on it. > The fixed-type version allows more strict checks to the min/max values > accepted, which is useful for defining registers like implemented by > i915 and xe drivers with their REG_GENMASK*() macros. > > The strict checks rely on shift-count-overflow compiler check to fail > the build if a number outside of the range allowed is passed. > Example: > > #define FOO_MASK GENMASK_U32(33, 4) > > will generate a warning like: > > ../include/linux/bits.h:41:31: error: left shift count >= width of type > [-Werror=shift-count-overflow] > 41 | (((t)~0ULL - ((t)(1) << (l)) + 1) & \ > | ^~ > > Signed-off-by: Yury Norov > Signed-off-by: Lucas De Marchi > Acked-by: Jani Nikula > Signed-off-by: Vincent Mailhol Co-developed-by? > --- > Changelog: > > v3 -> v4: > > - The v3 is one year old. Meanwhile people started using > __GENMASK() directly. So instead of generalizing __GENMASK() to > support different types, add a new GENMASK_t(). > > - replace ~0ULL by ~_ULL(0). Otherwise, __GENMASK_t() would fail > in asm code. > > - Make GENMASK_U8() and GENMASK_U16() return an unsigned int. In > v3, due to the integer promotion rules, these were returning a > signed integer. By casting these to unsigned int, at least the This comment will disappear when I'll apply the patch. Can you comment it in the code instead? > signedness is kept. > --- > include/linux/bitops.h | 1 - > include/linux/bits.h | 33 + > 2 files changed, 29 insertions(+), 5 deletions(-) > > diff --git a/include/linux/bitops.h b/include/linux/bitops.h > index > c1cb53cf2f0f8662ed3e324578f74330e63f935d..9be2d50da09a417966b3d11c84092bb2f4cd0bef > 100644 > --- a/include/linux/bitops.h > +++ b/include/linux/bitops.h > @@ -8,7 +8,6 @@ > > #include > > -#define BITS_PER_TYPE(type) (sizeof(type) * BITS_PER_BYTE) > #define BITS_TO_LONGS(nr)__KERNEL_DIV_ROUND_UP(nr, BITS_PER_TYPE(long)) > #define BITS_TO_U64(nr) __KERNEL_DIV_ROUND_UP(nr, > BITS_PER_TYPE(u64)) > #define BITS_TO_U32(nr) __KERNEL_DIV_ROUND_UP(nr, > BITS_PER_TYPE(u32)) > diff --git a/include/linux/bits.h b/include/linux/bits.h > index > 5f68980a1b98d771426872c74d7b5c0f79e5e802..f202e46d2f4b7899c16d975120f3fa3ae41556ae > 100644 > --- a/include/linux/bits.h > +++ b/include/linux/bits.h > @@ -12,6 +12,7 @@ > #define BIT_ULL_MASK(nr) (ULL(1) << ((nr) % BITS_PER_LONG_LONG)) > #define BIT_ULL_WORD(nr) ((nr) / BITS_PER_LONG_LONG) > #define BITS_PER_BYTE8 > +#define BITS_PER_TYPE(type) (sizeof(type) * BITS_PER_BYTE) > > /* > * Create a contiguous bitmask starting at bit position @l and ending at > @@ -25,14 +26,38 @@ > > #define GENMASK_INPUT_CHECK(h, l) BUILD_BUG_ON_ZERO(const_true((l) > (h))) > > -#define GENMASK(h, l) \ > - (GENMASK_INPUT_CHECK(h, l) + __GENMASK(h, l)) > -#define GENMASK_ULL(h, l) \ > - (GENMASK_INPUT_CHECK(h, l) + __GENMASK_ULL(h, l)) > +/* > + * Generate a mask for the specified type @t. Additional checks are made to > + * guarantee the value returned fits in that type, relying on > + * shift-count-overflow compiler check to detect incompatible arguments. > + * For example, all these create build errors or warnings: > + * > + * - GENMASK(15, 20): wrong argument order > + * - GENMASK(72, 15): doesn't fit unsigned long > + * - GENMASK_U32(33, 15): doesn't fit in a u32 > + */ > +#define GENMASK_t(t, h, l) \ Agree with Andy. This should be GENMASK_TYPE, or triple-underscored ___GENMASK() maybe. This _t thing looks misleading. > + (GENMASK_INPUT_CHECK(h, l) +\ > + (((t)~ULL(0) - ((t)1 << (l)) + 1) &\ > + ((t)~ULL(0) >> (BITS_PER_TYPE(t) - 1 - (h) Can you rebase it on top of -next? In this dev cycle I merge a patch that reverts the __GENMASK() back to: #define __GENMASK(h, l) (((~_UL(0)) << (l)) & (~_UL(0) >> (BITS_PER_LONG - 1 - (h > +#define GENMASK(h, l) GENMASK_t(unsigned long, h, l) > +#define GENMASK_ULL(h, l) GENMASK_t(unsigned long long, h, l) This makes __GENMASK() and __GENMASK_ULL() unused in the kernel, other than in uapi. Or I misunderstand it? Having, in fact, different implementations of the same macro for kernel and userspace is a source of problems. Can we move GENMASK_TYPE() to uapi, and implement __GENMASK() on top of them? If not, I'd prefer to keep GENMASK and GENMASK_ULL untouched. Can you run bloat-o-meter and ensure there's no unwanted effects on code generation? > /* > * Missing asm support > * > + * __GENMASK_U*() depends on BITS_PER_TYPE() which would not work in the asm And there
Re: [PATCH v4 4/8] bits: introduce fixed-type BIT
On 06/03/2025 at 00:48, Andy Shevchenko wrote: > On Wed, Mar 05, 2025 at 11:48:10PM +0900, Vincent Mailhol wrote: >> On 05/03/2025 at 23:33, Andy Shevchenko wrote: >>> On Wed, Mar 05, 2025 at 10:00:16PM +0900, Vincent Mailhol via B4 Relay >>> wrote: > > ... > +#define BIT_U8(b) (BIT_INPUT_CHECK(u8, b) + (unsigned int)BIT(b)) +#define BIT_U16(b) (BIT_INPUT_CHECK(u16, b) + (unsigned int)BIT(b)) >>> >>> Why not u8 and u16? This inconsistency needs to be well justified. >> >> Because of the C integer promotion rules, if casted to u8 or u16, the >> expression will immediately become a signed integer as soon as it is get >> used. For example, if casted to u8 >> >> BIT_U8(0) + BIT_U8(1) >> >> would be a signed integer. And that may surprise people. > > Yes, but wouldn't be better to put it more explicitly like > > #define BIT_U8(b) (BIT_INPUT_CHECK(u8, b) + (u8)BIT(b) + 0 + UL(0)) // + > ULL(0) ? OK, the final result would be unsigned. But, I do not follow how this is more explicit. Also, why doing: (u8)BIT(b) + 0 + UL(0) and not just: (u8)BIT(b) + UL(0) ? What is that intermediary '+ 0' for? I am sorry, but I am having a hard time understanding how casting to u8 and then doing an addition with an unsigned long is more explicit than directly doing a cast to the desired type. As I mentioned in my answer to Yuri, I have a slight preference for the unsigned int cast, but I am OK to go back to the u8/u16 cast as it was in v3. However, I really do not see how that '+ 0 + UL(0)' would be an improvement. > Also, BIT_Uxx() gives different type at the end, shouldn't they all be > promoted > to unsigned long long at the end? Probably it won't work in real assembly. > Can you add test cases which are written in assembly? (Yes, I understand that > it will > be architecture dependent, but still.) No. I purposely guarded the definition of the BIT_Uxx() by a #if !defined(__ASSEMBLY__) so that these are never visible in assembly. I actually put a comment to explain why the GENMASK_U*() are not available in assembly. I can copy paste the same comment to explain why why BIT_U*() are not made available either: /* * Missing asm support * * BIT_U*() depends on BITS_PER_TYPE() which would not work in the asm * code as BITS_PER_TYPE() relies on sizeof(), something not available * in asm. Nethertheless, the concept of fixed width integers is a C * thing which does not apply to assembly code. */ I really believe that it would be a mistake to make the GENMASK_U*() or the BIT_U*() available to assembly. >> David also pointed this in the v3: >> >> https://lore.kernel.org/intel-xe/d42dc197a15649e69d459362849a3...@acums.aculab.com/ >> >> and I agree with his comment. >> >> I explained this in the changelog below the --- cutter, but it is >> probably better to make the explanation more visible. I will add a >> comment in the code to explain this. >> +#define BIT_U32(b) (BIT_INPUT_CHECK(u32, b) + (u32)BIT(b)) +#define BIT_U64(b) (BIT_INPUT_CHECK(u64, b) + (u64)BIT_ULL(b)) > Yours sincerely, Vincent Mailhol
Re: [PATCH v5 1/7] bits: split the definition of the asm and non-asm GENMASK()
On 07/03/2025 at 04:23, David Laight wrote: > On Thu, 06 Mar 2025 20:29:52 +0900 > Vincent Mailhol via B4 Relay > wrote: > >> From: Vincent Mailhol >> >> In an upcoming change, GENMASK() and its friends will indirectly >> depend on sizeof() which is not available in asm. >> >> Instead of adding further complexity to __GENMASK() to make it work >> for both asm and non asm, just split the definition of the two >> variants. > ... >> +#else /* defined(__ASSEMBLY__) */ >> + >> +#define GENMASK(h, l) __GENMASK(h, l) >> +#define GENMASK_ULL(h, l) __GENMASK_ULL(h, l) > > What do those actually expand to now? > As I've said a few times both UL(0) and ULL(0) are just (0) for __ASSEMBLY__ > so the expansions of __GENMASK() and __GENMASK_ULL() contained the > same numeric constants. Indeed, in asm, the UL(0) and ULL(0) expands to the same thing: 0. But the two macros still expand to something different on 32 bits architectures: * __GENMASK: (((~(0)) << (l)) & (~(0) >> (32 - 1 - (h * __GENMASK_ULL: (((~(0)) << (l)) & (~(0) >> (64 - 1 - (h On 64 bits architecture these are the same. > This means they should be generating the same values. > I don't know the correct 'sizeof (int_type)' for the shift right of ~0. > My suspicion is that a 32bit assembler used 32bit signed integers and a > 64bit one 64bit signed integers (but a 32bit asm on a 64bit host might > be 64bit). > So the asm versions need to avoid the right shift and only do left shifts. > > Which probably means they need to be enirely separate from the C versions. > And then the C ones can have all the ULL() removed. In this v5, I already have the ULL() removed from the non-uapi C version. And we are left with two distinct variants: - the uapi C & asm - the non-uapi C (including fix width) For the uapi ones, I do not think we can modify it without a risk of breaking some random userland. At least, this is not a risk I will take. And if we have to keep the __GENMASK() and __GENMASK_ULL(), then I would rather just reuse these for the asm variant instead of splitting further more and finding ourselves with three variants: - the uapi C - the asm - the non-uapi C (including fix width) If __GENMASK() and __GENMASK_ULL() were not in the uapi, I would have agreed with you. If you believe that the risk of modifying the uapi GENMASK*() is low enough, then you can submit a patch. But I will definitely not touch these myself. Yours sincerely, Vincent Mailhol
Re: [PATCH v4 3/8] bits: introduce fixed-type genmasks
On 05/03/2025 at 23:30, Andy Shevchenko wrote: > On Wed, Mar 05, 2025 at 10:00:15PM +0900, Vincent Mailhol via B4 Relay wrote: >> From: Yury Norov >> >> Add __GENMASK_t() which generalizes __GENMASK() to support different > > Is it with double underscore? I do not see it. This is my mistake. In an earlier draft, it was __GENMASK_t(), meanwhile, I dropped the __ prefix but forget to update the patch description. > _t is used for typedef simple types. It's unfortunate to have it > in such a macro. Ack. > Perhaps T or TYPE will suffice. Or perhaps we want > __GENMASK_Uxx() here? If no objection, I have a preference for GENMASK_TYPE(). >> types, and implement fixed-types versions of GENMASK() based on it. >> The fixed-type version allows more strict checks to the min/max values >> accepted, which is useful for defining registers like implemented by >> i915 and xe drivers with their REG_GENMASK*() macros. >> >> The strict checks rely on shift-count-overflow compiler check to fail >> the build if a number outside of the range allowed is passed. >> Example: >> >> #define FOO_MASK GENMASK_U32(33, 4) >> >> will generate a warning like: >> >> ../include/linux/bits.h:41:31: error: left shift count >= width of type >> [-Werror=shift-count-overflow] >> 41 | (((t)~0ULL - ((t)(1) << (l)) + 1) & \ >>| ^~ > > ... > >> + * __GENMASK_U*() depends on BITS_PER_TYPE() which would not work in the asm > > Where are the double underscore variants? I see it only for U128. Same as above. The description is incorrect. I will fix this in v5. >> + * code as BITS_PER_TYPE() relies on sizeof(), something not available in >> + * asm. Nethertheless, the concept of fixed width integers is a C thing >> which >> + * does not apply to assembly code. Yours sincerely, Vincent Mailhol
[PATCH RFC v3 1/7] drm/display: dp: implement new access helpers
From: Dmitry Baryshkov
Existing DPCD access functions return an error code or the number of
bytes being read / write in case of partial access. However a lot of
drivers either (incorrectly) ignore partial access or mishandle error
codes. In other cases this results in a boilerplate code which compares
returned value with the size.
Implement new set of DPCD access helpers, which ignore partial access,
always return 0 or an error code.
Suggested-by: Jani Nikula
Acked-by: Jani Nikula
Signed-off-by: Dmitry Baryshkov
---
drivers/gpu/drm/display/drm_dp_helper.c | 4 ++
include/drm/display/drm_dp_helper.h | 92 -
2 files changed, 94 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/display/drm_dp_helper.c
b/drivers/gpu/drm/display/drm_dp_helper.c
index
dbce1c3f49691fc687fee2404b723c73d533f23d..e43a8f4a252dae22eeaae1f4ca94da064303033d
100644
--- a/drivers/gpu/drm/display/drm_dp_helper.c
+++ b/drivers/gpu/drm/display/drm_dp_helper.c
@@ -704,6 +704,8 @@ EXPORT_SYMBOL(drm_dp_dpcd_set_powered);
* function returns -EPROTO. Errors from the underlying AUX channel transfer
* function, with the exception of -EBUSY (which causes the transaction to
* be retried), are propagated to the caller.
+ *
+ * In most of the cases you want to use drm_dp_dpcd_read_data() instead.
*/
ssize_t drm_dp_dpcd_read(struct drm_dp_aux *aux, unsigned int offset,
void *buffer, size_t size)
@@ -752,6 +754,8 @@ EXPORT_SYMBOL(drm_dp_dpcd_read);
* function returns -EPROTO. Errors from the underlying AUX channel transfer
* function, with the exception of -EBUSY (which causes the transaction to
* be retried), are propagated to the caller.
+ *
+ * In most of the cases you want to use drm_dp_dpcd_write_data() instead.
*/
ssize_t drm_dp_dpcd_write(struct drm_dp_aux *aux, unsigned int offset,
void *buffer, size_t size)
diff --git a/include/drm/display/drm_dp_helper.h
b/include/drm/display/drm_dp_helper.h
index
5ae4241959f24e2c1fb581d7c7d770485d603099..c5be44d72c9a04474f6c795e03bf02bf08f5eaef
100644
--- a/include/drm/display/drm_dp_helper.h
+++ b/include/drm/display/drm_dp_helper.h
@@ -527,6 +527,64 @@ ssize_t drm_dp_dpcd_read(struct drm_dp_aux *aux, unsigned
int offset,
ssize_t drm_dp_dpcd_write(struct drm_dp_aux *aux, unsigned int offset,
void *buffer, size_t size);
+/**
+ * drm_dp_dpcd_read_data() - read a series of bytes from the DPCD
+ * @aux: DisplayPort AUX channel (SST or MST)
+ * @offset: address of the (first) register to read
+ * @buffer: buffer to store the register values
+ * @size: number of bytes in @buffer
+ *
+ * Returns zero (0) on success, or a negative error
+ * code on failure. -EIO is returned if the request was NAKed by the sink or
+ * if the retry count was exceeded. If not all bytes were transferred, this
+ * function returns -EPROTO. Errors from the underlying AUX channel transfer
+ * function, with the exception of -EBUSY (which causes the transaction to
+ * be retried), are propagated to the caller.
+ */
+static inline int drm_dp_dpcd_read_data(struct drm_dp_aux *aux,
+ unsigned int offset,
+ void *buffer, size_t size)
+{
+ int ret;
+
+ ret = drm_dp_dpcd_read(aux, offset, buffer, size);
+ if (ret < 0)
+ return ret;
+ if (ret < size)
+ return -EPROTO;
+
+ return 0;
+}
+
+/**
+ * drm_dp_dpcd_write_data() - write a series of bytes to the DPCD
+ * @aux: DisplayPort AUX channel (SST or MST)
+ * @offset: address of the (first) register to write
+ * @buffer: buffer containing the values to write
+ * @size: number of bytes in @buffer
+ *
+ * Returns zero (0) on success, or a negative error
+ * code on failure. -EIO is returned if the request was NAKed by the sink or
+ * if the retry count was exceeded. If not all bytes were transferred, this
+ * function returns -EPROTO. Errors from the underlying AUX channel transfer
+ * function, with the exception of -EBUSY (which causes the transaction to
+ * be retried), are propagated to the caller.
+ */
+static inline int drm_dp_dpcd_write_data(struct drm_dp_aux *aux,
+unsigned int offset,
+void *buffer, size_t size)
+{
+ int ret;
+
+ ret = drm_dp_dpcd_write(aux, offset, buffer, size);
+ if (ret < 0)
+ return ret;
+ if (ret < size)
+ return -EPROTO;
+
+ return 0;
+}
+
/**
* drm_dp_dpcd_readb() - read a single byte from the DPCD
* @aux: DisplayPort AUX channel
@@ -534,7 +592,8 @@ ssize_t drm_dp_dpcd_write(struct drm_dp_aux *aux, unsigned
int offset,
* @valuep: location where the value of the register will be stored
*
* Returns the number of bytes transferred (1) on success, or a negative
- * error code on failure.
+ * error code on failure. In most of the cases yo
[PATCH v5 3/7] bits: introduce fixed-type BIT_U*()
From: Lucas De Marchi Implement fixed-type BIT_U*() to help drivers add stricter checks, like was done for GENMASK_U*(). Signed-off-by: Lucas De Marchi Acked-by: Jani Nikula Co-developed-by: Vincent Mailhol Signed-off-by: Vincent Mailhol --- Changelog: v4 -> v5: - Rename GENMASK_t() to GENMASK_TYPE(). - Use tab indentations instead of single space to separate the macro name from its body. - Add a global comment at the beginning of the file to explain why GENMASK_U*() and BIT_U*() are not available in asm. - Add a new BIT_TYPE() helper function, similar to GENMASK_TYPE(). - Remove the unsigned int cast for the U8 and U16 variants. Move the cast to BIT_TYPE(). - Rename the argument from BIT_U*(b) to BIT_U=(nr) for consistency with vdso/bits.h. v3 -> v4: - Use const_true() to simplify BIT_INPUT_CHECK(). - Make BIT_U8() and BIT_U16() return an unsigned int instead of a u8 and u16. Because of the integer promotion rules in C, an u8 or an u16 would become a signed integer as soon as these are used in any expression. By casting these to unsigned ints, at least the signedness is kept. - Put the cast next to the BIT() macro. - In BIT_U64(): use BIT_ULL() instead of BIT(). --- include/linux/bits.h | 26 ++ 1 file changed, 22 insertions(+), 4 deletions(-) diff --git a/include/linux/bits.h b/include/linux/bits.h index 74219521a56e2639ccff7fdc899d6805ee355a0c..f95e7815cb18636cc47ac17ef66d1bd6668e6819 100644 --- a/include/linux/bits.h +++ b/include/linux/bits.h @@ -22,10 +22,10 @@ /* * Missing asm support * - * GENMASK_U*() depends on BITS_PER_TYPE() which relies on sizeof(), - * something not available in asm. Nethertheless, fixed width integers - * is a C concept. Assembly code can rely on the long and long long - * versions instead. + * GENMASK_U*() and BIT_U*() depend on BITS_PER_TYPE() which relies on + * sizeof(), something not available in asm. Nethertheless, fixed + * width integers is a C concept. Assembly code can rely on the long + * and long long versions instead. */ #include @@ -58,6 +58,24 @@ #define GENMASK_U64(h, l) GENMASK_TYPE(u64, h, l) #define GENMASK_U128(h, l) GENMASK_TYPE(u128, h, l) +/* + * Fixed-type variants of BIT(), with additional checks like GENMASK_TYPE(). The + * following examples generate compiler warnings due to shift-count-overflow: + * + * - BIT_U8(8) + * - BIT_U32(-1) + * - BIT_U32(40) + */ +#define BIT_INPUT_CHECK(type, nr) \ + BUILD_BUG_ON_ZERO(const_true((nr) >= BITS_PER_TYPE(type))) + +#define BIT_TYPE(type, nr) ((type)(BIT_INPUT_CHECK(type, nr) + BIT_ULL(nr))) + +#define BIT_U8(nr) BIT_TYPE(u8, nr) +#define BIT_U16(nr)BIT_TYPE(u16, nr) +#define BIT_U32(nr)BIT_TYPE(u32, nr) +#define BIT_U64(nr)BIT_TYPE(u64, nr) + #else /* defined(__ASSEMBLY__) */ #define GENMASK(h, l) __GENMASK(h, l) -- 2.45.3
Re: [PATCH v4 3/8] bits: introduce fixed-type genmasks
On 06/03/2025 at 00:47, Yury Norov wrote: > On Wed, Mar 05, 2025 at 10:00:15PM +0900, Vincent Mailhol via B4 Relay wrote: >> From: Yury Norov >> >> Add __GENMASK_t() which generalizes __GENMASK() to support different >> types, and implement fixed-types versions of GENMASK() based on it. >> The fixed-type version allows more strict checks to the min/max values >> accepted, which is useful for defining registers like implemented by >> i915 and xe drivers with their REG_GENMASK*() macros. >> >> The strict checks rely on shift-count-overflow compiler check to fail >> the build if a number outside of the range allowed is passed. >> Example: >> >> #define FOO_MASK GENMASK_U32(33, 4) >> >> will generate a warning like: >> >> ../include/linux/bits.h:41:31: error: left shift count >= width of type >> [-Werror=shift-count-overflow] >> 41 | (((t)~0ULL - ((t)(1) << (l)) + 1) & \ >>| ^~ >> >> Signed-off-by: Yury Norov >> Signed-off-by: Lucas De Marchi >> Acked-by: Jani Nikula >> Signed-off-by: Vincent Mailhol > > Co-developed-by? OK. I will keep you as the main author and credit me as Co-developer. >> --- >> Changelog: >> >> v3 -> v4: >> >> - The v3 is one year old. Meanwhile people started using >> __GENMASK() directly. So instead of generalizing __GENMASK() to >> support different types, add a new GENMASK_t(). >> >> - replace ~0ULL by ~_ULL(0). Otherwise, __GENMASK_t() would fail >> in asm code. >> >> - Make GENMASK_U8() and GENMASK_U16() return an unsigned int. In >> v3, due to the integer promotion rules, these were returning a >> signed integer. By casting these to unsigned int, at least the > > This comment will disappear when I'll apply the patch. Can you comment > it in the code instead? Ack. I will add below comment in the code: /* * Because of the C integer promotion rules, the U8 and the U16 * variants would immediately become signed integers when used in * expressions. Cast them to unsigned int so that, at least, the * signedness is preserved. */ (unless if you prefer to go back to the u8 and u16 casts, c.f. below). >> signedness is kept. >> --- >> include/linux/bitops.h | 1 - >> include/linux/bits.h | 33 + >> 2 files changed, 29 insertions(+), 5 deletions(-) >> >> diff --git a/include/linux/bitops.h b/include/linux/bitops.h >> index >> c1cb53cf2f0f8662ed3e324578f74330e63f935d..9be2d50da09a417966b3d11c84092bb2f4cd0bef >> 100644 >> --- a/include/linux/bitops.h >> +++ b/include/linux/bitops.h >> @@ -8,7 +8,6 @@ >> >> #include >> >> -#define BITS_PER_TYPE(type) (sizeof(type) * BITS_PER_BYTE) >> #define BITS_TO_LONGS(nr) __KERNEL_DIV_ROUND_UP(nr, BITS_PER_TYPE(long)) >> #define BITS_TO_U64(nr) __KERNEL_DIV_ROUND_UP(nr, >> BITS_PER_TYPE(u64)) >> #define BITS_TO_U32(nr) __KERNEL_DIV_ROUND_UP(nr, >> BITS_PER_TYPE(u32)) >> diff --git a/include/linux/bits.h b/include/linux/bits.h >> index >> 5f68980a1b98d771426872c74d7b5c0f79e5e802..f202e46d2f4b7899c16d975120f3fa3ae41556ae >> 100644 >> --- a/include/linux/bits.h >> +++ b/include/linux/bits.h >> @@ -12,6 +12,7 @@ >> #define BIT_ULL_MASK(nr)(ULL(1) << ((nr) % BITS_PER_LONG_LONG)) >> #define BIT_ULL_WORD(nr)((nr) / BITS_PER_LONG_LONG) >> #define BITS_PER_BYTE 8 >> +#define BITS_PER_TYPE(type) (sizeof(type) * BITS_PER_BYTE) >> >> /* >> * Create a contiguous bitmask starting at bit position @l and ending at >> @@ -25,14 +26,38 @@ >> >> #define GENMASK_INPUT_CHECK(h, l) BUILD_BUG_ON_ZERO(const_true((l) > (h))) >> >> -#define GENMASK(h, l) \ >> -(GENMASK_INPUT_CHECK(h, l) + __GENMASK(h, l)) >> -#define GENMASK_ULL(h, l) \ >> -(GENMASK_INPUT_CHECK(h, l) + __GENMASK_ULL(h, l)) >> +/* >> + * Generate a mask for the specified type @t. Additional checks are made to >> + * guarantee the value returned fits in that type, relying on >> + * shift-count-overflow compiler check to detect incompatible arguments. >> + * For example, all these create build errors or warnings: >> + * >> + * - GENMASK(15, 20): wrong argument order >> + * - GENMASK(72, 15): doesn't fit unsigned long >> + * - GENMASK_U32(33, 15): doesn't fit in a u32 >> + */ >> +#define GENMASK_t(t, h, l) \ > > Agree with Andy. This should be GENMASK_TYPE, or triple-underscored > ___GENMASK() maybe. This _t thing looks misleading. My preference goes to GENMASK_TYPE(). >> +(GENMASK_INPUT_CHECK(h, l) +\ >> + (((t)~ULL(0) - ((t)1 << (l)) + 1) &\ >> + ((t)~ULL(0) >> (BITS_PER_TYPE(t) - 1 - (h) > > Can you rebase it on top of -next? In this dev cycle I merge a patch > that reverts the __GENMASK() back to: Oh, I did not realize that. Do you mean a rebase on top of: https://github.com/norov/linux/tree/bitmap-for-next ? I will do so. > #define __GENMASK(h, l) (((~_UL(0)) << (l)) &
[PATCH v4 2/8] bits: split the definition of the asm and non-asm GENMASK()
From: Vincent Mailhol In an upcoming change, GENMASK() and its friends will indirectly depend on sizeof() which is not available in asm. Instead of adding further complexity to __GENMASK() to make it work for both asm and non asm, just split the definition of the two variants. Signed-off-by: Vincent Mailhol --- include/linux/bits.h | 18 +- 1 file changed, 9 insertions(+), 9 deletions(-) diff --git a/include/linux/bits.h b/include/linux/bits.h index 14fd0ca9a6cd17339dd2f69e449558312a8a001b..5f68980a1b98d771426872c74d7b5c0f79e5e802 100644 --- a/include/linux/bits.h +++ b/include/linux/bits.h @@ -19,23 +19,17 @@ * GENMASK_ULL(39, 21) gives us the 64bit vector 0x00e0. */ #if !defined(__ASSEMBLY__) + #include #include + #define GENMASK_INPUT_CHECK(h, l) BUILD_BUG_ON_ZERO(const_true((l) > (h))) -#else -/* - * BUILD_BUG_ON_ZERO is not available in h files included from asm files, - * disable the input check if that is the case. - */ -#define GENMASK_INPUT_CHECK(h, l) 0 -#endif #define GENMASK(h, l) \ (GENMASK_INPUT_CHECK(h, l) + __GENMASK(h, l)) #define GENMASK_ULL(h, l) \ (GENMASK_INPUT_CHECK(h, l) + __GENMASK_ULL(h, l)) -#if !defined(__ASSEMBLY__) /* * Missing asm support * @@ -48,6 +42,12 @@ */ #define GENMASK_U128(h, l) \ (GENMASK_INPUT_CHECK(h, l) + __GENMASK_U128(h, l)) -#endif + +#else /* defined(__ASSEMBLY__) */ + +#define GENMASK(h, l) __GENMASK(h, l) +#define GENMASK_ULL(h, l) __GENMASK_ULL(h, l) + +#endif /* !defined(__ASSEMBLY__) */ #endif /* __LINUX_BITS_H */ -- 2.45.3
Re: [PATCH v5 1/7] bits: split the definition of the asm and non-asm GENMASK()
On 06/03/2025 at 23:34, Lucas De Marchi wrote: > On Thu, Mar 06, 2025 at 08:29:52PM +0900, Vincent Mailhol via B4 Relay > wrote: (...) > it seems we now have 1 inconsistency that we comment why > GENMASK_U128() is not available in asm, but we don't comment why > GENMASK_INPUT_CHECK() is not available there. Maybe move this comment on > top of GENMASK_INPUT_CHECK(). I will restore the comment in v6 and put it next to the asm definition, c.f. my reply to Andy. > Anyway, > > Reviewed-by: Lucas De Marchi Is this only valid for the first patch or for the full series? If this is for the full series, would you mind replying to the cover letter with your review tag? > thanks for picking up this series. You are welcome! > Lucas De Marchi (...) Yours sincerely, Vincent Mailhol
Re: Discussion: Moving away from Patchwork for Intel i915/Xe CI
On Thu, Mar 06, 2025 at 12:42:07PM +0200, Jani Nikula wrote: > Side note, I often pipe messages from my MUA (notmuch-emacs) to b4, as > it nicely parses the mails and picks up the message-id from > there. Overall it works great. However, b4 seems to err on the side of > writing color codes to pipes, and I get this as output: > > --- > [32m✓[0m [PATCH v5->v6 1/6] drm/i915/hpd: Track HPD pins instead of ports > for HPD pulse events > + Reviewed-by: Jani Nikula ([32m✓[0m > DKIM/intel.com) > [32m✓[0m [PATCH v5->v6 2/6] drm/i915/hpd: Let an HPD pin be in the disabled > state when handling missed IRQs > + Reviewed-by: Jani Nikula ([32m✓[0m > DKIM/intel.com) > [32m✓[0m [PATCH v6 3/6] drm/i915/hpd: Add support for blocking the IRQ > handling on an HPD pin > [32m✓[0m [PATCH v5->v6 4/6] drm/i915/dp: Fix link training interrupted by a > short HPD pulse > + Reviewed-by: Jani Nikula ([32m✓[0m > DKIM/intel.com) > [32m✓[0m [PATCH v6 5/6] drm/i915/dp: Queue a link check after link > training is complete > [32m✓[0m [PATCH v5->v6 6/6] drm/i915/crt: Use intel_hpd_block/unblock() > instead of intel_hpd_disable/enable() > --- > [32m✓[0m Signed: DKIM/intel.com > --- > > I haven't had the time to dig into b4 source on this, but it would be > great if it could automatically detect whether sending colors is the > right thing to do or not. Basically only emit color codes to interactive > terminals, unless forced also for pipes. Yes, it should do that automatically. Please send a bug report to to...@kernel.org and I'll work an automated switch to "simple" attestation marks when we don't have a terminal. -K
[PATCH RFC v3 6/7] drm/display: dp-mst-topology: use new DCPD access helpers
From: Dmitry Baryshkov
Switch drm_dp_mst_topology.c to use new set of DPCD read / write helpers.
Reviewed-by: Lyude Paul
Acked-by: Jani Nikula
Signed-off-by: Dmitry Baryshkov
---
drivers/gpu/drm/display/drm_dp_mst_topology.c | 105 +-
1 file changed, 51 insertions(+), 54 deletions(-)
diff --git a/drivers/gpu/drm/display/drm_dp_mst_topology.c
b/drivers/gpu/drm/display/drm_dp_mst_topology.c
index
8b68bb3fbffb04dfcbd910fd0fd78b998440d6e8..e8716e73480bdf6abbef71897d1632f69a7b8a47
100644
--- a/drivers/gpu/drm/display/drm_dp_mst_topology.c
+++ b/drivers/gpu/drm/display/drm_dp_mst_topology.c
@@ -2201,15 +2201,12 @@ static int drm_dp_check_mstb_guid(struct
drm_dp_mst_branch *mstb, guid_t *guid)
mstb->port_parent,
DP_GUID, sizeof(buf), buf);
} else {
- ret = drm_dp_dpcd_write(mstb->mgr->aux,
- DP_GUID, buf, sizeof(buf));
+ ret = drm_dp_dpcd_write_data(mstb->mgr->aux,
+DP_GUID, buf, sizeof(buf));
}
}
- if (ret < 16 && ret > 0)
- return -EPROTO;
-
- return ret == 16 ? 0 : ret;
+ return ret;
}
static void build_mst_prop_path(const struct drm_dp_mst_branch *mstb,
@@ -2744,14 +2741,13 @@ static int drm_dp_send_sideband_msg(struct
drm_dp_mst_topology_mgr *mgr,
do {
tosend = min3(mgr->max_dpcd_transaction_bytes, 16, total);
- ret = drm_dp_dpcd_write(mgr->aux, regbase + offset,
- &msg[offset],
- tosend);
- if (ret != tosend) {
- if (ret == -EIO && retries < 5) {
- retries++;
- goto retry;
- }
+ ret = drm_dp_dpcd_write_data(mgr->aux, regbase + offset,
+&msg[offset],
+tosend);
+ if (ret == -EIO && retries < 5) {
+ retries++;
+ goto retry;
+ } else if (ret < 0) {
drm_dbg_kms(mgr->dev, "failed to dpcd write %d %d\n",
tosend, ret);
return -EIO;
@@ -3624,7 +3620,7 @@ enum drm_dp_mst_mode drm_dp_read_mst_cap(struct
drm_dp_aux *aux,
if (dpcd[DP_DPCD_REV] < DP_DPCD_REV_12)
return DRM_DP_SST;
- if (drm_dp_dpcd_readb(aux, DP_MSTM_CAP, &mstm_cap) != 1)
+ if (drm_dp_dpcd_read_byte(aux, DP_MSTM_CAP, &mstm_cap) < 0)
return DRM_DP_SST;
if (mstm_cap & DP_MST_CAP)
@@ -3679,10 +3675,10 @@ int drm_dp_mst_topology_mgr_set_mst(struct
drm_dp_mst_topology_mgr *mgr, bool ms
mgr->mst_primary = mstb;
drm_dp_mst_topology_get_mstb(mgr->mst_primary);
- ret = drm_dp_dpcd_writeb(mgr->aux, DP_MSTM_CTRL,
-DP_MST_EN |
-DP_UP_REQ_EN |
-DP_UPSTREAM_IS_SRC);
+ ret = drm_dp_dpcd_write_byte(mgr->aux, DP_MSTM_CTRL,
+DP_MST_EN |
+DP_UP_REQ_EN |
+DP_UPSTREAM_IS_SRC);
if (ret < 0)
goto out_unlock;
@@ -3697,7 +3693,7 @@ int drm_dp_mst_topology_mgr_set_mst(struct
drm_dp_mst_topology_mgr *mgr, bool ms
mstb = mgr->mst_primary;
mgr->mst_primary = NULL;
/* this can fail if the device is gone */
- drm_dp_dpcd_writeb(mgr->aux, DP_MSTM_CTRL, 0);
+ drm_dp_dpcd_write_byte(mgr->aux, DP_MSTM_CTRL, 0);
ret = 0;
mgr->payload_id_table_cleared = false;
@@ -3763,8 +3759,8 @@ EXPORT_SYMBOL(drm_dp_mst_topology_queue_probe);
void drm_dp_mst_topology_mgr_suspend(struct drm_dp_mst_topology_mgr *mgr)
{
mutex_lock(&mgr->lock);
- drm_dp_dpcd_writeb(mgr->aux, DP_MSTM_CTRL,
- DP_MST_EN | DP_UPSTREAM_IS_SRC);
+ drm_dp_dpcd_write_byte(mgr->aux, DP_MSTM_CTRL,
+ DP_MST_EN | DP_UPSTREAM_IS_SRC);
mutex_unlock(&mgr->lock);
flush_work(&mgr->up_req_work);
flush_work(&mgr->work);
@@ -3813,18 +3809,18 @@ int drm_dp_mst_topology_mgr_resume(struct
drm_dp_mst_topology_mgr *mgr,
goto out_fail;
}
- ret = drm_dp_dpcd_writeb(mgr->aux, DP_MSTM_CTRL,
-DP_MST_EN |
-DP_UP_REQ_EN |
-DP_UPSTREAM_IS_SRC);
+ ret = drm_dp_dpcd_write_byte(mgr->aux, DP_MSTM_CTRL,
[PATCH v4 4/8] bits: introduce fixed-type BIT
From: Lucas De Marchi Implement fixed-type BIT to help drivers add stricter checks, like was done for GENMASK(). Signed-off-by: Lucas De Marchi Acked-by: Jani Nikula Signed-off-by: Vincent Mailhol --- Changelog: v3 -> v4: - Use const_true() to simplify BIT_INPUT_CHECK(). - Make BIT_U8() and BIT_U16() return an unsigned int instead of a u8 and u16. Because of the integer promotion rules in C, an u8 or an u16 would become a signed integer as soon as these are used in any expression. By casting these to unsigned ints, at least the signedness is kept. - Put the cast next to the BIT() macro. - In BIT_U64(): use BIT_ULL() instead of BIT(). --- include/linux/bits.h | 16 1 file changed, 16 insertions(+) diff --git a/include/linux/bits.h b/include/linux/bits.h index f202e46d2f4b7899c16d975120f3fa3ae41556ae..1b6f5262b79093a01aae6c14ead944e0e85821cc 100644 --- a/include/linux/bits.h +++ b/include/linux/bits.h @@ -68,6 +68,22 @@ #define GENMASK_U128(h, l) \ (GENMASK_INPUT_CHECK(h, l) + __GENMASK_U128(h, l)) +/* + * Fixed-type variants of BIT(), with additional checks like GENMASK_t(). The + * following examples generate compiler warnings due to shift-count-overflow: + * + * - BIT_U8(8) + * - BIT_U32(-1) + * - BIT_U32(40) + */ +#define BIT_INPUT_CHECK(type, b) \ + BUILD_BUG_ON_ZERO(const_true((b) >= BITS_PER_TYPE(type))) + +#define BIT_U8(b) (BIT_INPUT_CHECK(u8, b) + (unsigned int)BIT(b)) +#define BIT_U16(b) (BIT_INPUT_CHECK(u16, b) + (unsigned int)BIT(b)) +#define BIT_U32(b) (BIT_INPUT_CHECK(u32, b) + (u32)BIT(b)) +#define BIT_U64(b) (BIT_INPUT_CHECK(u64, b) + (u64)BIT_ULL(b)) + #else /* defined(__ASSEMBLY__) */ #define GENMASK(h, l) __GENMASK(h, l) -- 2.45.3
Re: Discussion: Moving away from Patchwork for Intel i915/Xe CI
On Wed, 2025-03-05 at 19:52 +0200, Jani Nikula wrote: > On Wed, 05 Mar 2025, "Knop, Ryszard" wrote: > > Hey everyone, > > > > Patchwork has been having lots of issues recently, dropping patches, > > being unusably slow and generally starting to become more of a pain > > than help. Over on the CI side we are also not super fond of it and we > > don't have enough resources to maintain it properly. Lucas has > > suggested using public-inbox archives directly, and with some recent > > tools like b4/lei making common ML workflows feasible without > > reinventing the wheel, we are considering setting up a bridge between > > MLs and GitHub/GitLab to instead drive CI using more modern tools. > > I am supportive of this change. > > > We have not decided whether to drop Patchwork yet - this is a thread to > > gather people's thoughts if this sounds like a good idea. > > > > The workflow would look like this: > > > > - A drm-tip mirror would be set up on GitHub/fd.o GitLab, automatically > > pulling all changes from drm-tip upstream fd.o GitLab as a secondary > > source. > > - For each new series on lore.kernel.org a bridge would create a PR by > > taking the latest mirrored drm-tip source, then applying a new series > > with `b4 shazam`. > > There's a small catch here. Patchwork is currently more clever about > handling series revisions when only some of the patches in a series are > updated by way of replying to the individual patch. For example [1][2]. > > I've been meaning to report it to upstream b4, but haven't gotten around > to it yet. But I wouldn't consider this a blocker. > > [1] https://lore.kernel.org/r/20250305114820.3523077-2-imre.d...@intel.com > [2] https://patchwork.freedesktop.org/series/145782/ > > > - That PR would then go through the normal CI flow, with CI checks > > being reported on that PR, instead of sending all the reports to the > > mailing list. > > - On the mailing list, the bridge would send an ack that a series has > > been seen and where are its results. You would no longer receive > > multiple emails with KBs of logs in your email client, but everything > > would be available from PR checks (as status checks and links to full > > logs only, no trimming and "last 1000 lines only"). > > \o/ > > > - Mirrors, PRs and checks for public mailing lists would be public, > > much like on the current public Patchwork instance. > > - Logs behind links will be stored for a few months (3-6, depends on > > traffic and how the situation evolves). GitHub Checks themselves (check > > status, shortlogs and links) have a hard retention period of 400 days. > > - Not sure about PR retention: we need a mechanism to correctly > > identify merged series somehow, then to trim these from the list. > > Expected retention time? > > With the velocity of the driver development, the test results go stale > in a matter of a week or two. I normally wouldn't merge patches older > than that without a fresh test round. > > IMO a long retention isn't necessary. At most a few months? The patches > will still stay on the list forever. > > > - Not sure about reporting on "CI finished": Maybe we could send one > > more email with a summary of checks when the entire workflow has been > > finished? > > I've previously suggested one short mail as an acknowledgement with a > URL to the results, and another mail when testing has ended one way or > another. I think it would be a good starting point. > > > On GitHub vs fd.o GitLab: I'm thinking more of GitHub here: > > > > - GitHub generally performs better with large repositories. > > - Extra fallback drm-tip source for fd.o downtime periods. > > - Bonus points: We can store public Intel CI tags directly in that > > mirror for moderate periods of time without abusing fd.o servers. > > > > Either option would work fine though, so opinions here would be > > appreciated :) > > I think eventually we will want to consider accepting contributions via > gitlab merge requests directly. > > It would also be interesting if maintainers/committers could merge the > contributions via gitlab UI already when CI applied the patches from the > mailing list and created the merge request. > > In the merge request case, they'd have to be against individual repos > that feed into drm-tip, *not* merge requests against drm-tip > directly. So for testing CI would have to recreate drm-tip the same way > as 'dim push-branch' currently does. This is doable, but perf-wise is not going to be great. We would have to checkout all trees pulled into drm/tip for each build as listed in the latest integration-manifest, replace target tree with the MR tree, then provide results from that. We'll see how this works out in practice. (It should be just `dim rebuild-tip` after pointing all the branches at the required commits?) This also means having a backup drm/tip source when fd.o is offline is out; it's patched into too many places if dim gets used. Ryszard > I don't think these are hard re
[PATCH v5 4/7] drm/i915: Convert REG_GENMASK*() to fixed-width GENMASK_U*()
From: Lucas De Marchi Now that include/linux/bits.h implements fixed-width GENMASK_U*(), use them to implement the i915/xe specific macros. Converting each driver to use the generic macros are left for later, when/if other driver-specific macros are also generalized. Signed-off-by: Lucas De Marchi Acked-by: Jani Nikula Signed-off-by: Vincent Mailhol --- Changelog: v4 -> v5: - Add braket to macro names in patch description, e.g. 'REG_GENMASK*' -> 'REG_GENMASK*()' v3 -> v4: - Remove the prefixes in macro parameters, e.g. 'REG_GENMASK(__high, __low)' -> 'REG_GENMASK(high, low)' --- drivers/gpu/drm/i915/i915_reg_defs.h | 108 --- 1 file changed, 11 insertions(+), 97 deletions(-) diff --git a/drivers/gpu/drm/i915/i915_reg_defs.h b/drivers/gpu/drm/i915/i915_reg_defs.h index e251bcc0c89f5710125bc70f07851b2cb978c89c..39e5ed9511174b8757b9201bff735fa362651b34 100644 --- a/drivers/gpu/drm/i915/i915_reg_defs.h +++ b/drivers/gpu/drm/i915/i915_reg_defs.h @@ -9,76 +9,19 @@ #include #include -/** - * REG_BIT() - Prepare a u32 bit value - * @__n: 0-based bit number - * - * Local wrapper for BIT() to force u32, with compile time checks. - * - * @return: Value with bit @__n set. - */ -#define REG_BIT(__n) \ - ((u32)(BIT(__n) + \ - BUILD_BUG_ON_ZERO(__is_constexpr(__n) && \ -((__n) < 0 || (__n) > 31 - -/** - * REG_BIT8() - Prepare a u8 bit value - * @__n: 0-based bit number - * - * Local wrapper for BIT() to force u8, with compile time checks. - * - * @return: Value with bit @__n set. - */ -#define REG_BIT8(__n) \ - ((u8)(BIT(__n) +\ - BUILD_BUG_ON_ZERO(__is_constexpr(__n) && \ -((__n) < 0 || (__n) > 7 - -/** - * REG_GENMASK() - Prepare a continuous u32 bitmask - * @__high: 0-based high bit - * @__low: 0-based low bit - * - * Local wrapper for GENMASK() to force u32, with compile time checks. - * - * @return: Continuous bitmask from @__high to @__low, inclusive. - */ -#define REG_GENMASK(__high, __low) \ - ((u32)(GENMASK(__high, __low) + \ - BUILD_BUG_ON_ZERO(__is_constexpr(__high) && \ -__is_constexpr(__low) && \ -((__low) < 0 || (__high) > 31 || (__low) > (__high) - -/** - * REG_GENMASK64() - Prepare a continuous u64 bitmask - * @__high: 0-based high bit - * @__low: 0-based low bit - * - * Local wrapper for GENMASK_ULL() to force u64, with compile time checks. - * - * @return: Continuous bitmask from @__high to @__low, inclusive. +/* + * Wrappers over the generic BIT_* and GENMASK_* implementations, + * for compatibility reasons with previous implementation */ -#define REG_GENMASK64(__high, __low) \ - ((u64)(GENMASK_ULL(__high, __low) + \ - BUILD_BUG_ON_ZERO(__is_constexpr(__high) && \ -__is_constexpr(__low) && \ -((__low) < 0 || (__high) > 63 || (__low) > (__high) +#define REG_GENMASK(high, low) GENMASK_U32(high, low) +#define REG_GENMASK64(high, low) GENMASK_U64(high, low) +#define REG_GENMASK16(high, low) GENMASK_U16(high, low) +#define REG_GENMASK8(high, low)GENMASK_U8(high, low) -/** - * REG_GENMASK8() - Prepare a continuous u8 bitmask - * @__high: 0-based high bit - * @__low: 0-based low bit - * - * Local wrapper for GENMASK() to force u8, with compile time checks. - * - * @return: Continuous bitmask from @__high to @__low, inclusive. - */ -#define REG_GENMASK8(__high, __low) \ - ((u8)(GENMASK(__high, __low) + \ - BUILD_BUG_ON_ZERO(__is_constexpr(__high) && \ -__is_constexpr(__low) && \ -((__low) < 0 || (__high) > 7 || (__low) > (__high) +#define REG_BIT(n) BIT_U32(n) +#define REG_BIT64(n) BIT_U64(n) +#define REG_BIT16(n) BIT_U16(n) +#define REG_BIT8(n)BIT_U8(n) /* * Local integer constant expression version of is_power_of_2(). @@ -143,35 +86,6 @@ */ #define REG_FIELD_GET64(__mask, __val) ((u64)FIELD_GET(__mask, __val)) -/** - * REG_BIT16() - Prepare a u16 bit value - * @__n: 0-based bit number - * - * Local wrapper for BIT() to force u16, with compile time - * checks. - * - * @return: Value with bit @__n set. - */ -#define REG_BIT16(__n)
Re: [PATCH v4 4/8] bits: introduce fixed-type BIT
On Wed, 5 Mar 2025 17:48:05 +0200 Andy Shevchenko wrote: > On Wed, Mar 05, 2025 at 11:48:10PM +0900, Vincent Mailhol wrote: > > On 05/03/2025 at 23:33, Andy Shevchenko wrote: > > > On Wed, Mar 05, 2025 at 10:00:16PM +0900, Vincent Mailhol via B4 Relay > > > wrote: > > ... > > > >> +#define BIT_U8(b) (BIT_INPUT_CHECK(u8, b) + (unsigned int)BIT(b)) > > >> +#define BIT_U16(b) (BIT_INPUT_CHECK(u16, b) + (unsigned int)BIT(b)) Why even pretend you are checking against a type - just use 8 or 16. > > > > > > Why not u8 and u16? This inconsistency needs to be well justified. What is the type of BIT(b) ? it really ought to be unsigned int (so always 32bit), but I bet it is unsigned long (possibly historically because someone was worried int might be 16 bits!) > > > > Because of the C integer promotion rules, if casted to u8 or u16, the > > expression will immediately become a signed integer as soon as it is get > > used. For example, if casted to u8 > > > > BIT_U8(0) + BIT_U8(1) > > > > would be a signed integer. And that may surprise people. They always get 'surprised' by that. I found some 'dayjob' code that was doing (byte_var << 1) >> 1 in order to get the high bit discarded. Been like that for best part of 30 years... I wasn't scared to fix it :-) > Yes, but wouldn't be better to put it more explicitly like > > #define BIT_U8(b) (BIT_INPUT_CHECK(u8, b) + (u8)BIT(b) + 0 + UL(0)) // + > ULL(0) ? I don't think you should force it to 'unsigned long'. On 64bit a comparison against a 32bit 'signed int' will sign-extend the value before making it unsigned. While that shouldn't matter here, someone might copy it. You just want to ensure that all the values are 'unsigned int', trying to return u8 or u16 isn't worth the effort. When I was doing min_unsigned() I did ((x) + 0u + 0ul + 0ull) to ensure that values would always be zero extended. But I was doing the same to both sides of the expression - and the compiler optimises away all the 'known 0' extension to 64bits. > Also, BIT_Uxx() gives different type at the end, shouldn't they all be > promoted > to unsigned long long at the end? Probably it won't work in real assembly. > Can you add test cases which are written in assembly? (Yes, I understand that > it will > be architecture dependent, but still.) There is no point doing multiple versions for asm files. The reason UL(x) and ULL(x) exist is because the assembler just has integers. Both expand to (x). There might not even be a distinction between signed and unsigned. I'm not sure you can assume that a shift right won't replicate the sign bit. Since the expression can only be valid for constants, something simple like ((2 << (hi)) - (1 << (lo)) really is the best you are going to get for GENMASK(). So just define a completely different version for asm any nuke the UL() etc for readability. David
[PATCH v5 6/7] test_bits: add tests for GENMASK_U*()
From: Lucas De Marchi
Add some additional tests in lib/test_bits.c to cover the
expected/non-expected values of the fixed-type GENMASK_U*() macros.
Also check that the result value matches the expected type. Since
those are known at build time, use static_assert() instead of normal
kunit tests.
Signed-off-by: Lucas De Marchi
Signed-off-by: Vincent Mailhol
---
Changelog:
v4 -> v5:
- Revert v4 change. GENMASK_U8()/GENMASK_U16() are now back to
u8/u16.
v3 -> v4:
- Adjust the type of GENMASK_U8()/GENMASK_U16() from u8/u16 to
unsigned int.
- Reorder the tests to match the order in which the macros are
declared in bits.h.
---
lib/test_bits.c | 19 +++
1 file changed, 19 insertions(+)
diff --git a/lib/test_bits.c b/lib/test_bits.c
index
dc93ded9fdb201e0d44b3c1cd71e233fd62258a5..91968227687bb11b7d1361b153c27eb851c6c1c2
100644
--- a/lib/test_bits.c
+++ b/lib/test_bits.c
@@ -5,7 +5,16 @@
#include
#include
+#include
+#define assert_type(t, x) _Generic(x, t: x, default: 0)
+
+static_assert(assert_type(unsigned long, GENMASK(31, 0)) == U32_MAX);
+static_assert(assert_type(unsigned long long, GENMASK_ULL(63, 0)) == U64_MAX);
+static_assert(assert_type(u8, GENMASK_U8(7, 0)) == U8_MAX);
+static_assert(assert_type(u16, GENMASK_U16(15, 0)) == U16_MAX);
+static_assert(assert_type(u32, GENMASK_U32(31, 0)) == U32_MAX);
+static_assert(assert_type(u64, GENMASK_U64(63, 0)) == U64_MAX);
static void __genmask_test(struct kunit *test)
{
@@ -30,11 +39,21 @@ static void genmask_test(struct kunit *test)
KUNIT_EXPECT_EQ(test, 6ul, GENMASK(2, 1));
KUNIT_EXPECT_EQ(test, 0xul, GENMASK(31, 0));
+ KUNIT_EXPECT_EQ(test, 1u, GENMASK_U8(0, 0));
+ KUNIT_EXPECT_EQ(test, 3u, GENMASK_U16(1, 0));
+ KUNIT_EXPECT_EQ(test, 0x1, GENMASK_U32(16, 16));
+
#ifdef TEST_GENMASK_FAILURES
/* these should fail compilation */
GENMASK(0, 1);
GENMASK(0, 10);
GENMASK(9, 10);
+
+ GENMASK_U32(0, 31);
+ GENMASK_U64(64, 0);
+ GENMASK_U32(32, 0);
+ GENMASK_U16(16, 0);
+ GENMASK_U8(8, 0);
#endif
--
2.45.3
Re: [PATCH v5 7/7] test_bits: add tests for BIT_U*()
On 06/03/2025 at 22:11, Andy Shevchenko wrote:
> On Thu, Mar 06, 2025 at 08:29:58PM +0900, Vincent Mailhol via B4 Relay wrote:
>> From: Vincent Mailhol
>>
>> Add some additional tests in lib/test_bits.c to cover the expected
>> results of the fixed type BIT_U*() macros.
>
> Still would be good to have a small assembly test case for GENMASK*() as they
> went split and it will be a good regression test in case somebody decides to
> unify both without much thinking..
Let me confirm that I correctly understood your ask. Would something
like this meet your expectations?
diff --git a/lib/test_bits.c b/lib/test_bits.c
index 72984fae7b81..869b291587e6 100644
--- a/lib/test_bits.c
+++ b/lib/test_bits.c
@@ -136,6 +136,29 @@ static void genmask_input_check_test(struct kunit
*test)
KUNIT_EXPECT_EQ(test, 0, GENMASK_INPUT_CHECK(127, 0));
}
+#undef __LINUX_BITS_H
+#undef GENMASK
+#undef GENMASK_ULL
+#define __ASSEMBLY__
+#include
+static void asm_genmask_test(struct kunit *test)
+{
+ KUNIT_EXPECT_EQ(test, 1ul, GENMASK(0, 0));
+ KUNIT_EXPECT_EQ(test, 3ul, GENMASK(1, 0));
+ KUNIT_EXPECT_EQ(test, 6ul, GENMASK(2, 1));
+ KUNIT_EXPECT_EQ(test, 0xul, GENMASK(31, 0));
+}
+
+static void asm_genmask_ull_test(struct kunit *test)
+{
+ KUNIT_EXPECT_EQ(test, 1ull, GENMASK_ULL(0, 0));
+ KUNIT_EXPECT_EQ(test, 3ull, GENMASK_ULL(1, 0));
+ KUNIT_EXPECT_EQ(test, 0x00e0ull, GENMASK_ULL(39, 21));
+ KUNIT_EXPECT_EQ(test, 0xull, GENMASK_ULL(63, 0));
+}
+#undef __ASSEMBLY__
+#undef GENMASK
+#undef GENMASK_ULL
static struct kunit_case bits_test_cases[] = {
KUNIT_CASE(__genmask_test),
@@ -144,6 +167,8 @@ static struct kunit_case bits_test_cases[] = {
KUNIT_CASE(genmask_ull_test),
KUNIT_CASE(genmask_u128_test),
KUNIT_CASE(genmask_input_check_test),
+ KUNIT_CASE(asm_genmask_test),
+ KUNIT_CASE(asm_genmask_ull_test),
{}
};
Yours sincerely,
Vincent Mailhol
