Re: [PATCH 00/10] drm/i915: PREEMPT_RT related fixups.
On 2024-04-05 16:18:18 [+0200], To intel-gfx@lists.freedesktop.org wrote: Hi, > The following patches are from the PREEMPT_RT queue. It is mostly about > disabling interrupts/preemption which leads to problems. Unfortunately … Could I please get some feedback? I didn't receive anything but automated mails from bots and I can't tell if this is a problem or not. As of -rc2 I noticed that I can drop [PATCH 06/10] drm/i915/gt: Queue and wait for the irq_work item. from the series. Sebastian
Fixes that failed to pick to v6.10-rc2
Jouni, Animesh, there are some PSR commits with Fixes: pointing at
commits in v6.9 or v6.10-rc1.
This does not apply cleanly to -rc1:
d07a578703db ("drm/i915/display: Do not print "psr: enabled" for on Panel
Replay")
This applies but does not build:
45b5853114ad ("drm/i915/psr: Get Early Transport status in
intel_psr_pipe_get_config")
This applies and builds but decided to punt because of the above:
cd43a85ec3c6 ("drm/i915/psr: Use enable boolean from intel_crtc_state for Early
Transport")
If these are important fixes to be backported to v6.10, please provide
the backports.
BR,
Jani.
--
Jani Nikula, Intel
Re: [PATCH 06/12] drm/i915: convert fsb_freq and mem_freq to kHz
On Tue, May 28, 2024 at 05:24:55PM +0300, Jani Nikula wrote:
> We'll want to use fsb frequency for deriving GT clock and rawclk
> frequencies in the future. Increase the accuracy by converting to
> kHz. Do the same for mem freq to be aligned.
mem_freq is used in:
- gen5_rps_init() -> needs to be adjusted, with care taken for rounding
- intel_gt_pm_frequency_dump() -> should probably be nuked from here
>
> Round the frequencies ending in 666 to 667.
>
> Signed-off-by: Jani Nikula
> ---
> drivers/gpu/drm/i915/display/i9xx_wm.c | 6 ++--
> drivers/gpu/drm/i915/gt/intel_rps.c| 4 +--
> drivers/gpu/drm/i915/soc/intel_dram.c | 50 +-
> 3 files changed, 30 insertions(+), 30 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/i9xx_wm.c
> b/drivers/gpu/drm/i915/display/i9xx_wm.c
> index 8b8a0f305c3a..08c5d122af8f 100644
> --- a/drivers/gpu/drm/i915/display/i9xx_wm.c
> +++ b/drivers/gpu/drm/i915/display/i9xx_wm.c
> @@ -83,14 +83,14 @@ static const struct cxsr_latency
> *pnv_get_cxsr_latency(struct drm_i915_private *
>
> if (is_desktop == latency->is_desktop &&
> i915->is_ddr3 == latency->is_ddr3 &&
> - i915->fsb_freq == latency->fsb_freq &&
> - i915->mem_freq == latency->mem_freq)
> + DIV_ROUND_CLOSEST(i915->fsb_freq, 1000) ==
> latency->fsb_freq &&
> + DIV_ROUND_CLOSEST(i915->mem_freq, 1000) ==
> latency->mem_freq)
> return latency;
> }
>
> err:
> drm_dbg_kms(&i915->drm,
> - "Could not find CxSR latency for DDR%s, FSB %u MHz, MEM %u
> MHz\n",
> + "Could not find CxSR latency for DDR%s, FSB %u kHz, MEM %u
> kHz\n",
> i915->is_ddr3 ? "3" : "2", i915->fsb_freq, i915->mem_freq);
>
> return NULL;
> diff --git a/drivers/gpu/drm/i915/gt/intel_rps.c
> b/drivers/gpu/drm/i915/gt/intel_rps.c
> index c9cb2a391942..5d3de1cddcf6 100644
> --- a/drivers/gpu/drm/i915/gt/intel_rps.c
> +++ b/drivers/gpu/drm/i915/gt/intel_rps.c
> @@ -280,9 +280,9 @@ static void gen5_rps_init(struct intel_rps *rps)
> u32 rgvmodectl;
> int c_m, i;
>
> - if (i915->fsb_freq <= 3200)
> + if (i915->fsb_freq <= 320)
> c_m = 0;
> - else if (i915->fsb_freq <= 4800)
> + else if (i915->fsb_freq <= 480)
> c_m = 1;
> else
> c_m = 2;
> diff --git a/drivers/gpu/drm/i915/soc/intel_dram.c
> b/drivers/gpu/drm/i915/soc/intel_dram.c
> index 266ed6cfa485..ace9372244a4 100644
> --- a/drivers/gpu/drm/i915/soc/intel_dram.c
> +++ b/drivers/gpu/drm/i915/soc/intel_dram.c
> @@ -56,11 +56,11 @@ static unsigned int pnv_mem_freq(struct drm_i915_private
> *dev_priv)
>
> switch (tmp & CLKCFG_MEM_MASK) {
> case CLKCFG_MEM_533:
> - return 533;
> + return 53;
> case CLKCFG_MEM_667:
> - return 667;
> + return 67;
> case CLKCFG_MEM_800:
> - return 800;
> + return 80;
> }
>
> return 0;
> @@ -73,13 +73,13 @@ static unsigned int ilk_mem_freq(struct drm_i915_private
> *dev_priv)
> ddrpll = intel_uncore_read16(&dev_priv->uncore, DDRMPLL1);
> switch (ddrpll & 0xff) {
> case 0xc:
> - return 800;
> + return 80;
> case 0x10:
> - return 1066;
> + return 107;
> case 0x14:
> - return 1333;
> + return 133;
> case 0x18:
> - return 1600;
> + return 160;
> default:
> drm_dbg(&dev_priv->drm, "unknown memory frequency 0x%02x\n",
> ddrpll & 0xff);
> @@ -97,9 +97,9 @@ static unsigned int chv_mem_freq(struct drm_i915_private
> *i915)
>
> switch ((val >> 2) & 0x7) {
> case 3:
> - return 2000;
> + return 200;
> default:
> - return 1600;
> + return 160;
> }
> }
>
> @@ -114,11 +114,11 @@ static unsigned int vlv_mem_freq(struct
> drm_i915_private *i915)
> switch ((val >> 6) & 3) {
> case 0:
> case 1:
> - return 800;
> + return 80;
> case 2:
> - return 1066;
> + return 107;
> case 3:
> - return 1333;
> + return 133;
> }
>
> return 0;
> @@ -139,7 +139,7 @@ static void detect_mem_freq(struct drm_i915_private *i915)
> i915->is_ddr3 = pnv_is_ddr3(i915);
>
> if (i915->mem_freq)
> - drm_dbg(&i915->drm, "DDR speed: %d MHz\n", i915->mem_freq);
> + drm_dbg(&i915->drm, "DDR speed: %d kHz\n", i915->mem_freq);
> }
>
> static unsigned int pnv_fsb_freq(struct drm_i915_private *i915)
> @@ -150,13 +150,13 @@ static unsigned int pnv_fsb_freq(struct
> drm_i915_private *i915)
>
> switch (fsb) {
> case CLKCFG_FSB_400:
> -
Re: Fixes that failed to pick to v6.10-rc2
On Wed, 2024-06-05 at 13:06 +0300, Jani Nikula wrote:
>
> Jouni, Animesh, there are some PSR commits with Fixes: pointing at
> commits in v6.9 or v6.10-rc1.
>
> This does not apply cleanly to -rc1:
> d07a578703db ("drm/i915/display: Do not print "psr: enabled" for on
> Panel Replay")
>
> This applies but does not build:
> 45b5853114ad ("drm/i915/psr: Get Early Transport status in
> intel_psr_pipe_get_config")
>
> This applies and builds but decided to punt because of the above:
> cd43a85ec3c6 ("drm/i915/psr: Use enable boolean from intel_crtc_state
> for Early Transport")
>
> If these are important fixes to be backported to v6.10, please
> provide
> the backports.
First patch is just for shaping debugfs interface printout. I think
that is ok to leave out.
Early transport is disabled by default currently -> should be ok to
leave out two last patches.
BR,
Jouni Högander
>
> BR,
> Jani.
>
>
Re: [PATCH 07/12] drm/i915: extend the fsb_freq initialization to more platforms
On Tue, Jun 04, 2024 at 02:46:18PM +0300, Jani Nikula wrote:
> On Thu, 30 May 2024, Jani Nikula wrote:
> > On Wed, 29 May 2024, Matt Roper wrote:
> >> On Tue, May 28, 2024 at 05:24:56PM +0300, Jani Nikula wrote:
> >>> Initialize fsb frequency for more platforms to be able to use it for GT
> >>> clock and rawclk frequency initialization.
> >>>
> >>> Note: There's a discrepancy between existing pnv_fsb_freq() and
> >>> i9xx_hrawclk() regarding CLKCFG interpretation. Presume all PNV is
> >>> mobile.
> >>
> >> Do you just mean we assume PNV always treats CLKCFG the same way mobile
> >> platforms do? Because we have both mobile and non-mobile platforms
> >> defined in the driver (pnv_m_info vs pnv_g_info) and that matches
> >> https://ark.intel.com/content/www/us/en/ark/products/codename/32201/products-formerly-pineview.html
> >> that lists both desktop and mobile.
> >
> > Yeah. The problem is, current code in intel_dram.c and intel_cdclk.c
> > interpret the CLKCFG register differently for desktop PNV. At least one
> > of them is wrong. Basically I just picked one, and secretly hoped Ville
> > would tell me. ;)
>
> Ville, do you have any idea about CLKCFG?
Acording to the datasheet PNV only really supports the 667MHz
option, so technically might not even matter. Maybe there's some
way to force it to use a different clock, but at least one "desktop"
PNV I looked at didn't have any knobs in the BIOS for this.
Anyways, based on past experience PNV always looks like a mobile
part, despite potentially being itself considered the "desktop"
variant. That interpretation also matches the existing
pnv_detect_mem_freq() implementation. So from that POV the
patch looks correct to me.
>
> BR,
> Jani.
>
>
> >
> > BR,
> > Jani.
> >
> >
> >>
> >>
> >> Matt
> >>
> >>>
> >>> FIXME: What should the default or failure mode be when the value is
> >>> unknown?
> >>>
> >>> Signed-off-by: Jani Nikula
> >>> ---
> >>> drivers/gpu/drm/i915/soc/intel_dram.c | 54 ---
> >>> 1 file changed, 40 insertions(+), 14 deletions(-)
> >>>
> >>> diff --git a/drivers/gpu/drm/i915/soc/intel_dram.c
> >>> b/drivers/gpu/drm/i915/soc/intel_dram.c
> >>> index ace9372244a4..74b5b70e91f9 100644
> >>> --- a/drivers/gpu/drm/i915/soc/intel_dram.c
> >>> +++ b/drivers/gpu/drm/i915/soc/intel_dram.c
> >>> @@ -142,24 +142,50 @@ static void detect_mem_freq(struct drm_i915_private
> >>> *i915)
> >>> drm_dbg(&i915->drm, "DDR speed: %d kHz\n", i915->mem_freq);
> >>> }
> >>>
> >>> -static unsigned int pnv_fsb_freq(struct drm_i915_private *i915)
> >>> +static unsigned int i9xx_fsb_freq(struct drm_i915_private *i915)
> >>> {
> >>> u32 fsb;
> >>>
> >>> fsb = intel_uncore_read(&i915->uncore, CLKCFG) & CLKCFG_FSB_MASK;
> >>>
> >>> - switch (fsb) {
> >>> - case CLKCFG_FSB_400:
> >>> - return 40;
> >>> - case CLKCFG_FSB_533:
> >>> - return 53;
> >>> - case CLKCFG_FSB_667:
> >>> - return 67;
> >>> - case CLKCFG_FSB_800:
> >>> - return 80;
> >>> + if (IS_PINEVIEW(i915) || IS_MOBILE(i915)) {
> >>> + switch (fsb) {
> >>> + case CLKCFG_FSB_400:
> >>> + return 40;
> >>> + case CLKCFG_FSB_533:
> >>> + return 53;
> >>> + case CLKCFG_FSB_667:
> >>> + return 67;
> >>> + case CLKCFG_FSB_800:
> >>> + return 80;
> >>> + case CLKCFG_FSB_1067:
> >>> + return 107;
> >>> + case CLKCFG_FSB_1333:
> >>> + return 133;
> >>> + default:
> >>> + MISSING_CASE(fsb);
> >>> + return 133;
> >>> + }
> >>> + } else {
> >>> + switch (fsb) {
> >>> + case CLKCFG_FSB_400_ALT:
> >>> + return 40;
> >>> + case CLKCFG_FSB_533:
> >>> + return 53;
> >>> + case CLKCFG_FSB_667:
> >>> + return 67;
> >>> + case CLKCFG_FSB_800:
> >>> + return 80;
> >>> + case CLKCFG_FSB_1067_ALT:
> >>> + return 107;
> >>> + case CLKCFG_FSB_1333_ALT:
> >>> + return 133;
> >>> + case CLKCFG_FSB_1600_ALT:
> >>> + return 160;
> >>> + default:
> >>> + return 53;
> >>> + }
> >>> }
> >>> -
> >>> - return 0;
> >>> }
> >>>
> >>> static unsigned int ilk_fsb_freq(struct drm_i915_private *dev_priv)
> >>> @@ -193,8 +219,8 @@ static void detect_fsb_freq(struct drm_i915_private
> >>> *i915)
> >>> {
> >>> if (GRAPHICS_VER(i915) == 5)
> >>> i915->fsb_freq = ilk_fsb_freq(i915);
> >>> - else if (IS_PINEVIEW(i915))
> >>> - i915->fsb_freq = pnv_fsb_freq(i915);
> >>> + else if (GRAPHICS_VER(i915) == 3 || GRAPHICS_VER(i915) == 4)
> >>> + i915->fsb_freq = i9xx_fsb_freq(i915);
> >>>
> >>> if (i915->fsb_freq)
> >>> drm_dbg(&i915->drm, "FSB frequenc
Re: [PATCH 07/12] drm/i915: extend the fsb_freq initialization to more platforms
On Tue, May 28, 2024 at 05:24:56PM +0300, Jani Nikula wrote:
> Initialize fsb frequency for more platforms to be able to use it for GT
> clock and rawclk frequency initialization.
>
> Note: There's a discrepancy between existing pnv_fsb_freq() and
> i9xx_hrawclk() regarding CLKCFG interpretation. Presume all PNV is
> mobile.
>
> FIXME: What should the default or failure mode be when the value is
> unknown?
>
> Signed-off-by: Jani Nikula
> ---
> drivers/gpu/drm/i915/soc/intel_dram.c | 54 ---
> 1 file changed, 40 insertions(+), 14 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/soc/intel_dram.c
> b/drivers/gpu/drm/i915/soc/intel_dram.c
> index ace9372244a4..74b5b70e91f9 100644
> --- a/drivers/gpu/drm/i915/soc/intel_dram.c
> +++ b/drivers/gpu/drm/i915/soc/intel_dram.c
> @@ -142,24 +142,50 @@ static void detect_mem_freq(struct drm_i915_private
> *i915)
> drm_dbg(&i915->drm, "DDR speed: %d kHz\n", i915->mem_freq);
> }
>
> -static unsigned int pnv_fsb_freq(struct drm_i915_private *i915)
> +static unsigned int i9xx_fsb_freq(struct drm_i915_private *i915)
> {
> u32 fsb;
>
> fsb = intel_uncore_read(&i915->uncore, CLKCFG) & CLKCFG_FSB_MASK;
>
> - switch (fsb) {
> - case CLKCFG_FSB_400:
> - return 40;
> - case CLKCFG_FSB_533:
> - return 53;
> - case CLKCFG_FSB_667:
> - return 67;
> - case CLKCFG_FSB_800:
> - return 80;
> + if (IS_PINEVIEW(i915) || IS_MOBILE(i915)) {
> + switch (fsb) {
> + case CLKCFG_FSB_400:
> + return 40;
> + case CLKCFG_FSB_533:
> + return 53;
> + case CLKCFG_FSB_667:
> + return 67;
> + case CLKCFG_FSB_800:
> + return 80;
> + case CLKCFG_FSB_1067:
> + return 107;
> + case CLKCFG_FSB_1333:
> + return 133;
> + default:
> + MISSING_CASE(fsb);
> + return 133;
> + }
> + } else {
> + switch (fsb) {
> + case CLKCFG_FSB_400_ALT:
> + return 40;
> + case CLKCFG_FSB_533:
> + return 53;
> + case CLKCFG_FSB_667:
> + return 67;
> + case CLKCFG_FSB_800:
> + return 80;
> + case CLKCFG_FSB_1067_ALT:
> + return 107;
> + case CLKCFG_FSB_1333_ALT:
> + return 133;
> + case CLKCFG_FSB_1600_ALT:
> + return 160;
> + default:
No MISSING_CASE() here?
> + return 53;
Why a different default value vs. the other branch?
> + }
> }
> -
> - return 0;
> }
>
> static unsigned int ilk_fsb_freq(struct drm_i915_private *dev_priv)
> @@ -193,8 +219,8 @@ static void detect_fsb_freq(struct drm_i915_private *i915)
> {
> if (GRAPHICS_VER(i915) == 5)
> i915->fsb_freq = ilk_fsb_freq(i915);
> - else if (IS_PINEVIEW(i915))
> - i915->fsb_freq = pnv_fsb_freq(i915);
> + else if (GRAPHICS_VER(i915) == 3 || GRAPHICS_VER(i915) == 4)
> + i915->fsb_freq = i9xx_fsb_freq(i915);
>
> if (i915->fsb_freq)
> drm_dbg(&i915->drm, "FSB frequency: %d kHz\n", i915->fsb_freq);
> --
> 2.39.2
--
Ville Syrjälä
Intel
[PATCH v6 00/26] Panel Replay eDP support
This patch set is implementing eDP1.5 Panel Replay for Intel hw. Patch to disable Region Early Transport by default is reverted as it is needed by eDP Panel Replay. Patches 1 - 14 are fixes and clean-ups for DP2.0 Panel Replay found while testing with eDP1.5 panel. Patches 15 - 26 are implementing Panel Replay eDP. v6: - fix and rework sink enable - rework checking vblank length for LunarLake and Panel Replay - reorder patches v5: - use psr->su_region_et_enabled instead of psr2_su_region_et_valid - do not check Vblank >= PSR2_CTL Block Count Number for Panel Replay v4: - add some patch from "Panel Replay fixes" set here - check 128b/132b encoding and HDCP enable - use intel_alpm_aux_wake_supported instead of local variable v3: - commit message modifications - s/intel_psr_psr_mode/intel_psr_print_mode/ - remove extra space from "PSR mode: disabled" - do not allow eDP Panel Replay when using 128b/132b encoding - do not allow eDP Panel Replay when HDCP is enabled v2: - printout "Selective Update enabled (Early Transport)" instead of "Selective Update Early Transport enabled" - ensure that fastset is performed when the disable bit changes Jouni Högander (26): drm/i915/alpm: Do not use fast_wake_lines for aux less wake time drm/i915/alpm: Write also AUX Less Wake lines into ALPM_CTL drm/i915/display: Take panel replay into account in vsc sdp unpacking drm/i915/display: Skip Panel Replay on pipe comparison if no active planes drm/display: Add missing Panel Replay Enable SU Region ET bit drm/i915/psr: Split enabling sink for PSR and Panel Replay drm/i915/alpm: Make alpm support checks non-static drm/i915/psr: Use intel_alpm_aux_wake_supported instead of local variable drm/i915/psr: Add Panel Replay support to intel_psr2_config_et_valid drm/i915/psr: Print Panel Replay status instead of frame lock status drm/i915/psr: Move vblank length check to separate function drm/i915/psr: Take into account SU SDP scanline indication in vblank check drm/i915/psr: Check vblank against IO buffer wake time on Lunarlake dmr/i915/psr: Wake time is aux less wake time for Panel Replay drm/i915/psr: Check panel ALPM capability for eDP Panel Replay drm/i915/psr: Inform Panel Replay source support on eDP as well drm/i915/psr: enable sink for eDP1.5 Panel Replay drm/i915/psr: Check panel Early Transport capability for eDP PR drm/i915/psr: Perfrom psr2 checks related to ALPM for Panel Replay drm/i915/psr: Add Panel Replay compute_config helper drm/i915/psr: 128b/132b Panel Replay is not supported on eDP drm/i915/psr: HW will not allow PR on eDP when HDCP enabled drm/i915/psr: Check Early Transport for Panel Replay as well drm/i915/psr: Modify dg2_activate_panel_replay to support eDP drm/i915/psr: Add new debug bit to disable Panel Replay Revert "drm/i915/psr: Disable early transport by default" drivers/gpu/drm/i915/display/intel_alpm.c | 11 +- drivers/gpu/drm/i915/display/intel_alpm.h | 2 + drivers/gpu/drm/i915/display/intel_display.c | 4 +- .../drm/i915/display/intel_display_types.h| 2 + drivers/gpu/drm/i915/display/intel_dp.c | 5 +- drivers/gpu/drm/i915/display/intel_psr.c | 309 -- include/drm/display/drm_dp.h | 1 + 7 files changed, 223 insertions(+), 111 deletions(-) -- 2.34.1
[PATCH v6 02/26] drm/i915/alpm: Write also AUX Less Wake lines into ALPM_CTL
Currently AUX Less Wake lines are not written into ALPM_CTL. Fix this.
Fixes: 1ccbf135862b ("drm/i915/psr: Enable ALPM on source side for eDP Panel
replay")
Signed-off-by: Jouni Högander
---
drivers/gpu/drm/i915/display/intel_alpm.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/display/intel_alpm.c
b/drivers/gpu/drm/i915/display/intel_alpm.c
index 52a573367976..18c1c5803670 100644
--- a/drivers/gpu/drm/i915/display/intel_alpm.c
+++ b/drivers/gpu/drm/i915/display/intel_alpm.c
@@ -323,7 +323,8 @@ static void lnl_alpm_configure(struct intel_dp *intel_dp,
(crtc_state->has_lobf &&
intel_alpm_aux_less_wake_supported(intel_dp))) {
alpm_ctl = ALPM_CTL_ALPM_ENABLE |
ALPM_CTL_ALPM_AUX_LESS_ENABLE |
- ALPM_CTL_AUX_LESS_SLEEP_HOLD_TIME_50_SYMBOLS;
+ ALPM_CTL_AUX_LESS_SLEEP_HOLD_TIME_50_SYMBOLS |
+
ALPM_CTL_AUX_LESS_WAKE_TIME(intel_dp->alpm_parameters.aux_less_wake_lines);
intel_de_write(dev_priv,
PORT_ALPM_CTL(dev_priv, cpu_transcoder),
--
2.34.1
[PATCH v6 03/26] drm/i915/display: Take panel replay into account in vsc sdp unpacking
Currently intel_dp_vsc_sdp_unpack is not taking into account Panel Replay
vsc sdp. Fix this by adding vsc sdp revision 0x6 and length 0x10 into
intel_dp_vsc_sdp_unpack
Signed-off-by: Jouni Högander
---
drivers/gpu/drm/i915/display/intel_dp.c | 5 -
1 file changed, 4 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c
b/drivers/gpu/drm/i915/display/intel_dp.c
index fd054e16850d..286119eb77f8 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -4438,7 +4438,8 @@ static int intel_dp_vsc_sdp_unpack(struct drm_dp_vsc_sdp
*vsc,
vsc->length = sdp->sdp_header.HB3;
if ((sdp->sdp_header.HB2 == 0x2 && sdp->sdp_header.HB3 == 0x8) ||
- (sdp->sdp_header.HB2 == 0x4 && sdp->sdp_header.HB3 == 0xe)) {
+ (sdp->sdp_header.HB2 == 0x4 && sdp->sdp_header.HB3 == 0xe) ||
+ (sdp->sdp_header.HB2 == 0x6 && sdp->sdp_header.HB3 == 0x10)) {
/*
* - HB2 = 0x2, HB3 = 0x8
* VSC SDP supporting 3D stereo + PSR
@@ -4446,6 +4447,8 @@ static int intel_dp_vsc_sdp_unpack(struct drm_dp_vsc_sdp
*vsc,
* VSC SDP supporting 3D stereo + PSR2 with Y-coordinate of
* first scan line of the SU region (applies to eDP v1.4b
* and higher).
+* - HB2 = 0x6, HB3 = 0x10
+* VSC SDP supporting 3D stereo + Panel Replay.
*/
return 0;
} else if (sdp->sdp_header.HB2 == 0x5 && sdp->sdp_header.HB3 == 0x13) {
--
2.34.1
[PATCH v6 01/26] drm/i915/alpm: Do not use fast_wake_lines for aux less wake time
We want to have own variables for fast wake lines and aux less wake
time. It might be needed to choose if we can enable Panel Replay Selective
Update or PSR2.
Also currently aux less wake time is overwritten by calculated fast wake
time.
v2:use less wake time in intel_alpm_lobf_compute_config
Fixes: da6a9836ac09 ("drm/i915/psr: Calculate aux less wake time")
Signed-off-by: Jouni Högander
---
drivers/gpu/drm/i915/display/intel_alpm.c | 4 ++--
drivers/gpu/drm/i915/display/intel_display_types.h | 1 +
2 files changed, 3 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_alpm.c
b/drivers/gpu/drm/i915/display/intel_alpm.c
index a26716c14aa3..52a573367976 100644
--- a/drivers/gpu/drm/i915/display/intel_alpm.c
+++ b/drivers/gpu/drm/i915/display/intel_alpm.c
@@ -159,7 +159,7 @@ static int _lnl_compute_aux_less_alpm_params(struct
intel_dp *intel_dp,
if (i915->display.params.psr_safest_params)
aux_less_wake_lines = ALPM_CTL_AUX_LESS_WAKE_TIME_MASK;
- intel_dp->alpm_parameters.fast_wake_lines = aux_less_wake_lines;
+ intel_dp->alpm_parameters.aux_less_wake_lines = aux_less_wake_lines;
intel_dp->alpm_parameters.silence_period_sym_clocks = silence_period;
intel_dp->alpm_parameters.lfps_half_cycle_num_of_syms = lfps_half_cycle;
@@ -298,7 +298,7 @@ void intel_alpm_lobf_compute_config(struct intel_dp
*intel_dp,
if (intel_alpm_aux_less_wake_supported(intel_dp))
waketime_in_lines = intel_dp->alpm_parameters.io_wake_lines;
else
- waketime_in_lines = intel_dp->alpm_parameters.fast_wake_lines;
+ waketime_in_lines =
intel_dp->alpm_parameters.aux_less_wake_lines;
crtc_state->has_lobf = (context_latency + guardband) >
(first_sdp_position + waketime_in_lines);
diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h
b/drivers/gpu/drm/i915/display/intel_display_types.h
index 77609656317b..df29ec37ef28 100644
--- a/drivers/gpu/drm/i915/display/intel_display_types.h
+++ b/drivers/gpu/drm/i915/display/intel_display_types.h
@@ -1847,6 +1847,7 @@ struct intel_dp {
/* LNL and beyond */
u8 check_entry_lines;
+ u8 aux_less_wake_lines;
u8 silence_period_sym_clocks;
u8 lfps_half_cycle_num_of_syms;
} alpm_parameters;
--
2.34.1
[PATCH v6 04/26] drm/i915/display: Skip Panel Replay on pipe comparison if no active planes
Panel Replay is not enabled if there are no active planes. Do not compare
it on pipe comparison. Otherwise we get pipe mismatch.
Fixes: ac9ef327327b ("drm/i915/psr: Panel replay has to be enabled before link
training")
Signed-off-by: Jouni Högander
---
drivers/gpu/drm/i915/display/intel_display.c | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display.c
b/drivers/gpu/drm/i915/display/intel_display.c
index 7370acdd6b8b..2747dd01bb0a 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -5331,7 +5331,9 @@ intel_pipe_config_compare(const struct intel_crtc_state
*current_config,
* Panel replay has to be enabled before link training. PSR doesn't have
* this requirement -> check these only if using panel replay
*/
- if (current_config->has_panel_replay || pipe_config->has_panel_replay) {
+ if (current_config->active_planes &&
+ (current_config->has_panel_replay ||
+pipe_config->has_panel_replay)) {
PIPE_CONF_CHECK_BOOL(has_psr);
PIPE_CONF_CHECK_BOOL(has_sel_update);
PIPE_CONF_CHECK_BOOL(enable_psr2_sel_fetch);
--
2.34.1
[PATCH v6 05/26] drm/display: Add missing Panel Replay Enable SU Region ET bit
Add missing Panel Replay Enable SU Region ET bit defined in DP2.1 specification. Signed-off-by: Jouni Högander --- include/drm/display/drm_dp.h | 1 + 1 file changed, 1 insertion(+) diff --git a/include/drm/display/drm_dp.h b/include/drm/display/drm_dp.h index f246fa03a3cb..173548c6473a 100644 --- a/include/drm/display/drm_dp.h +++ b/include/drm/display/drm_dp.h @@ -743,6 +743,7 @@ # define DP_PANEL_REPLAY_RFB_STORAGE_ERROR_EN (1 << 4) # define DP_PANEL_REPLAY_ACTIVE_FRAME_CRC_ERROR_EN (1 << 5) # define DP_PANEL_REPLAY_SU_ENABLE (1 << 6) +# define DP_PANEL_REPLAY_ENABLE_SU_REGION_ET(1 << 7) /* DP 2.1 */ #define PANEL_REPLAY_CONFIG2 0x1b1 /* eDP 1.5 */ # define DP_PANEL_REPLAY_SINK_REFRESH_RATE_UNLOCK_GRANTED (1 << 0) -- 2.34.1
[PATCH v6 06/26] drm/i915/psr: Split enabling sink for PSR and Panel Replay
Current intel_psr_enable_sink is a mess due to partly reusing PSR bit
definitions for Panel Replay. Even thought PSR and Panel Replay enable
registers do have common bits they still have also different bits and same
bits with different meaning. For sake of clarity split enabling sink to PSR
and Panel Replay specific parts.
Also fix issue caused by using psr->panel_replay_enabled to early.
Fixes: 88ae6c65ecdb ("drm/i915/psr: Unify panel replay enable/disable sink")
Signed-off-by: Jouni Högander
---
drivers/gpu/drm/i915/display/intel_psr.c | 81 +---
1 file changed, 44 insertions(+), 37 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_psr.c
b/drivers/gpu/drm/i915/display/intel_psr.c
index 4a4124a92a0d..3cc38ba2f954 100644
--- a/drivers/gpu/drm/i915/display/intel_psr.c
+++ b/drivers/gpu/drm/i915/display/intel_psr.c
@@ -686,56 +686,62 @@ static bool psr2_su_region_et_valid(struct intel_dp
*intel_dp)
return false;
}
-static unsigned int intel_psr_get_enable_sink_offset(struct intel_dp *intel_dp)
+static void _panel_replay_enable_sink(struct intel_dp *intel_dp,
+const struct intel_crtc_state *crtc_state)
{
- return intel_dp->psr.panel_replay_enabled ?
- PANEL_REPLAY_CONFIG : DP_PSR_EN_CFG;
+ u8 val = DP_PANEL_REPLAY_ENABLE |
+ DP_PANEL_REPLAY_VSC_SDP_CRC_EN |
+ DP_PANEL_REPLAY_UNRECOVERABLE_ERROR_EN |
+ DP_PANEL_REPLAY_RFB_STORAGE_ERROR_EN |
+ DP_PANEL_REPLAY_ACTIVE_FRAME_CRC_ERROR_EN;
+
+ if (crtc_state->has_sel_update)
+ val |= DP_PANEL_REPLAY_SU_ENABLE;
+
+ if (crtc_state->enable_psr2_su_region_et)
+ val |= DP_PANEL_REPLAY_ENABLE_SU_REGION_ET;
+
+ drm_dp_dpcd_writeb(&intel_dp->aux, PANEL_REPLAY_CONFIG, val);
}
-/*
- * Note: Most of the bits are same in PANEL_REPLAY_CONFIG and DP_PSR_EN_CFG. We
- * are relying on PSR definitions on these "common" bits.
- */
-void intel_psr_enable_sink(struct intel_dp *intel_dp,
- const struct intel_crtc_state *crtc_state)
+static void _psr_enable_sink(struct intel_dp *intel_dp,
+ const struct intel_crtc_state *crtc_state)
{
- struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
- u8 dpcd_val = DP_PSR_ENABLE;
+ struct drm_i915_private *i915 = dp_to_i915(intel_dp);
+ u8 val = DP_PSR_ENABLE;
if (crtc_state->has_sel_update) {
- /* Enable ALPM at sink for psr2 */
- if (!crtc_state->has_panel_replay) {
- drm_dp_dpcd_writeb(&intel_dp->aux,
- DP_RECEIVER_ALPM_CONFIG,
- DP_ALPM_ENABLE |
- DP_ALPM_LOCK_ERROR_IRQ_HPD_ENABLE);
-
- if (crtc_state->enable_psr2_su_region_et)
- dpcd_val |= DP_PSR_ENABLE_SU_REGION_ET;
- }
-
- dpcd_val |= DP_PSR_ENABLE_PSR2 | DP_PSR_IRQ_HPD_WITH_CRC_ERRORS;
+ val |= DP_PSR_ENABLE_PSR2 | DP_PSR_IRQ_HPD_WITH_CRC_ERRORS;
} else {
if (intel_dp->psr.link_standby)
- dpcd_val |= DP_PSR_MAIN_LINK_ACTIVE;
+ val |= DP_PSR_MAIN_LINK_ACTIVE;
- if (!crtc_state->has_panel_replay && DISPLAY_VER(dev_priv) >= 8)
- dpcd_val |= DP_PSR_CRC_VERIFICATION;
+ if (DISPLAY_VER(i915) >= 8)
+ val |= DP_PSR_CRC_VERIFICATION;
}
- if (crtc_state->has_panel_replay)
- dpcd_val |= DP_PANEL_REPLAY_UNRECOVERABLE_ERROR_EN |
- DP_PANEL_REPLAY_RFB_STORAGE_ERROR_EN;
-
- if (crtc_state->req_psr2_sdp_prior_scanline)
- dpcd_val |= DP_PSR_SU_REGION_SCANLINE_CAPTURE;
+ if (crtc_state->enable_psr2_su_region_et)
+ val |= DP_PANEL_REPLAY_ENABLE_SU_REGION_ET;
if (intel_dp->psr.entry_setup_frames > 0)
- dpcd_val |= DP_PSR_FRAME_CAPTURE;
+ val |= DP_PSR_FRAME_CAPTURE;
- drm_dp_dpcd_writeb(&intel_dp->aux,
- intel_psr_get_enable_sink_offset(intel_dp),
- dpcd_val);
+ drm_dp_dpcd_writeb(&intel_dp->aux, DP_PSR_EN_CFG, val);
+}
+
+void intel_psr_enable_sink(struct intel_dp *intel_dp,
+ const struct intel_crtc_state *crtc_state)
+{
+ /* Enable ALPM at sink for psr2 */
+ if (!crtc_state->has_panel_replay && crtc_state->has_sel_update)
+ drm_dp_dpcd_writeb(&intel_dp->aux,
+ DP_RECEIVER_ALPM_CONFIG,
+ DP_ALPM_ENABLE |
+ DP_ALPM_LOCK_ERROR_IRQ_HPD_ENABLE);
+
+ crtc_state->has_panel_replay ?
+ _panel_replay_enable_sink(intel_dp, crtc_state) :
+ _ps
[PATCH v6 07/26] drm/i915/alpm: Make alpm support checks non-static
We want to use intel_alpm_aux_wake_supported and
intel_alpm_aux_less_wake_supported in intel_psr.c. Convert them as
non-static.
Signed-off-by: Jouni Högander
---
drivers/gpu/drm/i915/display/intel_alpm.c | 4 ++--
drivers/gpu/drm/i915/display/intel_alpm.h | 2 ++
2 files changed, 4 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_alpm.c
b/drivers/gpu/drm/i915/display/intel_alpm.c
index 18c1c5803670..90072f6e3a33 100644
--- a/drivers/gpu/drm/i915/display/intel_alpm.c
+++ b/drivers/gpu/drm/i915/display/intel_alpm.c
@@ -11,12 +11,12 @@
#include "intel_dp_aux.h"
#include "intel_psr_regs.h"
-static bool intel_alpm_aux_wake_supported(struct intel_dp *intel_dp)
+bool intel_alpm_aux_wake_supported(struct intel_dp *intel_dp)
{
return intel_dp->alpm_dpcd & DP_ALPM_CAP;
}
-static bool intel_alpm_aux_less_wake_supported(struct intel_dp *intel_dp)
+bool intel_alpm_aux_less_wake_supported(struct intel_dp *intel_dp)
{
return intel_dp->alpm_dpcd & DP_ALPM_AUX_LESS_CAP;
}
diff --git a/drivers/gpu/drm/i915/display/intel_alpm.h
b/drivers/gpu/drm/i915/display/intel_alpm.h
index c82ecc7b4001..d4fb60393c91 100644
--- a/drivers/gpu/drm/i915/display/intel_alpm.h
+++ b/drivers/gpu/drm/i915/display/intel_alpm.h
@@ -22,4 +22,6 @@ void intel_alpm_lobf_compute_config(struct intel_dp *intel_dp,
void intel_alpm_configure(struct intel_dp *intel_dp,
const struct intel_crtc_state *crtc_state);
void intel_alpm_lobf_debugfs_add(struct intel_connector *connector);
+bool intel_alpm_aux_wake_supported(struct intel_dp *intel_dp);
+bool intel_alpm_aux_less_wake_supported(struct intel_dp *intel_dp);
#endif
--
2.34.1
[PATCH v6 08/26] drm/i915/psr: Use intel_alpm_aux_wake_supported instead of local variable
We have now intel_alpm_aux_wake_supported. Use that instead of local
variable.
Signed-off-by: Jouni Högander
---
drivers/gpu/drm/i915/display/intel_psr.c | 14 ++
1 file changed, 2 insertions(+), 12 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_psr.c
b/drivers/gpu/drm/i915/display/intel_psr.c
index 3cc38ba2f954..a3ad4488fcee 100644
--- a/drivers/gpu/drm/i915/display/intel_psr.c
+++ b/drivers/gpu/drm/i915/display/intel_psr.c
@@ -446,16 +446,6 @@ void intel_psr_irq_handler(struct intel_dp *intel_dp, u32
psr_iir)
}
}
-static bool intel_dp_get_alpm_status(struct intel_dp *intel_dp)
-{
- u8 alpm_caps = 0;
-
- if (drm_dp_dpcd_readb(&intel_dp->aux, DP_RECEIVER_ALPM_CAP,
- &alpm_caps) != 1)
- return false;
- return alpm_caps & DP_ALPM_CAP;
-}
-
static u8 intel_dp_get_sink_sync_latency(struct intel_dp *intel_dp)
{
struct drm_i915_private *i915 = dp_to_i915(intel_dp);
@@ -600,7 +590,6 @@ static void _psr_init_dpcd(struct intel_dp *intel_dp)
intel_dp->psr_dpcd[0] >= DP_PSR2_WITH_Y_COORD_IS_SUPPORTED) {
bool y_req = intel_dp->psr_dpcd[1] &
DP_PSR2_SU_Y_COORDINATE_REQUIRED;
- bool alpm = intel_dp_get_alpm_status(intel_dp);
/*
* All panels that supports PSR version 03h (PSR2 +
@@ -613,7 +602,8 @@ static void _psr_init_dpcd(struct intel_dp *intel_dp)
* Y-coordinate requirement panels we would need to enable
* GTC first.
*/
- intel_dp->psr.sink_psr2_support = y_req && alpm;
+ intel_dp->psr.sink_psr2_support = y_req &&
+ intel_alpm_aux_wake_supported(intel_dp);
drm_dbg_kms(&i915->drm, "PSR2 %ssupported\n",
intel_dp->psr.sink_psr2_support ? "" : "not ");
}
--
2.34.1
[PATCH v6 09/26] drm/i915/psr: Add Panel Replay support to intel_psr2_config_et_valid
Early Transport is possible and in our HW mandatory on eDP Panel
Replay. Add parameter to intel_psr2_config_et_valid to differentiate
validity check for Panel Replay.
Signed-off-by: Jouni Högander
---
drivers/gpu/drm/i915/display/intel_psr.c | 15 ---
1 file changed, 8 insertions(+), 7 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_psr.c
b/drivers/gpu/drm/i915/display/intel_psr.c
index a3ad4488fcee..7bdae0d0ea45 100644
--- a/drivers/gpu/drm/i915/display/intel_psr.c
+++ b/drivers/gpu/drm/i915/display/intel_psr.c
@@ -664,16 +664,17 @@ static void hsw_psr_setup_aux(struct intel_dp *intel_dp)
aux_ctl);
}
-static bool psr2_su_region_et_valid(struct intel_dp *intel_dp)
+static bool psr2_su_region_et_valid(struct intel_dp *intel_dp, bool
panel_replay)
{
struct drm_i915_private *i915 = dp_to_i915(intel_dp);
- if (DISPLAY_VER(i915) >= 20 &&
- intel_dp->psr_dpcd[0] == DP_PSR2_WITH_Y_COORD_ET_SUPPORTED &&
- !(intel_dp->psr.debug & I915_PSR_DEBUG_SU_REGION_ET_DISABLE))
- return true;
+ if (DISPLAY_VER(i915) < 20 || !intel_dp_is_edp(intel_dp) ||
+ intel_dp->psr.debug & I915_PSR_DEBUG_SU_REGION_ET_DISABLE)
+ return false;
- return false;
+ return panel_replay ?
+ intel_dp->pr_dpcd & DP_PANEL_REPLAY_EARLY_TRANSPORT_SUPPORT :
+ intel_dp->psr_dpcd[0] != DP_PSR2_WITH_Y_COORD_ET_SUPPORTED;
}
static void _panel_replay_enable_sink(struct intel_dp *intel_dp,
@@ -1351,7 +1352,7 @@ static bool intel_psr2_config_valid(struct intel_dp
*intel_dp,
tgl_dc3co_exitline_compute_config(intel_dp, crtc_state);
- if (psr2_su_region_et_valid(intel_dp))
+ if (psr2_su_region_et_valid(intel_dp, crtc_state->has_panel_replay))
crtc_state->enable_psr2_su_region_et = true;
return true;
--
2.34.1
[PATCH v6 10/26] drm/i915/psr: Print Panel Replay status instead of frame lock status
Currently Panel Replay status printout is printing frame lock status. It
should print Panel Replay status instead. Panel Replay status register
field follows PSR status register field. Use existing PSR code for that.
Fixes: ef75c25e8fed ("drm/i915/panelreplay: Debugfs support for panel replay")
Signed-off-by: Jouni Högander
---
drivers/gpu/drm/i915/display/intel_psr.c | 22 +-
1 file changed, 5 insertions(+), 17 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_psr.c
b/drivers/gpu/drm/i915/display/intel_psr.c
index 7bdae0d0ea45..3530e5f44096 100644
--- a/drivers/gpu/drm/i915/display/intel_psr.c
+++ b/drivers/gpu/drm/i915/display/intel_psr.c
@@ -3579,16 +3579,9 @@ static int i915_psr_sink_status_show(struct seq_file *m,
void *data)
"reserved",
"sink internal error",
};
- static const char * const panel_replay_status[] = {
- "Sink device frame is locked to the Source device",
- "Sink device is coasting, using the VTotal target",
- "Sink device is governing the frame rate (frame rate unlock is
granted)",
- "Sink device in the process of re-locking with the Source
device",
- };
const char *str;
int ret;
u8 status, error_status;
- u32 idx;
if (!(CAN_PSR(intel_dp) || CAN_PANEL_REPLAY(intel_dp))) {
seq_puts(m, "PSR/Panel-Replay Unsupported\n");
@@ -3602,16 +3595,11 @@ static int i915_psr_sink_status_show(struct seq_file
*m, void *data)
if (ret)
return ret;
- str = "unknown";
- if (intel_dp->psr.panel_replay_enabled) {
- idx = (status & DP_SINK_FRAME_LOCKED_MASK) >>
DP_SINK_FRAME_LOCKED_SHIFT;
- if (idx < ARRAY_SIZE(panel_replay_status))
- str = panel_replay_status[idx];
- } else if (intel_dp->psr.enabled) {
- idx = status & DP_PSR_SINK_STATE_MASK;
- if (idx < ARRAY_SIZE(sink_status))
- str = sink_status[idx];
- }
+ status &= DP_PSR_SINK_STATE_MASK;
+ if (status < ARRAY_SIZE(sink_status))
+ str = sink_status[status];
+ else
+ str = "unknown";
seq_printf(m, "Sink %s status: 0x%x [%s]\n", psr_mode_str(intel_dp),
status, str);
--
2.34.1
[PATCH v6 12/26] drm/i915/psr: Take into account SU SDP scanline indication in vblank check
SU SDP scanline indication should be taken into account when checking vblank length. In Bspec we have: PSR2_CTL[ SU SDP scanline indication ] = 0: (TRANS_VBLANK Vertical Blank End- TRANS_VBLANK Vertical Blank Start) > PSR2_CTL Block Count Number value in lines PSR2_CTL[ SU SDP scanline indication ] = 1: (TRANS_VBLANK Vertical Blank End- TRANS_VBLANK Vertical Blank Start- 1) > PSR2_CTL Block Count Number value in lines Bspec: 49274 Signed-off-by: Jouni Högander --- drivers/gpu/drm/i915/display/intel_psr.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c index 23c3fed1f983..471b60032304 100644 --- a/drivers/gpu/drm/i915/display/intel_psr.c +++ b/drivers/gpu/drm/i915/display/intel_psr.c @@ -1250,6 +1250,9 @@ static bool vblank_length_valid(struct intel_dp *intel_dp, crtc_state->hw.adjusted_mode.crtc_vblank_start; int wake_lines = psr2_block_count_lines(intel_dp); + if (crtc_state->req_psr2_sdp_prior_scanline) + vblank -= 1; + /* Vblank >= PSR2_CTL Block Count Number maximum line count */ if (vblank < wake_lines) return false; -- 2.34.1
[PATCH v6 11/26] drm/i915/psr: Move vblank length check to separate function
We are about to add more complexity to vblank length check. It makes sense
to move it to separate function for sake of clarity.
Signed-off-by: Jouni Högander
---
drivers/gpu/drm/i915/display/intel_psr.c | 18 +++---
1 file changed, 15 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_psr.c
b/drivers/gpu/drm/i915/display/intel_psr.c
index 3530e5f44096..23c3fed1f983 100644
--- a/drivers/gpu/drm/i915/display/intel_psr.c
+++ b/drivers/gpu/drm/i915/display/intel_psr.c
@@ -1243,6 +1243,20 @@ static int intel_psr_entry_setup_frames(struct intel_dp
*intel_dp,
return entry_setup_frames;
}
+static bool vblank_length_valid(struct intel_dp *intel_dp,
+ const struct intel_crtc_state *crtc_state)
+{
+ int vblank = crtc_state->hw.adjusted_mode.crtc_vblank_end -
+ crtc_state->hw.adjusted_mode.crtc_vblank_start;
+ int wake_lines = psr2_block_count_lines(intel_dp);
+
+ /* Vblank >= PSR2_CTL Block Count Number maximum line count */
+ if (vblank < wake_lines)
+ return false;
+
+ return true;
+}
+
static bool intel_psr2_config_valid(struct intel_dp *intel_dp,
struct intel_crtc_state *crtc_state)
{
@@ -1333,9 +1347,7 @@ static bool intel_psr2_config_valid(struct intel_dp
*intel_dp,
}
/* Vblank >= PSR2_CTL Block Count Number maximum line count */
- if (crtc_state->hw.adjusted_mode.crtc_vblank_end -
- crtc_state->hw.adjusted_mode.crtc_vblank_start <
- psr2_block_count_lines(intel_dp)) {
+ if (!vblank_length_valid(intel_dp, crtc_state)) {
drm_dbg_kms(&dev_priv->drm,
"PSR2 not enabled, too short vblank time\n");
return false;
--
2.34.1
[PATCH v6 13/26] drm/i915/psr: Check vblank against IO buffer wake time on Lunarlake
As Lunarlake doesn't have block count configuration vblank should be
checked against IO buffer wake time.
Bspec: 68920
Signed-off-by: Jouni Högander
---
drivers/gpu/drm/i915/display/intel_psr.c | 6 +-
1 file changed, 5 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/display/intel_psr.c
b/drivers/gpu/drm/i915/display/intel_psr.c
index 471b60032304..c9fcb25184ee 100644
--- a/drivers/gpu/drm/i915/display/intel_psr.c
+++ b/drivers/gpu/drm/i915/display/intel_psr.c
@@ -1246,9 +1246,13 @@ static int intel_psr_entry_setup_frames(struct intel_dp
*intel_dp,
static bool vblank_length_valid(struct intel_dp *intel_dp,
const struct intel_crtc_state *crtc_state)
{
+ struct drm_i915_private *i915 = dp_to_i915(intel_dp);
int vblank = crtc_state->hw.adjusted_mode.crtc_vblank_end -
crtc_state->hw.adjusted_mode.crtc_vblank_start;
- int wake_lines = psr2_block_count_lines(intel_dp);
+ int wake_lines;
+
+ wake_lines = DISPLAY_VER(i915) < 20 ? psr2_block_count_lines(intel_dp) :
+ intel_dp->alpm_parameters.io_wake_lines;
if (crtc_state->req_psr2_sdp_prior_scanline)
vblank -= 1;
--
2.34.1
[PATCH v6 14/26] dmr/i915/psr: Wake time is aux less wake time for Panel Replay
When checking vblank length used wake time is aux less wake time for eDP Panel Replay (vblank length is not checked for DP2.0 Panel Replay). Signed-off-by: Jouni Högander --- drivers/gpu/drm/i915/display/intel_psr.c | 8 ++-- 1 file changed, 6 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c index c9fcb25184ee..ccb7c022e364 100644 --- a/drivers/gpu/drm/i915/display/intel_psr.c +++ b/drivers/gpu/drm/i915/display/intel_psr.c @@ -1251,8 +1251,12 @@ static bool vblank_length_valid(struct intel_dp *intel_dp, crtc_state->hw.adjusted_mode.crtc_vblank_start; int wake_lines; - wake_lines = DISPLAY_VER(i915) < 20 ? psr2_block_count_lines(intel_dp) : - intel_dp->alpm_parameters.io_wake_lines; + if (crtc_state->has_panel_replay) + wake_lines = intel_dp->alpm_parameters.aux_less_wake_lines; + else + wake_lines = DISPLAY_VER(i915) < 20 ? + psr2_block_count_lines(intel_dp) : + intel_dp->alpm_parameters.io_wake_lines; if (crtc_state->req_psr2_sdp_prior_scanline) vblank -= 1; -- 2.34.1
[PATCH v6 15/26] drm/i915/psr: Check panel ALPM capability for eDP Panel Replay
Our HW doesn't support Panel Replay without AUX_LESS ALPM on eDP. Check
panel support for this and prevent eDP panel replay if it doesn't exits.
Bspec: 68920
v2: use intel_alpm_aux_less_wake_supported
Signed-off-by: Jouni Högander
---
drivers/gpu/drm/i915/display/intel_psr.c | 7 +++
1 file changed, 7 insertions(+)
diff --git a/drivers/gpu/drm/i915/display/intel_psr.c
b/drivers/gpu/drm/i915/display/intel_psr.c
index ccb7c022e364..839171635b97 100644
--- a/drivers/gpu/drm/i915/display/intel_psr.c
+++ b/drivers/gpu/drm/i915/display/intel_psr.c
@@ -551,6 +551,13 @@ static void _panel_replay_init_dpcd(struct intel_dp
*intel_dp)
{
struct drm_i915_private *i915 = dp_to_i915(intel_dp);
+ if (intel_dp_is_edp(intel_dp) &&
+ (!intel_alpm_aux_less_wake_supported(intel_dp))) {
+ drm_dbg_kms(&i915->drm,
+ "Panel doesn't support AUX-less ALPM, eDP Panel
Replay not possible\n");
+ return;
+ }
+
intel_dp->psr.sink_panel_replay_support = true;
if (intel_dp->pr_dpcd & DP_PANEL_REPLAY_SU_SUPPORT)
--
2.34.1
[PATCH v6 16/26] drm/i915/psr: Inform Panel Replay source support on eDP as well
Display version >= 20 support eDP 1.5. Inform Panel Replay source support on eDP for display version >= 20. Bspec: 68920 Signed-off-by: Jouni Högander --- drivers/gpu/drm/i915/display/intel_psr.c | 6 -- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c index 839171635b97..f13eb01966f5 100644 --- a/drivers/gpu/drm/i915/display/intel_psr.c +++ b/drivers/gpu/drm/i915/display/intel_psr.c @@ -3078,9 +3078,11 @@ void intel_psr_init(struct intel_dp *intel_dp) return; } - if (HAS_DP20(dev_priv) && !intel_dp_is_edp(intel_dp)) + if ((HAS_DP20(dev_priv) && !intel_dp_is_edp(intel_dp)) || + DISPLAY_VER(dev_priv) >= 20) intel_dp->psr.source_panel_replay_support = true; - else + + if (HAS_PSR(dev_priv) && intel_dp_is_edp(intel_dp)) intel_dp->psr.source_support = true; /* Disable early transport for now */ -- 2.34.1
[PATCH v6 17/26] drm/i915/psr: enable sink for eDP1.5 Panel Replay
eDP1.5 allows Panel Replay on eDP as well. Take this into account when
enabling sink PSR/Panel Replay. Write also PANEL_REPLAY_CONFIG2 register
accordingly.
v3:
- set DP_PANEL_REPLAY_CRC_VERIFICATION in PANEL_REPLAY_CONFIG2
- PANEL_REPLAY_CONFIG2 is available in DP2.1 as well
v2: do not configure ALPM for DP2.0 Panel Replay
Signed-off-by: Jouni Högander
---
drivers/gpu/drm/i915/display/intel_psr.c | 36
1 file changed, 30 insertions(+), 6 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_psr.c
b/drivers/gpu/drm/i915/display/intel_psr.c
index f13eb01966f5..171ea2a03ed6 100644
--- a/drivers/gpu/drm/i915/display/intel_psr.c
+++ b/drivers/gpu/drm/i915/display/intel_psr.c
@@ -692,6 +692,7 @@ static void _panel_replay_enable_sink(struct intel_dp
*intel_dp,
DP_PANEL_REPLAY_UNRECOVERABLE_ERROR_EN |
DP_PANEL_REPLAY_RFB_STORAGE_ERROR_EN |
DP_PANEL_REPLAY_ACTIVE_FRAME_CRC_ERROR_EN;
+ u8 panel_replay_config2 = DP_PANEL_REPLAY_CRC_VERIFICATION;
if (crtc_state->has_sel_update)
val |= DP_PANEL_REPLAY_SU_ENABLE;
@@ -699,7 +700,14 @@ static void _panel_replay_enable_sink(struct intel_dp
*intel_dp,
if (crtc_state->enable_psr2_su_region_et)
val |= DP_PANEL_REPLAY_ENABLE_SU_REGION_ET;
+ if (crtc_state->req_psr2_sdp_prior_scanline)
+ panel_replay_config2 |=
+ DP_PANEL_REPLAY_SU_REGION_SCANLINE_CAPTURE;
+
drm_dp_dpcd_writeb(&intel_dp->aux, PANEL_REPLAY_CONFIG, val);
+
+ drm_dp_dpcd_writeb(&intel_dp->aux, PANEL_REPLAY_CONFIG2,
+ panel_replay_config2);
}
static void _psr_enable_sink(struct intel_dp *intel_dp,
@@ -727,15 +735,31 @@ static void _psr_enable_sink(struct intel_dp *intel_dp,
drm_dp_dpcd_writeb(&intel_dp->aux, DP_PSR_EN_CFG, val);
}
+static void intel_psr_enable_sink_alpm(struct intel_dp *intel_dp,
+ const struct intel_crtc_state
*crtc_state)
+{
+ u8 val;
+
+ /*
+* eDP Panel Replay uses always ALPM
+* PSR2 uses ALPM but PSR1 doesn't
+*/
+ if (!intel_dp_is_edp(intel_dp) || (!crtc_state->has_panel_replay &&
+ !crtc_state->has_sel_update))
+ return;
+
+ val = DP_ALPM_ENABLE | DP_ALPM_LOCK_ERROR_IRQ_HPD_ENABLE;
+
+ if (crtc_state->has_panel_replay)
+ val |= DP_ALPM_MODE_AUX_LESS;
+
+ drm_dp_dpcd_writeb(&intel_dp->aux, DP_RECEIVER_ALPM_CONFIG, val);
+}
+
void intel_psr_enable_sink(struct intel_dp *intel_dp,
const struct intel_crtc_state *crtc_state)
{
- /* Enable ALPM at sink for psr2 */
- if (!crtc_state->has_panel_replay && crtc_state->has_sel_update)
- drm_dp_dpcd_writeb(&intel_dp->aux,
- DP_RECEIVER_ALPM_CONFIG,
- DP_ALPM_ENABLE |
- DP_ALPM_LOCK_ERROR_IRQ_HPD_ENABLE);
+ intel_psr_enable_sink_alpm(intel_dp, crtc_state);
crtc_state->has_panel_replay ?
_panel_replay_enable_sink(intel_dp, crtc_state) :
--
2.34.1
[PATCH v6 18/26] drm/i915/psr: Check panel Early Transport capability for eDP PR
Our HW doesn't support panel replay without Early Transport on eDP.
Bspec: 68920
Signed-off-by: Jouni Högander
---
drivers/gpu/drm/i915/display/intel_psr.c | 17 -
1 file changed, 12 insertions(+), 5 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_psr.c
b/drivers/gpu/drm/i915/display/intel_psr.c
index 171ea2a03ed6..bc8c822094e7 100644
--- a/drivers/gpu/drm/i915/display/intel_psr.c
+++ b/drivers/gpu/drm/i915/display/intel_psr.c
@@ -551,11 +551,18 @@ static void _panel_replay_init_dpcd(struct intel_dp
*intel_dp)
{
struct drm_i915_private *i915 = dp_to_i915(intel_dp);
- if (intel_dp_is_edp(intel_dp) &&
- (!intel_alpm_aux_less_wake_supported(intel_dp))) {
- drm_dbg_kms(&i915->drm,
- "Panel doesn't support AUX-less ALPM, eDP Panel
Replay not possible\n");
- return;
+ if (intel_dp_is_edp(intel_dp)) {
+ if (!intel_alpm_aux_less_wake_supported(intel_dp)) {
+ drm_dbg_kms(&i915->drm,
+ "Panel doesn't support AUX-less ALPM, eDP
Panel Replay not possible\n");
+ return;
+ }
+
+ if (!(intel_dp->pr_dpcd &
DP_PANEL_REPLAY_EARLY_TRANSPORT_SUPPORT)) {
+ drm_dbg_kms(&i915->drm,
+ "Panel doesn't support early transport, eDP
Panel Replay not possible\n");
+ return;
+ }
}
intel_dp->psr.sink_panel_replay_support = true;
--
2.34.1
[PATCH v6 20/26] drm/i915/psr: Add Panel Replay compute_config helper
We are about to add more checks for Panel Replay. Due to that it makes
sense to add now Panel Replay compute config helper.
Signed-off-by: Jouni Högander
---
drivers/gpu/drm/i915/display/intel_psr.c | 11 +--
1 file changed, 9 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_psr.c
b/drivers/gpu/drm/i915/display/intel_psr.c
index f8a8f98eb44e..8c881a7cad3f 100644
--- a/drivers/gpu/drm/i915/display/intel_psr.c
+++ b/drivers/gpu/drm/i915/display/intel_psr.c
@@ -1495,6 +1495,14 @@ static bool _psr_compute_config(struct intel_dp
*intel_dp,
return true;
}
+static bool _panel_replay_compute_config(struct intel_dp *intel_dp)
+{
+ if (!CAN_PANEL_REPLAY(intel_dp))
+ return false;
+
+ return true;
+}
+
void intel_psr_compute_config(struct intel_dp *intel_dp,
struct intel_crtc_state *crtc_state,
struct drm_connector_state *conn_state)
@@ -1530,8 +1538,7 @@ void intel_psr_compute_config(struct intel_dp *intel_dp,
return;
}
- if (CAN_PANEL_REPLAY(intel_dp))
- crtc_state->has_panel_replay = true;
+ crtc_state->has_panel_replay = _panel_replay_compute_config(intel_dp);
crtc_state->has_psr = crtc_state->has_panel_replay ? true :
_psr_compute_config(intel_dp, crtc_state);
--
2.34.1
[PATCH v6 24/26] drm/i915/psr: Modify dg2_activate_panel_replay to support eDP
There are couple of bits in PSR2_CTL which needs to be written in case of
eDP Panel Replay
Bspec: 68920
v2: use boolean instead of assuming eDP Panel Replay mean Early Transport
Signed-off-by: Jouni Högander
---
drivers/gpu/drm/i915/display/intel_psr.c | 13 +
1 file changed, 13 insertions(+)
diff --git a/drivers/gpu/drm/i915/display/intel_psr.c
b/drivers/gpu/drm/i915/display/intel_psr.c
index 97d1e4ef6ca5..a10d9383cc87 100644
--- a/drivers/gpu/drm/i915/display/intel_psr.c
+++ b/drivers/gpu/drm/i915/display/intel_psr.c
@@ -927,6 +927,19 @@ static u8 frames_before_su_entry(struct intel_dp *intel_dp)
static void dg2_activate_panel_replay(struct intel_dp *intel_dp)
{
struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
+ struct intel_psr *psr = &intel_dp->psr;
+ enum transcoder cpu_transcoder = intel_dp->psr.transcoder;
+
+ if (intel_dp_is_edp(intel_dp) && psr->sel_update_enabled) {
+ u32 val = psr->su_region_et_enabled ?
+ LNL_EDP_PSR2_SU_REGION_ET_ENABLE : 0;
+
+ if (intel_dp->psr.req_psr2_sdp_prior_scanline)
+ val |= EDP_PSR2_SU_SDP_SCANLINE;
+
+ intel_de_write(dev_priv, EDP_PSR2_CTL(dev_priv, cpu_transcoder),
+ val);
+ }
intel_de_rmw(dev_priv,
PSR2_MAN_TRK_CTL(dev_priv, intel_dp->psr.transcoder),
--
2.34.1
[PATCH v6 26/26] Revert "drm/i915/psr: Disable early transport by default"
This reverts commit f3c2031db7dfdf470a2d9bf3bd1efa6edfa72d8d. We want to notice possible issues faced with PSR2 Region Early Transport as early as possible -> let's revert patch disabling Region Early Transport by default. Also eDP 1.5 Panel Replay requires Early Transport. Signed-off-by: Jouni Högander --- drivers/gpu/drm/i915/display/intel_psr.c | 3 --- 1 file changed, 3 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c index b4cd7a8b17bc..36dedd8e9a9c 100644 --- a/drivers/gpu/drm/i915/display/intel_psr.c +++ b/drivers/gpu/drm/i915/display/intel_psr.c @@ -3171,9 +3171,6 @@ void intel_psr_init(struct intel_dp *intel_dp) if (HAS_PSR(dev_priv) && intel_dp_is_edp(intel_dp)) intel_dp->psr.source_support = true; - /* Disable early transport for now */ - intel_dp->psr.debug |= I915_PSR_DEBUG_SU_REGION_ET_DISABLE; - /* Set link_standby x link_off defaults */ if (DISPLAY_VER(dev_priv) < 12) /* For new platforms up to TGL let's respect VBT back again */ -- 2.34.1
[PATCH v6 22/26] drm/i915/psr: HW will not allow PR on eDP when HDCP enabled
Take into account in Panel Replay compute config that HW will not allow PR
on eDP when HDCP enabled.
Signed-off-by: Jouni Högander
---
drivers/gpu/drm/i915/display/intel_psr.c | 18 --
1 file changed, 16 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_psr.c
b/drivers/gpu/drm/i915/display/intel_psr.c
index 01bc5b76d398..3aec56d005ef 100644
--- a/drivers/gpu/drm/i915/display/intel_psr.c
+++ b/drivers/gpu/drm/i915/display/intel_psr.c
@@ -1497,8 +1497,13 @@ static bool _psr_compute_config(struct intel_dp
*intel_dp,
static bool
_panel_replay_compute_config(struct intel_dp *intel_dp,
-const struct intel_crtc_state *crtc_state)
+const struct intel_crtc_state *crtc_state,
+const struct drm_connector_state *conn_state)
{
+ struct intel_connector *connector =
+ to_intel_connector(conn_state->connector);
+ struct intel_hdcp *hdcp = &connector->hdcp;
+
if (!CAN_PANEL_REPLAY(intel_dp))
return false;
@@ -1511,6 +1516,14 @@ _panel_replay_compute_config(struct intel_dp *intel_dp,
if (intel_dp_is_uhbr(crtc_state))
return false;
+ /* HW will not allow Panel Replay on eDP when HDCP enabled */
+ if (conn_state->content_protection ==
+ DRM_MODE_CONTENT_PROTECTION_DESIRED ||
+ (conn_state->content_protection ==
+DRM_MODE_CONTENT_PROTECTION_ENABLED && hdcp->value ==
+DRM_MODE_CONTENT_PROTECTION_UNDESIRED))
+ return false;
+
return true;
}
@@ -1550,7 +1563,8 @@ void intel_psr_compute_config(struct intel_dp *intel_dp,
}
crtc_state->has_panel_replay = _panel_replay_compute_config(intel_dp,
- crtc_state);
+ crtc_state,
+ conn_state);
crtc_state->has_psr = crtc_state->has_panel_replay ? true :
_psr_compute_config(intel_dp, crtc_state);
--
2.34.1
[PATCH v6 23/26] drm/i915/psr: Check Early Transport for Panel Replay as well
Move Early Transport validity check to be performed for Panel Replay as well and use Early Transport for eDP Panel Replay always. v2:set crtc_state->enable_psr2_su_region_et directly (not in if block) Signed-off-by: Jouni Högander --- drivers/gpu/drm/i915/display/intel_psr.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c index 3aec56d005ef..97d1e4ef6ca5 100644 --- a/drivers/gpu/drm/i915/display/intel_psr.c +++ b/drivers/gpu/drm/i915/display/intel_psr.c @@ -1394,9 +1394,6 @@ static bool intel_psr2_config_valid(struct intel_dp *intel_dp, tgl_dc3co_exitline_compute_config(intel_dp, crtc_state); - if (psr2_su_region_et_valid(intel_dp, crtc_state->has_panel_replay)) - crtc_state->enable_psr2_su_region_et = true; - return true; } @@ -1458,6 +1455,9 @@ static bool intel_sel_update_config_valid(struct intel_dp *intel_dp, goto unsupported; } + crtc_state->enable_psr2_su_region_et = + psr2_su_region_et_valid(intel_dp, crtc_state->has_panel_replay); + return true; unsupported: -- 2.34.1
[PATCH v6 19/26] drm/i915/psr: Perfrom psr2 checks related to ALPM for Panel Replay
eDP1.5 support ALPM with Panel Replay as well. We need to check ALPM
related things for Panel Replay as well.
Bspec: 68920
v3: move vblank check as well
v2: do not move Vblank >= PSR2_CTL Block Count Number maximum line count
check
Signed-off-by: Jouni Högander
---
drivers/gpu/drm/i915/display/intel_psr.c | 40 +---
1 file changed, 21 insertions(+), 19 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_psr.c
b/drivers/gpu/drm/i915/display/intel_psr.c
index bc8c822094e7..f8a8f98eb44e 100644
--- a/drivers/gpu/drm/i915/display/intel_psr.c
+++ b/drivers/gpu/drm/i915/display/intel_psr.c
@@ -1383,25 +1383,6 @@ static bool intel_psr2_config_valid(struct intel_dp
*intel_dp,
return false;
}
- if (!_compute_psr2_sdp_prior_scanline_indication(intel_dp, crtc_state))
{
- drm_dbg_kms(&dev_priv->drm,
- "PSR2 not enabled, PSR2 SDP indication do not fit
in hblank\n");
- return false;
- }
-
- if (!intel_alpm_compute_params(intel_dp, crtc_state)) {
- drm_dbg_kms(&dev_priv->drm,
- "PSR2 not enabled, Unable to use long enough wake
times\n");
- return false;
- }
-
- /* Vblank >= PSR2_CTL Block Count Number maximum line count */
- if (!vblank_length_valid(intel_dp, crtc_state)) {
- drm_dbg_kms(&dev_priv->drm,
- "PSR2 not enabled, too short vblank time\n");
- return false;
- }
-
if (!crtc_state->enable_psr2_sel_fetch &&
(crtc_hdisplay > psr_max_h || crtc_vdisplay > psr_max_v)) {
drm_dbg_kms(&dev_priv->drm,
@@ -1440,6 +1421,27 @@ static bool intel_sel_update_config_valid(struct
intel_dp *intel_dp,
if (!crtc_state->has_panel_replay && !intel_psr2_config_valid(intel_dp,
crtc_state))
goto unsupported;
+ if (intel_dp_is_edp(intel_dp)) {
+ if (!_compute_psr2_sdp_prior_scanline_indication(intel_dp,
+crtc_state)) {
+ drm_dbg_kms(&dev_priv->drm,
+ "Selective update not enabled, SDP
indication do not fit in hblank\n");
+ goto unsupported;
+ }
+
+ if (!intel_alpm_compute_params(intel_dp, crtc_state)) {
+ drm_dbg_kms(&dev_priv->drm,
+ "Selective update not enabled, Unable to
use long enough wake times\n");
+ goto unsupported;
+ }
+
+ if (!vblank_length_valid(intel_dp, crtc_state)) {
+ drm_dbg_kms(&dev_priv->drm,
+ "Selective update not enabled, too short
vblank time\n");
+ goto unsupported;
+ }
+ }
+
if (crtc_state->has_panel_replay && (DISPLAY_VER(dev_priv) < 14 ||
!intel_dp->psr.sink_panel_replay_su_support))
goto unsupported;
--
2.34.1
[PATCH v6 21/26] drm/i915/psr: 128b/132b Panel Replay is not supported on eDP
Take into account that 128b/132b Panel Replay is not supported on eDP.
Bspec: 68920
Signed-off-by: Jouni Högander
---
drivers/gpu/drm/i915/display/intel_psr.c | 16 ++--
1 file changed, 14 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_psr.c
b/drivers/gpu/drm/i915/display/intel_psr.c
index 8c881a7cad3f..01bc5b76d398 100644
--- a/drivers/gpu/drm/i915/display/intel_psr.c
+++ b/drivers/gpu/drm/i915/display/intel_psr.c
@@ -1495,11 +1495,22 @@ static bool _psr_compute_config(struct intel_dp
*intel_dp,
return true;
}
-static bool _panel_replay_compute_config(struct intel_dp *intel_dp)
+static bool
+_panel_replay_compute_config(struct intel_dp *intel_dp,
+const struct intel_crtc_state *crtc_state)
{
if (!CAN_PANEL_REPLAY(intel_dp))
return false;
+ if (!intel_dp_is_edp(intel_dp))
+ return true;
+
+ /* Remaining checks are for eDP only */
+
+ /* 128b/132b Panel Replay is not supported on eDP */
+ if (intel_dp_is_uhbr(crtc_state))
+ return false;
+
return true;
}
@@ -1538,7 +1549,8 @@ void intel_psr_compute_config(struct intel_dp *intel_dp,
return;
}
- crtc_state->has_panel_replay = _panel_replay_compute_config(intel_dp);
+ crtc_state->has_panel_replay = _panel_replay_compute_config(intel_dp,
+ crtc_state);
crtc_state->has_psr = crtc_state->has_panel_replay ? true :
_psr_compute_config(intel_dp, crtc_state);
--
2.34.1
[PATCH v6 25/26] drm/i915/psr: Add new debug bit to disable Panel Replay
Currently there is no way to disable Panel Replay without disabling
PSR. Add new debug bit to be used with i915_edp_psr_debug debugfs
interface.
v2: ensure that fastset is performed when the bit changes
Signed-off-by: Jouni Högander
---
drivers/gpu/drm/i915/display/intel_display_types.h | 1 +
drivers/gpu/drm/i915/display/intel_psr.c | 11 +--
2 files changed, 10 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h
b/drivers/gpu/drm/i915/display/intel_display_types.h
index df29ec37ef28..089c53d5f3c9 100644
--- a/drivers/gpu/drm/i915/display/intel_display_types.h
+++ b/drivers/gpu/drm/i915/display/intel_display_types.h
@@ -1690,6 +1690,7 @@ struct intel_psr {
#define I915_PSR_DEBUG_ENABLE_SEL_FETCH0x4
#define I915_PSR_DEBUG_IRQ 0x10
#define I915_PSR_DEBUG_SU_REGION_ET_DISABLE0x20
+#define I915_PSR_DEBUG_PANEL_REPLAY_DISABLE0x40
u32 debug;
bool sink_support;
diff --git a/drivers/gpu/drm/i915/display/intel_psr.c
b/drivers/gpu/drm/i915/display/intel_psr.c
index a10d9383cc87..b4cd7a8b17bc 100644
--- a/drivers/gpu/drm/i915/display/intel_psr.c
+++ b/drivers/gpu/drm/i915/display/intel_psr.c
@@ -1520,6 +1520,9 @@ _panel_replay_compute_config(struct intel_dp *intel_dp,
if (!CAN_PANEL_REPLAY(intel_dp))
return false;
+ if (intel_dp->psr.debug & I915_PSR_DEBUG_PANEL_REPLAY_DISABLE)
+ return false;
+
if (!intel_dp_is_edp(intel_dp))
return true;
@@ -2845,11 +2848,13 @@ int intel_psr_debug_set(struct intel_dp *intel_dp, u64
val)
{
struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
const u32 mode = val & I915_PSR_DEBUG_MODE_MASK;
- const u32 disable_bits = val & I915_PSR_DEBUG_SU_REGION_ET_DISABLE;
+ const u32 disable_bits = val & (I915_PSR_DEBUG_SU_REGION_ET_DISABLE |
+ I915_PSR_DEBUG_PANEL_REPLAY_DISABLE);
u32 old_mode, old_disable_bits;
int ret;
if (val & ~(I915_PSR_DEBUG_IRQ | I915_PSR_DEBUG_SU_REGION_ET_DISABLE |
+ I915_PSR_DEBUG_PANEL_REPLAY_DISABLE |
I915_PSR_DEBUG_MODE_MASK) ||
mode > I915_PSR_DEBUG_ENABLE_SEL_FETCH) {
drm_dbg_kms(&dev_priv->drm, "Invalid debug mask %llx\n", val);
@@ -2862,7 +2867,9 @@ int intel_psr_debug_set(struct intel_dp *intel_dp, u64
val)
old_mode = intel_dp->psr.debug & I915_PSR_DEBUG_MODE_MASK;
old_disable_bits = intel_dp->psr.debug &
- I915_PSR_DEBUG_SU_REGION_ET_DISABLE;
+ (I915_PSR_DEBUG_SU_REGION_ET_DISABLE |
+I915_PSR_DEBUG_PANEL_REPLAY_DISABLE);
+
intel_dp->psr.debug = val;
/*
--
2.34.1
Re: [PATCH 09/12] drm/i915/cdclk: use i9xx_fsb_freq() for rawclk_freq initialization
On Tue, May 28, 2024 at 05:24:58PM +0300, Jani Nikula wrote:
> Instead of duplicating the CLKCFG parsing, reuse i9xx_fsb_freq() to
> figure out rawclk_freq where applicable.
>
> Signed-off-by: Jani Nikula
> ---
> drivers/gpu/drm/i915/display/intel_cdclk.c | 46 ++
> 1 file changed, 3 insertions(+), 43 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c
> b/drivers/gpu/drm/i915/display/intel_cdclk.c
> index b78154c82a71..c731c489c925 100644
> --- a/drivers/gpu/drm/i915/display/intel_cdclk.c
> +++ b/drivers/gpu/drm/i915/display/intel_cdclk.c
> @@ -23,6 +23,7 @@
>
> #include
>
> +#include "soc/intel_dram.h"
> #include "hsw_ips.h"
> #include "i915_reg.h"
> #include "intel_atomic.h"
> @@ -3529,10 +3530,8 @@ static int vlv_hrawclk(struct drm_i915_private
> *dev_priv)
> CCK_DISPLAY_REF_CLOCK_CONTROL);
> }
>
> -static int i9xx_hrawclk(struct drm_i915_private *dev_priv)
> +static int i9xx_hrawclk(struct drm_i915_private *i915)
> {
> - u32 clkcfg;
> -
> /*
>* hrawclock is 1/4 the FSB frequency
>*
> @@ -3543,46 +3542,7 @@ static int i9xx_hrawclk(struct drm_i915_private
> *dev_priv)
>* don't know which registers have that information,
>* and all the relevant docs have gone to bit heaven :(
>*/
^ the note about the actual clock vs. straps should probably be moved
into i9xx_fsb_freq() as a followup.
> - clkcfg = intel_de_read(dev_priv, CLKCFG) & CLKCFG_FSB_MASK;
> -
> - if (IS_MOBILE(dev_priv)) {
> - switch (clkcfg) {
> - case CLKCFG_FSB_400:
> - return 10;
> - case CLKCFG_FSB_533:
> - return 13;
> - case CLKCFG_FSB_667:
> - return 17;
> - case CLKCFG_FSB_800:
> - return 20;
> - case CLKCFG_FSB_1067:
> - return 27;
> - case CLKCFG_FSB_1333:
> - return 33;
> - default:
> - MISSING_CASE(clkcfg);
> - return 13;
> - }
> - } else {
> - switch (clkcfg) {
> - case CLKCFG_FSB_400_ALT:
> - return 10;
> - case CLKCFG_FSB_533:
> - return 13;
> - case CLKCFG_FSB_667:
> - return 17;
> - case CLKCFG_FSB_800:
> - return 20;
> - case CLKCFG_FSB_1067_ALT:
> - return 27;
> - case CLKCFG_FSB_1333_ALT:
> - return 33;
> - case CLKCFG_FSB_1600_ALT:
> - return 40;
> - default:
> - return 13;
> - }
> - }
> + return DIV_ROUND_CLOSEST(i9xx_fsb_freq(i915), 4);
> }
>
> /**
> --
> 2.39.2
--
Ville Syrjälä
Intel
[PATCH 0/7] drm/i915: bdw+ pipe interrupt stuff
From: Ville Syrjälä Clean up the bdw+ pipe interrupt bits, and enable some new fault interrupts on tgl+ and mtl+. Ville Syrjälä (7): drm/i915: Use REG_BIT() for bdw+ pipe interrupts drm/i915: Document bdw+ pipe interrupt bits drm/i915: Sort bdw+ pipe interrupt bits drm/i915: Extend GEN9_PIPE_PLANE_FLIP_DONE() to cover all universal planes drm/i915: Nuke the intermediate pipe fault bitmasks drm/i915: Enable pipeDMC fault interrupts on tgl+ drm/i915: Enable plane/pipeDMC ATS fault interrupts on mtl .../gpu/drm/i915/display/intel_display_irq.c | 49 ++-- drivers/gpu/drm/i915/i915_reg.h | 80 --- 2 files changed, 79 insertions(+), 50 deletions(-) -- 2.44.1
[PATCH 1/7] drm/i915: Use REG_BIT() for bdw+ pipe interrupts
From: Ville Syrjälä Replace the hand rolled (1< --- drivers/gpu/drm/i915/i915_reg.h | 54 - 1 file changed, 27 insertions(+), 27 deletions(-) diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index 0569a23b83b2..6b77de060e33 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -2622,33 +2622,33 @@ #define GEN8_DE_PIPE_IMR(pipe) _MMIO(0x44404 + (0x10 * (pipe))) #define GEN8_DE_PIPE_IIR(pipe) _MMIO(0x44408 + (0x10 * (pipe))) #define GEN8_DE_PIPE_IER(pipe) _MMIO(0x4440c + (0x10 * (pipe))) -#define GEN8_PIPE_FIFO_UNDERRUN (1 << 31) -#define GEN8_PIPE_CDCLK_CRC_ERROR (1 << 29) -#define GEN8_PIPE_CDCLK_CRC_DONE (1 << 28) -#define XELPD_PIPE_SOFT_UNDERRUN (1 << 22) -#define XELPD_PIPE_HARD_UNDERRUN (1 << 21) -#define GEN12_PIPE_VBLANK_UNMOD (1 << 19) -#define GEN8_PIPE_CURSOR_FAULT(1 << 10) -#define GEN8_PIPE_SPRITE_FAULT(1 << 9) -#define GEN8_PIPE_PRIMARY_FAULT (1 << 8) -#define GEN8_PIPE_SPRITE_FLIP_DONE(1 << 5) -#define GEN8_PIPE_PRIMARY_FLIP_DONE (1 << 4) -#define GEN8_PIPE_SCAN_LINE_EVENT (1 << 2) -#define GEN8_PIPE_VSYNC (1 << 1) -#define GEN8_PIPE_VBLANK (1 << 0) -#define GEN9_PIPE_CURSOR_FAULT(1 << 11) -#define GEN11_PIPE_PLANE7_FAULT (1 << 22) -#define GEN11_PIPE_PLANE6_FAULT (1 << 21) -#define GEN11_PIPE_PLANE5_FAULT (1 << 20) -#define GEN9_PIPE_PLANE4_FAULT(1 << 10) -#define GEN9_PIPE_PLANE3_FAULT(1 << 9) -#define GEN9_PIPE_PLANE2_FAULT(1 << 8) -#define GEN9_PIPE_PLANE1_FAULT(1 << 7) -#define GEN9_PIPE_PLANE4_FLIP_DONE(1 << 6) -#define GEN9_PIPE_PLANE3_FLIP_DONE(1 << 5) -#define GEN9_PIPE_PLANE2_FLIP_DONE(1 << 4) -#define GEN9_PIPE_PLANE1_FLIP_DONE(1 << 3) -#define GEN9_PIPE_PLANE_FLIP_DONE(p) (1 << (3 + (p))) +#define GEN8_PIPE_FIFO_UNDERRUN REG_BIT(31) +#define GEN8_PIPE_CDCLK_CRC_ERROR REG_BIT(29) +#define GEN8_PIPE_CDCLK_CRC_DONE REG_BIT(28) +#define XELPD_PIPE_SOFT_UNDERRUN REG_BIT(22) +#define XELPD_PIPE_HARD_UNDERRUN REG_BIT(21) +#define GEN12_PIPE_VBLANK_UNMOD REG_BIT(19) +#define GEN8_PIPE_CURSOR_FAULTREG_BIT(10) +#define GEN8_PIPE_SPRITE_FAULTREG_BIT(9) +#define GEN8_PIPE_PRIMARY_FAULT REG_BIT(8) +#define GEN8_PIPE_SPRITE_FLIP_DONEREG_BIT(5) +#define GEN8_PIPE_PRIMARY_FLIP_DONE REG_BIT(4) +#define GEN8_PIPE_SCAN_LINE_EVENT REG_BIT(2) +#define GEN8_PIPE_VSYNC REG_BIT(1) +#define GEN8_PIPE_VBLANK REG_BIT(0) +#define GEN9_PIPE_CURSOR_FAULTREG_BIT(11) +#define GEN11_PIPE_PLANE7_FAULT REG_BIT(22) +#define GEN11_PIPE_PLANE6_FAULT REG_BIT(21) +#define GEN11_PIPE_PLANE5_FAULT REG_BIT(20) +#define GEN9_PIPE_PLANE4_FAULTREG_BIT(10) +#define GEN9_PIPE_PLANE3_FAULTREG_BIT(9) +#define GEN9_PIPE_PLANE2_FAULTREG_BIT(8) +#define GEN9_PIPE_PLANE1_FAULTREG_BIT(7) +#define GEN9_PIPE_PLANE4_FLIP_DONEREG_BIT(6) +#define GEN9_PIPE_PLANE3_FLIP_DONEREG_BIT(5) +#define GEN9_PIPE_PLANE2_FLIP_DONEREG_BIT(4) +#define GEN9_PIPE_PLANE1_FLIP_DONEREG_BIT(3) +#define GEN9_PIPE_PLANE_FLIP_DONE(p) REG_BIT(3 + (p)) #define GEN8_DE_PIPE_IRQ_FAULT_ERRORS \ (GEN8_PIPE_CURSOR_FAULT | \ GEN8_PIPE_SPRITE_FAULT | \ -- 2.44.1
[PATCH 2/7] drm/i915: Document bdw+ pipe interrupt bits
From: Ville Syrjälä Sprinkle some notes indicating which platforms have which pipe interrupt bits. Signed-off-by: Ville Syrjälä --- drivers/gpu/drm/i915/i915_reg.h | 42 - 1 file changed, 21 insertions(+), 21 deletions(-) diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index 6b77de060e33..2d0751fb9591 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -2625,30 +2625,30 @@ #define GEN8_PIPE_FIFO_UNDERRUN REG_BIT(31) #define GEN8_PIPE_CDCLK_CRC_ERROR REG_BIT(29) #define GEN8_PIPE_CDCLK_CRC_DONE REG_BIT(28) -#define XELPD_PIPE_SOFT_UNDERRUN REG_BIT(22) -#define XELPD_PIPE_HARD_UNDERRUN REG_BIT(21) -#define GEN12_PIPE_VBLANK_UNMOD REG_BIT(19) -#define GEN8_PIPE_CURSOR_FAULTREG_BIT(10) -#define GEN8_PIPE_SPRITE_FAULTREG_BIT(9) -#define GEN8_PIPE_PRIMARY_FAULT REG_BIT(8) -#define GEN8_PIPE_SPRITE_FLIP_DONEREG_BIT(5) -#define GEN8_PIPE_PRIMARY_FLIP_DONE REG_BIT(4) +#define XELPD_PIPE_SOFT_UNDERRUN REG_BIT(22) /* adl/dg2+ */ +#define XELPD_PIPE_HARD_UNDERRUN REG_BIT(21) /* adl/dg2+ */ +#define GEN12_PIPE_VBLANK_UNMOD REG_BIT(19) /* tgl+ */ +#define GEN8_PIPE_CURSOR_FAULTREG_BIT(10) /* bdw */ +#define GEN8_PIPE_SPRITE_FAULTREG_BIT(9) /* bdw */ +#define GEN8_PIPE_PRIMARY_FAULT REG_BIT(8) /* bdw */ +#define GEN8_PIPE_SPRITE_FLIP_DONEREG_BIT(5) /* bdw */ +#define GEN8_PIPE_PRIMARY_FLIP_DONE REG_BIT(4) /* bdw */ #define GEN8_PIPE_SCAN_LINE_EVENT REG_BIT(2) #define GEN8_PIPE_VSYNC REG_BIT(1) #define GEN8_PIPE_VBLANK REG_BIT(0) -#define GEN9_PIPE_CURSOR_FAULTREG_BIT(11) -#define GEN11_PIPE_PLANE7_FAULT REG_BIT(22) -#define GEN11_PIPE_PLANE6_FAULT REG_BIT(21) -#define GEN11_PIPE_PLANE5_FAULT REG_BIT(20) -#define GEN9_PIPE_PLANE4_FAULTREG_BIT(10) -#define GEN9_PIPE_PLANE3_FAULTREG_BIT(9) -#define GEN9_PIPE_PLANE2_FAULTREG_BIT(8) -#define GEN9_PIPE_PLANE1_FAULTREG_BIT(7) -#define GEN9_PIPE_PLANE4_FLIP_DONEREG_BIT(6) -#define GEN9_PIPE_PLANE3_FLIP_DONEREG_BIT(5) -#define GEN9_PIPE_PLANE2_FLIP_DONEREG_BIT(4) -#define GEN9_PIPE_PLANE1_FLIP_DONEREG_BIT(3) -#define GEN9_PIPE_PLANE_FLIP_DONE(p) REG_BIT(3 + (p)) +#define GEN9_PIPE_CURSOR_FAULTREG_BIT(11) /* skl+ */ +#define GEN11_PIPE_PLANE7_FAULT REG_BIT(22) /* icl/tgl */ +#define GEN11_PIPE_PLANE6_FAULT REG_BIT(21) /* icl/tgl */ +#define GEN11_PIPE_PLANE5_FAULT REG_BIT(20) /* icl+ */ +#define GEN9_PIPE_PLANE4_FAULTREG_BIT(10) /* skl+ */ +#define GEN9_PIPE_PLANE3_FAULTREG_BIT(9) /* skl+ */ +#define GEN9_PIPE_PLANE2_FAULTREG_BIT(8) /* skl+ */ +#define GEN9_PIPE_PLANE1_FAULTREG_BIT(7) /* skl+ */ +#define GEN9_PIPE_PLANE4_FLIP_DONEREG_BIT(6) /* skl+ */ +#define GEN9_PIPE_PLANE3_FLIP_DONEREG_BIT(5) /* skl+ */ +#define GEN9_PIPE_PLANE2_FLIP_DONEREG_BIT(4) /* skl+ */ +#define GEN9_PIPE_PLANE1_FLIP_DONEREG_BIT(3) /* skl+ */ +#define GEN9_PIPE_PLANE_FLIP_DONE(p) REG_BIT(3 + (p)) /* skl+ */ #define GEN8_DE_PIPE_IRQ_FAULT_ERRORS \ (GEN8_PIPE_CURSOR_FAULT | \ GEN8_PIPE_SPRITE_FAULT | \ -- 2.44.1
[PATCH 3/7] drm/i915: Sort bdw+ pipe interrupt bits
From: Ville Syrjälä It's really hard to figure out which bdw+ pipe interrupt bits we've defined and which we have not. Sort the defines to make that a bit easier (still not super easy since the bits have been shuffled a bit over the years). Signed-off-by: Ville Syrjälä --- drivers/gpu/drm/i915/i915_reg.h | 22 +++--- 1 file changed, 11 insertions(+), 11 deletions(-) diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index 2d0751fb9591..8e1053c60284 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -2626,29 +2626,29 @@ #define GEN8_PIPE_CDCLK_CRC_ERROR REG_BIT(29) #define GEN8_PIPE_CDCLK_CRC_DONE REG_BIT(28) #define XELPD_PIPE_SOFT_UNDERRUN REG_BIT(22) /* adl/dg2+ */ -#define XELPD_PIPE_HARD_UNDERRUN REG_BIT(21) /* adl/dg2+ */ -#define GEN12_PIPE_VBLANK_UNMOD REG_BIT(19) /* tgl+ */ -#define GEN8_PIPE_CURSOR_FAULTREG_BIT(10) /* bdw */ -#define GEN8_PIPE_SPRITE_FAULTREG_BIT(9) /* bdw */ -#define GEN8_PIPE_PRIMARY_FAULT REG_BIT(8) /* bdw */ -#define GEN8_PIPE_SPRITE_FLIP_DONEREG_BIT(5) /* bdw */ -#define GEN8_PIPE_PRIMARY_FLIP_DONE REG_BIT(4) /* bdw */ -#define GEN8_PIPE_SCAN_LINE_EVENT REG_BIT(2) -#define GEN8_PIPE_VSYNC REG_BIT(1) -#define GEN8_PIPE_VBLANK REG_BIT(0) -#define GEN9_PIPE_CURSOR_FAULTREG_BIT(11) /* skl+ */ #define GEN11_PIPE_PLANE7_FAULT REG_BIT(22) /* icl/tgl */ +#define XELPD_PIPE_HARD_UNDERRUN REG_BIT(21) /* adl/dg2+ */ #define GEN11_PIPE_PLANE6_FAULT REG_BIT(21) /* icl/tgl */ #define GEN11_PIPE_PLANE5_FAULT REG_BIT(20) /* icl+ */ +#define GEN12_PIPE_VBLANK_UNMOD REG_BIT(19) /* tgl+ */ +#define GEN9_PIPE_CURSOR_FAULTREG_BIT(11) /* skl+ */ #define GEN9_PIPE_PLANE4_FAULTREG_BIT(10) /* skl+ */ +#define GEN8_PIPE_CURSOR_FAULTREG_BIT(10) /* bdw */ #define GEN9_PIPE_PLANE3_FAULTREG_BIT(9) /* skl+ */ +#define GEN8_PIPE_SPRITE_FAULTREG_BIT(9) /* bdw */ #define GEN9_PIPE_PLANE2_FAULTREG_BIT(8) /* skl+ */ +#define GEN8_PIPE_PRIMARY_FAULT REG_BIT(8) /* bdw */ #define GEN9_PIPE_PLANE1_FAULTREG_BIT(7) /* skl+ */ #define GEN9_PIPE_PLANE4_FLIP_DONEREG_BIT(6) /* skl+ */ #define GEN9_PIPE_PLANE3_FLIP_DONEREG_BIT(5) /* skl+ */ +#define GEN8_PIPE_SPRITE_FLIP_DONEREG_BIT(5) /* bdw */ #define GEN9_PIPE_PLANE2_FLIP_DONEREG_BIT(4) /* skl+ */ +#define GEN8_PIPE_PRIMARY_FLIP_DONE REG_BIT(4) /* bdw */ #define GEN9_PIPE_PLANE1_FLIP_DONEREG_BIT(3) /* skl+ */ #define GEN9_PIPE_PLANE_FLIP_DONE(p) REG_BIT(3 + (p)) /* skl+ */ +#define GEN8_PIPE_SCAN_LINE_EVENT REG_BIT(2) +#define GEN8_PIPE_VSYNC REG_BIT(1) +#define GEN8_PIPE_VBLANK REG_BIT(0) #define GEN8_DE_PIPE_IRQ_FAULT_ERRORS \ (GEN8_PIPE_CURSOR_FAULT | \ GEN8_PIPE_SPRITE_FAULT | \ -- 2.44.1
[PATCH 4/7] drm/i915: Extend GEN9_PIPE_PLANE_FLIP_DONE() to cover all universal planes
From: Ville Syrjälä GEN9_PIPE_PLANE_FLIP_DONE() only works for planes 1-4. Extend it handle planes 5-7 as well. Somewhat annoyingly the bits are spread around into two distinct clumps. Currently this doesn't achieve anything, but if we ever extend async flip support to more than just the first plane then we'll need this. Signed-off-by: Ville Syrjälä --- drivers/gpu/drm/i915/i915_reg.h | 6 +- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index 8e1053c60284..4d5438ce73a2 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -2631,6 +2631,9 @@ #define GEN11_PIPE_PLANE6_FAULT REG_BIT(21) /* icl/tgl */ #define GEN11_PIPE_PLANE5_FAULT REG_BIT(20) /* icl+ */ #define GEN12_PIPE_VBLANK_UNMOD REG_BIT(19) /* tgl+ */ +#define GEN11_PIPE_PLANE7_FLIP_DONE REG_BIT(18) /* icl/tgl */ +#define GEN11_PIPE_PLANE6_FLIP_DONE REG_BIT(17) /* icl/tgl */ +#define GEN11_PIPE_PLANE5_FLIP_DONE REG_BIT(16) /* icl+ */ #define GEN9_PIPE_CURSOR_FAULTREG_BIT(11) /* skl+ */ #define GEN9_PIPE_PLANE4_FAULTREG_BIT(10) /* skl+ */ #define GEN8_PIPE_CURSOR_FAULTREG_BIT(10) /* bdw */ @@ -2645,7 +2648,8 @@ #define GEN9_PIPE_PLANE2_FLIP_DONEREG_BIT(4) /* skl+ */ #define GEN8_PIPE_PRIMARY_FLIP_DONE REG_BIT(4) /* bdw */ #define GEN9_PIPE_PLANE1_FLIP_DONEREG_BIT(3) /* skl+ */ -#define GEN9_PIPE_PLANE_FLIP_DONE(p) REG_BIT(3 + (p)) /* skl+ */ +#define GEN9_PIPE_PLANE_FLIP_DONE(plane_id) \ + REG_BIT(((plane_id) >= PLANE_5 ? 16 - PLANE_5 : 3 - PLANE_1) + (plane_id)) /* skl+ */ #define GEN8_PIPE_SCAN_LINE_EVENT REG_BIT(2) #define GEN8_PIPE_VSYNC REG_BIT(1) #define GEN8_PIPE_VBLANK REG_BIT(0) -- 2.44.1
[PATCH 5/7] drm/i915: Nuke the intermediate pipe fault bitmasks
From: Ville Syrjälä
GEN8_DE_PIPE_IRQ_FAULT_ERRORS & co. don't really achieve anything.
Get rid of them and just declare all the bits directly in
gen8_de_pipe_fault_mask().
Signed-off-by: Ville Syrjälä
---
.../gpu/drm/i915/display/intel_display_irq.c | 26 ---
drivers/gpu/drm/i915/i915_reg.h | 18 -
2 files changed, 22 insertions(+), 22 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display_irq.c
b/drivers/gpu/drm/i915/display/intel_display_irq.c
index d2d70b81aef9..219f7693207d 100644
--- a/drivers/gpu/drm/i915/display/intel_display_irq.c
+++ b/drivers/gpu/drm/i915/display/intel_display_irq.c
@@ -836,13 +836,31 @@ static u32 gen8_de_port_aux_mask(struct drm_i915_private
*dev_priv)
static u32 gen8_de_pipe_fault_mask(struct drm_i915_private *dev_priv)
{
if (DISPLAY_VER(dev_priv) >= 13 || HAS_D12_PLANE_MINIMIZATION(dev_priv))
- return RKL_DE_PIPE_IRQ_FAULT_ERRORS;
+ return GEN9_PIPE_CURSOR_FAULT |
+ GEN11_PIPE_PLANE5_FAULT |
+ GEN9_PIPE_PLANE4_FAULT |
+ GEN9_PIPE_PLANE3_FAULT |
+ GEN9_PIPE_PLANE2_FAULT |
+ GEN9_PIPE_PLANE1_FAULT;
else if (DISPLAY_VER(dev_priv) >= 11)
- return GEN11_DE_PIPE_IRQ_FAULT_ERRORS;
+ return GEN9_PIPE_CURSOR_FAULT |
+ GEN11_PIPE_PLANE7_FAULT |
+ GEN11_PIPE_PLANE6_FAULT |
+ GEN11_PIPE_PLANE5_FAULT |
+ GEN9_PIPE_PLANE4_FAULT |
+ GEN9_PIPE_PLANE3_FAULT |
+ GEN9_PIPE_PLANE2_FAULT |
+ GEN9_PIPE_PLANE1_FAULT;
else if (DISPLAY_VER(dev_priv) >= 9)
- return GEN9_DE_PIPE_IRQ_FAULT_ERRORS;
+ return GEN9_PIPE_CURSOR_FAULT |
+ GEN9_PIPE_PLANE4_FAULT |
+ GEN9_PIPE_PLANE3_FAULT |
+ GEN9_PIPE_PLANE2_FAULT |
+ GEN9_PIPE_PLANE1_FAULT;
else
- return GEN8_DE_PIPE_IRQ_FAULT_ERRORS;
+ return GEN8_PIPE_CURSOR_FAULT |
+ GEN8_PIPE_SPRITE_FAULT |
+ GEN8_PIPE_PRIMARY_FAULT;
}
static void intel_pmdemand_irq_handler(struct drm_i915_private *dev_priv)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 4d5438ce73a2..b85e12bb4781 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -2653,24 +2653,6 @@
#define GEN8_PIPE_SCAN_LINE_EVENT REG_BIT(2)
#define GEN8_PIPE_VSYNC REG_BIT(1)
#define GEN8_PIPE_VBLANK REG_BIT(0)
-#define GEN8_DE_PIPE_IRQ_FAULT_ERRORS \
- (GEN8_PIPE_CURSOR_FAULT | \
-GEN8_PIPE_SPRITE_FAULT | \
-GEN8_PIPE_PRIMARY_FAULT)
-#define GEN9_DE_PIPE_IRQ_FAULT_ERRORS \
- (GEN9_PIPE_CURSOR_FAULT | \
-GEN9_PIPE_PLANE4_FAULT | \
-GEN9_PIPE_PLANE3_FAULT | \
-GEN9_PIPE_PLANE2_FAULT | \
-GEN9_PIPE_PLANE1_FAULT)
-#define GEN11_DE_PIPE_IRQ_FAULT_ERRORS \
- (GEN9_DE_PIPE_IRQ_FAULT_ERRORS | \
-GEN11_PIPE_PLANE7_FAULT | \
-GEN11_PIPE_PLANE6_FAULT | \
-GEN11_PIPE_PLANE5_FAULT)
-#define RKL_DE_PIPE_IRQ_FAULT_ERRORS \
- (GEN9_DE_PIPE_IRQ_FAULT_ERRORS | \
-GEN11_PIPE_PLANE5_FAULT)
#define _HPD_PIN_DDI(hpd_pin) ((hpd_pin) - HPD_PORT_A)
#define _HPD_PIN_TC(hpd_pin) ((hpd_pin) - HPD_PORT_TC1)
--
2.44.1
[PATCH 6/7] drm/i915: Enable pipeDMC fault interrupts on tgl+
From: Ville Syrjälä
PipeDMC has its own fault interrupt. Enable that so that
we can know if things are failing.
While at it, define the other pipeDMC interrupt as well, even
though we're not currently using it.
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/display/intel_display_irq.c | 15 +--
drivers/gpu/drm/i915/i915_reg.h | 2 ++
2 files changed, 15 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display_irq.c
b/drivers/gpu/drm/i915/display/intel_display_irq.c
index 219f7693207d..6eb14ffc3c1b 100644
--- a/drivers/gpu/drm/i915/display/intel_display_irq.c
+++ b/drivers/gpu/drm/i915/display/intel_display_irq.c
@@ -836,13 +836,24 @@ static u32 gen8_de_port_aux_mask(struct drm_i915_private
*dev_priv)
static u32 gen8_de_pipe_fault_mask(struct drm_i915_private *dev_priv)
{
if (DISPLAY_VER(dev_priv) >= 13 || HAS_D12_PLANE_MINIMIZATION(dev_priv))
- return GEN9_PIPE_CURSOR_FAULT |
+ return GEN12_PIPEDMC_FAULT |
+ GEN9_PIPE_CURSOR_FAULT |
GEN11_PIPE_PLANE5_FAULT |
GEN9_PIPE_PLANE4_FAULT |
GEN9_PIPE_PLANE3_FAULT |
GEN9_PIPE_PLANE2_FAULT |
GEN9_PIPE_PLANE1_FAULT;
- else if (DISPLAY_VER(dev_priv) >= 11)
+ else if (DISPLAY_VER(dev_priv) == 12)
+ return GEN12_PIPEDMC_FAULT |
+ GEN9_PIPE_CURSOR_FAULT |
+ GEN11_PIPE_PLANE7_FAULT |
+ GEN11_PIPE_PLANE6_FAULT |
+ GEN11_PIPE_PLANE5_FAULT |
+ GEN9_PIPE_PLANE4_FAULT |
+ GEN9_PIPE_PLANE3_FAULT |
+ GEN9_PIPE_PLANE2_FAULT |
+ GEN9_PIPE_PLANE1_FAULT;
+ else if (DISPLAY_VER(dev_priv) == 11)
return GEN9_PIPE_CURSOR_FAULT |
GEN11_PIPE_PLANE7_FAULT |
GEN11_PIPE_PLANE6_FAULT |
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index b85e12bb4781..8cd5abc52a2d 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -2625,6 +2625,8 @@
#define GEN8_PIPE_FIFO_UNDERRUN REG_BIT(31)
#define GEN8_PIPE_CDCLK_CRC_ERROR REG_BIT(29)
#define GEN8_PIPE_CDCLK_CRC_DONE REG_BIT(28)
+#define GEN12_PIPEDMC_INTERRUPT REG_BIT(26) /* tgl+ */
+#define GEN12_PIPEDMC_FAULT REG_BIT(25) /* tgl+ */
#define XELPD_PIPE_SOFT_UNDERRUN REG_BIT(22) /* adl/dg2+ */
#define GEN11_PIPE_PLANE7_FAULT REG_BIT(22) /* icl/tgl */
#define XELPD_PIPE_HARD_UNDERRUN REG_BIT(21) /* adl/dg2+ */
--
2.44.1
[PATCH 7/7] drm/i915: Enable plane/pipeDMC ATS fault interrupts on mtl
From: Ville Syrjälä
MTL has some new IOMMU thing that has a few new fault interrupts.
Enable those so we can know if things are going poorly.
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/display/intel_display_irq.c | 10 ++
drivers/gpu/drm/i915/i915_reg.h | 2 ++
2 files changed, 12 insertions(+)
diff --git a/drivers/gpu/drm/i915/display/intel_display_irq.c
b/drivers/gpu/drm/i915/display/intel_display_irq.c
index 6eb14ffc3c1b..49bcba5e38cb 100644
--- a/drivers/gpu/drm/i915/display/intel_display_irq.c
+++ b/drivers/gpu/drm/i915/display/intel_display_irq.c
@@ -835,6 +835,16 @@ static u32 gen8_de_port_aux_mask(struct drm_i915_private
*dev_priv)
static u32 gen8_de_pipe_fault_mask(struct drm_i915_private *dev_priv)
{
+ if (DISPLAY_VER(dev_priv) >= 14)
+ return MTL_PIPEDMC_ATS_FAULT |
+ MTL_PLANE_ATS_FAULT |
+ GEN12_PIPEDMC_FAULT |
+ GEN9_PIPE_CURSOR_FAULT |
+ GEN11_PIPE_PLANE5_FAULT |
+ GEN9_PIPE_PLANE4_FAULT |
+ GEN9_PIPE_PLANE3_FAULT |
+ GEN9_PIPE_PLANE2_FAULT |
+ GEN9_PIPE_PLANE1_FAULT;
if (DISPLAY_VER(dev_priv) >= 13 || HAS_D12_PLANE_MINIMIZATION(dev_priv))
return GEN12_PIPEDMC_FAULT |
GEN9_PIPE_CURSOR_FAULT |
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 8cd5abc52a2d..33822816c27e 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -2627,12 +2627,14 @@
#define GEN8_PIPE_CDCLK_CRC_DONE REG_BIT(28)
#define GEN12_PIPEDMC_INTERRUPT REG_BIT(26) /* tgl+ */
#define GEN12_PIPEDMC_FAULT REG_BIT(25) /* tgl+ */
+#define MTL_PIPEDMC_ATS_FAULT REG_BIT(24) /* mtl+ */
#define XELPD_PIPE_SOFT_UNDERRUN REG_BIT(22) /* adl/dg2+ */
#define GEN11_PIPE_PLANE7_FAULT REG_BIT(22) /* icl/tgl */
#define XELPD_PIPE_HARD_UNDERRUN REG_BIT(21) /* adl/dg2+ */
#define GEN11_PIPE_PLANE6_FAULT REG_BIT(21) /* icl/tgl */
#define GEN11_PIPE_PLANE5_FAULT REG_BIT(20) /* icl+ */
#define GEN12_PIPE_VBLANK_UNMOD REG_BIT(19) /* tgl+ */
+#define MTL_PLANE_ATS_FAULT REG_BIT(18) /* mtl+ */
#define GEN11_PIPE_PLANE7_FLIP_DONE REG_BIT(18) /* icl/tgl */
#define GEN11_PIPE_PLANE6_FLIP_DONE REG_BIT(17) /* icl/tgl */
#define GEN11_PIPE_PLANE5_FLIP_DONE REG_BIT(16) /* icl+ */
--
2.44.1
[PATCH] drm/i915: Reduce DDI clock gating printk level from NOTICE to DEBUG
From: Ville Syrjälä No idea why the DDI clock gating print is done with drm_notice(). Just use drm_dbg_kms() since no one is going to be interested in this under normal circumstances. Signed-off-by: Ville Syrjälä --- drivers/gpu/drm/i915/display/intel_ddi.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c index 3c3fc53376ce..c76bbd13bb27 100644 --- a/drivers/gpu/drm/i915/display/intel_ddi.c +++ b/drivers/gpu/drm/i915/display/intel_ddi.c @@ -2072,9 +2072,9 @@ void intel_ddi_sanitize_encoder_pll_mapping(struct intel_encoder *encoder) !encoder->is_clock_enabled(encoder)) return; - drm_notice(&i915->drm, - "[ENCODER:%d:%s] is disabled/in DSI mode with an ungated DDI clock, gate it\n", - encoder->base.base.id, encoder->base.name); + drm_dbg_kms(&i915->drm, + "[ENCODER:%d:%s] is disabled/in DSI mode with an ungated DDI clock, gate it\n", + encoder->base.base.id, encoder->base.name); encoder->disable_clock(encoder); } -- 2.44.1
Re: [PATCH] drm/i915: Reduce DDI clock gating printk level from NOTICE to DEBUG
On Wed, 05 Jun 2024, Ville Syrjala wrote: > From: Ville Syrjälä > > No idea why the DDI clock gating print is done with drm_notice(). > Just use drm_dbg_kms() since no one is going to be interested in > this under normal circumstances. > > Signed-off-by: Ville Syrjälä Reviewed-by: Jani Nikula > --- > drivers/gpu/drm/i915/display/intel_ddi.c | 6 +++--- > 1 file changed, 3 insertions(+), 3 deletions(-) > > diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c > b/drivers/gpu/drm/i915/display/intel_ddi.c > index 3c3fc53376ce..c76bbd13bb27 100644 > --- a/drivers/gpu/drm/i915/display/intel_ddi.c > +++ b/drivers/gpu/drm/i915/display/intel_ddi.c > @@ -2072,9 +2072,9 @@ void intel_ddi_sanitize_encoder_pll_mapping(struct > intel_encoder *encoder) > !encoder->is_clock_enabled(encoder)) > return; > > - drm_notice(&i915->drm, > -"[ENCODER:%d:%s] is disabled/in DSI mode with an ungated DDI > clock, gate it\n", > -encoder->base.base.id, encoder->base.name); > + drm_dbg_kms(&i915->drm, > + "[ENCODER:%d:%s] is disabled/in DSI mode with an ungated > DDI clock, gate it\n", > + encoder->base.base.id, encoder->base.name); > > encoder->disable_clock(encoder); > } -- Jani Nikula, Intel
Re: [PATCH 1/3] drm/i915: drop redundant W=1 warnings from Makefile
On Thu, 23 May 2024, Jani Nikula wrote:
> Since commit a61ddb4393ad ("drm: enable (most) W=1 warnings by default
> across the subsystem"), most of the extra warnings in the driver
> Makefile are redundant. Remove them.
>
> Note that -Wmissing-declarations and -Wmissing-prototypes are always
> enabled by default in scripts/Makefile.extrawarn.
>
> Signed-off-by: Jani Nikula
Pushed this patch to drm-intel-next with Lucas' irc ack.
BR,
Jani.
> ---
> drivers/gpu/drm/i915/Makefile | 25 +
> 1 file changed, 1 insertion(+), 24 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makefile
> index 7cad944b825c..a70d95a8fd7a 100644
> --- a/drivers/gpu/drm/i915/Makefile
> +++ b/drivers/gpu/drm/i915/Makefile
> @@ -3,31 +3,8 @@
> # Makefile for the drm device driver. This driver provides support for the
> # Direct Rendering Infrastructure (DRI) in XFree86 4.1.0 and higher.
>
> -# Unconditionally enable W=1 warnings locally
> -# --- begin copy-paste W=1 warnings from scripts/Makefile.extrawarn
> -subdir-ccflags-y += -Wextra -Wunused -Wno-unused-parameter
> -subdir-ccflags-y += -Wmissing-declarations
> -subdir-ccflags-y += $(call cc-option, -Wrestrict)
> -subdir-ccflags-y += -Wmissing-format-attribute
> -subdir-ccflags-y += -Wmissing-prototypes
> -subdir-ccflags-y += -Wold-style-definition
> -subdir-ccflags-y += -Wmissing-include-dirs
> -subdir-ccflags-y += $(call cc-option, -Wunused-but-set-variable)
> -subdir-ccflags-y += $(call cc-option, -Wunused-const-variable)
> -subdir-ccflags-y += $(call cc-option, -Wpacked-not-aligned)
> -subdir-ccflags-y += $(call cc-option, -Wformat-overflow)
> +# Enable W=1 warnings not enabled in drm subsystem Makefile
> subdir-ccflags-y += $(call cc-option, -Wformat-truncation)
> -subdir-ccflags-y += $(call cc-option, -Wstringop-truncation)
> -# The following turn off the warnings enabled by -Wextra
> -ifeq ($(findstring 2, $(KBUILD_EXTRA_WARN)),)
> -subdir-ccflags-y += -Wno-missing-field-initializers
> -subdir-ccflags-y += -Wno-type-limits
> -subdir-ccflags-y += -Wno-shift-negative-value
> -endif
> -ifeq ($(findstring 3, $(KBUILD_EXTRA_WARN)),)
> -subdir-ccflags-y += -Wno-sign-compare
> -endif
> -# --- end copy-paste
>
> # Enable -Werror in CI and development
> subdir-ccflags-$(CONFIG_DRM_I915_WERROR) += -Werror
--
Jani Nikula, Intel
[PATCH v12 0/9] Implement CMRR Support
CMRR is a display feature that uses adaptive sync framework to vary Vtotal slightly to match the content rate exactly without frame drops. This feature is a variation of VRR where it varies Vtotal slightly (between additional 0 and 1 Vtotal scanlines) to match content rate exactly without frame drops using the adaptive sync framework. enable this feature by programing new registers for CMRR enable, CMRR_M, CMRR_N, vmin=vmax=flipline.The CMRR_M/CMRR_N ratio represents the fractional part in (actual refresh rate/target refresh rate) * origVTotal. --v6: - CMRR handling in co-existatnce of LRR and DRRS - Correct vtotal paramas accuracy and add 2 digit precision. --v7: - Rebased patches in-accordance to AS SDP merge. - Add neccessary gaurd to prevent crtc_state mismatch during intel_vrr_get_config. -v8: - Add support for AS SDP for CMRR. - update palce holder for CMRR register(Jani). - Make CMRR as subset of FAVT, as per comments in patch#3. -v9: - Add CMRR register definitions to separate intel_vrr_reg.h. - Remove cmrr_enabling/disabling, use vrr.enable instead. - Update AS SDP pack function to accomodate target_rr_divider. - Remove duplicated lines to compute vrr_vsync params. - Set cmrr.enable with a separate patch at last. -v10: - Separate VRR related register definitions. - Add dependency header intel_display_reg_defs.h. - Rename file name to intel_vrr_regs.h instead of reg.h. - Revert removed line. - Since vrr.enable and cmrr.enable are not mutually exclusive, handle accordingly. - is_edp is not required inside is_cmrr_frac_required function. - Add video_mode_required flag for future enhancement. - Correct cmrr_m/cmrr_n calculation. - target_rr_divider is bools so handle accordingly. -v11: - Move VRR related register and bits to separate file intel_vrr_regs.h. - Correct file header macro to intel_vrr_regs.h. - Remove adding CMRR flag to vrr_ctl register during set_transcoder_timing. - Replace vrr.enable flag to cmrr.enable where added mistakenly. - Move cmrr computation patch to last and set other other required params before computing cmrr.enable. -v12: - Add patch to fix check patch issues for VRR related registers in i915_reg.h then move them to intel_vrr_regs.h with separate patch. - Use drm_mode_vrefresh instead of manual refresh rate calculation. Mitul Golani (7): gpu/drm/i915: Update indentation for VRR registers and bits drm/i915: Separate VRR related register definitions drm/i915: Define and compute Transcoder CMRR registers drm/i915: Update trans_vrr_ctl flag when cmrr is computed drm/dp: Add refresh rate divider to struct representing AS SDP drm/i915/display: Add support for pack and unpack drm/i915/display: Compute Adaptive sync SDP params Ville Syrjälä (2): drm/i915: Protect CRC reg macro arguments for consistency drm-tip: 2024y-06m-05d-09h-52m-50s UTC integration manifest -- 2.25.1
[PATCH v12 1/9] drm/i915: Protect CRC reg macro arguments for consistency
From: Ville Syrjälä It's probably a good idea to start protecting all macro arguments to avoid any cargo-cult mistakes when people go looking for examples of how to define these things. Signed-off-by: Ville Syrjälä Link: https://patchwork.freedesktop.org/patch/msgid/20240531115342.2763-8-ville.syrj...@linux.intel.com Reviewed-by: Jani Nikula --- .../drm/i915/display/intel_pipe_crc_regs.h| 26 +-- 1 file changed, 13 insertions(+), 13 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_pipe_crc_regs.h b/drivers/gpu/drm/i915/display/intel_pipe_crc_regs.h index 383910a785f6..4e65f51d34e6 100644 --- a/drivers/gpu/drm/i915/display/intel_pipe_crc_regs.h +++ b/drivers/gpu/drm/i915/display/intel_pipe_crc_regs.h @@ -9,7 +9,7 @@ #include "intel_display_reg_defs.h" #define _PIPE_CRC_CTL_A0x60050 -#define PIPE_CRC_CTL(dev_priv, pipe) _MMIO_TRANS2(dev_priv, pipe, _PIPE_CRC_CTL_A) +#define PIPE_CRC_CTL(dev_priv, pipe) _MMIO_TRANS2((dev_priv), (pipe), _PIPE_CRC_CTL_A) #define PIPE_CRC_ENABLE REG_BIT(31) /* skl+ source selection */ #define PIPE_CRC_SOURCE_MASK_SKL REG_GENMASK(30, 28) @@ -76,19 +76,19 @@ #define PIPE_CRC_EXP_RES2_MASK REG_BIT(22, 0) /* pre-ivb */ #define _PIPE_CRC_RES_RED_A0x60060 -#define PIPE_CRC_RES_RED(dev_priv, pipe) _MMIO_TRANS2(dev_priv, pipe, _PIPE_CRC_RES_RED_A) +#define PIPE_CRC_RES_RED(dev_priv, pipe) _MMIO_TRANS2((dev_priv), (pipe), _PIPE_CRC_RES_RED_A) #define _PIPE_CRC_RES_GREEN_A 0x60064 -#define PIPE_CRC_RES_GREEN(dev_priv, pipe) _MMIO_TRANS2(dev_priv, pipe, _PIPE_CRC_RES_GREEN_A) +#define PIPE_CRC_RES_GREEN(dev_priv, pipe) _MMIO_TRANS2((dev_priv), (pipe), _PIPE_CRC_RES_GREEN_A) #define _PIPE_CRC_RES_BLUE_A 0x60068 -#define PIPE_CRC_RES_BLUE(dev_priv, pipe) _MMIO_TRANS2(dev_priv, pipe, _PIPE_CRC_RES_BLUE_A) +#define PIPE_CRC_RES_BLUE(dev_priv, pipe) _MMIO_TRANS2((dev_priv), (pipe), _PIPE_CRC_RES_BLUE_A) #define _PIPE_CRC_RES_RES1_A_I915 0x6006c /* i915+ */ -#define PIPE_CRC_RES_RES1_I915(dev_priv, pipe) _MMIO_TRANS2(dev_priv, pipe, _PIPE_CRC_RES_RES1_A_I915) +#define PIPE_CRC_RES_RES1_I915(dev_priv, pipe) _MMIO_TRANS2((dev_priv), (pipe), _PIPE_CRC_RES_RES1_A_I915) #define _PIPE_CRC_RES_RES2_A_G4X 0x60080 /* g4x+ */ -#define PIPE_CRC_RES_RES2_G4X(dev_priv, pipe) _MMIO_TRANS2(dev_priv, pipe, _PIPE_CRC_RES_RES2_A_G4X) +#define PIPE_CRC_RES_RES2_G4X(dev_priv, pipe) _MMIO_TRANS2((dev_priv), (pipe), _PIPE_CRC_RES_RES2_A_G4X) /* ivb */ #define _PIPE_CRC_EXP_2_A_IVB 0x60054 @@ -117,36 +117,36 @@ /* ivb */ #define _PIPE_CRC_RES_1_A_IVB 0x60064 #define _PIPE_CRC_RES_1_B_IVB 0x61064 -#define PIPE_CRC_RES_1_IVB(pipe) _MMIO_PIPE(pipe, _PIPE_CRC_RES_1_A_IVB, _PIPE_CRC_RES_1_B_IVB) +#define PIPE_CRC_RES_1_IVB(pipe) _MMIO_PIPE((pipe), _PIPE_CRC_RES_1_A_IVB, _PIPE_CRC_RES_1_B_IVB) /* ivb */ #define _PIPE_CRC_RES_2_A_IVB 0x60068 #define _PIPE_CRC_RES_2_B_IVB 0x61068 -#define PIPE_CRC_RES_2_IVB(pipe) _MMIO_PIPE(pipe, _PIPE_CRC_RES_2_A_IVB, _PIPE_CRC_RES_2_B_IVB) +#define PIPE_CRC_RES_2_IVB(pipe) _MMIO_PIPE((pipe), _PIPE_CRC_RES_2_A_IVB, _PIPE_CRC_RES_2_B_IVB) /* ivb */ #define _PIPE_CRC_RES_3_A_IVB 0x6006c #define _PIPE_CRC_RES_3_B_IVB 0x6106c -#define PIPE_CRC_RES_3_IVB(pipe) _MMIO_PIPE(pipe, _PIPE_CRC_RES_3_A_IVB, _PIPE_CRC_RES_3_B_IVB) +#define PIPE_CRC_RES_3_IVB(pipe) _MMIO_PIPE((pipe), _PIPE_CRC_RES_3_A_IVB, _PIPE_CRC_RES_3_B_IVB) /* ivb */ #define _PIPE_CRC_RES_4_A_IVB 0x60070 #define _PIPE_CRC_RES_4_B_IVB 0x61070 -#define PIPE_CRC_RES_4_IVB(pipe) _MMIO_PIPE(pipe, _PIPE_CRC_RES_4_A_IVB, _PIPE_CRC_RES_4_B_IVB) +#define PIPE_CRC_RES_4_IVB(pipe) _MMIO_PIPE((pipe), _PIPE_CRC_RES_4_A_IVB, _PIPE_CRC_RES_4_B_IVB) /* ivb */ #define _PIPE_CRC_RES_5_A_IVB 0x60074 #define _PIPE_CRC_RES_5_B_IVB 0x61074 -#define PIPE_CRC_RES_5_IVB(pipe) _MMIO_PIPE(pipe, _PIPE_CRC_RES_5_A_IVB, _PIPE_CRC_RES_5_B_IVB) +#define PIPE_CRC_RES_5_IVB(pipe) _MMIO_PIPE((pipe), _PIPE_CRC_RES_5_A_IVB, _PIPE_CRC_RES_5_B_IVB) /* hsw+ */ #define _PIPE_CRC_EXP_A_HSW0x60054 #define _PIPE_CRC_EXP_B_HSW0x61054 -#define PIPE_CRC_EXP_HSW(pipe) _MMIO_PIPE(pipe, _PIPE_CRC_EXP_A_HSW, _PIPE_CRC_EXP_B_HSW) +#define PIPE_CRC_EXP_HSW(pipe) _MMIO_PIPE((pipe), _PIPE_CRC_EXP_A_HSW, _PIPE_CRC_EXP_B_HSW) /* hsw+ */ #define _PIPE_CRC_RES_A_HSW0x60064 #define _PIPE_CRC_RES_B_HSW0x61064 -#define PIPE_CRC_RES_HSW(pipe) _MMIO_PIPE(pipe, _PIPE_CRC_RES_A_HSW, _PIPE_CRC_RES_B_HSW) +#define PIPE_CRC_RES_HSW(pipe) _MMIO_PIPE((pipe), _PIPE_CRC_RES_A_HSW, _PIPE_CRC_RE
[PATCH v12 2/9] drm-tip: 2024y-06m-05d-09h-52m-50s UTC integration manifest
From: Ville Syrjälä --- integration-manifest | 28 1 file changed, 28 insertions(+) create mode 100644 integration-manifest diff --git a/integration-manifest b/integration-manifest new file mode 100644 index ..d840964a2208 --- /dev/null +++ b/integration-manifest @@ -0,0 +1,28 @@ +drm drm-fixes c3f38fa61af77b49866b006939479069cd451173 + Linux 6.10-rc2 +drm-misc drm-misc-fixes 629f2b4e05225e53125aaf7ff0b87d5d53897128 + drm/panel: sitronix-st7789v: Add check for of_drm_get_panel_orientation +drm-intel drm-intel-fixes c3f38fa61af77b49866b006939479069cd451173 + Linux 6.10-rc2 +drm-xe drm-xe-fixes 0698ff57bf327d9a5735a898f78161b8dada160b + drm/xe/pf: Update the LMTT when freeing VF GT config +drm drm-next c3f38fa61af77b49866b006939479069cd451173 + Linux 6.10-rc2 +drm-misc drm-misc-next-fixes 539d33b5783804f22a62bd62ff463dfd1cef4265 + drm/komeda: remove unused struct 'gamma_curve_segment' +drm-intel drm-intel-next-fixes 1613e604df0cd359cf2a7fbd9be7a0bcfacfabd0 + Linux 6.10-rc1 +drm-xe drm-xe-next-fixes d69c3d4b53829097b8948d6791ea32c07de3faab + drm/xe/ads: Use flexible-array +drm-misc drm-misc-next 310ec03841a36e3f45fb528f0dfdfe5b9e84b037 + dma-buf: align fd_flags and heap_flags with dma_heap_allocation_data +drm-intel drm-intel-next 17419f5c6d409bcce5d094279a6fed5d5dbdba12 + drm/i915: Protect CRC reg macro arguments for consistency +drm-intel drm-intel-gt-next a09d2327a9ba8e3f5be238bc1b7ca2809255b464 + drm/i915/gt: Fix CCS id's calculation for CCS mode setting +drm-xe drm-xe-next 8b01f970ee890574b3607c85781354a765c849bd + drm/xe: Use missing lock in relay_needs_worker +drm-intel topic/core-for-CI a51e92845f99879e971677482b0f5fd96ef10d3c + thunderbolt: Add Kconfig option to disable PCIe tunneling +drm-xe topic/xe-for-CI 428c3ef38ef5565140b2104f0d3dafdae9056ca9 + Revert "drm/xe/gsc: define GSC FW for LNL" -- 2.25.1
[PATCH v12 3/9] gpu/drm/i915: Update indentation for VRR registers and bits
Update the indentation for the VRR register definition and its bits, and fix checkpatch issues to ensure smooth movement of registers and bits. Signed-off-by: Mitul Golani --- drivers/gpu/drm/i915/i915_reg.h | 9 + 1 file changed, 5 insertions(+), 4 deletions(-) diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index 0569a23b83b2..6b39211b5469 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -1152,7 +1152,7 @@ #define _TRANS_VRR_CTL_B 0x61420 #define _TRANS_VRR_CTL_C 0x62420 #define _TRANS_VRR_CTL_D 0x63420 -#define TRANS_VRR_CTL(dev_priv, trans) _MMIO_TRANS2(dev_priv, trans, _TRANS_VRR_CTL_A) +#define TRANS_VRR_CTL(dev_priv, trans) _MMIO_TRANS2(dev_priv, trans, _TRANS_VRR_CTL_A) #define VRR_CTL_VRR_ENABLE REG_BIT(31) #define VRR_CTL_IGN_MAX_SHIFTREG_BIT(30) #define VRR_CTL_FLIP_LINE_EN REG_BIT(29) @@ -1160,7 +1160,8 @@ #define VRR_CTL_PIPELINE_FULL(x) REG_FIELD_PREP(VRR_CTL_PIPELINE_FULL_MASK, (x)) #define VRR_CTL_PIPELINE_FULL_OVERRIDE REG_BIT(0) #define XELPD_VRR_CTL_VRR_GUARDBAND_MASK REG_GENMASK(15, 0) -#define XELPD_VRR_CTL_VRR_GUARDBAND(x) REG_FIELD_PREP(XELPD_VRR_CTL_VRR_GUARDBAND_MASK, (x)) +#define XELPD_VRR_CTL_VRR_GUARDBAND(x) REG_FIELD_PREP(XELPD_VRR_CTL_VRR_GUARDBAND_MASK, \ + (x)) #define _TRANS_VRR_VMAX_A 0x60424 #define _TRANS_VRR_VMAX_B 0x61424 @@ -1190,7 +1191,7 @@ #define _TRANS_VRR_STATUS_B0x6142C #define _TRANS_VRR_STATUS_C0x6242C #define _TRANS_VRR_STATUS_D0x6342C -#define TRANS_VRR_STATUS(dev_priv, trans) _MMIO_TRANS2(dev_priv, trans, _TRANS_VRR_STATUS_A) +#define TRANS_VRR_STATUS(dev_priv, trans) _MMIO_TRANS2(dev_priv, trans, _TRANS_VRR_STATUS_A) #define VRR_STATUS_VMAX_REACHED REG_BIT(31) #define VRR_STATUS_NOFLIP_TILL_BNDR REG_BIT(30) #define VRR_STATUS_FLIP_BEF_BNDR REG_BIT(29) @@ -1241,7 +1242,7 @@ #define TRANS_PUSH_SEND REG_BIT(30) #define _TRANS_VRR_VSYNC_A 0x60078 -#define TRANS_VRR_VSYNC(dev_priv, trans) _MMIO_TRANS2(dev_priv, trans, _TRANS_VRR_VSYNC_A) +#define TRANS_VRR_VSYNC(dev_priv, trans) _MMIO_TRANS2(dev_priv, trans, _TRANS_VRR_VSYNC_A) #define VRR_VSYNC_END_MASK REG_GENMASK(28, 16) #define VRR_VSYNC_END(vsync_end) REG_FIELD_PREP(VRR_VSYNC_END_MASK, (vsync_end)) #define VRR_VSYNC_START_MASK REG_GENMASK(12, 0) -- 2.25.1
[PATCH v12 4/9] drm/i915: Separate VRR related register definitions
Move VRR related register definitions to a separate file called intel_vrr_regs.h. Signed-off-by: Mitul Golani --- drivers/gpu/drm/i915/display/intel_vrr.c | 1 + drivers/gpu/drm/i915/display/intel_vrr_regs.h | 112 ++ drivers/gpu/drm/i915/i915_reg.h | 101 3 files changed, 113 insertions(+), 101 deletions(-) create mode 100644 drivers/gpu/drm/i915/display/intel_vrr_regs.h diff --git a/drivers/gpu/drm/i915/display/intel_vrr.c b/drivers/gpu/drm/i915/display/intel_vrr.c index 5f3657aa8313..871e6e6a184a 100644 --- a/drivers/gpu/drm/i915/display/intel_vrr.c +++ b/drivers/gpu/drm/i915/display/intel_vrr.c @@ -9,6 +9,7 @@ #include "intel_de.h" #include "intel_display_types.h" #include "intel_vrr.h" +#include "intel_vrr_regs.h" #include "intel_dp.h" bool intel_vrr_is_capable(struct intel_connector *connector) diff --git a/drivers/gpu/drm/i915/display/intel_vrr_regs.h b/drivers/gpu/drm/i915/display/intel_vrr_regs.h new file mode 100644 index ..d4eb74ee72a7 --- /dev/null +++ b/drivers/gpu/drm/i915/display/intel_vrr_regs.h @@ -0,0 +1,112 @@ +/* SPDX-License-Identifier: MIT */ +/* + * Copyright © 2024 Intel Corporation + */ + +#ifndef __INTEL_VRR_REGS_H__ +#define __INTEL_VRR_REGS_H__ + +#include "intel_display_reg_defs.h" + +/* VRR registers */ +#define _TRANS_VRR_CTL_A0x60420 +#define _TRANS_VRR_CTL_B0x61420 +#define _TRANS_VRR_CTL_C0x62420 +#define _TRANS_VRR_CTL_D0x63420 +#define TRANS_VRR_CTL(dev_priv, trans) _MMIO_TRANS2(dev_priv, trans, _TRANS_VRR_CTL_A) +#define VRR_CTL_VRR_ENABLEREG_BIT(31) +#define VRR_CTL_IGN_MAX_SHIFT REG_BIT(30) +#define VRR_CTL_FLIP_LINE_EN REG_BIT(29) +#define VRR_CTL_PIPELINE_FULL_MASKREG_GENMASK(10, 3) +#define VRR_CTL_PIPELINE_FULL(x) REG_FIELD_PREP(VRR_CTL_PIPELINE_FULL_MASK, (x)) +#define VRR_CTL_PIPELINE_FULL_OVERRIDEREG_BIT(0) +#define XELPD_VRR_CTL_VRR_GUARDBAND_MASK REG_GENMASK(15, 0) +#define XELPD_VRR_CTL_VRR_GUARDBAND(x) REG_FIELD_PREP(XELPD_VRR_CTL_VRR_GUARDBAND_MASK, \ + (x)) + +#define _TRANS_VRR_VMAX_A 0x60424 +#define _TRANS_VRR_VMAX_B 0x61424 +#define _TRANS_VRR_VMAX_C 0x62424 +#define _TRANS_VRR_VMAX_D 0x63424 +#define TRANS_VRR_VMAX(dev_priv, trans) _MMIO_TRANS2(dev_priv, trans, _TRANS_VRR_VMAX_A) +#define VRR_VMAX_MASK REG_GENMASK(19, 0) + +#define _TRANS_VRR_VMIN_A 0x60434 +#define _TRANS_VRR_VMIN_B 0x61434 +#define _TRANS_VRR_VMIN_C 0x62434 +#define _TRANS_VRR_VMIN_D 0x63434 +#define TRANS_VRR_VMIN(dev_priv, trans) _MMIO_TRANS2(dev_priv, trans, _TRANS_VRR_VMIN_A) +#define VRR_VMIN_MASK REG_GENMASK(15, 0) + +#define _TRANS_VRR_VMAXSHIFT_A 0x60428 +#define _TRANS_VRR_VMAXSHIFT_B 0x61428 +#define _TRANS_VRR_VMAXSHIFT_C 0x62428 +#define _TRANS_VRR_VMAXSHIFT_D 0x63428 +#define TRANS_VRR_VMAXSHIFT(dev_priv, trans)_MMIO_TRANS2(dev_priv, trans, \ + _TRANS_VRR_VMAXSHIFT_A) +#define VRR_VMAXSHIFT_DEC_MASKREG_GENMASK(29, 16) +#define VRR_VMAXSHIFT_DEC REG_BIT(16) +#define VRR_VMAXSHIFT_INC_MASKREG_GENMASK(12, 0) + +#define _TRANS_VRR_STATUS_A 0x6042C +#define _TRANS_VRR_STATUS_B 0x6142C +#define _TRANS_VRR_STATUS_C 0x6242C +#define _TRANS_VRR_STATUS_D 0x6342C +#define TRANS_VRR_STATUS(dev_priv, trans) _MMIO_TRANS2(dev_priv, trans, _TRANS_VRR_STATUS_A) +#define VRR_STATUS_VMAX_REACHED REG_BIT(31) +#define VRR_STATUS_NOFLIP_TILL_BNDR REG_BIT(30) +#define VRR_STATUS_FLIP_BEF_BNDR REG_BIT(29) +#define VRR_STATUS_NO_FLIP_FRAME REG_BIT(28) +#define VRR_STATUS_VRR_EN_LIVEREG_BIT(27) +#define VRR_STATUS_FLIPS_SERVICED REG_BIT(26) +#define VRR_STATUS_VBLANK_MASKREG_GENMASK(22, 20) +#define STATUS_FSM_IDLE REG_FIELD_PREP(VRR_STATUS_VBLANK_MASK, 0) +#define STATUS_FSM_WAIT_TILL_FDB REG_FIELD_PREP(VRR_STATUS_VBLANK_MASK, 1) +#define STATUS_FSM_WAIT_TILL_FS REG_FIELD_PREP(VRR_STATUS_VBLANK_MASK, 2) +#define STATUS_FSM_WAIT_TILL_FLIP REG_FIELD_PREP(VRR_STATUS_VBLANK_MASK, 3) +#define STATUS_FSM_PIPELINE_FILL REG_FIELD_PREP(VRR_STATUS_VBLANK_MASK, 4) +#define STATUS_FSM_ACTIVE REG_FIELD_PREP(VRR_STATUS_VBLANK_MASK, 5) +#define STATUS_FSM_LEGACY_VBLANK REG_FIELD_PREP(VRR_STATUS_VBLANK_MASK, 6) + +#define _TRANS_VRR_VTOTAL_PREV_A0x60480 +#define _TRANS_VRR_VTOTAL_PREV_B0x61480 +#define _TRANS_VRR_VTOTAL_PREV_C0x62480 +#define _TRANS_VRR_VTOTAL_PREV_D0x63480 +#define TRANS_VRR_VTOTAL_PREV
[PATCH v12 5/9] drm/i915: Define and compute Transcoder CMRR registers
Add register definitions for Transcoder Fixed Average
Vtotal mode/CMRR function, with the necessary bitfields.
Compute these registers when CMRR is enabled, extending
Adaptive refresh rate capabilities.
--v2:
- Use intel_de_read64_2x32 in intel_vrr_get_config. [Jani]
- Fix indent and order based on register offset. [Jani]
--v3:
- Removing RFC tag.
--v4:
- Update place holder for CMRR register definition. (Jani)
--v5:
- Add CMRR register definitions to a separate file intel_vrr_reg.h.
--v6:
- Fixed indentation. (Jani)
- Add dependency header intel_display_reg_defs.h. (Jani)
- Rename file name to intel_vrr_regs.h instead of reg.h (Jani)
--v7:
- Remove adding CMRR flag to vrr_ctl register during set_transcoder_timing,
as it is already being done during intel_vrr_enable. (Ankit)
Signed-off-by: Mitul Golani
Reviewed-by: Ankit Nautiyal
---
drivers/gpu/drm/i915/display/intel_display.c | 23 ++-
.../drm/i915/display/intel_display_types.h| 6 +
drivers/gpu/drm/i915/display/intel_vrr.c | 20
drivers/gpu/drm/i915/display/intel_vrr_regs.h | 14 +++
4 files changed, 62 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display.c
b/drivers/gpu/drm/i915/display/intel_display.c
index 7370acdd6b8b..29d750d2e6f7 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -1005,6 +1005,13 @@ static bool vrr_params_changed(const struct
intel_crtc_state *old_crtc_state,
old_crtc_state->vrr.pipeline_full !=
new_crtc_state->vrr.pipeline_full;
}
+static bool cmrr_params_changed(const struct intel_crtc_state *old_crtc_state,
+ const struct intel_crtc_state *new_crtc_state)
+{
+ return old_crtc_state->cmrr.cmrr_m != new_crtc_state->cmrr.cmrr_m ||
+ old_crtc_state->cmrr.cmrr_n != new_crtc_state->cmrr.cmrr_n;
+}
+
static bool vrr_enabling(const struct intel_crtc_state *old_crtc_state,
const struct intel_crtc_state *new_crtc_state)
{
@@ -5054,6 +5061,16 @@ intel_pipe_config_compare(const struct intel_crtc_state
*current_config,
} \
} while (0)
+#define PIPE_CONF_CHECK_LLI(name) do { \
+ if (current_config->name != pipe_config->name) { \
+ pipe_config_mismatch(&p, fastset, crtc, __stringify(name), \
+"(expected %lli, found %lli)", \
+current_config->name, \
+pipe_config->name); \
+ ret = false; \
+ } \
+} while (0)
+
#define PIPE_CONF_CHECK_BOOL(name) do { \
if (current_config->name != pipe_config->name) { \
BUILD_BUG_ON_MSG(!__same_type(current_config->name, bool), \
@@ -5432,10 +5449,13 @@ intel_pipe_config_compare(const struct intel_crtc_state
*current_config,
PIPE_CONF_CHECK_I(vrr.guardband);
PIPE_CONF_CHECK_I(vrr.vsync_start);
PIPE_CONF_CHECK_I(vrr.vsync_end);
+ PIPE_CONF_CHECK_LLI(cmrr.cmrr_m);
+ PIPE_CONF_CHECK_LLI(cmrr.cmrr_n);
}
#undef PIPE_CONF_CHECK_X
#undef PIPE_CONF_CHECK_I
+#undef PIPE_CONF_CHECK_LLI
#undef PIPE_CONF_CHECK_BOOL
#undef PIPE_CONF_CHECK_P
#undef PIPE_CONF_CHECK_FLAGS
@@ -6824,7 +6844,8 @@ static void intel_pre_update_crtc(struct
intel_atomic_state *state,
intel_crtc_needs_fastset(new_crtc_state))
icl_set_pipe_chicken(new_crtc_state);
- if (vrr_params_changed(old_crtc_state, new_crtc_state))
+ if (vrr_params_changed(old_crtc_state, new_crtc_state) ||
+ cmrr_params_changed(old_crtc_state, new_crtc_state))
intel_vrr_set_transcoder_timings(new_crtc_state);
}
diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h
b/drivers/gpu/drm/i915/display/intel_display_types.h
index 77609656317b..62ed3c9db94a 100644
--- a/drivers/gpu/drm/i915/display/intel_display_types.h
+++ b/drivers/gpu/drm/i915/display/intel_display_types.h
@@ -1401,6 +1401,12 @@ struct intel_crtc_state {
u32 vsync_end, vsync_start;
} vrr;
+ /* Content Match Refresh Rate state */
+ struct {
+ bool enable;
+ u64 cmrr_n, cmrr_m;
+ } cmrr;
+
/* Stream Splitter for eDP MSO */
struct {
bool enable;
diff --git a/drivers/gpu/drm/i915/display/intel_vrr.c
b/drivers/gpu/drm/i915/display/intel_vrr.c
index 871e6e6a184a..d2f854d9d18b 100644
--- a/drivers/gpu/drm/i915/display/intel_vrr.c
+++ b/drivers/gpu/drm/i915/display/intel_vrr.c
@@ -219,6 +219,17 @@ void intel_vrr_set_transcoder_timings(const struct
intel_crtc_state *crtc_state)
return;
}
+ if (crtc_state->cmrr.enable) {
+ intel_de_write(dev_priv, TRANS_CMRR_M_HI(dev_priv,
cpu_transcoder),
+
[PATCH v12 6/9] drm/i915: Update trans_vrr_ctl flag when cmrr is computed
Add/update trans_vrr_ctl flag when crtc_state->cmrr.enable
is set, With this commit setting the stage for subsequent
CMRR enablement.
--v2:
- Check pipe active state in cmrr enabling. [Jani]
- Remove usage of bitwise OR on booleans. [Jani]
- Revert unrelated changes. [Jani]
- Update intel_vrr_enable, vrr and cmrr enable conditions. [Jani]
- Simplify whole if-ladder in intel_vrr_enable. [Jani]
- Revert patch restructuring mistakes in intel_vrr_get_config. [Jani]
--v3:
- Check pipe active state in cmrr disabling.[Jani]
- Correct messed up condition in intel_vrr_enable. [Jani]
--v4:
- Removing RFC tag.
--v5:
- CMRR handling in co-existatnce of LRR and DRRS.
--v7:
- Rebase on top of AS SDP merge.
--v8:
- Remove cmrr_enabling/disabling and update commit message. (Ankit)
--v9:
- Revert removed line(Ankit).
Signed-off-by: Mitul Golani
Reviewed-by: Ankit Nautiyal
---
drivers/gpu/drm/i915/display/intel_vrr.c | 10 --
drivers/gpu/drm/i915/display/intel_vrr_regs.h | 2 ++
2 files changed, 10 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_vrr.c
b/drivers/gpu/drm/i915/display/intel_vrr.c
index d2f854d9d18b..19b364074de0 100644
--- a/drivers/gpu/drm/i915/display/intel_vrr.c
+++ b/drivers/gpu/drm/i915/display/intel_vrr.c
@@ -282,8 +282,14 @@ void intel_vrr_enable(const struct intel_crtc_state
*crtc_state)
VRR_VSYNC_END(crtc_state->vrr.vsync_end) |
VRR_VSYNC_START(crtc_state->vrr.vsync_start));
- intel_de_write(dev_priv, TRANS_VRR_CTL(dev_priv, cpu_transcoder),
- VRR_CTL_VRR_ENABLE | trans_vrr_ctl(crtc_state));
+ if (crtc_state->cmrr.enable) {
+ intel_de_write(dev_priv, TRANS_VRR_CTL(dev_priv,
cpu_transcoder),
+ VRR_CTL_VRR_ENABLE | VRR_CTL_CMRR_ENABLE |
+ trans_vrr_ctl(crtc_state));
+ } else {
+ intel_de_write(dev_priv, TRANS_VRR_CTL(dev_priv,
cpu_transcoder),
+ VRR_CTL_VRR_ENABLE | trans_vrr_ctl(crtc_state));
+ }
}
void intel_vrr_disable(const struct intel_crtc_state *old_crtc_state)
diff --git a/drivers/gpu/drm/i915/display/intel_vrr_regs.h
b/drivers/gpu/drm/i915/display/intel_vrr_regs.h
index 1aeb0cd45068..577b0abb66db 100644
--- a/drivers/gpu/drm/i915/display/intel_vrr_regs.h
+++ b/drivers/gpu/drm/i915/display/intel_vrr_regs.h
@@ -123,4 +123,6 @@
#define _TRANS_CMRR_N_HI_A 0x604FC
#define TRANS_CMRR_N_HI(dev_priv, trans)_MMIO_TRANS2(dev_priv, trans,
_TRANS_CMRR_N_HI_A)
+#define VRR_CTL_CMRR_ENABLEREG_BIT(27)
+
#endif /* __INTEL_VRR_REGS__ */
--
2.25.1
[PATCH v12 7/9] drm/dp: Add refresh rate divider to struct representing AS SDP
Add target_rr_divider to structure representing AS SDP.
It is valid only in FAVT mode, sink device ignores the bit in AVT
mode.
--v2:
- Update commit header and send patch to dri-devel.
Signed-off-by: Mitul Golani
Reviewed-by: Arun R Murthy
---
include/drm/display/drm_dp_helper.h | 1 +
1 file changed, 1 insertion(+)
diff --git a/include/drm/display/drm_dp_helper.h
b/include/drm/display/drm_dp_helper.h
index 8defcc399f42..ea03e1dd26ba 100644
--- a/include/drm/display/drm_dp_helper.h
+++ b/include/drm/display/drm_dp_helper.h
@@ -122,6 +122,7 @@ struct drm_dp_as_sdp {
int target_rr;
int duration_incr_ms;
int duration_decr_ms;
+ bool target_rr_divider;
enum operation_mode mode;
};
--
2.25.1
[PATCH v12 9/9] drm/i915/display: Compute Adaptive sync SDP params
Compute params for Adaptive Sync SDP when Fixed Average Vtotal
mode is enabled.
--v2:
Since vrr.enable is set in case of cmrr also, handle accordingly(Ankit).
--v3:
- Since vrr.enable is set in case of cmrr also, handle
accordingly(Ankit).
- check cmrr.enable when CMRR flags are set during intel_dp_compute_as_sdp.
--v4:
- Use drm_mode_vrefresh instead of manual calculation (Ankit).
Signed-off-by: Mitul Golani
Reviewed-by: Ankit Nautiyal
---
drivers/gpu/drm/i915/display/intel_dp.c | 14 +++---
1 file changed, 11 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c
b/drivers/gpu/drm/i915/display/intel_dp.c
index ac81b172b1ec..b5915c23302f 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -2637,11 +2637,19 @@ static void intel_dp_compute_as_sdp(struct intel_dp
*intel_dp,
/* Currently only DP_AS_SDP_AVT_FIXED_VTOTAL mode supported */
as_sdp->sdp_type = DP_SDP_ADAPTIVE_SYNC;
as_sdp->length = 0x9;
- as_sdp->mode = DP_AS_SDP_AVT_FIXED_VTOTAL;
- as_sdp->vtotal = adjusted_mode->vtotal;
- as_sdp->target_rr = 0;
as_sdp->duration_incr_ms = 0;
as_sdp->duration_incr_ms = 0;
+
+ if (crtc_state->cmrr.enable) {
+ as_sdp->mode = DP_AS_SDP_FAVT_TRR_REACHED;
+ as_sdp->vtotal = adjusted_mode->vtotal;
+ as_sdp->target_rr = drm_mode_vrefresh(adjusted_mode);
+ as_sdp->target_rr_divider = true;
+ } else {
+ as_sdp->mode = DP_AS_SDP_AVT_FIXED_VTOTAL;
+ as_sdp->vtotal = adjusted_mode->vtotal;
+ as_sdp->target_rr = 0;
+ }
}
static void intel_dp_compute_vsc_sdp(struct intel_dp *intel_dp,
--
2.25.1
[PATCH v12 8/9] drm/i915/display: Add support for pack and unpack
Add support of pack and unpack for target_rr_divider. --v2: - Set Target Refresh Rate Divider bit when related AS SDP bit is set (Ankit). --v3: - target_rr_divider is bools so set accordingly (Ankit). Signed-off-by: Mitul Golani Reviewed-by: Ankit Nautiyal --- drivers/gpu/drm/i915/display/intel_dp.c | 4 1 file changed, 4 insertions(+) diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c index fd054e16850d..ac81b172b1ec 100644 --- a/drivers/gpu/drm/i915/display/intel_dp.c +++ b/drivers/gpu/drm/i915/display/intel_dp.c @@ -4232,6 +4232,9 @@ static ssize_t intel_dp_as_sdp_pack(const struct drm_dp_as_sdp *as_sdp, sdp->db[3] = as_sdp->target_rr & 0xFF; sdp->db[4] = (as_sdp->target_rr >> 8) & 0x3; + if (as_sdp->target_rr_divider) + sdp->db[4] |= 0x20; + return length; } @@ -4413,6 +4416,7 @@ int intel_dp_as_sdp_unpack(struct drm_dp_as_sdp *as_sdp, as_sdp->mode = sdp->db[0] & DP_ADAPTIVE_SYNC_SDP_OPERATION_MODE; as_sdp->vtotal = (sdp->db[2] << 8) | sdp->db[1]; as_sdp->target_rr = (u64)sdp->db[3] | ((u64)sdp->db[4] & 0x3); + as_sdp->target_rr_divider = sdp->db[4] & 0x20 ? true : false; return 0; } -- 2.25.1
Re: [PATCH 2/3] drm/xe: drop redundant W=1 warnings from Makefile
On Thu, 23 May 2024, Jani Nikula wrote:
> Since commit a61ddb4393ad ("drm: enable (most) W=1 warnings by default
> across the subsystem"), most of the extra warnings in the driver
> Makefile are redundant. Remove them.
>
> Note that -Wmissing-declarations and -Wmissing-prototypes are always
> enabled by default in scripts/Makefile.extrawarn.
>
> Signed-off-by: Jani Nikula
Pushed this patch to drm-xe-next with Lucas' irc ack.
BR,
Jani.
> ---
> drivers/gpu/drm/xe/Makefile | 25 +
> 1 file changed, 1 insertion(+), 24 deletions(-)
>
> diff --git a/drivers/gpu/drm/xe/Makefile b/drivers/gpu/drm/xe/Makefile
> index c9f067b8f54d..f4366cb958be 100644
> --- a/drivers/gpu/drm/xe/Makefile
> +++ b/drivers/gpu/drm/xe/Makefile
> @@ -3,31 +3,8 @@
> # Makefile for the drm device driver. This driver provides support for the
> # Direct Rendering Infrastructure (DRI) in XFree86 4.1.0 and higher.
>
> -# Unconditionally enable W=1 warnings locally
> -# --- begin copy-paste W=1 warnings from scripts/Makefile.extrawarn
> -subdir-ccflags-y += -Wextra -Wunused -Wno-unused-parameter
> -subdir-ccflags-y += -Wmissing-declarations
> -subdir-ccflags-y += $(call cc-option, -Wrestrict)
> -subdir-ccflags-y += -Wmissing-format-attribute
> -subdir-ccflags-y += -Wmissing-prototypes
> -subdir-ccflags-y += -Wold-style-definition
> -subdir-ccflags-y += -Wmissing-include-dirs
> -subdir-ccflags-y += $(call cc-option, -Wunused-but-set-variable)
> -subdir-ccflags-y += $(call cc-option, -Wunused-const-variable)
> -subdir-ccflags-y += $(call cc-option, -Wpacked-not-aligned)
> -subdir-ccflags-y += $(call cc-option, -Wformat-overflow)
> +# Enable W=1 warnings not enabled in drm subsystem Makefile
> subdir-ccflags-y += $(call cc-option, -Wformat-truncation)
> -subdir-ccflags-y += $(call cc-option, -Wstringop-truncation)
> -# The following turn off the warnings enabled by -Wextra
> -ifeq ($(findstring 2, $(KBUILD_EXTRA_WARN)),)
> -subdir-ccflags-y += -Wno-missing-field-initializers
> -subdir-ccflags-y += -Wno-type-limits
> -subdir-ccflags-y += -Wno-shift-negative-value
> -endif
> -ifeq ($(findstring 3, $(KBUILD_EXTRA_WARN)),)
> -subdir-ccflags-y += -Wno-sign-compare
> -endif
> -# --- end copy-paste
>
> # Enable -Werror in CI and development
> subdir-ccflags-$(CONFIG_DRM_XE_WERROR) += -Werror
--
Jani Nikula, Intel
Re: [PATCH 3/3] drm/amdgpu: drop redundant W=1 warnings from Makefile
On Thu, 23 May 2024, Jani Nikula wrote:
> Since commit a61ddb4393ad ("drm: enable (most) W=1 warnings by default
> across the subsystem"), most of the extra warnings in the driver
> Makefile are redundant. Remove them.
>
> Note that -Wmissing-declarations and -Wmissing-prototypes are always
> enabled by default in scripts/Makefile.extrawarn.
>
> Signed-off-by: Jani Nikula
Alex, this one's for you to do whatever you want. ;)
BR,
Jani.
> ---
> drivers/gpu/drm/amd/amdgpu/Makefile | 18 +-
> 1 file changed, 1 insertion(+), 17 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/Makefile
> b/drivers/gpu/drm/amd/amdgpu/Makefile
> index 1f6b56ec99f6..9508d0b5708e 100644
> --- a/drivers/gpu/drm/amd/amdgpu/Makefile
> +++ b/drivers/gpu/drm/amd/amdgpu/Makefile
> @@ -39,23 +39,7 @@ ccflags-y := -I$(FULL_AMD_PATH)/include/asic_reg \
> -I$(FULL_AMD_DISPLAY_PATH)/amdgpu_dm \
> -I$(FULL_AMD_PATH)/amdkfd
>
> -subdir-ccflags-y := -Wextra
> -subdir-ccflags-y += -Wunused
> -subdir-ccflags-y += -Wmissing-prototypes
> -subdir-ccflags-y += -Wmissing-declarations
> -subdir-ccflags-y += -Wmissing-include-dirs
> -subdir-ccflags-y += -Wold-style-definition
> -subdir-ccflags-y += -Wmissing-format-attribute
> -# Need this to avoid recursive variable evaluation issues
> -cond-flags := $(call cc-option, -Wunused-but-set-variable) \
> - $(call cc-option, -Wunused-const-variable) \
> - $(call cc-option, -Wstringop-truncation) \
> - $(call cc-option, -Wpacked-not-aligned)
> -subdir-ccflags-y += $(cond-flags)
> -subdir-ccflags-y += -Wno-unused-parameter
> -subdir-ccflags-y += -Wno-type-limits
> -subdir-ccflags-y += -Wno-sign-compare
> -subdir-ccflags-y += -Wno-missing-field-initializers
> +# Locally disable W=1 warnings enabled in drm subsystem Makefile
> subdir-ccflags-y += -Wno-override-init
> subdir-ccflags-$(CONFIG_DRM_AMDGPU_WERROR) += -Werror
--
Jani Nikula, Intel
Re: [PATCH 06/12] drm/i915: convert fsb_freq and mem_freq to kHz
On Wed, 05 Jun 2024, Ville Syrjälä wrote:
> On Tue, May 28, 2024 at 05:24:55PM +0300, Jani Nikula wrote:
>> We'll want to use fsb frequency for deriving GT clock and rawclk
>> frequencies in the future. Increase the accuracy by converting to
>> kHz. Do the same for mem freq to be aligned.
>
> mem_freq is used in:
> - gen5_rps_init() -> needs to be adjusted, with care taken for rounding
> - intel_gt_pm_frequency_dump() -> should probably be nuked from here
Good catches. Sloppy on my part.
Thanks,
Jani.
>
>>
>> Round the frequencies ending in 666 to 667.
>>
>> Signed-off-by: Jani Nikula
>> ---
>> drivers/gpu/drm/i915/display/i9xx_wm.c | 6 ++--
>> drivers/gpu/drm/i915/gt/intel_rps.c| 4 +--
>> drivers/gpu/drm/i915/soc/intel_dram.c | 50 +-
>> 3 files changed, 30 insertions(+), 30 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/i915/display/i9xx_wm.c
>> b/drivers/gpu/drm/i915/display/i9xx_wm.c
>> index 8b8a0f305c3a..08c5d122af8f 100644
>> --- a/drivers/gpu/drm/i915/display/i9xx_wm.c
>> +++ b/drivers/gpu/drm/i915/display/i9xx_wm.c
>> @@ -83,14 +83,14 @@ static const struct cxsr_latency
>> *pnv_get_cxsr_latency(struct drm_i915_private *
>>
>> if (is_desktop == latency->is_desktop &&
>> i915->is_ddr3 == latency->is_ddr3 &&
>> -i915->fsb_freq == latency->fsb_freq &&
>> -i915->mem_freq == latency->mem_freq)
>> +DIV_ROUND_CLOSEST(i915->fsb_freq, 1000) ==
>> latency->fsb_freq &&
>> +DIV_ROUND_CLOSEST(i915->mem_freq, 1000) ==
>> latency->mem_freq)
>> return latency;
>> }
>>
>> err:
>> drm_dbg_kms(&i915->drm,
>> -"Could not find CxSR latency for DDR%s, FSB %u MHz, MEM %u
>> MHz\n",
>> +"Could not find CxSR latency for DDR%s, FSB %u kHz, MEM %u
>> kHz\n",
>> i915->is_ddr3 ? "3" : "2", i915->fsb_freq, i915->mem_freq);
>>
>> return NULL;
>> diff --git a/drivers/gpu/drm/i915/gt/intel_rps.c
>> b/drivers/gpu/drm/i915/gt/intel_rps.c
>> index c9cb2a391942..5d3de1cddcf6 100644
>> --- a/drivers/gpu/drm/i915/gt/intel_rps.c
>> +++ b/drivers/gpu/drm/i915/gt/intel_rps.c
>> @@ -280,9 +280,9 @@ static void gen5_rps_init(struct intel_rps *rps)
>> u32 rgvmodectl;
>> int c_m, i;
>>
>> -if (i915->fsb_freq <= 3200)
>> +if (i915->fsb_freq <= 320)
>> c_m = 0;
>> -else if (i915->fsb_freq <= 4800)
>> +else if (i915->fsb_freq <= 480)
>> c_m = 1;
>> else
>> c_m = 2;
>> diff --git a/drivers/gpu/drm/i915/soc/intel_dram.c
>> b/drivers/gpu/drm/i915/soc/intel_dram.c
>> index 266ed6cfa485..ace9372244a4 100644
>> --- a/drivers/gpu/drm/i915/soc/intel_dram.c
>> +++ b/drivers/gpu/drm/i915/soc/intel_dram.c
>> @@ -56,11 +56,11 @@ static unsigned int pnv_mem_freq(struct drm_i915_private
>> *dev_priv)
>>
>> switch (tmp & CLKCFG_MEM_MASK) {
>> case CLKCFG_MEM_533:
>> -return 533;
>> +return 53;
>> case CLKCFG_MEM_667:
>> -return 667;
>> +return 67;
>> case CLKCFG_MEM_800:
>> -return 800;
>> +return 80;
>> }
>>
>> return 0;
>> @@ -73,13 +73,13 @@ static unsigned int ilk_mem_freq(struct drm_i915_private
>> *dev_priv)
>> ddrpll = intel_uncore_read16(&dev_priv->uncore, DDRMPLL1);
>> switch (ddrpll & 0xff) {
>> case 0xc:
>> -return 800;
>> +return 80;
>> case 0x10:
>> -return 1066;
>> +return 107;
>> case 0x14:
>> -return 1333;
>> +return 133;
>> case 0x18:
>> -return 1600;
>> +return 160;
>> default:
>> drm_dbg(&dev_priv->drm, "unknown memory frequency 0x%02x\n",
>> ddrpll & 0xff);
>> @@ -97,9 +97,9 @@ static unsigned int chv_mem_freq(struct drm_i915_private
>> *i915)
>>
>> switch ((val >> 2) & 0x7) {
>> case 3:
>> -return 2000;
>> +return 200;
>> default:
>> -return 1600;
>> +return 160;
>> }
>> }
>>
>> @@ -114,11 +114,11 @@ static unsigned int vlv_mem_freq(struct
>> drm_i915_private *i915)
>> switch ((val >> 6) & 3) {
>> case 0:
>> case 1:
>> -return 800;
>> +return 80;
>> case 2:
>> -return 1066;
>> +return 107;
>> case 3:
>> -return 1333;
>> +return 133;
>> }
>>
>> return 0;
>> @@ -139,7 +139,7 @@ static void detect_mem_freq(struct drm_i915_private
>> *i915)
>> i915->is_ddr3 = pnv_is_ddr3(i915);
>>
>> if (i915->mem_freq)
>> -drm_dbg(&i915->drm, "DDR speed: %d MHz\n", i915->mem_freq);
>> +drm_dbg(&i915->drm, "DDR speed: %d kHz\n", i915->mem_freq);
>> }
>>
>> static unsigned int pnv_fsb_freq(struct drm_i915_pr
RE: [PATCH v12 1/9] drm/i915: Protect CRC reg macro arguments for consistency
Hi, I made a mistake while creating patch and this was sent by mistake. Please ignore this patch. I will rebase my patch series and send the correct version. Sorry for inconvenience. Regards, Mitul > -Original Message- > From: Intel-gfx On Behalf Of Mitul > Golani > Sent: Wednesday, June 5, 2024 5:58 PM > To: intel-gfx@lists.freedesktop.org > Cc: dri-de...@lists.freedesktop.org; Nautiyal, Ankit K > ; Nikula, Jani > Subject: [PATCH v12 1/9] drm/i915: Protect CRC reg macro arguments for > consistency > > From: Ville Syrjälä > > It's probably a good idea to start protecting all macro arguments to avoid any > cargo-cult mistakes when people go looking for examples of how to define > these things. > > Signed-off-by: Ville Syrjälä > Link: https://patchwork.freedesktop.org/patch/msgid/20240531115342.2763- > 8-ville.syrj...@linux.intel.com > Reviewed-by: Jani Nikula > --- > .../drm/i915/display/intel_pipe_crc_regs.h| 26 +-- > 1 file changed, 13 insertions(+), 13 deletions(-) > > diff --git a/drivers/gpu/drm/i915/display/intel_pipe_crc_regs.h > b/drivers/gpu/drm/i915/display/intel_pipe_crc_regs.h > index 383910a785f6..4e65f51d34e6 100644 > --- a/drivers/gpu/drm/i915/display/intel_pipe_crc_regs.h > +++ b/drivers/gpu/drm/i915/display/intel_pipe_crc_regs.h > @@ -9,7 +9,7 @@ > #include "intel_display_reg_defs.h" > > #define _PIPE_CRC_CTL_A 0x60050 > -#define PIPE_CRC_CTL(dev_priv, pipe) _MMIO_TRANS2(dev_priv, > pipe, _PIPE_CRC_CTL_A) > +#define PIPE_CRC_CTL(dev_priv, pipe) _MMIO_TRANS2((dev_priv), > (pipe), _PIPE_CRC_CTL_A) > #define PIPE_CRC_ENABLEREG_BIT(31) > /* skl+ source selection */ > #define PIPE_CRC_SOURCE_MASK_SKL REG_GENMASK(30, 28) > @@ -76,19 +76,19 @@ > #define PIPE_CRC_EXP_RES2_MASK REG_BIT(22, 0) /* pre-ivb */ > > #define _PIPE_CRC_RES_RED_A 0x60060 > -#define PIPE_CRC_RES_RED(dev_priv, pipe) _MMIO_TRANS2(dev_priv, > pipe, _PIPE_CRC_RES_RED_A) > +#define PIPE_CRC_RES_RED(dev_priv, pipe) _MMIO_TRANS2((dev_priv), > (pipe), _PIPE_CRC_RES_RED_A) > > #define _PIPE_CRC_RES_GREEN_A0x60064 > -#define PIPE_CRC_RES_GREEN(dev_priv, pipe) _MMIO_TRANS2(dev_priv, > pipe, _PIPE_CRC_RES_GREEN_A) > +#define PIPE_CRC_RES_GREEN(dev_priv, pipe) _MMIO_TRANS2((dev_priv), > (pipe), _PIPE_CRC_RES_GREEN_A) > > #define _PIPE_CRC_RES_BLUE_A 0x60068 > -#define PIPE_CRC_RES_BLUE(dev_priv, pipe)_MMIO_TRANS2(dev_priv, > pipe, _PIPE_CRC_RES_BLUE_A) > +#define PIPE_CRC_RES_BLUE(dev_priv, pipe)_MMIO_TRANS2((dev_priv), > (pipe), _PIPE_CRC_RES_BLUE_A) > > #define _PIPE_CRC_RES_RES1_A_I9150x6006c /* i915+ */ > -#define PIPE_CRC_RES_RES1_I915(dev_priv, pipe) > _MMIO_TRANS2(dev_priv, pipe, _PIPE_CRC_RES_RES1_A_I915) > +#define PIPE_CRC_RES_RES1_I915(dev_priv, pipe) > _MMIO_TRANS2((dev_priv), (pipe), _PIPE_CRC_RES_RES1_A_I915) > > #define _PIPE_CRC_RES_RES2_A_G4X 0x60080 /* g4x+ */ > -#define PIPE_CRC_RES_RES2_G4X(dev_priv, pipe) > _MMIO_TRANS2(dev_priv, pipe, _PIPE_CRC_RES_RES2_A_G4X) > +#define PIPE_CRC_RES_RES2_G4X(dev_priv, pipe) > _MMIO_TRANS2((dev_priv), (pipe), _PIPE_CRC_RES_RES2_A_G4X) > > /* ivb */ > #define _PIPE_CRC_EXP_2_A_IVB0x60054 > @@ -117,36 +117,36 @@ > /* ivb */ > #define _PIPE_CRC_RES_1_A_IVB0x60064 > #define _PIPE_CRC_RES_1_B_IVB0x61064 > -#define PIPE_CRC_RES_1_IVB(pipe) _MMIO_PIPE(pipe, > _PIPE_CRC_RES_1_A_IVB, _PIPE_CRC_RES_1_B_IVB) > +#define PIPE_CRC_RES_1_IVB(pipe) _MMIO_PIPE((pipe), > _PIPE_CRC_RES_1_A_IVB, _PIPE_CRC_RES_1_B_IVB) > > /* ivb */ > #define _PIPE_CRC_RES_2_A_IVB0x60068 > #define _PIPE_CRC_RES_2_B_IVB0x61068 > -#define PIPE_CRC_RES_2_IVB(pipe) _MMIO_PIPE(pipe, > _PIPE_CRC_RES_2_A_IVB, _PIPE_CRC_RES_2_B_IVB) > +#define PIPE_CRC_RES_2_IVB(pipe) _MMIO_PIPE((pipe), > _PIPE_CRC_RES_2_A_IVB, _PIPE_CRC_RES_2_B_IVB) > > /* ivb */ > #define _PIPE_CRC_RES_3_A_IVB0x6006c > #define _PIPE_CRC_RES_3_B_IVB0x6106c > -#define PIPE_CRC_RES_3_IVB(pipe) _MMIO_PIPE(pipe, > _PIPE_CRC_RES_3_A_IVB, _PIPE_CRC_RES_3_B_IVB) > +#define PIPE_CRC_RES_3_IVB(pipe) _MMIO_PIPE((pipe), > _PIPE_CRC_RES_3_A_IVB, _PIPE_CRC_RES_3_B_IVB) > > /* ivb */ > #define _PIPE_CRC_RES_4_A_IVB0x60070 > #define _PIPE_CRC_RES_4_B_IVB0x61070 > -#define PIPE_CRC_RES_4_IVB(pipe) _MMIO_PIPE(pipe, > _PIPE_CRC_RES_4_A_IVB, _PIPE_CRC_RES_4_B_IVB) > +#define PIPE_CRC_RES_4_IVB(pipe) _MMIO_PIPE((pipe), > _PIPE_CRC_RES_4_A_IVB, _PIPE_CRC_RES_4_B_IVB) > > /* ivb */ > #define _PIPE_CRC_RES_5_A_IVB0x60074 > #define _PIPE_CRC_RES_5_B_IVB0x61074 > -#define PIPE_CRC_RES_5_IVB(pipe) _MMIO_PIPE(pipe, > _PIPE_CRC_RES_5_A_IVB, _PIPE_CRC_RES_5_B_IVB) > +#define PIPE_CRC_RE
RE: [PATCH v12 2/9] drm-tip: 2024y-06m-05d-09h-52m-50s UTC integration manifest
Hi, Similar to Patch #1 this was sent by mistake. Please ignore this patch. I will rebase my patch series and send the correct version. Sorry for inconvenience. Regards, Mitul > -Original Message- > From: Intel-gfx On Behalf Of Mitul > Golani > Sent: Wednesday, June 5, 2024 5:58 PM > To: intel-gfx@lists.freedesktop.org > Cc: dri-de...@lists.freedesktop.org; Nautiyal, Ankit K > ; Nikula, Jani > Subject: [PATCH v12 2/9] drm-tip: 2024y-06m-05d-09h-52m-50s UTC > integration manifest > > From: Ville Syrjälä > > --- > integration-manifest | 28 > 1 file changed, 28 insertions(+) > create mode 100644 integration-manifest > > diff --git a/integration-manifest b/integration-manifest new file mode 100644 > index ..d840964a2208 > --- /dev/null > +++ b/integration-manifest > @@ -0,0 +1,28 @@ > +drm drm-fixes c3f38fa61af77b49866b006939479069cd451173 > + Linux 6.10-rc2 > +drm-misc drm-misc-fixes 629f2b4e05225e53125aaf7ff0b87d5d53897128 > + drm/panel: sitronix-st7789v: Add check for > +of_drm_get_panel_orientation drm-intel drm-intel-fixes > c3f38fa61af77b49866b006939479069cd451173 > + Linux 6.10-rc2 > +drm-xe drm-xe-fixes 0698ff57bf327d9a5735a898f78161b8dada160b > + drm/xe/pf: Update the LMTT when freeing VF GT config drm drm-next > +c3f38fa61af77b49866b006939479069cd451173 > + Linux 6.10-rc2 > +drm-misc drm-misc-next-fixes > 539d33b5783804f22a62bd62ff463dfd1cef4265 > + drm/komeda: remove unused struct 'gamma_curve_segment' > +drm-intel drm-intel-next-fixes 1613e604df0cd359cf2a7fbd9be7a0bcfacfabd0 > + Linux 6.10-rc1 > +drm-xe drm-xe-next-fixes d69c3d4b53829097b8948d6791ea32c07de3faab > + drm/xe/ads: Use flexible-array > +drm-misc drm-misc-next 310ec03841a36e3f45fb528f0dfdfe5b9e84b037 > + dma-buf: align fd_flags and heap_flags with > dma_heap_allocation_data > +drm-intel drm-intel-next 17419f5c6d409bcce5d094279a6fed5d5dbdba12 > + drm/i915: Protect CRC reg macro arguments for consistency drm-intel > +drm-intel-gt-next a09d2327a9ba8e3f5be238bc1b7ca2809255b464 > + drm/i915/gt: Fix CCS id's calculation for CCS mode setting drm-xe > +drm-xe-next 8b01f970ee890574b3607c85781354a765c849bd > + drm/xe: Use missing lock in relay_needs_worker drm-intel > +topic/core-for-CI a51e92845f99879e971677482b0f5fd96ef10d3c > + thunderbolt: Add Kconfig option to disable PCIe tunneling drm-xe > +topic/xe-for-CI 428c3ef38ef5565140b2104f0d3dafdae9056ca9 > + Revert "drm/xe/gsc: define GSC FW for LNL" > -- > 2.25.1
Re: [PATCH v1 1/1] treewide: Align match_string() with sysfs_match_string()
On Sun, Jun 02, 2024 at 06:57:12PM +0300, Andy Shevchenko wrote: > Make two APIs look similar. Hence convert match_string() to be > a 2-argument macro. In order to avoid unneeded churn, convert > all users as well. There is no functional change intended. > > Signed-off-by: Andy Shevchenko > --- > > Compile tested with `make allyesconfig` and `make allmodconfig` > on x86_64, arm, aarch64, powerpc64 (8 builds total). > > I guess the best is to apply it to Linus' tree directly. > And now it seems a good timing as there are no new users > of this API either in v6.10-rcX, or in Linux Next. > > But if you think differently, tell me. > > arch/powerpc/xmon/xmon.c | 5 ++-- > arch/x86/kernel/cpu/mtrr/if.c | 4 +-- > crypto/asymmetric_keys/pkcs7_verify.c | 4 +-- > drivers/acpi/scan.c | 4 +-- > drivers/ata/pata_hpt366.c | 2 +- > drivers/ata/pata_hpt37x.c | 2 +- > drivers/base/property.c | 6 ++-- > drivers/char/ipmi/ipmi_msghandler.c | 2 +- > drivers/char/ipmi/ipmi_si_hardcode.c | 2 +- > drivers/clk/bcm/clk-bcm2835.c | 4 +-- > drivers/clk/rockchip/clk.c| 4 +-- > drivers/clk/tegra/clk-tegra124-emc.c | 7 ++--- > drivers/cpufreq/amd-pstate.c | 4 +-- > drivers/cpufreq/intel_pstate.c| 2 +- > .../intel/qat/qat_common/adf_cfg_services.c | 5 ++-- > .../gpu/drm/drm_panel_orientation_quirks.c| 2 +- > drivers/gpu/drm/i915/display/intel_pipe_crc.c | 2 +- > drivers/gpu/drm/nouveau/dispnv04/tvnv17.c | 4 +-- > drivers/gpu/drm/nouveau/dispnv50/crc.c| 2 +- > drivers/hwmon/ltc4282.c | 14 - > drivers/hwmon/nct6775-platform.c | 6 ++-- > drivers/hwtracing/intel_th/msu.c | 2 +- > drivers/i2c/busses/i2c-i801.c | 4 +-- > drivers/leds/leds-sun50i-a100.c | 2 +- > drivers/mfd/omap-usb-host.c | 2 +- > drivers/mmc/host/sdhci-xenon-phy.c| 13 - > drivers/mtd/nand/raw/nand_macronix.c | 10 ++- > .../net/ethernet/chelsio/cxgb4/cudbg_lib.c| 6 ++-- > .../net/wireless/intel/iwlwifi/mvm/debugfs.c | 2 +- > drivers/pci/pcie/aer.c| 2 +- > drivers/phy/mediatek/phy-mtk-tphy.c | 8 ++--- > drivers/phy/tegra/xusb.c | 4 +-- > drivers/pinctrl/mvebu/pinctrl-armada-37xx.c | 6 ++-- > drivers/pinctrl/pinmux.c | 6 ++-- > drivers/platform/x86/hp/hp-wmi.c | 29 +++ > drivers/platform/x86/msi-ec.c | 4 +-- > drivers/power/supply/ab8500_btemp.c | 2 +- > drivers/power/supply/ab8500_chargalg.c| 2 +- > drivers/power/supply/ab8500_charger.c | 2 +- > drivers/power/supply/ab8500_fg.c | 2 +- > drivers/staging/gdm724x/gdm_tty.c | 5 ++-- > .../int340x_thermal/processor_thermal_rfim.c | 4 +-- > .../processor_thermal_wt_req.c| 2 +- > drivers/usb/common/common.c | 8 ++--- > drivers/usb/dwc3/dwc3-rtk.c | 2 +- > drivers/usb/typec/class.c | 14 - > drivers/usb/typec/tipd/core.c | 3 +- > drivers/video/fbdev/pxafb.c | 4 +-- > fs/bcachefs/compress.c| 2 +- > fs/bcachefs/opts.c| 4 +-- > fs/bcachefs/util.c| 4 +-- > fs/ubifs/auth.c | 8 ++--- > include/linux/string.h| 12 +++- > kernel/cgroup/rdma.c | 2 +- > kernel/sched/debug.c | 2 +- > kernel/trace/trace.c | 4 +-- > kernel/trace/trace_osnoise.c | 4 +-- > lib/dynamic_debug.c | 5 ++-- > lib/string_helpers.c | 6 ++-- > mm/mempolicy.c| 4 +-- > mm/vmpressure.c | 4 +-- > security/apparmor/lsm.c | 9 +++--- > security/integrity/ima/ima_main.c | 2 +- > security/integrity/ima/ima_policy.c | 2 +- > sound/firewire/oxfw/oxfw.c| 2 +- > sound/pci/oxygen/oxygen_mixer.c | 2 +- > sound/soc/codecs/max98088.c | 2 +- > sound/soc/codecs/max98095.c | 2 +- > sound/soc/soc-dapm.c | 5 ++-- > 69 files changed, 150 insertions(+), 174 deletions(-) > > diff --git a/arch/powerpc/xmon/xmon.c b/arch/powerpc/xmon/xmon.c > index bd4813bad317..f479cc62674a 100644 > --- a/arch/powerpc/xmon/xmon.c > +++ b/arch/powerpc/xmon/xmon.c > @@ -3478,8 +3478,7 @@ skipbl(void) > return c; > } > > -#define N_PTREGS
Re: [PATCH v1 1/1] treewide: Align match_string() with sysfs_match_string()
Il 02/06/24 17:57, Andy Shevchenko ha scritto: Make two APIs look similar. Hence convert match_string() to be a 2-argument macro. In order to avoid unneeded churn, convert all users as well. There is no functional change intended. Signed-off-by: Andy Shevchenko For MediaTek Reviewed-by: AngeloGioacchino Del Regno
Re: [PATCH v1 1/1] treewide: Align match_string() with sysfs_match_string()
On Tue, 04 Jun 2024 10:45:37 +0300 Jani Nikula wrote: > On Sun, 02 Jun 2024, Andy Shevchenko > wrote: > > Make two APIs look similar. Hence convert match_string() to be > > a 2-argument macro. In order to avoid unneeded churn, convert > > all users as well. There is no functional change intended. > > Why do we think it's a good idea to increase and normalize the use of > double-underscore function names across the kernel, like > __match_string() in this case? It should mean "reserved for the > implementation, not to be called directly". > > If it's to be used directly, it should be named accordingly, right? > > Being in line with __sysfs_match_string() isn't a great argument alone, > because this adds three times the number of __match_string() calls than > there are __sysfs_match_string() calls. It's not a good model to follow. > Arguably both should be renamed. Agreed. I want to get rid of any functions starting with an underscore except for those that are basically the same function used internally for convenience. Perhaps "match_string_dynamic()"? Where it is used for dynamically allocated arrays without known size. Or, allow a third parameter for dynamic arrays. #define match_string(_a, _s, ...) char ___STR[] = __stringify((__VA_ARGS__)); \ if (sizeof(___STR) > 3) \ __match_string(_a, _s, ##__VA_ARGS__); \ else\ __match_string(_a, _s, ARRAY_SIZE(_a)); What the above stringify((__VA_ARGS__)) does is to check the size of any args added to match_string(). if there isn't any, it will turn into: "()\0", which is of size 3. If you add an argument, it will be: "()\0", which will have a size greater than three. (trace_printk() does this trick in include/linux/kernel.h). This way, both: match_string(array, sting); or match_string(array, string, size); will work. -- Steve
Re: [PATCH v1 1/1] treewide: Align match_string() with sysfs_match_string()
On Tue, 4 Jun 2024 at 11:25, Rodrigo Vivi wrote: > > (I believe that the new _match_string(str1, size, str2) deserves a better > name, > but since I'm bad with naming stuff, I don't have any good suggestion) I hated the enormous cc list, so I didn't reply to all. But clearly everybody else is just doing so. Anyway, here's my NAK for this patch with explanation: https://lore.kernel.org/all/CAHk-=wg5f99-gzpetsasjd0jb0jgcdmmpehrxctt4_i83h8...@mail.gmail.com/ and part of it was the naming, but there were other oddities there too. Linus
Re: [PATCH v1 1/1] treewide: Align match_string() with sysfs_match_string()
On Sun, Jun 02, 2024 at 06:57:12PM +0300, Andy Shevchenko wrote: > Make two APIs look similar. Hence convert match_string() to be > a 2-argument macro. In order to avoid unneeded churn, convert > all users as well. There is no functional change intended. > diff --git a/drivers/cpufreq/amd-pstate.c b/drivers/cpufreq/amd-pstate.c > index 1b7e82a0ad2e..b6f52f44625f 100644 > --- a/drivers/cpufreq/amd-pstate.c > +++ b/drivers/cpufreq/amd-pstate.c > @@ -1117,9 +1117,9 @@ static ssize_t store_energy_performance_preference( > if (ret != 1) > return -EINVAL; > > - ret = match_string(energy_perf_strings, -1, str_preference); > + ret = __match_string(energy_perf_strings, -1, str_preference); > if (ret < 0) > - return -EINVAL; > + return ret; > > mutex_lock(&amd_pstate_limits_lock); > ret = amd_pstate_set_energy_pref_index(cpudata, ret); For drivers/cpufreq/amd-pstate.c Acked-by: Gautham R. Shenoy -- Thanks and Regards gautham.
✗ Fi.CI.CHECKPATCH: warning for Panel Replay eDP support (rev7)
== Series Details == Series: Panel Replay eDP support (rev7) URL : https://patchwork.freedesktop.org/series/133684/ State : warning == Summary == Error: dim checkpatch failed 58d77df5a406 drm/i915/alpm: Do not use fast_wake_lines for aux less wake time c88c51ffc880 drm/i915/alpm: Write also AUX Less Wake lines into ALPM_CTL 8a6da99681bf drm/i915/display: Take panel replay into account in vsc sdp unpacking d30d994293ae drm/i915/display: Skip Panel Replay on pipe comparison if no active planes dbeae5c71686 drm/display: Add missing Panel Replay Enable SU Region ET bit 08d039c5fae8 drm/i915/psr: Split enabling sink for PSR and Panel Replay -:30: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis #30: FILE: drivers/gpu/drm/i915/display/intel_psr.c:690: +static void _panel_replay_enable_sink(struct intel_dp *intel_dp, +const struct intel_crtc_state *crtc_state) -:56: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis #56: FILE: drivers/gpu/drm/i915/display/intel_psr.c:708: +static void _psr_enable_sink(struct intel_dp *intel_dp, + const struct intel_crtc_state *crtc_state) total: 0 errors, 0 warnings, 2 checks, 107 lines checked aa55db234d5a drm/i915/alpm: Make alpm support checks non-static 6508138be2bb drm/i915/psr: Use intel_alpm_aux_wake_supported instead of local variable 781f9c969607 drm/i915/psr: Add Panel Replay support to intel_psr2_config_et_valid 3a3ff5d7aacd drm/i915/psr: Print Panel Replay status instead of frame lock status 93a47fc8f4c6 drm/i915/psr: Move vblank length check to separate function cdbb50bbd2c4 drm/i915/psr: Take into account SU SDP scanline indication in vblank check -:13: WARNING:COMMIT_LOG_LONG_LINE: Prefer a maximum 75 chars per line (possible unwrapped commit description?) #13: PSR2_CTL[ SU SDP scanline indication ] = 0: (TRANS_VBLANK Vertical Blank End- TRANS_VBLANK Vertical Blank Start) > PSR2_CTL Block Count Number value in lines total: 0 errors, 1 warnings, 0 checks, 9 lines checked 0528a2f1ae66 drm/i915/psr: Check vblank against IO buffer wake time on Lunarlake 6c7064b1eae4 dmr/i915/psr: Wake time is aux less wake time for Panel Replay eb51bbcf2f64 drm/i915/psr: Check panel ALPM capability for eDP Panel Replay 9fc7c1222152 drm/i915/psr: Inform Panel Replay source support on eDP as well 0b76eb0066f2 drm/i915/psr: enable sink for eDP1.5 Panel Replay 1171daebc2e8 drm/i915/psr: Check panel Early Transport capability for eDP PR d3edd4407ff8 drm/i915/psr: Perfrom psr2 checks related to ALPM for Panel Replay e452c662970e drm/i915/psr: Add Panel Replay compute_config helper 6e181aaea9f3 drm/i915/psr: 128b/132b Panel Replay is not supported on eDP 6b139f7228ad drm/i915/psr: HW will not allow PR on eDP when HDCP enabled a316167dae81 drm/i915/psr: Check Early Transport for Panel Replay as well 22ac33c073dc drm/i915/psr: Modify dg2_activate_panel_replay to support eDP 0514724f5b34 drm/i915/psr: Add new debug bit to disable Panel Replay f89f919cb3aa Revert "drm/i915/psr: Disable early transport by default"
✗ Fi.CI.SPARSE: warning for Panel Replay eDP support (rev7)
== Series Details == Series: Panel Replay eDP support (rev7) URL : https://patchwork.freedesktop.org/series/133684/ State : warning == Summary == Error: dim sparse failed Sparse version: v0.6.2 Fast mode used, each commit won't be checked separately.
[PATCH 1/2] drm/i915/bios: Define block 46 chromaticity coordinates properly
From: Ville Syrjälä
The VBT spec does a very poor job of defining how the chromaticity
coordinates in block 46 are laid out. After double checking the
Windows implementation it turns out these more or less match the
EDID definition, where the 10bit values are split into 2bit + 8bit
chunks. Adjust our struct definition to reflect that.
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/display/intel_vbt_defs.h | 27 ---
1 file changed, 17 insertions(+), 10 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_vbt_defs.h
b/drivers/gpu/drm/i915/display/intel_vbt_defs.h
index 862c5923b83d..da8694771f69 100644
--- a/drivers/gpu/drm/i915/display/intel_vbt_defs.h
+++ b/drivers/gpu/drm/i915/display/intel_vbt_defs.h
@@ -1376,16 +1376,23 @@ struct chromaticity {
u8 chromaticity_from_edid_base_block:1;
u8 rsvd:6;
- u8 red_green;
- u8 blue_white;
- u8 red_x;
- u8 red_y;
- u8 green_x;
- u8 green_y;
- u8 blue_x;
- u8 blue_y;
- u8 white_x;
- u8 white_y;
+ u8 green_y_lo:2;
+ u8 green_x_lo:2;
+ u8 red_y_lo:2;
+ u8 red_x_lo:2;
+ u8 white_y_lo:2;
+ u8 white_x_lo:2;
+ u8 blue_y_lo:2;
+ u8 blue_x_lo:2;
+
+ u8 red_x_hi;
+ u8 red_y_hi;
+ u8 green_x_hi;
+ u8 green_y_hi;
+ u8 blue_x_hi;
+ u8 blue_y_hi;
+ u8 white_x_hi;
+ u8 white_y_hi;
} __packed;
struct bdb_chromaticity {
--
2.44.1
[PATCH 2/2] drm/i915/bios: Define the "luminance and gamma" sub-struct of block 46
From: Ville Syrjälä
Since BDB version 211 block 46 has included more luminance and
gamma related information. Define it fully. The data is semi-based
on DisplayID v2.0 apparently.
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/display/intel_vbt_defs.h | 12
1 file changed, 12 insertions(+)
diff --git a/drivers/gpu/drm/i915/display/intel_vbt_defs.h
b/drivers/gpu/drm/i915/display/intel_vbt_defs.h
index da8694771f69..1af8407e2081 100644
--- a/drivers/gpu/drm/i915/display/intel_vbt_defs.h
+++ b/drivers/gpu/drm/i915/display/intel_vbt_defs.h
@@ -1395,8 +1395,20 @@ struct chromaticity {
u8 white_y_hi;
} __packed;
+struct luminance_and_gamma {
+ u8 luminance_enable:1; /* 211+
*/
+ u8 gamma_enable:1; /* 211+
*/
+ u8 rsvd:6;
+
+ u16 min_luminance; /* 211+
*/
+ u16 max_luminance; /* 211+
*/
+ u16 one_percent_max_luminance; /* 211+
*/
+ u8 gamma; /* 211+
*/
+} __packed;
+
struct bdb_chromaticity {
struct chromaticity chromaticity[16];
+ struct luminance_and_gamma luminance_and_gamma[16]; /* 211+
*/
} __packed;
/*
--
2.44.1
✓ Fi.CI.BAT: success for Panel Replay eDP support (rev7)
== Series Details ==
Series: Panel Replay eDP support (rev7)
URL : https://patchwork.freedesktop.org/series/133684/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_14881 -> Patchwork_133684v7
Summary
---
**SUCCESS**
No regressions found.
External URL:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133684v7/index.html
Participating hosts (38 -> 35)
--
Additional (1): fi-kbl-8809g
Missing(4): bat-kbl-2 bat-dg2-11 fi-snb-2520m bat-arls-3
Possible new issues
---
Here are the unknown changes that may have been introduced in
Patchwork_133684v7:
### IGT changes ###
Suppressed
The following results come from untrusted machines, tests, or statuses.
They do not affect the overall result.
* igt@i915_module_load@load:
- {bat-mtlp-9}: [PASS][1] -> [ABORT][2]
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14881/bat-mtlp-9/igt@i915_module_l...@load.html
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133684v7/bat-mtlp-9/igt@i915_module_l...@load.html
Known issues
Here are the changes found in Patchwork_133684v7 that come from known issues:
### IGT changes ###
Issues hit
* igt@gem_huc_copy@huc-copy:
- fi-kbl-8809g: NOTRUN -> [SKIP][3] ([i915#2190])
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133684v7/fi-kbl-8809g/igt@gem_huc_c...@huc-copy.html
* igt@gem_lmem_swapping@basic:
- fi-kbl-8809g: NOTRUN -> [SKIP][4] ([i915#4613]) +3 other tests skip
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133684v7/fi-kbl-8809g/igt@gem_lmem_swapp...@basic.html
* igt@kms_force_connector_basic@force-load-detect:
- fi-kbl-8809g: NOTRUN -> [SKIP][5] +30 other tests skip
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133684v7/fi-kbl-8809g/igt@kms_force_connector_ba...@force-load-detect.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[i915#2190]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/2190
[i915#4613]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4613
Build changes
-
* Linux: CI_DRM_14881 -> Patchwork_133684v7
CI-20190529: 20190529
CI_DRM_14881: a494545483635d3d93d19e8f483f61e7d4198383 @
git://anongit.freedesktop.org/gfx-ci/linux
IGT_7878: eecd5683bd98cee3fc6bd3f26a1f053c897f6bdf @
https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
Patchwork_133684v7: a494545483635d3d93d19e8f483f61e7d4198383 @
git://anongit.freedesktop.org/gfx-ci/linux
== Logs ==
For more details see:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133684v7/index.html
✗ Fi.CI.CHECKPATCH: warning for drm/i915: bdw+ pipe interrupt stuff
== Series Details == Series: drm/i915: bdw+ pipe interrupt stuff URL : https://patchwork.freedesktop.org/series/134497/ State : warning == Summary == Error: dim checkpatch failed 1e0bd32b8a29 drm/i915: Use REG_BIT() for bdw+ pipe interrupts 8711ec9d6af6 drm/i915: Document bdw+ pipe interrupt bits 31327a5af06b drm/i915: Sort bdw+ pipe interrupt bits f181d09ea92d drm/i915: Extend GEN9_PIPE_PLANE_FLIP_DONE() to cover all universal planes -:39: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'plane_id' - possible side-effects? #39: FILE: drivers/gpu/drm/i915/i915_reg.h:2651: +#define GEN9_PIPE_PLANE_FLIP_DONE(plane_id) \ + REG_BIT(((plane_id) >= PLANE_5 ? 16 - PLANE_5 : 3 - PLANE_1) + (plane_id)) /* skl+ */ total: 0 errors, 0 warnings, 1 checks, 18 lines checked c5a53e5f5b21 drm/i915: Nuke the intermediate pipe fault bitmasks 45d472fc2a27 drm/i915: Enable pipeDMC fault interrupts on tgl+ 386081d16cde drm/i915: Enable plane/pipeDMC ATS fault interrupts on mtl
✓ Fi.CI.BAT: success for drm/i915: bdw+ pipe interrupt stuff
== Series Details ==
Series: drm/i915: bdw+ pipe interrupt stuff
URL : https://patchwork.freedesktop.org/series/134497/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_14881 -> Patchwork_134497v1
Summary
---
**SUCCESS**
No regressions found.
External URL:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_134497v1/index.html
Participating hosts (38 -> 37)
--
Additional (3): bat-dg2-14 bat-adlp-9 bat-adlp-6
Missing(4): bat-kbl-2 bat-dg2-11 fi-snb-2520m bat-arls-3
Possible new issues
---
Here are the unknown changes that may have been introduced in
Patchwork_134497v1:
### IGT changes ###
Suppressed
The following results come from untrusted machines, tests, or statuses.
They do not affect the overall result.
* igt@core_hotunplug@unbind-rebind:
- {bat-apl-1}:[PASS][1] -> [ABORT][2]
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14881/bat-apl-1/igt@core_hotunp...@unbind-rebind.html
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_134497v1/bat-apl-1/igt@core_hotunp...@unbind-rebind.html
Known issues
Here are the changes found in Patchwork_134497v1 that come from known issues:
### IGT changes ###
Issues hit
* igt@debugfs_test@basic-hwmon:
- bat-adlp-9: NOTRUN -> [SKIP][3] ([i915#9318])
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_134497v1/bat-adlp-9/igt@debugfs_t...@basic-hwmon.html
- bat-adlp-6: NOTRUN -> [SKIP][4] ([i915#9318])
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_134497v1/bat-adlp-6/igt@debugfs_t...@basic-hwmon.html
* igt@gem_lmem_swapping@basic:
- bat-adlp-9: NOTRUN -> [SKIP][5] ([i915#4613]) +3 other tests skip
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_134497v1/bat-adlp-9/igt@gem_lmem_swapp...@basic.html
* igt@gem_lmem_swapping@random-engines:
- bat-adlp-6: NOTRUN -> [SKIP][6] ([i915#4613]) +3 other tests skip
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_134497v1/bat-adlp-6/igt@gem_lmem_swapp...@random-engines.html
* igt@gem_mmap@basic:
- bat-dg2-14: NOTRUN -> [SKIP][7] ([i915#4083])
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_134497v1/bat-dg2-14/igt@gem_m...@basic.html
* igt@gem_render_tiled_blits@basic:
- bat-dg2-14: NOTRUN -> [SKIP][8] ([i915#4079]) +1 other test skip
[8]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_134497v1/bat-dg2-14/igt@gem_render_tiled_bl...@basic.html
* igt@gem_tiled_fence_blits@basic:
- bat-dg2-14: NOTRUN -> [SKIP][9] ([i915#4077]) +2 other tests skip
[9]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_134497v1/bat-dg2-14/igt@gem_tiled_fence_bl...@basic.html
* igt@gem_tiled_pread_basic:
- bat-adlp-6: NOTRUN -> [SKIP][10] ([i915#3282])
[10]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_134497v1/bat-adlp-6/igt@gem_tiled_pread_basic.html
- bat-adlp-9: NOTRUN -> [SKIP][11] ([i915#3282])
[11]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_134497v1/bat-adlp-9/igt@gem_tiled_pread_basic.html
* igt@i915_pm_rps@basic-api:
- bat-adlp-9: NOTRUN -> [SKIP][12] ([i915#6621])
[12]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_134497v1/bat-adlp-9/igt@i915_pm_...@basic-api.html
- bat-dg2-14: NOTRUN -> [SKIP][13] ([i915#6621])
[13]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_134497v1/bat-dg2-14/igt@i915_pm_...@basic-api.html
- bat-adlp-6: NOTRUN -> [SKIP][14] ([i915#6621])
[14]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_134497v1/bat-adlp-6/igt@i915_pm_...@basic-api.html
* igt@kms_addfb_basic@addfb25-y-tiled-small-legacy:
- bat-dg2-14: NOTRUN -> [SKIP][15] ([i915#5190])
[15]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_134497v1/bat-dg2-14/igt@kms_addfb_ba...@addfb25-y-tiled-small-legacy.html
* igt@kms_addfb_basic@basic-x-tiled-legacy:
- bat-dg2-14: NOTRUN -> [SKIP][16] ([i915#4212]) +7 other tests skip
[16]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_134497v1/bat-dg2-14/igt@kms_addfb_ba...@basic-x-tiled-legacy.html
* igt@kms_addfb_basic@basic-y-tiled-legacy:
- bat-dg2-14: NOTRUN -> [SKIP][17] ([i915#4215] / [i915#5190])
[17]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_134497v1/bat-dg2-14/igt@kms_addfb_ba...@basic-y-tiled-legacy.html
* igt@kms_cursor_legacy@basic-busy-flip-before-cursor-atomic:
- bat-adlp-9: NOTRUN -> [SKIP][18] ([i915#4103]) +1 other test skip
[18]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_134497v1/bat-adlp-9/igt@kms_cursor_leg...@basic-busy-flip-before-cursor-atomic.html
* igt@kms_cursor_legacy@basic-busy-flip-before-cursor-legacy:
- bat-dg2-14: NOTRUN -> [SKIP][19] ([i915#4103] / [i915#4213]) +1
other test ski
✗ Fi.CI.BUILD: failure for Implement CMRR Support (rev12)
== Series Details == Series: Implement CMRR Support (rev12) URL : https://patchwork.freedesktop.org/series/126443/ State : failure == Summary == Error: patch https://patchwork.freedesktop.org/api/1.0/series/126443/revisions/12/mbox/ not applied Applying: drm/i915: Protect CRC reg macro arguments for consistency Using index info to reconstruct a base tree... M drivers/gpu/drm/i915/display/intel_pipe_crc_regs.h Falling back to patching base and 3-way merge... No changes -- Patch already applied. Applying: drm-tip: 2024y-06m-05d-09h-52m-50s UTC integration manifest Using index info to reconstruct a base tree... Falling back to patching base and 3-way merge... CONFLICT (add/add): Merge conflict in integration-manifest Auto-merging integration-manifest error: Failed to merge in the changes. hint: Use 'git am --show-current-patch=diff' to see the failed patch Patch failed at 0002 drm-tip: 2024y-06m-05d-09h-52m-50s UTC integration manifest When you have resolved this problem, run "git am --continue". If you prefer to skip this patch, run "git am --skip" instead. To restore the original branch and stop patching, run "git am --abort". Build failed, no error log produced
✓ Fi.CI.BAT: success for drm/i915: Reduce DDI clock gating printk level from NOTICE to DEBUG
== Series Details == Series: drm/i915: Reduce DDI clock gating printk level from NOTICE to DEBUG URL : https://patchwork.freedesktop.org/series/134499/ State : success == Summary == CI Bug Log - changes from CI_DRM_14881 -> Patchwork_134499v1 Summary --- **SUCCESS** No regressions found. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_134499v1/index.html Participating hosts (38 -> 36) -- Missing(2): bat-mtlp-9 fi-snb-2520m Known issues Here are the changes found in Patchwork_134499v1 that come from known issues: ### IGT changes ### Possible fixes * igt@gem_lmem_swapping@basic@lmem0: - bat-dg2-9: [FAIL][1] ([i915#10378]) -> [PASS][2] [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14881/bat-dg2-9/igt@gem_lmem_swapping@ba...@lmem0.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_134499v1/bat-dg2-9/igt@gem_lmem_swapping@ba...@lmem0.html [i915#10378]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/10378 Build changes - * Linux: CI_DRM_14881 -> Patchwork_134499v1 CI-20190529: 20190529 CI_DRM_14881: a494545483635d3d93d19e8f483f61e7d4198383 @ git://anongit.freedesktop.org/gfx-ci/linux IGT_7878: eecd5683bd98cee3fc6bd3f26a1f053c897f6bdf @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git Patchwork_134499v1: a494545483635d3d93d19e8f483f61e7d4198383 @ git://anongit.freedesktop.org/gfx-ci/linux == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_134499v1/index.html
✗ Fi.CI.BAT: failure for series starting with [1/2] drm/i915/bios: Define block 46 chromaticity coordinates properly
== Series Details == Series: series starting with [1/2] drm/i915/bios: Define block 46 chromaticity coordinates properly URL : https://patchwork.freedesktop.org/series/134505/ State : failure == Summary == CI Bug Log - changes from CI_DRM_14881 -> Patchwork_134505v1 Summary --- **FAILURE** Serious unknown changes coming with Patchwork_134505v1 absolutely need to be verified manually. If you think the reported changes have nothing to do with the changes introduced in Patchwork_134505v1, please notify your bug team (i915-ci-in...@lists.freedesktop.org) to allow them to document this new failure mode, which will reduce false positives in CI. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_134505v1/index.html Participating hosts (38 -> 34) -- Additional (2): fi-kbl-8809g fi-bsw-n3050 Missing(6): bat-mtlp-9 bat-arls-3 fi-snb-2520m bat-dg2-11 bat-jsl-1 bat-mtlp-6 Possible new issues --- Here are the unknown changes that may have been introduced in Patchwork_134505v1: ### IGT changes ### Possible regressions * igt@i915_selftest@live@active: - fi-glk-j4005: [PASS][1] -> [DMESG-FAIL][2] [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14881/fi-glk-j4005/igt@i915_selftest@l...@active.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_134505v1/fi-glk-j4005/igt@i915_selftest@l...@active.html Known issues Here are the changes found in Patchwork_134505v1 that come from known issues: ### IGT changes ### Issues hit * igt@gem_huc_copy@huc-copy: - fi-kbl-8809g: NOTRUN -> [SKIP][3] ([i915#2190]) [3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_134505v1/fi-kbl-8809g/igt@gem_huc_c...@huc-copy.html * igt@gem_lmem_swapping@basic: - fi-kbl-8809g: NOTRUN -> [SKIP][4] ([i915#4613]) +3 other tests skip [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_134505v1/fi-kbl-8809g/igt@gem_lmem_swapp...@basic.html * igt@gem_lmem_swapping@random-engines: - fi-bsw-n3050: NOTRUN -> [SKIP][5] +19 other tests skip [5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_134505v1/fi-bsw-n3050/igt@gem_lmem_swapp...@random-engines.html * igt@kms_force_connector_basic@force-load-detect: - fi-kbl-8809g: NOTRUN -> [SKIP][6] +30 other tests skip [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_134505v1/fi-kbl-8809g/igt@kms_force_connector_ba...@force-load-detect.html [i915#2190]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/2190 [i915#4613]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4613 Build changes - * Linux: CI_DRM_14881 -> Patchwork_134505v1 CI-20190529: 20190529 CI_DRM_14881: a494545483635d3d93d19e8f483f61e7d4198383 @ git://anongit.freedesktop.org/gfx-ci/linux IGT_7878: eecd5683bd98cee3fc6bd3f26a1f053c897f6bdf @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git Patchwork_134505v1: a494545483635d3d93d19e8f483f61e7d4198383 @ git://anongit.freedesktop.org/gfx-ci/linux == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_134505v1/index.html
Re: [PATCH 1/3] drm/i915: Rename all bigjoiner to joiner
On Mon, Jun 03, 2024 at 02:25:49PM +0300, Stanislav Lisovskiy wrote:
> Lets unify both bigjoiner and ultrajoiner under simple "joiner" name,
> because in future we might have multiple configurations, involving
> multiple bigjoiners, ultrajoiner, however it is possible to use
> same api for handling both.
>
> Signed-off-by: Stanislav Lisovskiy
> ---
> .../gpu/drm/i915/display/intel_atomic_plane.c | 4 +-
> drivers/gpu/drm/i915/display/intel_cdclk.c| 8 +-
> .../drm/i915/display/intel_crtc_state_dump.c | 8 +-
> drivers/gpu/drm/i915/display/intel_cursor.c | 4 +-
> drivers/gpu/drm/i915/display/intel_ddi.c | 4 +-
> drivers/gpu/drm/i915/display/intel_display.c | 204 +-
> drivers/gpu/drm/i915/display/intel_display.h | 8 +-
> .../drm/i915/display/intel_display_debugfs.c | 10 +-
> .../drm/i915/display/intel_display_types.h| 4 +-
> drivers/gpu/drm/i915/display/intel_dp.c | 60 +++---
> drivers/gpu/drm/i915/display/intel_dp.h | 8 +-
> drivers/gpu/drm/i915/display/intel_dp_mst.c | 22 +-
> drivers/gpu/drm/i915/display/intel_drrs.c | 6 +-
> .../drm/i915/display/intel_modeset_setup.c| 38 ++--
> drivers/gpu/drm/i915/display/intel_psr.c | 6 +-
> drivers/gpu/drm/i915/display/intel_vdsc.c | 12 +-
> drivers/gpu/drm/i915/display/intel_vdsc.h | 2 +-
> drivers/gpu/drm/i915/display/intel_vrr.c | 2 +-
> .../drm/i915/display/skl_universal_plane.c| 4 +-
> 19 files changed, 207 insertions(+), 207 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_atomic_plane.c
> b/drivers/gpu/drm/i915/display/intel_atomic_plane.c
> index a4ce39a7f265..36798899222b 100644
> --- a/drivers/gpu/drm/i915/display/intel_atomic_plane.c
> +++ b/drivers/gpu/drm/i915/display/intel_atomic_plane.c
> @@ -2744,13 +2744,13 @@ static int intel_vdsc_min_cdclk(const struct
> intel_crtc_state *crtc_state)
>*
>* => CDCLK >= compressed_bpp * Pixel clock / (PPC * Bigjoiner
> Interface bits)
>*
> - * Since PPC = 2 with bigjoiner
> + * Since PPC = 2 with joiner
>* => CDCLK >= compressed_bpp * Pixel clock / 2 * Bigjoiner
> Interface bits
>*/
> - int bigjoiner_interface_bits = DISPLAY_VER(i915) >= 14 ? 36 :
> 24;
> + int joiner_interface_bits = DISPLAY_VER(i915) >= 14 ? 36 : 24;
> int min_cdclk_bj =
> (to_bpp_int_roundup(crtc_state->dsc.compressed_bpp_x16)
> *
> - pixel_clock) / (2 * bigjoiner_interface_bits);
> + pixel_clock) / (2 * joiner_interface_bits);
This stuff is specifically about bigjoiner/dsc.
>
> min_cdclk = max(min_cdclk, min_cdclk_bj);
> }
> diff --git a/drivers/gpu/drm/i915/display/intel_display_debugfs.c
> b/drivers/gpu/drm/i915/display/intel_display_debugfs.c
> index 86d9900c40af..f681234d5b0b 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_debugfs.c
> +++ b/drivers/gpu/drm/i915/display/intel_display_debugfs.c
> @@ -575,10 +575,10 @@ static void intel_crtc_info(struct seq_file *m, struct
> intel_crtc *crtc)
>
> intel_scaler_info(m, crtc);
>
> - if (crtc_state->bigjoiner_pipes)
> + if (crtc_state->joiner_pipes)
> seq_printf(m, "\tLinked to 0x%x pipes as a %s\n",
> -crtc_state->bigjoiner_pipes,
> -intel_crtc_is_bigjoiner_slave(crtc_state) ? "slave"
> : "master");
> +crtc_state->joiner_pipes,
> +intel_crtc_is_joiner_slave(crtc_state) ? "slave" :
> "master");
>
> for_each_intel_encoder_mask(&dev_priv->drm, encoder,
> crtc_state->uapi.encoder_mask)
> @@ -1544,8 +1544,8 @@ void intel_connector_debugfs_add(struct intel_connector
> *connector)
> if (DISPLAY_VER(i915) >= 11 &&
> (connector_type == DRM_MODE_CONNECTOR_DisplayPort ||
>connector_type == DRM_MODE_CONNECTOR_eDP)) {
> - debugfs_create_bool("i915_bigjoiner_force_enable", 0644, root,
> - &connector->force_bigjoiner_enable);
> + debugfs_create_bool("i915_joiner_force_enable", 0644, root,
> + &connector->force_joiner_enable);
That'll need changes in igt.
> }
>
> if (connector_type == DRM_MODE_CONNECTOR_DSI ||
> diff --git a/drivers/gpu/drm/i915/display/intel_dp.c
> b/drivers/gpu/drm/i915/display/intel_dp.c
> index fd054e16850d..a60e84e8773f 100644
> --- a/drivers/gpu/drm/i915/display/intel_dp.c
> +++ b/drivers/gpu/drm/i915/display/intel_dp.c
> @@ -437,7 +437,7 @@ int intel_dp_max_link_data_rate(struct intel_dp *intel_dp,
> return max_rate;
> }
>
> -bool intel_dp_has_bigjoiner(struct intel_dp *intel_dp)
> +bool intel_dp_has_joiner(struct intel_dp *intel_dp)
> {
> struct intel_digital_port *intel_dig_port =
[linux-next:master] BUILD REGRESSION 234cb065ad82915ff8d06ce01e01c3e640b674d2
tree/branch: https://git.kernel.org/pub/scm/linux/kernel/git/next/linux-next.git master branch HEAD: 234cb065ad82915ff8d06ce01e01c3e640b674d2 Add linux-next specific files for 20240605 Error/Warning reports: https://lore.kernel.org/oe-kbuild-all/202406051521.mroqvr5l-...@intel.com https://lore.kernel.org/oe-kbuild-all/202406051524.a12jqlqx-...@intel.com https://lore.kernel.org/oe-kbuild-all/202406051711.ds1sqz9n-...@intel.com https://lore.kernel.org/oe-kbuild-all/202406051855.9viyxbtb-...@intel.com Error/Warning: (recently discovered and may have been fixed) include/linux/container_of.h:20:54: error: 'struct ftrace_ops' has no member named 'list' include/linux/list.h:769:26: error: 'struct ftrace_ops' has no member named 'list' include/linux/stddef.h:16:33: error: 'struct ftrace_ops' has no member named 'list' kernel/trace/fgraph.c:883:43: error: 'struct ftrace_ops' has no member named 'subop_list' kernel/trace/fgraph.c:934:15: error: implicit declaration of function 'ftrace_startup_subops'; did you mean 'ftrace_startup'? [-Werror=implicit-function-declaration] kernel/trace/fgraph.c:973:9: error: implicit declaration of function 'ftrace_shutdown_subops'; did you mean 'ftrace_shutdown'? [-Werror=implicit-function-declaration] Error/Warning ids grouped by kconfigs: gcc_recent_errors |-- arc-randconfig-r061-20240605 | |-- drivers-gpu-drm-arm-display-komeda-komeda_dev.c:error:implicit-declaration-of-function-seq_puts | |-- drivers-gpu-drm-arm-display-komeda-komeda_dev.c:error:invalid-use-of-undefined-type-struct-seq_file | `-- drivers-gpu-drm-arm-display-komeda-komeda_dev.c:error:type-defaults-to-int-in-declaration-of-DEFINE_SHOW_ATTRIBUTE |-- csky-randconfig-r053-20240605 | |-- include-linux-container_of.h:error:struct-ftrace_ops-has-no-member-named-list | |-- include-linux-list.h:error:struct-ftrace_ops-has-no-member-named-list | |-- include-linux-stddef.h:error:struct-ftrace_ops-has-no-member-named-list | |-- kernel-trace-fgraph.c:error:implicit-declaration-of-function-ftrace_shutdown_subops | |-- kernel-trace-fgraph.c:error:implicit-declaration-of-function-ftrace_startup_subops | `-- kernel-trace-fgraph.c:error:struct-ftrace_ops-has-no-member-named-subop_list |-- i386-randconfig-061-20240605 | `-- drivers-hwmon-cros_ec_hwmon.c:sparse:sparse:cast-to-restricted-__le16 |-- i386-randconfig-063-20240605 | |-- kernel-trace-ftrace.c:sparse:sparse:incorrect-type-in-argument-(different-address-spaces)-expected-struct-ftrace_hash-B-got-struct-ftrace_hash-noderef-__rcu-filter_hash | |-- kernel-trace-ftrace.c:sparse:sparse:incorrect-type-in-argument-(different-address-spaces)-expected-struct-ftrace_hash-B-got-struct-ftrace_hash-noderef-__rcu-notrace_hash | |-- kernel-trace-ftrace.c:sparse:sparse:incorrect-type-in-argument-(different-address-spaces)-expected-struct-ftrace_hash-new_hash-got-struct-ftrace_hash-noderef-__rcu-filter_hash | |-- kernel-trace-ftrace.c:sparse:sparse:incorrect-type-in-argument-(different-address-spaces)-expected-struct-ftrace_hash-new_hash1-got-struct-ftrace_hash-noderef-__rcu-filter_hash | |-- kernel-trace-ftrace.c:sparse:sparse:incorrect-type-in-argument-(different-address-spaces)-expected-struct-ftrace_hash-new_hash2-got-struct-ftrace_hash-noderef-__rcu-filter_hash | |-- kernel-trace-ftrace.c:sparse:sparse:incorrect-type-in-argument-(different-address-spaces)-expected-struct-ftrace_hash-new_hash2-got-struct-ftrace_hash-noderef-__rcu-notrace_hash | |-- kernel-trace-ftrace.c:sparse:sparse:incorrect-type-in-argument-(different-address-spaces)-expected-struct-ftrace_hash-orig_hash-got-struct-ftrace_hash-noderef-__rcu | |-- kernel-trace-ftrace.c:sparse:sparse:incorrect-type-in-argument-(different-address-spaces)-expected-struct-ftrace_hash-src-got-struct-ftrace_hash-noderef-__rcu-filter_hash | |-- kernel-trace-ftrace.c:sparse:sparse:incorrect-type-in-argument-(different-address-spaces)-expected-struct-ftrace_hash-src-got-struct-ftrace_hash-noderef-__rcu-notrace_hash | |-- kernel-trace-ftrace.c:sparse:sparse:incorrect-type-in-assignment-(different-address-spaces)-expected-struct-ftrace_hash-noderef-__rcu-filter_hash-got-struct-ftrace_hash | |-- kernel-trace-ftrace.c:sparse:sparse:incorrect-type-in-assignment-(different-address-spaces)-expected-struct-ftrace_hash-noderef-__rcu-filter_hash-got-struct-ftrace_hash-assigned-filter_hash | |-- kernel-trace-ftrace.c:sparse:sparse:incorrect-type-in-assignment-(different-address-spaces)-expected-struct-ftrace_hash-noderef-__rcu-filter_hash-got-struct-ftrace_hash-save_filter_hash | |-- kernel-trace-ftrace.c:sparse:sparse:incorrect-type-in-assignment-(different-address-spaces)-expected-struct-ftrace_hash-noderef-__rcu-notrace_hash-got-struct-ftrace_hash | |-- kernel-trace-ftrace.c:sparse:sparse:incorrect-type-in-assignment-(different-address-spaces)-e
[PATCH v13 0/9] Implement CMRR Support
CMRR is a display feature that uses adaptive sync framework to vary Vtotal slightly to match the content rate exactly without frame drops. This feature is a variation of VRR where it varies Vtotal slightly (between additional 0 and 1 Vtotal scanlines) to match content rate exactly without frame drops using the adaptive sync framework. enable this feature by programing new registers for CMRR enable, CMRR_M, CMRR_N, vmin=vmax=flipline.The CMRR_M/CMRR_N ratio represents the fractional part in (actual refresh rate/target refresh rate) * origVTotal. --v6: - CMRR handling in co-existatnce of LRR and DRRS - Correct vtotal paramas accuracy and add 2 digit precision. --v7: - Rebased patches in-accordance to AS SDP merge. - Add neccessary gaurd to prevent crtc_state mismatch during intel_vrr_get_config. -v8: - Add support for AS SDP for CMRR. - update palce holder for CMRR register(Jani). - Make CMRR as subset of FAVT, as per comments in patch#3. -v9: - Add CMRR register definitions to separate intel_vrr_reg.h. - Remove cmrr_enabling/disabling, use vrr.enable instead. - Update AS SDP pack function to accomodate target_rr_divider. - Remove duplicated lines to compute vrr_vsync params. - Set cmrr.enable with a separate patch at last. -v10: - Separate VRR related register definitions. - Add dependency header intel_display_reg_defs.h. - Rename file name to intel_vrr_regs.h instead of reg.h. - Revert removed line. - Since vrr.enable and cmrr.enable are not mutually exclusive, handle accordingly. - is_edp is not required inside is_cmrr_frac_required function. - Add video_mode_required flag for future enhancement. - Correct cmrr_m/cmrr_n calculation. - target_rr_divider is bools so handle accordingly. -v11: - Move VRR related register and bits to separate file intel_vrr_regs.h. - Correct file header macro to intel_vrr_regs.h. - Remove adding CMRR flag to vrr_ctl register during set_transcoder_timing. - Replace vrr.enable flag to cmrr.enable where added mistakenly. - Move cmrr computation patch to last and set other other required params before computing cmrr.enable. -v12: - Add patch to fix check patch issues for VRR related registers in i915_reg.h then move them to intel_vrr_regs.h with separate patch. -v13: - Reverted unrelated patches while rebase. Mitul Golani (9): gpu/drm/i915: Update indentation for VRR registers and bits drm/i915: Separate VRR related register definitions drm/i915: Define and compute Transcoder CMRR registers drm/i915: Update trans_vrr_ctl flag when cmrr is computed drm/dp: Add refresh rate divider to struct representing AS SDP drm/i915/display: Add support for pack and unpack drm/i915/display: Compute Adaptive sync SDP params drm/i915/display: Compute vrr vsync params drm/i915: Compute CMRR and calculate vtotal drivers/gpu/drm/i915/display/intel_display.c | 24 +++- .../drm/i915/display/intel_display_device.h | 1 + .../drm/i915/display/intel_display_types.h| 6 + drivers/gpu/drm/i915/display/intel_dp.c | 18 ++- drivers/gpu/drm/i915/display/intel_vrr.c | 128 -- drivers/gpu/drm/i915/display/intel_vrr_regs.h | 128 ++ drivers/gpu/drm/i915/i915_reg.h | 100 -- include/drm/display/drm_dp_helper.h | 1 + 8 files changed, 287 insertions(+), 119 deletions(-) create mode 100644 drivers/gpu/drm/i915/display/intel_vrr_regs.h -- 2.25.1
[PATCH v13 1/9] gpu/drm/i915: Update indentation for VRR registers and bits
Update the indentation for the VRR register definition and its bits, and fix checkpatch issues to ensure smooth movement of registers and bits. Signed-off-by: Mitul Golani --- drivers/gpu/drm/i915/i915_reg.h | 9 + 1 file changed, 5 insertions(+), 4 deletions(-) diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index 0569a23b83b2..6b39211b5469 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -1152,7 +1152,7 @@ #define _TRANS_VRR_CTL_B 0x61420 #define _TRANS_VRR_CTL_C 0x62420 #define _TRANS_VRR_CTL_D 0x63420 -#define TRANS_VRR_CTL(dev_priv, trans) _MMIO_TRANS2(dev_priv, trans, _TRANS_VRR_CTL_A) +#define TRANS_VRR_CTL(dev_priv, trans) _MMIO_TRANS2(dev_priv, trans, _TRANS_VRR_CTL_A) #define VRR_CTL_VRR_ENABLE REG_BIT(31) #define VRR_CTL_IGN_MAX_SHIFTREG_BIT(30) #define VRR_CTL_FLIP_LINE_EN REG_BIT(29) @@ -1160,7 +1160,8 @@ #define VRR_CTL_PIPELINE_FULL(x) REG_FIELD_PREP(VRR_CTL_PIPELINE_FULL_MASK, (x)) #define VRR_CTL_PIPELINE_FULL_OVERRIDE REG_BIT(0) #define XELPD_VRR_CTL_VRR_GUARDBAND_MASK REG_GENMASK(15, 0) -#define XELPD_VRR_CTL_VRR_GUARDBAND(x) REG_FIELD_PREP(XELPD_VRR_CTL_VRR_GUARDBAND_MASK, (x)) +#define XELPD_VRR_CTL_VRR_GUARDBAND(x) REG_FIELD_PREP(XELPD_VRR_CTL_VRR_GUARDBAND_MASK, \ + (x)) #define _TRANS_VRR_VMAX_A 0x60424 #define _TRANS_VRR_VMAX_B 0x61424 @@ -1190,7 +1191,7 @@ #define _TRANS_VRR_STATUS_B0x6142C #define _TRANS_VRR_STATUS_C0x6242C #define _TRANS_VRR_STATUS_D0x6342C -#define TRANS_VRR_STATUS(dev_priv, trans) _MMIO_TRANS2(dev_priv, trans, _TRANS_VRR_STATUS_A) +#define TRANS_VRR_STATUS(dev_priv, trans) _MMIO_TRANS2(dev_priv, trans, _TRANS_VRR_STATUS_A) #define VRR_STATUS_VMAX_REACHED REG_BIT(31) #define VRR_STATUS_NOFLIP_TILL_BNDR REG_BIT(30) #define VRR_STATUS_FLIP_BEF_BNDR REG_BIT(29) @@ -1241,7 +1242,7 @@ #define TRANS_PUSH_SEND REG_BIT(30) #define _TRANS_VRR_VSYNC_A 0x60078 -#define TRANS_VRR_VSYNC(dev_priv, trans) _MMIO_TRANS2(dev_priv, trans, _TRANS_VRR_VSYNC_A) +#define TRANS_VRR_VSYNC(dev_priv, trans) _MMIO_TRANS2(dev_priv, trans, _TRANS_VRR_VSYNC_A) #define VRR_VSYNC_END_MASK REG_GENMASK(28, 16) #define VRR_VSYNC_END(vsync_end) REG_FIELD_PREP(VRR_VSYNC_END_MASK, (vsync_end)) #define VRR_VSYNC_START_MASK REG_GENMASK(12, 0) -- 2.25.1
[PATCH v13 2/9] drm/i915: Separate VRR related register definitions
Move VRR related register definitions to a separate file called intel_vrr_regs.h. Signed-off-by: Mitul Golani --- drivers/gpu/drm/i915/display/intel_vrr.c | 1 + drivers/gpu/drm/i915/display/intel_vrr_regs.h | 112 ++ drivers/gpu/drm/i915/i915_reg.h | 101 3 files changed, 113 insertions(+), 101 deletions(-) create mode 100644 drivers/gpu/drm/i915/display/intel_vrr_regs.h diff --git a/drivers/gpu/drm/i915/display/intel_vrr.c b/drivers/gpu/drm/i915/display/intel_vrr.c index 5f3657aa8313..871e6e6a184a 100644 --- a/drivers/gpu/drm/i915/display/intel_vrr.c +++ b/drivers/gpu/drm/i915/display/intel_vrr.c @@ -9,6 +9,7 @@ #include "intel_de.h" #include "intel_display_types.h" #include "intel_vrr.h" +#include "intel_vrr_regs.h" #include "intel_dp.h" bool intel_vrr_is_capable(struct intel_connector *connector) diff --git a/drivers/gpu/drm/i915/display/intel_vrr_regs.h b/drivers/gpu/drm/i915/display/intel_vrr_regs.h new file mode 100644 index ..d4eb74ee72a7 --- /dev/null +++ b/drivers/gpu/drm/i915/display/intel_vrr_regs.h @@ -0,0 +1,112 @@ +/* SPDX-License-Identifier: MIT */ +/* + * Copyright © 2024 Intel Corporation + */ + +#ifndef __INTEL_VRR_REGS_H__ +#define __INTEL_VRR_REGS_H__ + +#include "intel_display_reg_defs.h" + +/* VRR registers */ +#define _TRANS_VRR_CTL_A0x60420 +#define _TRANS_VRR_CTL_B0x61420 +#define _TRANS_VRR_CTL_C0x62420 +#define _TRANS_VRR_CTL_D0x63420 +#define TRANS_VRR_CTL(dev_priv, trans) _MMIO_TRANS2(dev_priv, trans, _TRANS_VRR_CTL_A) +#define VRR_CTL_VRR_ENABLEREG_BIT(31) +#define VRR_CTL_IGN_MAX_SHIFT REG_BIT(30) +#define VRR_CTL_FLIP_LINE_EN REG_BIT(29) +#define VRR_CTL_PIPELINE_FULL_MASKREG_GENMASK(10, 3) +#define VRR_CTL_PIPELINE_FULL(x) REG_FIELD_PREP(VRR_CTL_PIPELINE_FULL_MASK, (x)) +#define VRR_CTL_PIPELINE_FULL_OVERRIDEREG_BIT(0) +#define XELPD_VRR_CTL_VRR_GUARDBAND_MASK REG_GENMASK(15, 0) +#define XELPD_VRR_CTL_VRR_GUARDBAND(x) REG_FIELD_PREP(XELPD_VRR_CTL_VRR_GUARDBAND_MASK, \ + (x)) + +#define _TRANS_VRR_VMAX_A 0x60424 +#define _TRANS_VRR_VMAX_B 0x61424 +#define _TRANS_VRR_VMAX_C 0x62424 +#define _TRANS_VRR_VMAX_D 0x63424 +#define TRANS_VRR_VMAX(dev_priv, trans) _MMIO_TRANS2(dev_priv, trans, _TRANS_VRR_VMAX_A) +#define VRR_VMAX_MASK REG_GENMASK(19, 0) + +#define _TRANS_VRR_VMIN_A 0x60434 +#define _TRANS_VRR_VMIN_B 0x61434 +#define _TRANS_VRR_VMIN_C 0x62434 +#define _TRANS_VRR_VMIN_D 0x63434 +#define TRANS_VRR_VMIN(dev_priv, trans) _MMIO_TRANS2(dev_priv, trans, _TRANS_VRR_VMIN_A) +#define VRR_VMIN_MASK REG_GENMASK(15, 0) + +#define _TRANS_VRR_VMAXSHIFT_A 0x60428 +#define _TRANS_VRR_VMAXSHIFT_B 0x61428 +#define _TRANS_VRR_VMAXSHIFT_C 0x62428 +#define _TRANS_VRR_VMAXSHIFT_D 0x63428 +#define TRANS_VRR_VMAXSHIFT(dev_priv, trans)_MMIO_TRANS2(dev_priv, trans, \ + _TRANS_VRR_VMAXSHIFT_A) +#define VRR_VMAXSHIFT_DEC_MASKREG_GENMASK(29, 16) +#define VRR_VMAXSHIFT_DEC REG_BIT(16) +#define VRR_VMAXSHIFT_INC_MASKREG_GENMASK(12, 0) + +#define _TRANS_VRR_STATUS_A 0x6042C +#define _TRANS_VRR_STATUS_B 0x6142C +#define _TRANS_VRR_STATUS_C 0x6242C +#define _TRANS_VRR_STATUS_D 0x6342C +#define TRANS_VRR_STATUS(dev_priv, trans) _MMIO_TRANS2(dev_priv, trans, _TRANS_VRR_STATUS_A) +#define VRR_STATUS_VMAX_REACHED REG_BIT(31) +#define VRR_STATUS_NOFLIP_TILL_BNDR REG_BIT(30) +#define VRR_STATUS_FLIP_BEF_BNDR REG_BIT(29) +#define VRR_STATUS_NO_FLIP_FRAME REG_BIT(28) +#define VRR_STATUS_VRR_EN_LIVEREG_BIT(27) +#define VRR_STATUS_FLIPS_SERVICED REG_BIT(26) +#define VRR_STATUS_VBLANK_MASKREG_GENMASK(22, 20) +#define STATUS_FSM_IDLE REG_FIELD_PREP(VRR_STATUS_VBLANK_MASK, 0) +#define STATUS_FSM_WAIT_TILL_FDB REG_FIELD_PREP(VRR_STATUS_VBLANK_MASK, 1) +#define STATUS_FSM_WAIT_TILL_FS REG_FIELD_PREP(VRR_STATUS_VBLANK_MASK, 2) +#define STATUS_FSM_WAIT_TILL_FLIP REG_FIELD_PREP(VRR_STATUS_VBLANK_MASK, 3) +#define STATUS_FSM_PIPELINE_FILL REG_FIELD_PREP(VRR_STATUS_VBLANK_MASK, 4) +#define STATUS_FSM_ACTIVE REG_FIELD_PREP(VRR_STATUS_VBLANK_MASK, 5) +#define STATUS_FSM_LEGACY_VBLANK REG_FIELD_PREP(VRR_STATUS_VBLANK_MASK, 6) + +#define _TRANS_VRR_VTOTAL_PREV_A0x60480 +#define _TRANS_VRR_VTOTAL_PREV_B0x61480 +#define _TRANS_VRR_VTOTAL_PREV_C0x62480 +#define _TRANS_VRR_VTOTAL_PREV_D0x63480 +#define TRANS_VRR_VTOTAL_PREV
[PATCH v13 3/9] drm/i915: Define and compute Transcoder CMRR registers
Add register definitions for Transcoder Fixed Average
Vtotal mode/CMRR function, with the necessary bitfields.
Compute these registers when CMRR is enabled, extending
Adaptive refresh rate capabilities.
--v2:
- Use intel_de_read64_2x32 in intel_vrr_get_config. [Jani]
- Fix indent and order based on register offset. [Jani]
--v3:
- Removing RFC tag.
--v4:
- Update place holder for CMRR register definition. (Jani)
--v5:
- Add CMRR register definitions to a separate file intel_vrr_reg.h.
--v6:
- Fixed indentation. (Jani)
- Add dependency header intel_display_reg_defs.h. (Jani)
- Rename file name to intel_vrr_regs.h instead of reg.h (Jani)
--v7:
- Remove adding CMRR flag to vrr_ctl register during set_transcoder_timing,
as it is already being done during intel_vrr_enable. (Ankit)
Signed-off-by: Mitul Golani
Reviewed-by: Ankit Nautiyal
---
drivers/gpu/drm/i915/display/intel_display.c | 23 ++-
.../drm/i915/display/intel_display_types.h| 6 +
drivers/gpu/drm/i915/display/intel_vrr.c | 20
drivers/gpu/drm/i915/display/intel_vrr_regs.h | 14 +++
4 files changed, 62 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display.c
b/drivers/gpu/drm/i915/display/intel_display.c
index 7370acdd6b8b..29d750d2e6f7 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -1005,6 +1005,13 @@ static bool vrr_params_changed(const struct
intel_crtc_state *old_crtc_state,
old_crtc_state->vrr.pipeline_full !=
new_crtc_state->vrr.pipeline_full;
}
+static bool cmrr_params_changed(const struct intel_crtc_state *old_crtc_state,
+ const struct intel_crtc_state *new_crtc_state)
+{
+ return old_crtc_state->cmrr.cmrr_m != new_crtc_state->cmrr.cmrr_m ||
+ old_crtc_state->cmrr.cmrr_n != new_crtc_state->cmrr.cmrr_n;
+}
+
static bool vrr_enabling(const struct intel_crtc_state *old_crtc_state,
const struct intel_crtc_state *new_crtc_state)
{
@@ -5054,6 +5061,16 @@ intel_pipe_config_compare(const struct intel_crtc_state
*current_config,
} \
} while (0)
+#define PIPE_CONF_CHECK_LLI(name) do { \
+ if (current_config->name != pipe_config->name) { \
+ pipe_config_mismatch(&p, fastset, crtc, __stringify(name), \
+"(expected %lli, found %lli)", \
+current_config->name, \
+pipe_config->name); \
+ ret = false; \
+ } \
+} while (0)
+
#define PIPE_CONF_CHECK_BOOL(name) do { \
if (current_config->name != pipe_config->name) { \
BUILD_BUG_ON_MSG(!__same_type(current_config->name, bool), \
@@ -5432,10 +5449,13 @@ intel_pipe_config_compare(const struct intel_crtc_state
*current_config,
PIPE_CONF_CHECK_I(vrr.guardband);
PIPE_CONF_CHECK_I(vrr.vsync_start);
PIPE_CONF_CHECK_I(vrr.vsync_end);
+ PIPE_CONF_CHECK_LLI(cmrr.cmrr_m);
+ PIPE_CONF_CHECK_LLI(cmrr.cmrr_n);
}
#undef PIPE_CONF_CHECK_X
#undef PIPE_CONF_CHECK_I
+#undef PIPE_CONF_CHECK_LLI
#undef PIPE_CONF_CHECK_BOOL
#undef PIPE_CONF_CHECK_P
#undef PIPE_CONF_CHECK_FLAGS
@@ -6824,7 +6844,8 @@ static void intel_pre_update_crtc(struct
intel_atomic_state *state,
intel_crtc_needs_fastset(new_crtc_state))
icl_set_pipe_chicken(new_crtc_state);
- if (vrr_params_changed(old_crtc_state, new_crtc_state))
+ if (vrr_params_changed(old_crtc_state, new_crtc_state) ||
+ cmrr_params_changed(old_crtc_state, new_crtc_state))
intel_vrr_set_transcoder_timings(new_crtc_state);
}
diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h
b/drivers/gpu/drm/i915/display/intel_display_types.h
index 77609656317b..62ed3c9db94a 100644
--- a/drivers/gpu/drm/i915/display/intel_display_types.h
+++ b/drivers/gpu/drm/i915/display/intel_display_types.h
@@ -1401,6 +1401,12 @@ struct intel_crtc_state {
u32 vsync_end, vsync_start;
} vrr;
+ /* Content Match Refresh Rate state */
+ struct {
+ bool enable;
+ u64 cmrr_n, cmrr_m;
+ } cmrr;
+
/* Stream Splitter for eDP MSO */
struct {
bool enable;
diff --git a/drivers/gpu/drm/i915/display/intel_vrr.c
b/drivers/gpu/drm/i915/display/intel_vrr.c
index 871e6e6a184a..d2f854d9d18b 100644
--- a/drivers/gpu/drm/i915/display/intel_vrr.c
+++ b/drivers/gpu/drm/i915/display/intel_vrr.c
@@ -219,6 +219,17 @@ void intel_vrr_set_transcoder_timings(const struct
intel_crtc_state *crtc_state)
return;
}
+ if (crtc_state->cmrr.enable) {
+ intel_de_write(dev_priv, TRANS_CMRR_M_HI(dev_priv,
cpu_transcoder),
+
[PATCH v13 6/9] drm/i915/display: Add support for pack and unpack
Add support of pack and unpack for target_rr_divider. --v2: - Set Target Refresh Rate Divider bit when related AS SDP bit is set (Ankit). --v3: - target_rr_divider is bools so set accordingly (Ankit). Signed-off-by: Mitul Golani Reviewed-by: Ankit Nautiyal --- drivers/gpu/drm/i915/display/intel_dp.c | 4 1 file changed, 4 insertions(+) diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c index fd054e16850d..ac81b172b1ec 100644 --- a/drivers/gpu/drm/i915/display/intel_dp.c +++ b/drivers/gpu/drm/i915/display/intel_dp.c @@ -4232,6 +4232,9 @@ static ssize_t intel_dp_as_sdp_pack(const struct drm_dp_as_sdp *as_sdp, sdp->db[3] = as_sdp->target_rr & 0xFF; sdp->db[4] = (as_sdp->target_rr >> 8) & 0x3; + if (as_sdp->target_rr_divider) + sdp->db[4] |= 0x20; + return length; } @@ -4413,6 +4416,7 @@ int intel_dp_as_sdp_unpack(struct drm_dp_as_sdp *as_sdp, as_sdp->mode = sdp->db[0] & DP_ADAPTIVE_SYNC_SDP_OPERATION_MODE; as_sdp->vtotal = (sdp->db[2] << 8) | sdp->db[1]; as_sdp->target_rr = (u64)sdp->db[3] | ((u64)sdp->db[4] & 0x3); + as_sdp->target_rr_divider = sdp->db[4] & 0x20 ? true : false; return 0; } -- 2.25.1
[PATCH v13 5/9] drm/dp: Add refresh rate divider to struct representing AS SDP
Add target_rr_divider to structure representing AS SDP.
It is valid only in FAVT mode, sink device ignores the bit in AVT
mode.
--v2:
- Update commit header and send patch to dri-devel.
Signed-off-by: Mitul Golani
Reviewed-by: Arun R Murthy
---
include/drm/display/drm_dp_helper.h | 1 +
1 file changed, 1 insertion(+)
diff --git a/include/drm/display/drm_dp_helper.h
b/include/drm/display/drm_dp_helper.h
index 8defcc399f42..ea03e1dd26ba 100644
--- a/include/drm/display/drm_dp_helper.h
+++ b/include/drm/display/drm_dp_helper.h
@@ -122,6 +122,7 @@ struct drm_dp_as_sdp {
int target_rr;
int duration_incr_ms;
int duration_decr_ms;
+ bool target_rr_divider;
enum operation_mode mode;
};
--
2.25.1
[PATCH v13 9/9] drm/i915: Compute CMRR and calculate vtotal
Compute Fixed Average Vtotal/CMRR with resepect to
userspace VRR enablement. Also calculate required
parameters in case of CMRR is enabled. During
intel_vrr_compute_config, CMRR is getting enabled
based on userspace has enabled Variable refresh mode
with VRR timing generator or not. Make CMRR as small subset of
FAVT mode, when Panel is running on Fixed refresh rate
and on VRR framework then only enable CMRR to match with
actual refresh rate.
--v2:
- Update is_cmrr_frac_required function return as bool, not int. [Jani]
- Use signed int math instead of unsigned in cmrr_get_vtotal2. [Jani]
- Fix typo and usage of camel case in cmrr_get_vtotal. [Jani]
- Use do_div in cmrr_get_vtotalwhile calculating cmrr_m. [ Jani]
- Simplify cmrr and vrr compute config in intel_vrr_compute_config. [Jani]
- Correct valiable name usage in is_cmrr_frac_required. [Ville]
--v3:
- Removing RFC tag.
--v4:
- Added edp check to address edp usecase for now. (ville)
- Updated is_cmrr_fraction_required to more simplified calculation.
- on longterm goal to be worked upon uapi as suggestion from ville.
--v5:
- Correct vtotal paramas accuracy and add 2 digit precision.
- Avoid using DIV_ROUND_UP and improve scanline precision.
--v6:
- Make CMRR a small subset of FAVT mode.
--v7:
- Update commit message to avoid confusion with Legacy VRR (Ankit).
- Add cmrr.enable in last, so remove from this patch.
--v8:
- Set cmrr.enable in current patch instead of separate patch (Ankit).
- Since vrr.enable and cmrr.enable are not mutually exclusive,
handle accordingly (Ankit).
- is_edp is not required inside is_cmrr_frac_required function (Ankit).
- Add video_mode_required flag for future enhancement.
- Correct cmrr_m/cmrr_n calculation.
--v9:
- Move patch to last and set other bits before computing
cmrr.enable.(Ankit)
- Add TODO: for to address target refresh rate precision as future
enhancement.
Signed-off-by: Mitul Golani
Reviewed-by: Ankit Nautiyal
---
drivers/gpu/drm/i915/display/intel_display.c | 1 +
.../drm/i915/display/intel_display_device.h | 1 +
drivers/gpu/drm/i915/display/intel_vrr.c | 92 ---
3 files changed, 83 insertions(+), 11 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display.c
b/drivers/gpu/drm/i915/display/intel_display.c
index 29d750d2e6f7..63464b1a 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -5451,6 +5451,7 @@ intel_pipe_config_compare(const struct intel_crtc_state
*current_config,
PIPE_CONF_CHECK_I(vrr.vsync_end);
PIPE_CONF_CHECK_LLI(cmrr.cmrr_m);
PIPE_CONF_CHECK_LLI(cmrr.cmrr_n);
+ PIPE_CONF_CHECK_BOOL(cmrr.enable);
}
#undef PIPE_CONF_CHECK_X
diff --git a/drivers/gpu/drm/i915/display/intel_display_device.h
b/drivers/gpu/drm/i915/display/intel_display_device.h
index e1d9947394dc..92a438ad45a8 100644
--- a/drivers/gpu/drm/i915/display/intel_display_device.h
+++ b/drivers/gpu/drm/i915/display/intel_display_device.h
@@ -152,6 +152,7 @@ enum intel_display_subplatform {
BIT(trans)) != 0)
#define HAS_VRR(i915) (DISPLAY_VER(i915) >= 11)
#define HAS_AS_SDP(i915) (DISPLAY_VER(i915) >= 13)
+#define HAS_CMRR(i915) (DISPLAY_VER(i915) >= 20)
#define INTEL_NUM_PIPES(i915)
(hweight8(DISPLAY_RUNTIME_INFO(i915)->pipe_mask))
#define I915_HAS_HOTPLUG(i915) (DISPLAY_INFO(i915)->has_hotplug)
#define OVERLAY_NEEDS_PHYSICAL(i915)
(DISPLAY_INFO(i915)->overlay_needs_physical)
diff --git a/drivers/gpu/drm/i915/display/intel_vrr.c
b/drivers/gpu/drm/i915/display/intel_vrr.c
index 4ad99a54aa83..05f67dc9d98d 100644
--- a/drivers/gpu/drm/i915/display/intel_vrr.c
+++ b/drivers/gpu/drm/i915/display/intel_vrr.c
@@ -12,6 +12,9 @@
#include "intel_vrr_regs.h"
#include "intel_dp.h"
+#define FIXED_POINT_PRECISION 100
+#define CMRR_PRECISION_TOLERANCE 10
+
bool intel_vrr_is_capable(struct intel_connector *connector)
{
const struct drm_display_info *info = &connector->base.display_info;
@@ -107,6 +110,52 @@ int intel_vrr_vmax_vblank_start(const struct
intel_crtc_state *crtc_state)
return crtc_state->vrr.vmax - intel_vrr_vblank_exit_length(crtc_state);
}
+static bool
+is_cmrr_frac_required(struct intel_crtc_state *crtc_state)
+{
+ int calculated_refresh_k, actual_refresh_k, pixel_clock_per_line;
+ struct drm_display_mode *adjusted_mode = &crtc_state->hw.adjusted_mode;
+ struct drm_i915_private *i915 = to_i915(crtc_state->uapi.crtc->dev);
+
+ if (!HAS_CMRR(i915))
+ return false;
+
+ actual_refresh_k =
+ drm_mode_vrefresh(adjusted_mode) * FIXED_POINT_PRECISION;
+ pixel_clock_per_line =
+ adjusted_mode->crtc_clock * 1000 / adjusted_mode->crtc_htotal;
+ calculated_refresh_k =
+ pixel_clock_per_line * FIXED_POINT_PRECISION /
[PATCH v13 4/9] drm/i915: Update trans_vrr_ctl flag when cmrr is computed
Add/update trans_vrr_ctl flag when crtc_state->cmrr.enable
is set, With this commit setting the stage for subsequent
CMRR enablement.
--v2:
- Check pipe active state in cmrr enabling. [Jani]
- Remove usage of bitwise OR on booleans. [Jani]
- Revert unrelated changes. [Jani]
- Update intel_vrr_enable, vrr and cmrr enable conditions. [Jani]
- Simplify whole if-ladder in intel_vrr_enable. [Jani]
- Revert patch restructuring mistakes in intel_vrr_get_config. [Jani]
--v3:
- Check pipe active state in cmrr disabling.[Jani]
- Correct messed up condition in intel_vrr_enable. [Jani]
--v4:
- Removing RFC tag.
--v5:
- CMRR handling in co-existatnce of LRR and DRRS.
--v7:
- Rebase on top of AS SDP merge.
--v8:
- Remove cmrr_enabling/disabling and update commit message. (Ankit)
--v9:
- Revert removed line(Ankit).
Signed-off-by: Mitul Golani
Reviewed-by: Ankit Nautiyal
---
drivers/gpu/drm/i915/display/intel_vrr.c | 10 --
drivers/gpu/drm/i915/display/intel_vrr_regs.h | 2 ++
2 files changed, 10 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_vrr.c
b/drivers/gpu/drm/i915/display/intel_vrr.c
index d2f854d9d18b..19b364074de0 100644
--- a/drivers/gpu/drm/i915/display/intel_vrr.c
+++ b/drivers/gpu/drm/i915/display/intel_vrr.c
@@ -282,8 +282,14 @@ void intel_vrr_enable(const struct intel_crtc_state
*crtc_state)
VRR_VSYNC_END(crtc_state->vrr.vsync_end) |
VRR_VSYNC_START(crtc_state->vrr.vsync_start));
- intel_de_write(dev_priv, TRANS_VRR_CTL(dev_priv, cpu_transcoder),
- VRR_CTL_VRR_ENABLE | trans_vrr_ctl(crtc_state));
+ if (crtc_state->cmrr.enable) {
+ intel_de_write(dev_priv, TRANS_VRR_CTL(dev_priv,
cpu_transcoder),
+ VRR_CTL_VRR_ENABLE | VRR_CTL_CMRR_ENABLE |
+ trans_vrr_ctl(crtc_state));
+ } else {
+ intel_de_write(dev_priv, TRANS_VRR_CTL(dev_priv,
cpu_transcoder),
+ VRR_CTL_VRR_ENABLE | trans_vrr_ctl(crtc_state));
+ }
}
void intel_vrr_disable(const struct intel_crtc_state *old_crtc_state)
diff --git a/drivers/gpu/drm/i915/display/intel_vrr_regs.h
b/drivers/gpu/drm/i915/display/intel_vrr_regs.h
index 1aeb0cd45068..577b0abb66db 100644
--- a/drivers/gpu/drm/i915/display/intel_vrr_regs.h
+++ b/drivers/gpu/drm/i915/display/intel_vrr_regs.h
@@ -123,4 +123,6 @@
#define _TRANS_CMRR_N_HI_A 0x604FC
#define TRANS_CMRR_N_HI(dev_priv, trans)_MMIO_TRANS2(dev_priv, trans,
_TRANS_CMRR_N_HI_A)
+#define VRR_CTL_CMRR_ENABLEREG_BIT(27)
+
#endif /* __INTEL_VRR_REGS__ */
--
2.25.1
[PATCH v13 7/9] drm/i915/display: Compute Adaptive sync SDP params
Compute params for Adaptive Sync SDP when Fixed Average Vtotal
mode is enabled.
--v2:
Since vrr.enable is set in case of cmrr also, handle accordingly(Ankit).
--v3:
- Since vrr.enable is set in case of cmrr also, handle
accordingly(Ankit).
- check cmrr.enable when CMRR flags are set during intel_dp_compute_as_sdp.
--v4:
- Use drm_mode_vrefresh instead of manual calculation (Ankit).
Signed-off-by: Mitul Golani
Reviewed-by: Ankit Nautiyal
---
drivers/gpu/drm/i915/display/intel_dp.c | 14 +++---
1 file changed, 11 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c
b/drivers/gpu/drm/i915/display/intel_dp.c
index ac81b172b1ec..b5915c23302f 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -2637,11 +2637,19 @@ static void intel_dp_compute_as_sdp(struct intel_dp
*intel_dp,
/* Currently only DP_AS_SDP_AVT_FIXED_VTOTAL mode supported */
as_sdp->sdp_type = DP_SDP_ADAPTIVE_SYNC;
as_sdp->length = 0x9;
- as_sdp->mode = DP_AS_SDP_AVT_FIXED_VTOTAL;
- as_sdp->vtotal = adjusted_mode->vtotal;
- as_sdp->target_rr = 0;
as_sdp->duration_incr_ms = 0;
as_sdp->duration_incr_ms = 0;
+
+ if (crtc_state->cmrr.enable) {
+ as_sdp->mode = DP_AS_SDP_FAVT_TRR_REACHED;
+ as_sdp->vtotal = adjusted_mode->vtotal;
+ as_sdp->target_rr = drm_mode_vrefresh(adjusted_mode);
+ as_sdp->target_rr_divider = true;
+ } else {
+ as_sdp->mode = DP_AS_SDP_AVT_FIXED_VTOTAL;
+ as_sdp->vtotal = adjusted_mode->vtotal;
+ as_sdp->target_rr = 0;
+ }
}
static void intel_dp_compute_vsc_sdp(struct intel_dp *intel_dp,
--
2.25.1
[PATCH v13 8/9] drm/i915/display: Compute vrr vsync params
Compute vrr vsync params in case of FAVT as well instead of
only to AVT mode of operation.
--v2:
- Remove redundant computation for vrr_vsync_start
and vrr_vsync_end(Ankit).
--v3:
- vrr.enable and cmrr.enable check together is not required as both
will be true at the same point in time. (Ankit)
- Replace vrr.enable flag to cmrr.enable, mistakenly added. (Ankit)
Signed-off-by: Mitul Golani
Reviewed-by: Ankit Nautiyal
---
drivers/gpu/drm/i915/display/intel_vrr.c | 17 +
1 file changed, 9 insertions(+), 8 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_vrr.c
b/drivers/gpu/drm/i915/display/intel_vrr.c
index 19b364074de0..4ad99a54aa83 100644
--- a/drivers/gpu/drm/i915/display/intel_vrr.c
+++ b/drivers/gpu/drm/i915/display/intel_vrr.c
@@ -175,14 +175,15 @@ intel_vrr_compute_config(struct intel_crtc_state
*crtc_state,
if (crtc_state->uapi.vrr_enabled) {
crtc_state->vrr.enable = true;
crtc_state->mode_flags |= I915_MODE_FLAG_VRR;
- if (intel_dp_as_sdp_supported(intel_dp)) {
- crtc_state->vrr.vsync_start =
- (crtc_state->hw.adjusted_mode.crtc_vtotal -
-
crtc_state->hw.adjusted_mode.vsync_start);
- crtc_state->vrr.vsync_end =
- (crtc_state->hw.adjusted_mode.crtc_vtotal -
- crtc_state->hw.adjusted_mode.vsync_end);
- }
+ }
+
+ if (intel_dp_as_sdp_supported(intel_dp)) {
+ crtc_state->vrr.vsync_start =
+ (crtc_state->hw.adjusted_mode.crtc_vtotal -
+crtc_state->hw.adjusted_mode.vsync_start);
+ crtc_state->vrr.vsync_end =
+ (crtc_state->hw.adjusted_mode.crtc_vtotal -
+crtc_state->hw.adjusted_mode.vsync_end);
}
}
--
2.25.1
✗ Fi.CI.IGT: failure for Panel Replay eDP support (rev7)
== Series Details == Series: Panel Replay eDP support (rev7) URL : https://patchwork.freedesktop.org/series/133684/ State : failure == Summary == CI Bug Log - changes from CI_DRM_14881_full -> Patchwork_133684v7_full Summary --- **FAILURE** Serious unknown changes coming with Patchwork_133684v7_full absolutely need to be verified manually. If you think the reported changes have nothing to do with the changes introduced in Patchwork_133684v7_full, please notify your bug team (i915-ci-in...@lists.freedesktop.org) to allow them to document this new failure mode, which will reduce false positives in CI. Participating hosts (9 -> 9) -- No changes in participating hosts Possible new issues --- Here are the unknown changes that may have been introduced in Patchwork_133684v7_full: ### IGT changes ### Possible regressions * igt@kms_flip@flip-vs-suspend-interruptible@b-hdmi-a3: - shard-dg1: NOTRUN -> [FAIL][1] +6 other tests fail [1]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133684v7/shard-dg1-13/igt@kms_flip@flip-vs-suspend-interrupti...@b-hdmi-a3.html * igt@kms_vblank@ts-continuation-dpms-suspend@pipe-d-hdmi-a-1: - shard-dg2: NOTRUN -> [FAIL][2] +10 other tests fail [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133684v7/shard-dg2-10/igt@kms_vblank@ts-continuation-dpms-susp...@pipe-d-hdmi-a-1.html Known issues Here are the changes found in Patchwork_133684v7_full that come from known issues: ### IGT changes ### Issues hit * igt@drm_fdinfo@all-busy-idle-check-all: - shard-mtlp: NOTRUN -> [SKIP][3] ([i915#8414]) [3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133684v7/shard-mtlp-7/igt@drm_fdi...@all-busy-idle-check-all.html * igt@drm_fdinfo@busy-idle@bcs0: - shard-dg2: NOTRUN -> [SKIP][4] ([i915#8414]) +6 other tests skip [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133684v7/shard-dg2-10/igt@drm_fdinfo@busy-i...@bcs0.html * igt@drm_fdinfo@isolation@vecs0: - shard-dg1: NOTRUN -> [SKIP][5] ([i915#8414]) +9 other tests skip [5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133684v7/shard-dg1-17/igt@drm_fdinfo@isolat...@vecs0.html * igt@gem_ccs@block-multicopy-compressed: - shard-dg1: NOTRUN -> [SKIP][6] ([i915#9323]) [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133684v7/shard-dg1-17/igt@gem_...@block-multicopy-compressed.html * igt@gem_ccs@block-multicopy-inplace: - shard-dg1: NOTRUN -> [SKIP][7] ([i915#3555] / [i915#9323]) +1 other test skip [7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133684v7/shard-dg1-18/igt@gem_...@block-multicopy-inplace.html * igt@gem_ctx_exec@basic-nohangcheck: - shard-rkl: [PASS][8] -> [FAIL][9] ([i915#6268]) [8]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14881/shard-rkl-5/igt@gem_ctx_e...@basic-nohangcheck.html [9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133684v7/shard-rkl-3/igt@gem_ctx_e...@basic-nohangcheck.html * igt@gem_ctx_isolation@preservation-s3@bcs0: - shard-dg1: NOTRUN -> [FAIL][10] ([i915#10086]) +4 other tests fail [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133684v7/shard-dg1-17/igt@gem_ctx_isolation@preservation...@bcs0.html * igt@gem_ctx_persistence@heartbeat-many: - shard-dg1: NOTRUN -> [SKIP][11] ([i915#8555]) [11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133684v7/shard-dg1-18/igt@gem_ctx_persiste...@heartbeat-many.html * igt@gem_ctx_persistence@heartbeat-stop: - shard-mtlp: NOTRUN -> [SKIP][12] ([i915#8555]) +1 other test skip [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133684v7/shard-mtlp-7/igt@gem_ctx_persiste...@heartbeat-stop.html * igt@gem_ctx_sseu@invalid-sseu: - shard-dg1: NOTRUN -> [SKIP][13] ([i915#280]) [13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133684v7/shard-dg1-13/igt@gem_ctx_s...@invalid-sseu.html * igt@gem_eio@hibernate: - shard-dg2: NOTRUN -> [ABORT][14] ([i915#10030] / [i915#7975] / [i915#8213]) [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133684v7/shard-dg2-7/igt@gem_...@hibernate.html * igt@gem_eio@kms: - shard-tglu: [PASS][15] -> [INCOMPLETE][16] ([i915#10513]) [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14881/shard-tglu-3/igt@gem_...@kms.html [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133684v7/shard-tglu-7/igt@gem_...@kms.html * igt@gem_exec_balancer@bonded-false-hang: - shard-dg1: NOTRUN -> [SKIP][17] ([i915#4812]) +2 other tests skip [17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133684v7/shard-dg1-17/igt@gem_exec_balan...@bonded-false-hang.html * igt@gem_exec_balancer@noheartbeat: - s
✗ Fi.CI.SPARSE: warning for Implement CMRR Support (rev13)
== Series Details == Series: Implement CMRR Support (rev13) URL : https://patchwork.freedesktop.org/series/126443/ State : warning == Summary == Error: dim sparse failed Sparse version: v0.6.2 Fast mode used, each commit won't be checked separately.
✗ Fi.CI.CHECKPATCH: warning for Implement CMRR Support (rev13)
== Series Details ==
Series: Implement CMRR Support (rev13)
URL : https://patchwork.freedesktop.org/series/126443/
State : warning
== Summary ==
Error: dim checkpatch failed
71b880e0125f gpu/drm/i915: Update indentation for VRR registers and bits
00df34d55970 drm/i915: Separate VRR related register definitions
-:24: WARNING:FILE_PATH_CHANGES: added, moved or deleted file(s), does
MAINTAINERS need updating?
#24:
new file mode 100644
total: 0 errors, 1 warnings, 0 checks, 226 lines checked
c378b46201ff drm/i915: Define and compute Transcoder CMRR registers
-:58: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'name' - possible
side-effects?
#58: FILE: drivers/gpu/drm/i915/display/intel_display.c:5064:
+#define PIPE_CONF_CHECK_LLI(name) do { \
+ if (current_config->name != pipe_config->name) { \
+ pipe_config_mismatch(&p, fastset, crtc, __stringify(name), \
+"(expected %lli, found %lli)", \
+current_config->name, \
+pipe_config->name); \
+ ret = false; \
+ } \
+} while (0)
-:58: CHECK:MACRO_ARG_PRECEDENCE: Macro argument 'name' may be better as
'(name)' to avoid precedence issues
#58: FILE: drivers/gpu/drm/i915/display/intel_display.c:5064:
+#define PIPE_CONF_CHECK_LLI(name) do { \
+ if (current_config->name != pipe_config->name) { \
+ pipe_config_mismatch(&p, fastset, crtc, __stringify(name), \
+"(expected %lli, found %lli)", \
+current_config->name, \
+pipe_config->name); \
+ ret = false; \
+ } \
+} while (0)
total: 0 errors, 0 warnings, 2 checks, 113 lines checked
f1b4f9a44c61 drm/i915: Update trans_vrr_ctl flag when cmrr is computed
4e00c44f77da drm/dp: Add refresh rate divider to struct representing AS SDP
3c724ca659bc drm/i915/display: Add support for pack and unpack
0420415fbabf drm/i915/display: Compute Adaptive sync SDP params
9aa2b2a078df drm/i915/display: Compute vrr vsync params
749400a8261e drm/i915: Compute CMRR and calculate vtotal
✓ Fi.CI.BAT: success for Implement CMRR Support (rev13)
== Series Details == Series: Implement CMRR Support (rev13) URL : https://patchwork.freedesktop.org/series/126443/ State : success == Summary == CI Bug Log - changes from CI_DRM_14881 -> Patchwork_126443v13 Summary --- **SUCCESS** No regressions found. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126443v13/index.html Participating hosts (38 -> 35) -- Additional (4): fi-kbl-8809g fi-elk-e7500 bat-adlp-9 fi-bsw-n3050 Missing(7): bat-mtlp-9 fi-snb-2520m fi-cfl-8109u bat-dg2-11 bat-arls-1 bat-jsl-1 bat-arls-3 Known issues Here are the changes found in Patchwork_126443v13 that come from known issues: ### IGT changes ### Issues hit * igt@debugfs_test@basic-hwmon: - bat-adlp-9: NOTRUN -> [SKIP][1] ([i915#9318]) [1]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126443v13/bat-adlp-9/igt@debugfs_t...@basic-hwmon.html * igt@gem_huc_copy@huc-copy: - fi-kbl-8809g: NOTRUN -> [SKIP][2] ([i915#2190]) [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126443v13/fi-kbl-8809g/igt@gem_huc_c...@huc-copy.html * igt@gem_lmem_swapping@basic: - bat-adlp-9: NOTRUN -> [SKIP][3] ([i915#4613]) +3 other tests skip [3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126443v13/bat-adlp-9/igt@gem_lmem_swapp...@basic.html - fi-kbl-8809g: NOTRUN -> [SKIP][4] ([i915#4613]) +3 other tests skip [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126443v13/fi-kbl-8809g/igt@gem_lmem_swapp...@basic.html * igt@gem_lmem_swapping@random-engines: - fi-bsw-n3050: NOTRUN -> [SKIP][5] +19 other tests skip [5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126443v13/fi-bsw-n3050/igt@gem_lmem_swapp...@random-engines.html * igt@gem_tiled_pread_basic: - bat-adlp-9: NOTRUN -> [SKIP][6] ([i915#3282]) [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126443v13/bat-adlp-9/igt@gem_tiled_pread_basic.html * igt@i915_pm_rps@basic-api: - bat-adlp-9: NOTRUN -> [SKIP][7] ([i915#6621]) [7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126443v13/bat-adlp-9/igt@i915_pm_...@basic-api.html * igt@kms_cursor_legacy@basic-busy-flip-before-cursor-atomic: - bat-adlp-9: NOTRUN -> [SKIP][8] ([i915#4103]) +1 other test skip [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126443v13/bat-adlp-9/igt@kms_cursor_leg...@basic-busy-flip-before-cursor-atomic.html * igt@kms_dsc@dsc-basic: - bat-adlp-9: NOTRUN -> [SKIP][9] ([i915#3555] / [i915#3840]) [9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126443v13/bat-adlp-9/igt@kms_...@dsc-basic.html * igt@kms_force_connector_basic@force-load-detect: - fi-kbl-8809g: NOTRUN -> [SKIP][10] +30 other tests skip [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126443v13/fi-kbl-8809g/igt@kms_force_connector_ba...@force-load-detect.html - bat-adlp-9: NOTRUN -> [SKIP][11] [11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126443v13/bat-adlp-9/igt@kms_force_connector_ba...@force-load-detect.html * igt@kms_pm_backlight@basic-brightness: - bat-adlp-9: NOTRUN -> [SKIP][12] ([i915#9812]) [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126443v13/bat-adlp-9/igt@kms_pm_backli...@basic-brightness.html * igt@kms_pm_rpm@basic-pci-d3-state: - fi-elk-e7500: NOTRUN -> [SKIP][13] +24 other tests skip [13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126443v13/fi-elk-e7500/igt@kms_pm_...@basic-pci-d3-state.html * igt@kms_psr@psr-sprite-plane-onoff: - bat-adlp-9: NOTRUN -> [SKIP][14] ([i915#1072] / [i915#9673] / [i915#9732]) +3 other tests skip [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126443v13/bat-adlp-9/igt@kms_...@psr-sprite-plane-onoff.html * igt@kms_setmode@basic-clone-single-crtc: - bat-adlp-9: NOTRUN -> [SKIP][15] ([i915#3555]) [15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126443v13/bat-adlp-9/igt@kms_setm...@basic-clone-single-crtc.html * igt@prime_vgem@basic-fence-read: - bat-adlp-9: NOTRUN -> [SKIP][16] ([i915#3291] / [i915#3708]) +2 other tests skip [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126443v13/bat-adlp-9/igt@prime_v...@basic-fence-read.html [i915#1072]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/1072 [i915#2190]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/2190 [i915#3282]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3282 [i915#3291]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3291 [i915#3555]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3555 [i915#3708]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3708 [i915#3840]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3840 [i915#4103]: https:/
✗ Fi.CI.IGT: failure for drm/i915: bdw+ pipe interrupt stuff
== Series Details == Series: drm/i915: bdw+ pipe interrupt stuff URL : https://patchwork.freedesktop.org/series/134497/ State : failure == Summary == CI Bug Log - changes from CI_DRM_14881_full -> Patchwork_134497v1_full Summary --- **FAILURE** Serious unknown changes coming with Patchwork_134497v1_full absolutely need to be verified manually. If you think the reported changes have nothing to do with the changes introduced in Patchwork_134497v1_full, please notify your bug team (i915-ci-in...@lists.freedesktop.org) to allow them to document this new failure mode, which will reduce false positives in CI. Participating hosts (9 -> 9) -- No changes in participating hosts Possible new issues --- Here are the unknown changes that may have been introduced in Patchwork_134497v1_full: ### IGT changes ### Possible regressions * igt@kms_color@ctm-0-25@pipe-a: - shard-tglu: [PASS][1] -> [INCOMPLETE][2] [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14881/shard-tglu-10/igt@kms_color@ctm-0...@pipe-a.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_134497v1/shard-tglu-9/igt@kms_color@ctm-0...@pipe-a.html * igt@kms_flip@blocking-wf_vblank@d-hdmi-a4: - shard-dg1: NOTRUN -> [INCOMPLETE][3] [3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_134497v1/shard-dg1-18/igt@kms_flip@blocking-wf_vbl...@d-hdmi-a4.html * igt@kms_vblank@ts-continuation-dpms-suspend@pipe-a-hdmi-a-4: - shard-dg1: NOTRUN -> [FAIL][4] +2 other tests fail [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_134497v1/shard-dg1-16/igt@kms_vblank@ts-continuation-dpms-susp...@pipe-a-hdmi-a-4.html * igt@kms_vblank@ts-continuation-dpms-suspend@pipe-d-hdmi-a-1: - shard-dg2: NOTRUN -> [FAIL][5] +16 other tests fail [5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_134497v1/shard-dg2-4/igt@kms_vblank@ts-continuation-dpms-susp...@pipe-d-hdmi-a-1.html Known issues Here are the changes found in Patchwork_134497v1_full that come from known issues: ### IGT changes ### Issues hit * igt@drm_fdinfo@all-busy-idle-check-all: - shard-mtlp: NOTRUN -> [SKIP][6] ([i915#8414]) [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_134497v1/shard-mtlp-3/igt@drm_fdi...@all-busy-idle-check-all.html * igt@drm_fdinfo@busy-idle@bcs0: - shard-dg2: NOTRUN -> [SKIP][7] ([i915#8414]) +6 other tests skip [7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_134497v1/shard-dg2-4/igt@drm_fdinfo@busy-i...@bcs0.html * igt@drm_fdinfo@isolation@vecs0: - shard-dg1: NOTRUN -> [SKIP][8] ([i915#8414]) +9 other tests skip [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_134497v1/shard-dg1-15/igt@drm_fdinfo@isolat...@vecs0.html * igt@gem_ccs@block-multicopy-compressed: - shard-dg1: NOTRUN -> [SKIP][9] ([i915#9323]) [9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_134497v1/shard-dg1-15/igt@gem_...@block-multicopy-compressed.html * igt@gem_ccs@block-multicopy-inplace: - shard-rkl: NOTRUN -> [SKIP][10] ([i915#3555] / [i915#9323]) [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_134497v1/shard-rkl-5/igt@gem_...@block-multicopy-inplace.html - shard-dg1: NOTRUN -> [SKIP][11] ([i915#3555] / [i915#9323]) +1 other test skip [11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_134497v1/shard-dg1-17/igt@gem_...@block-multicopy-inplace.html * igt@gem_ctx_isolation@preservation-s3@bcs0: - shard-dg1: NOTRUN -> [FAIL][12] ([i915#10086]) +4 other tests fail [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_134497v1/shard-dg1-15/igt@gem_ctx_isolation@preservation...@bcs0.html * igt@gem_ctx_persistence@heartbeat-stop: - shard-mtlp: NOTRUN -> [SKIP][13] ([i915#8555]) +1 other test skip [13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_134497v1/shard-mtlp-3/igt@gem_ctx_persiste...@heartbeat-stop.html * igt@gem_ctx_sseu@invalid-args: - shard-rkl: NOTRUN -> [SKIP][14] ([i915#280]) [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_134497v1/shard-rkl-3/igt@gem_ctx_s...@invalid-args.html * igt@gem_ctx_sseu@invalid-sseu: - shard-dg1: NOTRUN -> [SKIP][15] ([i915#280]) [15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_134497v1/shard-dg1-18/igt@gem_ctx_s...@invalid-sseu.html * igt@gem_exec_balancer@bonded-false-hang: - shard-dg1: NOTRUN -> [SKIP][16] ([i915#4812]) +2 other tests skip [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_134497v1/shard-dg1-15/igt@gem_exec_balan...@bonded-false-hang.html * igt@gem_exec_balancer@noheartbeat: - shard-dg2: NOTRUN -> [SKIP][17] ([i915#8555]) [17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13449
[PATCH] drm/i915/gt/uc: Evaluate GuC priority within locks
The ce->guc_state.lock was made to protect guc_prio, which
indicates the GuC priority level.
But at the begnning of the function we perform some sanity check
of guc_prio outside its protected section. Move them within the
locked region.
Use this occasion to expand the if statement to make it clearer.
Fixes: ee242ca704d3 ("drm/i915/guc: Implement GuC priority management")
Signed-off-by: Andi Shyti
Cc: Matthew Brost
Cc: # v5.15+
---
drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c | 15 +++
1 file changed, 11 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
index 0eaa1064242c..1181043bc5e9 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
@@ -4267,13 +4267,18 @@ static void guc_bump_inflight_request_prio(struct
i915_request *rq,
u8 new_guc_prio = map_i915_prio_to_guc_prio(prio);
/* Short circuit function */
- if (prio < I915_PRIORITY_NORMAL ||
- rq->guc_prio == GUC_PRIO_FINI ||
- (rq->guc_prio != GUC_PRIO_INIT &&
-!new_guc_prio_higher(rq->guc_prio, new_guc_prio)))
+ if (prio < I915_PRIORITY_NORMAL)
return;
spin_lock(&ce->guc_state.lock);
+
+ if (rq->guc_prio == GUC_PRIO_FINI)
+ goto exit;
+
+ if (rq->guc_prio != GUC_PRIO_INIT &&
+ !new_guc_prio_higher(rq->guc_prio, new_guc_prio))
+ goto exit;
+
if (rq->guc_prio != GUC_PRIO_FINI) {
if (rq->guc_prio != GUC_PRIO_INIT)
sub_context_inflight_prio(ce, rq->guc_prio);
@@ -4281,6 +4286,8 @@ static void guc_bump_inflight_request_prio(struct
i915_request *rq,
add_context_inflight_prio(ce, rq->guc_prio);
update_context_prio(ce);
}
+
+exit:
spin_unlock(&ce->guc_state.lock);
}
--
2.45.1
✓ Fi.CI.BAT: success for drm/i915/gt/uc: Evaluate GuC priority within locks
== Series Details == Series: drm/i915/gt/uc: Evaluate GuC priority within locks URL : https://patchwork.freedesktop.org/series/134525/ State : success == Summary == CI Bug Log - changes from CI_DRM_14881 -> Patchwork_134525v1 Summary --- **SUCCESS** No regressions found. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_134525v1/index.html Participating hosts (38 -> 32) -- Additional (1): fi-bsw-n3050 Missing(7): bat-dg1-7 bat-kbl-2 bat-mtlp-9 fi-snb-2520m fi-glk-j4005 fi-cfl-8109u bat-arls-3 Known issues Here are the changes found in Patchwork_134525v1 that come from known issues: ### IGT changes ### Issues hit * igt@gem_lmem_swapping@random-engines: - fi-bsw-n3050: NOTRUN -> [SKIP][1] +19 other tests skip [1]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_134525v1/fi-bsw-n3050/igt@gem_lmem_swapp...@random-engines.html Build changes - * Linux: CI_DRM_14881 -> Patchwork_134525v1 CI-20190529: 20190529 CI_DRM_14881: a494545483635d3d93d19e8f483f61e7d4198383 @ git://anongit.freedesktop.org/gfx-ci/linux IGT_7878: eecd5683bd98cee3fc6bd3f26a1f053c897f6bdf @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git Patchwork_134525v1: a494545483635d3d93d19e8f483f61e7d4198383 @ git://anongit.freedesktop.org/gfx-ci/linux == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_134525v1/index.html
Re: [PATCH] drm/i915/gt: Delete the live_hearbeat_fast selftest
Hi Krzysztof, On Mon, Jun 03, 2024 at 06:20:22PM +0200, Niemiec, Krzysztof wrote: > The test is trying to push the heartbeat frequency to the limit, which > might sometimes fail. Such a failure does not provide valuable > information, because it does not indicate that there is something > necessarily wrong with either the driver or the hardware. > > Remove the test to prevent random, unnecessary failures from appearing > in CI. > > Suggested-by: Chris Wilson > Signed-off-by: Niemiec, Krzysztof merged in drm-intel-gt-next. Thank you, Andi
Re: [PATCH] drm/i915/gt: Fix potential UAF by revoke of fence registers
Hi Janusz,
On Tue, Jun 04, 2024 at 05:27:24PM +0200, Janusz Krzysztofik wrote:
> On Tuesday, 4 June 2024 02:48:43 GMT+2 Andi Shyti wrote:
> > On Mon, Jun 03, 2024 at 09:54:45PM +0200, Janusz Krzysztofik wrote:
> > > CI has been sporadically reporting the following issue triggered by
> > > igt@i915_selftest@live@hangcheck on ADL-P and similar machines:
> > >
> > > <6> [414.049203] i915: Running
> > > intel_hangcheck_live_selftests/igt_reset_evict_fence
> > > ...
> > > <6> [414.068804] i915 :00:02.0: [drm] GT0: GUC: submission enabled
> > > <6> [414.068812] i915 :00:02.0: [drm] GT0: GUC: SLPC enabled
> > > <3> [414.070354] Unable to pin Y-tiled fence; err:-4
> > > <3> [414.071282] i915_vma_revoke_fence:301
> > > GEM_BUG_ON(!i915_active_is_idle(&fence->active))
> > > ...
> > > <4>[ 609.603992] [ cut here ]
> > > <2>[ 609.603995] kernel BUG at
> > > drivers/gpu/drm/i915/gt/intel_ggtt_fencing.c:301!
> > > <4>[ 609.604003] invalid opcode: [#1] PREEMPT SMP NOPTI
> > > <4>[ 609.604006] CPU: 0 PID: 268 Comm: kworker/u64:3 Tainted: G U W
> > > 6.9.0-CI_DRM_14785-g1ba62f8cea9c+ #1
> > > <4>[ 609.604008] Hardware name: Intel Corporation Alder Lake Client
> > > Platform/AlderLake-P DDR4 RVP, BIOS RPLPFWI1.R00.4035.A00.2301200723
> > > 01/20/2023
> > > <4>[ 609.604010] Workqueue: i915 __i915_gem_free_work [i915]
> > > <4>[ 609.604149] RIP: 0010:i915_vma_revoke_fence+0x187/0x1f0 [i915]
> > > ...
> > > <4>[ 609.604271] Call Trace:
> > > <4>[ 609.604273]
> > > ...
> > > <4>[ 609.604716] __i915_vma_evict+0x2e9/0x550 [i915]
> > > <4>[ 609.604852] __i915_vma_unbind+0x7c/0x160 [i915]
> > > <4>[ 609.604977] force_unbind+0x24/0xa0 [i915]
> > > <4>[ 609.605098] i915_vma_destroy+0x2f/0xa0 [i915]
> > > <4>[ 609.605210] __i915_gem_object_pages_fini+0x51/0x2f0 [i915]
> > > <4>[ 609.605330] __i915_gem_free_objects.isra.0+0x6a/0xc0 [i915]
> > > <4>[ 609.605440] process_scheduled_works+0x351/0x690
> > > ...
> > >
> > > In the past, there were similar failures reported by CI from other IGT
> > > tests, observed on other platforms.
> > >
> > > Before commit 63baf4f3d587 ("drm/i915/gt: Only wait for GPU activity
> > > before unbinding a GGTT fence"), i915_vma_revoke_fence() was waiting for
> > > idleness of vma->active via fence_update(). That commit introduced
> > > vma->fence->active in order for the fence_update() to be able to wait
> > > selectively on that one instead of vma->active since only idleness of
> > > fence registers was needed. But then, another commit 0d86ee35097a
> > > ("drm/i915/gt: Make fence revocation unequivocal") replaced the call to
> > > fence_update() in i915_vma_revoke_fence() with only fence_write(), and
> > > also added that GEM_BUG_ON(!i915_active_is_idle(&fence->active)) in front.
> > > No justification was provided on why we might then expect idleness of
> > > vma->fence->active without first waiting on it.
> > >
> > > The issue can be potentially caused by a race among revocation of fence
> > > registers on one side and sequential execution of signal callbacks invoked
> > > on completion of a request that was using them on the other, still
> > > processed in parallel to revocation of those fence registers. Fix it by
> > > waiting for idleness of vma->fence->active in i915_vma_revoke_fence().
> > >
> > > Fixes: 0d86ee35097a ("drm/i915/gt: Make fence revocation unequivocal")
> > > Closes: https://gitlab.freedesktop.org/drm/intel/issues/10021
> > > Signed-off-by: Janusz Krzysztofik
> > > Cc: sta...@vger.kernel.org # v5.8+
> >
> > Just wondering whether we really need the stable kernel here.
> >
> > We have just an alleged failure reported on a selftest. I think
> > we can drop the stable requirement.
>
> Please note there were similar failures from other tests reported by CI in
> the
> past, e.g., https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/8846,
> https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/10638. Would you
> like
> me to mention them in commit description.
I guess that's fine.
> OTOH, stable will probably pick this patch up themselves, based on the Fixes:
> commit ID, even if we drop the Cc: stable.
I was referring to the whole Fixes+stable... but you are right,
let's keep them... just an oversight from me.
I retriggered another test... but I'm pretty sure this is good to
go.
Thanks,
Andi
> Anyway, please feel free to drop Cc: stable, you or anyone who will be
> pushing.
Re: [PATCH] drm/i915/gt/uc: Evaluate GuC priority within locks
On Thu, Jun 06, 2024 at 02:17:02AM +0200, Andi Shyti wrote:
> The ce->guc_state.lock was made to protect guc_prio, which
> indicates the GuC priority level.
>
> But at the begnning of the function we perform some sanity check
> of guc_prio outside its protected section. Move them within the
> locked region.
>
> Use this occasion to expand the if statement to make it clearer.
>
> Fixes: ee242ca704d3 ("drm/i915/guc: Implement GuC priority management")
> Signed-off-by: Andi Shyti
> Cc: Matthew Brost
Reviewed-by: Matthew Brost
> Cc: # v5.15+
> ---
> drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c | 15 +++
> 1 file changed, 11 insertions(+), 4 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
> b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
> index 0eaa1064242c..1181043bc5e9 100644
> --- a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
> +++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
> @@ -4267,13 +4267,18 @@ static void guc_bump_inflight_request_prio(struct
> i915_request *rq,
> u8 new_guc_prio = map_i915_prio_to_guc_prio(prio);
>
> /* Short circuit function */
> - if (prio < I915_PRIORITY_NORMAL ||
> - rq->guc_prio == GUC_PRIO_FINI ||
> - (rq->guc_prio != GUC_PRIO_INIT &&
> - !new_guc_prio_higher(rq->guc_prio, new_guc_prio)))
> + if (prio < I915_PRIORITY_NORMAL)
> return;
>
> spin_lock(&ce->guc_state.lock);
> +
> + if (rq->guc_prio == GUC_PRIO_FINI)
> + goto exit;
> +
> + if (rq->guc_prio != GUC_PRIO_INIT &&
> + !new_guc_prio_higher(rq->guc_prio, new_guc_prio))
> + goto exit;
> +
> if (rq->guc_prio != GUC_PRIO_FINI) {
> if (rq->guc_prio != GUC_PRIO_INIT)
> sub_context_inflight_prio(ce, rq->guc_prio);
> @@ -4281,6 +4286,8 @@ static void guc_bump_inflight_request_prio(struct
> i915_request *rq,
> add_context_inflight_prio(ce, rq->guc_prio);
> update_context_prio(ce);
> }
> +
> +exit:
> spin_unlock(&ce->guc_state.lock);
> }
>
> --
> 2.45.1
>
✓ Fi.CI.BAT: success for drm/i915/gt/uc: Evaluate GuC priority within locks (rev2)
== Series Details == Series: drm/i915/gt/uc: Evaluate GuC priority within locks (rev2) URL : https://patchwork.freedesktop.org/series/134525/ State : success == Summary == CI Bug Log - changes from CI_DRM_14883 -> Patchwork_134525v2 Summary --- **SUCCESS** No regressions found. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_134525v2/index.html Participating hosts (35 -> 36) -- Additional (6): bat-arls-4 bat-mtlp-6 bat-jsl-3 bat-dg2-11 bat-jsl-1 bat-arls-3 Missing(5): bat-kbl-2 bat-adlp-9 bat-adlp-6 fi-snb-2520m bat-dg2-14 Known issues Here are the changes found in Patchwork_134525v2 that come from known issues: ### IGT changes ### Issues hit * igt@debugfs_test@basic-hwmon: - bat-jsl-3: NOTRUN -> [SKIP][1] ([i915#9318]) [1]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_134525v2/bat-jsl-3/igt@debugfs_t...@basic-hwmon.html - bat-jsl-1: NOTRUN -> [SKIP][2] ([i915#9318]) [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_134525v2/bat-jsl-1/igt@debugfs_t...@basic-hwmon.html - bat-arls-3: NOTRUN -> [SKIP][3] ([i915#9318]) [3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_134525v2/bat-arls-3/igt@debugfs_t...@basic-hwmon.html - bat-mtlp-6: NOTRUN -> [SKIP][4] ([i915#9318]) [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_134525v2/bat-mtlp-6/igt@debugfs_t...@basic-hwmon.html * igt@fbdev@info: - bat-arls-3: NOTRUN -> [SKIP][5] ([i915#1849]) [5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_134525v2/bat-arls-3/igt@fb...@info.html - bat-mtlp-6: NOTRUN -> [SKIP][6] ([i915#1849] / [i915#2582]) [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_134525v2/bat-mtlp-6/igt@fb...@info.html * igt@fbdev@write: - bat-arls-3: NOTRUN -> [SKIP][7] ([i915#11191]) +3 other tests skip [7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_134525v2/bat-arls-3/igt@fb...@write.html - bat-mtlp-6: NOTRUN -> [SKIP][8] ([i915#2582]) +3 other tests skip [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_134525v2/bat-mtlp-6/igt@fb...@write.html * igt@gem_huc_copy@huc-copy: - bat-jsl-1: NOTRUN -> [SKIP][9] ([i915#2190]) [9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_134525v2/bat-jsl-1/igt@gem_huc_c...@huc-copy.html - bat-jsl-3: NOTRUN -> [SKIP][10] ([i915#2190]) [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_134525v2/bat-jsl-3/igt@gem_huc_c...@huc-copy.html * igt@gem_lmem_swapping@basic: - bat-jsl-3: NOTRUN -> [SKIP][11] ([i915#4613]) +3 other tests skip [11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_134525v2/bat-jsl-3/igt@gem_lmem_swapp...@basic.html * igt@gem_lmem_swapping@parallel-random-engines: - bat-arls-3: NOTRUN -> [SKIP][12] ([i915#10213]) +3 other tests skip [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_134525v2/bat-arls-3/igt@gem_lmem_swapp...@parallel-random-engines.html * igt@gem_lmem_swapping@verify-random: - bat-mtlp-6: NOTRUN -> [SKIP][13] ([i915#4613]) +3 other tests skip [13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_134525v2/bat-mtlp-6/igt@gem_lmem_swapp...@verify-random.html - bat-jsl-1: NOTRUN -> [SKIP][14] ([i915#4613]) +3 other tests skip [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_134525v2/bat-jsl-1/igt@gem_lmem_swapp...@verify-random.html * igt@gem_mmap@basic: - bat-dg2-11: NOTRUN -> [SKIP][15] ([i915#4083]) [15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_134525v2/bat-dg2-11/igt@gem_m...@basic.html - bat-arls-3: NOTRUN -> [SKIP][16] ([i915#4083]) [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_134525v2/bat-arls-3/igt@gem_m...@basic.html - bat-mtlp-6: NOTRUN -> [SKIP][17] ([i915#4083]) [17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_134525v2/bat-mtlp-6/igt@gem_m...@basic.html * igt@gem_render_tiled_blits@basic: - bat-arls-3: NOTRUN -> [SKIP][18] ([i915#10197] / [i915#10211] / [i915#4079]) [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_134525v2/bat-arls-3/igt@gem_render_tiled_bl...@basic.html * igt@gem_tiled_blits@basic: - bat-arls-3: NOTRUN -> [SKIP][19] ([i915#10196] / [i915#4077]) +2 other tests skip [19]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_134525v2/bat-arls-3/igt@gem_tiled_bl...@basic.html - bat-mtlp-6: NOTRUN -> [SKIP][20] ([i915#4077]) +2 other tests skip [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_134525v2/bat-mtlp-6/igt@gem_tiled_bl...@basic.html * igt@gem_tiled_fence_blits@basic: - bat-dg2-11: NOTRUN -> [SKIP][21] ([i915#4077]) +2 other tests skip [21]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_134525v2/bat-dg2
✗ Fi.CI.CHECKPATCH: warning for drm/i915/gt: Fix potential UAF by revoke of fence registers (rev2)
== Series Details == Series: drm/i915/gt: Fix potential UAF by revoke of fence registers (rev2) URL : https://patchwork.freedesktop.org/series/134411/ State : warning == Summary == Error: dim checkpatch failed 68a3074a63dc drm/i915/gt: Fix potential UAF by revoke of fence registers -:9: WARNING:COMMIT_LOG_LONG_LINE: Prefer a maximum 75 chars per line (possible unwrapped commit description?) #9: <6> [414.049203] i915: Running intel_hangcheck_live_selftests/igt_reset_evict_fence total: 0 errors, 1 warnings, 0 checks, 7 lines checked
✓ Fi.CI.BAT: success for drm/i915/gt: Fix potential UAF by revoke of fence registers (rev2)
== Series Details == Series: drm/i915/gt: Fix potential UAF by revoke of fence registers (rev2) URL : https://patchwork.freedesktop.org/series/134411/ State : success == Summary == CI Bug Log - changes from CI_DRM_14883 -> Patchwork_134411v2 Summary --- **SUCCESS** No regressions found. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_134411v2/index.html Participating hosts (35 -> 38) -- Additional (4): bat-arls-4 bat-mtlp-6 bat-jsl-1 bat-jsl-3 Missing(1): fi-snb-2520m Known issues Here are the changes found in Patchwork_134411v2 that come from known issues: ### IGT changes ### Issues hit * igt@debugfs_test@basic-hwmon: - bat-jsl-3: NOTRUN -> [SKIP][1] ([i915#9318]) [1]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_134411v2/bat-jsl-3/igt@debugfs_t...@basic-hwmon.html - bat-jsl-1: NOTRUN -> [SKIP][2] ([i915#9318]) [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_134411v2/bat-jsl-1/igt@debugfs_t...@basic-hwmon.html - bat-mtlp-6: NOTRUN -> [SKIP][3] ([i915#9318]) [3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_134411v2/bat-mtlp-6/igt@debugfs_t...@basic-hwmon.html * igt@fbdev@info: - bat-mtlp-6: NOTRUN -> [SKIP][4] ([i915#1849] / [i915#2582]) [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_134411v2/bat-mtlp-6/igt@fb...@info.html * igt@fbdev@write: - bat-mtlp-6: NOTRUN -> [SKIP][5] ([i915#2582]) +3 other tests skip [5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_134411v2/bat-mtlp-6/igt@fb...@write.html * igt@gem_huc_copy@huc-copy: - bat-jsl-1: NOTRUN -> [SKIP][6] ([i915#2190]) [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_134411v2/bat-jsl-1/igt@gem_huc_c...@huc-copy.html - bat-jsl-3: NOTRUN -> [SKIP][7] ([i915#2190]) [7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_134411v2/bat-jsl-3/igt@gem_huc_c...@huc-copy.html * igt@gem_lmem_swapping@basic: - bat-jsl-3: NOTRUN -> [SKIP][8] ([i915#4613]) +3 other tests skip [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_134411v2/bat-jsl-3/igt@gem_lmem_swapp...@basic.html * igt@gem_lmem_swapping@verify-random: - bat-mtlp-6: NOTRUN -> [SKIP][9] ([i915#4613]) +3 other tests skip [9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_134411v2/bat-mtlp-6/igt@gem_lmem_swapp...@verify-random.html - bat-jsl-1: NOTRUN -> [SKIP][10] ([i915#4613]) +3 other tests skip [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_134411v2/bat-jsl-1/igt@gem_lmem_swapp...@verify-random.html * igt@gem_mmap@basic: - bat-mtlp-6: NOTRUN -> [SKIP][11] ([i915#4083]) [11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_134411v2/bat-mtlp-6/igt@gem_m...@basic.html * igt@gem_tiled_blits@basic: - bat-mtlp-6: NOTRUN -> [SKIP][12] ([i915#4077]) +2 other tests skip [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_134411v2/bat-mtlp-6/igt@gem_tiled_bl...@basic.html * igt@gem_tiled_pread_basic: - bat-mtlp-6: NOTRUN -> [SKIP][13] ([i915#4079]) +1 other test skip [13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_134411v2/bat-mtlp-6/igt@gem_tiled_pread_basic.html * igt@i915_pm_rps@basic-api: - bat-mtlp-6: NOTRUN -> [SKIP][14] ([i915#6621]) [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_134411v2/bat-mtlp-6/igt@i915_pm_...@basic-api.html * igt@kms_addfb_basic@addfb25-x-tiled-legacy: - bat-mtlp-6: NOTRUN -> [SKIP][15] ([i915#4212] / [i915#9792]) +8 other tests skip [15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_134411v2/bat-mtlp-6/igt@kms_addfb_ba...@addfb25-x-tiled-legacy.html * igt@kms_addfb_basic@addfb25-y-tiled-small-legacy: - bat-mtlp-6: NOTRUN -> [SKIP][16] ([i915#5190] / [i915#9792]) [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_134411v2/bat-mtlp-6/igt@kms_addfb_ba...@addfb25-y-tiled-small-legacy.html * igt@kms_cursor_legacy@basic-busy-flip-before-cursor-legacy: - bat-jsl-3: NOTRUN -> [SKIP][17] ([i915#4103]) +1 other test skip [17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_134411v2/bat-jsl-3/igt@kms_cursor_leg...@basic-busy-flip-before-cursor-legacy.html - bat-jsl-1: NOTRUN -> [SKIP][18] ([i915#4103]) +1 other test skip [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_134411v2/bat-jsl-1/igt@kms_cursor_leg...@basic-busy-flip-before-cursor-legacy.html * igt@kms_cursor_legacy@basic-flip-after-cursor-legacy: - bat-mtlp-6: NOTRUN -> [SKIP][19] ([i915#9792]) +17 other tests skip [19]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_134411v2/bat-mtlp-6/igt@kms_cursor_leg...@basic-flip-after-cursor-legacy.html * igt@kms_dsc@dsc-basic: - bat-jsl-1: NOTRUN -> [SKIP][
