Re: [Intel-gfx] [PATCH v2 1/2] drm/i915/hdcp: Add DP HDCP2.2 timeout to read entire msg
LGTM.
Reviewed-by: Ankit Nautiyal
On 3/24/2021 5:00 PM, Anshuman Gupta wrote:
As documented in HDCP 2.2 DP Errata spec transmitter should abort the
authentication protocol in case transmitter has not received the
entire {AKE_Send_Cert, AKE_Send_H_prime, AKE_Send_Paring_Info} msg
within {110,7,5} miliseconds.
Adding above msg timeout values and aborting the HDCP authentication
in case it timedout to read entire msg.
https://www.digital-cp.com/sites/default/files/HDCP%202_2_DisplayPort_Errata_v3_0.pdf
v2:
- Removed redundant variable msg_can_timedout. [Ankit]
Cc: Ramalingam C
Signed-off-by: Anshuman Gupta
---
drivers/gpu/drm/i915/display/intel_dp_hdcp.c | 45 ++--
include/drm/drm_hdcp.h | 3 ++
2 files changed, 35 insertions(+), 13 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_dp_hdcp.c
b/drivers/gpu/drm/i915/display/intel_dp_hdcp.c
index 40c516e90193..8bad4b3d34dd 100644
--- a/drivers/gpu/drm/i915/display/intel_dp_hdcp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp_hdcp.c
@@ -294,37 +294,39 @@ struct hdcp2_dp_msg_data {
bool msg_detectable;
u32 timeout;
u32 timeout2; /* Added for non_paired situation */
+ /* Timeout to read entire msg */
+ u32 msg_read_timeout;
};
static const struct hdcp2_dp_msg_data hdcp2_dp_msg_data[] = {
- { HDCP_2_2_AKE_INIT, DP_HDCP_2_2_AKE_INIT_OFFSET, false, 0, 0 },
+ { HDCP_2_2_AKE_INIT, DP_HDCP_2_2_AKE_INIT_OFFSET, false, 0, 0, 0},
{ HDCP_2_2_AKE_SEND_CERT, DP_HDCP_2_2_AKE_SEND_CERT_OFFSET,
- false, HDCP_2_2_CERT_TIMEOUT_MS, 0 },
+ false, HDCP_2_2_CERT_TIMEOUT_MS, 0, HDCP_2_2_DP_CERT_READ_TIMEOUT_MS},
{ HDCP_2_2_AKE_NO_STORED_KM, DP_HDCP_2_2_AKE_NO_STORED_KM_OFFSET,
- false, 0, 0 },
+ false, 0, 0, 0 },
{ HDCP_2_2_AKE_STORED_KM, DP_HDCP_2_2_AKE_STORED_KM_OFFSET,
- false, 0, 0 },
+ false, 0, 0, 0 },
{ HDCP_2_2_AKE_SEND_HPRIME, DP_HDCP_2_2_AKE_SEND_HPRIME_OFFSET,
true, HDCP_2_2_HPRIME_PAIRED_TIMEOUT_MS,
- HDCP_2_2_HPRIME_NO_PAIRED_TIMEOUT_MS },
+ HDCP_2_2_HPRIME_NO_PAIRED_TIMEOUT_MS,
HDCP_2_2_DP_HPRIME_READ_TIMEOUT_MS},
{ HDCP_2_2_AKE_SEND_PAIRING_INFO,
DP_HDCP_2_2_AKE_SEND_PAIRING_INFO_OFFSET, true,
- HDCP_2_2_PAIRING_TIMEOUT_MS, 0 },
- { HDCP_2_2_LC_INIT, DP_HDCP_2_2_LC_INIT_OFFSET, false, 0, 0 },
+ HDCP_2_2_PAIRING_TIMEOUT_MS, 0, HDCP_2_2_DP_PAIRING_READ_TIMEOUT_MS },
+ { HDCP_2_2_LC_INIT, DP_HDCP_2_2_LC_INIT_OFFSET, false, 0, 0, 0 },
{ HDCP_2_2_LC_SEND_LPRIME, DP_HDCP_2_2_LC_SEND_LPRIME_OFFSET,
- false, HDCP_2_2_DP_LPRIME_TIMEOUT_MS, 0 },
+ false, HDCP_2_2_DP_LPRIME_TIMEOUT_MS, 0, 0 },
{ HDCP_2_2_SKE_SEND_EKS, DP_HDCP_2_2_SKE_SEND_EKS_OFFSET, false,
- 0, 0 },
+ 0, 0, 0 },
{ HDCP_2_2_REP_SEND_RECVID_LIST,
DP_HDCP_2_2_REP_SEND_RECVID_LIST_OFFSET, true,
- HDCP_2_2_RECVID_LIST_TIMEOUT_MS, 0 },
+ HDCP_2_2_RECVID_LIST_TIMEOUT_MS, 0, 0 },
{ HDCP_2_2_REP_SEND_ACK, DP_HDCP_2_2_REP_SEND_ACK_OFFSET, false,
- 0, 0 },
+ 0, 0, 0 },
{ HDCP_2_2_REP_STREAM_MANAGE,
DP_HDCP_2_2_REP_STREAM_MANAGE_OFFSET, false,
- 0, 0 },
+ 0, 0, 0},
{ HDCP_2_2_REP_STREAM_READY, DP_HDCP_2_2_REP_STREAM_READY_OFFSET,
- false, HDCP_2_2_STREAM_READY_TIMEOUT_MS, 0 },
+ false, HDCP_2_2_STREAM_READY_TIMEOUT_MS, 0, 0 },
/* local define to shovel this through the write_2_2 interface */
#define HDCP_2_2_ERRATA_DP_STREAM_TYPE50
{ HDCP_2_2_ERRATA_DP_STREAM_TYPE,
@@ -513,6 +515,8 @@ int intel_dp_hdcp2_read_msg(struct intel_digital_port
*dig_port,
u8 *byte = buf;
ssize_t ret, bytes_to_recv, len;
const struct hdcp2_dp_msg_data *hdcp2_msg_data;
+ ktime_t msg_end;
+ bool msg_expired;
hdcp2_msg_data = get_hdcp2_dp_msg_data(msg_id);
if (!hdcp2_msg_data)
@@ -539,6 +543,11 @@ int intel_dp_hdcp2_read_msg(struct intel_digital_port
*dig_port,
len = bytes_to_recv > DP_AUX_MAX_PAYLOAD_BYTES ?
DP_AUX_MAX_PAYLOAD_BYTES : bytes_to_recv;
+ /* Entire msg read timeout since initiate of msg read */
+ if (bytes_to_recv == size - 1 && hdcp2_msg_data->msg_read_timeout
> 0)
+ msg_end = ktime_add_ms(ktime_get_raw(),
+
hdcp2_msg_data->msg_read_timeout);
+
ret = drm_dp_dpcd_read(&dig_port->dp.aux, offset,
(void *)byte, len);
if (ret < 0) {
@@ -551,6 +560,16 @@ int intel_dp_hdcp2_read_msg(struct intel_digital_port
*dig_port,
byte += ret;
offset += ret;
}
+
+ if (hdcp2_msg_data->msg_read_timeout > 0) {
+ msg_expired = ktime_after(ktime_get_raw(), msg_end);
+ if (msg_expired) {
+
[Intel-gfx] [PATCH] drivers: gpu: drm: Remove repeated declaration
struct drm_i915_private, struct intel_crtc_state and struct intel_crtc have been declared before. Remove the duplicate. Signed-off-by: Wan Jiabing --- drivers/gpu/drm/i915/display/intel_crt.h | 1 - drivers/gpu/drm/i915/display/intel_display.h | 1 - drivers/gpu/drm/i915/display/intel_vrr.h | 1 - 3 files changed, 3 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_crt.h b/drivers/gpu/drm/i915/display/intel_crt.h index 1b3fba359efc..6c5c44600cbd 100644 --- a/drivers/gpu/drm/i915/display/intel_crt.h +++ b/drivers/gpu/drm/i915/display/intel_crt.h @@ -11,7 +11,6 @@ enum pipe; struct drm_encoder; struct drm_i915_private; -struct drm_i915_private; bool intel_crt_port_enabled(struct drm_i915_private *dev_priv, i915_reg_t adpa_reg, enum pipe *pipe); diff --git a/drivers/gpu/drm/i915/display/intel_display.h b/drivers/gpu/drm/i915/display/intel_display.h index 76f8a805b0a3..29cb6d84ed70 100644 --- a/drivers/gpu/drm/i915/display/intel_display.h +++ b/drivers/gpu/drm/i915/display/intel_display.h @@ -48,7 +48,6 @@ struct i915_ggtt_view; struct intel_atomic_state; struct intel_crtc; struct intel_crtc_state; -struct intel_crtc_state; struct intel_digital_port; struct intel_dp; struct intel_encoder; diff --git a/drivers/gpu/drm/i915/display/intel_vrr.h b/drivers/gpu/drm/i915/display/intel_vrr.h index fac01bf4ab50..96f9c9c27ab9 100644 --- a/drivers/gpu/drm/i915/display/intel_vrr.h +++ b/drivers/gpu/drm/i915/display/intel_vrr.h @@ -15,7 +15,6 @@ struct intel_crtc; struct intel_crtc_state; struct intel_dp; struct intel_encoder; -struct intel_crtc; bool intel_vrr_is_capable(struct drm_connector *connector); void intel_vrr_check_modeset(struct intel_atomic_state *state); -- 2.25.1 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH 03/11] security: commoncap: fix -Wstringop-overread warning
On Mon, 22 Mar 2021, Arnd Bergmann wrote: > From: Arnd Bergmann > > gcc-11 introdces a harmless warning for cap_inode_getsecurity: > > security/commoncap.c: In function ‘cap_inode_getsecurity’: > security/commoncap.c:440:33: error: ‘memcpy’ reading 16 bytes from a region > of size 0 [-Werror=stringop-overread] > 440 | memcpy(&nscap->data, &cap->data, > sizeof(__le32) * 2 * VFS_CAP_U32); > | > ^~ > > The problem here is that tmpbuf is initialized to NULL, so gcc assumes > it is not accessible unless it gets set by vfs_getxattr_alloc(). This is > a legitimate warning as far as I can tell, but the code is correct since > it correctly handles the error when that function fails. > > Add a separate NULL check to tell gcc about it as well. > > Signed-off-by: Arnd Bergmann Applied to git://git.kernel.org/pub/scm/linux/kernel/git/jmorris/linux-security.git fixes-v5.12 -- James Morris ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH 11/11] [RFC] drm/i915/dp: fix array overflow warning
On Mon, 22 Mar 2021, Arnd Bergmann wrote:
> From: Arnd Bergmann
>
> gcc-11 warns that intel_dp_check_mst_status() has a local array of
> fourteen bytes and passes the last four bytes into a function that
> expects a six-byte array:
>
> drivers/gpu/drm/i915/display/intel_dp.c: In function
> ‘intel_dp_check_mst_status’:
> drivers/gpu/drm/i915/display/intel_dp.c:4556:22: error:
> ‘drm_dp_channel_eq_ok’ reading 6 bytes from a region of size 4
> [-Werror=stringop-overread]
> 4556 | !drm_dp_channel_eq_ok(&esi[10],
> intel_dp->lane_count)) {
> |
> ^~~~
> drivers/gpu/drm/i915/display/intel_dp.c:4556:22: note: referencing argument 1
> of type ‘const u8 *’ {aka ‘const unsigned char *’}
> In file included from drivers/gpu/drm/i915/display/intel_dp.c:38:
> include/drm/drm_dp_helper.h:1459:6: note: in a call to function
> ‘drm_dp_channel_eq_ok’
> 1459 | bool drm_dp_channel_eq_ok(const u8 link_status[DP_LINK_STATUS_SIZE],
> | ^~~~
>
> Clearly something is wrong here, but I can't quite figure out what.
> Changing the array size to 16 bytes avoids the warning, but is
> probably the wrong solution here.
Ugh. drm_dp_channel_eq_ok() does not actually require more than
DP_LINK_STATUS_SIZE - 2 elements in the link_status. It's some other
related functions that do, and in most cases it's convenient to read all
those DP_LINK_STATUS_SIZE bytes.
However, here the case is slightly different for DP MST, and the change
causes reserved DPCD addresses to be read. Not sure it matters, but
really I think the problem is what drm_dp_channel_eq_ok() advertizes.
I also don't like the array notation with sizes in function parameters
in general, because I think it's misleading. Would gcc-11 warn if a
function actually accesses the memory out of bounds of the size?
Anyway. I don't think we're going to get rid of the array notation
anytime soon, if ever, no matter how much I dislike it, so I think the
right fix would be to at least state the correct required size in
drm_dp_channel_eq_ok().
BR,
Jani.
>
> Signed-off-by: Arnd Bergmann
> ---
> drivers/gpu/drm/i915/display/intel_dp.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_dp.c
> b/drivers/gpu/drm/i915/display/intel_dp.c
> index 8c12d5375607..830e2515f119 100644
> --- a/drivers/gpu/drm/i915/display/intel_dp.c
> +++ b/drivers/gpu/drm/i915/display/intel_dp.c
> @@ -65,7 +65,7 @@
> #include "intel_vdsc.h"
> #include "intel_vrr.h"
>
> -#define DP_DPRX_ESI_LEN 14
> +#define DP_DPRX_ESI_LEN 16
>
> /* DP DSC throughput values used for slice count calculations KPixels/s */
> #define DP_DSC_PEAK_PIXEL_RATE 272
--
Jani Nikula, Intel Open Source Graphics Center
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Re: [Intel-gfx] [PATCH 1/2] drm/i915: Fix transposed arguments to skl_plane_wm_level()
On Thu, Mar 25, 2021 at 02:44:14AM +0200, Ville Syrjala wrote:
> From: Ville Syrjälä
>
> Accidentally transposed the arguments to skl_plane_wm_level()
> which is causing us to mistakenly think that the plane watermarks
> have/have not changed when the opposite may be true. Swap the
> arguments so this actually works.
>
> The other uses of this look OK.
Reviewed-by: Stanislav Lisovskiy
>
> Cc: Stanislav Lisovskiy
> Fixes: 2871b2fde449 ("drm/i915: Fix TGL+ plane SAGV watermark programming")
> Signed-off-by: Ville Syrjälä
> ---
> drivers/gpu/drm/i915/intel_pm.c | 4 ++--
> 1 file changed, 2 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> index 820f850d5cbb..b2aede2be89d 100644
> --- a/drivers/gpu/drm/i915/intel_pm.c
> +++ b/drivers/gpu/drm/i915/intel_pm.c
> @@ -6017,8 +6017,8 @@ static bool skl_plane_selected_wm_equals(struct
> intel_plane *plane,
>* use it. It only gets used for calculating the required
>* ddb allocation.
>*/
> - if (!skl_wm_level_equals(skl_plane_wm_level(old_pipe_wm, level,
> plane->id),
> - skl_plane_wm_level(new_pipe_wm, level,
> plane->id)))
> + if (!skl_wm_level_equals(skl_plane_wm_level(old_pipe_wm,
> plane->id, level),
> + skl_plane_wm_level(new_pipe_wm,
> plane->id, level)))
> return false;
> }
>
> --
> 2.26.2
>
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[Intel-gfx] linux-next: please do not base your tree on v5.12-rc1-dontuse
Hi all, The latest version of the drm-misc tree consists of just 2 commits on top of Linus' v5.12-rc1-dontuse tag. -- Cheers, Stephen Rothwell pgp3hJ0faDbsT.pgp Description: OpenPGP digital signature ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH v4] vfio/pci: Add support for opregion v2.1+
Thank you for offering your valuable advice.
Will send the updated version soon.
> -Original Message-
> From: Alex Williamson
> Sent: Saturday, March 20, 2021 3:27 AM
> To: Gao, Fred
> Cc: k...@vger.kernel.org; intel-gfx@lists.freedesktop.org; Zhenyu Wang
> ; Fonn, Swee Yee
> Subject: Re: [PATCH v4] vfio/pci: Add support for opregion v2.1+
>
> On Tue, 2 Mar 2021 21:02:20 +0800
> Fred Gao wrote:
>
> > Before opregion version 2.0 VBT data is stored in opregion mailbox #4,
> > However, When VBT data exceeds 6KB size and cannot be within mailbox
> > #4 starting from opregion v2.0+, Extended VBT region, next to
> > opregion, is used to hold the VBT data, so the total size will be
> > opregion size plus extended VBT region size.
> >
> > since opregion v2.0 with physical host VBT address should not be
> > practically available for end user, it is not supported.
> >
> > Cc: Zhenyu Wang
> > Signed-off-by: Swee Yee Fonn
> > Signed-off-by: Fred Gao
> > ---
> > drivers/vfio/pci/vfio_pci_igd.c | 49
> > +
> > 1 file changed, 49 insertions(+)
> >
> > diff --git a/drivers/vfio/pci/vfio_pci_igd.c
> > b/drivers/vfio/pci/vfio_pci_igd.c index 53d97f459252..4edb8afcdbfc
> > 100644
> > --- a/drivers/vfio/pci/vfio_pci_igd.c
> > +++ b/drivers/vfio/pci/vfio_pci_igd.c
> > @@ -21,6 +21,10 @@
> > #define OPREGION_SIZE (8 * 1024)
> > #define OPREGION_PCI_ADDR 0xfc
> >
> > +#define OPREGION_RVDA 0x3ba
> > +#define OPREGION_RVDS 0x3c2
> > +#define OPREGION_VERSION 0x16
> > +
> > static size_t vfio_pci_igd_rw(struct vfio_pci_device *vdev, char __user
> *buf,
> > size_t count, loff_t *ppos, bool iswrite) { @@ -
> 58,6 +62,7
> > @@ static int vfio_pci_igd_opregion_init(struct vfio_pci_device *vdev)
> > u32 addr, size;
> > void *base;
> > int ret;
> > + u16 version;
> >
> > ret = pci_read_config_dword(vdev->pdev, OPREGION_PCI_ADDR,
> &addr);
> > if (ret)
> > @@ -83,6 +88,50 @@ static int vfio_pci_igd_opregion_init(struct
> > vfio_pci_device *vdev)
> >
> > size *= 1024; /* In KB */
> >
> > + /*
> > +* Support opregion v2.1+
> > +* When VBT data exceeds 6KB size and cannot be within mailbox #4
>
> s/#4/#4, then the/
>
> > +* Extended VBT region, next to opregion, is used to hold the VBT
> data.
> > +* RVDA (Relative Address of VBT Data from Opregion Base) and
> RVDS
> > +* (VBT Data Size) from opregion structure member are used to hold
> the
> > +* address from region base and size of VBT data while RVDA/RVDS
> > +* are not defined before opregion 2.0.
> > +*
> > +* opregion 2.0: rvda is the physical VBT address.
>
> Let's expand the comment to include why this is a problem to support
> (virtualization of this register would be required in userspace) and why we're
> choosing not to manipulate this into a 2.1+ table, which I think is both the
> practical lack of v2.0 tables in use and any implicit dependencies software
> may have on the OpRegion version.
>
> > +*
> > +* opregion 2.1+: rvda is unsigned, relative offset from
> > +* opregion base, and should never point within opregion.
>
> And for our purposes must exactly follow the base opregion to avoid
> exposing unknown host memory to userspace, ie. provide a more descriptive
> justification for the 2nd error condition below.
>
> > +*/
> > + version = le16_to_cpu(*(__le16 *)(base + OPREGION_VERSION));
> > + if (version >= 0x0200) {
> > + u64 rvda;
> > + u32 rvds;
> > +
> > + rvda = le64_to_cpu(*(__le64 *)(base + OPREGION_RVDA));
> > + rvds = le32_to_cpu(*(__le32 *)(base + OPREGION_RVDS));
> > + if (rvda && rvds) {
> > + /* no support for opregion v2.0 with physical VBT
> address */
> > + if (version == 0x0200) {
> > + memunmap(base);
> > + pci_err(vdev->pdev,
> > + "IGD passthrough does not support
> opregion\n"
> > + "version 0x%x with physical rvda
> 0x%llx\n", version, rvda);
>
>
> Why do we need a new line midway through this log message?
>
> s/passthrough/assignment/
>
> In testing the version you include the leading zero, do you also want that
> leading zero in the printed version, ie. %04x?
>
> If we get to this code, we already know that both rvda and rvds are non-zero,
> why is it useful to print the rvda value in this error message? For example,
> we could print:
>
> "IGD assignment does not support opregion version 0x%04x with an
> extended VBT region"
>
> > + return -EINVAL;
> > + }
> > +
> > + if ((u32)rvda != size) {
>
> What allows us to assume rvda is a 32bit value given that it's a 64bit
> register?
> It seems safer not to include this cast.
>
> > + memunmap(base
[Intel-gfx] [PATCH v5] vfio/pci: Add support for opregion v2.1+
Before opregion version 2.0 VBT data is stored in opregion mailbox #4,
but when VBT data exceeds 6KB size and cannot be within mailbox #4
then from opregion v2.0+, Extended VBT region, next to opregion is
used to hold the VBT data, so the total size will be opregion size plus
extended VBT region size.
Since opregion v2.0 with physical host VBT address would not be
practically available for end user and guest can not directly access
host physical address, so it is not supported.
Cc: Zhenyu Wang
Signed-off-by: Swee Yee Fonn
Signed-off-by: Fred Gao
---
drivers/vfio/pci/vfio_pci_igd.c | 53 +
1 file changed, 53 insertions(+)
diff --git a/drivers/vfio/pci/vfio_pci_igd.c b/drivers/vfio/pci/vfio_pci_igd.c
index e66dfb0178ed..228df565e9bc 100644
--- a/drivers/vfio/pci/vfio_pci_igd.c
+++ b/drivers/vfio/pci/vfio_pci_igd.c
@@ -21,6 +21,10 @@
#define OPREGION_SIZE (8 * 1024)
#define OPREGION_PCI_ADDR 0xfc
+#define OPREGION_RVDA 0x3ba
+#define OPREGION_RVDS 0x3c2
+#define OPREGION_VERSION 0x16
+
static size_t vfio_pci_igd_rw(struct vfio_pci_device *vdev, char __user *buf,
size_t count, loff_t *ppos, bool iswrite)
{
@@ -58,6 +62,7 @@ static int vfio_pci_igd_opregion_init(struct vfio_pci_device
*vdev)
u32 addr, size;
void *base;
int ret;
+ u16 version;
ret = pci_read_config_dword(vdev->pdev, OPREGION_PCI_ADDR, &addr);
if (ret)
@@ -83,6 +88,54 @@ static int vfio_pci_igd_opregion_init(struct vfio_pci_device
*vdev)
size *= 1024; /* In KB */
+ /*
+* Support opregion v2.1+
+* When VBT data exceeds 6KB size and cannot be within mailbox #4, then
+* the Extended VBT region next to opregion is used to hold the VBT
data.
+* RVDA (Relative Address of VBT Data from Opregion Base) and RVDS
+* (Raw VBT Data Size) from opregion structure member are used to hold
the
+* address from region base and size of VBT data. RVDA/RVDS are not
+* defined before opregion 2.0.
+*
+* opregion 2.1+: RVDA is unsigned, relative offset from
+* opregion base, and should point to the end of opregion.
+* otherwise, exposing to userspace to allow read access to everything
between
+* the OpRegion and VBT is not safe.
+* RVDS is defined as size in bytes.
+*
+* opregion 2.0: rvda is the physical VBT address.
+* Since rvda is HPA it cannot be directly used in guest.
+* And it should not be practically available for end user,so it is not
supported.
+*/
+ version = le16_to_cpu(*(__le16 *)(base + OPREGION_VERSION));
+ if (version >= 0x0200) {
+ u64 rvda;
+ u32 rvds;
+
+ rvda = le64_to_cpu(*(__le64 *)(base + OPREGION_RVDA));
+ rvds = le32_to_cpu(*(__le32 *)(base + OPREGION_RVDS));
+ if (rvda && rvds) {
+ /* no support for opregion v2.0 with physical VBT
address */
+ if (version == 0x0200) {
+ memunmap(base);
+ pci_err(vdev->pdev,
+ "IGD assignment does not support
opregion v2.0 with an extended VBT region\n");
+ return -EINVAL;
+ }
+
+ if (rvda != size) {
+ memunmap(base);
+ pci_err(vdev->pdev,
+ "Extended VBT does not follow opregion
on version 0x%04x\n",
+ version);
+ return -EINVAL;
+ }
+
+ /* region size for opregion v2.0+: opregion and VBT
size. */
+ size += rvds;
+ }
+ }
+
if (size != OPREGION_SIZE) {
memunmap(base);
base = memremap(addr, size, MEMREMAP_WB);
--
2.24.1.1.gb6d4d82bd5
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Re: [Intel-gfx] linux-next: please do not base your tree on v5.12-rc1-dontuse
On Thu, Mar 25, 2021 at 9:48 AM Stephen Rothwell wrote: > > Hi all, > > The latest version of the drm-misc tree consists of just 2 commits on > top of Linus' v5.12-rc1-dontuse tag. Yeah committer pushed patches to the wrong tree, which meant you get the wrong tree. We'll fix for tomorrow. -Daniel -- Daniel Vetter Software Engineer, Intel Corporation http://blog.ffwll.ch ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH] drm/i915: Fix userptr so we do not have to worry about obj->mm.lock, v8.
Instead of doing what we do currently, which will never work with
PROVE_LOCKING, do the same as AMD does, and something similar to
relocation slowpath. When all locks are dropped, we acquire the
pages for pinning. When the locks are taken, we transfer those
pages in .get_pages() to the bo. As a final check before installing
the fences, we ensure that the mmu notifier was not called; if it is,
we return -EAGAIN to userspace to signal it has to start over.
Changes since v1:
- Unbinding is done in submit_init only. submit_begin() removed.
- MMU_NOTFIER -> MMU_NOTIFIER
Changes since v2:
- Make i915->mm.notifier a spinlock.
Changes since v3:
- Add WARN_ON if there are any page references left, should have been 0.
- Return 0 on success in submit_init(), bug from spinlock conversion.
- Release pvec outside of notifier_lock (Thomas).
Changes since v4:
- Mention why we're clearing eb->[i + 1].vma in the code. (Thomas)
- Actually check all invalidations in eb_move_to_gpu. (Thomas)
- Do not wait when process is exiting to fix gem_ctx_persistence.userptr.
Changes since v5:
- Clarify why check on PF_EXITING is (temporarily) required.
Changes since v6:
- Ensure userptr validity is checked in set_domain through a special path.
Changes since v7:
- Chane kvfree to kvfree().
Signed-off-by: Maarten Lankhorst
Acked-by: Dave Airlie
Reviewed-by: Thomas Hellström
---
drivers/gpu/drm/i915/gem/i915_gem_domain.c| 18 +-
.../gpu/drm/i915/gem/i915_gem_execbuffer.c| 101 ++-
drivers/gpu/drm/i915/gem/i915_gem_object.h| 38 +-
.../gpu/drm/i915/gem/i915_gem_object_types.h | 10 +-
drivers/gpu/drm/i915/gem/i915_gem_pages.c | 2 +-
drivers/gpu/drm/i915/gem/i915_gem_userptr.c | 796 ++
drivers/gpu/drm/i915/i915_drv.h | 9 +-
drivers/gpu/drm/i915/i915_gem.c | 5 +-
8 files changed, 395 insertions(+), 584 deletions(-)
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_domain.c
b/drivers/gpu/drm/i915/gem/i915_gem_domain.c
index 2f4980bf742e..76cb9f5c66aa 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_domain.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_domain.c
@@ -468,14 +468,28 @@ i915_gem_set_domain_ioctl(struct drm_device *dev, void
*data,
if (!obj)
return -ENOENT;
+ if (i915_gem_object_is_userptr(obj)) {
+ /*
+* Try to grab userptr pages, iris uses set_domain to check
+* userptr validity
+*/
+ err = i915_gem_object_userptr_validate(obj);
+ if (!err)
+ err = i915_gem_object_wait(obj,
+ I915_WAIT_INTERRUPTIBLE |
+ I915_WAIT_PRIORITY |
+ (write_domain ?
I915_WAIT_ALL : 0),
+ MAX_SCHEDULE_TIMEOUT);
+ goto out;
+ }
+
/*
* Proxy objects do not control access to the backing storage, ergo
* they cannot be used as a means to manipulate the cache domain
* tracking for that backing storage. The proxy object is always
* considered to be outside of any cache domain.
*/
- if (i915_gem_object_is_proxy(obj) &&
- !i915_gem_object_is_userptr(obj)) {
+ if (i915_gem_object_is_proxy(obj)) {
err = -ENXIO;
goto out;
}
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c
b/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c
index 795c68fcc6ed..b5ca9eb53565 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c
@@ -53,14 +53,16 @@ enum {
/* __EXEC_OBJECT_NO_RESERVE is BIT(31), defined in i915_vma.h */
#define __EXEC_OBJECT_HAS_PIN BIT(30)
#define __EXEC_OBJECT_HAS_FENCEBIT(29)
-#define __EXEC_OBJECT_NEEDS_MAPBIT(28)
-#define __EXEC_OBJECT_NEEDS_BIAS BIT(27)
-#define __EXEC_OBJECT_INTERNAL_FLAGS (~0u << 27) /* all of the above + */
+#define __EXEC_OBJECT_USERPTR_INIT BIT(28)
+#define __EXEC_OBJECT_NEEDS_MAPBIT(27)
+#define __EXEC_OBJECT_NEEDS_BIAS BIT(26)
+#define __EXEC_OBJECT_INTERNAL_FLAGS (~0u << 26) /* all of the above + */
#define __EXEC_OBJECT_RESERVED (__EXEC_OBJECT_HAS_PIN |
__EXEC_OBJECT_HAS_FENCE)
#define __EXEC_HAS_RELOC BIT(31)
#define __EXEC_ENGINE_PINNED BIT(30)
-#define __EXEC_INTERNAL_FLAGS (~0u << 30)
+#define __EXEC_USERPTR_USEDBIT(29)
+#define __EXEC_INTERNAL_FLAGS (~0u << 29)
#define UPDATE PIN_OFFSET_FIXED
#define BATCH_OFFSET_BIAS (256*1024)
@@ -871,6 +873,26 @@ static int eb_lookup_vmas(struct i915_execbuffer *eb)
}
eb_add_vma(eb, i, batch, vma);
+
+ if (i915_gem_object_is_userptr(vma->obj)) {
+ err = i915_gem_object_userptr_submit_init(vma->obj);
+
[Intel-gfx] [PULL] drm-intel-fixes
Hi Dave and Daniel, with GT fence revocation runtime PM logic targeting 4.12+ stable, here goes drm-intel-fixes-2021-03-25-1: - DisplayPort LTTPR fixes around link training and limiting it according to supported spec version. (Imre) - Fix enabled_planes bitmask to really represent only logically enabled planes (Ville). - Fix DSS CTL registers for ICL DSI transcoders (Jani) - Fix the GT fence revocation runtime PM logic. (Imre) Thanks, Rodrigo. The following changes since commit 0d02ec6b3136c73c09e7859f0d0e4e2c4c07b49b: Linux 5.12-rc4 (2021-03-21 14:56:43 -0700) are available in the Git repository at: git://anongit.freedesktop.org/drm/drm-intel tags/drm-intel-fixes-2021-03-25-1 for you to fetch changes up to 8840e3bd981f128846b01c12d3966d115e8617c9: drm/i915: Fix the GT fence revocation runtime PM logic (2021-03-24 09:12:07 -0400) - DisplayPort LTTPR fixes around link training and limiting it according to supported spec version. (Imre) - Fix enabled_planes bitmask to really represent only logically enabled planes (Ville). - Fix DSS CTL registers for ICL DSI transcoders (Jani) - Fix the GT fence revocation runtime PM logic. (Imre) Imre Deak (4): drm/i915/ilk-glk: Fix link training on links with LTTPRs drm/i915: Disable LTTPR support when the DPCD rev < 1.4 drm/i915: Disable LTTPR support when the LTTPR rev < 1.4 drm/i915: Fix the GT fence revocation runtime PM logic Jani Nikula (1): drm/i915/dsc: fix DSS CTL register usage for ICL DSI transcoders Ville Syrjälä (1): drm/i915: Fix enabled_planes bitmask drivers/gpu/drm/i915/display/intel_atomic_plane.c | 5 +- drivers/gpu/drm/i915/display/intel_dp.c| 4 +- drivers/gpu/drm/i915/display/intel_dp_aux.c| 7 ++ .../gpu/drm/i915/display/intel_dp_link_training.c | 75 +- .../gpu/drm/i915/display/intel_dp_link_training.h | 2 +- drivers/gpu/drm/i915/display/intel_vdsc.c | 10 +-- drivers/gpu/drm/i915/gt/intel_ggtt_fencing.c | 13 +++- drivers/gpu/drm/i915/intel_runtime_pm.c| 29 +++-- drivers/gpu/drm/i915/intel_runtime_pm.h| 5 ++ 9 files changed, 113 insertions(+), 37 deletions(-) ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH 2/2] drm/i915: Stop adding planes to the commit needlessly
On Thu, Mar 25, 2021 at 02:44:15AM +0200, Ville Syrjala wrote:
> From: Ville Syrjälä
>
> The dbuf bandwidth calculations don't need the planes to be
> added to the state. Each plane's data rate has already been
> precalculated and stored in the crtc state, and that with
> the dbuf slice usage for each plane is all the dbuf bandwidth
> code needs to figure out what the minimum cdclk is.
>
> What we're trying to do here is make sure each plane recalculates
> its minimum cdclk (ie. plane->min_cdclk()) on those platforms where
> the number of active planes affects the result of said calculation.
> Nothing to do with any dbuf cdclk requirements.
So does it mean that if we lets say had active plane mask as
011(planes 0, 1 were active) and new active planes are 101(planes 0, 2
are active) - we should not add plane 2 to the state?
Because hamming weight will be obviously same, however I think it would
be wrong not have plane 2 in the state at all then..
Or will it be added somewhere else?
Stan
>
> Not sure if we had stuff in slightly different order or what,
> but at least in the current scheme this is not necessary.
>
> Cc: Stanislav Lisovskiy
> Signed-off-by: Ville Syrjälä
> ---
> drivers/gpu/drm/i915/display/intel_display.c | 10 ++
> 1 file changed, 2 insertions(+), 8 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_display.c
> b/drivers/gpu/drm/i915/display/intel_display.c
> index 17490d29dc13..2300d58ba47f 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.c
> +++ b/drivers/gpu/drm/i915/display/intel_display.c
> @@ -9811,7 +9811,7 @@ static bool active_planes_affects_min_cdclk(struct
> drm_i915_private *dev_priv)
> /* See {hsw,vlv,ivb}_plane_ratio() */
> return IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv) ||
> IS_CHERRYVIEW(dev_priv) || IS_VALLEYVIEW(dev_priv) ||
> - IS_IVYBRIDGE(dev_priv) || (DISPLAY_VER(dev_priv) >= 11);
> + IS_IVYBRIDGE(dev_priv);
> }
>
> static int intel_crtc_add_bigjoiner_planes(struct intel_atomic_state *state,
> @@ -9898,13 +9898,7 @@ static int intel_atomic_check_planes(struct
> intel_atomic_state *state)
> old_active_planes = old_crtc_state->active_planes &
> ~BIT(PLANE_CURSOR);
> new_active_planes = new_crtc_state->active_planes &
> ~BIT(PLANE_CURSOR);
>
> - /*
> - * Not only the number of planes, but if the plane
> configuration had
> - * changed might already mean we need to recompute min CDCLK,
> - * because different planes might consume different amount of
> Dbuf bandwidth
> - * according to formula: Bw per plane = Pixel rate * bpp *
> pipe/plane scale factor
> - */
> - if (old_active_planes == new_active_planes)
> + if (hweight8(old_active_planes) == hweight8(new_active_planes))
> continue;
>
> ret = intel_crtc_add_planes_to_state(state, crtc,
> new_active_planes);
> --
> 2.26.2
>
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Re: [Intel-gfx] [PATCH 2/2] drm/doc: Add RFC section
Acked-by: Simon Ser ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PULL] drm-misc-next
Hi Dave, Daniel, It's still a fairly quiet week, but here's this week's drm-misc-next PR maxime drm-misc-next-2021-03-25: drm-misc-next for 5.13: UAPI Changes: - New USB connector type Cross-subsystem Changes: Core Changes: - ttm: Introduce a per-device LRU lock, remove swap LRU Driver Changes: - Introduction of USB Display driver - an78xx: DP-Aux fixes - an6345: DP-Aux fixes - tilcdc: Pixel clocks fixes The following changes since commit 51c3b916a4d7e24b4918925965867fdd9bd8dd59: Merge tag 'drm-misc-next-2021-03-03' of git://anongit.freedesktop.org/drm/drm-misc into drm-next (2021-03-16 17:08:46 +1000) are available in the Git repository at: git://anongit.freedesktop.org/drm/drm-misc tags/drm-misc-next-2021-03-25 for you to fetch changes up to a1f091f8ef2b680a5184db065527612247cb4cae: drm/ttm: switch to per device LRU lock (2021-03-24 17:05:25 +0100) drm-misc-next for 5.13: UAPI Changes: - New USB connector type Cross-subsystem Changes: Core Changes: - ttm: Introduce a per-device LRU lock, remove swap LRU Driver Changes: - Introduction of USB Display driver - an78xx: DP-Aux fixes - an6345: DP-Aux fixes - tilcdc: Pixel clocks fixes Arnd Bergmann (2): fbdev: omapfb: avoid -Wempty-body warning vgaarb: avoid -Wempty-body warnings Bhaskar Chowdhury (2): drm: Few typo fixes drm/meson: Fix few typo Christian König (7): drm/sched: select new rq even if there is only one v3 drm/qxl: clean up qxl_bo_move_notify drm/nouveau: clean up nouveau_bo_move_ntfy drm/vmwgfx: clean up vmw_move_notify v2 drm/ttm: move swapout logic around v3 drm/ttm: remove swap LRU v3 drm/ttm: switch to per device LRU lock Daniel Vetter (1): dma-fence: Document recoverable page fault implications Dario Binacchi (3): drm/tilcdc: rename req_rate to pclk_rate drm/tilcdc: fix LCD pixel clock setting drm/tilcdc: fix pixel clock setting warning message Douglas Anderson (6): drm/panel-simple: Undo enable if HPD never asserts drm/panel-simple: Don't wait longer for HPD than hpd_absent_delay drm/panel-simple: Retry if we timeout waiting for HPD dt-bindings: dt-bindings: display: simple: Add N116BCA-EA1 drm/panel-simple: Add N116BCA-EA1 drm: panel: simple: Set enable delay for BOE NV110WTM-N61 Jagan Teki (1): drm/stm: ltdc: Use simple encoder Jianhui Zhao (1): docs: gpu: fix typo Linus Walleij (1): drm/mcde/panel: Inverse misunderstood flag Lyude Paul (9): drm/bridge/tc358767: Don't register DP AUX channel until bridge is attached drm/bridge/ti-sn65dsi86: (Un)register aux device on bridge attach/detach drm/bridge/analogix/anx78xx: Add missing drm_dp_aux_unregister() call drm/bridge/analogix/anx78xx: Setup encoder before registering connector drm/bridge/analogix/anx78xx: Cleanup on error in anx78xx_bridge_attach() drm/bridge/analogix/anx6345: Add missing drm_dp_aux_unregister() call drm/bridge/analogix/anx6345: Don't link encoder until after connector registration drm/bridge/analogix/anx6345: Cleanup on errors in anx6345_bridge_attach() drm/bridge/analogix/dp_core: Unregister DP AUX channel on error in analogix_dp_probe() Matthew Wilcox (Oracle) (1): fb_defio: Remove custom address_space_operations Maxime Ripard (2): Merge drm/drm-next into drm-misc-next drm/rockchip: Remove unused variable Noralf Trønnes (3): drm/uapi: Add USB connector type drm/probe-helper: Check epoch counter in output_poll_execute() drm: Add GUD USB Display driver Paul Cercueil (1): drm/ingenic: Fix non-OSD mode Simon Ser (1): drm/uapi: document kernel capabilities Tian Tao (2): drm/vboxvideo: Use managed VRAM-helper initialization drm/sysfs: Convert sysfs sprintf/snprintf family to sysfs_emit Yang Li (2): drm/gma500: use NULL instead of using plain integer as pointer drm/tilcdc: panel: fix platform_no_drv_owner.cocci warnings Yannick Fertre (1): drm/stm: dsi: Avoid printing errors for -EPROBE_DEFER kernel test robot (2): drm/gud: fix sizeof use drm/gud: Remove unneeded semicolon xndcn (1): drm/virtio: fix possible leak/unlock virtio_gpu_object_array .../bindings/display/panel/panel-simple.yaml | 2 + Documentation/driver-api/dma-buf.rst | 76 +++ Documentation/gpu/todo.rst | 2 +- MAINTAINERS| 8 + drivers/gpu/drm/Kconfig| 2 + drivers/gpu/drm/Makefile | 1 + drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c | 8 +- drivers/gpu/drm/bridge/analogix/analogix-anx6345.c | 27 +- drivers/gpu/drm/bridge/analogix/analogix-anx78xx.c | 27 +- drivers/
[Intel-gfx] [PATCH] drm/i915: Tweaked Wa_14010685332 for all PCHs
dispcnlunit1_cp_xosc_clkreq clock observed to be active on TGL-H platform
despite Wa_14010685332 original sequence thus blocks entry to deeper s0ix state.
The Tweaked Wa_14010685332 sequence fixes this issue, therefore use tweaked
Wa_14010685332 sequence for every PCH since PCH_CNP.
Fixes: b896898c7369 ("drm/i915: Tweaked Wa_14010685332 for PCHs used on gen11
platforms")
Cc: Matt Roper
Cc: Rodrigo Vivi
Signed-off-by: Anshuman Gupta
---
.../drm/i915/display/intel_display_power.c| 18 +---
drivers/gpu/drm/i915/i915_irq.c | 21 ---
2 files changed, 10 insertions(+), 29 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c
b/drivers/gpu/drm/i915/display/intel_display_power.c
index 7e0eaa872350..4e970be36487 100644
--- a/drivers/gpu/drm/i915/display/intel_display_power.c
+++ b/drivers/gpu/drm/i915/display/intel_display_power.c
@@ -5910,13 +5910,14 @@ void intel_display_power_suspend_late(struct
drm_i915_private *i915)
{
if (INTEL_GEN(i915) >= 11 || IS_GEN9_LP(i915)) {
bxt_enable_dc9(i915);
- /* Tweaked Wa_14010685332:icp,jsp,mcc */
- if (INTEL_PCH_TYPE(i915) >= PCH_ICP && INTEL_PCH_TYPE(i915) <=
PCH_MCC)
- intel_de_rmw(i915, SOUTH_CHICKEN1,
-SBCLK_RUN_REFCLK_DIS,
SBCLK_RUN_REFCLK_DIS);
} else if (IS_HASWELL(i915) || IS_BROADWELL(i915)) {
hsw_enable_pc8(i915);
}
+
+ /* Tweaked Wa_14010685332:cnp,icp,jsp,mcc,tgp,rkl,adp */
+ if (INTEL_PCH_TYPE(i915) == PCH_CNP ||
+ (INTEL_PCH_TYPE(i915) >= PCH_ICP && INTEL_PCH_TYPE(i915) < PCH_DG1))
+ intel_de_rmw(i915, SOUTH_CHICKEN1, SBCLK_RUN_REFCLK_DIS,
SBCLK_RUN_REFCLK_DIS);
}
void intel_display_power_resume_early(struct drm_i915_private *i915)
@@ -5924,13 +5925,14 @@ void intel_display_power_resume_early(struct
drm_i915_private *i915)
if (INTEL_GEN(i915) >= 11 || IS_GEN9_LP(i915)) {
gen9_sanitize_dc_state(i915);
bxt_disable_dc9(i915);
- /* Tweaked Wa_14010685332:icp,jsp,mcc */
- if (INTEL_PCH_TYPE(i915) >= PCH_ICP && INTEL_PCH_TYPE(i915) <=
PCH_MCC)
- intel_de_rmw(i915, SOUTH_CHICKEN1,
SBCLK_RUN_REFCLK_DIS, 0);
-
} else if (IS_HASWELL(i915) || IS_BROADWELL(i915)) {
hsw_disable_pc8(i915);
}
+
+ /* Tweaked Wa_14010685332:cnp,icp,jsp,mcc,tgp,rkl,adp */
+ if (INTEL_PCH_TYPE(i915) == PCH_CNP ||
+ (INTEL_PCH_TYPE(i915) >= PCH_ICP && INTEL_PCH_TYPE(i915) < PCH_DG1))
+ intel_de_rmw(i915, SOUTH_CHICKEN1, SBCLK_RUN_REFCLK_DIS, 0);
}
void intel_display_power_suspend(struct drm_i915_private *i915)
diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index 44aed4cbf894..8abcd35df926 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -3040,24 +3040,6 @@ static void valleyview_irq_reset(struct drm_i915_private
*dev_priv)
spin_unlock_irq(&dev_priv->irq_lock);
}
-static void cnp_display_clock_wa(struct drm_i915_private *dev_priv)
-{
- struct intel_uncore *uncore = &dev_priv->uncore;
-
- /*
-* Wa_14010685332:cnp/cmp,tgp,adp
-* TODO: Clarify which platforms this applies to
-* TODO: Figure out if this workaround can be applied in the s0ix
suspend/resume handlers as
-* on earlier platforms and whether the workaround is also needed for
runtime suspend/resume
-*/
- if (INTEL_PCH_TYPE(dev_priv) == PCH_CNP ||
- (INTEL_PCH_TYPE(dev_priv) >= PCH_TGP && INTEL_PCH_TYPE(dev_priv) <
PCH_DG1)) {
- intel_uncore_rmw(uncore, SOUTH_CHICKEN1, SBCLK_RUN_REFCLK_DIS,
-SBCLK_RUN_REFCLK_DIS);
- intel_uncore_rmw(uncore, SOUTH_CHICKEN1, SBCLK_RUN_REFCLK_DIS,
0);
- }
-}
-
static void gen8_irq_reset(struct drm_i915_private *dev_priv)
{
struct intel_uncore *uncore = &dev_priv->uncore;
@@ -3082,7 +3064,6 @@ static void gen8_irq_reset(struct drm_i915_private
*dev_priv)
if (HAS_PCH_SPLIT(dev_priv))
ibx_irq_reset(dev_priv);
- cnp_display_clock_wa(dev_priv);
}
static void gen11_display_irq_reset(struct drm_i915_private *dev_priv)
@@ -3123,8 +3104,6 @@ static void gen11_display_irq_reset(struct
drm_i915_private *dev_priv)
if (INTEL_PCH_TYPE(dev_priv) >= PCH_ICP)
GEN3_IRQ_RESET(uncore, SDE);
-
- cnp_display_clock_wa(dev_priv);
}
static void gen11_irq_reset(struct drm_i915_private *dev_priv)
--
2.26.2
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Re: [Intel-gfx] [PATCH] drm/i915: Implement SINGLE_TIMELINE with a syncobj (v2)
On 24/03/2021 17:18, Jason Ekstrand wrote: On Wed, Mar 24, 2021 at 6:36 AM Tvrtko Ursulin wrote: On 24/03/2021 09:52, Daniel Vetter wrote: On Wed, Mar 24, 2021 at 09:28:58AM +, Tvrtko Ursulin wrote: On 23/03/2021 17:51, Jason Ekstrand wrote: This API is entirely unnecessary and I'd love to get rid of it. If userspace wants a single timeline across multiple contexts, they can either use implicit synchronization or a syncobj, both of which existed at the time this feature landed. The justification given at the time was that it would help GL drivers which are inherently single-timeline. However, neither of our GL drivers actually wanted the feature. i965 was already in maintenance mode at the time and iris uses syncobj for everything. Unfortunately, as much as I'd love to get rid of it, it is used by the media driver so we can't do that. We can, however, do the next-best thing which is to embed a syncobj in the context and do exactly what we'd expect from userspace internally. This isn't an entirely identical implementation because it's no longer atomic if userspace races with itself by calling execbuffer2 twice simultaneously from different threads. It won't crash in that case; it just doesn't guarantee any ordering between those two submits. Moving SINGLE_TIMELINE to a syncobj emulation has a couple of technical advantages beyond mere annoyance. One is that intel_timeline is no longer an api-visible object and can remain entirely an implementation detail. This may be advantageous as we make scheduler changes going forward. Second is that, together with deleting the CLONE_CONTEXT API, we should now have a 1:1 mapping between intel_context and intel_timeline which may help us reduce locking. Much, much better commit message although I still fail to understand where do you see implementation details leaking out. So for me this is still something I'd like to get to the bottom of. I didn't say "leaking". I said it's no longer API-visible. That's just true. It used to be a kernel object that userspace was unaware of, then we added SINGLE_TIMELINE and userspace now has some influence over the object. With this patch, it's hidden again. I don't get why that's confusing. I am definitely glad we moved on from leaking to less dramatic wording, but it is still not API "visible" in so much struct file_operations * is not user visible in any negative way when you do open(2), being just implementation detail. But I give up. I would also mention the difference regarding fence context change. There are no fence context changes. The fence that we stuff in the syncobj is an i915 fence and the fence we pull back out is an i915 fence. A syncobj is just a fancy wrapper for a dma_buf pointer. Change is in the dma_fence->context. Current code single timeline is one fence context. With this patch that is no longer the case. Not sure that it has any practical implications for the internal dma_fence code like is_later checks , haven't analysed it. And sync fence info ioctl exposes this value to userspace which probably has no practical implications. Unless some indirect effect when merging fences. Main point is that I think these are the things which need to be discussed in the commit message. And in general I would maintain this patch as part of a series which ends up demonstrating the "mays" and "shoulds". I disagree. The past few years we've merged way too much patches and features without carefully answering the high level questions of - do we really need to solve this problem - and if so, are we really solving this problem in the right place Now we're quite in a hole, and we're not going to get out of this hole if we keep applying the same standards that got us here. Anything that does not clearly and without reservation the above two questions with "yes" needs to be removed or walled off, just so we can eventually see which complexity we really need, and what is actually superflous. I understand your general point but when I apply it to this specific patch, even if it is simple, it is neither removing the uapi or walling it off. So I see it as the usual review standard to ask to see what "mays" and "shoulds" actually get us in concrete terms. Instead of focusing on the term "leak", let's focus on this line of the commit message instead: Second is that, together with deleting the CLONE_CONTEXT API, we should now have a 1:1 mapping between intel_context and intel_timeline which may help us reduce locking. Now, I've not written any patches yet which actually reduce the locking. I can try to look into that today. I CC'd Maarten on the first send of this because I was hoping he would have good intuition about this. It may be that this object will always have to require some amount of locking if the scheduler has to touch them in parallel with other stuff. What I can say concretely, however, is that this does reduce the sharing of an internal object eve
Re: [Intel-gfx] [PATCH] drm/i915: Implement SINGLE_TIMELINE with a syncobj (v2)
On Thu, Mar 25, 2021 at 10:48 AM Tvrtko Ursulin wrote: > > > On 24/03/2021 17:18, Jason Ekstrand wrote: > > On Wed, Mar 24, 2021 at 6:36 AM Tvrtko Ursulin > > wrote: > >> > >> > >> On 24/03/2021 09:52, Daniel Vetter wrote: > >>> On Wed, Mar 24, 2021 at 09:28:58AM +, Tvrtko Ursulin wrote: > > On 23/03/2021 17:51, Jason Ekstrand wrote: > > This API is entirely unnecessary and I'd love to get rid of it. If > > userspace wants a single timeline across multiple contexts, they can > > either use implicit synchronization or a syncobj, both of which existed > > at the time this feature landed. The justification given at the time > > was that it would help GL drivers which are inherently single-timeline. > > However, neither of our GL drivers actually wanted the feature. i965 > > was already in maintenance mode at the time and iris uses syncobj for > > everything. > > > > Unfortunately, as much as I'd love to get rid of it, it is used by the > > media driver so we can't do that. We can, however, do the next-best > > thing which is to embed a syncobj in the context and do exactly what > > we'd expect from userspace internally. This isn't an entirely identical > > implementation because it's no longer atomic if userspace races with > > itself by calling execbuffer2 twice simultaneously from different > > threads. It won't crash in that case; it just doesn't guarantee any > > ordering between those two submits. > > > > Moving SINGLE_TIMELINE to a syncobj emulation has a couple of technical > > advantages beyond mere annoyance. One is that intel_timeline is no > > longer an api-visible object and can remain entirely an implementation > > detail. This may be advantageous as we make scheduler changes going > > forward. Second is that, together with deleting the CLONE_CONTEXT API, > > we should now have a 1:1 mapping between intel_context and > > intel_timeline which may help us reduce locking. > > Much, much better commit message although I still fail to understand > where > do you see implementation details leaking out. So for me this is still > something I'd like to get to the bottom of. > > > > I didn't say "leaking". I said it's no longer API-visible. That's > > just true. It used to be a kernel object that userspace was unaware > > of, then we added SINGLE_TIMELINE and userspace now has some influence > > over the object. With this patch, it's hidden again. I don't get why > > that's confusing. > > I am definitely glad we moved on from leaking to less dramatic wording, > but it is still not API "visible" in so much struct file_operations * is > not user visible in any negative way when you do open(2), being just > implementation detail. But I give up. > > I would also mention the difference regarding fence context change. > > > > There are no fence context changes. The fence that we stuff in the > > syncobj is an i915 fence and the fence we pull back out is an i915 > > fence. A syncobj is just a fancy wrapper for a dma_buf pointer. > > Change is in the dma_fence->context. > > Current code single timeline is one fence context. With this patch that > is no longer the case. > > Not sure that it has any practical implications for the internal > dma_fence code like is_later checks , haven't analysed it. We merge fewer fences at the higher levels and rely more on the fence dependency tracking of the scheduler frontend to sort stuff out. > And sync fence info ioctl exposes this value to userspace which probably > has no practical implications. Unless some indirect effect when merging > fences. Userspace can use that to do fence merging. Which is always only a strict optimization. I'm not even sure whether Android does that or not. > Main point is that I think these are the things which need to be > discussed in the commit message. Yeah makes sense to add these as impact, next to the "we don't deal with races anymore" part. -Daniel > > And in general I would maintain this patch as part of a series which > ends up > demonstrating the "mays" and "shoulds". > >>> > >>> I disagree. The past few years we've merged way too much patches and > >>> features without carefully answering the high level questions of > >>> - do we really need to solve this problem > >>> - and if so, are we really solving this problem in the right place > >>> > >>> Now we're quite in a hole, and we're not going to get out of this hole if > >>> we keep applying the same standards that got us here. Anything that does > >>> not clearly and without reservation the above two questions with "yes" > >>> needs to be removed or walled off, just so we can eventually see which > >>> complexity we really need, and what is actually superflous. > >> > >> I understand your general point but when I apply it to this specific > >> patch, even if it is simple, it is neither removing the uapi
Re: [Intel-gfx] [PATCH] drm/i915: Fix userptr so we do not have to worry about obj->mm.lock, v8.
On 3/25/21 10:23 AM, Maarten Lankhorst wrote: Instead of doing what we do currently, which will never work with PROVE_LOCKING, do the same as AMD does, and something similar to relocation slowpath. When all locks are dropped, we acquire the pages for pinning. When the locks are taken, we transfer those pages in .get_pages() to the bo. As a final check before installing the fences, we ensure that the mmu notifier was not called; if it is, we return -EAGAIN to userspace to signal it has to start over. Changes since v1: - Unbinding is done in submit_init only. submit_begin() removed. - MMU_NOTFIER -> MMU_NOTIFIER Changes since v2: - Make i915->mm.notifier a spinlock. Changes since v3: - Add WARN_ON if there are any page references left, should have been 0. - Return 0 on success in submit_init(), bug from spinlock conversion. - Release pvec outside of notifier_lock (Thomas). Changes since v4: - Mention why we're clearing eb->[i + 1].vma in the code. (Thomas) - Actually check all invalidations in eb_move_to_gpu. (Thomas) - Do not wait when process is exiting to fix gem_ctx_persistence.userptr. Changes since v5: - Clarify why check on PF_EXITING is (temporarily) required. Changes since v6: - Ensure userptr validity is checked in set_domain through a special path. Changes since v7: - Chane kvfree to kvfree(). v8: Change "Chane kvfree to kvfree()" to "Change kfree() to kvfree()" ? :) /Thomas ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH] drm/i915: Tweaked Wa_14010685332 for all PCHs
On Thu, Mar 25, 2021 at 03:02:13PM +0530, Anshuman Gupta wrote:
> dispcnlunit1_cp_xosc_clkreq clock observed to be active on TGL-H platform
> despite Wa_14010685332 original sequence thus blocks entry to deeper s0ix
> state.
>
> The Tweaked Wa_14010685332 sequence fixes this issue, therefore use tweaked
> Wa_14010685332 sequence for every PCH since PCH_CNP.
>
> Fixes: b896898c7369 ("drm/i915: Tweaked Wa_14010685332 for PCHs used on gen11
> platforms")
> Cc: Matt Roper
> Cc: Rodrigo Vivi
> Signed-off-by: Anshuman Gupta
> ---
> .../drm/i915/display/intel_display_power.c| 18 +---
> drivers/gpu/drm/i915/i915_irq.c | 21 ---
> 2 files changed, 10 insertions(+), 29 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c
> b/drivers/gpu/drm/i915/display/intel_display_power.c
> index 7e0eaa872350..4e970be36487 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_power.c
> +++ b/drivers/gpu/drm/i915/display/intel_display_power.c
> @@ -5910,13 +5910,14 @@ void intel_display_power_suspend_late(struct
> drm_i915_private *i915)
> {
> if (INTEL_GEN(i915) >= 11 || IS_GEN9_LP(i915)) {
> bxt_enable_dc9(i915);
> - /* Tweaked Wa_14010685332:icp,jsp,mcc */
> - if (INTEL_PCH_TYPE(i915) >= PCH_ICP && INTEL_PCH_TYPE(i915) <=
> PCH_MCC)
> - intel_de_rmw(i915, SOUTH_CHICKEN1,
> - SBCLK_RUN_REFCLK_DIS,
> SBCLK_RUN_REFCLK_DIS);
> } else if (IS_HASWELL(i915) || IS_BROADWELL(i915)) {
> hsw_enable_pc8(i915);
> }
> +
> + /* Tweaked Wa_14010685332:cnp,icp,jsp,mcc,tgp,rkl,adp */
why are you adding "rkl"?
I don't like mixing gpu with pch names...
> + if (INTEL_PCH_TYPE(i915) == PCH_CNP ||
> + (INTEL_PCH_TYPE(i915) >= PCH_ICP && INTEL_PCH_TYPE(i915) < PCH_DG1))
why can't we simply use
if (INTEL_PCH_TYPE(i915) >= PCH_CNP)
?
> + intel_de_rmw(i915, SOUTH_CHICKEN1, SBCLK_RUN_REFCLK_DIS,
> SBCLK_RUN_REFCLK_DIS);
> }
>
> void intel_display_power_resume_early(struct drm_i915_private *i915)
> @@ -5924,13 +5925,14 @@ void intel_display_power_resume_early(struct
> drm_i915_private *i915)
> if (INTEL_GEN(i915) >= 11 || IS_GEN9_LP(i915)) {
> gen9_sanitize_dc_state(i915);
> bxt_disable_dc9(i915);
> - /* Tweaked Wa_14010685332:icp,jsp,mcc */
> - if (INTEL_PCH_TYPE(i915) >= PCH_ICP && INTEL_PCH_TYPE(i915) <=
> PCH_MCC)
> - intel_de_rmw(i915, SOUTH_CHICKEN1,
> SBCLK_RUN_REFCLK_DIS, 0);
> -
> } else if (IS_HASWELL(i915) || IS_BROADWELL(i915)) {
> hsw_disable_pc8(i915);
> }
> +
> + /* Tweaked Wa_14010685332:cnp,icp,jsp,mcc,tgp,rkl,adp */
> + if (INTEL_PCH_TYPE(i915) == PCH_CNP ||
> + (INTEL_PCH_TYPE(i915) >= PCH_ICP && INTEL_PCH_TYPE(i915) < PCH_DG1))
> + intel_de_rmw(i915, SOUTH_CHICKEN1, SBCLK_RUN_REFCLK_DIS, 0);
> }
>
> void intel_display_power_suspend(struct drm_i915_private *i915)
> diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
> index 44aed4cbf894..8abcd35df926 100644
> --- a/drivers/gpu/drm/i915/i915_irq.c
> +++ b/drivers/gpu/drm/i915/i915_irq.c
> @@ -3040,24 +3040,6 @@ static void valleyview_irq_reset(struct
> drm_i915_private *dev_priv)
> spin_unlock_irq(&dev_priv->irq_lock);
> }
>
> -static void cnp_display_clock_wa(struct drm_i915_private *dev_priv)
> -{
> - struct intel_uncore *uncore = &dev_priv->uncore;
> -
> - /*
> - * Wa_14010685332:cnp/cmp,tgp,adp
> - * TODO: Clarify which platforms this applies to
> - * TODO: Figure out if this workaround can be applied in the s0ix
> suspend/resume handlers as
> - * on earlier platforms and whether the workaround is also needed for
> runtime suspend/resume
> - */
> - if (INTEL_PCH_TYPE(dev_priv) == PCH_CNP ||
> - (INTEL_PCH_TYPE(dev_priv) >= PCH_TGP && INTEL_PCH_TYPE(dev_priv) <
> PCH_DG1)) {
> - intel_uncore_rmw(uncore, SOUTH_CHICKEN1, SBCLK_RUN_REFCLK_DIS,
> - SBCLK_RUN_REFCLK_DIS);
> - intel_uncore_rmw(uncore, SOUTH_CHICKEN1, SBCLK_RUN_REFCLK_DIS,
> 0);
> - }
> -}
> -
> static void gen8_irq_reset(struct drm_i915_private *dev_priv)
> {
> struct intel_uncore *uncore = &dev_priv->uncore;
> @@ -3082,7 +3064,6 @@ static void gen8_irq_reset(struct drm_i915_private
> *dev_priv)
> if (HAS_PCH_SPLIT(dev_priv))
> ibx_irq_reset(dev_priv);
>
> - cnp_display_clock_wa(dev_priv);
> }
>
> static void gen11_display_irq_reset(struct drm_i915_private *dev_priv)
> @@ -3123,8 +3104,6 @@ static void gen11_display_irq_reset(struct
> drm_i915_private *dev_priv)
>
> if (INTEL_PCH_TYPE(dev_priv) >= PCH_ICP)
> GEN3_IRQ_RESET(uncore, SDE);
> -
> - cnp_display_clock_wa(dev_priv);
> }
>
> static void gen11_irq_reset(struct drm_i915_p
Re: [Intel-gfx] [PATCH] drm/i915: Fix userptr so we do not have to worry about obj->mm.lock, v8.
On Thu, Mar 25, 2021 at 10:55:11AM +0100, Thomas Hellström (Intel) wrote: > > On 3/25/21 10:23 AM, Maarten Lankhorst wrote: > > Instead of doing what we do currently, which will never work with > > PROVE_LOCKING, do the same as AMD does, and something similar to > > relocation slowpath. When all locks are dropped, we acquire the > > pages for pinning. When the locks are taken, we transfer those > > pages in .get_pages() to the bo. As a final check before installing > > the fences, we ensure that the mmu notifier was not called; if it is, > > we return -EAGAIN to userspace to signal it has to start over. > > > > Changes since v1: > > - Unbinding is done in submit_init only. submit_begin() removed. > > - MMU_NOTFIER -> MMU_NOTIFIER > > Changes since v2: > > - Make i915->mm.notifier a spinlock. > > Changes since v3: > > - Add WARN_ON if there are any page references left, should have been 0. > > - Return 0 on success in submit_init(), bug from spinlock conversion. > > - Release pvec outside of notifier_lock (Thomas). > > Changes since v4: > > - Mention why we're clearing eb->[i + 1].vma in the code. (Thomas) > > - Actually check all invalidations in eb_move_to_gpu. (Thomas) > > - Do not wait when process is exiting to fix gem_ctx_persistence.userptr. > > Changes since v5: > > - Clarify why check on PF_EXITING is (temporarily) required. > > Changes since v6: > > - Ensure userptr validity is checked in set_domain through a special path. > > Changes since v7: > > - Chane kvfree to kvfree(). > > v8: Change "Chane kvfree to kvfree()" to "Change kfree() to kvfree()" ? :) Luckily the fix I've done got that part right :-) -Daniel -- Daniel Vetter Software Engineer, Intel Corporation http://blog.ffwll.ch ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH 2/2] drm/i915: Stop adding planes to the commit needlessly
On Thu, Mar 25, 2021 at 11:35:53AM +0200, Lisovskiy, Stanislav wrote:
> On Thu, Mar 25, 2021 at 02:44:15AM +0200, Ville Syrjala wrote:
> > From: Ville Syrjälä
> >
> > The dbuf bandwidth calculations don't need the planes to be
> > added to the state. Each plane's data rate has already been
> > precalculated and stored in the crtc state, and that with
> > the dbuf slice usage for each plane is all the dbuf bandwidth
> > code needs to figure out what the minimum cdclk is.
> >
> > What we're trying to do here is make sure each plane recalculates
> > its minimum cdclk (ie. plane->min_cdclk()) on those platforms where
> > the number of active planes affects the result of said calculation.
> > Nothing to do with any dbuf cdclk requirements.
>
> So does it mean that if we lets say had active plane mask as
> 011(planes 0, 1 were active) and new active planes are 101(planes 0, 2
> are active) - we should not add plane 2 to the state?
> Because hamming weight will be obviously same, however I think it would
> be wrong not have plane 2 in the state at all then..
>
> Or will it be added somewhere else?
If someone is asking to disable plane 2 then it will be added to
the state already during the atomic/setplance ioctl handling.
>
>
> Stan
>
> >
> > Not sure if we had stuff in slightly different order or what,
> > but at least in the current scheme this is not necessary.
> >
> > Cc: Stanislav Lisovskiy
> > Signed-off-by: Ville Syrjälä
> > ---
> > drivers/gpu/drm/i915/display/intel_display.c | 10 ++
> > 1 file changed, 2 insertions(+), 8 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/display/intel_display.c
> > b/drivers/gpu/drm/i915/display/intel_display.c
> > index 17490d29dc13..2300d58ba47f 100644
> > --- a/drivers/gpu/drm/i915/display/intel_display.c
> > +++ b/drivers/gpu/drm/i915/display/intel_display.c
> > @@ -9811,7 +9811,7 @@ static bool active_planes_affects_min_cdclk(struct
> > drm_i915_private *dev_priv)
> > /* See {hsw,vlv,ivb}_plane_ratio() */
> > return IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv) ||
> > IS_CHERRYVIEW(dev_priv) || IS_VALLEYVIEW(dev_priv) ||
> > - IS_IVYBRIDGE(dev_priv) || (DISPLAY_VER(dev_priv) >= 11);
> > + IS_IVYBRIDGE(dev_priv);
> > }
> >
> > static int intel_crtc_add_bigjoiner_planes(struct intel_atomic_state
> > *state,
> > @@ -9898,13 +9898,7 @@ static int intel_atomic_check_planes(struct
> > intel_atomic_state *state)
> > old_active_planes = old_crtc_state->active_planes &
> > ~BIT(PLANE_CURSOR);
> > new_active_planes = new_crtc_state->active_planes &
> > ~BIT(PLANE_CURSOR);
> >
> > - /*
> > -* Not only the number of planes, but if the plane
> > configuration had
> > -* changed might already mean we need to recompute min CDCLK,
> > -* because different planes might consume different amount of
> > Dbuf bandwidth
> > -* according to formula: Bw per plane = Pixel rate * bpp *
> > pipe/plane scale factor
> > -*/
> > - if (old_active_planes == new_active_planes)
> > + if (hweight8(old_active_planes) == hweight8(new_active_planes))
> > continue;
> >
> > ret = intel_crtc_add_planes_to_state(state, crtc,
> > new_active_planes);
> > --
> > 2.26.2
> >
--
Ville Syrjälä
Intel
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[Intel-gfx] [PULL] drm-misc-fixes
drm-misc-fixes-2021-03-25: drm-misc-fixes for v5.12: - Use FOLL_FORCE and FOLL_LONGTERM in etnaviv The following changes since commit 6909115442759efef3d4bc5d9c54d7943f1afc14: drm/omap: dsi: fix unsigned expression compared with zero (2021-03-17 13:59:23 +0200) are available in the Git repository at: git://anongit.freedesktop.org/drm/drm-misc tags/drm-misc-fixes-2021-03-25 for you to fetch changes up to 50891bead80bc79871528c2962d65c781c02330b: drm/etnaviv: User FOLL_LONGTERM in userptr (2021-03-19 20:15:48 +0100) drm-misc-fixes for v5.12: - Use FOLL_FORCE and FOLL_LONGTERM in etnaviv Daniel Vetter (2): drm/etnaviv: Use FOLL_FORCE for userptr drm/etnaviv: User FOLL_LONGTERM in userptr drivers/gpu/drm/etnaviv/etnaviv_gem.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 1/2] drm/i915/display/vlv_dsi: Do not skip panel_pwr_cycle_delay when disabling the panel
After the recently added commit fe0f1e3bfdfe ("drm/i915: Shut down
displays gracefully on reboot"), the DSI panel on a Cherry Trail based
Predia Basic tablet would no longer properly light up after reboot.
I've managed to reproduce this without rebooting by doing:
chvt 3; echo 1 > /sys/class/graphics/fb0/blank;\
echo 0 > /sys/class/graphics/fb0/blank
Which rapidly turns the panel off and back on again.
The vlv_dsi.c code uses an intel_dsi_msleep() helper for the various delays
used for panel on/off, since starting with MIPI-sequences version >= 3 the
delays are already included inside the MIPI-sequences.
The problems exposed by the "Shut down displays gracefully on reboot"
change, show that using this helper for the panel_pwr_cycle_delay is
not the right thing to do. This has not been noticed until now because
normally the panel never is cycled off and directly on again in quick
succession.
Change the msleep for the panel_pwr_cycle_delay to a normal msleep()
call to avoid the panel staying black after a quick off + on cycle.
Cc: Ville Syrjälä
Fixes: fe0f1e3bfdfe ("drm/i915: Shut down displays gracefully on reboot")
Signed-off-by: Hans de Goede
---
drivers/gpu/drm/i915/display/vlv_dsi.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/vlv_dsi.c
b/drivers/gpu/drm/i915/display/vlv_dsi.c
index d5a3f69c5df3..38d5a1f3ded5 100644
--- a/drivers/gpu/drm/i915/display/vlv_dsi.c
+++ b/drivers/gpu/drm/i915/display/vlv_dsi.c
@@ -996,14 +996,14 @@ static void intel_dsi_post_disable(struct
intel_atomic_state *state,
* FIXME As we do with eDP, just make a note of the time here
* and perform the wait before the next panel power on.
*/
- intel_dsi_msleep(intel_dsi, intel_dsi->panel_pwr_cycle_delay);
+ msleep(intel_dsi->panel_pwr_cycle_delay);
}
static void intel_dsi_shutdown(struct intel_encoder *encoder)
{
struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);
- intel_dsi_msleep(intel_dsi, intel_dsi->panel_pwr_cycle_delay);
+ msleep(intel_dsi->panel_pwr_cycle_delay);
}
static bool intel_dsi_get_hw_state(struct intel_encoder *encoder,
--
2.30.2
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[Intel-gfx] [PATCH 2/2] drm/i915/display/vlv_dsi: Move panel_pwr_cycle_delay to next panel-on
Instead of sleeping panel_pwr_cycle_delay ms when turning the panel off,
record the time it is turned off and if necessary wait any (remaining)
time when the panel is turned on again.
Also sleep the remaining time on shutdown, because on reboot the
GOP will immediately turn on the panel again.
Cc: Ville Syrjälä
Signed-off-by: Hans de Goede
---
drivers/gpu/drm/i915/display/intel_dsi.h | 1 +
drivers/gpu/drm/i915/display/vlv_dsi.c | 25 ++--
2 files changed, 20 insertions(+), 6 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_dsi.h
b/drivers/gpu/drm/i915/display/intel_dsi.h
index 625f2f1ae061..50d6da0b2419 100644
--- a/drivers/gpu/drm/i915/display/intel_dsi.h
+++ b/drivers/gpu/drm/i915/display/intel_dsi.h
@@ -124,6 +124,7 @@ struct intel_dsi {
u16 panel_on_delay;
u16 panel_off_delay;
u16 panel_pwr_cycle_delay;
+ ktime_t panel_power_off_time;
};
struct intel_dsi_host {
diff --git a/drivers/gpu/drm/i915/display/vlv_dsi.c
b/drivers/gpu/drm/i915/display/vlv_dsi.c
index 38d5a1f3ded5..3ede55cb3f43 100644
--- a/drivers/gpu/drm/i915/display/vlv_dsi.c
+++ b/drivers/gpu/drm/i915/display/vlv_dsi.c
@@ -717,6 +717,19 @@ static void intel_dsi_port_disable(struct intel_encoder
*encoder)
}
}
+static void intel_dsi_wait_panel_power_cycle(struct intel_dsi *intel_dsi)
+{
+ ktime_t panel_power_on_time;
+ s64 panel_power_off_duration;
+
+ panel_power_on_time = ktime_get_boottime();
+ panel_power_off_duration = ktime_ms_delta(panel_power_on_time,
+
intel_dsi->panel_power_off_time);
+
+ if (panel_power_off_duration < (s64)intel_dsi->panel_pwr_cycle_delay)
+ msleep(intel_dsi->panel_pwr_cycle_delay -
panel_power_off_duration);
+}
+
static void intel_dsi_prepare(struct intel_encoder *intel_encoder,
const struct intel_crtc_state *pipe_config);
static void intel_dsi_unprepare(struct intel_encoder *encoder);
@@ -778,6 +791,8 @@ static void intel_dsi_pre_enable(struct intel_atomic_state
*state,
drm_dbg_kms(&dev_priv->drm, "\n");
+ intel_dsi_wait_panel_power_cycle(intel_dsi);
+
intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
/*
@@ -992,18 +1007,14 @@ static void intel_dsi_post_disable(struct
intel_atomic_state *state,
intel_dsi_msleep(intel_dsi, intel_dsi->panel_off_delay);
intel_dsi_vbt_exec_sequence(intel_dsi, MIPI_SEQ_POWER_OFF);
- /*
-* FIXME As we do with eDP, just make a note of the time here
-* and perform the wait before the next panel power on.
-*/
- msleep(intel_dsi->panel_pwr_cycle_delay);
+ intel_dsi->panel_power_off_time = ktime_get_boottime();
}
static void intel_dsi_shutdown(struct intel_encoder *encoder)
{
struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);
- msleep(intel_dsi->panel_pwr_cycle_delay);
+ intel_dsi_wait_panel_power_cycle(intel_dsi);
}
static bool intel_dsi_get_hw_state(struct intel_encoder *encoder,
@@ -1884,6 +1895,8 @@ void vlv_dsi_init(struct drm_i915_private *dev_priv)
else
intel_encoder->pipe_mask = BIT(PIPE_B);
+ intel_dsi->panel_power_off_time = ktime_get_boottime();
+
if (dev_priv->vbt.dsi.config->dual_link)
intel_dsi->ports = BIT(PORT_A) | BIT(PORT_C);
else
--
2.30.2
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[Intel-gfx] [PATCH v2] drm/i915: Tweaked Wa_14010685332 for all PCHs
dispcnlunit1_cp_xosc_clkreq clock observed to be active on TGL-H platform
despite Wa_14010685332 original sequence, thus blocks entry to deeper s0ix
state.
The Tweaked Wa_14010685332 sequence fixes this issue, therefore use tweaked
Wa_14010685332 sequence for every PCH since PCH_CNP.
v2:
- removed RKL from comment and simplified condition. [Rodrigo]
Fixes: b896898c7369 ("drm/i915: Tweaked Wa_14010685332 for PCHs used on gen11
platforms")
Cc: Matt Roper
Cc: Rodrigo Vivi
Cc: Imre Deak
Signed-off-by: Anshuman Gupta
---
.../drm/i915/display/intel_display_power.c| 16 +++---
drivers/gpu/drm/i915/i915_irq.c | 21 ---
2 files changed, 8 insertions(+), 29 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c
b/drivers/gpu/drm/i915/display/intel_display_power.c
index cef177208e68..b76cc4379d5c 100644
--- a/drivers/gpu/drm/i915/display/intel_display_power.c
+++ b/drivers/gpu/drm/i915/display/intel_display_power.c
@@ -5910,13 +5910,13 @@ void intel_display_power_suspend_late(struct
drm_i915_private *i915)
{
if (DISPLAY_VER(i915) >= 11 || IS_GEN9_LP(i915)) {
bxt_enable_dc9(i915);
- /* Tweaked Wa_14010685332:icp,jsp,mcc */
- if (INTEL_PCH_TYPE(i915) >= PCH_ICP && INTEL_PCH_TYPE(i915) <=
PCH_MCC)
- intel_de_rmw(i915, SOUTH_CHICKEN1,
-SBCLK_RUN_REFCLK_DIS,
SBCLK_RUN_REFCLK_DIS);
} else if (IS_HASWELL(i915) || IS_BROADWELL(i915)) {
hsw_enable_pc8(i915);
}
+
+ /* Tweaked Wa_14010685332:cnp,icp,jsp,mcc,tgp,adp */
+ if (INTEL_PCH_TYPE(i915) >= PCH_CNP && INTEL_PCH_TYPE(i915) < PCH_DG1)
+ intel_de_rmw(i915, SOUTH_CHICKEN1, SBCLK_RUN_REFCLK_DIS,
SBCLK_RUN_REFCLK_DIS);
}
void intel_display_power_resume_early(struct drm_i915_private *i915)
@@ -5924,13 +5924,13 @@ void intel_display_power_resume_early(struct
drm_i915_private *i915)
if (DISPLAY_VER(i915) >= 11 || IS_GEN9_LP(i915)) {
gen9_sanitize_dc_state(i915);
bxt_disable_dc9(i915);
- /* Tweaked Wa_14010685332:icp,jsp,mcc */
- if (INTEL_PCH_TYPE(i915) >= PCH_ICP && INTEL_PCH_TYPE(i915) <=
PCH_MCC)
- intel_de_rmw(i915, SOUTH_CHICKEN1,
SBCLK_RUN_REFCLK_DIS, 0);
-
} else if (IS_HASWELL(i915) || IS_BROADWELL(i915)) {
hsw_disable_pc8(i915);
}
+
+ /* Tweaked Wa_14010685332:cnp,icp,jsp,mcc,tgp,adp */
+ if (INTEL_PCH_TYPE(i915) >= PCH_CNP && INTEL_PCH_TYPE(i915) < PCH_DG1)
+ intel_de_rmw(i915, SOUTH_CHICKEN1, SBCLK_RUN_REFCLK_DIS, 0);
}
void intel_display_power_suspend(struct drm_i915_private *i915)
diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index 7eefbdec25a2..4547ba2f19b2 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -3040,24 +3040,6 @@ static void valleyview_irq_reset(struct drm_i915_private
*dev_priv)
spin_unlock_irq(&dev_priv->irq_lock);
}
-static void cnp_display_clock_wa(struct drm_i915_private *dev_priv)
-{
- struct intel_uncore *uncore = &dev_priv->uncore;
-
- /*
-* Wa_14010685332:cnp/cmp,tgp,adp
-* TODO: Clarify which platforms this applies to
-* TODO: Figure out if this workaround can be applied in the s0ix
suspend/resume handlers as
-* on earlier platforms and whether the workaround is also needed for
runtime suspend/resume
-*/
- if (INTEL_PCH_TYPE(dev_priv) == PCH_CNP ||
- (INTEL_PCH_TYPE(dev_priv) >= PCH_TGP && INTEL_PCH_TYPE(dev_priv) <
PCH_DG1)) {
- intel_uncore_rmw(uncore, SOUTH_CHICKEN1, SBCLK_RUN_REFCLK_DIS,
-SBCLK_RUN_REFCLK_DIS);
- intel_uncore_rmw(uncore, SOUTH_CHICKEN1, SBCLK_RUN_REFCLK_DIS,
0);
- }
-}
-
static void gen8_irq_reset(struct drm_i915_private *dev_priv)
{
struct intel_uncore *uncore = &dev_priv->uncore;
@@ -3082,7 +3064,6 @@ static void gen8_irq_reset(struct drm_i915_private
*dev_priv)
if (HAS_PCH_SPLIT(dev_priv))
ibx_irq_reset(dev_priv);
- cnp_display_clock_wa(dev_priv);
}
static void gen11_display_irq_reset(struct drm_i915_private *dev_priv)
@@ -3123,8 +3104,6 @@ static void gen11_display_irq_reset(struct
drm_i915_private *dev_priv)
if (INTEL_PCH_TYPE(dev_priv) >= PCH_ICP)
GEN3_IRQ_RESET(uncore, SDE);
-
- cnp_display_clock_wa(dev_priv);
}
static void gen11_irq_reset(struct drm_i915_private *dev_priv)
--
2.26.2
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Re: [Intel-gfx] [PATCH v2] drm/i915: Tweaked Wa_14010685332 for all PCHs
On Thu, Mar 25, 2021 at 05:39:47PM +0530, Anshuman Gupta wrote:
> dispcnlunit1_cp_xosc_clkreq clock observed to be active on TGL-H platform
> despite Wa_14010685332 original sequence, thus blocks entry to deeper s0ix
> state.
>
> The Tweaked Wa_14010685332 sequence fixes this issue, therefore use tweaked
> Wa_14010685332 sequence for every PCH since PCH_CNP.
>
> v2:
> - removed RKL from comment and simplified condition. [Rodrigo]
>
> Fixes: b896898c7369 ("drm/i915: Tweaked Wa_14010685332 for PCHs used on gen11
> platforms")
> Cc: Matt Roper
> Cc: Rodrigo Vivi
> Cc: Imre Deak
> Signed-off-by: Anshuman Gupta
Reviewed-by: Rodrigo Vivi
> ---
> .../drm/i915/display/intel_display_power.c| 16 +++---
> drivers/gpu/drm/i915/i915_irq.c | 21 ---
> 2 files changed, 8 insertions(+), 29 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c
> b/drivers/gpu/drm/i915/display/intel_display_power.c
> index cef177208e68..b76cc4379d5c 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_power.c
> +++ b/drivers/gpu/drm/i915/display/intel_display_power.c
> @@ -5910,13 +5910,13 @@ void intel_display_power_suspend_late(struct
> drm_i915_private *i915)
> {
> if (DISPLAY_VER(i915) >= 11 || IS_GEN9_LP(i915)) {
> bxt_enable_dc9(i915);
> - /* Tweaked Wa_14010685332:icp,jsp,mcc */
> - if (INTEL_PCH_TYPE(i915) >= PCH_ICP && INTEL_PCH_TYPE(i915) <=
> PCH_MCC)
> - intel_de_rmw(i915, SOUTH_CHICKEN1,
> - SBCLK_RUN_REFCLK_DIS,
> SBCLK_RUN_REFCLK_DIS);
> } else if (IS_HASWELL(i915) || IS_BROADWELL(i915)) {
> hsw_enable_pc8(i915);
> }
> +
> + /* Tweaked Wa_14010685332:cnp,icp,jsp,mcc,tgp,adp */
> + if (INTEL_PCH_TYPE(i915) >= PCH_CNP && INTEL_PCH_TYPE(i915) < PCH_DG1)
> + intel_de_rmw(i915, SOUTH_CHICKEN1, SBCLK_RUN_REFCLK_DIS,
> SBCLK_RUN_REFCLK_DIS);
> }
>
> void intel_display_power_resume_early(struct drm_i915_private *i915)
> @@ -5924,13 +5924,13 @@ void intel_display_power_resume_early(struct
> drm_i915_private *i915)
> if (DISPLAY_VER(i915) >= 11 || IS_GEN9_LP(i915)) {
> gen9_sanitize_dc_state(i915);
> bxt_disable_dc9(i915);
> - /* Tweaked Wa_14010685332:icp,jsp,mcc */
> - if (INTEL_PCH_TYPE(i915) >= PCH_ICP && INTEL_PCH_TYPE(i915) <=
> PCH_MCC)
> - intel_de_rmw(i915, SOUTH_CHICKEN1,
> SBCLK_RUN_REFCLK_DIS, 0);
> -
> } else if (IS_HASWELL(i915) || IS_BROADWELL(i915)) {
> hsw_disable_pc8(i915);
> }
> +
> + /* Tweaked Wa_14010685332:cnp,icp,jsp,mcc,tgp,adp */
> + if (INTEL_PCH_TYPE(i915) >= PCH_CNP && INTEL_PCH_TYPE(i915) < PCH_DG1)
> + intel_de_rmw(i915, SOUTH_CHICKEN1, SBCLK_RUN_REFCLK_DIS, 0);
> }
>
> void intel_display_power_suspend(struct drm_i915_private *i915)
> diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
> index 7eefbdec25a2..4547ba2f19b2 100644
> --- a/drivers/gpu/drm/i915/i915_irq.c
> +++ b/drivers/gpu/drm/i915/i915_irq.c
> @@ -3040,24 +3040,6 @@ static void valleyview_irq_reset(struct
> drm_i915_private *dev_priv)
> spin_unlock_irq(&dev_priv->irq_lock);
> }
>
> -static void cnp_display_clock_wa(struct drm_i915_private *dev_priv)
> -{
> - struct intel_uncore *uncore = &dev_priv->uncore;
> -
> - /*
> - * Wa_14010685332:cnp/cmp,tgp,adp
> - * TODO: Clarify which platforms this applies to
> - * TODO: Figure out if this workaround can be applied in the s0ix
> suspend/resume handlers as
> - * on earlier platforms and whether the workaround is also needed for
> runtime suspend/resume
> - */
> - if (INTEL_PCH_TYPE(dev_priv) == PCH_CNP ||
> - (INTEL_PCH_TYPE(dev_priv) >= PCH_TGP && INTEL_PCH_TYPE(dev_priv) <
> PCH_DG1)) {
> - intel_uncore_rmw(uncore, SOUTH_CHICKEN1, SBCLK_RUN_REFCLK_DIS,
> - SBCLK_RUN_REFCLK_DIS);
> - intel_uncore_rmw(uncore, SOUTH_CHICKEN1, SBCLK_RUN_REFCLK_DIS,
> 0);
> - }
> -}
> -
> static void gen8_irq_reset(struct drm_i915_private *dev_priv)
> {
> struct intel_uncore *uncore = &dev_priv->uncore;
> @@ -3082,7 +3064,6 @@ static void gen8_irq_reset(struct drm_i915_private
> *dev_priv)
> if (HAS_PCH_SPLIT(dev_priv))
> ibx_irq_reset(dev_priv);
>
> - cnp_display_clock_wa(dev_priv);
> }
>
> static void gen11_display_irq_reset(struct drm_i915_private *dev_priv)
> @@ -3123,8 +3104,6 @@ static void gen11_display_irq_reset(struct
> drm_i915_private *dev_priv)
>
> if (INTEL_PCH_TYPE(dev_priv) >= PCH_ICP)
> GEN3_IRQ_RESET(uncore, SDE);
> -
> - cnp_display_clock_wa(dev_priv);
> }
>
> static void gen11_irq_reset(struct drm_i915_private *dev_priv)
> --
> 2.26.2
>
> ___
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> Intel-g
Re: [Intel-gfx] [PATCH v2 0/2] HDCP 2.2 DP errata
On Wed, 24 Mar 2021, Anshuman Gupta wrote: > HDCP DP 2.2 errata is part of HDCP DP 2.3 specs > as well. > > Anshuman Gupta (2): > drm/i915/hdcp: Add DP HDCP2.2 timeout to read entire msg > drm/hdcp: DP HDCP2.2 errata LC_Send_L_Prime=16 > > drivers/gpu/drm/i915/display/intel_dp_hdcp.c | 45 ++-- > include/drm/drm_hdcp.h | 5 ++- > 2 files changed, 36 insertions(+), 14 deletions(-) Maarten, Maxime, Thomas - Can I get an ack for merging this via drm-intel-next, please? BR, Jani. -- Jani Nikula, Intel Open Source Graphics Center ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH 11/11] [RFC] drm/i915/dp: fix array overflow warning
On Thu, Mar 25, 2021 at 9:05 AM Jani Nikula wrote:
> > Clearly something is wrong here, but I can't quite figure out what.
> > Changing the array size to 16 bytes avoids the warning, but is
> > probably the wrong solution here.
>
> Ugh. drm_dp_channel_eq_ok() does not actually require more than
> DP_LINK_STATUS_SIZE - 2 elements in the link_status. It's some other
> related functions that do, and in most cases it's convenient to read all
> those DP_LINK_STATUS_SIZE bytes.
>
> However, here the case is slightly different for DP MST, and the change
> causes reserved DPCD addresses to be read. Not sure it matters, but
> really I think the problem is what drm_dp_channel_eq_ok() advertizes.
>
> I also don't like the array notation with sizes in function parameters
> in general, because I think it's misleading. Would gcc-11 warn if a
> function actually accesses the memory out of bounds of the size?
Yes, that is the point of the warning. Using an explicit length in an
array argument type tells gcc that the function will never access
beyond the end of that bound, and that passing a short array
is a bug.
I don't know if this /only/ means triggering a warning, or if gcc
is also able to make optimizations after classifying this as undefined
behavior that it would not make for an unspecified length.
> Anyway. I don't think we're going to get rid of the array notation
> anytime soon, if ever, no matter how much I dislike it, so I think the
> right fix would be to at least state the correct required size in
> drm_dp_channel_eq_ok().
Ok. Just to confirm: Changing the declaration to an unspecified length
avoids the warnings, as does the patch below:
diff --git a/drivers/gpu/drm/drm_dp_helper.c b/drivers/gpu/drm/drm_dp_helper.c
index eedbb48815b7..6ebeec3d88a7 100644
--- a/drivers/gpu/drm/drm_dp_helper.c
+++ b/drivers/gpu/drm/drm_dp_helper.c
@@ -46,12 +46,12 @@
*/
/* Helpers for DP link training */
-static u8 dp_link_status(const u8 link_status[DP_LINK_STATUS_SIZE], int r)
+static u8 dp_link_status(const u8 link_status[DP_LINK_STATUS_SIZE - 2], int r)
{
return link_status[r - DP_LANE0_1_STATUS];
}
-static u8 dp_get_lane_status(const u8 link_status[DP_LINK_STATUS_SIZE],
+static u8 dp_get_lane_status(const u8 link_status[DP_LINK_STATUS_SIZE - 2],
int lane)
{
int i = DP_LANE0_1_STATUS + (lane >> 1);
@@ -61,7 +61,7 @@ static u8 dp_get_lane_status(const u8
link_status[DP_LINK_STATUS_SIZE],
return (l >> s) & 0xf;
}
-bool drm_dp_channel_eq_ok(const u8 link_status[DP_LINK_STATUS_SIZE],
+bool drm_dp_channel_eq_ok(const u8 link_status[DP_LINK_STATUS_SIZE - 2],
int lane_count)
{
u8 lane_align;
diff --git a/include/drm/drm_dp_helper.h b/include/drm/drm_dp_helper.h
index edffd1dcca3e..160f7fd127b1 100644
--- a/include/drm/drm_dp_helper.h
+++ b/include/drm/drm_dp_helper.h
@@ -1456,7 +1456,7 @@ enum drm_dp_phy {
#define DP_LINK_CONSTANT_N_VALUE 0x8000
#define DP_LINK_STATUS_SIZE 6
-bool drm_dp_channel_eq_ok(const u8 link_status[DP_LINK_STATUS_SIZE],
+bool drm_dp_channel_eq_ok(const u8 link_status[DP_LINK_STATUS_SIZE - 2],
int lane_count);
bool drm_dp_clock_recovery_ok(const u8 link_status[DP_LINK_STATUS_SIZE],
int lane_count);
This obviously needs a good explanation in the code and the changelog text,
which I don't have, but if the above is what you had in mind, please take that
and add Reported-by/Tested-by: Arnd Bergmann .
Arnd
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Re: [Intel-gfx] [PATCH 11/11] [RFC] drm/i915/dp: fix array overflow warning
On 3/25/21 3:53 AM, Arnd Bergmann wrote:
On Thu, Mar 25, 2021 at 9:05 AM Jani Nikula wrote:
Clearly something is wrong here, but I can't quite figure out what.
Changing the array size to 16 bytes avoids the warning, but is
probably the wrong solution here.
Ugh. drm_dp_channel_eq_ok() does not actually require more than
DP_LINK_STATUS_SIZE - 2 elements in the link_status. It's some other
related functions that do, and in most cases it's convenient to read all
those DP_LINK_STATUS_SIZE bytes.
However, here the case is slightly different for DP MST, and the change
causes reserved DPCD addresses to be read. Not sure it matters, but
really I think the problem is what drm_dp_channel_eq_ok() advertizes.
I also don't like the array notation with sizes in function parameters
in general, because I think it's misleading. Would gcc-11 warn if a
function actually accesses the memory out of bounds of the size?
Yes, that is the point of the warning. Using an explicit length in an
array argument type tells gcc that the function will never access
beyond the end of that bound, and that passing a short array
is a bug.
I don't know if this /only/ means triggering a warning, or if gcc
is also able to make optimizations after classifying this as undefined
behavior that it would not make for an unspecified length.
GCC uses the array parameter notation as a hint for warnings but
it doesn't optimize on this basis and never will be able to because
code that accesses more elements from the array isn't invalid.
Adding static to the bound, as in void f (int[static N]) does
imply that the function won't access more than N elements and
C intends for optimizers to rely on it, although GCC doesn't yet.
The warning for the array notation is a more portable alternative
to explicitly annotating functions with attribute access, and to
-Wvla-parameter for VLA parameters. The latter seem to be used
relatively rarely, sometimes deliberately because of the bad rap
of VLA objects, even though VLA parameters don't suffer from
the same problems.
Martin
Anyway. I don't think we're going to get rid of the array notation
anytime soon, if ever, no matter how much I dislike it, so I think the
right fix would be to at least state the correct required size in
drm_dp_channel_eq_ok().
Ok. Just to confirm: Changing the declaration to an unspecified length
avoids the warnings, as does the patch below:
diff --git a/drivers/gpu/drm/drm_dp_helper.c b/drivers/gpu/drm/drm_dp_helper.c
index eedbb48815b7..6ebeec3d88a7 100644
--- a/drivers/gpu/drm/drm_dp_helper.c
+++ b/drivers/gpu/drm/drm_dp_helper.c
@@ -46,12 +46,12 @@
*/
/* Helpers for DP link training */
-static u8 dp_link_status(const u8 link_status[DP_LINK_STATUS_SIZE], int r)
+static u8 dp_link_status(const u8 link_status[DP_LINK_STATUS_SIZE - 2], int r)
{
return link_status[r - DP_LANE0_1_STATUS];
}
-static u8 dp_get_lane_status(const u8 link_status[DP_LINK_STATUS_SIZE],
+static u8 dp_get_lane_status(const u8 link_status[DP_LINK_STATUS_SIZE - 2],
int lane)
{
int i = DP_LANE0_1_STATUS + (lane >> 1);
@@ -61,7 +61,7 @@ static u8 dp_get_lane_status(const u8
link_status[DP_LINK_STATUS_SIZE],
return (l >> s) & 0xf;
}
-bool drm_dp_channel_eq_ok(const u8 link_status[DP_LINK_STATUS_SIZE],
+bool drm_dp_channel_eq_ok(const u8 link_status[DP_LINK_STATUS_SIZE - 2],
int lane_count)
{
u8 lane_align;
diff --git a/include/drm/drm_dp_helper.h b/include/drm/drm_dp_helper.h
index edffd1dcca3e..160f7fd127b1 100644
--- a/include/drm/drm_dp_helper.h
+++ b/include/drm/drm_dp_helper.h
@@ -1456,7 +1456,7 @@ enum drm_dp_phy {
#define DP_LINK_CONSTANT_N_VALUE 0x8000
#define DP_LINK_STATUS_SIZE 6
-bool drm_dp_channel_eq_ok(const u8 link_status[DP_LINK_STATUS_SIZE],
+bool drm_dp_channel_eq_ok(const u8 link_status[DP_LINK_STATUS_SIZE - 2],
int lane_count);
bool drm_dp_clock_recovery_ok(const u8 link_status[DP_LINK_STATUS_SIZE],
int lane_count);
This obviously needs a good explanation in the code and the changelog text,
which I don't have, but if the above is what you had in mind, please take that
and add Reported-by/Tested-by: Arnd Bergmann .
Arnd
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[Intel-gfx] ✗ Fi.CI.DOCS: warning for drm/i915: missing workarounds and refactors
== Series Details == Series: drm/i915: missing workarounds and refactors URL : https://patchwork.freedesktop.org/series/88408/ State : warning == Summary == $ make htmldocs 2>&1 > /dev/null | grep i915 ./drivers/gpu/drm/i915/gem/i915_gem_shrinker.c:102: warning: Function parameter or member 'ww' not described in 'i915_gem_shrink' ./drivers/gpu/drm/i915/i915_cmd_parser.c:1420: warning: Excess function parameter 'trampoline' description in 'intel_engine_cmd_parser' ./drivers/gpu/drm/i915/i915_cmd_parser.c:1420: warning: Function parameter or member 'jump_whitelist' not described in 'intel_engine_cmd_parser' ./drivers/gpu/drm/i915/i915_cmd_parser.c:1420: warning: Function parameter or member 'shadow_map' not described in 'intel_engine_cmd_parser' ./drivers/gpu/drm/i915/i915_cmd_parser.c:1420: warning: Function parameter or member 'batch_map' not described in 'intel_engine_cmd_parser' ./drivers/gpu/drm/i915/i915_cmd_parser.c:1420: warning: Excess function parameter 'trampoline' description in 'intel_engine_cmd_parser' /home/cidrm/kernel/Documentation/gpu/i915:22: ./drivers/gpu/drm/i915/intel_runtime_pm.c:423: WARNING: Inline strong start-string without end-string. ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✗ Fi.CI.BAT: failure for drm/i915: missing workarounds and refactors
== Series Details ==
Series: drm/i915: missing workarounds and refactors
URL : https://patchwork.freedesktop.org/series/88408/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_9894 -> Patchwork_19849
Summary
---
**FAILURE**
Serious unknown changes coming with Patchwork_19849 absolutely need to be
verified manually.
If you think the reported changes have nothing to do with the changes
introduced in Patchwork_19849, please notify your bug team to allow them
to document this new failure mode, which will reduce false positives in CI.
External URL:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19849/index.html
Possible new issues
---
Here are the unknown changes that may have been introduced in Patchwork_19849:
### IGT changes ###
Possible regressions
* igt@prime_vgem@basic-userptr:
- fi-icl-y: NOTRUN -> [SKIP][1]
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19849/fi-icl-y/igt@prime_v...@basic-userptr.html
Suppressed
The following results come from untrusted machines, tests, or statuses.
They do not affect the overall result.
* igt@gem_exec_parallel@engines@contexts:
- {fi-rkl-11500t}:[FAIL][2] ([i915#3277]) -> [FAIL][3]
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9894/fi-rkl-11500t/igt@gem_exec_parallel@engi...@contexts.html
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19849/fi-rkl-11500t/igt@gem_exec_parallel@engi...@contexts.html
Known issues
Here are the changes found in Patchwork_19849 that come from known issues:
### IGT changes ###
Issues hit
* igt@amdgpu/amd_basic@semaphore:
- fi-icl-y: NOTRUN -> [SKIP][4] ([fdo#109315]) +17 similar issues
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19849/fi-icl-y/igt@amdgpu/amd_ba...@semaphore.html
* igt@gem_huc_copy@huc-copy:
- fi-icl-y: NOTRUN -> [SKIP][5] ([i915#2190])
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19849/fi-icl-y/igt@gem_huc_c...@huc-copy.html
* igt@gem_tiled_blits@basic:
- fi-tgl-y: [PASS][6] -> [DMESG-WARN][7] ([i915#402]) +1 similar
issue
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9894/fi-tgl-y/igt@gem_tiled_bl...@basic.html
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19849/fi-tgl-y/igt@gem_tiled_bl...@basic.html
* igt@kms_chamelium@dp-crc-fast:
- fi-icl-y: NOTRUN -> [SKIP][8] ([fdo#109284] / [fdo#111827]) +8
similar issues
[8]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19849/fi-icl-y/igt@kms_chamel...@dp-crc-fast.html
* igt@kms_force_connector_basic@force-load-detect:
- fi-icl-y: NOTRUN -> [SKIP][9] ([fdo#109285])
[9]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19849/fi-icl-y/igt@kms_force_connector_ba...@force-load-detect.html
* igt@kms_pipe_crc_basic@compare-crc-sanitycheck-pipe-d:
- fi-icl-y: NOTRUN -> [SKIP][10] ([fdo#109278])
[10]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19849/fi-icl-y/igt@kms_pipe_crc_ba...@compare-crc-sanitycheck-pipe-d.html
* igt@kms_psr@primary_mmap_gtt:
- fi-icl-y: NOTRUN -> [SKIP][11] ([fdo#110189]) +3 similar issues
[11]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19849/fi-icl-y/igt@kms_psr@primary_mmap_gtt.html
Possible fixes
* igt@gem_flink_basic@bad-open:
- fi-tgl-y: [DMESG-WARN][12] ([i915#402]) -> [PASS][13]
[12]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9894/fi-tgl-y/igt@gem_flink_ba...@bad-open.html
[13]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19849/fi-tgl-y/igt@gem_flink_ba...@bad-open.html
* igt@i915_selftest@live@gt_heartbeat:
- fi-tgl-y: [DMESG-FAIL][14] -> [PASS][15]
[14]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9894/fi-tgl-y/igt@i915_selftest@live@gt_heartbeat.html
[15]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19849/fi-tgl-y/igt@i915_selftest@live@gt_heartbeat.html
* igt@i915_selftest@live@workarounds:
- fi-tgl-u2: [DMESG-WARN][16] ([i915#2867]) -> [PASS][17] +15
similar issues
[16]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9894/fi-tgl-u2/igt@i915_selftest@l...@workarounds.html
[17]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19849/fi-tgl-u2/igt@i915_selftest@l...@workarounds.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#109278]: https://bugs.freedesktop.org/show_bug.cgi?id=109278
[fdo#109284]: https://bugs.freedesktop.org/show_bug.cgi?id=109284
[fdo#109285]: https://bugs.freedesktop.org/show_bug.cgi?id=109285
[fdo#109315]: https://bugs.freedesktop.org/show_bug.cgi?id=109315
[fdo#110189]: https://bugs.freedesktop.org/show_bug.cgi?id=110189
[fdo#111827]: http
[Intel-gfx] [PATCH v2 03/50] drm/i915/xelpd: Enhanced pipe underrun reporting
XE_LPD brings enhanced underrun recovery: the hardware can somewhat
mitigate underruns by using an interpolated replacement pixel (soft
underrun) or the previous pixel (hard underrun). Furthermore, underruns
can now be caused downstream by the port, even if the pipe itself is
operating properly. The interrupt register and PIPE_STATUS register
give us extra bits to recognize hard/soft underruns and determine
whether the underrun was caused by the port, so we'll use that
information to print some more descriptive errors when underruns occur.
v2:
- Keep ICL's PIPE_STATUS defined separately from the old GMCH pipe
status register. (Ville)
- Only read/clear the PIPE_STATUS register on platforms with
display ver >= 11. (Lucas)
Bspec: 50335
Bspec: 50366
Cc: Lucas De Marchi
Cc: Ville Syrjälä
Signed-off-by: Matt Roper
---
.../drm/i915/display/intel_fifo_underrun.c| 65 ++-
drivers/gpu/drm/i915/i915_irq.c | 14 +++-
drivers/gpu/drm/i915/i915_reg.h | 8 +++
3 files changed, 84 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_fifo_underrun.c
b/drivers/gpu/drm/i915/display/intel_fifo_underrun.c
index 9605a1064366..b194453838ac 100644
--- a/drivers/gpu/drm/i915/display/intel_fifo_underrun.c
+++ b/drivers/gpu/drm/i915/display/intel_fifo_underrun.c
@@ -359,6 +359,39 @@ bool intel_set_pch_fifo_underrun_reporting(struct
drm_i915_private *dev_priv,
return old;
}
+static u32
+underrun_pipestat_mask(struct drm_i915_private *dev_priv)
+{
+ u32 mask = PIPE_FIFO_UNDERRUN_STATUS;
+
+ if (DISPLAY_VER(dev_priv) >= 13)
+ mask |= PIPE_STAT_SOFT_UNDERRUN_XELPD |
+ PIPE_STAT_HARD_UNDERRUN_XELPD |
+ PIPE_STAT_PORT_UNDERRUN_XELPD;
+
+ return mask;
+}
+
+static const char *
+pipe_underrun_reason(u32 pipestat_underruns)
+{
+ if (pipestat_underruns & PIPE_STAT_SOFT_UNDERRUN_XELPD)
+ /*
+* Hardware used replacement/interpolated pixels at
+* underrun locations.
+*/
+ return "soft";
+ else if (pipestat_underruns & PIPE_STAT_HARD_UNDERRUN_XELPD)
+ /*
+* Hardware used previous pixel value at underrun
+* locations.
+*/
+ return "hard";
+ else
+ /* Old platform or no extra soft/hard bit set */
+ return "FIFO";
+}
+
/**
* intel_cpu_fifo_underrun_irq_handler - handle CPU fifo underrun interrupt
* @dev_priv: i915 device instance
@@ -372,6 +405,7 @@ void intel_cpu_fifo_underrun_irq_handler(struct
drm_i915_private *dev_priv,
enum pipe pipe)
{
struct intel_crtc *crtc = intel_get_crtc_for_pipe(dev_priv, pipe);
+ u32 underruns = 0;
/* We may be called too early in init, thanks BIOS! */
if (crtc == NULL)
@@ -382,10 +416,37 @@ void intel_cpu_fifo_underrun_irq_handler(struct
drm_i915_private *dev_priv,
crtc->cpu_fifo_underrun_disabled)
return;
+ /*
+* Starting with display version 11, the PIPE_STAT register records
+* whether an underrun has happened, and on XELPD+, it will also record
+* whether the underrun was soft/hard and whether it was triggered by
+* the downstream port logic. We should clear these bits (which use
+* write-1-to-clear logic) too.
+*
+* Note that although the IIR gives us the same underrun and soft/hard
+* information, PIPE_STAT is the only place we can find out whether
+* the underrun was caused by the downstream port.
+*/
+ if (DISPLAY_VER(dev_priv) >= 11) {
+ underruns = intel_uncore_read(&dev_priv->uncore,
+ ICL_PIPESTATUS(pipe)) &
+ underrun_pipestat_mask(dev_priv);
+ intel_uncore_write(&dev_priv->uncore, ICL_PIPESTATUS(pipe),
+ underruns);
+ }
+
if (intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false)) {
trace_intel_cpu_fifo_underrun(dev_priv, pipe);
- drm_err(&dev_priv->drm, "CPU pipe %c FIFO underrun\n",
- pipe_name(pipe));
+
+ if (underruns & PIPE_STAT_PORT_UNDERRUN_XELPD)
+ /* Underrun was caused downstream from the pipes */
+ drm_err(&dev_priv->drm, "Port triggered a %s underrun
on pipe %c\n",
+ pipe_underrun_reason(underruns),
+ pipe_name(pipe));
+ else
+ drm_err(&dev_priv->drm, "CPU pipe %c %s underrun\n",
+ pipe_name(pipe),
+ pipe_underrun_reason(underruns));
}
intel_fbc_handle_fifo_underrun_irq(dev_priv);
diff --git a/dri
[Intel-gfx] [PATCH v2 01/50] drm/i915/xelpd: add XE_LPD display characteristics
Let's start preparing for upcoming platforms that will use an XE_LPD
design.
v2:
- Use the now-preferred "XE_LPD" term to refer to this design
- Utilize DISPLAY_VER() rather than a feature flag
- Drop unused mbus_size field (Lucas)
Signed-off-by: Matt Roper
---
drivers/gpu/drm/i915/i915_pci.c | 10 ++
1 file changed, 10 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
index 480553746794..295a39bc7a2f 100644
--- a/drivers/gpu/drm/i915/i915_pci.c
+++ b/drivers/gpu/drm/i915/i915_pci.c
@@ -936,6 +936,16 @@ static const struct intel_device_info adl_s_info = {
.dma_mask_size = 46,
};
+#define XE_LPD_FEATURES \
+ .display.version = 13, \
+ .display.has_psr_hw_tracking = 0, \
+ .abox_mask = GENMASK(1, 0), \
+ .pipe_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C) | BIT(PIPE_D), \
+ .cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B) | \
+ BIT(TRANSCODER_C) | BIT(TRANSCODER_D), \
+ .ddb_size = 4096, \
+ .num_supported_dbuf_slices = 4
+
#undef GEN
#undef PLATFORM
--
2.25.4
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[Intel-gfx] [PATCH v2 00/50] Introduce Alder Lake-P
The previous version of this series was here: https://lists.freedesktop.org/archives/intel-gfx/2021-March/262168.html The preparation patches that convert display/ to use DISPLAY_VER() instead of INTEL_GEN() have landed on drm-tip now, so this is mostly just a straightforward rebase of the remaining patches. I think there was only one minor functional fix to the last patch of the series (PSR changes). Cc: Clinton Taylor Cc: Lucas De Marchi Animesh Manna (3): drm/i915/bigjoiner: Mode validation with uncompressed pipe joiner drm/i915/bigjoiner: Avoid dsc_compute_config for uncompressed bigjoiner drm/i915/bigjoiner: atomic commit changes for uncompressed joiner Anusha Srivatsa (7): drm/i915/adl_p: Load DMC drm/i915/adl_p: Setup ports/phys drm/i915/adl_p: Add cdclk support for ADL-P drm/i915/adl_p: Add initial ADL_P Workarounds drm/i915/adl_p: Add PLL Support drm/i915/adlp: Add PIPE_MISC2 programming drm/i915/adl_p: Update memory bandwidth parameters Clint Taylor (1): drm/i915/adlp: Define GuC/HuC for Alderlake_P Clinton Taylor (3): drm/i915/adl_p: Add PCI Devices IDs drm/i915/adl_p: ADL_P device info enabling drm/i915/adl_p: Add PCH support José Roberto de Souza (9): drm/i915/display/tc: Rename safe_mode functions ownership drm/i915/adl_p: Handle TC cold drm/i915/adl_p: Implement TC sequences drm/i915/adl_p: Enable modular fia drm/i915/adl_p: Don't config MBUS and DBUF during display initialization drm/i915/adl_p: Implement Wa_22011091694 drm/i915/display/adl_p: Implement Wa_22011320316 drm/i915/display/adl_p: Remove CCS support drm/i915/display/adl_p: Implement PSR changes Juha-Pekka Heikkilä (1): drm/i915/xelpd: Support 128k plane stride Manasi Navare (1): drm/i915/xelpd: Add VRR guardband for VRR CTL Matt Roper (11): drm/i915/xelpd: add XE_LPD display characteristics drm/i915/xelpd: Handle proper AUX interrupt bits drm/i915/xelpd: Enhanced pipe underrun reporting drm/i915/xelpd: Define plane capabilities drm/i915/xelpd: Handle new location of outputs D and E drm/i915/xelpd: Add XE_LPD power wells drm/i915/xelpd: Increase maximum watermark lines to 255 drm/i915/xelpd: Required bandwidth increases when VT-d is active drm/i915/xelpd: Add Wa_14011503030 drm/i915/adl_p: Add dedicated SAGV watermarks drm/i915/adl_p: Extend PLANE_WM bits for blocks & lines Mika Kahola (3): drm/i915/adl_p: Tx escape clock with DSI drm/i915/adl_p: Define and use ADL-P specific DP translation tables drm/i915/adl_p: Enable/disable loadgen sharing Uma Shankar (1): drm/i915/xelpd: Handle LPSP for XE_LPD Umesh Nerlige Ramappa (1): drm/i915/perf: Enable OA formats for ADL_P Vandita Kulkarni (7): drm/i915/display/dsc: Refactor intel_dp_dsc_compute_bpp drm/i915/xelpd: Support DP1.4 compression BPPs drm/i915: Get slice height before computing rc params drm/i915/xelpd: Calculate VDSC RC parameters drm/i915/xelpd: Add rc_qp_table for rcparams calculation drm/i915/adl_p: Add ddb allocation support drm/i915/adl_p: MBUS programming Ville Syrjälä (2): drm/i915: Introduce MBUS relative dbuf offsets drm/i915: Move intel_modeset_all_pipes() arch/x86/kernel/early-quirks.c| 1 + drivers/gpu/drm/i915/display/icl_dsi.c| 21 +- drivers/gpu/drm/i915/display/intel_atomic.c | 20 + drivers/gpu/drm/i915/display/intel_atomic.h | 1 + drivers/gpu/drm/i915/display/intel_bios.c | 10 +- drivers/gpu/drm/i915/display/intel_bw.c | 5 +- drivers/gpu/drm/i915/display/intel_cdclk.c| 86 ++-- drivers/gpu/drm/i915/display/intel_csr.c | 10 +- drivers/gpu/drm/i915/display/intel_ddi.c | 40 +- .../drm/i915/display/intel_ddi_buf_trans.c| 34 ++ .../drm/i915/display/intel_ddi_buf_trans.h| 4 + drivers/gpu/drm/i915/display/intel_display.c | 127 - drivers/gpu/drm/i915/display/intel_display.h | 9 + .../drm/i915/display/intel_display_debugfs.c | 6 + .../drm/i915/display/intel_display_power.c| 455 +- .../drm/i915/display/intel_display_power.h| 11 + .../drm/i915/display/intel_display_types.h| 2 +- drivers/gpu/drm/i915/display/intel_dp.c | 75 ++- drivers/gpu/drm/i915/display/intel_dp_aux.c | 14 +- drivers/gpu/drm/i915/display/intel_dpll_mgr.c | 71 ++- .../drm/i915/display/intel_fifo_underrun.c| 65 ++- drivers/gpu/drm/i915/display/intel_hdmi.c | 2 +- drivers/gpu/drm/i915/display/intel_psr.c | 53 +- .../gpu/drm/i915/display/intel_qp_tables.c| 272 +++ .../gpu/drm/i915/display/intel_qp_tables.h| 34 ++ drivers/gpu/drm/i915/display/intel_tc.c | 159 +- drivers/gpu/drm/i915/display/intel_vdsc.c | 160 +- drivers/gpu/drm/i915/display/intel_vdsc.h | 2 + drivers/gpu/drm/i915/display/intel_vrr.c | 56 ++- .../drm/i915/display/skl_universal_plane.c| 77 ++- drivers/gpu/drm/i915/gt/gen8_engine_cs.c | 4 +- drivers/gpu/drm/i915/gt/intel_workaroun
[Intel-gfx] [PATCH v2 06/50] drm/i915/xelpd: Handle new location of outputs D and E
The DDI naming template for display version 12 went A-C, TC1-TC6. With
XE_LPD, that naming scheme for DDI's has now changed to A-E, TC1-TC4.
The XE_LPD design keeps the register offsets and bitfields relating to
the TC outputs in the same location they were previously. The new "D"
and "E" outputs now take the locations that were previously used by TC5
and TC6 outputs, or what we would have considered to be outputs "H" and
"I" under the legacy lettering scheme.
For the most part everything will just work as long as we initialize the
output with the proper 'enum port' value. However we do need to take
care to pick the correct AUX channel when parsing the VBT (e.g., a
reference to 'AUX D' is actually asking us to use the 8th aux channel,
not the fourth). We should also make sure that our encoders and aux
channels are named appropriately so that it's easier to correlate driver
debug messages with the bspec instructions.
v2:
- Update handling of TGL_TRANS_CLK_SEL_PORT. (Jose)
Cc: José Roberto de Souza
Cc: Ville Syrjälä
Signed-off-by: Matt Roper
---
drivers/gpu/drm/i915/display/intel_bios.c| 8 +--
drivers/gpu/drm/i915/display/intel_ddi.c | 25 +---
drivers/gpu/drm/i915/display/intel_display.c | 6 -
drivers/gpu/drm/i915/display/intel_display.h | 8 +++
drivers/gpu/drm/i915/display/intel_dp_aux.c | 14 +++
5 files changed, 44 insertions(+), 17 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_bios.c
b/drivers/gpu/drm/i915/display/intel_bios.c
index 3d0c035b5e38..6847fb5aff4d 100644
--- a/drivers/gpu/drm/i915/display/intel_bios.c
+++ b/drivers/gpu/drm/i915/display/intel_bios.c
@@ -2852,7 +2852,9 @@ enum aux_ch intel_bios_port_aux_ch(struct
drm_i915_private *i915,
aux_ch = AUX_CH_C;
break;
case DP_AUX_D:
- if (IS_ALDERLAKE_S(i915))
+ if (DISPLAY_VER(i915) >= 13)
+ aux_ch = AUX_CH_D_XELPD;
+ else if (IS_ALDERLAKE_S(i915))
aux_ch = AUX_CH_USBC3;
else if (IS_DG1(i915) || IS_ROCKETLAKE(i915))
aux_ch = AUX_CH_USBC2;
@@ -2860,7 +2862,9 @@ enum aux_ch intel_bios_port_aux_ch(struct
drm_i915_private *i915,
aux_ch = AUX_CH_D;
break;
case DP_AUX_E:
- if (IS_ALDERLAKE_S(i915))
+ if (DISPLAY_VER(i915) >= 13)
+ aux_ch = AUX_CH_E_XELPD;
+ else if (IS_ALDERLAKE_S(i915))
aux_ch = AUX_CH_USBC4;
else
aux_ch = AUX_CH_E;
diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c
b/drivers/gpu/drm/i915/display/intel_ddi.c
index 953de42e277c..933af861253e 100644
--- a/drivers/gpu/drm/i915/display/intel_ddi.c
+++ b/drivers/gpu/drm/i915/display/intel_ddi.c
@@ -850,18 +850,19 @@ void intel_ddi_enable_pipe_clock(struct intel_encoder
*encoder,
{
struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
- enum port port = encoder->port;
enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
+ enum phy phy = intel_port_to_phy(dev_priv, encoder->port);
+ u32 val;
if (cpu_transcoder != TRANSCODER_EDP) {
- if (DISPLAY_VER(dev_priv) >= 12)
- intel_de_write(dev_priv,
- TRANS_CLK_SEL(cpu_transcoder),
- TGL_TRANS_CLK_SEL_PORT(port));
+ if (DISPLAY_VER(dev_priv) >= 13)
+ val = TGL_TRANS_CLK_SEL_PORT(phy);
+ else if (DISPLAY_VER(dev_priv) >= 12)
+ val = TGL_TRANS_CLK_SEL_PORT(encoder->port);
else
- intel_de_write(dev_priv,
- TRANS_CLK_SEL(cpu_transcoder),
- TRANS_CLK_SEL_PORT(port));
+ val = TRANS_CLK_SEL_PORT(encoder->port);
+
+ intel_de_write(dev_priv, TRANS_CLK_SEL(cpu_transcoder), val);
}
}
@@ -4489,7 +4490,13 @@ void intel_ddi_init(struct drm_i915_private *dev_priv,
enum port port)
encoder = &dig_port->base;
encoder->devdata = devdata;
- if (DISPLAY_VER(dev_priv) >= 12) {
+ if (DISPLAY_VER(dev_priv) >= 13 && port >= PORT_D_XELPD) {
+ drm_encoder_init(&dev_priv->drm, &encoder->base,
&intel_ddi_funcs,
+DRM_MODE_ENCODER_TMDS,
+"DDI %c/PHY %c",
+port_name(port - PORT_D_XELPD + PORT_D),
+phy_name(phy));
+ } else if (DISPLAY_VER(dev_priv) >= 12) {
enum tc_port tc_port = intel_port_to_tc(dev_priv, port);
drm_encoder_init(&dev_priv->drm, &encoder->base,
&intel_ddi_func
[Intel-gfx] [PATCH v2 05/50] drm/i915/xelpd: Support 128k plane stride
From: Juha-Pekka Heikkilä
XE_LPD supports plane strides up to 128KB.
v2:
- Drop a duplicated comment
- Add missing horizontal pixels for cpp!=8 case (Lucas)
- Take into account larger possible offsets for warnings
Cc: Vandita Kulkarni
Signed-off-by: Juha-Pekka Heikkilä
Signed-off-by: Matt Roper
Reviewed-by: Lucas De Marchi
---
.../drm/i915/display/skl_universal_plane.c| 46 +++
drivers/gpu/drm/i915/i915_reg.h | 2 +
2 files changed, 39 insertions(+), 9 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/skl_universal_plane.c
b/drivers/gpu/drm/i915/display/skl_universal_plane.c
index 80d7d1dba6c0..4a1a4caf6453 100644
--- a/drivers/gpu/drm/i915/display/skl_universal_plane.c
+++ b/drivers/gpu/drm/i915/display/skl_universal_plane.c
@@ -456,17 +456,35 @@ skl_plane_max_stride(struct intel_plane *plane,
u32 pixel_format, u64 modifier,
unsigned int rotation)
{
+ struct drm_i915_private *i915 = to_i915(plane->base.dev);
const struct drm_format_info *info = drm_format_info(pixel_format);
int cpp = info->cpp[0];
+ int max_horizontal_pixels = 8192;
+ int max_stride_bytes;
+
+ if (DISPLAY_VER(i915) >= 13) {
+ /*
+* The stride in bytes must not exceed of the size
+* of 128K bytes. For pixel formats of 64bpp will allow
+* for a 16K pixel surface.
+*/
+ max_stride_bytes = 131072;
+ if (cpp == 8)
+ max_horizontal_pixels = 16384;
+ else
+ max_horizontal_pixels = 65536;
+ } else {
+ /*
+* "The stride in bytes must not exceed the
+* of the size of 8K pixels and 32K bytes."
+*/
+ max_stride_bytes = 32768;
+ }
- /*
-* "The stride in bytes must not exceed the
-* of the size of 8K pixels and 32K bytes."
-*/
if (drm_rotation_90_or_270(rotation))
- return min(8192, 32768 / cpp);
+ return min(max_horizontal_pixels, max_stride_bytes / cpp);
else
- return min(8192 * cpp, 32768);
+ return min(max_horizontal_pixels * cpp, max_stride_bytes);
}
@@ -1450,7 +1468,10 @@ static int skl_check_main_surface(struct
intel_plane_state *plane_state)
}
}
- drm_WARN_ON(&dev_priv->drm, x > 8191 || y > 8191);
+ if (DISPLAY_VER(dev_priv) >= 13)
+ drm_WARN_ON(&dev_priv->drm, x > 65535 || y > 65535);
+ else
+ drm_WARN_ON(&dev_priv->drm, x > 8191 || y > 8191);
plane_state->color_plane[0].offset = offset;
plane_state->color_plane[0].x = x;
@@ -1524,7 +1545,10 @@ static int skl_check_nv12_aux_surface(struct
intel_plane_state *plane_state)
}
}
- drm_WARN_ON(&i915->drm, x > 8191 || y > 8191);
+ if (DISPLAY_VER(i915) >= 13)
+ drm_WARN_ON(&i915->drm, x > 65535 || y > 65535);
+ else
+ drm_WARN_ON(&i915->drm, x > 8191 || y > 8191);
plane_state->color_plane[uv_plane].offset = offset;
plane_state->color_plane[uv_plane].x = x;
@@ -2248,7 +2272,11 @@ skl_get_initial_plane_config(struct intel_crtc *crtc,
val = intel_de_read(dev_priv, PLANE_STRIDE(pipe, plane_id));
stride_mult = skl_plane_stride_mult(fb, 0, DRM_MODE_ROTATE_0);
- fb->pitches[0] = (val & 0x3ff) * stride_mult;
+
+ if (DISPLAY_VER(dev_priv) >= 13)
+ fb->pitches[0] = (val & PLANE_STRIDE_MASK_XELPD) * stride_mult;
+ else
+ fb->pitches[0] = (val & PLANE_STRIDE_MASK) * stride_mult;
aligned_height = intel_fb_align_height(fb, 0, fb->height);
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 6c024a5f1117..460c44270011 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -7213,6 +7213,8 @@ enum {
_PIPE(pipe, _PLANE_STRIDE_3_A, _PLANE_STRIDE_3_B)
#define PLANE_STRIDE(pipe, plane) \
_MMIO_PLANE(plane, _PLANE_STRIDE_1(pipe), _PLANE_STRIDE_2(pipe))
+#define PLANE_STRIDE_MASK REG_GENMASK(10, 0)
+#define PLANE_STRIDE_MASK_XELPDREG_GENMASK(11, 0)
#define _PLANE_POS_1_B 0x7118c
#define _PLANE_POS_2_B 0x7128c
--
2.25.4
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[Intel-gfx] [PATCH v2 09/50] drm/i915/xelpd: Increase maximum watermark lines to 255
XE_LPD continues to use the same "skylake-style" watermark
programming as other recent platforms. The only change to the watermark
calculations compared to Display12 is that XE_LPD now allows a
maximum of 255 lines vs the old limit of 31.
Due to the larger possible lines value, the corresponding bits
representing the value in PLANE_WM are also extended, so make sure we
read/write enough bits. Let's also take this opportunity to switch over
to the REG_FIELD notation.
Bspec: 49325
Bspec: 50419
Cc: Ville Syrjälä
Cc: Anshuman Gupta
Signed-off-by: Matt Roper
---
drivers/gpu/drm/i915/i915_reg.h | 3 +--
drivers/gpu/drm/i915/intel_pm.c | 15 +++
2 files changed, 12 insertions(+), 6 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index b3731cc9afad..d16f228bbef2 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -6436,8 +6436,7 @@ enum {
#define _CUR_WM_TRANS_B_0 0x71168
#define PLANE_WM_EN (1 << 31)
#define PLANE_WM_IGNORE_LINES(1 << 30)
-#define PLANE_WM_LINES_SHIFT 14
-#define PLANE_WM_LINES_MASK 0x1f
+#define PLANE_WM_LINES_MASK REG_GENMASK(21, 14)
#define PLANE_WM_BLOCKS_MASK 0x7ff /* skl+: 10 bits, icl+ 11 bits */
#define _CUR_WM_0(pipe) _PIPE(pipe, _CUR_WM_A_0, _CUR_WM_B_0)
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 820f850d5cbb..18ee225016fa 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -5199,6 +5199,14 @@ static bool skl_wm_has_lines(struct drm_i915_private
*dev_priv, int level)
return level > 0;
}
+static int skl_wm_max_lines(struct drm_i915_private *dev_priv)
+{
+ if (DISPLAY_VER(dev_priv) >= 13)
+ return 255;
+ else
+ return 31;
+}
+
static void skl_compute_plane_wm(const struct intel_crtc_state *crtc_state,
int level,
unsigned int latency,
@@ -5303,7 +5311,7 @@ static void skl_compute_plane_wm(const struct
intel_crtc_state *crtc_state,
if (!skl_wm_has_lines(dev_priv, level))
lines = 0;
- if (lines > 31) {
+ if (lines > skl_wm_max_lines(dev_priv)) {
/* reject it */
result->min_ddb_alloc = U16_MAX;
return;
@@ -5599,7 +5607,7 @@ static void skl_write_wm_level(struct drm_i915_private
*dev_priv,
if (level->ignore_lines)
val |= PLANE_WM_IGNORE_LINES;
val |= level->blocks;
- val |= level->lines << PLANE_WM_LINES_SHIFT;
+ val |= REG_FIELD_PREP(PLANE_WM_LINES_MASK, level->lines);
intel_de_write_fw(dev_priv, reg, val);
}
@@ -6207,8 +6215,7 @@ static void skl_wm_level_from_reg_val(u32 val, struct
skl_wm_level *level)
level->enable = val & PLANE_WM_EN;
level->ignore_lines = val & PLANE_WM_IGNORE_LINES;
level->blocks = val & PLANE_WM_BLOCKS_MASK;
- level->lines = (val >> PLANE_WM_LINES_SHIFT) &
- PLANE_WM_LINES_MASK;
+ level->lines = REG_FIELD_GET(PLANE_WM_LINES_MASK, val);
}
void skl_pipe_wm_get_hw_state(struct intel_crtc *crtc,
--
2.25.4
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[Intel-gfx] [PATCH v2 07/50] drm/i915/xelpd: Add XE_LPD power wells
Aside from the hardware-managed PG0, XE_LPD has power wells 1-2 and
A-D. These power wells should be enabled/disabled according to the
following dependency tree (enable top to bottom, disable bottom to top):
PG0
|
--PG1--
/ \
PGA --PG2--
/ | \
PGB PGC PGD
PWR_WELL_CTL follows the general ICL/TGL design and places PG A-D in the
bits that would have been PG 6-9 under the old scheme.
PWR_WELL_CTL_{DDI,AUX}'s bit indexing for DDI's A-C and TC1 is the same
as TGL, but DDI-D is placed at index 7 (bits 14 & 15).
Bspec: 49233
Bspec: 49503
Bspec: 49504
Bspec: 49505
Bspec: 49296
Bspec: 50090
Bspec: 53920
Cc: Anshuman Gupta
Cc: Imre Deak
Cc: Anshuman Gupta
Cc: José Roberto de Souza
Signed-off-by: Matt Roper
Reviewed-by: Lucas De Marchi
---
.../drm/i915/display/intel_display_power.c| 426 +-
.../drm/i915/display/intel_display_power.h| 9 +
drivers/gpu/drm/i915/display/intel_vdsc.c | 4 +-
drivers/gpu/drm/i915/i915_reg.h | 10 +
4 files changed, 445 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c
b/drivers/gpu/drm/i915/display/intel_display_power.c
index cef177208e68..e3495d3305b3 100644
--- a/drivers/gpu/drm/i915/display/intel_display_power.c
+++ b/drivers/gpu/drm/i915/display/intel_display_power.c
@@ -1035,7 +1035,7 @@ static void assert_can_enable_dc5(struct drm_i915_private
*dev_priv)
enum i915_power_well_id high_pg;
/* Power wells at this level and above must be disabled for DC5 entry */
- if (DISPLAY_VER(dev_priv) >= 12)
+ if (DISPLAY_VER(dev_priv) == 12)
high_pg = ICL_DISP_PW_3;
else
high_pg = SKL_DISP_PW_2;
@@ -3012,6 +3012,113 @@ intel_display_power_put_mask_in_set(struct
drm_i915_private *i915,
BIT_ULL(POWER_DOMAIN_AUX_B) | \
BIT_ULL(POWER_DOMAIN_INIT))
+/*
+ * XE_LPD Power Domains
+ *
+ * Previous platforms required that PG(n-1) be enabled before PG(n). That
+ * dependency chain turns into a dependency tree on XE_LPD:
+ *
+ * PG0
+ *|
+ * --PG1--
+ */ \
+ * PGA --PG2--
+ * / | \
+ * PGB PGC PGD
+ *
+ * Power wells must be enabled from top to bottom and disabled from bottom
+ * to top. This allows pipes to be power gated independently.
+ */
+
+#define XELPD_PW_D_POWER_DOMAINS ( \
+ BIT_ULL(POWER_DOMAIN_PIPE_D) | \
+ BIT_ULL(POWER_DOMAIN_PIPE_D_PANEL_FITTER) | \
+ BIT_ULL(POWER_DOMAIN_TRANSCODER_D) |\
+ BIT_ULL(POWER_DOMAIN_INIT))
+
+#define XELPD_PW_C_POWER_DOMAINS ( \
+ BIT_ULL(POWER_DOMAIN_PIPE_C) | \
+ BIT_ULL(POWER_DOMAIN_PIPE_C_PANEL_FITTER) | \
+ BIT_ULL(POWER_DOMAIN_TRANSCODER_C) |\
+ BIT_ULL(POWER_DOMAIN_INIT))
+
+#define XELPD_PW_B_POWER_DOMAINS ( \
+ BIT_ULL(POWER_DOMAIN_PIPE_B) | \
+ BIT_ULL(POWER_DOMAIN_PIPE_B_PANEL_FITTER) | \
+ BIT_ULL(POWER_DOMAIN_TRANSCODER_B) |\
+ BIT_ULL(POWER_DOMAIN_INIT))
+
+#define XELPD_PW_A_POWER_DOMAINS ( \
+ BIT_ULL(POWER_DOMAIN_PIPE_A) | \
+ BIT_ULL(POWER_DOMAIN_PIPE_A_PANEL_FITTER) | \
+ BIT_ULL(POWER_DOMAIN_INIT))
+
+#define XELPD_PW_2_POWER_DOMAINS ( \
+ XELPD_PW_B_POWER_DOMAINS | \
+ XELPD_PW_C_POWER_DOMAINS | \
+ XELPD_PW_D_POWER_DOMAINS | \
+ BIT_ULL(POWER_DOMAIN_AUDIO) | \
+ BIT_ULL(POWER_DOMAIN_VGA) | \
+ BIT_ULL(POWER_DOMAIN_PORT_DDI_C_LANES) |\
+ BIT_ULL(POWER_DOMAIN_PORT_DDI_LANES_D_XELPD) | \
+ BIT_ULL(POWER_DOMAIN_PORT_DDI_LANES_E_XELPD) | \
+ BIT_ULL(POWER_DOMAIN_AUX_C) | \
+ BIT_ULL(POWER_DOMAIN_PORT_DDI_LANES_TC1) | \
+ BIT_ULL(POWER_DOMAIN_PORT_DDI_LANES_TC2) | \
+ BIT_ULL(POWER_DOMAIN_PORT_DDI_LANES_TC3) | \
+ BIT_ULL(POWER_DOMAIN_PORT_DDI_LANES_TC4) | \
+ BIT_ULL(POWER_DOMAIN_AUX_C) | \
+ BIT_ULL(POWER_DOMAIN_AUX_D_XELPD) | \
+ BIT_ULL(POWER_DOMAIN_AUX_E_XELPD) | \
+ BIT_ULL(POWER_DOMAIN_AUX_USBC1) | \
+ BIT_ULL(POWER_DOMAIN_AUX_USBC2) | \
+ BIT_ULL(POWER_DOMAIN_AUX_USBC3) | \
+ BIT_ULL(POWER_DOMAIN_AUX_USBC4) | \
+ BIT_ULL(POWER_DOMAIN_INIT))
+
+/*
+ * XELPD PW_1/PG_1 domains (under HW/DMC control):
+ * - DBUF function (registers are in PW0)
+ * - Transcoder A
+ * - DDI_A and DDI_B
+ *
+ * XELPD PW_0/PW_1 domains (under HW/DMC control):
+ * - PCI
+ * - Clocks excep
[Intel-gfx] [PATCH v2 04/50] drm/i915/xelpd: Define plane capabilities
XE_LPD's plane support is identical to RKL and ADL-S --- 5 universal + 1
cursor with NV12 UV support on planes 1-3 and NV12 Y support on planes
4-5.
v2:
- Drop the extra 90/270 rotation check in skl_plane_check_fb(); the DRM
property code will already prevent userspace from passing us values
that weren't advertised. (Lucas)
Bspec: 53657
Bspec: 49251
Cc: Lucas De Marchi
Signed-off-by: Matt Roper
Reviewed-by: Lucas De Marchi
---
drivers/gpu/drm/i915/display/skl_universal_plane.c | 11 +++
drivers/gpu/drm/i915/i915_irq.c| 2 +-
drivers/gpu/drm/i915/intel_device_info.c | 2 +-
3 files changed, 9 insertions(+), 6 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/skl_universal_plane.c
b/drivers/gpu/drm/i915/display/skl_universal_plane.c
index c6d7b6c054b5..80d7d1dba6c0 100644
--- a/drivers/gpu/drm/i915/display/skl_universal_plane.c
+++ b/drivers/gpu/drm/i915/display/skl_universal_plane.c
@@ -266,7 +266,7 @@ int skl_format_to_fourcc(int format, bool rgb_order, bool
alpha)
static u8 icl_nv12_y_plane_mask(struct drm_i915_private *i915)
{
- if (HAS_D12_PLANE_MINIMIZATION(i915))
+ if (DISPLAY_VER(i915) >= 13 || HAS_D12_PLANE_MINIMIZATION(i915))
return BIT(PLANE_SPRITE2) | BIT(PLANE_SPRITE3);
else
return BIT(PLANE_SPRITE4) | BIT(PLANE_SPRITE5);
@@ -2072,9 +2072,12 @@ skl_universal_plane_create(struct drm_i915_private
*dev_priv,
if (ret)
goto fail;
- supported_rotations =
- DRM_MODE_ROTATE_0 | DRM_MODE_ROTATE_90 |
- DRM_MODE_ROTATE_180 | DRM_MODE_ROTATE_270;
+ if (DISPLAY_VER(dev_priv) >= 13)
+ supported_rotations = DRM_MODE_ROTATE_0 | DRM_MODE_ROTATE_180;
+ else
+ supported_rotations =
+ DRM_MODE_ROTATE_0 | DRM_MODE_ROTATE_90 |
+ DRM_MODE_ROTATE_180 | DRM_MODE_ROTATE_270;
if (DISPLAY_VER(dev_priv) >= 11 || IS_CANNONLAKE(dev_priv))
supported_rotations |= DRM_MODE_REFLECT_X;
diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index 0fe836ffcad3..b583c0bec9d3 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -2308,7 +2308,7 @@ static u32 gen8_de_port_aux_mask(struct drm_i915_private
*dev_priv)
static u32 gen8_de_pipe_fault_mask(struct drm_i915_private *dev_priv)
{
- if (HAS_D12_PLANE_MINIMIZATION(dev_priv))
+ if (DISPLAY_VER(dev_priv) >= 13 || HAS_D12_PLANE_MINIMIZATION(dev_priv))
return RKL_DE_PIPE_IRQ_FAULT_ERRORS;
else if (DISPLAY_VER(dev_priv) >= 11)
return GEN11_DE_PIPE_IRQ_FAULT_ERRORS;
diff --git a/drivers/gpu/drm/i915/intel_device_info.c
b/drivers/gpu/drm/i915/intel_device_info.c
index aeb28d589b2b..8a55cdfc802c 100644
--- a/drivers/gpu/drm/i915/intel_device_info.c
+++ b/drivers/gpu/drm/i915/intel_device_info.c
@@ -265,7 +265,7 @@ void intel_device_info_runtime_init(struct drm_i915_private
*dev_priv)
BUILD_BUG_ON(BITS_PER_TYPE(intel_engine_mask_t) < I915_NUM_ENGINES);
- if (HAS_D12_PLANE_MINIMIZATION(dev_priv))
+ if (DISPLAY_VER(dev_priv) >= 13 || HAS_D12_PLANE_MINIMIZATION(dev_priv))
for_each_pipe(dev_priv, pipe)
runtime->num_sprites[pipe] = 4;
else if (INTEL_GEN(dev_priv) >= 11)
--
2.25.4
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[Intel-gfx] [PATCH v2 15/50] drm/i915/xelpd: Calculate VDSC RC parameters
From: Vandita Kulkarni
Add methods to calculate rc parameters for all bpps, against the fixed
arrays that we already have for 8,10,12 valid o/p bpps, to cover RGB 444
formats. Our hw doesn't support YUV compression yet. The calculations
used here are from VESA C model for DSC 1.1
v2:
- Checkpatch fixes
Cc: Manasi Navare
Cc: Juha-Pekka Heikkil
Signed-off-by: Vandita Kulkarni
Signed-off-by: Mohammed Khajapasha
Signed-off-by: Matt Roper
---
drivers/gpu/drm/i915/display/intel_vdsc.c | 96 ---
1 file changed, 86 insertions(+), 10 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_vdsc.c
b/drivers/gpu/drm/i915/display/intel_vdsc.c
index 38f89e777f2b..933918256d24 100644
--- a/drivers/gpu/drm/i915/display/intel_vdsc.c
+++ b/drivers/gpu/drm/i915/display/intel_vdsc.c
@@ -5,7 +5,7 @@
* Author: Gaurav K Singh
* Manasi Navare
*/
-
+#include
#include "i915_drv.h"
#include "intel_display_types.h"
#include "intel_dsi.h"
@@ -372,12 +372,73 @@ static bool is_pipe_dsc(const struct intel_crtc_state
*crtc_state)
return true;
}
+static void
+calculate_rc_params(struct rc_parameters *rc,
+ struct drm_dsc_config *vdsc_cfg)
+{
+ int bpc = vdsc_cfg->bits_per_component;
+ int bpp = vdsc_cfg->bits_per_pixel >> 4;
+ int ofs_und6[] = { 0, -2, -2, -4, -6, -6, -8, -8, -8, -10, -10, -12,
-12, -12, -12 };
+ int ofs_und8[] = { 2, 0, 0, -2, -4, -6, -8, -8, -8, -10, -10, -10, -12,
-12, -12 };
+ int ofs_und12[] = { 2, 0, 0, -2, -4, -6, -8, -8, -8, -10, -10, -10,
-12, -12, -12 };
+ int ofs_und15[] = { 10, 8, 6, 4, 2, 0, -2, -4, -6, -8, -10, -10, -12,
-12, -12 };
+ int qp_bpc_modifier = (bpc - 8) * 2;
+ u32 res, buf_i;
+
+ if (vdsc_cfg->slice_height >= 8)
+ rc->first_line_bpg_offset = 12 + DIV_ROUND_UP((9 * min(34,
vdsc_cfg->slice_height - 8)), 100);
+ else
+ rc->first_line_bpg_offset = 2 * (vdsc_cfg->slice_height - 1);
+
+ /* Our hw supports only 444 modes as of today */
+ if (bpp >= 12)
+ rc->initial_offset = 2048;
+ else if (bpp >= 10)
+ rc->initial_offset = 5632 - DIV_ROUND_UP(((bpp - 10) * 3584),
2);
+ else if (bpp >= 8)
+ rc->initial_offset = 6144 - DIV_ROUND_UP(((bpp - 8) * 512), 2);
+ else
+ rc->initial_offset = 6144;
+
+ /* initial_xmit_delay = rc_model_size/2/compression_bpp */
+ rc->initial_xmit_delay = DIV_ROUND_UP(DSC_RC_MODEL_SIZE_CONST, 2 * bpp);
+
+ rc->flatness_min_qp = 3 + qp_bpc_modifier;
+ rc->flatness_max_qp = 12 + qp_bpc_modifier;
+
+ rc->rc_quant_incr_limit0 = 11 + qp_bpc_modifier;
+ rc->rc_quant_incr_limit1 = 11 + qp_bpc_modifier;
+
+ for (buf_i = 0; buf_i < DSC_NUM_BUF_RANGES; buf_i++) {
+ /* Calculate range_bgp_offset */
+ if (bpp <= 6) {
+ rc->rc_range_params[buf_i].range_bpg_offset =
ofs_und6[buf_i];
+ } else if (bpp <= 8) {
+ res = DIV_ROUND_UP(((bpp - 6) * (ofs_und8[buf_i] -
ofs_und6[buf_i])), 2);
+ rc->rc_range_params[buf_i].range_bpg_offset =
+ ofs_und6[buf_i]
+ res;
+ } else if (bpp <= 12) {
+ rc->rc_range_params[buf_i].range_bpg_offset =
+ ofs_und8[buf_i];
+ } else if (bpp <= 15) {
+ res = DIV_ROUND_UP(((bpp - 12) * (ofs_und15[buf_i] -
ofs_und12[buf_i])), 3);
+ rc->rc_range_params[buf_i].range_bpg_offset =
+
ofs_und12[buf_i] + res;
+ } else {
+ rc->rc_range_params[buf_i].range_bpg_offset =
+
ofs_und15[buf_i];
+ }
+ }
+}
+
int intel_dsc_compute_params(struct intel_encoder *encoder,
struct intel_crtc_state *pipe_config)
{
+ struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
struct drm_dsc_config *vdsc_cfg = &pipe_config->dsc.config;
u16 compressed_bpp = pipe_config->dsc.compressed_bpp;
const struct rc_parameters *rc_params;
+ struct rc_parameters *rc = NULL;
u8 i = 0;
vdsc_cfg->pic_width = pipe_config->hw.adjusted_mode.crtc_hdisplay;
@@ -412,9 +473,24 @@ int intel_dsc_compute_params(struct intel_encoder *encoder,
vdsc_cfg->rc_buf_thresh[13] = 0x7D;
}
- rc_params = get_rc_params(compressed_bpp, vdsc_cfg->bits_per_component);
- if (!rc_params)
- return -EINVAL;
+ /*
+* From XE_LPD onwards we supports compression bpps in steps of 1
+* upto uncompressed bpp-1, hence add calculations for all the rc
+* parameters
+*/
+
[Intel-gfx] [PATCH v2 02/50] drm/i915/xelpd: Handle proper AUX interrupt bits
XE_LPD has new AUX interrupt bits for DDI-D and DDI-E that take the
spots that were used by TC5/TC6 on Display12 platforms.
While we're at it, let's convert the bit definitions for all TGL+ aux
bits over to the modern REG_BIT() notation.
v2:
- Maintain bit order rather than logical order. (Lucas)
- Convert surrounding code to REG_BIT() notation. (Lucas)
Bspec: 50064
Cc: Anusha Srivatsa
Cc: Lucas De Marchi
Signed-off-by: Matt Roper
Reviewed-by: Anusha Srivatsa
---
drivers/gpu/drm/i915/i915_irq.c | 12 +++-
drivers/gpu/drm/i915/i915_reg.h | 20 +++-
2 files changed, 22 insertions(+), 10 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index 7eefbdec25a2..031ca1660ef3 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -2269,7 +2269,17 @@ static u32 gen8_de_port_aux_mask(struct drm_i915_private
*dev_priv)
{
u32 mask;
- if (DISPLAY_VER(dev_priv) >= 12)
+ if (DISPLAY_VER(dev_priv) >= 13)
+ return TGL_DE_PORT_AUX_DDIA |
+ TGL_DE_PORT_AUX_DDIB |
+ TGL_DE_PORT_AUX_DDIC |
+ XELPD_DE_PORT_AUX_DDID |
+ XELPD_DE_PORT_AUX_DDIE |
+ TGL_DE_PORT_AUX_USBC1 |
+ TGL_DE_PORT_AUX_USBC2 |
+ TGL_DE_PORT_AUX_USBC3 |
+ TGL_DE_PORT_AUX_USBC4;
+ else if (DISPLAY_VER(dev_priv) >= 12)
return TGL_DE_PORT_AUX_DDIA |
TGL_DE_PORT_AUX_DDIB |
TGL_DE_PORT_AUX_DDIC |
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index cbf7a60afe54..20d60dd11ea3 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -7866,15 +7866,17 @@ enum {
#define BDW_DE_PORT_HOTPLUG_MASK GEN8_DE_PORT_HOTPLUG(HPD_PORT_A)
#define BXT_DE_PORT_GMBUS (1 << 1)
#define GEN8_AUX_CHANNEL_A(1 << 0)
-#define TGL_DE_PORT_AUX_USBC6 (1 << 13)
-#define TGL_DE_PORT_AUX_USBC5 (1 << 12)
-#define TGL_DE_PORT_AUX_USBC4 (1 << 11)
-#define TGL_DE_PORT_AUX_USBC3 (1 << 10)
-#define TGL_DE_PORT_AUX_USBC2 (1 << 9)
-#define TGL_DE_PORT_AUX_USBC1 (1 << 8)
-#define TGL_DE_PORT_AUX_DDIC (1 << 2)
-#define TGL_DE_PORT_AUX_DDIB (1 << 1)
-#define TGL_DE_PORT_AUX_DDIA (1 << 0)
+#define TGL_DE_PORT_AUX_USBC6 REG_BIT(13)
+#define XELPD_DE_PORT_AUX_DDIEREG_BIT(13)
+#define TGL_DE_PORT_AUX_USBC5 REG_BIT(12)
+#define XELPD_DE_PORT_AUX_DDIDREG_BIT(12)
+#define TGL_DE_PORT_AUX_USBC4 REG_BIT(11)
+#define TGL_DE_PORT_AUX_USBC3 REG_BIT(10)
+#define TGL_DE_PORT_AUX_USBC2 REG_BIT(9)
+#define TGL_DE_PORT_AUX_USBC1 REG_BIT(8)
+#define TGL_DE_PORT_AUX_DDIC REG_BIT(2)
+#define TGL_DE_PORT_AUX_DDIB REG_BIT(1)
+#define TGL_DE_PORT_AUX_DDIA REG_BIT(0)
#define GEN8_DE_MISC_ISR _MMIO(0x44460)
#define GEN8_DE_MISC_IMR _MMIO(0x44464)
--
2.25.4
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[Intel-gfx] [PATCH v2 14/50] drm/i915: Get slice height before computing rc params
From: Vandita Kulkarni We need slice height to calculate few RC parameters hence assign slice height first. Cc: Manasi Navare Signed-off-by: Vandita Kulkarni Signed-off-by: Matt Roper --- drivers/gpu/drm/i915/display/intel_dp.c | 8 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c index af2c47e50884..57a1868475ae 100644 --- a/drivers/gpu/drm/i915/display/intel_dp.c +++ b/drivers/gpu/drm/i915/display/intel_dp.c @@ -1190,10 +1190,6 @@ static int intel_dp_dsc_compute_params(struct intel_encoder *encoder, */ vdsc_cfg->rc_model_size = DSC_RC_MODEL_SIZE_CONST; - ret = intel_dsc_compute_params(encoder, crtc_state); - if (ret) - return ret; - /* * Slice Height of 8 works for all currently available panels. So start * with that if pic_height is an integral multiple of 8. Eventually add @@ -1206,6 +1202,10 @@ static int intel_dp_dsc_compute_params(struct intel_encoder *encoder, else vdsc_cfg->slice_height = 2; + ret = intel_dsc_compute_params(encoder, crtc_state); + if (ret) + return ret; + vdsc_cfg->dsc_version_major = (intel_dp->dsc_dpcd[DP_DSC_REV - DP_DSC_SUPPORT] & DP_DSC_MAJOR_MASK) >> DP_DSC_MAJOR_SHIFT; -- 2.25.4 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH v2 19/50] drm/i915/adl_p: ADL_P device info enabling
From: Clinton Taylor
Add ADL-P to the device_info table and support MACROS.
Bspec: 49185, 55372, 55373
Cc: Matt Atwood
Cc: Matt Roper
Signed-off-by: Clinton Taylor
Signed-off-by: Matt Roper
---
arch/x86/kernel/early-quirks.c | 1 +
drivers/gpu/drm/i915/i915_drv.h | 1 +
drivers/gpu/drm/i915/i915_pci.c | 12
drivers/gpu/drm/i915/intel_device_info.c | 1 +
drivers/gpu/drm/i915/intel_device_info.h | 1 +
5 files changed, 16 insertions(+)
diff --git a/arch/x86/kernel/early-quirks.c b/arch/x86/kernel/early-quirks.c
index 6edd1e2ee8af..b553ffe9b985 100644
--- a/arch/x86/kernel/early-quirks.c
+++ b/arch/x86/kernel/early-quirks.c
@@ -552,6 +552,7 @@ static const struct pci_device_id intel_early_ids[]
__initconst = {
INTEL_TGL_12_IDS(&gen11_early_ops),
INTEL_RKL_IDS(&gen11_early_ops),
INTEL_ADLS_IDS(&gen11_early_ops),
+ INTEL_ADLP_IDS(&gen11_early_ops),
};
struct resource intel_graphics_stolen_res __ro_after_init = DEFINE_RES_MEM(0,
0);
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index c78d7d37a754..ab1db490bbcf 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -1375,6 +1375,7 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915,
#define IS_ROCKETLAKE(dev_priv)IS_PLATFORM(dev_priv, INTEL_ROCKETLAKE)
#define IS_DG1(dev_priv)IS_PLATFORM(dev_priv, INTEL_DG1)
#define IS_ALDERLAKE_S(dev_priv) IS_PLATFORM(dev_priv, INTEL_ALDERLAKE_S)
+#define IS_ALDERLAKE_P(dev_priv) IS_PLATFORM(dev_priv, INTEL_ALDERLAKE_P)
#define IS_HSW_EARLY_SDV(dev_priv) (IS_HASWELL(dev_priv) && \
(INTEL_DEVID(dev_priv) & 0xFF00) == 0x0C00)
#define IS_BDW_ULT(dev_priv) \
diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
index 295a39bc7a2f..1ceb3cd4068d 100644
--- a/drivers/gpu/drm/i915/i915_pci.c
+++ b/drivers/gpu/drm/i915/i915_pci.c
@@ -946,6 +946,17 @@ static const struct intel_device_info adl_s_info = {
.ddb_size = 4096, \
.num_supported_dbuf_slices = 4
+static const struct intel_device_info adl_p_info = {
+ GEN12_FEATURES,
+ XE_LPD_FEATURES,
+ PLATFORM(INTEL_ALDERLAKE_P),
+ .require_force_probe = 1,
+ .platform_engine_mask =
+ BIT(RCS0) | BIT(BCS0) | BIT(VECS0) | BIT(VCS0) | BIT(VCS2),
+ .ppgtt_size = 48,
+ .dma_mask_size = 46,
+};
+
#undef GEN
#undef PLATFORM
@@ -1023,6 +1034,7 @@ static const struct pci_device_id pciidlist[] = {
INTEL_TGL_12_IDS(&tgl_info),
INTEL_RKL_IDS(&rkl_info),
INTEL_ADLS_IDS(&adl_s_info),
+ INTEL_ADLP_IDS(&adl_p_info),
{0, 0, 0}
};
MODULE_DEVICE_TABLE(pci, pciidlist);
diff --git a/drivers/gpu/drm/i915/intel_device_info.c
b/drivers/gpu/drm/i915/intel_device_info.c
index 8a55cdfc802c..16d8be7f734f 100644
--- a/drivers/gpu/drm/i915/intel_device_info.c
+++ b/drivers/gpu/drm/i915/intel_device_info.c
@@ -67,6 +67,7 @@ static const char * const platform_names[] = {
PLATFORM_NAME(ROCKETLAKE),
PLATFORM_NAME(DG1),
PLATFORM_NAME(ALDERLAKE_S),
+ PLATFORM_NAME(ALDERLAKE_P),
};
#undef PLATFORM_NAME
diff --git a/drivers/gpu/drm/i915/intel_device_info.h
b/drivers/gpu/drm/i915/intel_device_info.h
index 90acbaf800d5..bd948457e0e4 100644
--- a/drivers/gpu/drm/i915/intel_device_info.h
+++ b/drivers/gpu/drm/i915/intel_device_info.h
@@ -85,6 +85,7 @@ enum intel_platform {
INTEL_ROCKETLAKE,
INTEL_DG1,
INTEL_ALDERLAKE_S,
+ INTEL_ALDERLAKE_P,
INTEL_MAX_PLATFORMS
};
--
2.25.4
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[Intel-gfx] [PATCH v2 10/50] drm/i915/xelpd: Required bandwidth increases when VT-d is active
If VT-d is active, the memory bandwidth usage of the display is 5% higher. Take this into account when determining whether we can support a display configuration. Bspec: 64631 Cc: Matt Atwood Signed-off-by: Matt Roper Reviewed-by: Anusha Srivatsa --- drivers/gpu/drm/i915/display/intel_bw.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/drivers/gpu/drm/i915/display/intel_bw.c b/drivers/gpu/drm/i915/display/intel_bw.c index 584ab5ce4106..72e2721f949b 100644 --- a/drivers/gpu/drm/i915/display/intel_bw.c +++ b/drivers/gpu/drm/i915/display/intel_bw.c @@ -344,6 +344,9 @@ static unsigned int intel_bw_data_rate(struct drm_i915_private *dev_priv, for_each_pipe(dev_priv, pipe) data_rate += bw_state->data_rate[pipe]; + if (DISPLAY_VER(dev_priv) >= 13 && intel_vtd_active()) + data_rate = data_rate * 105 / 100; + return data_rate; } -- 2.25.4 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH v2 16/50] drm/i915/xelpd: Add rc_qp_table for rcparams calculation
From: Vandita Kulkarni
Add the qp table for 444 formats, for 8bpc, 10bpc and 12bpc, as given by
the VESA C model for DSC 1.1
v2:
- Add include guard to header (Jani)
- Move the big tables to a .c file (Chris, Jani, Lucas)
Cc: Manasi Navare
Signed-off-by: Vandita Kulkarni
Signed-off-by: Matt Roper
---
.../gpu/drm/i915/display/intel_qp_tables.c| 272 ++
.../gpu/drm/i915/display/intel_qp_tables.h| 34 +++
drivers/gpu/drm/i915/display/intel_vdsc.c | 22 +-
3 files changed, 327 insertions(+), 1 deletion(-)
create mode 100644 drivers/gpu/drm/i915/display/intel_qp_tables.c
create mode 100644 drivers/gpu/drm/i915/display/intel_qp_tables.h
diff --git a/drivers/gpu/drm/i915/display/intel_qp_tables.c
b/drivers/gpu/drm/i915/display/intel_qp_tables.c
new file mode 100644
index ..cc1d3493bc9d
--- /dev/null
+++ b/drivers/gpu/drm/i915/display/intel_qp_tables.c
@@ -0,0 +1,272 @@
+// SPDX-License-Identifier: MIT
+/*
+ * Copyright © 2021 Intel Corporation
+ */
+
+#include "intel_qp_tables.h"
+
+/*
+ * These qp tables are as per the C model
+ * and it has the rows pointing to bpps which increment
+ * in steps of 0.5
+ * We do not support fractional bpps as of today,
+ * hence we would skip the fractional bpps during
+ * our references for qp calclulations.
+ */
+const u8
rc_range_minqp444_8bpc[DSC_NUM_BUF_RANGES][RC_RANGE_QP444_8BPC_MAX_NUM_BPP] = {
+ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+ { 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+ { 3, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+ { 3, 3, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+ { 5, 4, 4, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 2, 1, 1, 1, 1, 1, 1, 1, 1,
+ 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+ { 5, 4, 4, 4, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 2, 1, 1, 1, 1, 1, 1, 1,
+ 1, 1, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0 },
+ { 5, 5, 4, 4, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 2, 2, 2, 1, 1, 1, 1, 1,
+ 1, 1, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0 },
+ { 5, 5, 4, 4, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 2, 2, 2, 2, 2, 2, 2, 2,
+ 2, 2, 2, 1, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0 },
+ { 5, 5, 4, 4, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 2, 2, 2, 2, 2, 2, 2, 2,
+ 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 0, 0, 0 },
+ { 6, 5, 5, 4, 4, 4, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3,
+ 3, 3, 3, 2, 2, 1, 1, 1, 1, 1, 1, 0, 0, 0 },
+ { 6, 6, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 4, 4, 4, 4, 4, 4, 4, 4, 4, 3,
+ 3, 3, 3, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 0 },
+ { 6, 6, 6, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 4, 4, 4, 4, 4, 4,
+ 4, 4, 4, 3, 3, 2, 2, 2, 2, 1, 1, 1, 1, 0 },
+ { 6, 6, 6, 6, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 4,
+ 4, 4, 4, 3, 3, 2, 2, 2, 2, 1, 1, 1, 1, 0 },
+ { 9, 9, 9, 9, 8, 8, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 6, 6, 5,
+ 5, 5, 5, 4, 4, 3, 3, 3, 3, 2, 2, 1, 1, 1 },
+ { 14, 14, 13, 13, 12, 12, 12, 12, 11, 11, 10, 10, 10, 10, 9, 9, 9, 8, 8,
+ 8, 7, 7, 7, 7, 6, 6, 5, 5, 5, 5, 4, 4, 4, 3, 3, 3, 3 }
+};
+
+const u8
rc_range_maxqp444_8bpc[DSC_NUM_BUF_RANGES][RC_RANGE_QP444_8BPC_MAX_NUM_BPP] = {
+ { 4, 4, 4, 4, 4, 4, 3, 3, 3, 3, 2, 2, 2, 2, 1, 1, 1, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+ { 6, 6, 5, 5, 4, 4, 4, 4, 4, 4, 4, 4, 3, 3, 3, 2, 2, 1, 1, 1, 1, 1, 1,
+ 1, 1, 1, 1, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0 },
+ { 8, 7, 7, 6, 5, 5, 5, 5, 5, 5, 5, 5, 4, 4, 4, 3, 2, 2, 1, 1, 1, 1, 1,
+ 1, 1, 1, 1, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0 },
+ { 8, 8, 7, 7, 6, 6, 6, 6, 6, 6, 6, 6, 5, 5, 5, 4, 3, 3, 2, 2, 2, 2, 2,
+ 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 0 },
+ { 9, 8, 8, 7, 7, 7, 7, 7, 7, 7, 7, 7, 6, 6, 5, 4, 4, 3, 2, 2, 2, 2, 2,
+ 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 0 },
+ { 9, 8, 8, 8, 7, 7, 7, 7, 7, 7, 7, 7, 6, 6, 6, 5, 4, 4, 3, 3, 3, 3, 3,
+ 3, 3, 3, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1 },
+ { 9, 9, 8, 8, 7, 7, 7, 7, 7, 7, 7, 7, 7, 6, 6, 5, 4, 4, 3, 3, 3, 3, 3,
+ 3, 3, 3, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1 },
+ { 10, 10, 9, 9, 8, 8, 8, 8, 8, 8, 8, 8, 8, 7, 7, 6, 5, 5, 4, 4, 4, 4, 3,
+ 3, 3, 3, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1 },
+ { 11, 11, 10, 10, 9, 9, 9, 9, 9, 9, 8, 8, 8, 7, 7, 6, 6, 5, 5, 5, 5, 5,
+ 4, 4, 4, 4, 3, 3, 2, 2, 2, 2, 2, 2, 1, 1, 1 },
+ { 12, 11, 11, 10, 10, 10, 9, 9, 9, 9, 9, 9, 9, 8, 8, 7, 6, 6, 5, 5, 5,
+ 5, 4, 4, 4, 4, 3, 3, 2, 2, 2, 2, 2, 2, 1, 1, 1 },
+ { 12, 12, 11, 11, 10, 10, 10, 10, 10, 10, 9, 9, 9, 8, 8, 7, 7, 6, 6, 6,
+ 5, 5, 4, 4, 4, 4, 3, 3, 2, 2, 2, 2, 2, 2, 2, 2, 1 },
[Intel-gfx] [PATCH v2 11/50] drm/i915/xelpd: Add Wa_14011503030
Cc: Aditya Swarup
Signed-off-by: Matt Roper
---
drivers/gpu/drm/i915/display/intel_display_power.c | 4
drivers/gpu/drm/i915/i915_reg.h| 2 ++
2 files changed, 6 insertions(+)
diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c
b/drivers/gpu/drm/i915/display/intel_display_power.c
index e3495d3305b3..930488fba3cd 100644
--- a/drivers/gpu/drm/i915/display/intel_display_power.c
+++ b/drivers/gpu/drm/i915/display/intel_display_power.c
@@ -5840,6 +5840,10 @@ static void icl_display_core_init(struct
drm_i915_private *dev_priv,
DCPR_MASK_LPMODE | DCPR_MASK_MAXLATENCY_MEMUP_CLR;
intel_uncore_rmw(&dev_priv->uncore, GEN11_CHICKEN_DCPR_2, 0,
val);
}
+
+ /* Wa_14011503030:xelpd */
+ if (DISPLAY_VER(dev_priv) >= 13)
+ intel_de_write(dev_priv, XELPD_DISPLAY_ERR_FATAL_MASK, ~0);
}
static void icl_display_core_uninit(struct drm_i915_private *dev_priv)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index d16f228bbef2..22beacb28920 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -7791,6 +7791,8 @@ enum {
#define GEN8_GT_BCS_IRQ (1 << 1)
#define GEN8_GT_RCS_IRQ (1 << 0)
+#define XELPD_DISPLAY_ERR_FATAL_MASK _MMIO(0x4421c)
+
#define GEN8_GT_ISR(which) _MMIO(0x44300 + (0x10 * (which)))
#define GEN8_GT_IMR(which) _MMIO(0x44304 + (0x10 * (which)))
#define GEN8_GT_IIR(which) _MMIO(0x44308 + (0x10 * (which)))
--
2.25.4
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[Intel-gfx] [PATCH v2 18/50] drm/i915/adl_p: Add PCI Devices IDs
From: Clinton Taylor Add 18 known PCI device IDs Bspec: 55376 Cc: Caz Yokoyama Cc: Matt Atwood Cc: Matt Roper Signed-off-by: Clinton Taylor Signed-off-by: Matt Roper Reviewed-by: Anusha Srivatsa --- include/drm/i915_pciids.h | 21 + 1 file changed, 21 insertions(+) diff --git a/include/drm/i915_pciids.h b/include/drm/i915_pciids.h index ebd0dd1c35b3..2448be8c72f8 100644 --- a/include/drm/i915_pciids.h +++ b/include/drm/i915_pciids.h @@ -645,4 +645,25 @@ INTEL_VGA_DEVICE(0x4692, info), \ INTEL_VGA_DEVICE(0x4693, info) +/* ADL-P */ +#define INTEL_ADLP_IDS(info) \ + INTEL_VGA_DEVICE(0x46A0, info), \ + INTEL_VGA_DEVICE(0x46A1, info), \ + INTEL_VGA_DEVICE(0x46A2, info), \ + INTEL_VGA_DEVICE(0x46A3, info), \ + INTEL_VGA_DEVICE(0x46A6, info), \ + INTEL_VGA_DEVICE(0x46A8, info), \ + INTEL_VGA_DEVICE(0x46AA, info), \ + INTEL_VGA_DEVICE(0x462A, info), \ + INTEL_VGA_DEVICE(0x4626, info), \ + INTEL_VGA_DEVICE(0x4628, info), \ + INTEL_VGA_DEVICE(0x46B0, info), \ + INTEL_VGA_DEVICE(0x46B1, info), \ + INTEL_VGA_DEVICE(0x46B2, info), \ + INTEL_VGA_DEVICE(0x46B3, info), \ + INTEL_VGA_DEVICE(0x46C0, info), \ + INTEL_VGA_DEVICE(0x46C1, info), \ + INTEL_VGA_DEVICE(0x46C2, info), \ + INTEL_VGA_DEVICE(0x46C3, info) + #endif /* _I915_PCIIDS_H */ -- 2.25.4 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH v2 20/50] drm/i915/adl_p: Add PCH support
From: Clinton Taylor
Add ADP-P PCH device ID and assign as ADL PCH if found. Previously we
would assign the DDC pin map based on the PCH, but it can also change
based on the CPU. From Bspec 20124: "The physical port to pin pair
mapping are defined in the Bspec per PCH. Mapping can further change
based on CPU Si used as CPU and PCH can be mixed and matched".
Bspec: 20124
Cc: Matt Atwood
Cc: Matt Roper
Signed-off-by: Clinton Taylor
Signed-off-by: Matt Roper
Reviewed-by: Anusha Srivatsa
---
drivers/gpu/drm/i915/display/intel_bios.c | 2 +-
drivers/gpu/drm/i915/display/intel_hdmi.c | 2 +-
drivers/gpu/drm/i915/intel_pch.c | 6 --
drivers/gpu/drm/i915/intel_pch.h | 1 +
4 files changed, 7 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_bios.c
b/drivers/gpu/drm/i915/display/intel_bios.c
index 6847fb5aff4d..3fbcd57118d0 100644
--- a/drivers/gpu/drm/i915/display/intel_bios.c
+++ b/drivers/gpu/drm/i915/display/intel_bios.c
@@ -1651,7 +1651,7 @@ static u8 map_ddc_pin(struct drm_i915_private *i915, u8
vbt_pin)
const u8 *ddc_pin_map;
int n_entries;
- if (HAS_PCH_ADP(i915)) {
+ if (IS_ALDERLAKE_S(i915)) {
ddc_pin_map = adls_ddc_pin_map;
n_entries = ARRAY_SIZE(adls_ddc_pin_map);
} else if (INTEL_PCH_TYPE(i915) >= PCH_DG1) {
diff --git a/drivers/gpu/drm/i915/display/intel_hdmi.c
b/drivers/gpu/drm/i915/display/intel_hdmi.c
index d69f0a6dc26d..1c5bf35442e8 100644
--- a/drivers/gpu/drm/i915/display/intel_hdmi.c
+++ b/drivers/gpu/drm/i915/display/intel_hdmi.c
@@ -2708,7 +2708,7 @@ static u8 intel_hdmi_ddc_pin(struct intel_encoder
*encoder)
return ddc_pin;
}
- if (HAS_PCH_ADP(dev_priv))
+ if (IS_ALDERLAKE_S(dev_priv))
ddc_pin = adls_port_to_ddc_pin(dev_priv, port);
else if (INTEL_PCH_TYPE(dev_priv) >= PCH_DG1)
ddc_pin = dg1_port_to_ddc_pin(dev_priv, port);
diff --git a/drivers/gpu/drm/i915/intel_pch.c b/drivers/gpu/drm/i915/intel_pch.c
index 7476f0e063c6..98a17dd1bda4 100644
--- a/drivers/gpu/drm/i915/intel_pch.c
+++ b/drivers/gpu/drm/i915/intel_pch.c
@@ -130,8 +130,10 @@ intel_pch_type(const struct drm_i915_private *dev_priv,
unsigned short id)
drm_WARN_ON(&dev_priv->drm, !IS_JSL_EHL(dev_priv));
return PCH_JSP;
case INTEL_PCH_ADP_DEVICE_ID_TYPE:
+ case INTEL_PCH_ADP2_DEVICE_ID_TYPE:
drm_dbg_kms(&dev_priv->drm, "Found Alder Lake PCH\n");
- drm_WARN_ON(&dev_priv->drm, !IS_ALDERLAKE_S(dev_priv));
+ drm_WARN_ON(&dev_priv->drm, !IS_ALDERLAKE_S(dev_priv) &&
+ !IS_ALDERLAKE_P(dev_priv));
return PCH_ADP;
default:
return PCH_NONE;
@@ -161,7 +163,7 @@ intel_virt_detect_pch(const struct drm_i915_private
*dev_priv,
* make an educated guess as to which PCH is really there.
*/
- if (IS_ALDERLAKE_S(dev_priv))
+ if (IS_ALDERLAKE_S(dev_priv) || IS_ALDERLAKE_P(dev_priv))
id = INTEL_PCH_ADP_DEVICE_ID_TYPE;
else if (IS_TIGERLAKE(dev_priv) || IS_ROCKETLAKE(dev_priv))
id = INTEL_PCH_TGP_DEVICE_ID_TYPE;
diff --git a/drivers/gpu/drm/i915/intel_pch.h b/drivers/gpu/drm/i915/intel_pch.h
index 7318377503b0..e2f3f30c6445 100644
--- a/drivers/gpu/drm/i915/intel_pch.h
+++ b/drivers/gpu/drm/i915/intel_pch.h
@@ -55,6 +55,7 @@ enum intel_pch {
#define INTEL_PCH_JSP_DEVICE_ID_TYPE 0x4D80
#define INTEL_PCH_JSP2_DEVICE_ID_TYPE 0x3880
#define INTEL_PCH_ADP_DEVICE_ID_TYPE 0x7A80
+#define INTEL_PCH_ADP2_DEVICE_ID_TYPE 0x5180
#define INTEL_PCH_P2X_DEVICE_ID_TYPE 0x7100
#define INTEL_PCH_P3X_DEVICE_ID_TYPE 0x7000
#define INTEL_PCH_QEMU_DEVICE_ID_TYPE 0x2900 /* qemu q35 has 2918 */
--
2.25.4
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[Intel-gfx] [PATCH v2 12/50] drm/i915/display/dsc: Refactor intel_dp_dsc_compute_bpp
From: Vandita Kulkarni
Move the platform specific max bpc calculation into
intel_dp_dsc_compute_bpp function
Cc: Manasi Navare
Signed-off-by: Vandita Kulkarni
Signed-off-by: Matt Roper
---
drivers/gpu/drm/i915/display/intel_dp.c | 20 ++--
1 file changed, 10 insertions(+), 10 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c
b/drivers/gpu/drm/i915/display/intel_dp.c
index d81b8d238163..d7648a0a7d9d 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -1133,10 +1133,18 @@ intel_dp_compute_link_config_fast(struct intel_dp
*intel_dp,
return -EINVAL;
}
-static int intel_dp_dsc_compute_bpp(struct intel_dp *intel_dp, u8 dsc_max_bpc)
+static int intel_dp_dsc_compute_bpp(struct intel_dp *intel_dp, u8 max_req_bpc)
{
+ struct drm_i915_private *i915 = dp_to_i915(intel_dp);
int i, num_bpc;
u8 dsc_bpc[3] = {0};
+ u8 dsc_max_bpc;
+
+ /* Max DSC Input BPC for ICL is 10 and for TGL+ is 12 */
+ if (DISPLAY_VER(i915) >= 12)
+ dsc_max_bpc = min_t(u8, 12, max_req_bpc);
+ else
+ dsc_max_bpc = min_t(u8, 10, max_req_bpc);
num_bpc = drm_dp_dsc_sink_supported_input_bpcs(intel_dp->dsc_dpcd,
dsc_bpc);
@@ -1224,7 +1232,6 @@ static int intel_dp_dsc_compute_config(struct intel_dp
*intel_dp,
struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev);
const struct drm_display_mode *adjusted_mode =
&pipe_config->hw.adjusted_mode;
- u8 dsc_max_bpc;
int pipe_bpp;
int ret;
@@ -1234,14 +1241,7 @@ static int intel_dp_dsc_compute_config(struct intel_dp
*intel_dp,
if (!intel_dp_supports_dsc(intel_dp, pipe_config))
return -EINVAL;
- /* Max DSC Input BPC for ICL is 10 and for TGL+ is 12 */
- if (DISPLAY_VER(dev_priv) >= 12)
- dsc_max_bpc = min_t(u8, 12, conn_state->max_requested_bpc);
- else
- dsc_max_bpc = min_t(u8, 10,
- conn_state->max_requested_bpc);
-
- pipe_bpp = intel_dp_dsc_compute_bpp(intel_dp, dsc_max_bpc);
+ pipe_bpp = intel_dp_dsc_compute_bpp(intel_dp,
conn_state->max_requested_bpc);
/* Min Input BPC for ICL+ is 8 */
if (pipe_bpp < 8 * 3) {
--
2.25.4
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[Intel-gfx] [PATCH v2 08/50] drm/i915/xelpd: Handle LPSP for XE_LPD
From: Uma Shankar
Enable LPSP for XE_LPD and get the proper power well
enable check in place. For XE_LPD it is PW2 which
need to check for LPSP.
v2:
- Move the XE_LPD check outside of the switch. (Lucas)
Cc: Anshuman Gupta
Cc: Animesh Manna
Cc: Matt Roper
Cc: Lucas De Marchi
Suggested-by: Matt Roper
Signed-off-by: Uma Shankar
Signed-off-by: Anshuman Gupta
Signed-off-by: Matt Roper
---
drivers/gpu/drm/i915/display/intel_display_debugfs.c | 6 ++
1 file changed, 6 insertions(+)
diff --git a/drivers/gpu/drm/i915/display/intel_display_debugfs.c
b/drivers/gpu/drm/i915/display/intel_display_debugfs.c
index 564509a4e666..d5956c329745 100644
--- a/drivers/gpu/drm/i915/display/intel_display_debugfs.c
+++ b/drivers/gpu/drm/i915/display/intel_display_debugfs.c
@@ -1339,6 +1339,12 @@ static int i915_lpsp_status(struct seq_file *m, void
*unused)
{
struct drm_i915_private *i915 = node_to_i915(m->private);
+ if (DISPLAY_VER(i915) >= 13) {
+ LPSP_STATUS(!intel_lpsp_power_well_enabled(i915,
+ SKL_DISP_PW_2));
+ return 0;
+ }
+
switch (DISPLAY_VER(i915)) {
case 12:
case 11:
--
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[Intel-gfx] [PATCH v2 17/50] drm/i915/xelpd: Add VRR guardband for VRR CTL
From: Manasi Navare
On XE_LPD, VRR CTL register adds a new VRR Guardband bitfield
replacing the pipeline full and deprecating the pipeline override
bit.
This patch adds this corresponding bitfield in the register defs,
crtc state vrr structure and populates this in vrr compute
config and vrr enable functions. It also adds the corresponding
HW state readout for this field.
Cc: Aditya Swarup
Cc: Ville Syrjala
Signed-off-by: Manasi Navare
---
drivers/gpu/drm/i915/display/intel_display.c | 8 ++-
.../drm/i915/display/intel_display_types.h| 2 +-
drivers/gpu/drm/i915/display/intel_vrr.c | 56 +--
drivers/gpu/drm/i915/i915_drv.h | 3 +
drivers/gpu/drm/i915/i915_reg.h | 2 +
5 files changed, 51 insertions(+), 20 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display.c
b/drivers/gpu/drm/i915/display/intel_display.c
index 03d1e0eedaa8..d1b067586c0b 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -8159,10 +8159,11 @@ static void intel_dump_pipe_config(const struct
intel_crtc_state *pipe_config,
intel_hdmi_infoframe_enable(DP_SDP_VSC))
intel_dump_dp_vsc_sdp(dev_priv, &pipe_config->infoframes.vsc);
- drm_dbg_kms(&dev_priv->drm, "vrr: %s, vmin: %d, vmax: %d, pipeline
full: %d, flipline: %d, vmin vblank: %d, vmax vblank: %d\n",
+ drm_dbg_kms(&dev_priv->drm, "vrr: %s, vmin: %d, vmax: %d, pipeline
full: %d, guardband: %d flipline: %d, vmin vblank: %d, vmax vblank: %d\n",
yesno(pipe_config->vrr.enable),
pipe_config->vrr.vmin, pipe_config->vrr.vmax,
- pipe_config->vrr.pipeline_full, pipe_config->vrr.flipline,
+ pipe_config->vrr.pipeline_full, pipe_config->vrr.guardband,
+ pipe_config->vrr.flipline,
intel_vrr_vmin_vblank_start(pipe_config),
intel_vrr_vmax_vblank_start(pipe_config));
@@ -9168,6 +9169,7 @@ intel_pipe_config_compare(const struct intel_crtc_state
*current_config,
PIPE_CONF_CHECK_I(vrr.vmax);
PIPE_CONF_CHECK_I(vrr.flipline);
PIPE_CONF_CHECK_I(vrr.pipeline_full);
+ PIPE_CONF_CHECK_I(vrr.guardband);
#undef PIPE_CONF_CHECK_X
#undef PIPE_CONF_CHECK_I
@@ -12628,6 +12630,8 @@ int intel_modeset_init_noirq(struct drm_i915_private
*i915)
i915->framestart_delay = 1; /* 1-4 */
+ i915->window2_delay = 0; /* No DSB so no window2 delay */
+
intel_mode_config_init(i915);
ret = intel_cdclk_init(i915);
diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h
b/drivers/gpu/drm/i915/display/intel_display_types.h
index 946e030313a8..7afd7b85a4be 100644
--- a/drivers/gpu/drm/i915/display/intel_display_types.h
+++ b/drivers/gpu/drm/i915/display/intel_display_types.h
@@ -1178,7 +1178,7 @@ struct intel_crtc_state {
struct {
bool enable;
u8 pipeline_full;
- u16 flipline, vmin, vmax;
+ u16 flipline, vmin, vmax, guardband;
} vrr;
/* Stream Splitter for eDP MSO */
diff --git a/drivers/gpu/drm/i915/display/intel_vrr.c
b/drivers/gpu/drm/i915/display/intel_vrr.c
index a9c2b2fd9252..7013163f4978 100644
--- a/drivers/gpu/drm/i915/display/intel_vrr.c
+++ b/drivers/gpu/drm/i915/display/intel_vrr.c
@@ -67,7 +67,10 @@ static int intel_vrr_vblank_exit_length(const struct
intel_crtc_state *crtc_stat
struct drm_i915_private *i915 = to_i915(crtc->base.dev);
/* The hw imposes the extra scanline before frame start */
- return crtc_state->vrr.pipeline_full + i915->framestart_delay + 1;
+ if (DISPLAY_VER(i915) >= 13)
+ return crtc_state->vrr.guardband + i915->framestart_delay + 1;
+ else
+ return crtc_state->vrr.pipeline_full + i915->framestart_delay +
1;
}
int intel_vrr_vmin_vblank_start(const struct intel_crtc_state *crtc_state)
@@ -85,6 +88,8 @@ void
intel_vrr_compute_config(struct intel_crtc_state *crtc_state,
struct drm_connector_state *conn_state)
{
+ struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
+ struct drm_i915_private *i915 = to_i915(crtc->base.dev);
struct intel_connector *connector =
to_intel_connector(conn_state->connector);
struct drm_display_mode *adjusted_mode = &crtc_state->hw.adjusted_mode;
@@ -123,17 +128,26 @@ intel_vrr_compute_config(struct intel_crtc_state
*crtc_state,
crtc_state->vrr.flipline = crtc_state->vrr.vmin + 1;
/*
-* FIXME: s/4/framestart_delay+1/ to get consistent
-* earliest/latest points for register latching regardless
-* of the framestart_delay used?
-*
-* FIXME: this really needs the extra scanline to provide consistent
-* behaviour for all framestart_delay values. Otherwise with
-* framestart_delay==3 we
[Intel-gfx] [PATCH v2 21/50] drm/i915/adl_p: Add dedicated SAGV watermarks
XE_LPD reduces the number of regular watermark latency levels from 8
to 6 on non-dgfx platforms. However the hardware also adds a special
purpose SAGV wateramrk (and an accompanying transition watermark) that
will be used by the hardware in place of the level 0 values during SAGV
transitions.
Bspec: 49325, 49326, 50419
Cc: Matt Atwood
Signed-off-by: Matt Roper
Signed-off-by: Clinton Taylor
---
drivers/gpu/drm/i915/display/intel_display.c | 32 +++
drivers/gpu/drm/i915/i915_drv.h | 2 +
drivers/gpu/drm/i915/i915_reg.h | 59 ++--
drivers/gpu/drm/i915/intel_pm.c | 56 +--
4 files changed, 128 insertions(+), 21 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display.c
b/drivers/gpu/drm/i915/display/intel_display.c
index d1b067586c0b..d04924d405e5 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -9275,6 +9275,38 @@ static void verify_wm_state(struct intel_crtc *crtc,
hw_wm_level->lines);
}
+ hw_wm_level = &hw->wm.planes[plane->id].sagv.wm0;
+ sw_wm_level = &sw_wm->planes[plane->id].sagv.wm0;
+
+ if (HAS_HW_SAGV_WM(dev_priv) &&
+ !skl_wm_level_equals(hw_wm_level, sw_wm_level)) {
+ drm_err(&dev_priv->drm,
+ "[PLANE:%d:%s] mismatch in SAGV WM (expected
e=%d b=%u l=%u, got e=%d b=%u l=%u)\n",
+ plane->base.base.id, plane->base.name,
+ sw_wm_level->enable,
+ sw_wm_level->blocks,
+ sw_wm_level->lines,
+ hw_wm_level->enable,
+ hw_wm_level->blocks,
+ hw_wm_level->lines);
+ }
+
+ hw_wm_level = &hw->wm.planes[plane->id].sagv.trans_wm;
+ sw_wm_level = &sw_wm->planes[plane->id].sagv.trans_wm;
+
+ if (HAS_HW_SAGV_WM(dev_priv) &&
+ !skl_wm_level_equals(hw_wm_level, sw_wm_level)) {
+ drm_err(&dev_priv->drm,
+ "[PLANE:%d:%s] mismatch in SAGV trans WM
(expected e=%d b=%u l=%u, got e=%d b=%u l=%u)\n",
+ plane->base.base.id, plane->base.name,
+ sw_wm_level->enable,
+ sw_wm_level->blocks,
+ sw_wm_level->lines,
+ hw_wm_level->enable,
+ hw_wm_level->blocks,
+ hw_wm_level->lines);
+ }
+
/* DDB */
hw_ddb_entry = &hw->ddb_y[plane->id];
sw_ddb_entry = &new_crtc_state->wm.skl.plane_ddb_y[plane->id];
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index ab1db490bbcf..68e216f5e0bb 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -581,6 +581,8 @@ i915_fence_timeout(const struct drm_i915_private *i915)
/* Amount of SAGV/QGV points, BSpec precisely defines this */
#define I915_NUM_QGV_POINTS 8
+#define HAS_HW_SAGV_WM(i915) ((DISPLAY_VER(i915) == 13) && !IS_DGFX(i915))
+
struct ddi_vbt_port_info {
/* Non-NULL if port present. */
struct intel_bios_encoder_data *devdata;
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 73ffdbc4e382..e39c2bbaa490 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -6426,16 +6426,28 @@ enum {
/* Watermark register definitions for SKL */
#define _CUR_WM_A_00x70140
#define _CUR_WM_B_00x71140
+#define _CUR_WM_SAGV_A 0x70158
+#define _CUR_WM_SAGV_B 0x71158
+#define _CUR_WM_SAGV_TRANS_A 0x7015C
+#define _CUR_WM_SAGV_TRANS_B 0x7115C
+#define _CUR_WM_TRANS_A0x70168
+#define _CUR_WM_TRANS_B0x71168
#define _PLANE_WM_1_A_00x70240
#define _PLANE_WM_1_B_00x71240
#define _PLANE_WM_2_A_00x70340
#define _PLANE_WM_2_B_00x71340
-#define _PLANE_WM_TRANS_1_A_0 0x70268
-#define _PLANE_WM_TRANS_1_B_0 0x71268
-#define _PLANE_WM_TRANS_2_A_0 0x70368
-#define _PLANE_WM_TRANS_2_B_0 0x71368
-#define _CUR_WM_TRANS_A_0 0x70168
-#define _CUR_WM_TRANS_B_0 0x71168
+#define _PLANE_WM_SAGV_1_A 0x70258
+#define _PLANE_WM_SAGV_1_B 0x71258
+#define _PLANE_WM_SAGV_2_A 0x70358
+#define _PLANE_WM_SAGV_2_B 0x71358
+#define _PLANE_WM_SAGV_TRANS_1_A 0x7025C
+#define _PLANE_WM_SAGV_TRANS_1_B 0x7125C
+#define _PLANE_WM_SAGV_TRANS_2_A 0x7035C
+#define _PLANE_WM_SAGV_TRANS_2_B 0x7135C
+#define _PLANE_WM_TRANS_1_A0x70268
+#define _PLANE_WM_TRANS_1_B0x71268
+#define _PLANE_WM_TRANS_2
[Intel-gfx] [PATCH v2 22/50] drm/i915/adl_p: Extend PLANE_WM bits for blocks & lines
ADL-P further extends the bits in PLANE_WM that represent blocks and
lines; we need to extend our masks accordingly. Since these bits are
reserved and MBZ on earlier platforms, it's safe to use the larger
bitmask on all platforms.
Bspec: 50419
Cc: Matt Atwood
Signed-off-by: Matt Roper
Signed-off-by: Clinton Taylor
Reviewed-by: Anusha Srivatsa
---
drivers/gpu/drm/i915/i915_reg.h | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index e39c2bbaa490..8a04dcaf056d 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -6450,8 +6450,8 @@ enum {
#define _PLANE_WM_TRANS_2_B0x71368
#define PLANE_WM_EN (1 << 31)
#define PLANE_WM_IGNORE_LINES(1 << 30)
-#define PLANE_WM_LINES_MASK REG_GENMASK(21, 14)
-#define PLANE_WM_BLOCKS_MASK 0x7ff /* skl+: 10 bits, icl+ 11 bits */
+#define PLANE_WM_LINES_MASK REG_GENMASK(26, 14)
+#define PLANE_WM_BLOCKS_MASK REG_GENMASK(11, 0)
#define _CUR_WM_0(pipe) _PIPE(pipe, _CUR_WM_A_0, _CUR_WM_B_0)
#define CUR_WM(pipe, level) _MMIO(_CUR_WM_0(pipe) + ((4) * (level)))
--
2.25.4
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[Intel-gfx] [PATCH v2 23/50] drm/i915/adl_p: Load DMC
From: Anusha Srivatsa
Load DMC v2.08 on ADLP. The release notes mention that
this version enables few power savings features.
Cc: Lucas De Marchi
Cc: Clint Taylor
Signed-off-by: Anusha Srivatsa
Signed-off-by: Clinton Taylor
Signed-off-by: Matt Roper
---
drivers/gpu/drm/i915/display/intel_csr.c | 10 +-
.../gpu/drm/i915/display/intel_display_power.c | 16 +++-
2 files changed, 24 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_csr.c
b/drivers/gpu/drm/i915/display/intel_csr.c
index 794efcc3ca08..015fb545f6f8 100644
--- a/drivers/gpu/drm/i915/display/intel_csr.c
+++ b/drivers/gpu/drm/i915/display/intel_csr.c
@@ -40,6 +40,10 @@
#define GEN12_CSR_MAX_FW_SIZE ICL_CSR_MAX_FW_SIZE
+#define ADLP_CSR_PATH "i915/adlp_dmc_ver2_08.bin"
+#define ADLP_CSR_VERSION_REQUIRED CSR_VERSION(2, 8)
+MODULE_FIRMWARE(ADLP_CSR_PATH);
+
#define ADLS_CSR_PATH "i915/adls_dmc_ver2_01.bin"
#define ADLS_CSR_VERSION_REQUIRED CSR_VERSION(2, 1)
MODULE_FIRMWARE(ADLS_CSR_PATH);
@@ -693,7 +697,11 @@ void intel_csr_ucode_init(struct drm_i915_private
*dev_priv)
*/
intel_csr_runtime_pm_get(dev_priv);
- if (IS_ALDERLAKE_S(dev_priv)) {
+ if (IS_ALDERLAKE_P(dev_priv)) {
+ csr->fw_path = ADLP_CSR_PATH;
+ csr->required_version = ADLP_CSR_VERSION_REQUIRED;
+ csr->max_fw_size = GEN12_CSR_MAX_FW_SIZE;
+ } else if (IS_ALDERLAKE_S(dev_priv)) {
csr->fw_path = ADLS_CSR_PATH;
csr->required_version = ADLS_CSR_VERSION_REQUIRED;
csr->max_fw_size = GEN12_CSR_MAX_FW_SIZE;
diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c
b/drivers/gpu/drm/i915/display/intel_display_power.c
index 930488fba3cd..20cfb86c0174 100644
--- a/drivers/gpu/drm/i915/display/intel_display_power.c
+++ b/drivers/gpu/drm/i915/display/intel_display_power.c
@@ -4953,7 +4953,21 @@ static u32 get_allowed_dc_mask(const struct
drm_i915_private *dev_priv,
int requested_dc;
int max_dc;
- if (IS_DG1(dev_priv))
+ if (!HAS_DISPLAY(dev_priv))
+ return 0;
+
+ if (DISPLAY_VER(dev_priv) == 13)
+ /*
+* FIXME: We need to disable DC-states for two reasons:
+*
+* - Although not documented in the bspec, we've been told
+*that we need to upload Pipe DMC firmwares in addition
+*to the main DMC firmware for DC5 to work properly.
+*We need proper bspec documentation before we can handle
+*this.
+*/
+ max_dc = 0;
+ else if (IS_DG1(dev_priv))
max_dc = 3;
else if (DISPLAY_VER(dev_priv) >= 12)
max_dc = 4;
--
2.25.4
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[Intel-gfx] [PATCH v2 13/50] drm/i915/xelpd: Support DP1.4 compression BPPs
From: Vandita Kulkarni
Support compression BPPs from bpc to uncompressed BPP -1.
So far we have 8,10,12 as valid compressed BPPS now the
support is extended.
Cc: Manasi Navare
Signed-off-by: Vandita Kulkarni
Signed-off-by: Matt Roper
---
drivers/gpu/drm/i915/display/intel_dp.c | 32 ++---
1 file changed, 24 insertions(+), 8 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c
b/drivers/gpu/drm/i915/display/intel_dp.c
index d7648a0a7d9d..af2c47e50884 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -107,6 +107,7 @@ bool intel_dp_is_edp(struct intel_dp *intel_dp)
}
static void intel_dp_unset_edid(struct intel_dp *intel_dp);
+static int intel_dp_dsc_compute_bpp(struct intel_dp *intel_dp, u8 dsc_max_bpc);
/* update sink rates from dpcd */
static void intel_dp_set_sink_rates(struct intel_dp *intel_dp)
@@ -492,7 +493,8 @@ small_joiner_ram_size_bits(struct drm_i915_private *i915)
static u16 intel_dp_dsc_get_output_bpp(struct drm_i915_private *i915,
u32 link_clock, u32 lane_count,
u32 mode_clock, u32 mode_hdisplay,
- bool bigjoiner)
+ bool bigjoiner,
+ u32 pipe_bpp)
{
u32 bits_per_pixel, max_bpp_small_joiner_ram;
int i;
@@ -517,6 +519,7 @@ static u16 intel_dp_dsc_get_output_bpp(struct
drm_i915_private *i915,
drm_dbg_kms(&i915->drm, "Max small joiner bpp: %u\n",
max_bpp_small_joiner_ram);
+
/*
* Greatest allowed DSC BPP = MIN (output BPP from available Link BW
* check, output bpp from small joiner RAM check)
@@ -539,12 +542,17 @@ static u16 intel_dp_dsc_get_output_bpp(struct
drm_i915_private *i915,
return 0;
}
- /* Find the nearest match in the array of known BPPs from VESA */
- for (i = 0; i < ARRAY_SIZE(valid_dsc_bpp) - 1; i++) {
- if (bits_per_pixel < valid_dsc_bpp[i + 1])
- break;
+ /* From XE_LPD onwards we support from bpc upto uncompressed bpp-1 BPPs
*/
+ if (DISPLAY_VER(i915) >= 13) {
+ bits_per_pixel = min(bits_per_pixel, pipe_bpp - 1);
+ } else {
+ /* Find the nearest match in the array of known BPPs from VESA
*/
+ for (i = 0; i < ARRAY_SIZE(valid_dsc_bpp) - 1; i++) {
+ if (bits_per_pixel < valid_dsc_bpp[i + 1])
+ break;
+ }
+ bits_per_pixel = valid_dsc_bpp[i];
}
- bits_per_pixel = valid_dsc_bpp[i];
/*
* Compressed BPP in U6.4 format so multiply by 16, for Gen 11,
@@ -778,6 +786,12 @@ intel_dp_mode_valid(struct drm_connector *connector,
*/
if (DISPLAY_VER(dev_priv) >= 10 &&
drm_dp_sink_supports_dsc(intel_dp->dsc_dpcd)) {
+ /*
+* TBD pass the connector BPC,
+* for now U8_MAX so that max BPC on that platform would be
picked
+*/
+ int pipe_bpp = intel_dp_dsc_compute_bpp(intel_dp, U8_MAX);
+
if (intel_dp_is_edp(intel_dp)) {
dsc_max_output_bpp =
drm_edp_dsc_sink_output_bpp(intel_dp->dsc_dpcd)
>> 4;
@@ -791,7 +805,8 @@ intel_dp_mode_valid(struct drm_connector *connector,
max_lanes,
target_clock,
mode->hdisplay,
- bigjoiner) >> 4;
+ bigjoiner,
+ pipe_bpp) >> 4;
dsc_slice_count =
intel_dp_dsc_get_slice_count(intel_dp,
target_clock,
@@ -1276,7 +1291,8 @@ static int intel_dp_dsc_compute_config(struct intel_dp
*intel_dp,
pipe_config->lane_count,
adjusted_mode->crtc_clock,
adjusted_mode->crtc_hdisplay,
- pipe_config->bigjoiner);
+ pipe_config->bigjoiner,
+ pipe_bpp);
dsc_dp_slice_count =
intel_dp_dsc_get_slice_count(intel_dp,
adjusted_mode->crtc_clock,
--
2.25.4
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[Intel-gfx] [PATCH v2 31/50] drm/i915/adl_p: Add ddb allocation support
From: Vandita Kulkarni
On adlp the two mbuses have two display pipes and
two DBUFS, Pipe A and D on Mbus1 and Pipe B and C on
Mbus2. The Mbus can be joined and all the DBUFS can be
used on Pipe A or B.
Bspec: 49255
Cc: Anusha Srivatsa
Signed-off-by: Vandita Kulkarni
Signed-off-by: Clinton Taylor
Signed-off-by: Matt Roper
---
.../drm/i915/display/intel_display_power.h| 2 +
drivers/gpu/drm/i915/i915_reg.h | 22 +++-
drivers/gpu/drm/i915/intel_pm.c | 121 +-
3 files changed, 140 insertions(+), 5 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display_power.h
b/drivers/gpu/drm/i915/display/intel_display_power.h
index f20d22b09a65..4f0917df4375 100644
--- a/drivers/gpu/drm/i915/display/intel_display_power.h
+++ b/drivers/gpu/drm/i915/display/intel_display_power.h
@@ -389,6 +389,8 @@ intel_display_power_put_all_in_set(struct drm_i915_private
*i915,
enum dbuf_slice {
DBUF_S1,
DBUF_S2,
+ DBUF_S3,
+ DBUF_S4,
I915_MAX_DBUF_SLICES
};
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 5b378e5091fa..da8ee0a3b652 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -7299,7 +7299,7 @@ enum {
#define _PLANE_BUF_CFG_1_B 0x7127c
#define _PLANE_BUF_CFG_2_B 0x7137c
-#define DDB_ENTRY_MASK0x7FF /* skl+: 10 bits,
icl+ 11 bits */
+#define DDB_ENTRY_MASK0xFFF /* skl+: 10 bits,
icl+ 11 bits, adlp+ 12 bits */
#define DDB_ENTRY_END_SHIFT 16
#define _PLANE_BUF_CFG_1(pipe) \
_PIPE(pipe, _PLANE_BUF_CFG_1_A, _PLANE_BUF_CFG_1_B)
@@ -8136,9 +8136,23 @@ enum {
#define DISP_DATA_PARTITION_5_6 (1 << 6)
#define DISP_IPC_ENABLE (1 << 3)
-#define _DBUF_CTL_S1 0x45008
-#define _DBUF_CTL_S2 0x44FE8
-#define DBUF_CTL_S(slice) _MMIO(_PICK_EVEN(slice,
_DBUF_CTL_S1, _DBUF_CTL_S2))
+/*
+ * The below are numbered starting from "S1" on gen11/gen12, but starting
+ * with gen13 display, the bspec switches to a 0-based numbering scheme
+ * (although the addresses stay the same so new S0 = old S1, new S1 = old S2).
+ * We'll just use the 0-based numbering here for all platforms since it's the
+ * way things will be named by the hardware team going forward, plus it's more
+ * consistent with how most of the rest of our registers are named.
+ */
+#define _DBUF_CTL_S0 0x45008
+#define _DBUF_CTL_S1 0x44FE8
+#define _DBUF_CTL_S2 0x44300
+#define _DBUF_CTL_S3 0x44304
+#define DBUF_CTL_S(slice) _MMIO(_PICK(slice, \
+ _DBUF_CTL_S0, \
+ _DBUF_CTL_S1, \
+ _DBUF_CTL_S2, \
+ _DBUF_CTL_S3))
#define DBUF_POWER_REQUESTREG_BIT(31)
#define DBUF_POWER_STATE REG_BIT(30)
#define DBUF_TRACKER_STATE_SERVICE_MASK REG_GENMASK(23, 19)
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index acc6c2b9e6e9..f0ba23c0f419 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -4573,6 +4573,118 @@ static const struct dbuf_slice_conf_entry
tgl_allowed_dbufs[] =
{}
};
+static const struct dbuf_slice_conf_entry adlp_allowed_dbufs[] = {
+ {
+ .active_pipes = BIT(PIPE_A),
+ .dbuf_mask = {
+ [PIPE_A] = BIT(DBUF_S1) | BIT(DBUF_S2),
+ },
+ },
+ {
+ .active_pipes = BIT(PIPE_B),
+ .dbuf_mask = {
+ [PIPE_B] = BIT(DBUF_S3) | BIT(DBUF_S4),
+ },
+ },
+ {
+ .active_pipes = BIT(PIPE_A) | BIT(PIPE_B),
+ .dbuf_mask = {
+ [PIPE_A] = BIT(DBUF_S1) | BIT(DBUF_S2),
+ [PIPE_B] = BIT(DBUF_S3) | BIT(DBUF_S4),
+ },
+ },
+ {
+ .active_pipes = BIT(PIPE_C),
+ .dbuf_mask = {
+ [PIPE_C] = BIT(DBUF_S3) | BIT(DBUF_S4),
+ },
+ },
+ {
+ .active_pipes = BIT(PIPE_A) | BIT(PIPE_C),
+ .dbuf_mask = {
+ [PIPE_A] = BIT(DBUF_S1) | BIT(DBUF_S2),
+ [PIPE_C] = BIT(DBUF_S3) | BIT(DBUF_S4),
+ },
+ },
+ {
+ .active_pipes = BIT(PIPE_B) | BIT(PIPE_C),
+ .dbuf_mask = {
+ [PIPE_B] = BIT(DBUF_S3) | BIT(DBUF_S4),
+ [PIPE_C] = BIT(DBUF_S3) | BIT(DBUF_S4),
+
[Intel-gfx] [PATCH v2 36/50] drm/i915/adl_p: Add initial ADL_P Workarounds
From: Anusha Srivatsa
Most of the context WA are already implemented for previous platforms.
Adding adl_p platform tag to reflect so.
BSpec: 54369
Cc: Matt Roper
Cc: Aditya Swarup
Cc: Madhumitha Tolakanahalli Pradeep
Cc: Radhakrishna Sripada
Cc: José Roberto de Souza
Cc: Swathi Dhanavanthri
Signed-off-by: Anusha Srivatsa
Signed-off-by: Clinton Taylor
Signed-off-by: Matt Roper
---
drivers/gpu/drm/i915/display/intel_dpll_mgr.c | 2 +-
drivers/gpu/drm/i915/gt/gen8_engine_cs.c | 4 +-
drivers/gpu/drm/i915/gt/intel_workarounds.c | 59 +++
drivers/gpu/drm/i915/intel_pm.c | 8 ++-
4 files changed, 43 insertions(+), 30 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
index 1ae158d12c07..268ecf1c000f 100644
--- a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
+++ b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
@@ -2650,7 +2650,7 @@ ehl_combo_pll_div_frac_wa_needed(struct drm_i915_private
*i915)
{
return ((IS_PLATFORM(i915, INTEL_ELKHARTLAKE) &&
IS_JSL_EHL_REVID(i915, EHL_REVID_B0, REVID_FOREVER)) ||
-IS_TIGERLAKE(i915)) &&
+IS_TIGERLAKE(i915) || IS_ALDERLAKE_P(i915)) &&
i915->dpll.ref_clks.nssc == 38400;
}
diff --git a/drivers/gpu/drm/i915/gt/gen8_engine_cs.c
b/drivers/gpu/drm/i915/gt/gen8_engine_cs.c
index 4b69ede3485d..6d449f494e43 100644
--- a/drivers/gpu/drm/i915/gt/gen8_engine_cs.c
+++ b/drivers/gpu/drm/i915/gt/gen8_engine_cs.c
@@ -208,7 +208,7 @@ int gen12_emit_flush_rcs(struct i915_request *rq, u32 mode)
flags |= PIPE_CONTROL_FLUSH_L3;
flags |= PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH;
flags |= PIPE_CONTROL_DEPTH_CACHE_FLUSH;
- /* Wa_1409600907:tgl */
+ /* Wa_1409600907:tgl,adl_p */
flags |= PIPE_CONTROL_DEPTH_STALL;
flags |= PIPE_CONTROL_DC_FLUSH_ENABLE;
flags |= PIPE_CONTROL_FLUSH_ENABLE;
@@ -625,7 +625,7 @@ u32 *gen12_emit_fini_breadcrumb_rcs(struct i915_request
*rq, u32 *cs)
PIPE_CONTROL_FLUSH_L3 |
PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH |
PIPE_CONTROL_DEPTH_CACHE_FLUSH |
- /* Wa_1409600907:tgl */
+ /* Wa_1409600907:tgl,adl_p */
PIPE_CONTROL_DEPTH_STALL |
PIPE_CONTROL_DC_FLUSH_ENABLE |
PIPE_CONTROL_FLUSH_ENABLE);
diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c
b/drivers/gpu/drm/i915/gt/intel_workarounds.c
index bb2357119792..d3167ff4ca6b 100644
--- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
+++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
@@ -650,15 +650,16 @@ static void gen12_ctx_workarounds_init(struct
intel_engine_cs *engine,
struct i915_wa_list *wal)
{
/*
-* Wa_1409142259:tgl
-* Wa_1409347922:tgl
-* Wa_1409252684:tgl
-* Wa_1409217633:tgl
-* Wa_1409207793:tgl
-* Wa_1409178076:tgl
-* Wa_1408979724:tgl
-* Wa_14010443199:rkl
-* Wa_14010698770:rkl
+* Wa_1409142259:tgl, adl_p
+* Wa_1409347922:tgl, adl_p
+* Wa_1409252684:tgl, adl_p
+* Wa_1409217633:tgl, adl_p
+* Wa_1409207793:tgl, adl_p
+* Wa_1409178076:tgl, adl_p
+* Wa_1408979724:tgl, adl_p
+* Wa_14010443199:rkl, adl_p
+* Wa_14010698770:rkl, adl_p
+* Wa_1409342910: adl_p
*/
wa_masked_en(wal, GEN11_COMMON_SLICE_CHICKEN3,
GEN12_DISABLE_CPS_AWARE_COLOR_PIPE);
@@ -1644,31 +1645,32 @@ rcs_engine_wa_init(struct intel_engine_cs *engine,
struct i915_wa_list *wal)
IS_ROCKETLAKE(i915) || IS_TIGERLAKE(i915)) {
/* Wa_1606931601:tgl,rkl,dg1,adl-s */
wa_masked_en(wal, GEN7_ROW_CHICKEN2, GEN12_DISABLE_EARLY_READ);
+ }
+
+ if (IS_ALDERLAKE_P(i915) || IS_ALDERLAKE_S(i915) || IS_DG1(i915) ||
+ IS_ROCKETLAKE(i915) || IS_TIGERLAKE(i915)) {
+ /*
+* Wa_1606700617:tgl,dg1,adlp
+* Wa_22010271021:tgl,rkl,dg1,adls,adlp
+* Wa_14010826681: tgl,dg1
+*/
+ wa_masked_en(wal,
+GEN9_CS_DEBUG_MODE1,
+FF_DOP_CLOCK_GATE_DISABLE);
/*
* Wa_1407928979:tgl A*
* Wa_18011464164:tgl[B0+],dg1[B0+]
* Wa_22010931296:tgl[B0+],dg1[B0+]
-* Wa_14010919138:rkl,dg1,adl-s
+* Wa_14010919138:rkl,dg1,adl-s,adl-p
*/
wa_write_or(wal, GEN7_FF_THREAD_MODE,
GEN12_FF_TESSELAT
[Intel-gfx] [PATCH v2 41/50] drm/i915/bigjoiner: Mode validation with uncompressed pipe joiner
From: Animesh Manna No need for checking dsc flag for uncompressed pipe joiner mode validation. Cc: Manasi Navare Signed-off-by: Animesh Manna Signed-off-by: Clinton Taylor Signed-off-by: Matt Roper --- drivers/gpu/drm/i915/display/intel_dp.c | 7 +-- 1 file changed, 5 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c index 57a1868475ae..ab9b36a14809 100644 --- a/drivers/gpu/drm/i915/display/intel_dp.c +++ b/drivers/gpu/drm/i915/display/intel_dp.c @@ -817,8 +817,11 @@ intel_dp_mode_valid(struct drm_connector *connector, dsc = dsc_max_output_bpp && dsc_slice_count; } - /* big joiner configuration needs DSC */ - if (bigjoiner && !dsc) + /* +* Big joiner configuration needs DSC for TGL which is not true for +* ADLP where uncompressed joiner is supported. +*/ + if (!(DISPLAY_VER(dev_priv) == 13) && bigjoiner && !dsc) return MODE_CLOCK_HIGH; if (mode_rate > max_rate && !dsc) -- 2.25.4 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH v2 30/50] drm/i915/adl_p: Don't config MBUS and DBUF during display initialization
From: José Roberto de Souza Alderlake-P don't have programing sequences for MBUS or DBUF during display initializaiton, instead it requires programing to those registers during modeset because it to depend on the pipes left enabled. Bspec: 49213 Cc: Matt Roper Signed-off-by: José Roberto de Souza Signed-off-by: Clinton Taylor Signed-off-by: Matt Roper --- drivers/gpu/drm/i915/display/intel_display_power.c | 6 ++ 1 file changed, 6 insertions(+) diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c b/drivers/gpu/drm/i915/display/intel_display_power.c index 3e407d0bf363..969cde822e1e 100644 --- a/drivers/gpu/drm/i915/display/intel_display_power.c +++ b/drivers/gpu/drm/i915/display/intel_display_power.c @@ -5249,6 +5249,9 @@ static void gen12_dbuf_slices_config(struct drm_i915_private *dev_priv) const int num_slices = INTEL_INFO(dev_priv)->num_supported_dbuf_slices; enum dbuf_slice slice; + if (IS_ALDERLAKE_P(dev_priv)) + return; + for (slice = DBUF_S1; slice < (DBUF_S1 + num_slices); slice++) intel_de_rmw(dev_priv, DBUF_CTL_S(slice), DBUF_TRACKER_STATE_SERVICE_MASK, @@ -5260,6 +5263,9 @@ static void icl_mbus_init(struct drm_i915_private *dev_priv) unsigned long abox_regs = INTEL_INFO(dev_priv)->abox_mask; u32 mask, val, i; + if (IS_ALDERLAKE_P(dev_priv)) + return; + mask = MBUS_ABOX_BT_CREDIT_POOL1_MASK | MBUS_ABOX_BT_CREDIT_POOL2_MASK | MBUS_ABOX_B_CREDIT_MASK | -- 2.25.4 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH v2 37/50] drm/i915/adlp: Define GuC/HuC for Alderlake_P
From: Clint Taylor Initial GuC/HuC definitions for ADL_P Cc: Anusha Srivatsa Cc: Matt Roper Signed-off-by: Clint Taylor Signed-off-by: Matt Roper --- drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c b/drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c index df647c9a8d56..eeb0192c33b2 100644 --- a/drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c +++ b/drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c @@ -48,6 +48,7 @@ void intel_uc_fw_change_status(struct intel_uc_fw *uc_fw, * firmware as TGL. */ #define INTEL_UC_FIRMWARE_DEFS(fw_def, guc_def, huc_def) \ + fw_def(ALDERLAKE_P, 0, guc_def(tgl, 49, 0, 1), huc_def(tgl, 7, 5, 0)) \ fw_def(ALDERLAKE_S, 0, guc_def(tgl, 49, 0, 1), huc_def(tgl, 7, 5, 0)) \ fw_def(ROCKETLAKE, 0, guc_def(tgl, 49, 0, 1), huc_def(tgl, 7, 5, 0)) \ fw_def(TIGERLAKE, 0, guc_def(tgl, 49, 0, 1), huc_def(tgl, 7, 5, 0)) \ -- 2.25.4 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH v2 47/50] drm/i915/display/adl_p: Implement Wa_22011320316
From: José Roberto de Souza
Implementation details are in the HSD 22011320316, requiring CD clock
to be at least 307MHz to make DC states to work.
Cc: Matt Roper
Cc: Anusha Srivatsa
Signed-off-by: José Roberto de Souza
Signed-off-by: Clinton Taylor
Signed-off-by: Matt Roper
---
drivers/gpu/drm/i915/display/intel_cdclk.c | 21 -
drivers/gpu/drm/i915/i915_drv.h| 7 +++
2 files changed, 27 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c
b/drivers/gpu/drm/i915/display/intel_cdclk.c
index 4c441b359d7f..a1fafd3573e8 100644
--- a/drivers/gpu/drm/i915/display/intel_cdclk.c
+++ b/drivers/gpu/drm/i915/display/intel_cdclk.c
@@ -1257,6 +1257,21 @@ static const struct intel_cdclk_vals rkl_cdclk_table[] =
{
{}
};
+static const struct intel_cdclk_vals adlp_a_step_cdclk_table[] = {
+ { .refclk = 19200, .cdclk = 307200, .divider = 2, .ratio = 32 },
+ { .refclk = 19200, .cdclk = 556800, .divider = 2, .ratio = 58 },
+ { .refclk = 19200, .cdclk = 652800, .divider = 2, .ratio = 68 },
+
+ { .refclk = 24000, .cdclk = 312000, .divider = 2, .ratio = 26 },
+ { .refclk = 24000, .cdclk = 552000, .divider = 2, .ratio = 46 },
+ { .refclk = 24400, .cdclk = 648000, .divider = 2, .ratio = 54 },
+
+ { .refclk = 38400, .cdclk = 307200, .divider = 2, .ratio = 16 },
+ { .refclk = 38400, .cdclk = 556800, .divider = 2, .ratio = 29 },
+ { .refclk = 38400, .cdclk = 652800, .divider = 2, .ratio = 34 },
+ {}
+};
+
static const struct intel_cdclk_vals adlp_cdclk_table[] = {
{ .refclk = 19200, .cdclk = 172800, .divider = 3, .ratio = 27 },
{ .refclk = 19200, .cdclk = 192000, .divider = 2, .ratio = 20 },
@@ -2836,7 +2851,11 @@ void intel_init_cdclk_hooks(struct drm_i915_private
*dev_priv)
dev_priv->display.bw_calc_min_cdclk = skl_bw_calc_min_cdclk;
dev_priv->display.modeset_calc_cdclk = bxt_modeset_calc_cdclk;
dev_priv->display.calc_voltage_level = tgl_calc_voltage_level;
- dev_priv->cdclk.table = adlp_cdclk_table;
+ /* Wa_22011320316:adlp[a0] */
+ if (IS_ADLP_REVID(dev_priv, ADLP_REVID_A0, ADLP_REVID_A0))
+ dev_priv->cdclk.table = adlp_a_step_cdclk_table;
+ else
+ dev_priv->cdclk.table = adlp_cdclk_table;
} else if (IS_ROCKETLAKE(dev_priv)) {
dev_priv->display.set_cdclk = bxt_set_cdclk;
dev_priv->display.bw_calc_min_cdclk = skl_bw_calc_min_cdclk;
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 68e216f5e0bb..b89b27b94e22 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -1598,6 +1598,13 @@ tgl_stepping_get(struct drm_i915_private *dev_priv)
tgl_stepping_get(p)->gt_stepping >= (since) && \
tgl_stepping_get(p)->gt_stepping <= (until))
+#define ADLP_REVID_A0 0x0
+#define ADLP_REVID_B0 0x4
+#define ADLP_REVID_C0 0x8
+
+#define IS_ADLP_REVID(p, since, until) \
+ (IS_ALDERLAKE_P(p) && IS_REVID(p, since, until))
+
#define IS_LP(dev_priv)(INTEL_INFO(dev_priv)->is_lp)
#define IS_GEN9_LP(dev_priv) (IS_GEN(dev_priv, 9) && IS_LP(dev_priv))
#define IS_GEN9_BC(dev_priv) (IS_GEN(dev_priv, 9) && !IS_LP(dev_priv))
--
2.25.4
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[Intel-gfx] [PATCH v2 25/50] drm/i915/adl_p: Add cdclk support for ADL-P
From: Anusha Srivatsa
ADL-P has 3 possible refclk frequencies: 19.2MHz,
24MHz and 38.4MHz
BSpec: 55409, 49208
Cc: Matt Roper
Cc: Clinton Taylor
Cc: José Roberto de Souza
Signed-off-by: Anusha Srivatsa
Signed-off-by: Clinton Taylor
Signed-off-by: Matt Roper
---
drivers/gpu/drm/i915/display/intel_cdclk.c | 29 +-
1 file changed, 28 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c
b/drivers/gpu/drm/i915/display/intel_cdclk.c
index 3f43ad4d7362..85da8c43d5d6 100644
--- a/drivers/gpu/drm/i915/display/intel_cdclk.c
+++ b/drivers/gpu/drm/i915/display/intel_cdclk.c
@@ -1257,6 +1257,27 @@ static const struct intel_cdclk_vals rkl_cdclk_table[] =
{
{}
};
+static const struct intel_cdclk_vals adlp_cdclk_table[] = {
+ { .refclk = 19200, .cdclk = 172800, .divider = 3, .ratio = 27 },
+ { .refclk = 19200, .cdclk = 192000, .divider = 2, .ratio = 20 },
+ { .refclk = 19200, .cdclk = 307200, .divider = 2, .ratio = 32 },
+ { .refclk = 19200, .cdclk = 556800, .divider = 2, .ratio = 58 },
+ { .refclk = 19200, .cdclk = 652800, .divider = 2, .ratio = 68 },
+
+ { .refclk = 24000, .cdclk = 176000, .divider = 3, .ratio = 22 },
+ { .refclk = 24000, .cdclk = 192000, .divider = 2, .ratio = 16 },
+ { .refclk = 24000, .cdclk = 312000, .divider = 2, .ratio = 26 },
+ { .refclk = 24000, .cdclk = 552000, .divider = 2, .ratio = 46 },
+ { .refclk = 24400, .cdclk = 648000, .divider = 2, .ratio = 54 },
+
+ { .refclk = 38400, .cdclk = 179200, .divider = 3, .ratio = 14 },
+ { .refclk = 38400, .cdclk = 192000, .divider = 2, .ratio = 10 },
+ { .refclk = 38400, .cdclk = 307200, .divider = 2, .ratio = 16 },
+ { .refclk = 38400, .cdclk = 556800, .divider = 2, .ratio = 29 },
+ { .refclk = 38400, .cdclk = 652800, .divider = 2, .ratio = 34 },
+ {}
+};
+
static int bxt_calc_cdclk(struct drm_i915_private *dev_priv, int min_cdclk)
{
const struct intel_cdclk_vals *table = dev_priv->cdclk.table;
@@ -2848,7 +2869,13 @@ u32 intel_read_rawclk(struct drm_i915_private *dev_priv)
*/
void intel_init_cdclk_hooks(struct drm_i915_private *dev_priv)
{
- if (IS_ROCKETLAKE(dev_priv)) {
+ if (IS_ALDERLAKE_P(dev_priv)) {
+ dev_priv->display.set_cdclk = bxt_set_cdclk;
+ dev_priv->display.bw_calc_min_cdclk = skl_bw_calc_min_cdclk;
+ dev_priv->display.modeset_calc_cdclk = bxt_modeset_calc_cdclk;
+ dev_priv->display.calc_voltage_level = tgl_calc_voltage_level;
+ dev_priv->cdclk.table = adlp_cdclk_table;
+ } else if (IS_ROCKETLAKE(dev_priv)) {
dev_priv->display.set_cdclk = bxt_set_cdclk;
dev_priv->display.bw_calc_min_cdclk = skl_bw_calc_min_cdclk;
dev_priv->display.modeset_calc_cdclk = bxt_modeset_calc_cdclk;
--
2.25.4
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[Intel-gfx] [PATCH v2 24/50] drm/i915/adl_p: Setup ports/phys
From: Anusha Srivatsa
The SoC has 6 DDI ports(DDI A,DDI B and DDI TC1-4.
The first two are connected to combo phys while
the rest are connected to TC phys.
Cc: Matt Roper
Cc: Clinton Taylor
Cc: Lucas De Marchi
Cc: Swathi Dhanavanthri
Signed-off-by: Anusha Srivatsa
Signed-off-by: Clinton Taylor
Signed-off-by: Matt Roper
---
drivers/gpu/drm/i915/display/intel_display.c | 13 +++--
1 file changed, 11 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display.c
b/drivers/gpu/drm/i915/display/intel_display.c
index d04924d405e5..265518bc197e 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -4196,7 +4196,9 @@ bool intel_phy_is_combo(struct drm_i915_private
*dev_priv, enum phy phy)
bool intel_phy_is_tc(struct drm_i915_private *dev_priv, enum phy phy)
{
- if (IS_TIGERLAKE(dev_priv))
+ if (IS_ALDERLAKE_P(dev_priv))
+ return phy >= PHY_F && phy <= PHY_I;
+ else if (IS_TIGERLAKE(dev_priv))
return phy >= PHY_D && phy <= PHY_I;
else if (IS_ICELAKE(dev_priv))
return phy >= PHY_C && phy <= PHY_F;
@@ -11695,7 +11697,14 @@ static void intel_setup_outputs(struct
drm_i915_private *dev_priv)
if (!HAS_DISPLAY(dev_priv))
return;
- if (IS_ALDERLAKE_S(dev_priv)) {
+ if (IS_ALDERLAKE_P(dev_priv)) {
+ intel_ddi_init(dev_priv, PORT_A);
+ intel_ddi_init(dev_priv, PORT_B);
+ intel_ddi_init(dev_priv, PORT_TC1);
+ intel_ddi_init(dev_priv, PORT_TC2);
+ intel_ddi_init(dev_priv, PORT_TC3);
+ intel_ddi_init(dev_priv, PORT_TC4);
+ } else if (IS_ALDERLAKE_S(dev_priv)) {
intel_ddi_init(dev_priv, PORT_A);
intel_ddi_init(dev_priv, PORT_TC1);
intel_ddi_init(dev_priv, PORT_TC2);
--
2.25.4
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[Intel-gfx] [PATCH v2 34/50] drm/i915/adl_p: MBUS programming
From: Vandita Kulkarni
Update MBUS_CTL register if the 2 mbus can be joined as per the current
DDB allocation and active pipes, also update hashing mode and pipe
select bits as per the sequence mentioned in the bspec.
Cc: Stanislav Lisovskiy
Cc: José Roberto de Souza
Signed-off-by: Vandita Kulkarni
Signed-off-by: Clinton Taylor
Signed-off-by: Matt Roper
---
drivers/gpu/drm/i915/display/intel_atomic.c | 20 +
drivers/gpu/drm/i915/display/intel_atomic.h | 1 +
drivers/gpu/drm/i915/display/intel_display.c | 3 +
drivers/gpu/drm/i915/i915_reg.h | 11 +++
drivers/gpu/drm/i915/intel_pm.c | 93 ++--
drivers/gpu/drm/i915/intel_pm.h | 2 +-
6 files changed, 121 insertions(+), 9 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_atomic.c
b/drivers/gpu/drm/i915/display/intel_atomic.c
index 4fa389fce8cb..c65cfcb8a501 100644
--- a/drivers/gpu/drm/i915/display/intel_atomic.c
+++ b/drivers/gpu/drm/i915/display/intel_atomic.c
@@ -198,6 +198,26 @@ intel_connector_needs_modeset(struct intel_atomic_state
*state,
new_conn_state->crtc)));
}
+/**
+ * intel_any_crtc_needs_modeset - check if any CRTC needs a modeset
+ * @state: the atomic state corresponding to this modeset
+ *
+ * Returns true if any CRTC in @state needs a modeset.
+ */
+bool intel_any_crtc_needs_modeset(struct intel_atomic_state *state)
+{
+ struct intel_crtc *crtc;
+ struct intel_crtc_state *crtc_state;
+ int i;
+
+ for_each_new_intel_crtc_in_state(state, crtc, crtc_state, i) {
+ if (intel_crtc_needs_modeset(crtc_state))
+ return true;
+ }
+
+ return false;
+}
+
struct intel_digital_connector_state *
intel_atomic_get_digital_connector_state(struct intel_atomic_state *state,
struct intel_connector *connector)
diff --git a/drivers/gpu/drm/i915/display/intel_atomic.h
b/drivers/gpu/drm/i915/display/intel_atomic.h
index 62a3365ed5e6..d2700c74c9da 100644
--- a/drivers/gpu/drm/i915/display/intel_atomic.h
+++ b/drivers/gpu/drm/i915/display/intel_atomic.h
@@ -35,6 +35,7 @@ struct drm_connector_state *
intel_digital_connector_duplicate_state(struct drm_connector *connector);
bool intel_connector_needs_modeset(struct intel_atomic_state *state,
struct drm_connector *connector);
+bool intel_any_crtc_needs_modeset(struct intel_atomic_state *state);
struct intel_digital_connector_state *
intel_atomic_get_digital_connector_state(struct intel_atomic_state *state,
struct intel_connector *connector);
diff --git a/drivers/gpu/drm/i915/display/intel_display.c
b/drivers/gpu/drm/i915/display/intel_display.c
index 33cdc419c627..64c64993b755 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -10488,6 +10488,9 @@ static int intel_atomic_check(struct drm_device *dev,
if (ret)
goto fail;
+ if (intel_any_crtc_needs_modeset(state))
+ any_ms = true;
+
if (any_ms) {
ret = intel_modeset_checks(state);
if (ret)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index da8ee0a3b652..8e24be53b63f 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -2929,6 +2929,15 @@ static inline bool i915_mmio_reg_valid(i915_reg_t reg)
#define MBUS_BBOX_CTL_S1 _MMIO(0x45040)
#define MBUS_BBOX_CTL_S2 _MMIO(0x45044)
+#define MBUS_CTL _MMIO(0x4438C)
+#define MBUS_JOIN REG_BIT(31)
+#define MBUS_HASHING_MODE_MASK REG_BIT(30)
+#define MBUS_HASHING_MODE_2x2 REG_FIELD_PREP(MBUS_HASHING_MODE_MASK,
0)
+#define MBUS_HASHING_MODE_1x4 REG_FIELD_PREP(MBUS_HASHING_MODE_MASK,
1)
+#define MBUS_JOIN_PIPE_SELECT_MASK REG_GENMASK(28, 26)
+#define MBUS_JOIN_PIPE_SELECT(pipe)
REG_FIELD_PREP(MBUS_JOIN_PIPE_SELECT_MASK, pipe)
+#define MBUS_JOIN_PIPE_SELECT_NONE MBUS_JOIN_PIPE_SELECT(7)
+
#define HDPORT_STATE _MMIO(0x45050)
#define HDPORT_DPLL_USED_MASKREG_GENMASK(15, 12)
#define HDPORT_DDI_USED(phy) REG_BIT(2 * (phy) + 1)
@@ -8157,6 +8166,8 @@ enum {
#define DBUF_POWER_STATE REG_BIT(30)
#define DBUF_TRACKER_STATE_SERVICE_MASK REG_GENMASK(23, 19)
#define DBUF_TRACKER_STATE_SERVICE(x)
REG_FIELD_PREP(DBUF_TRACKER_STATE_SERVICE_MASK, x)
+#define DBUF_MIN_TRACKER_STATE_SERVICE_MASK REG_GENMASK(18, 16) /* ADL-P+ */
+#define DBUF_MIN_TRACKER_STATE_SERVICE(x)
REG_FIELD_PREP(DBUF_MIN_TRACKER_STATE_SERVICE_MASK, x) /* ADL-P+ */
#define GEN7_MSG_CTL _MMIO(0x45010)
#define WAIT_FOR_PCH_RESET_ACK(1 << 1)
diff --git a/drivers/gpu/drm/i915/intel_
[Intel-gfx] [PATCH v2 43/50] drm/i915/bigjoiner: atomic commit changes for uncompressed joiner
From: Animesh Manna
Respective bit for master or slave to be set for uncompressed
bigjoiner in dss_ctl1 register.
Cc: Manasi Navare
Signed-off-by: Animesh Manna
Signed-off-by: Clinton Taylor
Signed-off-by: Matt Roper
---
drivers/gpu/drm/i915/display/intel_display.c | 6 +++
drivers/gpu/drm/i915/display/intel_vdsc.c| 40 +++-
drivers/gpu/drm/i915/display/intel_vdsc.h| 2 +
drivers/gpu/drm/i915/i915_reg.h | 2 +
4 files changed, 49 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display.c
b/drivers/gpu/drm/i915/display/intel_display.c
index 64c64993b755..6543db5e1c6c 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -3936,6 +3936,7 @@ static void icl_ddi_bigjoiner_pre_enable(struct
intel_atomic_state *state,
const struct intel_crtc_state
*crtc_state)
{
struct intel_crtc *master = to_intel_crtc(crtc_state->uapi.crtc);
+ struct drm_i915_private *dev_priv = to_i915(master->base.dev);
struct intel_crtc_state *master_crtc_state;
struct drm_connector_state *conn_state;
struct drm_connector *conn;
@@ -3969,6 +3970,9 @@ static void icl_ddi_bigjoiner_pre_enable(struct
intel_atomic_state *state,
/* and DSC on slave */
intel_dsc_enable(NULL, crtc_state);
}
+
+ if (DISPLAY_VER(dev_priv) == 13)
+ intel_uncompressed_joiner_enable(crtc_state);
}
static void hsw_crtc_enable(struct intel_atomic_state *state,
@@ -6785,6 +6789,8 @@ static bool hsw_get_pipe_config(struct intel_crtc *crtc,
}
intel_dsc_get_config(pipe_config);
+ if ((DISPLAY_VER(dev_priv) == 13) &&
!pipe_config->dsc.compression_enable)
+ intel_uncompressed_joiner_get_config(pipe_config);
if (!active) {
/* bigjoiner slave doesn't enable transcoder */
diff --git a/drivers/gpu/drm/i915/display/intel_vdsc.c
b/drivers/gpu/drm/i915/display/intel_vdsc.c
index 014a172d2bee..1cfb9aca5e50 100644
--- a/drivers/gpu/drm/i915/display/intel_vdsc.c
+++ b/drivers/gpu/drm/i915/display/intel_vdsc.c
@@ -1116,6 +1116,22 @@ static i915_reg_t dss_ctl2_reg(const struct
intel_crtc_state *crtc_state)
return is_pipe_dsc(crtc_state) ? ICL_PIPE_DSS_CTL2(pipe) : DSS_CTL2;
}
+void intel_uncompressed_joiner_enable(const struct intel_crtc_state
*crtc_state)
+{
+ struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
+ struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
+ u32 dss_ctl1_val = 0;
+
+ if (crtc_state->bigjoiner && !crtc_state->dsc.compression_enable) {
+ if (crtc_state->bigjoiner_slave)
+ dss_ctl1_val |= UNCOMPRESSED_JOINER_SLAVE;
+ else
+ dss_ctl1_val |= UNCOMPRESSED_JOINER_MASTER;
+
+ intel_de_write(dev_priv, dss_ctl1_reg(crtc_state),
dss_ctl1_val);
+ }
+}
+
void intel_dsc_enable(struct intel_encoder *encoder,
const struct intel_crtc_state *crtc_state)
{
@@ -1155,13 +1171,35 @@ void intel_dsc_disable(const struct intel_crtc_state
*old_crtc_state)
struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->uapi.crtc);
struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
- if (!old_crtc_state->dsc.compression_enable)
+ if (!(old_crtc_state->dsc.compression_enable &&
+ old_crtc_state->bigjoiner))
return;
intel_de_write(dev_priv, dss_ctl1_reg(old_crtc_state), 0);
intel_de_write(dev_priv, dss_ctl2_reg(old_crtc_state), 0);
}
+void intel_uncompressed_joiner_get_config(struct intel_crtc_state *crtc_state)
+{
+ struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
+ struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
+ u32 dss_ctl1;
+
+ dss_ctl1 = intel_de_read(dev_priv, dss_ctl1_reg(crtc_state));
+ if (dss_ctl1 & UNCOMPRESSED_JOINER_MASTER) {
+ crtc_state->bigjoiner = true;
+ if (!WARN_ON(INTEL_NUM_PIPES(dev_priv) == crtc->pipe + 1))
+ crtc_state->bigjoiner_linked_crtc =
+ intel_get_crtc_for_pipe(dev_priv, crtc->pipe +
1);
+ } else if (dss_ctl1 & UNCOMPRESSED_JOINER_SLAVE) {
+ crtc_state->bigjoiner = true;
+ crtc_state->bigjoiner_slave = true;
+ if (!WARN_ON(crtc->pipe == PIPE_A))
+ crtc_state->bigjoiner_linked_crtc =
+ intel_get_crtc_for_pipe(dev_priv, crtc->pipe -
1);
+ }
+}
+
void intel_dsc_get_config(struct intel_crtc_state *crtc_state)
{
struct drm_dsc_config *vdsc_cfg = &crtc_state->dsc.config;
diff --git a/drivers/gpu/drm/i915/display/intel_vdsc.h
b/drivers/gpu/drm/i915/display/intel_vdsc.h
index 65d301c23580..fe4d45561253 100644
--- a/driver
[Intel-gfx] [PATCH v2 26/50] drm/i915/display/tc: Rename safe_mode functions ownership
From: José Roberto de Souza
When DP_PHY_MODE_STATUS_NOT_SAFE is set, it means that display
has the control over the TC phy.
The "not safe" naming is confusing using ownership make it easier
to read also future platforms will have a new register that does the
same job as DP_PHY_MODE_STATUS_NOT_SAFE but with the onwership name.
BSpec: 49294
Cc: Imre Deak
Signed-off-by: José Roberto de Souza
Signed-off-by: Clinton Taylor
Signed-off-by: Matt Roper
---
drivers/gpu/drm/i915/display/intel_tc.c | 35 -
1 file changed, 17 insertions(+), 18 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_tc.c
b/drivers/gpu/drm/i915/display/intel_tc.c
index 71b8edafb1c3..c007803cfd30 100644
--- a/drivers/gpu/drm/i915/display/intel_tc.c
+++ b/drivers/gpu/drm/i915/display/intel_tc.c
@@ -256,8 +256,8 @@ static bool icl_tc_phy_status_complete(struct
intel_digital_port *dig_port)
return val & DP_PHY_MODE_STATUS_COMPLETED(dig_port->tc_phy_fia_idx);
}
-static bool icl_tc_phy_set_safe_mode(struct intel_digital_port *dig_port,
-bool enable)
+static bool icl_tc_phy_take_ownership(struct intel_digital_port *dig_port,
+ bool take)
{
struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
struct intel_uncore *uncore = &i915->uncore;
@@ -267,20 +267,20 @@ static bool icl_tc_phy_set_safe_mode(struct
intel_digital_port *dig_port,
PORT_TX_DFLEXDPCSSS(dig_port->tc_phy_fia));
if (val == 0x) {
drm_dbg_kms(&i915->drm,
- "Port %s: PHY in TCCOLD, can't set safe-mode to
%s\n",
- dig_port->tc_port_name, enableddisabled(enable));
+ "Port %s: PHY in TCCOLD, can't %s ownership\n",
+ dig_port->tc_port_name, take ? "take" : "release");
return false;
}
val &= ~DP_PHY_MODE_STATUS_NOT_SAFE(dig_port->tc_phy_fia_idx);
- if (!enable)
+ if (take)
val |= DP_PHY_MODE_STATUS_NOT_SAFE(dig_port->tc_phy_fia_idx);
intel_uncore_write(uncore,
PORT_TX_DFLEXDPCSSS(dig_port->tc_phy_fia), val);
- if (enable && wait_for(!icl_tc_phy_status_complete(dig_port), 10))
+ if (!take && wait_for(!icl_tc_phy_status_complete(dig_port), 10))
drm_dbg_kms(&i915->drm,
"Port %s: PHY complete clear timed out\n",
dig_port->tc_port_name);
@@ -288,7 +288,7 @@ static bool icl_tc_phy_set_safe_mode(struct
intel_digital_port *dig_port,
return true;
}
-static bool icl_tc_phy_is_in_safe_mode(struct intel_digital_port *dig_port)
+static bool icl_tc_phy_is_owned(struct intel_digital_port *dig_port)
{
struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
struct intel_uncore *uncore = &i915->uncore;
@@ -303,7 +303,7 @@ static bool icl_tc_phy_is_in_safe_mode(struct
intel_digital_port *dig_port)
return true;
}
- return !(val & DP_PHY_MODE_STATUS_NOT_SAFE(dig_port->tc_phy_fia_idx));
+ return val & DP_PHY_MODE_STATUS_NOT_SAFE(dig_port->tc_phy_fia_idx);
}
/*
@@ -329,7 +329,7 @@ static void icl_tc_phy_connect(struct intel_digital_port
*dig_port,
goto out_set_tbt_alt_mode;
}
- if (!icl_tc_phy_set_safe_mode(dig_port, false) &&
+ if (!icl_tc_phy_take_ownership(dig_port, true) &&
!drm_WARN_ON(&i915->drm, dig_port->tc_legacy_port))
goto out_set_tbt_alt_mode;
@@ -348,7 +348,7 @@ static void icl_tc_phy_connect(struct intel_digital_port
*dig_port,
if (!(tc_port_live_status_mask(dig_port) & BIT(TC_PORT_DP_ALT))) {
drm_dbg_kms(&i915->drm, "Port %s: PHY sudden disconnect\n",
dig_port->tc_port_name);
- goto out_set_safe_mode;
+ goto out_release_phy;
}
if (max_lanes < required_lanes) {
@@ -356,15 +356,15 @@ static void icl_tc_phy_connect(struct intel_digital_port
*dig_port,
"Port %s: PHY max lanes %d < required lanes %d\n",
dig_port->tc_port_name,
max_lanes, required_lanes);
- goto out_set_safe_mode;
+ goto out_release_phy;
}
dig_port->tc_mode = TC_PORT_DP_ALT;
return;
-out_set_safe_mode:
- icl_tc_phy_set_safe_mode(dig_port, true);
+out_release_phy:
+ icl_tc_phy_take_ownership(dig_port, false);
out_set_tbt_alt_mode:
dig_port->tc_mode = TC_PORT_TBT_ALT;
}
@@ -380,7 +380,7 @@ static void icl_tc_phy_disconnect(struct intel_digital_port
*dig_port)
/* Nothing to do, we never disconnect from legacy mode */
break;
case TC_PORT_DP_ALT:
- icl_tc_phy_set_safe_mode(dig_port,
[Intel-gfx] [PATCH v2 27/50] drm/i915/adl_p: Handle TC cold
From: José Roberto de Souza On ADL-P TC cold is exited and blocked when legacy aux is powered, that is exacly the same of what ICL need for static TC ports. TODO: When a TBT hub or monitor is connected it will cause TBT and legacy aux to be powered at the same time, hopefully this will not cause any issues but if it do, some rework will be needed. BSpec: 55480 Cc: Imre Deak Signed-off-by: José Roberto de Souza Signed-off-by: Clinton Taylor Signed-off-by: Matt Roper --- drivers/gpu/drm/i915/display/intel_display_power.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c b/drivers/gpu/drm/i915/display/intel_display_power.c index 20cfb86c0174..3e407d0bf363 100644 --- a/drivers/gpu/drm/i915/display/intel_display_power.c +++ b/drivers/gpu/drm/i915/display/intel_display_power.c @@ -550,7 +550,8 @@ static void icl_tc_port_assert_ref_held(struct drm_i915_private *dev_priv, if (drm_WARN_ON(&dev_priv->drm, !dig_port)) return; - if (IS_DISPLAY_VER(dev_priv, 11) && dig_port->tc_legacy_port) + if (IS_ALDERLAKE_P(dev_priv) || + (IS_DISPLAY_VER(dev_priv, 11) && dig_port->tc_legacy_port)) return; drm_WARN_ON(&dev_priv->drm, !intel_tc_port_ref_held(dig_port)); -- 2.25.4 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH v2 45/50] drm/i915/adl_p: Update memory bandwidth parameters
From: Anusha Srivatsa ADL_P has same memory characteristics as ADL_S platform. Bspec: 64631 Cc: José Roberto de Souza Cc: Clint Taylor Signed-off-by: Anusha Srivatsa Signed-off-by: Clinton Taylor Signed-off-by: Matt Roper --- drivers/gpu/drm/i915/display/intel_bw.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/display/intel_bw.c b/drivers/gpu/drm/i915/display/intel_bw.c index 72e2721f949b..c04a1438a488 100644 --- a/drivers/gpu/drm/i915/display/intel_bw.c +++ b/drivers/gpu/drm/i915/display/intel_bw.c @@ -267,7 +267,7 @@ void intel_bw_init_hw(struct drm_i915_private *dev_priv) if (!HAS_DISPLAY(dev_priv)) return; - if (IS_ALDERLAKE_S(dev_priv)) + if (IS_ALDERLAKE_S(dev_priv) || IS_ALDERLAKE_P(dev_priv)) icl_get_bw_info(dev_priv, &adls_sa_info); else if (IS_ROCKETLAKE(dev_priv)) icl_get_bw_info(dev_priv, &rkl_sa_info); -- 2.25.4 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH v2 48/50] drm/i915/display/adl_p: Remove CCS support
From: José Roberto de Souza
Buffer compression is not usable in A stepping.
Cc: Matt Roper
Cc: Anusha Srivatsa
Cc: Clinton A Taylor
Cc: Juha-Pekka Heikkilä
Signed-off-by: José Roberto de Souza
Signed-off-by: Clinton Taylor
Signed-off-by: Matt Roper
Reviewed-by: Anusha Srivatsa
---
.../drm/i915/display/skl_universal_plane.c| 20 ++-
1 file changed, 19 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/display/skl_universal_plane.c
b/drivers/gpu/drm/i915/display/skl_universal_plane.c
index 4a1a4caf6453..dd754b11a21d 100644
--- a/drivers/gpu/drm/i915/display/skl_universal_plane.c
+++ b/drivers/gpu/drm/i915/display/skl_universal_plane.c
@@ -197,6 +197,13 @@ static const u64 gen12_plane_format_modifiers_rc_ccs[] = {
DRM_FORMAT_MOD_INVALID
};
+static const u64 adlp_step_a_plane_format_modifiers[] = {
+ I915_FORMAT_MOD_Y_TILED,
+ I915_FORMAT_MOD_X_TILED,
+ DRM_FORMAT_MOD_LINEAR,
+ DRM_FORMAT_MOD_INVALID
+};
+
int skl_format_to_fourcc(int format, bool rgb_order, bool alpha)
{
switch (format) {
@@ -1885,6 +1892,10 @@ static bool gen12_plane_supports_mc_ccs(struct
drm_i915_private *dev_priv,
IS_TGL_DISP_STEPPING(dev_priv, STEP_A0, STEP_C0))
return false;
+ /* Wa_22011186057 */
+ if (IS_ADLP_REVID(dev_priv, ADLP_REVID_A0, ADLP_REVID_A0))
+ return false;
+
return plane_id < PLANE_SPRITE4;
}
@@ -1902,8 +1913,12 @@ static bool gen12_plane_format_mod_supported(struct
drm_plane *_plane,
case DRM_FORMAT_MOD_LINEAR:
case I915_FORMAT_MOD_X_TILED:
case I915_FORMAT_MOD_Y_TILED:
+ break;
case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS:
case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC:
+ /* Wa_22011186057 */
+ if (IS_ADLP_REVID(dev_priv, ADLP_REVID_A0, ADLP_REVID_A0))
+ return false;
break;
default:
return false;
@@ -1958,7 +1973,10 @@ static bool gen12_plane_format_mod_supported(struct
drm_plane *_plane,
static const u64 *gen12_get_plane_modifiers(struct drm_i915_private *dev_priv,
enum plane_id plane_id)
{
- if (gen12_plane_supports_mc_ccs(dev_priv, plane_id))
+ /* Wa_22011186057 */
+ if (IS_ADLP_REVID(dev_priv, ADLP_REVID_A0, ADLP_REVID_A0))
+ return adlp_step_a_plane_format_modifiers;
+ else if (gen12_plane_supports_mc_ccs(dev_priv, plane_id))
return gen12_plane_format_modifiers_mc_ccs;
else
return gen12_plane_format_modifiers_rc_ccs;
--
2.25.4
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH v2 38/50] drm/i915/adl_p: Define and use ADL-P specific DP translation tables
From: Mika Kahola
Define and use DP voltage swing and pre-emphasis translation tables
for ADL-P.
BSpec: 54956
Cc: Imre Deak
Signed-off-by: Mika Kahola
Signed-off-by: Clinton Taylor
Signed-off-by: Matt Roper
---
drivers/gpu/drm/i915/display/intel_ddi.c | 7 +++-
.../drm/i915/display/intel_ddi_buf_trans.c| 34 +++
.../drm/i915/display/intel_ddi_buf_trans.h| 4 +++
3 files changed, 44 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c
b/drivers/gpu/drm/i915/display/intel_ddi.c
index 933af861253e..1a5213447db1 100644
--- a/drivers/gpu/drm/i915/display/intel_ddi.c
+++ b/drivers/gpu/drm/i915/display/intel_ddi.c
@@ -975,6 +975,8 @@ static u8 intel_ddi_dp_voltage_max(struct intel_dp
*intel_dp,
if (DISPLAY_VER(dev_priv) >= 12) {
if (intel_phy_is_combo(dev_priv, phy))
tgl_get_combo_buf_trans(encoder, crtc_state,
&n_entries);
+ else if (IS_ALDERLAKE_P(dev_priv))
+ adlp_get_dkl_buf_trans(encoder, crtc_state, &n_entries);
else
tgl_get_dkl_buf_trans(encoder, crtc_state, &n_entries);
} else if (IS_DISPLAY_VER(dev_priv, 11)) {
@@ -1421,7 +1423,10 @@ tgl_dkl_phy_ddi_vswing_sequence(struct intel_encoder
*encoder,
if (enc_to_dig_port(encoder)->tc_mode == TC_PORT_TBT_ALT)
return;
- ddi_translations = tgl_get_dkl_buf_trans(encoder, crtc_state,
&n_entries);
+ if (IS_ALDERLAKE_P(dev_priv))
+ ddi_translations = adlp_get_dkl_buf_trans(encoder, crtc_state,
&n_entries);
+ else
+ ddi_translations = tgl_get_dkl_buf_trans(encoder, crtc_state,
&n_entries);
if (drm_WARN_ON_ONCE(&dev_priv->drm, !ddi_translations))
return;
diff --git a/drivers/gpu/drm/i915/display/intel_ddi_buf_trans.c
b/drivers/gpu/drm/i915/display/intel_ddi_buf_trans.c
index 5d9ce6042e87..bb4f799a8ef2 100644
--- a/drivers/gpu/drm/i915/display/intel_ddi_buf_trans.c
+++ b/drivers/gpu/drm/i915/display/intel_ddi_buf_trans.c
@@ -734,6 +734,20 @@ static const struct cnl_ddi_buf_trans
rkl_combo_phy_ddi_translations_dp_hbr2_hbr
{ 0x6, 0x7F, 0x3F, 0x00, 0x00 },/* 900 900 0.0 */
};
+static const struct tgl_dkl_phy_ddi_buf_trans adlp_dkl_phy_dp_ddi_trans[] = {
+ /* VS pre-emp Non-trans mVPre-emph dB */
+ { 0x7, 0x0, 0x00 }, /* 00 400mV 0 dB */
+ { 0x5, 0x0, 0x03 }, /* 01 400mV 3.5 dB */
+ { 0x2, 0x0, 0x0B }, /* 02 400mV 6 dB */
+ { 0x0, 0x0, 0x19 }, /* 03 400mV 9.5 dB */
+ { 0x5, 0x0, 0x00 }, /* 10 600mV 0 dB */
+ { 0x2, 0x0, 0x03 }, /* 11 600mV 3.5 dB */
+ { 0x0, 0x0, 0x14 }, /* 12 600mV 6 dB */
+ { 0x2, 0x0, 0x00 }, /* 20 800mV 0 dB */
+ { 0x0, 0x0, 0x0B }, /* 21 800mV 3.5 dB */
+ { 0x0, 0x0, 0x00 }, /* 30 1200mV 0 dB */
+};
+
bool is_hobl_buf_trans(const struct cnl_ddi_buf_trans *table)
{
return table == tgl_combo_phy_ddi_translations_edp_hbr2_hobl;
@@ -1347,6 +1361,26 @@ tgl_get_dkl_buf_trans(struct intel_encoder *encoder,
return tgl_get_dkl_buf_trans_dp(encoder, crtc_state, n_entries);
}
+static const struct tgl_dkl_phy_ddi_buf_trans *
+adlp_get_dkl_buf_trans_dp(struct intel_encoder *encoder,
+ const struct intel_crtc_state *crtc_state,
+ int *n_entries)
+{
+ *n_entries = ARRAY_SIZE(tgl_dkl_phy_dp_ddi_trans);
+ return adlp_dkl_phy_dp_ddi_trans;
+}
+
+const struct tgl_dkl_phy_ddi_buf_trans *
+adlp_get_dkl_buf_trans(struct intel_encoder *encoder,
+ const struct intel_crtc_state *crtc_state,
+ int *n_entries)
+{
+ if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI))
+ return tgl_get_dkl_buf_trans_hdmi(encoder, crtc_state,
n_entries);
+ else
+ return adlp_get_dkl_buf_trans_dp(encoder, crtc_state,
n_entries);
+}
+
int intel_ddi_hdmi_num_entries(struct intel_encoder *encoder,
const struct intel_crtc_state *crtc_state,
int *default_entry)
diff --git a/drivers/gpu/drm/i915/display/intel_ddi_buf_trans.h
b/drivers/gpu/drm/i915/display/intel_ddi_buf_trans.h
index f8f0ef87e977..4c2efab38642 100644
--- a/drivers/gpu/drm/i915/display/intel_ddi_buf_trans.h
+++ b/drivers/gpu/drm/i915/display/intel_ddi_buf_trans.h
@@ -67,6 +67,10 @@ bxt_get_buf_trans(struct intel_encoder *encoder,
const struct intel_crtc_state *crtc_state,
int *n_entries);
+const struct tgl_dkl_phy_ddi_buf_trans *
+adlp_get_dkl_buf_trans(struct intel_encoder *encoder,
+ con
[Intel-gfx] [PATCH v2 32/50] drm/i915: Introduce MBUS relative dbuf offsets
From: Ville Syrjälä
The dbuf slices are going to be split across several MBUS units.
The actual dbuf programming will use offsets relative to the
MBUS unit. To accomodate that we shall store the MBUS relative
offsets into the dbuf_state->ddb[] and crtc_state->plane_ddb*[].
For crtc_state->wm.skl.ddb however we want to stick to global
offsets as we use this to sanity check that the ddb allocations
don't overlap between pipes.
Cc: Clint Taylor
Signed-off-by: Ville Syrjälä
Signed-off-by: Clinton Taylor
Signed-off-by: Matt Roper
---
drivers/gpu/drm/i915/intel_pm.c | 40 -
1 file changed, 34 insertions(+), 6 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index f0ba23c0f419..34a5c6c08376 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -4069,6 +4069,20 @@ skl_ddb_entry_for_slices(struct drm_i915_private
*dev_priv, u8 slice_mask,
WARN_ON(ddb->end > intel_dbuf_size(dev_priv));
}
+static unsigned int mbus_ddb_offset(struct drm_i915_private *i915, u8
slice_mask)
+{
+ struct skl_ddb_entry ddb;
+
+ if (slice_mask & (BIT(DBUF_S1) | BIT(DBUF_S2)))
+ slice_mask = BIT(DBUF_S1);
+ else if (slice_mask & (BIT(DBUF_S3) | BIT(DBUF_S4)))
+ slice_mask = BIT(DBUF_S3);
+
+ skl_ddb_entry_for_slices(i915, slice_mask, &ddb);
+
+ return ddb.start;
+}
+
u32 skl_ddb_dbuf_slice_mask(struct drm_i915_private *dev_priv,
const struct skl_ddb_entry *entry)
{
@@ -4164,6 +4178,7 @@ skl_crtc_allocate_ddb(struct intel_atomic_state *state,
struct intel_crtc *crtc)
struct intel_crtc_state *crtc_state;
struct skl_ddb_entry ddb_slices;
enum pipe pipe = crtc->pipe;
+ unsigned int mbus_offset;
u32 ddb_range_size;
u32 dbuf_slice_mask;
u32 start, end;
@@ -4178,6 +4193,7 @@ skl_crtc_allocate_ddb(struct intel_atomic_state *state,
struct intel_crtc *crtc)
dbuf_slice_mask = new_dbuf_state->slices[pipe];
skl_ddb_entry_for_slices(dev_priv, dbuf_slice_mask, &ddb_slices);
+ mbus_offset = mbus_ddb_offset(dev_priv, dbuf_slice_mask);
ddb_range_size = skl_ddb_entry_size(&ddb_slices);
intel_crtc_dbuf_weights(new_dbuf_state, pipe,
@@ -4186,11 +4202,11 @@ skl_crtc_allocate_ddb(struct intel_atomic_state *state,
struct intel_crtc *crtc)
start = ddb_range_size * weight_start / weight_total;
end = ddb_range_size * weight_end / weight_total;
- new_dbuf_state->ddb[pipe].start = ddb_slices.start + start;
- new_dbuf_state->ddb[pipe].end = ddb_slices.start + end;
-
+ new_dbuf_state->ddb[pipe].start = ddb_slices.start - mbus_offset +
start;
+ new_dbuf_state->ddb[pipe].end = ddb_slices.start - mbus_offset + end;
out:
- if (skl_ddb_entry_equal(&old_dbuf_state->ddb[pipe],
+ if (old_dbuf_state->slices[pipe] == new_dbuf_state->slices[pipe] &&
+ skl_ddb_entry_equal(&old_dbuf_state->ddb[pipe],
&new_dbuf_state->ddb[pipe]))
return 0;
@@ -4202,7 +4218,12 @@ skl_crtc_allocate_ddb(struct intel_atomic_state *state,
struct intel_crtc *crtc)
if (IS_ERR(crtc_state))
return PTR_ERR(crtc_state);
- crtc_state->wm.skl.ddb = new_dbuf_state->ddb[pipe];
+ /*
+* Used for checking overlaps, so we need absolute
+* offsets instead of MBUS relative offsets.
+*/
+ crtc_state->wm.skl.ddb.start = mbus_offset +
new_dbuf_state->ddb[pipe].start;
+ crtc_state->wm.skl.ddb.end = mbus_offset +
new_dbuf_state->ddb[pipe].end;
drm_dbg_kms(&dev_priv->drm,
"[CRTC:%d:%s] dbuf slices 0x%x -> 0x%x, ddb (%d - %d) ->
(%d - %d), active pipes 0x%x -> 0x%x\n",
@@ -6432,6 +6453,7 @@ void skl_wm_get_hw_state(struct drm_i915_private
*dev_priv)
struct intel_crtc_state *crtc_state =
to_intel_crtc_state(crtc->base.state);
enum pipe pipe = crtc->pipe;
+ unsigned int mbus_offset;
enum plane_id plane_id;
skl_pipe_wm_get_hw_state(crtc, &crtc_state->wm.skl.optimal);
@@ -6457,7 +6479,13 @@ void skl_wm_get_hw_state(struct drm_i915_private
*dev_priv)
dbuf_state->weight[pipe] = intel_crtc_ddb_weight(crtc_state);
- crtc_state->wm.skl.ddb = dbuf_state->ddb[pipe];
+ /*
+* Used for checking overlaps, so we need absolute
+* offsets instead of MBUS relative offsets.
+*/
+ mbus_offset = mbus_ddb_offset(dev_priv,
dbuf_state->slices[pipe]);
+ crtc_state->wm.skl.ddb.start = mbus_offset +
dbuf_state->ddb[pipe].start;
+ crtc_state->wm.skl.ddb.end = mbus_offset +
dbuf_state->ddb[pipe].end;
drm_dbg_kms(&dev_priv->drm,
"[CRTC:%d:%s]
[Intel-gfx] [PATCH v2 39/50] drm/i915/adl_p: Enable/disable loadgen sharing
From: Mika Kahola
Disable loadgen sharing for DP link rate 1.62 GHz and HDMI 5.94 GHz.
For all other modes, we can enable loadgen sharing feature.
BSpec: 55359
Cc: Imre Deak
Signed-off-by: Mika Kahola
Signed-off-by: Clinton Taylor
Signed-off-by: Matt Roper
---
drivers/gpu/drm/i915/display/intel_ddi.c | 8
drivers/gpu/drm/i915/i915_reg.h | 1 +
2 files changed, 9 insertions(+)
diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c
b/drivers/gpu/drm/i915/display/intel_ddi.c
index 1a5213447db1..d58f6d297a2f 100644
--- a/drivers/gpu/drm/i915/display/intel_ddi.c
+++ b/drivers/gpu/drm/i915/display/intel_ddi.c
@@ -1460,6 +1460,14 @@ tgl_dkl_phy_ddi_vswing_sequence(struct intel_encoder
*encoder,
val = intel_de_read(dev_priv, DKL_TX_DPCNTL2(tc_port));
val &= ~DKL_TX_DP20BITMODE;
intel_de_write(dev_priv, DKL_TX_DPCNTL2(tc_port), val);
+
+ if ((intel_crtc_has_dp_encoder(crtc_state) &&
+ crtc_state->port_clock == 162000) ||
+ (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI) &&
+ crtc_state->port_clock == 594000))
+ val |= DKL_TX_LOADGEN_SHARING_PMD_DISABLE;
+ else
+ val &= ~DKL_TX_LOADGEN_SHARING_PMD_DISABLE;
}
}
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index f25f68f3b2f4..393071cde6d4 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -10887,6 +10887,7 @@ enum skl_power_gate {
_DKL_TX_DPCNTL1)
#define _DKL_TX_DPCNTL20x2C8
+#define DKL_TX_LOADGEN_SHARING_PMD_DISABLEREG_BIT(12)
#define DKL_TX_DP20BITMODE(1 << 2)
#define DKL_TX_DPCNTL2(tc_port) _MMIO(_PORT(tc_port, \
_DKL_PHY1_BASE, \
--
2.25.4
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[Intel-gfx] [PATCH v2 50/50] drm/i915/display/adl_p: Implement PSR changes
From: José Roberto de Souza
Implements changes around PSR for alderlake-P:
- EDP_SU_TRACK_ENABLE was removed and bit 30 now has other function
- Some bits of PSR2_MAN_TRK_CTL moved and SF_PARTIAL_FRAME_UPDATE was
removed setting SU_REGION_START/END_ADDR will do this job
- SU_REGION_START/END_ADDR have now line granularity but will need to
be aligned with DSC when the PSRS + DSC support lands
v2:
- Don't lose EDP_PSR2_ENABLE bit in hsw_activate_psr2() (Gwan-gyeong)
BSpec: 50422
BSpec: 50424
Cc: Gwan-gyeong Mun
Cc: Anusha Srivatsa
Signed-off-by: José Roberto de Souza
Signed-off-by: Clinton Taylor
Signed-off-by: Matt Roper
---
drivers/gpu/drm/i915/display/intel_psr.c | 53 ++--
drivers/gpu/drm/i915/i915_reg.h | 26 +++-
2 files changed, 57 insertions(+), 22 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_psr.c
b/drivers/gpu/drm/i915/display/intel_psr.c
index d05f9aaa8c06..7a3e8a94450c 100644
--- a/drivers/gpu/drm/i915/display/intel_psr.c
+++ b/drivers/gpu/drm/i915/display/intel_psr.c
@@ -519,11 +519,13 @@ static u32 intel_psr2_get_tp_time(struct intel_dp
*intel_dp)
static void hsw_activate_psr2(struct intel_dp *intel_dp)
{
struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
- u32 val;
+ u32 val = EDP_PSR2_ENABLE;
+
+ val |= psr_compute_idle_frames(intel_dp) << EDP_PSR2_IDLE_FRAME_SHIFT;
- val = psr_compute_idle_frames(intel_dp) << EDP_PSR2_IDLE_FRAME_SHIFT;
+ if (!IS_ALDERLAKE_P(dev_priv))
+ val |= EDP_SU_TRACK_ENABLE;
- val |= EDP_PSR2_ENABLE | EDP_SU_TRACK_ENABLE;
if (DISPLAY_VER(dev_priv) >= 10)
val |= EDP_Y_COORDINATE_ENABLE;
@@ -1245,21 +1247,32 @@ void intel_psr2_program_trans_man_trk_ctl(const struct
intel_crtc_state *crtc_st
static void psr2_man_trk_ctl_calc(struct intel_crtc_state *crtc_state,
struct drm_rect *clip, bool full_update)
{
+ struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
+ struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
u32 val = PSR2_MAN_TRK_CTL_ENABLE;
if (full_update) {
- val |= PSR2_MAN_TRK_CTL_SF_SINGLE_FULL_FRAME;
+ if (IS_ALDERLAKE_P(dev_priv))
+ val |= ADLP_PSR2_MAN_TRK_CTL_SF_SINGLE_FULL_FRAME;
+ else
+ val |= PSR2_MAN_TRK_CTL_SF_SINGLE_FULL_FRAME;
+
goto exit;
}
if (clip->y1 == -1)
goto exit;
- drm_WARN_ON(crtc_state->uapi.crtc->dev, clip->y1 % 4 || clip->y2 % 4);
+ if (IS_ALDERLAKE_P(dev_priv)) {
+ val |= ADLP_PSR2_MAN_TRK_CTL_SU_REGION_START_ADDR(clip->y1);
+ val |= ADLP_PSR2_MAN_TRK_CTL_SU_REGION_END_ADDR(clip->y2);
+ } else {
+ drm_WARN_ON(crtc_state->uapi.crtc->dev, clip->y1 % 4 ||
clip->y2 % 4);
- val |= PSR2_MAN_TRK_CTL_SF_PARTIAL_FRAME_UPDATE;
- val |= PSR2_MAN_TRK_CTL_SU_REGION_START_ADDR(clip->y1 / 4 + 1);
- val |= PSR2_MAN_TRK_CTL_SU_REGION_END_ADDR(clip->y2 / 4 + 1);
+ val |= PSR2_MAN_TRK_CTL_SF_PARTIAL_FRAME_UPDATE;
+ val |= PSR2_MAN_TRK_CTL_SU_REGION_START_ADDR(clip->y1 / 4 + 1);
+ val |= PSR2_MAN_TRK_CTL_SU_REGION_END_ADDR(clip->y2 / 4 + 1);
+ }
exit:
crtc_state->psr2_man_track_ctl = val;
}
@@ -1280,6 +1293,25 @@ static void clip_area_update(struct drm_rect
*overlap_damage_area,
overlap_damage_area->y2 = damage_area->y2;
}
+static void intel_psr2_sel_fetch_pipe_alignment(const struct intel_crtc_state
*crtc_state,
+ struct drm_rect *pipe_clip)
+{
+ struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
+ struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
+
+ if (IS_ALDERLAKE_P(dev_priv)) {
+ /*
+* TODO: ADL-P have line granularity but when DSC is enabled it
+* needs to be aligned with DSC boundaries.
+*/
+ } else {
+ /* It must be aligned to 4 lines/1 block */
+ pipe_clip->y1 -= pipe_clip->y1 % 4;
+ if (pipe_clip->y2 % 4)
+ pipe_clip->y2 = ((pipe_clip->y2 / 4) + 1) * 4;
+ }
+}
+
int intel_psr2_sel_fetch_update(struct intel_atomic_state *state,
struct intel_crtc *crtc)
{
@@ -1388,10 +1420,7 @@ int intel_psr2_sel_fetch_update(struct
intel_atomic_state *state,
if (full_update)
goto skip_sel_fetch_set_loop;
- /* It must be aligned to 4 lines */
- pipe_clip.y1 -= pipe_clip.y1 % 4;
- if (pipe_clip.y2 % 4)
- pipe_clip.y2 = ((pipe_clip.y2 / 4) + 1) * 4;
+ intel_psr2_sel_fetch_pipe_alignment(crtc_state, &pipe_clip);
/*
* Now that we have the pipe damaged area check if it intersect with
diff
[Intel-gfx] [PATCH v2 28/50] drm/i915/adl_p: Implement TC sequences
From: José Roberto de Souza
ADL-P have basically the same TC connection and disconnection
sequences as ICL and TGL, the major difference is the new registers.
So here adding functions without the icl prefix in the name and
making the new functions call the platform specific function to access
the correct register.
BSpec: 55480
Cc: Imre Deak
Signed-off-by: José Roberto de Souza
Signed-off-by: Clinton Taylor
Signed-off-by: Matt Roper
---
drivers/gpu/drm/i915/display/intel_tc.c | 132 ++--
drivers/gpu/drm/i915/i915_reg.h | 10 ++
2 files changed, 131 insertions(+), 11 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_tc.c
b/drivers/gpu/drm/i915/display/intel_tc.c
index c007803cfd30..7bae0193aa0f 100644
--- a/drivers/gpu/drm/i915/display/intel_tc.c
+++ b/drivers/gpu/drm/i915/display/intel_tc.c
@@ -205,7 +205,7 @@ static void tc_port_fixup_legacy_flag(struct
intel_digital_port *dig_port,
dig_port->tc_legacy_port = !dig_port->tc_legacy_port;
}
-static u32 tc_port_live_status_mask(struct intel_digital_port *dig_port)
+static u32 icl_tc_port_live_status_mask(struct intel_digital_port *dig_port)
{
struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
struct intel_uncore *uncore = &i915->uncore;
@@ -238,6 +238,40 @@ static u32 tc_port_live_status_mask(struct
intel_digital_port *dig_port)
return mask;
}
+static u32 adl_tc_port_live_status_mask(struct intel_digital_port *dig_port)
+{
+ struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
+ enum tc_port tc_port = intel_port_to_tc(i915, dig_port->base.port);
+ u32 isr_bit = i915->hotplug.pch_hpd[dig_port->base.hpd_pin];
+ struct intel_uncore *uncore = &i915->uncore;
+ u32 val, mask = 0;
+
+ val = intel_uncore_read(uncore, TCSS_DDI_STATUS(tc_port));
+ if (val & TCSS_DDI_STATUS_HPD_LIVE_STATUS_ALT)
+ mask |= BIT(TC_PORT_DP_ALT);
+ if (val & TCSS_DDI_STATUS_HPD_LIVE_STATUS_TBT)
+ mask |= BIT(TC_PORT_TBT_ALT);
+
+ if (intel_uncore_read(uncore, SDEISR) & isr_bit)
+ mask |= BIT(TC_PORT_LEGACY);
+
+ /* The sink can be connected only in a single mode. */
+ if (!drm_WARN_ON(&i915->drm, hweight32(mask) > 1))
+ tc_port_fixup_legacy_flag(dig_port, mask);
+
+ return mask;
+}
+
+static u32 tc_port_live_status_mask(struct intel_digital_port *dig_port)
+{
+ struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
+
+ if (IS_ALDERLAKE_P(i915))
+ return adl_tc_port_live_status_mask(dig_port);
+
+ return icl_tc_port_live_status_mask(dig_port);
+}
+
static bool icl_tc_phy_status_complete(struct intel_digital_port *dig_port)
{
struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
@@ -256,6 +290,33 @@ static bool icl_tc_phy_status_complete(struct
intel_digital_port *dig_port)
return val & DP_PHY_MODE_STATUS_COMPLETED(dig_port->tc_phy_fia_idx);
}
+static bool adl_tc_phy_status_complete(struct intel_digital_port *dig_port)
+{
+ struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
+ struct intel_uncore *uncore = &i915->uncore;
+ u32 val;
+
+ val = intel_uncore_read(uncore,
TCSS_DDI_STATUS(dig_port->tc_phy_fia_idx));
+ if (val == 0x) {
+ drm_dbg_kms(&i915->drm,
+ "Port %s: PHY in TCCOLD, assuming not complete\n",
+ dig_port->tc_port_name);
+ return false;
+ }
+
+ return val & TCSS_DDI_STATUS_READY;
+}
+
+static bool tc_phy_status_complete(struct intel_digital_port *dig_port)
+{
+ struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
+
+ if (IS_ALDERLAKE_P(i915))
+ return adl_tc_phy_status_complete(dig_port);
+
+ return icl_tc_phy_status_complete(dig_port);
+}
+
static bool icl_tc_phy_take_ownership(struct intel_digital_port *dig_port,
bool take)
{
@@ -280,7 +341,7 @@ static bool icl_tc_phy_take_ownership(struct
intel_digital_port *dig_port,
intel_uncore_write(uncore,
PORT_TX_DFLEXDPCSSS(dig_port->tc_phy_fia), val);
- if (!take && wait_for(!icl_tc_phy_status_complete(dig_port), 10))
+ if (!take && wait_for(!tc_phy_status_complete(dig_port), 10))
drm_dbg_kms(&i915->drm,
"Port %s: PHY complete clear timed out\n",
dig_port->tc_port_name);
@@ -288,6 +349,34 @@ static bool icl_tc_phy_take_ownership(struct
intel_digital_port *dig_port,
return true;
}
+static bool adl_tc_phy_take_ownership(struct intel_digital_port *dig_port,
+ bool take)
+{
+ struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
+ struct intel_uncore *uncore = &i915->uncore;
+ enum port port = dig_port
[Intel-gfx] [PATCH v2 33/50] drm/i915: Move intel_modeset_all_pipes()
From: Ville Syrjälä
Move intel_modeset_all_pipes() to a central place so that we can
use it elsewhere as well. No functional changes.
Cc: Stanislav Lisovskiy
Signed-off-by: Ville Syrjälä
Signed-off-by: Clinton Taylor
Signed-off-by: Matt Roper
---
drivers/gpu/drm/i915/display/intel_cdclk.c | 38
drivers/gpu/drm/i915/display/intel_display.c | 38
drivers/gpu/drm/i915/display/intel_display.h | 1 +
3 files changed, 39 insertions(+), 38 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c
b/drivers/gpu/drm/i915/display/intel_cdclk.c
index 85da8c43d5d6..4c441b359d7f 100644
--- a/drivers/gpu/drm/i915/display/intel_cdclk.c
+++ b/drivers/gpu/drm/i915/display/intel_cdclk.c
@@ -2410,44 +2410,6 @@ static int bxt_modeset_calc_cdclk(struct
intel_cdclk_state *cdclk_state)
return 0;
}
-static int intel_modeset_all_pipes(struct intel_atomic_state *state)
-{
- struct drm_i915_private *dev_priv = to_i915(state->base.dev);
- struct intel_crtc *crtc;
-
- /*
-* Add all pipes to the state, and force
-* a modeset on all the active ones.
-*/
- for_each_intel_crtc(&dev_priv->drm, crtc) {
- struct intel_crtc_state *crtc_state;
- int ret;
-
- crtc_state = intel_atomic_get_crtc_state(&state->base, crtc);
- if (IS_ERR(crtc_state))
- return PTR_ERR(crtc_state);
-
- if (!crtc_state->hw.active ||
- drm_atomic_crtc_needs_modeset(&crtc_state->uapi))
- continue;
-
- crtc_state->uapi.mode_changed = true;
-
- ret = drm_atomic_add_affected_connectors(&state->base,
-&crtc->base);
- if (ret)
- return ret;
-
- ret = intel_atomic_add_affected_planes(state, crtc);
- if (ret)
- return ret;
-
- crtc_state->update_planes |= crtc_state->active_planes;
- }
-
- return 0;
-}
-
static int fixed_modeset_calc_cdclk(struct intel_cdclk_state *cdclk_state)
{
int min_cdclk;
diff --git a/drivers/gpu/drm/i915/display/intel_display.c
b/drivers/gpu/drm/i915/display/intel_display.c
index 265518bc197e..33cdc419c627 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -9598,6 +9598,44 @@ intel_modeset_verify_disabled(struct drm_i915_private
*dev_priv,
verify_disabled_dpll_state(dev_priv);
}
+int intel_modeset_all_pipes(struct intel_atomic_state *state)
+{
+ struct drm_i915_private *dev_priv = to_i915(state->base.dev);
+ struct intel_crtc *crtc;
+
+ /*
+* Add all pipes to the state, and force
+* a modeset on all the active ones.
+*/
+ for_each_intel_crtc(&dev_priv->drm, crtc) {
+ struct intel_crtc_state *crtc_state;
+ int ret;
+
+ crtc_state = intel_atomic_get_crtc_state(&state->base, crtc);
+ if (IS_ERR(crtc_state))
+ return PTR_ERR(crtc_state);
+
+ if (!crtc_state->hw.active ||
+ drm_atomic_crtc_needs_modeset(&crtc_state->uapi))
+ continue;
+
+ crtc_state->uapi.mode_changed = true;
+
+ ret = drm_atomic_add_affected_connectors(&state->base,
+&crtc->base);
+ if (ret)
+ return ret;
+
+ ret = intel_atomic_add_affected_planes(state, crtc);
+ if (ret)
+ return ret;
+
+ crtc_state->update_planes |= crtc_state->active_planes;
+ }
+
+ return 0;
+}
+
static void
intel_crtc_update_active_timings(const struct intel_crtc_state *crtc_state)
{
diff --git a/drivers/gpu/drm/i915/display/intel_display.h
b/drivers/gpu/drm/i915/display/intel_display.h
index 5b19953840aa..11eb0f02bee3 100644
--- a/drivers/gpu/drm/i915/display/intel_display.h
+++ b/drivers/gpu/drm/i915/display/intel_display.h
@@ -670,6 +670,7 @@ void intel_modeset_driver_remove_noirq(struct
drm_i915_private *i915);
void intel_modeset_driver_remove_nogem(struct drm_i915_private *i915);
void intel_display_resume(struct drm_device *dev);
void intel_init_pch_refclk(struct drm_i915_private *dev_priv);
+int intel_modeset_all_pipes(struct intel_atomic_state *state);
/* modesetting asserts */
void assert_panel_unlocked(struct drm_i915_private *dev_priv,
--
2.25.4
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[Intel-gfx] [PATCH v2 46/50] drm/i915/adl_p: Implement Wa_22011091694
From: José Roberto de Souza
Adding a new hook to ADL-P just to avoid another platform check in
gen12lp_init_clock_gating() but also open to it.
BSpec: 54369
Cc: Matt Roper
Cc: Anusha Srivatsa
Signed-off-by: José Roberto de Souza
Signed-off-by: Clinton Taylor
Signed-off-by: Matt Roper
---
drivers/gpu/drm/i915/i915_reg.h | 3 +++
drivers/gpu/drm/i915/intel_pm.c | 12 +++-
2 files changed, 14 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 624253118efb..64bbb8cf4b8e 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -4179,6 +4179,9 @@ enum {
#define GEN9_CLKGATE_DIS_4 _MMIO(0x4653C)
#define BXT_GMBUS_GATING_DIS (1 << 14)
+#define GEN9_CLKGATE_DIS_5 _MMIO(0x46540)
+#define DPCE_GATING_DIS REG_BIT(17)
+
#define _CLKGATE_DIS_PSL_A 0x46520
#define _CLKGATE_DIS_PSL_B 0x46524
#define _CLKGATE_DIS_PSL_C 0x46528
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index b22af4774ef0..c6b9904ef7c8 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -7383,6 +7383,14 @@ static void gen12lp_init_clock_gating(struct
drm_i915_private *dev_priv)
0, DFR_DISABLE);
}
+static void adlp_init_clock_gating(struct drm_i915_private *dev_priv)
+{
+ gen12lp_init_clock_gating(dev_priv);
+
+ /* Wa_22011091694:adlp */
+ intel_de_rmw(dev_priv, GEN9_CLKGATE_DIS_5, 0, DPCE_GATING_DIS);
+}
+
static void dg1_init_clock_gating(struct drm_i915_private *dev_priv)
{
gen12lp_init_clock_gating(dev_priv);
@@ -7860,7 +7868,9 @@ static void nop_init_clock_gating(struct drm_i915_private
*dev_priv)
*/
void intel_init_clock_gating_hooks(struct drm_i915_private *dev_priv)
{
- if (IS_DG1(dev_priv))
+ if (IS_ALDERLAKE_P(dev_priv))
+ dev_priv->display.init_clock_gating = adlp_init_clock_gating;
+ else if (IS_DG1(dev_priv))
dev_priv->display.init_clock_gating = dg1_init_clock_gating;
else if (IS_GEN(dev_priv, 12))
dev_priv->display.init_clock_gating = gen12lp_init_clock_gating;
--
2.25.4
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[Intel-gfx] [PATCH v2 42/50] drm/i915/bigjoiner: Avoid dsc_compute_config for uncompressed bigjoiner
From: Animesh Manna
For uncompressed big joiner DSC engine will not be used so will avoid
compute config of DSC.
Cc: Manasi Navare
Signed-off-by: Animesh Manna
Signed-off-by: Clinton Taylor
Signed-off-by: Matt Roper
---
drivers/gpu/drm/i915/display/intel_dp.c | 8 ++--
1 file changed, 6 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c
b/drivers/gpu/drm/i915/display/intel_dp.c
index ab9b36a14809..9a661ed06ee5 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -1418,9 +1418,13 @@ intel_dp_compute_link_config(struct intel_encoder
*encoder,
/* Optimize for slow and wide. */
ret = intel_dp_compute_link_config_wide(intel_dp, pipe_config,
&limits);
- /* enable compression if the mode doesn't fit available BW */
+ /*
+* Pipe joiner needs compression upto display12 due to BW limitation.
DG2
+* onwards pipe joiner can be enabled without compression.
+*/
drm_dbg_kms(&i915->drm, "Force DSC en = %d\n", intel_dp->force_dsc_en);
- if (ret || intel_dp->force_dsc_en || pipe_config->bigjoiner) {
+ if (ret || intel_dp->force_dsc_en || (!(DISPLAY_VER(i915) == 13) &&
+ pipe_config->bigjoiner)) {
ret = intel_dp_dsc_compute_config(intel_dp, pipe_config,
conn_state, &limits);
if (ret < 0)
--
2.25.4
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[Intel-gfx] [PATCH v2 44/50] drm/i915/adlp: Add PIPE_MISC2 programming
From: Anusha Srivatsa
When scalers are enabled, we need to program underrun
bubble counter to 0x50 to avoid Soft Pipe A underruns.
Make sure other bits dont get overwritten.
Cc: Matt Roper
Cc: Clint Taylor
Cc: José Roberto de Souza
Signed-off-by: Anusha Srivatsa
Signed-off-by: Clinton Taylor
Signed-off-by: Matt Roper
---
drivers/gpu/drm/i915/display/intel_display.c | 21
drivers/gpu/drm/i915/i915_reg.h | 7 +++
2 files changed, 28 insertions(+)
diff --git a/drivers/gpu/drm/i915/display/intel_display.c
b/drivers/gpu/drm/i915/display/intel_display.c
index 6543db5e1c6c..7c9271585fcb 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -6249,8 +6249,12 @@ static void hsw_set_pipeconf(const struct
intel_crtc_state *crtc_state)
static void bdw_set_pipemisc(const struct intel_crtc_state *crtc_state)
{
struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
+const struct intel_crtc_scaler_state *scaler_state =
+&crtc_state->scaler_state;
+
struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
u32 val = 0;
+ int i;
switch (crtc_state->pipe_bpp) {
case 18:
@@ -6289,6 +6293,23 @@ static void bdw_set_pipemisc(const struct
intel_crtc_state *crtc_state)
if (DISPLAY_VER(dev_priv) >= 12)
val |= PIPEMISC_PIXEL_ROUNDING_TRUNC;
+ if (IS_ALDERLAKE_P(dev_priv)) {
+ bool scaler_in_use = false;
+
+ for (i = 0; i < crtc->num_scalers; i++) {
+ if (!scaler_state->scalers[i].in_use)
+ continue;
+
+ scaler_in_use = true;
+ break;
+ }
+
+ intel_de_rmw(dev_priv, PIPE_MISC2(crtc->pipe),
+PIPE_MISC2_UNDERRUN_BUBBLE_COUNTER_MASK,
+scaler_in_use ?
PIPE_MISC2_BUBBLE_COUNTER_SCALER_EN :
+
PIPE_MISC2_BUBBLE_COUNTER_SCALER_DIS);
+ }
+
intel_de_write(dev_priv, PIPEMISC(crtc->pipe), val);
}
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 552a1a146d8d..624253118efb 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -6155,6 +6155,13 @@ enum {
#define PIPEMISC_DITHER_TYPE_SP (0 << 2)
#define PIPEMISC(pipe) _MMIO_PIPE2(pipe, _PIPE_MISC_A)
+#define _PIPE_MISC2_A 0x7002C
+#define _PIPE_MISC2_B 0x7102C
+#define PIPE_MISC2_BUBBLE_COUNTER_SCALER_EN (0x50 << 24)
+#define PIPE_MISC2_BUBBLE_COUNTER_SCALER_DIS (0x14 << 24)
+#define PIPE_MISC2_UNDERRUN_BUBBLE_COUNTER_MASK (0xff << 24)
+#define PIPE_MISC2(pipe)
_MMIO_PIPE2(pipe, _PIPE_MISC2_A)
+
/* Skylake+ pipe bottom (background) color */
#define _SKL_BOTTOM_COLOR_A0x70034
#define SKL_BOTTOM_COLOR_GAMMA_ENABLE(1 << 31)
--
2.25.4
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[Intel-gfx] [PATCH v2 40/50] drm/i915/adl_p: Add PLL Support
From: Anusha Srivatsa
The clocks in ALD_P is similar to that of TGL.
The combo PLLs use the same DPLL0, DPLL1 and TBT_PLL.
This patch adds the helper function intel_mg_pll_enable_reg()
which is similar to intel_combo_pll_enable_reg() for being lookup
place for PLL_ENABLE register in combo phy cases.
Bspec: 55409,55316
Cc: Matt Roper
Cc: Clinton Taylor
Cc: Lucas De Marchi
Cc: José Roberto de Souza
Signed-off-by: Anusha Srivatsa
Signed-off-by: Clinton Taylor
Signed-off-by: Matt Roper
---
drivers/gpu/drm/i915/display/intel_dpll_mgr.c | 69 ++-
drivers/gpu/drm/i915/i915_reg.h | 8 +++
2 files changed, 60 insertions(+), 17 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
index 268ecf1c000f..618c61d4d3b6 100644
--- a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
+++ b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
@@ -147,6 +147,16 @@ void assert_shared_dpll(struct drm_i915_private *dev_priv,
pll->info->name, onoff(state), onoff(cur_state));
}
+static enum tc_port icl_pll_id_to_tc_port(enum intel_dpll_id id)
+{
+ return TC_PORT_1 + id - DPLL_ID_ICL_MGPLL1;
+}
+
+enum intel_dpll_id icl_tc_port_to_pll_id(enum tc_port tc_port)
+{
+ return tc_port - TC_PORT_1 + DPLL_ID_ICL_MGPLL1;
+}
+
static i915_reg_t
intel_combo_pll_enable_reg(struct drm_i915_private *i915,
struct intel_shared_dpll *pll)
@@ -159,6 +169,19 @@ intel_combo_pll_enable_reg(struct drm_i915_private *i915,
return CNL_DPLL_ENABLE(pll->info->id);
}
+static i915_reg_t
+intel_tc_pll_enable_reg(struct drm_i915_private *i915,
+ struct intel_shared_dpll *pll)
+{
+ const enum intel_dpll_id id = pll->info->id;
+ enum tc_port tc_port = icl_pll_id_to_tc_port(id);
+
+ if (IS_ALDERLAKE_P(i915))
+ return ADLP_PORTTC_PLL_ENABLE(tc_port);
+
+ return MG_PLL_ENABLE(tc_port);
+}
+
/**
* intel_prepare_shared_dpll - call a dpll's prepare hook
* @crtc_state: CRTC, and its state, which has a shared dpll
@@ -3118,16 +3141,6 @@ static void icl_calc_dpll_state(struct drm_i915_private
*i915,
pll_state->cfgcr1 |= DPLL_CFGCR1_CENTRAL_FREQ_8400;
}
-static enum tc_port icl_pll_id_to_tc_port(enum intel_dpll_id id)
-{
- return id - DPLL_ID_ICL_MGPLL1;
-}
-
-enum intel_dpll_id icl_tc_port_to_pll_id(enum tc_port tc_port)
-{
- return tc_port + DPLL_ID_ICL_MGPLL1;
-}
-
static bool icl_mg_pll_find_divisors(int clock_khz, bool is_dp, bool use_ssc,
u32 *target_dco_khz,
struct intel_dpll_hw_state *state,
@@ -3726,12 +3739,14 @@ static bool mg_pll_get_hw_state(struct drm_i915_private
*dev_priv,
bool ret = false;
u32 val;
+ i915_reg_t enable_reg = intel_tc_pll_enable_reg(dev_priv, pll);
+
wakeref = intel_display_power_get_if_enabled(dev_priv,
POWER_DOMAIN_DISPLAY_CORE);
if (!wakeref)
return false;
- val = intel_de_read(dev_priv, MG_PLL_ENABLE(tc_port));
+ val = intel_de_read(dev_priv, enable_reg);
if (!(val & PLL_ENABLE))
goto out;
@@ -3795,7 +3810,7 @@ static bool dkl_pll_get_hw_state(struct drm_i915_private
*dev_priv,
if (!wakeref)
return false;
- val = intel_de_read(dev_priv, MG_PLL_ENABLE(tc_port));
+ val = intel_de_read(dev_priv, intel_tc_pll_enable_reg(dev_priv, pll));
if (!(val & PLL_ENABLE))
goto out;
@@ -4167,8 +4182,7 @@ static void tbt_pll_enable(struct drm_i915_private
*dev_priv,
static void mg_pll_enable(struct drm_i915_private *dev_priv,
struct intel_shared_dpll *pll)
{
- i915_reg_t enable_reg =
- MG_PLL_ENABLE(icl_pll_id_to_tc_port(pll->info->id));
+ i915_reg_t enable_reg = intel_tc_pll_enable_reg(dev_priv, pll);
icl_pll_power_enable(dev_priv, pll, enable_reg);
@@ -4247,8 +4261,7 @@ static void tbt_pll_disable(struct drm_i915_private
*dev_priv,
static void mg_pll_disable(struct drm_i915_private *dev_priv,
struct intel_shared_dpll *pll)
{
- i915_reg_t enable_reg =
- MG_PLL_ENABLE(icl_pll_id_to_tc_port(pll->info->id));
+ i915_reg_t enable_reg = intel_tc_pll_enable_reg(dev_priv, pll);
icl_pll_disable(dev_priv, pll, enable_reg);
}
@@ -4414,6 +4427,26 @@ static const struct intel_dpll_mgr adls_pll_mgr = {
.dump_hw_state = icl_dump_hw_state,
};
+static const struct dpll_info adlp_plls[] = {
+ { "DPLL 0", &combo_pll_funcs, DPLL_ID_ICL_DPLL0, 0 },
+ { "DPLL 1", &combo_pll_funcs, DPLL_ID_ICL_DPLL1, 0 },
+ { "TBT PLL", &tbt_pll_funcs, DPLL_ID_ICL_TBTPLL, 0 },
+ { "TC PLL 1", &dkl_pll_funcs, DPLL_ID_ICL_MGPLL1, 0 },
+ { "TC PLL 2", &dkl_pll_funcs,
[Intel-gfx] [PATCH v2 29/50] drm/i915/adl_p: Enable modular fia
From: José Roberto de Souza
Alderlake P have modular FIA like TGL but it is always modular in all
skus, not like TGL that we had to read a register to check if it is
monolithic or modular.
BSpec: 55480
BSpec: 50572
Cc: Imre Deak
Signed-off-by: José Roberto de Souza
Signed-off-by: Clinton Taylor
Signed-off-by: Matt Roper
---
drivers/gpu/drm/i915/display/intel_tc.c | 4
drivers/gpu/drm/i915/i915_pci.c | 1 +
2 files changed, 5 insertions(+)
diff --git a/drivers/gpu/drm/i915/display/intel_tc.c
b/drivers/gpu/drm/i915/display/intel_tc.c
index 7bae0193aa0f..8f60a94852f3 100644
--- a/drivers/gpu/drm/i915/display/intel_tc.c
+++ b/drivers/gpu/drm/i915/display/intel_tc.c
@@ -734,6 +734,10 @@ tc_has_modular_fia(struct drm_i915_private *i915, struct
intel_digital_port *dig
if (!INTEL_INFO(i915)->display.has_modular_fia)
return false;
+ /* TODO: check if in real HW MODULAR_FIA_MASK is set, if so remove this
block */
+ if (IS_ALDERLAKE_P(i915))
+ return true;
+
wakeref = tc_cold_block(dig_port);
val = intel_uncore_read(&i915->uncore, PORT_TX_DFLEXDPSP(FIA1));
tc_cold_unblock(dig_port, wakeref);
diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
index 1ceb3cd4068d..39cbfdf7c50e 100644
--- a/drivers/gpu/drm/i915/i915_pci.c
+++ b/drivers/gpu/drm/i915/i915_pci.c
@@ -951,6 +951,7 @@ static const struct intel_device_info adl_p_info = {
XE_LPD_FEATURES,
PLATFORM(INTEL_ALDERLAKE_P),
.require_force_probe = 1,
+ .display.has_modular_fia = 1,
.platform_engine_mask =
BIT(RCS0) | BIT(BCS0) | BIT(VECS0) | BIT(VCS0) | BIT(VCS2),
.ppgtt_size = 48,
--
2.25.4
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[Intel-gfx] [PATCH v2 49/50] drm/i915/perf: Enable OA formats for ADL_P
From: Umesh Nerlige Ramappa Enable relevant OA formats for ADL_P. Cc: Ashutosh Dixit Signed-off-by: Umesh Nerlige Ramappa Signed-off-by: Clinton Taylor Signed-off-by: Matt Roper Reviewed-by: Ashutosh Dixit --- drivers/gpu/drm/i915/i915_perf.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/gpu/drm/i915/i915_perf.c b/drivers/gpu/drm/i915/i915_perf.c index 85ad62dbabfa..de8ebc34af0f 100644 --- a/drivers/gpu/drm/i915/i915_perf.c +++ b/drivers/gpu/drm/i915/i915_perf.c @@ -4318,6 +4318,7 @@ static void oa_init_supported_formats(struct i915_perf *perf) case INTEL_ROCKETLAKE: case INTEL_DG1: case INTEL_ALDERLAKE_S: + case INTEL_ALDERLAKE_P: oa_format_add(perf, I915_OA_FORMAT_A12); oa_format_add(perf, I915_OA_FORMAT_A12_B8_C8); oa_format_add(perf, I915_OA_FORMAT_A32u40_A4u32_B8_C8); -- 2.25.4 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH v2 35/50] drm/i915/adl_p: Tx escape clock with DSI
From: Mika Kahola
Today when the DSI controller is paired with the Combo-PHY it
uses the high-speed (HS) Word clock for its low power (LP)
transmit PPI communication to the DPHY. The interface signaling
only changes state at an Escape clock frequency (i.e. its
effectively running on a virtual Tx Escape clock that is controlled
by counters w/in the controller), but all the interface flops are
running off the HS clock.
This has the following drawbacks:
* It is a deviation from the PPI spec which assumes signaling is
running on a physical Escape clock
* The PV timings are over constrained (HS timed to 312.5MHz vs.
an Escape clock of 20MHz max)
This feature is proposing to change the LP Tx communication between
the controller and the DPHY from a virtual Tx Escape clock to a physical
clock.
To do this we need to program two "M" divisors. One for the usual
DSI_ESC_CLK_DIV and DPHY_ESC_CLK_DIV register and one for MIPIO_DWORD8.
For DSI_ESC_CLK_DIV and DPHY_ESC_CLK_DIV registers the "M" is calculated
as following
Nt = ceil(f_link/160) (theoretical word clock)
Nact = max[3, Nt + (Nt + 1)%2] (actual word clock)
M = Nact * 8
For MIPIO_DWORD8 register, the divisor "M" is calculated as following
M = (Nact - 1)/2
BSpec: 55171
Cc: Vandita Kulkarni
Signed-off-by: Mika Kahola
Signed-off-by: Clinton Taylor
Signed-off-by: Matt Roper
---
drivers/gpu/drm/i915/display/icl_dsi.c | 21 +++--
drivers/gpu/drm/i915/i915_reg.h| 6 ++
2 files changed, 25 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/icl_dsi.c
b/drivers/gpu/drm/i915/display/icl_dsi.c
index 9282978060b0..661b7f9dd031 100644
--- a/drivers/gpu/drm/i915/display/icl_dsi.c
+++ b/drivers/gpu/drm/i915/display/icl_dsi.c
@@ -361,10 +361,19 @@ static void gen11_dsi_program_esc_clk_div(struct
intel_encoder *encoder,
struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);
enum port port;
int afe_clk_khz;
- u32 esc_clk_div_m;
+ int theo_word_clk, act_word_clk;
+ u32 esc_clk_div_m, esc_clk_div_m_phy;
afe_clk_khz = afe_clk(encoder, crtc_state);
- esc_clk_div_m = DIV_ROUND_UP(afe_clk_khz, DSI_MAX_ESC_CLK);
+
+ if (IS_ALDERLAKE_S(dev_priv) || IS_ALDERLAKE_P(dev_priv)) {
+ theo_word_clk = DIV_ROUND_UP(afe_clk_khz, 8 * DSI_MAX_ESC_CLK);
+ act_word_clk = max(3, theo_word_clk + (theo_word_clk + 1) % 2);
+ esc_clk_div_m = act_word_clk * 8;
+ esc_clk_div_m_phy = (act_word_clk - 1)/2;
+ } else {
+ esc_clk_div_m = DIV_ROUND_UP(afe_clk_khz, DSI_MAX_ESC_CLK);
+ }
for_each_dsi_port(port, intel_dsi->ports) {
intel_de_write(dev_priv, ICL_DSI_ESC_CLK_DIV(port),
@@ -377,6 +386,14 @@ static void gen11_dsi_program_esc_clk_div(struct
intel_encoder *encoder,
esc_clk_div_m & ICL_ESC_CLK_DIV_MASK);
intel_de_posting_read(dev_priv, ICL_DPHY_ESC_CLK_DIV(port));
}
+
+ if (IS_ALDERLAKE_S(dev_priv) || IS_ALDERLAKE_P(dev_priv)) {
+ for_each_dsi_port(port, intel_dsi->ports) {
+ intel_de_write(dev_priv, ADL_MIPIO_DW(port, 8),
+ esc_clk_div_m_phy & TX_ESC_CLK_DIV_PHY);
+ intel_de_posting_read(dev_priv, ADL_MIPIO_DW(port, 8));
+ }
+ }
}
static void get_dsi_io_power_domains(struct drm_i915_private *dev_priv,
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 8e24be53b63f..f25f68f3b2f4 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -11326,6 +11326,12 @@ enum skl_power_gate {
#define ICL_ESC_CLK_DIV_SHIFT 0
#define DSI_MAX_ESC_CLK2 /* in KHz */
+#define _ADL_MIPIO_REG 0x180
+#define ADL_MIPIO_DW(port, dw) _MMIO(_ICL_COMBOPHY(port) +
_ADL_MIPIO_REG + 4 * (dw))
+#define TX_ESC_CLK_DIV_PHY_SEL REGBIT(16)
+#define TX_ESC_CLK_DIV_PHY_MASK REG_GENMASK(23, 16)
+#define TX_ESC_CLK_DIV_PHY REG_FIELD_PREP(TX_ESC_CLK_DIV_PHY_MASK,
0x7f)
+
#define _DSI_CMD_FRMCTL_0 0x6b034
#define _DSI_CMD_FRMCTL_1 0x6b834
#define DSI_CMD_FRMCTL(port) _MMIO_PORT(port,\
--
2.25.4
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[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for series starting with [1/2] drm/i915: add gem/gt TODO
== Series Details == Series: series starting with [1/2] drm/i915: add gem/gt TODO URL : https://patchwork.freedesktop.org/series/88413/ State : warning == Summary == $ dim checkpatch origin/drm-tip 591bc42605c7 drm/i915: add gem/gt TODO -:41: WARNING:FILE_PATH_CHANGES: added, moved or deleted file(s), does MAINTAINERS need updating? #41: new file mode 100644 -:86: WARNING:FROM_SIGN_OFF_MISMATCH: From:/Signed-off-by: email address mismatch: 'From: Daniel Vetter ' != 'Signed-off-by: Daniel Vetter ' total: 0 errors, 2 warnings, 0 checks, 41 lines checked c20d16dd7b3d drm/doc: Add RFC section -:37: WARNING:FILE_PATH_CHANGES: added, moved or deleted file(s), does MAINTAINERS need updating? #37: new file mode 100644 -:42: WARNING:SPDX_LICENSE_TAG: Missing or malformed SPDX-License-Identifier tag in line 1 #42: FILE: Documentation/gpu/rfc.rst:1: +=== -:58: WARNING:FROM_SIGN_OFF_MISMATCH: From:/Signed-off-by: email address mismatch: 'From: Daniel Vetter ' != 'Signed-off-by: Daniel Vetter ' total: 0 errors, 3 warnings, 0 checks, 24 lines checked ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✗ Fi.CI.DOCS: warning for series starting with [1/2] drm/i915: add gem/gt TODO
== Series Details == Series: series starting with [1/2] drm/i915: add gem/gt TODO URL : https://patchwork.freedesktop.org/series/88413/ State : warning == Summary == $ make htmldocs 2>&1 > /dev/null | grep i915 ./drivers/gpu/drm/i915/gem/i915_gem_shrinker.c:102: warning: Function parameter or member 'ww' not described in 'i915_gem_shrink' ./drivers/gpu/drm/i915/i915_cmd_parser.c:1420: warning: Excess function parameter 'trampoline' description in 'intel_engine_cmd_parser' ./drivers/gpu/drm/i915/i915_cmd_parser.c:1420: warning: Function parameter or member 'jump_whitelist' not described in 'intel_engine_cmd_parser' ./drivers/gpu/drm/i915/i915_cmd_parser.c:1420: warning: Function parameter or member 'shadow_map' not described in 'intel_engine_cmd_parser' ./drivers/gpu/drm/i915/i915_cmd_parser.c:1420: warning: Function parameter or member 'batch_map' not described in 'intel_engine_cmd_parser' ./drivers/gpu/drm/i915/i915_cmd_parser.c:1420: warning: Excess function parameter 'trampoline' description in 'intel_engine_cmd_parser' /home/cidrm/kernel/Documentation/gpu/i915:22: ./drivers/gpu/drm/i915/intel_runtime_pm.c:423: WARNING: Inline strong start-string without end-string. ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✓ Fi.CI.BAT: success for series starting with [1/2] drm/i915: add gem/gt TODO
== Series Details ==
Series: series starting with [1/2] drm/i915: add gem/gt TODO
URL : https://patchwork.freedesktop.org/series/88413/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_9895 -> Patchwork_19850
Summary
---
**SUCCESS**
No regressions found.
External URL:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19850/index.html
Possible new issues
---
Here are the unknown changes that may have been introduced in Patchwork_19850:
### IGT changes ###
Suppressed
The following results come from untrusted machines, tests, or statuses.
They do not affect the overall result.
* igt@i915_selftest@live@hangcheck:
- {fi-hsw-gt1}: [PASS][1] -> [DMESG-WARN][2]
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9895/fi-hsw-gt1/igt@i915_selftest@l...@hangcheck.html
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19850/fi-hsw-gt1/igt@i915_selftest@l...@hangcheck.html
Known issues
Here are the changes found in Patchwork_19850 that come from known issues:
### IGT changes ###
Issues hit
* igt@gem_exec_fence@basic-busy@bcs0:
- fi-kbl-soraka: NOTRUN -> [SKIP][3] ([fdo#109271]) +24 similar issues
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19850/fi-kbl-soraka/igt@gem_exec_fence@basic-b...@bcs0.html
* igt@gem_huc_copy@huc-copy:
- fi-kbl-soraka: NOTRUN -> [SKIP][4] ([fdo#109271] / [i915#2190])
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19850/fi-kbl-soraka/igt@gem_huc_c...@huc-copy.html
* igt@i915_selftest@live@execlists:
- fi-bsw-kefka: [PASS][5] -> [INCOMPLETE][6] ([i915#2782] /
[i915#2940])
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9895/fi-bsw-kefka/igt@i915_selftest@l...@execlists.html
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19850/fi-bsw-kefka/igt@i915_selftest@l...@execlists.html
* igt@i915_selftest@live@gt_pm:
- fi-kbl-soraka: NOTRUN -> [DMESG-FAIL][7] ([i915#1886] / [i915#2291])
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19850/fi-kbl-soraka/igt@i915_selftest@live@gt_pm.html
* igt@i915_selftest@live@late_gt_pm:
- fi-bsw-nick:[PASS][8] -> [DMESG-FAIL][9] ([i915#2927])
[8]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9895/fi-bsw-nick/igt@i915_selftest@live@late_gt_pm.html
[9]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19850/fi-bsw-nick/igt@i915_selftest@live@late_gt_pm.html
* igt@kms_chamelium@common-hpd-after-suspend:
- fi-kbl-soraka: NOTRUN -> [SKIP][10] ([fdo#109271] / [fdo#111827]) +8
similar issues
[10]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19850/fi-kbl-soraka/igt@kms_chamel...@common-hpd-after-suspend.html
* igt@kms_pipe_crc_basic@compare-crc-sanitycheck-pipe-d:
- fi-kbl-soraka: NOTRUN -> [SKIP][11] ([fdo#109271] / [i915#533])
[11]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19850/fi-kbl-soraka/igt@kms_pipe_crc_ba...@compare-crc-sanitycheck-pipe-d.html
* igt@runner@aborted:
- fi-bsw-kefka: NOTRUN -> [FAIL][12] ([i915#1436])
[12]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19850/fi-bsw-kefka/igt@run...@aborted.html
- fi-bsw-nick:NOTRUN -> [FAIL][13] ([i915#1436])
[13]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19850/fi-bsw-nick/igt@run...@aborted.html
* igt@vgem_basic@setversion:
- fi-tgl-y: [PASS][14] -> [DMESG-WARN][15] ([i915#402]) +2
similar issues
[14]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9895/fi-tgl-y/igt@vgem_ba...@setversion.html
[15]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19850/fi-tgl-y/igt@vgem_ba...@setversion.html
Possible fixes
* igt@gem_exec_suspend@basic-s3:
- fi-tgl-y: [DMESG-WARN][16] ([i915#2411] / [i915#402]) ->
[PASS][17]
[16]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9895/fi-tgl-y/igt@gem_exec_susp...@basic-s3.html
[17]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19850/fi-tgl-y/igt@gem_exec_susp...@basic-s3.html
* igt@i915_getparams_basic@basic-subslice-total:
- fi-tgl-y: [DMESG-WARN][18] ([i915#402]) -> [PASS][19] +1
similar issue
[18]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9895/fi-tgl-y/igt@i915_getparams_ba...@basic-subslice-total.html
[19]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19850/fi-tgl-y/igt@i915_getparams_ba...@basic-subslice-total.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
[fdo#111827]: https://bugs.freedesktop.org/show_bug.cgi?id=111827
[i915#1436]: https://gitlab.freedesktop.org/drm/intel/issues/1436
[i915#1849]: https://gitlab.freedesktop.org/drm/intel/issues/1849
[i915#1886]: https://g
[Intel-gfx] [PATCH i-g-t 1/5] benchmarks: Build gem_exec_tracer with meson
Seems it has been overlooked during mesonification. It's a shared module that's meant to be LD_PRELOAD-ed to intercept EXECBUFFER2 calls for the purpose of replaying them later. Signed-off-by: Arkadiusz Hiler --- benchmarks/meson.build | 8 1 file changed, 8 insertions(+) diff --git a/benchmarks/meson.build b/benchmarks/meson.build index c70e1aac..bede51dc 100644 --- a/benchmarks/meson.build +++ b/benchmarks/meson.build @@ -35,3 +35,11 @@ foreach prog : benchmark_progs install_dir : benchmarksdir, dependencies : igt_deps) endforeach + +lib_gem_exec_tracer = shared_module( + 'gem_exec_tracer', + 'gem_exec_tracer.c', + dependencies : dlsym, + include_directories : inc, + install_dir : benchmarksdir, + install: true) -- 2.31.0 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH i-g-t 4/5] .gitlab-ci: Don't test Autotools
Signed-off-by: Arkadiusz Hiler
---
.gitlab-ci.yml | 18 --
Dockerfile.build-debian | 8
2 files changed, 26 deletions(-)
diff --git a/.gitlab-ci.yml b/.gitlab-ci.yml
index e226d9d7..2b03fc98 100644
--- a/.gitlab-ci.yml
+++ b/.gitlab-ci.yml
@@ -154,17 +154,6 @@ build:tests-debian-meson-mips:
paths:
- build
-build:tests-debian-autotools:
- image: $CI_REGISTRY/$CI_PROJECT_PATH/build-debian:commit-$CI_COMMIT_SHA
- stage: build
- script:
-- ./autogen.sh --enable-{chamelium,audio,intel,amdgpu,nouveau,tests,runner}
-- make -j $(nproc) || make -j 1
-- cp tests/test-list.txt autotools-test-list.txt
- artifacts:
-paths:
- - autotools-test-list.txt
-
TEST ##
test:ninja-test:
@@ -236,13 +225,6 @@ test:ninja-test-mips:
- build
when: on_failure
-test:test-list-diff:
- dependencies:
-- build:tests-debian-autotools
-- build:tests-debian-meson
- stage: test
- script: diff <(sed "s/ /\n/g" meson-test-list.txt| grep -v
'vc4\|v3d\|panfrost\|nouveau' | sort) <(sed "s/ /\n/g" autotools-test-list.txt
| sort)
-
test:list-undocumented-tests:
dependencies:
- build:tests-fedora
diff --git a/Dockerfile.build-debian b/Dockerfile.build-debian
index b143a532..454f4bce 100644
--- a/Dockerfile.build-debian
+++ b/Dockerfile.build-debian
@@ -20,12 +20,4 @@ RUN apt-get install -y \
peg \
libdrm-intel1
-# autotools build deps
-RUN apt-get install -y \
- autoconf \
- automake \
- xutils-dev \
- libtool \
- make
-
RUN apt-get clean
--
2.31.0
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH i-g-t 5/5] Get rid of GNU Autotools
Autotools have been deprecated in favor of Meson since early 2019.
Cc: Daniel Vetter
Cc: Petri Latvala
Cc: Tomi Sarvela
Signed-off-by: Arkadiusz Hiler
---
Makefile.am | 44 ---
autogen.sh | 17 -
benchmarks/Makefile.am | 28 --
benchmarks/Makefile.sources | 28 --
configure.ac | 343 --
lib/Makefile.am | 226
lib/Makefile.sources | 195 ---
m4/as-compiler-flag.m4 | 62
m4/ax_gcc_func_attribute.m4 | 226
overlay/Makefile.am | 70
scripts/Makefile.am | 2 -
tests/Makefile.am| 153
tests/Makefile.sources | 581 ---
tests/intel-ci/Makefile.am | 5 -
tools/Makefile.am| 31 --
tools/Makefile.sources | 80 -
tools/i915-perf/Makefile.am | 29 --
tools/meson.build| 5 +-
tools/null_state_gen/Makefile.am | 31 --
tools/registers/Makefile.am | 2 -
20 files changed, 1 insertion(+), 2157 deletions(-)
delete mode 100644 Makefile.am
delete mode 100755 autogen.sh
delete mode 100644 benchmarks/Makefile.am
delete mode 100644 benchmarks/Makefile.sources
delete mode 100644 configure.ac
delete mode 100644 lib/Makefile.am
delete mode 100644 lib/Makefile.sources
delete mode 100644 m4/as-compiler-flag.m4
delete mode 100644 m4/ax_gcc_func_attribute.m4
delete mode 100644 overlay/Makefile.am
delete mode 100644 scripts/Makefile.am
delete mode 100644 tests/Makefile.am
delete mode 100644 tests/Makefile.sources
delete mode 100644 tests/intel-ci/Makefile.am
delete mode 100644 tools/Makefile.am
delete mode 100644 tools/Makefile.sources
delete mode 100644 tools/i915-perf/Makefile.am
delete mode 100644 tools/null_state_gen/Makefile.am
delete mode 100644 tools/registers/Makefile.am
diff --git a/Makefile.am b/Makefile.am
deleted file mode 100644
index 94250964..
--- a/Makefile.am
+++ /dev/null
@@ -1,44 +0,0 @@
-# Copyright © 2005 Adam Jackson.
-# Copyright © 2009,2013 Intel Corporation
-#
-# Permission is hereby granted, free of charge, to any person obtaining a
-# copy of this software and associated documentation files (the "Software"),
-# to deal in the Software without restriction, including without limitation
-# on the rights to use, copy, modify, merge, publish, distribute, sub
-# license, and/or sell copies of the Software, and to permit persons to whom
-# the Software is furnished to do so, subject to the following conditions:
-#
-# The above copyright notice and this permission notice (including the next
-# paragraph) shall be included in all copies or substantial portions of the
-# Software.
-#
-# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-# IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-# FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
-# ADAM JACKSON BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
-# IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
-# CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
-
-ACLOCAL_AMFLAGS = ${ACLOCAL_FLAGS} -I m4
-
-SUBDIRS = lib tools scripts benchmarks
-
-if BUILD_TESTS
-SUBDIRS += tests
-endif
-
-if BUILD_X86
-SUBDIRS += overlay benchmarks
-endif
-
-MAINTAINERCLEANFILES = ChangeLog INSTALL
-
-.PHONY: ChangeLog INSTALL
-
-INSTALL:
- $(INSTALL_CMD)
-
-ChangeLog:
- $(CHANGELOG_CMD)
-
-dist-hook: ChangeLog INSTALL
diff --git a/autogen.sh b/autogen.sh
deleted file mode 100755
index 65fcab2f..
--- a/autogen.sh
+++ /dev/null
@@ -1,17 +0,0 @@
-#! /bin/sh
-
-srcdir=`dirname $0`
-test -z "$srcdir" && srcdir=.
-
-ORIGDIR=`pwd`
-cd $srcdir
-
-autoreconf -v --install || exit 1
-cd $ORIGDIR || exit $?
-
-git config --local --get format.subjectPrefix >/dev/null 2>&1 ||
-git config --local format.subjectPrefix "PATCH i-g-t"
-
-if test -z "$NOCONFIGURE"; then
-$srcdir/configure "$@"
-fi
diff --git a/benchmarks/Makefile.am b/benchmarks/Makefile.am
deleted file mode 100644
index 45b923eb..
--- a/benchmarks/Makefile.am
+++ /dev/null
@@ -1,28 +0,0 @@
-include Makefile.sources
-
-benchmarks_PROGRAMS = $(benchmarks_prog_list)
-
-if HAVE_LIBDRM_INTEL
-benchmarks_PROGRAMS += $(LIBDRM_INTEL_BENCHMARKS)
-endif
-
-AM_CPPFLAGS = \
- -I$(top_srcdir) \
- -I$(top_srcdir)/include/drm-uapi \
- -I$(top_srcdir)/lib \
- -I$(top_srcdir)/lib/stubs/syscalls
-
-AM_CFLAGS = -I$(top_srcdir)/include/drm-uapi \
- $(DRM_CFLAGS) $(CWARNFLAGS) $(CAIRO_CFLAGS) $(LIBUNWIND_CFLAGS) \
- $(WERROR_CFLAGS) -D_GNU_SOURCE
-LDADD = $(top_builddir)/lib/libintel_tools.la
-
-benchmarks_LTLIBRARIES = gem_exec_tracer.la
-gem_exec_tracer_la_LDFLAGS = -module -avoid-version -no-undefined
-gem_exec_tracer_la_LIBADD = -ldl
-
-gem_latency_CFLAG
[Intel-gfx] [PATCH i-g-t 3/5] tests: Remove ddx_intel_after_fbdev
It's not a even a proper test.
Suggested-by: Petri Latvala
Signed-off-by: Arkadiusz Hiler
---
tests/Makefile.sources | 4 --
tests/ddx_intel_after_fbdev | 73 -
2 files changed, 77 deletions(-)
delete mode 100755 tests/ddx_intel_after_fbdev
diff --git a/tests/Makefile.sources b/tests/Makefile.sources
index 4f24fb3a..ffc7878a 100644
--- a/tests/Makefile.sources
+++ b/tests/Makefile.sources
@@ -550,10 +550,6 @@ kernel_tests_full = \
$(extra_kernel_tests) \
$(NULL)
-scripts = \
- ddx_intel_after_fbdev \
- $(NULL)
-
IMAGES = pass.png 1080p-left.png 1080p-right.png
testdisplay_SOURCES = \
diff --git a/tests/ddx_intel_after_fbdev b/tests/ddx_intel_after_fbdev
deleted file mode 100755
index f068209d..
--- a/tests/ddx_intel_after_fbdev
+++ /dev/null
@@ -1,73 +0,0 @@
-#!/bin/bash
-#
-# Testcase: Load Intel DDX after fbdev was loaded
-#
-
-whoami | grep -q root || {
- echo "ERROR: not running as root"
- exit 1
-}
-
-# no other X session should be running
-find /tmp/ -name .X*lock 2>/dev/null | grep -q X && {
- echo "ERROR: X session already running"
- exit 1
-}
-
-TMPDIR=$(mktemp -d /tmp/igt.) || {
- echo "ERROR: Failed to create temp dir"
- exit 1
-}
-
-cat > $TMPDIR/xorg.conf.fbdev << EOF
-Section "Device"
- Driver "fbdev"
- Identifier "Device[fbdev]"
-EndSection
-EOF
-
-cat > $TMPDIR/xorg.conf.intel << EOF
-Section "Device"
- Driver "intel"
- Identifier "Device[intel]"
-EndSection
-EOF
-
-# log before fbdev
-dmesg -c > $TMPDIR/dmesg.1.before.fbdev
-cp /var/log/Xorg.0.log $TMPDIR/Xorg.0.log.1.before.fbdev
-
-# run fbdev
-xinit -- /usr/bin/X -config $TMPDIR/xorg.conf.fbdev &
-sleep 5
-if [ -f `which intel_reg` ]; then
-`which intel_reg` dump > $TMPDIR/intel_reg_dump.1.fbdev
-fi
-killall X
-
-# log after fbdev & before intel
-dmesg -c > $TMPDIR/dmesg.2.after.fbdev.before.intel
-cp /var/log/Xorg.0.log $TMPDIR/Xorg.0.log.2.after.fbdev.before.intel
-
-sleep 5
-
-# run intel
-xinit -- /usr/bin/X -config $TMPDIR/xorg.conf.intel &
-sleep 5
-if [ -f `which intel_reg` ]; then
-`which intel_reg` dump > $TMPDIR/intel_reg_dump.2.intel
-fi
-killall X
-
-# log after intel
-dmesg -c > $TMPDIR/dmesg.3.after.intel
-cp /var/log/Xorg.0.log $TMPDIR/Xorg.0.log.3.after.intel
-
-cp $0 $TMPDIR/
-
-tar czf $TMPDIR.tar.gz $TMPDIR/*
-if [ -f $TMPDIR.tar.gz ]; then
- echo $TMPDIR.tar.gz contains this script, all configs and logs
generated on this tests
-fi
-
-exit 0
--
2.31.0
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH i-g-t 2/5] tests: Build gem_concurrent_all with meson
...and add it to test-list-full.txt just like we do when building with
autotools.
Signed-off-by: Arkadiusz Hiler
---
tests/meson.build | 13 +
1 file changed, 13 insertions(+)
diff --git a/tests/meson.build b/tests/meson.build
index 54a1a3c7..8e3cd390 100644
--- a/tests/meson.build
+++ b/tests/meson.build
@@ -402,6 +402,19 @@ test_list_target = custom_target('testlist',
install : true,
install_dir : libexecdir)
+test_executables += executable('gem_concurrent_all',
'i915/gem_concurrent_all.c',
+ dependencies : test_deps + [ libatomic ],
+ install_dir : libexecdir,
+ install_rpath : libexecdir_rpathdir,
+ install : true)
+test_list += 'gem_concurrent_all'
+
+test_list_full_target = custom_target('testlist-full',
+ output : 'test-list-full.txt',
+ command : [ gen_testlist, '@OUTPUT@', test_list ],
+ install : true,
+ install_dir : libexecdir)
+
test_script = find_program('igt_command_line.sh')
foreach prog : test_list
test('testcase check ' + prog, test_script, args : prog)
--
2.31.0
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✗ Fi.CI.DOCS: warning for series starting with [1/2] drm/i915: Fix transposed arguments to skl_plane_wm_level()
== Series Details == Series: series starting with [1/2] drm/i915: Fix transposed arguments to skl_plane_wm_level() URL : https://patchwork.freedesktop.org/series/88420/ State : warning == Summary == $ make htmldocs 2>&1 > /dev/null | grep i915 ./drivers/gpu/drm/i915/gem/i915_gem_shrinker.c:102: warning: Function parameter or member 'ww' not described in 'i915_gem_shrink' ./drivers/gpu/drm/i915/i915_cmd_parser.c:1420: warning: Excess function parameter 'trampoline' description in 'intel_engine_cmd_parser' ./drivers/gpu/drm/i915/i915_cmd_parser.c:1420: warning: Function parameter or member 'jump_whitelist' not described in 'intel_engine_cmd_parser' ./drivers/gpu/drm/i915/i915_cmd_parser.c:1420: warning: Function parameter or member 'shadow_map' not described in 'intel_engine_cmd_parser' ./drivers/gpu/drm/i915/i915_cmd_parser.c:1420: warning: Function parameter or member 'batch_map' not described in 'intel_engine_cmd_parser' ./drivers/gpu/drm/i915/i915_cmd_parser.c:1420: warning: Excess function parameter 'trampoline' description in 'intel_engine_cmd_parser' /home/cidrm/kernel/Documentation/gpu/i915:22: ./drivers/gpu/drm/i915/intel_runtime_pm.c:423: WARNING: Inline strong start-string without end-string. ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✓ Fi.CI.BAT: success for series starting with [1/2] drm/i915: Fix transposed arguments to skl_plane_wm_level()
== Series Details ==
Series: series starting with [1/2] drm/i915: Fix transposed arguments to
skl_plane_wm_level()
URL : https://patchwork.freedesktop.org/series/88420/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_9895 -> Patchwork_19851
Summary
---
**SUCCESS**
No regressions found.
External URL:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19851/index.html
Known issues
Here are the changes found in Patchwork_19851 that come from known issues:
### IGT changes ###
Issues hit
* igt@fbdev@read:
- fi-tgl-y: [PASS][1] -> [DMESG-WARN][2] ([i915#402])
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9895/fi-tgl-y/igt@fb...@read.html
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19851/fi-tgl-y/igt@fb...@read.html
* igt@gem_exec_fence@basic-busy@bcs0:
- fi-kbl-soraka: NOTRUN -> [SKIP][3] ([fdo#109271]) +24 similar issues
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19851/fi-kbl-soraka/igt@gem_exec_fence@basic-b...@bcs0.html
* igt@gem_huc_copy@huc-copy:
- fi-kbl-soraka: NOTRUN -> [SKIP][4] ([fdo#109271] / [i915#2190])
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19851/fi-kbl-soraka/igt@gem_huc_c...@huc-copy.html
* igt@i915_selftest@live@gt_pm:
- fi-kbl-soraka: NOTRUN -> [DMESG-FAIL][5] ([i915#1886] / [i915#2291])
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19851/fi-kbl-soraka/igt@i915_selftest@live@gt_pm.html
* igt@kms_chamelium@common-hpd-after-suspend:
- fi-kbl-soraka: NOTRUN -> [SKIP][6] ([fdo#109271] / [fdo#111827]) +8
similar issues
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19851/fi-kbl-soraka/igt@kms_chamel...@common-hpd-after-suspend.html
* igt@kms_chamelium@dp-crc-fast:
- fi-kbl-7500u: [PASS][7] -> [FAIL][8] ([i915#1372])
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9895/fi-kbl-7500u/igt@kms_chamel...@dp-crc-fast.html
[8]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19851/fi-kbl-7500u/igt@kms_chamel...@dp-crc-fast.html
* igt@kms_pipe_crc_basic@compare-crc-sanitycheck-pipe-d:
- fi-kbl-soraka: NOTRUN -> [SKIP][9] ([fdo#109271] / [i915#533])
[9]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19851/fi-kbl-soraka/igt@kms_pipe_crc_ba...@compare-crc-sanitycheck-pipe-d.html
Possible fixes
* igt@gem_exec_suspend@basic-s3:
- fi-tgl-y: [DMESG-WARN][10] ([i915#2411] / [i915#402]) ->
[PASS][11]
[10]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9895/fi-tgl-y/igt@gem_exec_susp...@basic-s3.html
[11]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19851/fi-tgl-y/igt@gem_exec_susp...@basic-s3.html
* igt@i915_getparams_basic@basic-subslice-total:
- fi-tgl-y: [DMESG-WARN][12] ([i915#402]) -> [PASS][13]
[12]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9895/fi-tgl-y/igt@i915_getparams_ba...@basic-subslice-total.html
[13]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19851/fi-tgl-y/igt@i915_getparams_ba...@basic-subslice-total.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
[fdo#111827]: https://bugs.freedesktop.org/show_bug.cgi?id=111827
[i915#1372]: https://gitlab.freedesktop.org/drm/intel/issues/1372
[i915#1849]: https://gitlab.freedesktop.org/drm/intel/issues/1849
[i915#1886]: https://gitlab.freedesktop.org/drm/intel/issues/1886
[i915#2190]: https://gitlab.freedesktop.org/drm/intel/issues/2190
[i915#2291]: https://gitlab.freedesktop.org/drm/intel/issues/2291
[i915#2411]: https://gitlab.freedesktop.org/drm/intel/issues/2411
[i915#3180]: https://gitlab.freedesktop.org/drm/intel/issues/3180
[i915#3278]: https://gitlab.freedesktop.org/drm/intel/issues/3278
[i915#402]: https://gitlab.freedesktop.org/drm/intel/issues/402
[i915#533]: https://gitlab.freedesktop.org/drm/intel/issues/533
Participating hosts (46 -> 42)
--
Additional (1): fi-kbl-soraka
Missing(5): fi-ilk-m540 fi-hsw-4200u fi-bsw-n3050 fi-bsw-cyan
fi-bdw-samus
Build changes
-
* Linux: CI_DRM_9895 -> Patchwork_19851
CI-20190529: 20190529
CI_DRM_9895: bb187b1b292c637c3ef195f46d6e5c74f60df8f4 @
git://anongit.freedesktop.org/gfx-ci/linux
IGT_6046: e76039273b1524147c43dba061756f06003d56ae @
git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_19851: bb530435a8e128e1d2d7b292efea3289d3b63b82 @
git://anongit.freedesktop.org/gfx-ci/linux
== Linux commits ==
bb530435a8e1 drm/i915: Stop adding planes to the commit needlessly
f91462ea538d drm/i915: Fix transposed arguments to skl_plane_wm_level()
== Logs ==
For more details see:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19851/ind
[Intel-gfx] [PATCH] drm/i915/dg1: Add HWMON power sensor support
As part of the System Managemenent Interface (SMI), use the HWMON
subsystem to display power utilization.
The following standard HWMON power sensors are currently supported
(and appropriately scaled):
/sys/class/drm/card0/device/hwmon/hwmon
- energy1_input
- power1_cap
- power1_max
Some non-standard HWMON power information is also provided, such as
enable bits and intervals.
Signed-off-by: Dale B Stimson
---
drivers/gpu/drm/i915/Kconfig | 1 +
drivers/gpu/drm/i915/Makefile | 1 +
drivers/gpu/drm/i915/i915_drv.c | 8 +
drivers/gpu/drm/i915/i915_drv.h | 3 +
drivers/gpu/drm/i915/i915_hwmon.c | 785 ++
drivers/gpu/drm/i915/i915_hwmon.h | 41 ++
drivers/gpu/drm/i915/i915_reg.h | 53 ++
7 files changed, 892 insertions(+)
create mode 100644 drivers/gpu/drm/i915/i915_hwmon.c
create mode 100644 drivers/gpu/drm/i915/i915_hwmon.h
diff --git a/drivers/gpu/drm/i915/Kconfig b/drivers/gpu/drm/i915/Kconfig
index 1e1cb245fca77..ec8d5a0d7ea96 100644
--- a/drivers/gpu/drm/i915/Kconfig
+++ b/drivers/gpu/drm/i915/Kconfig
@@ -14,6 +14,7 @@ config DRM_I915
select DRM_MIPI_DSI
select RELAY
select IRQ_WORK
+ select HWMON
# i915 depends on ACPI_VIDEO when ACPI is enabled
# but for select to work, need to select ACPI_VIDEO's dependencies, ick
select BACKLIGHT_CLASS_DEVICE if ACPI
diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makefile
index 14f1ab399ad08..1c110d306e493 100644
--- a/drivers/gpu/drm/i915/Makefile
+++ b/drivers/gpu/drm/i915/Makefile
@@ -37,6 +37,7 @@ i915-y += i915_drv.o \
i915_config.o \
i915_irq.o \
i915_getparam.o \
+ i915_hwmon.o \
i915_mitigations.o \
i915_params.o \
i915_pci.o \
diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index b2018e85afc2d..958517e5157b4 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -69,6 +69,7 @@
#include "i915_debugfs.h"
#include "i915_drv.h"
+#include "i915_hwmon.h"
#include "i915_ioc32.h"
#include "i915_irq.h"
#include "i915_memcpy.h"
@@ -671,6 +672,10 @@ static void i915_driver_register(struct drm_i915_private
*dev_priv)
return;
}
+ /* Register with hwmon */
+ if (i915_hwmon_init(&dev_priv->drm))
+ drm_err(&dev_priv->drm, "Failed to register driver hwmon!\n");
+
i915_debugfs_register(dev_priv);
i915_setup_sysfs(dev_priv);
@@ -711,6 +716,9 @@ static void i915_driver_unregister(struct drm_i915_private
*dev_priv)
i915_pmu_unregister(dev_priv);
i915_teardown_sysfs(dev_priv);
+
+ i915_hwmon_fini(&dev_priv->drm);
+
drm_dev_unplug(&dev_priv->drm);
i915_gem_driver_unregister(dev_priv);
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index fa596dace4902..7998461e2f00c 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -61,6 +61,7 @@
#include
#include
+#include "i915_hwmon.h"
#include "i915_params.h"
#include "i915_reg.h"
#include "i915_utils.h"
@@ -1108,6 +1109,8 @@ struct drm_i915_private {
struct i915_perf perf;
+ struct i915_hwmon hwmon;
+
/* Abstract the submission mechanism (legacy ringbuffer or execlists)
away */
struct intel_gt gt;
diff --git a/drivers/gpu/drm/i915/i915_hwmon.c
b/drivers/gpu/drm/i915/i915_hwmon.c
new file mode 100644
index 0..373bb937a373d
--- /dev/null
+++ b/drivers/gpu/drm/i915/i915_hwmon.c
@@ -0,0 +1,785 @@
+// SPDX-License-Identifier: MIT
+
+/*
+ * Copyright © 2020 Intel Corporation
+ */
+
+/*
+ * Power-related hwmon entries.
+ */
+
+#include
+#include
+
+#include "i915_drv.h"
+#include "gt/intel_gt.h"
+#include "i915_hwmon.h"
+
+/**
+ * SF_* - scale factors for particular quantities.
+ * The hwmon standard says that quantities of the given types are specified
+ * in the given units:
+ * - time - milliseconds
+ * - power - microwatts
+ * - energy - microjoules
+ */
+
+#define SF_TIME 1000
+#define SF_POWER 100
+#define SF_ENERGY 100
+
+static void
+_locked_with_pm_intel_uncore_rmw(struct intel_uncore *uncore,
+i915_reg_t reg, u32 clear, u32 set)
+{
+ struct drm_i915_private *i915 = uncore->i915;
+ struct i915_hwmon *hwmon = &i915->hwmon;
+ intel_wakeref_t wakeref;
+
+ mutex_lock(&hwmon->hwmon_lock);
+
+ with_intel_runtime_pm(uncore->rpm, wakeref)
+ intel_uncore_rmw(uncore, reg, clear, set);
+
+ mutex_unlock(&hwmon->hwmon_lock);
+}
+
+/*
+ * _field_read_and_scale()
+ * Return type of u64 allows for the case where the scaling might cause a
+ * result exceeding 32 bits.
+ */
+static __always_inline u64
+_field_read_and_scale(struct intel_uncore *uncore, i915_reg_t rgadr,
+ u32 field_mask, int
[Intel-gfx] ✗ Fi.CI.DOCS: warning for drivers: gpu: drm: Remove repeated declaration
== Series Details == Series: drivers: gpu: drm: Remove repeated declaration URL : https://patchwork.freedesktop.org/series/88431/ State : warning == Summary == $ make htmldocs 2>&1 > /dev/null | grep i915 ./drivers/gpu/drm/i915/gem/i915_gem_shrinker.c:102: warning: Function parameter or member 'ww' not described in 'i915_gem_shrink' ./drivers/gpu/drm/i915/i915_cmd_parser.c:1420: warning: Excess function parameter 'trampoline' description in 'intel_engine_cmd_parser' ./drivers/gpu/drm/i915/i915_cmd_parser.c:1420: warning: Function parameter or member 'jump_whitelist' not described in 'intel_engine_cmd_parser' ./drivers/gpu/drm/i915/i915_cmd_parser.c:1420: warning: Function parameter or member 'shadow_map' not described in 'intel_engine_cmd_parser' ./drivers/gpu/drm/i915/i915_cmd_parser.c:1420: warning: Function parameter or member 'batch_map' not described in 'intel_engine_cmd_parser' ./drivers/gpu/drm/i915/i915_cmd_parser.c:1420: warning: Excess function parameter 'trampoline' description in 'intel_engine_cmd_parser' /home/cidrm/kernel/Documentation/gpu/i915:22: ./drivers/gpu/drm/i915/intel_runtime_pm.c:423: WARNING: Inline strong start-string without end-string. ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH v3 3/8] drm/i915: add new helpers for accessing stepping info
On Mon, 2021-03-08 at 15:56 +0200, Jani Nikula wrote:
> Add new runtime info field for stepping. Add new helpers for accessing
> them. As we'll be switching platforms over to the new scheme
> incrementally, check for non-initialized steppings.
>
> In case a platform does not have separate display and gt steppings, it's
> okay to use a common shorthand. However, in this case the display
> stepping must not be initialized, and gt stepping is the single point of
> truth.
>
> v2: Rename stepping->step
>
> Signed-off-by: Jani Nikula
> ---
> drivers/gpu/drm/i915/i915_drv.h | 24 +++-
> drivers/gpu/drm/i915/intel_device_info.h | 4
> drivers/gpu/drm/i915/intel_step.h| 14 ++
> 3 files changed, 33 insertions(+), 9 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index 02170edd6628..a543b1ad9ba9 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -1274,6 +1274,21 @@ static inline struct drm_i915_private
> *pdev_to_i915(struct pci_dev *pdev)
> #define IS_REVID(p, since, until) \
> (INTEL_REVID(p) >= (since) && INTEL_REVID(p) <= (until))
>
>
> +#define INTEL_DISPLAY_STEP(__i915) (RUNTIME_INFO(__i915)->step.disp_stepping)
> +#define INTEL_GT_STEP(__i915) (RUNTIME_INFO(__i915)->step.gt_stepping)
> +
> +#define IS_DISPLAY_STEP(__i915, since, until) \
> + (drm_WARN_ON(&(__i915)->drm, INTEL_DISPLAY_STEP(__i915) == STEP_NONE), \
> + INTEL_DISPLAY_STEP(__i915) >= (since) && INTEL_DISPLAY_STEP(__i915) <=
> (until))
> +
> +#define IS_GT_STEP(__i915, since, until) \
> + (drm_WARN_ON(&(__i915)->drm, INTEL_GT_STEP(__i915) == STEP_NONE), \
> + INTEL_GT_STEP(__i915) >= (since) && INTEL_GT_STEP(__i915) <= (until))
> +
> +#define IS_STEP(p, since, until) \
> + (drm_WARN_ON(&(__i915)->drm, INTEL_DISPLAY_STEP(__i915) != STEP_NONE), \
(drm_WARN_ON(&(__i915)->drm, INTEL_DISPLAY_STEP(__i915) == STEP_NONE), \
But I don't think IS_STEP() is useful, better use IS_DISPLAY/GT_STEP even for
platforms with the same display and GT version.
With the change above:
Reviewed-by: José Roberto de Souza
> + INTEL_GT_STEP(__i915, since, until))
> +
> static __always_inline unsigned int
> __platform_mask_index(const struct intel_runtime_info *info,
> enum intel_platform p)
> @@ -1511,15 +1526,6 @@ enum {
> #define IS_JSL_EHL_REVID(p, since, until) \
> (IS_JSL_EHL(p) && IS_REVID(p, since, until))
>
>
> -enum {
> - STEP_A0,
> - STEP_A2,
> - STEP_B0,
> - STEP_B1,
> - STEP_C0,
> - STEP_D0,
> -};
> -
> static inline const struct i915_rev_steppings *
> tgl_stepping_get(struct drm_i915_private *dev_priv)
> {
> diff --git a/drivers/gpu/drm/i915/intel_device_info.h
> b/drivers/gpu/drm/i915/intel_device_info.h
> index d44f64b57b7a..f84569e8e711 100644
> --- a/drivers/gpu/drm/i915/intel_device_info.h
> +++ b/drivers/gpu/drm/i915/intel_device_info.h
> @@ -27,6 +27,8 @@
>
>
> #include
>
>
> +#include "intel_step.h"
> +
> #include "display/intel_display.h"
>
>
> #include "gt/intel_engine_types.h"
> @@ -225,6 +227,8 @@ struct intel_runtime_info {
> u8 num_scalers[I915_MAX_PIPES];
>
>
> u32 rawclk_freq;
> +
> + struct i915_rev_steppings step;
> };
>
>
> struct intel_driver_caps {
> diff --git a/drivers/gpu/drm/i915/intel_step.h
> b/drivers/gpu/drm/i915/intel_step.h
> index af922ae3bb4e..8b3ef19d935b 100644
> --- a/drivers/gpu/drm/i915/intel_step.h
> +++ b/drivers/gpu/drm/i915/intel_step.h
> @@ -22,4 +22,18 @@ extern const struct i915_rev_steppings
> tgl_uy_revid_step_tbl[TGL_UY_REVID_STEP_T
> extern const struct i915_rev_steppings
> tgl_revid_step_tbl[TGL_REVID_STEP_TBL_SIZE];
> extern const struct i915_rev_steppings
> adls_revid_step_tbl[ADLS_REVID_STEP_TBL_SIZE];
>
>
> +/*
> + * Symbolic steppings that do not match the hardware. These are valid both
> as gt
> + * and display steppings as symbolic names.
> + */
> +enum intel_step {
> + STEP_NONE = 0,
> + STEP_A0,
> + STEP_A2,
> + STEP_B0,
> + STEP_B1,
> + STEP_C0,
> + STEP_D0,
> +};
> +
> #endif /* __INTEL_STEP_H__ */
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH v3 4/8] drm/i915: switch KBL to the new stepping scheme
On Mon, 2021-03-08 at 15:56 +0200, Jani Nikula wrote:
> Add new symbolic names for revision ids, and convert KBL revids to use
> them via the new stepping check macros.
>
> This also fixes theoretical out of bounds access to kbl_revids array.
>
> v2: Rename stepping->step
>
> Signed-off-by: Jani Nikula
>
> ---
>
> The initialization sounds like an early part of
> intel_device_info_runtime_init(), and indeed touches runtime info.
> ---
> drivers/gpu/drm/i915/gt/gen8_engine_cs.c| 2 +-
> drivers/gpu/drm/i915/gt/intel_workarounds.c | 6 +-
> drivers/gpu/drm/i915/i915_drv.c | 3 +-
> drivers/gpu/drm/i915/i915_drv.h | 24 ++-
> drivers/gpu/drm/i915/intel_pm.c | 4 +-
> drivers/gpu/drm/i915/intel_step.c | 69 ++---
> drivers/gpu/drm/i915/intel_step.h | 11 +++-
> 7 files changed, 82 insertions(+), 37 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/gt/gen8_engine_cs.c
> b/drivers/gpu/drm/i915/gt/gen8_engine_cs.c
> index cac80af7ad1c..74e8acc72da0 100644
> --- a/drivers/gpu/drm/i915/gt/gen8_engine_cs.c
> +++ b/drivers/gpu/drm/i915/gt/gen8_engine_cs.c
> @@ -42,7 +42,7 @@ int gen8_emit_flush_rcs(struct i915_request *rq, u32 mode)
> vf_flush_wa = true;
>
>
> /* WaForGAMHang:kbl */
> - if (IS_KBL_GT_REVID(rq->engine->i915, 0, KBL_REVID_B0))
> + if (IS_KBL_GT_STEP(rq->engine->i915, 0, STEP_B0))
> dc_flush_wa = true;
> }
>
>
> diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c
> b/drivers/gpu/drm/i915/gt/intel_workarounds.c
> index 2827d4f2e086..0c502a733779 100644
> --- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
> +++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
> @@ -481,7 +481,7 @@ static void kbl_ctx_workarounds_init(struct
> intel_engine_cs *engine,
> gen9_ctx_workarounds_init(engine, wal);
>
>
> /* WaToEnableHwFixForPushConstHWBug:kbl */
> - if (IS_KBL_GT_REVID(i915, KBL_REVID_C0, REVID_FOREVER))
> + if (IS_KBL_GT_STEP(i915, STEP_C0, STEP_FOREVER))
> wa_masked_en(wal, COMMON_SLICE_CHICKEN2,
>GEN8_SBE_DISABLE_REPLAY_BUF_OPTIMIZATION);
>
>
> @@ -899,7 +899,7 @@ kbl_gt_workarounds_init(struct drm_i915_private *i915,
> struct i915_wa_list *wal)
> gen9_gt_workarounds_init(i915, wal);
>
>
> /* WaDisableDynamicCreditSharing:kbl */
> - if (IS_KBL_GT_REVID(i915, 0, KBL_REVID_B0))
> + if (IS_KBL_GT_STEP(i915, 0, STEP_B0))
> wa_write_or(wal,
> GAMT_CHKN_BIT_REG,
> GAMT_CHKN_DISABLE_DYNAMIC_CREDIT_SHARING);
> @@ -2020,7 +2020,7 @@ xcs_engine_wa_init(struct intel_engine_cs *engine,
> struct i915_wa_list *wal)
> struct drm_i915_private *i915 = engine->i915;
>
>
> /* WaKBLVECSSemaphoreWaitPoll:kbl */
> - if (IS_KBL_GT_REVID(i915, KBL_REVID_A0, KBL_REVID_E0)) {
> + if (IS_KBL_GT_STEP(i915, STEP_A0, STEP_E0)) {
> wa_write(wal,
>RING_SEMA_WAIT_POLL(engine->mmio_base),
>1);
> diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
> index 3edd5e47ad68..83214ffe6cf1 100644
> --- a/drivers/gpu/drm/i915/i915_drv.c
> +++ b/drivers/gpu/drm/i915/i915_drv.c
> @@ -273,7 +273,7 @@ static void intel_detect_preproduction_hw(struct
> drm_i915_private *dev_priv)
> pre |= IS_HSW_EARLY_SDV(dev_priv);
> pre |= IS_SKL_REVID(dev_priv, 0, SKL_REVID_F0);
> pre |= IS_BXT_REVID(dev_priv, 0, BXT_REVID_B_LAST);
> - pre |= IS_KBL_GT_REVID(dev_priv, 0, KBL_REVID_A0);
> + pre |= IS_KBL_GT_STEP(dev_priv, 0, STEP_A0);
> pre |= IS_GLK_REVID(dev_priv, 0, GLK_REVID_A2);
>
>
> if (pre) {
> @@ -307,6 +307,7 @@ static int i915_driver_early_probe(struct
> drm_i915_private *dev_priv)
> return -ENODEV;
>
>
> intel_device_info_subplatform_init(dev_priv);
> + intel_step_init(dev_priv);
>
>
> intel_uncore_mmio_debug_init_early(&dev_priv->mmio_debug);
> intel_uncore_init_early(&dev_priv->uncore, dev_priv);
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index a543b1ad9ba9..7f259aab4226 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -1475,26 +1475,10 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915,
> #define IS_BXT_REVID(dev_priv, since, until) \
> (IS_BROXTON(dev_priv) && IS_REVID(dev_priv, since, until))
>
>
> -enum {
> - KBL_REVID_A0,
> - KBL_REVID_B0,
> - KBL_REVID_B1,
> - KBL_REVID_C0,
> - KBL_REVID_D0,
> - KBL_REVID_D1,
> - KBL_REVID_E0,
> - KBL_REVID_F0,
> - KBL_REVID_G0,
> -};
> -
> -#define IS_KBL_GT_REVID(dev_priv, since, until) \
> - (IS_KABYLAKE(dev_priv) && \
> - kbl_revids[INTEL_REVID(dev_priv)].gt_stepping >= since && \
> - kbl_revids[INTEL_REVID(dev_priv)].gt_stepping <= u
[Intel-gfx] ✓ Fi.CI.BAT: success for drivers: gpu: drm: Remove repeated declaration
== Series Details ==
Series: drivers: gpu: drm: Remove repeated declaration
URL : https://patchwork.freedesktop.org/series/88431/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_9895 -> Patchwork_19852
Summary
---
**SUCCESS**
No regressions found.
External URL:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19852/index.html
Known issues
Here are the changes found in Patchwork_19852 that come from known issues:
### IGT changes ###
Issues hit
* igt@gem_exec_fence@basic-busy@bcs0:
- fi-kbl-soraka: NOTRUN -> [SKIP][1] ([fdo#109271]) +24 similar issues
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19852/fi-kbl-soraka/igt@gem_exec_fence@basic-b...@bcs0.html
* igt@gem_huc_copy@huc-copy:
- fi-kbl-soraka: NOTRUN -> [SKIP][2] ([fdo#109271] / [i915#2190])
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19852/fi-kbl-soraka/igt@gem_huc_c...@huc-copy.html
* igt@gem_ringfill@basic-all:
- fi-tgl-y: [PASS][3] -> [DMESG-WARN][4] ([i915#402])
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9895/fi-tgl-y/igt@gem_ringf...@basic-all.html
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19852/fi-tgl-y/igt@gem_ringf...@basic-all.html
* igt@i915_selftest@live@gt_pm:
- fi-kbl-soraka: NOTRUN -> [DMESG-FAIL][5] ([i915#1886] / [i915#2291])
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19852/fi-kbl-soraka/igt@i915_selftest@live@gt_pm.html
* igt@kms_chamelium@common-hpd-after-suspend:
- fi-kbl-soraka: NOTRUN -> [SKIP][6] ([fdo#109271] / [fdo#111827]) +8
similar issues
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19852/fi-kbl-soraka/igt@kms_chamel...@common-hpd-after-suspend.html
* igt@kms_pipe_crc_basic@compare-crc-sanitycheck-pipe-d:
- fi-kbl-soraka: NOTRUN -> [SKIP][7] ([fdo#109271] / [i915#533])
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19852/fi-kbl-soraka/igt@kms_pipe_crc_ba...@compare-crc-sanitycheck-pipe-d.html
Possible fixes
* igt@i915_getparams_basic@basic-subslice-total:
- fi-tgl-y: [DMESG-WARN][8] ([i915#402]) -> [PASS][9]
[8]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9895/fi-tgl-y/igt@i915_getparams_ba...@basic-subslice-total.html
[9]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19852/fi-tgl-y/igt@i915_getparams_ba...@basic-subslice-total.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
[fdo#111827]: https://bugs.freedesktop.org/show_bug.cgi?id=111827
[i915#1849]: https://gitlab.freedesktop.org/drm/intel/issues/1849
[i915#1886]: https://gitlab.freedesktop.org/drm/intel/issues/1886
[i915#2190]: https://gitlab.freedesktop.org/drm/intel/issues/2190
[i915#2291]: https://gitlab.freedesktop.org/drm/intel/issues/2291
[i915#3180]: https://gitlab.freedesktop.org/drm/intel/issues/3180
[i915#3278]: https://gitlab.freedesktop.org/drm/intel/issues/3278
[i915#402]: https://gitlab.freedesktop.org/drm/intel/issues/402
[i915#533]: https://gitlab.freedesktop.org/drm/intel/issues/533
Participating hosts (46 -> 43)
--
Additional (1): fi-kbl-soraka
Missing(4): fi-ilk-m540 fi-bsw-cyan fi-bdw-samus fi-hsw-4200u
Build changes
-
* Linux: CI_DRM_9895 -> Patchwork_19852
CI-20190529: 20190529
CI_DRM_9895: bb187b1b292c637c3ef195f46d6e5c74f60df8f4 @
git://anongit.freedesktop.org/gfx-ci/linux
IGT_6046: e76039273b1524147c43dba061756f06003d56ae @
git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_19852: 9dbfd658007680dfa36f829f1800c0ee918574a2 @
git://anongit.freedesktop.org/gfx-ci/linux
== Linux commits ==
9dbfd6580076 drivers: gpu: drm: Remove repeated declaration
== Logs ==
For more details see:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19852/index.html
___
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https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH v3 5/8] drm/i915: switch TGL and ADL to the new stepping scheme
On Mon, 2021-03-08 at 15:56 +0200, Jani Nikula wrote:
> This changes the way revids not present in the array are handled:
>
> - For gaps in the array, the next present revid is used.
>
> - For revids beyond the array, the new STEP_FUTURE is used instead of
> the last revid in the array.
>
> In both cases, we'll get debug logging of what's going on.
>
> v2: Rename stepping->step
>
Reviewed-by: José Roberto de Souza
> Signed-off-by: Jani Nikula
> ---
> drivers/gpu/drm/i915/i915_drv.h | 59 ---
> drivers/gpu/drm/i915/intel_step.c | 17 ++---
> drivers/gpu/drm/i915/intel_step.h | 8 -
> 3 files changed, 28 insertions(+), 56 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index 7f259aab4226..991318e90b5a 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -1510,44 +1510,17 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915,
> #define IS_JSL_EHL_REVID(p, since, until) \
> (IS_JSL_EHL(p) && IS_REVID(p, since, until))
>
>
>
>
> -static inline const struct i915_rev_steppings *
> -tgl_stepping_get(struct drm_i915_private *dev_priv)
> -{
> - u8 revid = INTEL_REVID(dev_priv);
> - u8 size;
> - const struct i915_rev_steppings *revid_step_tbl;
> -
> - if (IS_ALDERLAKE_S(dev_priv)) {
> - revid_step_tbl = adls_revid_step_tbl;
> - size = ARRAY_SIZE(adls_revid_step_tbl);
> - } else if (IS_TGL_U(dev_priv) || IS_TGL_Y(dev_priv)) {
> - revid_step_tbl = tgl_uy_revid_step_tbl;
> - size = ARRAY_SIZE(tgl_uy_revid_step_tbl);
> - } else {
> - revid_step_tbl = tgl_revid_step_tbl;
> - size = ARRAY_SIZE(tgl_revid_step_tbl);
> - }
> -
> - revid = min_t(u8, revid, size - 1);
> -
> - return &revid_step_tbl[revid];
> -}
> -
> -#define IS_TGL_DISP_STEPPING(p, since, until) \
> - (IS_TIGERLAKE(p) && \
> - tgl_stepping_get(p)->disp_stepping >= (since) && \
> - tgl_stepping_get(p)->disp_stepping <= (until))
> +#define IS_TGL_DISP_STEPPING(__i915, since, until) \
> + (IS_TIGERLAKE(__i915) && \
> + IS_DISPLAY_STEP(__i915, since, until))
>
>
>
>
> -#define IS_TGL_UY_GT_STEPPING(p, since, until) \
> - ((IS_TGL_U(p) || IS_TGL_Y(p)) && \
> - tgl_stepping_get(p)->gt_stepping >= (since) && \
> - tgl_stepping_get(p)->gt_stepping <= (until))
> +#define IS_TGL_UY_GT_STEPPING(__i915, since, until) \
> + ((IS_TGL_U(__i915) || IS_TGL_Y(__i915)) && \
> + IS_GT_STEP(__i915, since, until))
>
>
>
>
> -#define IS_TGL_GT_STEPPING(p, since, until) \
> - (IS_TIGERLAKE(p) && \
> - !(IS_TGL_U(p) || IS_TGL_Y(p)) && \
> - tgl_stepping_get(p)->gt_stepping >= (since) && \
> - tgl_stepping_get(p)->gt_stepping <= (until))
> +#define IS_TGL_GT_STEPPING(__i915, since, until) \
> + (IS_TIGERLAKE(__i915) && !(IS_TGL_U(__i915) || IS_TGL_Y(__i915)) && \
> + IS_GT_STEP(__i915, since, until))
>
>
>
>
> #define RKL_REVID_A0 0x0
> #define RKL_REVID_B0 0x1
> @@ -1562,15 +1535,13 @@ tgl_stepping_get(struct drm_i915_private *dev_priv)
> #define IS_DG1_REVID(p, since, until) \
> (IS_DG1(p) && IS_REVID(p, since, until))
>
>
>
>
> -#define IS_ADLS_DISP_STEPPING(p, since, until) \
> - (IS_ALDERLAKE_S(p) && \
> - tgl_stepping_get(p)->disp_stepping >= (since) && \
> - tgl_stepping_get(p)->disp_stepping <= (until))
> +#define IS_ADLS_DISP_STEPPING(__i915, since, until) \
> + (IS_ALDERLAKE_S(__i915) && \
> + IS_DISPLAY_STEP(__i915, since, until))
>
>
>
>
> -#define IS_ADLS_GT_STEPPING(p, since, until) \
> - (IS_ALDERLAKE_S(p) && \
> - tgl_stepping_get(p)->gt_stepping >= (since) && \
> - tgl_stepping_get(p)->gt_stepping <= (until))
> +#define IS_ADLS_GT_STEPPING(__i915, since, until) \
> + (IS_ALDERLAKE_S(__i915) && \
> + IS_GT_STEP(__i915, since, until))
>
>
>
>
> #define IS_LP(dev_priv) (INTEL_INFO(dev_priv)->is_lp)
> #define IS_GEN9_LP(dev_priv) (IS_GEN(dev_priv, 9) && IS_LP(dev_priv))
> diff --git a/drivers/gpu/drm/i915/intel_step.c
> b/drivers/gpu/drm/i915/intel_step.c
> index aaa9494b0f4f..4593eba24a7d 100644
> --- a/drivers/gpu/drm/i915/intel_step.c
> +++ b/drivers/gpu/drm/i915/intel_step.c
> @@ -26,7 +26,7 @@ static const struct i915_rev_steppings kbl_revids[] = {
> [7] = { .gt_stepping = STEP_G0, .disp_stepping = STEP_C0 },
> };
>
>
>
>
> -const struct i915_rev_steppings tgl_uy_revid_step_tbl[] = {
> +static const struct i915_rev_steppings tgl_uy_revid_step_tbl[] = {
> [0] = { .gt_stepping = STEP_A0, .disp_stepping = STEP_A0 },
> [1] = { .gt_stepping = STEP_B0, .disp_stepping = STEP_C0 },
> [2] = { .gt_stepping = STEP_B1, .disp_stepping = STEP_C0 },
> @@ -34,12 +34,12 @@ const struct i915_rev_steppings tgl_uy_revid_step_tbl[] =
> {
> };
>
>
>
>
> /* Same GT stepping between tgl_uy_revids and tgl_revids don't m
Re: [Intel-gfx] [PATCH v3 8/8] drm/i915: rename i915_rev_steppings->intel_step_info
On Mon, 2021-03-08 at 15:56 +0200, Jani Nikula wrote:
> Matter of taste. Match the prefix for everything else related to
> steppings. No functional changes.
Reviewed-by: José Roberto de Souza
For the renaming patches, 6, 7 and 8 I'm also fine with the current naming up
to you.
>
> Signed-off-by: Jani Nikula
> ---
> drivers/gpu/drm/i915/intel_device_info.h | 2 +-
> drivers/gpu/drm/i915/intel_step.c| 12 ++--
> drivers/gpu/drm/i915/intel_step.h| 2 +-
> 3 files changed, 8 insertions(+), 8 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_device_info.h
> b/drivers/gpu/drm/i915/intel_device_info.h
> index f84569e8e711..1bcae2a8c79b 100644
> --- a/drivers/gpu/drm/i915/intel_device_info.h
> +++ b/drivers/gpu/drm/i915/intel_device_info.h
> @@ -228,7 +228,7 @@ struct intel_runtime_info {
>
>
>
>
> u32 rawclk_freq;
>
>
>
>
> - struct i915_rev_steppings step;
> + struct intel_step_info step;
> };
>
>
>
>
> struct intel_driver_caps {
> diff --git a/drivers/gpu/drm/i915/intel_step.c
> b/drivers/gpu/drm/i915/intel_step.c
> index 9df2dd264841..914a5de4346e 100644
> --- a/drivers/gpu/drm/i915/intel_step.c
> +++ b/drivers/gpu/drm/i915/intel_step.c
> @@ -15,7 +15,7 @@
>
>
>
>
>
>
>
>
> /* FIXME: what about REVID_E0 */
> -static const struct i915_rev_steppings kbl_revids[] = {
> +static const struct intel_step_info kbl_revids[] = {
> [0] = { .gt_step = STEP_A0, .display_step = STEP_A0 },
> [1] = { .gt_step = STEP_B0, .display_step = STEP_B0 },
> [2] = { .gt_step = STEP_C0, .display_step = STEP_B0 },
> @@ -26,7 +26,7 @@ static const struct i915_rev_steppings kbl_revids[] = {
> [7] = { .gt_step = STEP_G0, .display_step = STEP_C0 },
> };
>
>
>
>
> -static const struct i915_rev_steppings tgl_uy_revid_step_tbl[] = {
> +static const struct intel_step_info tgl_uy_revid_step_tbl[] = {
> [0] = { .gt_step = STEP_A0, .display_step = STEP_A0 },
> [1] = { .gt_step = STEP_B0, .display_step = STEP_C0 },
> [2] = { .gt_step = STEP_B1, .display_step = STEP_C0 },
> @@ -34,12 +34,12 @@ static const struct i915_rev_steppings
> tgl_uy_revid_step_tbl[] = {
> };
>
>
>
>
> /* Same GT stepping between tgl_uy_revids and tgl_revids don't mean the same
> HW */
> -static const struct i915_rev_steppings tgl_revid_step_tbl[] = {
> +static const struct intel_step_info tgl_revid_step_tbl[] = {
> [0] = { .gt_step = STEP_A0, .display_step = STEP_B0 },
> [1] = { .gt_step = STEP_B0, .display_step = STEP_D0 },
> };
>
>
>
>
> -static const struct i915_rev_steppings adls_revid_step_tbl[] = {
> +static const struct intel_step_info adls_revid_step_tbl[] = {
> [0x0] = { .gt_step = STEP_A0, .display_step = STEP_A0 },
> [0x1] = { .gt_step = STEP_A0, .display_step = STEP_A2 },
> [0x4] = { .gt_step = STEP_B0, .display_step = STEP_B0 },
> @@ -49,10 +49,10 @@ static const struct i915_rev_steppings
> adls_revid_step_tbl[] = {
>
>
>
>
> void intel_step_init(struct drm_i915_private *i915)
> {
> - const struct i915_rev_steppings *revids = NULL;
> + const struct intel_step_info *revids = NULL;
> int size = 0;
> int revid = INTEL_REVID(i915);
> - struct i915_rev_steppings step = {};
> + struct intel_step_info step = {};
>
>
>
>
> if (IS_ALDERLAKE_S(i915)) {
> revids = adls_revid_step_tbl;
> diff --git a/drivers/gpu/drm/i915/intel_step.h
> b/drivers/gpu/drm/i915/intel_step.h
> index 102fd6a26893..958a8bb5d677 100644
> --- a/drivers/gpu/drm/i915/intel_step.h
> +++ b/drivers/gpu/drm/i915/intel_step.h
> @@ -10,7 +10,7 @@
>
>
>
>
> struct drm_i915_private;
>
>
>
>
> -struct i915_rev_steppings {
> +struct intel_step_info {
> u8 gt_step;
> u8 display_step;
> };
___
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Re: [Intel-gfx] [PATCH] drivers: gpu: drm: Remove repeated declaration
The changes looks good but can you resend changing the commit message to: "drm/i915: Remove repeated declaration"? To better match with i915 patches. With this change you can add Reviewed-by: José Roberto de Souza On Thu, 2021-03-25 at 13:00 +0800, Wan Jiabing wrote: > struct drm_i915_private, struct intel_crtc_state and > struct intel_crtc have been declared before. > Remove the duplicate. > > Signed-off-by: Wan Jiabing > --- > drivers/gpu/drm/i915/display/intel_crt.h | 1 - > drivers/gpu/drm/i915/display/intel_display.h | 1 - > drivers/gpu/drm/i915/display/intel_vrr.h | 1 - > 3 files changed, 3 deletions(-) > > diff --git a/drivers/gpu/drm/i915/display/intel_crt.h > b/drivers/gpu/drm/i915/display/intel_crt.h > index 1b3fba359efc..6c5c44600cbd 100644 > --- a/drivers/gpu/drm/i915/display/intel_crt.h > +++ b/drivers/gpu/drm/i915/display/intel_crt.h > @@ -11,7 +11,6 @@ > enum pipe; > struct drm_encoder; > struct drm_i915_private; > -struct drm_i915_private; > > > bool intel_crt_port_enabled(struct drm_i915_private *dev_priv, > i915_reg_t adpa_reg, enum pipe *pipe); > diff --git a/drivers/gpu/drm/i915/display/intel_display.h > b/drivers/gpu/drm/i915/display/intel_display.h > index 76f8a805b0a3..29cb6d84ed70 100644 > --- a/drivers/gpu/drm/i915/display/intel_display.h > +++ b/drivers/gpu/drm/i915/display/intel_display.h > @@ -48,7 +48,6 @@ struct i915_ggtt_view; > struct intel_atomic_state; > struct intel_crtc; > struct intel_crtc_state; > -struct intel_crtc_state; > struct intel_digital_port; > struct intel_dp; > struct intel_encoder; > diff --git a/drivers/gpu/drm/i915/display/intel_vrr.h > b/drivers/gpu/drm/i915/display/intel_vrr.h > index fac01bf4ab50..96f9c9c27ab9 100644 > --- a/drivers/gpu/drm/i915/display/intel_vrr.h > +++ b/drivers/gpu/drm/i915/display/intel_vrr.h > @@ -15,7 +15,6 @@ struct intel_crtc; > struct intel_crtc_state; > struct intel_dp; > struct intel_encoder; > -struct intel_crtc; > > > bool intel_vrr_is_capable(struct drm_connector *connector); > void intel_vrr_check_modeset(struct intel_atomic_state *state); ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
