[Intel-gfx] i915: v5.10.23: kernel hangs at boot when external monitor is connected?!
Hi, when booting with an external monitor connected the boot process seems to stop in the kernel. No additional output is show, it just hangs. kernel is 5.10.23 and driver is i915. When unplugging and reset computer, the system starts normal. Any ideas what could be the culprit and what to enable in kernel config to get a bit more insight what's probably going on? mfg thomas ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH xf86-video-intel] sna: Allow DRI3 on gen2/3
From: Ville Syrjälä Once we have DRI3 in Mesa i915 driver we can allow DRI3 on gen2/3. But due to the supposed missing DRI2 fallback with older Mesa let's only do that if the user explicitly requests it. Note that when I tried this with modern Mesa that lacks i915 DRI3 support things seemed to fall back to DRI2 just fine, but better safe than sorry I guess. Cc: Chris Wilson References: https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9734 Signed-off-by: Ville Syrjälä --- src/sna/sna_driver.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/src/sna/sna_driver.c b/src/sna/sna_driver.c index d810b262b452..b0e1683362d3 100644 --- a/src/sna/sna_driver.c +++ b/src/sna/sna_driver.c @@ -444,7 +444,8 @@ static void setup_dri(struct sna *sna) sna->dri3.override = !sna->dri3.available || xf86IsOptionSet(sna->Options, OPTION_DRI); - if (level >= 3 && sna->kgem.gen >= 040) + if (level >= 3 && (sna->kgem.gen >= 040 || + xf86IsOptionSet(sna->Options, OPTION_DRI))) sna->dri3.enable = sna->dri3.available; #endif #if HAVE_DRI2 -- 2.26.2 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH] drm/i915: Avoid div-by-zero on gen2
From: Ville Syrjälä
Gen2 tiles are 2KiB in size so i915_gem_object_get_tile_row_size()
can in fact return <4KiB, which leads to div-by-zero here.
Avoid that.
Not sure i915_gem_object_get_tile_row_size() is entirely
sane anyway since it doesn't account for the different tile
layouts on i8xx/i915...
I'm not able to hit this before commit 6846895fde05 ("drm/i915:
Replace PIN_NONFAULT with calls to PIN_NOEVICT") and it looks
like I also need to run recent version of Mesa. With those in
place xonotic trips on this quite easily on my 85x.
Cc: Chris Wilson
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/gem/i915_gem_mman.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_mman.c
b/drivers/gpu/drm/i915/gem/i915_gem_mman.c
index ec28a6cde49b..0b2434e29d00 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_mman.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_mman.c
@@ -189,7 +189,7 @@ compute_partial_view(const struct drm_i915_gem_object *obj,
struct i915_ggtt_view view;
if (i915_gem_object_is_tiled(obj))
- chunk = roundup(chunk, tile_row_pages(obj));
+ chunk = roundup(chunk, tile_row_pages(obj) ?: 1);
view.type = I915_GGTT_VIEW_PARTIAL;
view.partial.offset = rounddown(page_offset, chunk);
--
2.26.2
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[Intel-gfx] ✗ Fi.CI.BUILD: failure for sna: Allow DRI3 on gen2/3
== Series Details == Series: sna: Allow DRI3 on gen2/3 URL : https://patchwork.freedesktop.org/series/88216/ State : failure == Summary == Applying: sna: Allow DRI3 on gen2/3 error: sha1 information is lacking or useless (src/sna/sna_driver.c). error: could not build fake ancestor hint: Use 'git am --show-current-patch=diff' to see the failed patch Patch failed at 0001 sna: Allow DRI3 on gen2/3 When you have resolved this problem, run "git am --continue". If you prefer to skip this patch, run "git am --skip" instead. To restore the original branch and stop patching, run "git am --abort". ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH] drm/i915: Avoid div-by-zero on gen2
Quoting Ville Syrjala (2021-03-21 16:10:38)
> From: Ville Syrjälä
>
> Gen2 tiles are 2KiB in size so i915_gem_object_get_tile_row_size()
> can in fact return <4KiB, which leads to div-by-zero here.
> Avoid that.
So long as we overestimate it is fine, since we only care to find a
suitably small chunk that is large enough. I thought it was
overestimating, oh well.
> Not sure i915_gem_object_get_tile_row_size() is entirely
> sane anyway since it doesn't account for the different tile
> layouts on i8xx/i915...
It should not matter so long as we pick a common divisor, suitable for
the fence register.
> I'm not able to hit this before commit 6846895fde05 ("drm/i915:
> Replace PIN_NONFAULT with calls to PIN_NOEVICT") and it looks
> like I also need to run recent version of Mesa. With those in
> place xonotic trips on this quite easily on my 85x.
NOEVICT will make it much less eager to remove older bindings, with the
preference then to use smaller views of objects. The theory being that
the workingset is less than the whole object, so we can fit more active
pages in and cause less thrashing when moving the unused pages around
in the GTT.
> Cc: Chris Wilson
> Signed-off-by: Ville Syrjälä
> ---
> drivers/gpu/drm/i915/gem/i915_gem_mman.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/i915/gem/i915_gem_mman.c
> b/drivers/gpu/drm/i915/gem/i915_gem_mman.c
> index ec28a6cde49b..0b2434e29d00 100644
> --- a/drivers/gpu/drm/i915/gem/i915_gem_mman.c
> +++ b/drivers/gpu/drm/i915/gem/i915_gem_mman.c
> @@ -189,7 +189,7 @@ compute_partial_view(const struct drm_i915_gem_object
> *obj,
> struct i915_ggtt_view view;
>
> if (i915_gem_object_is_tiled(obj))
> - chunk = roundup(chunk, tile_row_pages(obj));
> + chunk = roundup(chunk, tile_row_pages(obj) ?: 1);
I was thinking the answer would be to align to the next page, and hey
presto!
Reviewed-by: Chris Wilson
-Chris
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Re: [Intel-gfx] [PATCH] drm/i915: Avoid div-by-zero on gen2
Quoting Chris Wilson (2021-03-21 16:28:07) > Quoting Ville Syrjala (2021-03-21 16:10:38) > > diff --git a/drivers/gpu/drm/i915/gem/i915_gem_mman.c > > b/drivers/gpu/drm/i915/gem/i915_gem_mman.c > > index ec28a6cde49b..0b2434e29d00 100644 > > --- a/drivers/gpu/drm/i915/gem/i915_gem_mman.c > > +++ b/drivers/gpu/drm/i915/gem/i915_gem_mman.c > > @@ -189,7 +189,7 @@ compute_partial_view(const struct drm_i915_gem_object > > *obj, > > struct i915_ggtt_view view; > > > > if (i915_gem_object_is_tiled(obj)) > > - chunk = roundup(chunk, tile_row_pages(obj)); > > + chunk = roundup(chunk, tile_row_pages(obj) ?: 1); > > I was thinking the answer would be to align to the next page, and hey > presto! Wait, the tile row cannot be a single page. Something else is zero that should not be. -Chris ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH] drm/i915: Avoid div-by-zero on gen2
Quoting Chris Wilson (2021-03-21 16:30:32) > Quoting Chris Wilson (2021-03-21 16:28:07) > > Quoting Ville Syrjala (2021-03-21 16:10:38) > > > diff --git a/drivers/gpu/drm/i915/gem/i915_gem_mman.c > > > b/drivers/gpu/drm/i915/gem/i915_gem_mman.c > > > index ec28a6cde49b..0b2434e29d00 100644 > > > --- a/drivers/gpu/drm/i915/gem/i915_gem_mman.c > > > +++ b/drivers/gpu/drm/i915/gem/i915_gem_mman.c > > > @@ -189,7 +189,7 @@ compute_partial_view(const struct drm_i915_gem_object > > > *obj, > > > struct i915_ggtt_view view; > > > > > > if (i915_gem_object_is_tiled(obj)) > > > - chunk = roundup(chunk, tile_row_pages(obj)); > > > + chunk = roundup(chunk, tile_row_pages(obj) ?: 1); > > > > I was thinking the answer would be to align to the next page, and hey > > presto! > > Wait, the tile row cannot be a single page. Something else is zero that > should not be. Which fortunately does not matter here, as we start with a 2MiB chunk and want to align that to a multiple of tile rows. Still, as you said, something stinks. -Chris ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915: Avoid div-by-zero on gen2
== Series Details == Series: drm/i915: Avoid div-by-zero on gen2 URL : https://patchwork.freedesktop.org/series/88217/ State : success == Summary == CI Bug Log - changes from CI_DRM_9878 -> Patchwork_19819 Summary --- **SUCCESS** No regressions found. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19819/index.html Known issues Here are the changes found in Patchwork_19819 that come from known issues: ### IGT changes ### Issues hit * igt@amdgpu/amd_basic@semaphore: - fi-bdw-5557u: NOTRUN -> [SKIP][1] ([fdo#109271]) +26 similar issues [1]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19819/fi-bdw-5557u/igt@amdgpu/amd_ba...@semaphore.html * igt@amdgpu/amd_cs_nop@sync-fork-compute0: - fi-snb-2600:NOTRUN -> [SKIP][2] ([fdo#109271]) +17 similar issues [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19819/fi-snb-2600/igt@amdgpu/amd_cs_...@sync-fork-compute0.html * igt@core_hotunplug@unbind-rebind: - fi-bdw-5557u: NOTRUN -> [WARN][3] ([i915#2283]) [3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19819/fi-bdw-5557u/igt@core_hotunp...@unbind-rebind.html * igt@gem_exec_gttfill@basic: - fi-bsw-n3050: NOTRUN -> [SKIP][4] ([fdo#109271]) [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19819/fi-bsw-n3050/igt@gem_exec_gttf...@basic.html * igt@gem_exec_suspend@basic-s3: - fi-bsw-n3050: NOTRUN -> [INCOMPLETE][5] ([i915#3159]) [5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19819/fi-bsw-n3050/igt@gem_exec_susp...@basic-s3.html * igt@gem_linear_blits@basic: - fi-kbl-8809g: [PASS][6] -> [TIMEOUT][7] ([i915#2502] / [i915#3145]) [6]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9878/fi-kbl-8809g/igt@gem_linear_bl...@basic.html [7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19819/fi-kbl-8809g/igt@gem_linear_bl...@basic.html * igt@kms_chamelium@dp-crc-fast: - fi-bdw-5557u: NOTRUN -> [SKIP][8] ([fdo#109271] / [fdo#111827]) +8 similar issues [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19819/fi-bdw-5557u/igt@kms_chamel...@dp-crc-fast.html Possible fixes * igt@i915_selftest@live@hangcheck: - fi-snb-2600:[INCOMPLETE][9] ([i915#2782]) -> [PASS][10] [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9878/fi-snb-2600/igt@i915_selftest@l...@hangcheck.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19819/fi-snb-2600/igt@i915_selftest@l...@hangcheck.html * igt@kms_chamelium@dp-crc-fast: - fi-kbl-7500u: [FAIL][11] ([i915#1372]) -> [PASS][12] [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9878/fi-kbl-7500u/igt@kms_chamel...@dp-crc-fast.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19819/fi-kbl-7500u/igt@kms_chamel...@dp-crc-fast.html [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271 [fdo#111827]: https://bugs.freedesktop.org/show_bug.cgi?id=111827 [i915#1372]: https://gitlab.freedesktop.org/drm/intel/issues/1372 [i915#2283]: https://gitlab.freedesktop.org/drm/intel/issues/2283 [i915#2502]: https://gitlab.freedesktop.org/drm/intel/issues/2502 [i915#2782]: https://gitlab.freedesktop.org/drm/intel/issues/2782 [i915#3145]: https://gitlab.freedesktop.org/drm/intel/issues/3145 [i915#3159]: https://gitlab.freedesktop.org/drm/intel/issues/3159 Participating hosts (43 -> 40) -- Additional (1): fi-bsw-n3050 Missing(4): fi-ilk-m540 fi-bsw-cyan fi-bdw-samus fi-hsw-4200u Build changes - * Linux: CI_DRM_9878 -> Patchwork_19819 CI-20190529: 20190529 CI_DRM_9878: f5d18496a7876fd70b9d96d6a87b3c910f5e2ef0 @ git://anongit.freedesktop.org/gfx-ci/linux IGT_6039: 8c4a2cda2a92bdd87797969ef299ad7f6e8e993b @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_19819: a2151c8bb46fba38c79b84480d05ad51ec56e9d4 @ git://anongit.freedesktop.org/gfx-ci/linux == Linux commits == a2151c8bb46f drm/i915: Avoid div-by-zero on gen2 == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19819/index.html ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915: Avoid div-by-zero on gen2
== Series Details == Series: drm/i915: Avoid div-by-zero on gen2 URL : https://patchwork.freedesktop.org/series/88217/ State : success == Summary == CI Bug Log - changes from CI_DRM_9878_full -> Patchwork_19819_full Summary --- **SUCCESS** No regressions found. Known issues Here are the changes found in Patchwork_19819_full that come from known issues: ### IGT changes ### Issues hit * igt@drm_mm@all@insert_range: - shard-skl: NOTRUN -> [INCOMPLETE][1] ([i915#2485]) [1]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19819/shard-skl6/igt@drm_mm@all@insert_range.html * igt@gem_ctx_persistence@clone: - shard-snb: NOTRUN -> [SKIP][2] ([fdo#109271] / [i915#1099]) +6 similar issues [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19819/shard-snb7/igt@gem_ctx_persiste...@clone.html * igt@gem_exec_fair@basic-none-share@rcs0: - shard-tglb: [PASS][3] -> [FAIL][4] ([i915#2842]) +1 similar issue [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9878/shard-tglb7/igt@gem_exec_fair@basic-none-sh...@rcs0.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19819/shard-tglb8/igt@gem_exec_fair@basic-none-sh...@rcs0.html * igt@gem_exec_fair@basic-pace@vecs0: - shard-kbl: [PASS][5] -> [FAIL][6] ([i915#2842]) [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9878/shard-kbl2/igt@gem_exec_fair@basic-p...@vecs0.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19819/shard-kbl2/igt@gem_exec_fair@basic-p...@vecs0.html * igt@gem_exec_fair@basic-throttle@rcs0: - shard-glk: NOTRUN -> [FAIL][7] ([i915#2842]) [7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19819/shard-glk3/igt@gem_exec_fair@basic-throt...@rcs0.html * igt@gem_exec_reloc@basic-wide-active@bcs0: - shard-apl: NOTRUN -> [FAIL][8] ([i915#2389]) +3 similar issues [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19819/shard-apl6/igt@gem_exec_reloc@basic-wide-act...@bcs0.html * igt@gem_exec_reloc@basic-wide-active@rcs0: - shard-snb: NOTRUN -> [FAIL][9] ([i915#2389]) +2 similar issues [9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19819/shard-snb2/igt@gem_exec_reloc@basic-wide-act...@rcs0.html * igt@gem_exec_schedule@u-fairslice@rcs0: - shard-skl: [PASS][10] -> [DMESG-WARN][11] ([i915#1610] / [i915#2803]) [10]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9878/shard-skl4/igt@gem_exec_schedule@u-fairsl...@rcs0.html [11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19819/shard-skl9/igt@gem_exec_schedule@u-fairsl...@rcs0.html * igt@gem_exec_schedule@u-fairslice@vecs0: - shard-iclb: [PASS][12] -> [DMESG-WARN][13] ([i915#2803]) [12]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9878/shard-iclb4/igt@gem_exec_schedule@u-fairsl...@vecs0.html [13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19819/shard-iclb5/igt@gem_exec_schedule@u-fairsl...@vecs0.html * igt@gem_exec_whisper@basic-fds-priority-all: - shard-glk: [PASS][14] -> [DMESG-WARN][15] ([i915#118] / [i915#95]) +1 similar issue [14]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9878/shard-glk4/igt@gem_exec_whis...@basic-fds-priority-all.html [15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19819/shard-glk3/igt@gem_exec_whis...@basic-fds-priority-all.html * igt@gem_mmap_gtt@cpuset-medium-copy-xy: - shard-iclb: [PASS][16] -> [FAIL][17] ([i915#2428]) [16]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9878/shard-iclb8/igt@gem_mmap_...@cpuset-medium-copy-xy.html [17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19819/shard-iclb5/igt@gem_mmap_...@cpuset-medium-copy-xy.html * igt@gem_pwrite@basic-exhaustion: - shard-skl: NOTRUN -> [WARN][18] ([i915#2658]) +1 similar issue [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19819/shard-skl6/igt@gem_pwr...@basic-exhaustion.html - shard-snb: NOTRUN -> [WARN][19] ([i915#2658]) +1 similar issue [19]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19819/shard-snb7/igt@gem_pwr...@basic-exhaustion.html - shard-glk: NOTRUN -> [WARN][20] ([i915#2658]) [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19819/shard-glk3/igt@gem_pwr...@basic-exhaustion.html * igt@gem_render_copy@x-tiled-to-vebox-yf-tiled: - shard-kbl: NOTRUN -> [SKIP][21] ([fdo#109271]) +124 similar issues [21]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19819/shard-kbl4/igt@gem_render_c...@x-tiled-to-vebox-yf-tiled.html * igt@gem_spin_batch@engines@vcs0: - shard-apl: [PASS][22] -> [FAIL][23] ([i915#2898]) [22]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9878/shard-apl3/igt@gem_spin_batch@engi...@vcs0.html [23]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19819/sha
Re: [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915/hdcp: mst streams type1 capability check (rev2)
> -Original Message- > From: Patchwork > Sent: Friday, March 19, 2021 4:25 PM > To: Gupta, Anshuman > Cc: intel-gfx@lists.freedesktop.org > Subject: ✗ Fi.CI.CHECKPATCH: warning for drm/i915/hdcp: mst streams type1 > capability check (rev2) > > == Series Details == > > Series: drm/i915/hdcp: mst streams type1 capability check (rev2) > URL : https://patchwork.freedesktop.org/series/86345/ > State : warning > > == Summary == > > $ dim checkpatch origin/drm-tip > bb93c668b788 drm/i915/hdcp: mst streams type1 capability check > -:18: WARNING:BAD_SIGN_OFF: Duplicate signature > #18: > Signed-off-by: Anshuman Gupta duplicated signature get added by mistake while floating the rebased patch, I will remove the duplicate signature while pushing this patch. Thanks, Anshuman Gupta. > > total: 0 errors, 1 warnings, 0 checks, 96 lines checked > ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] ✗ Fi.CI.IGT: failure for drm/i915/hdcp: mst streams type1 capability check (rev2)
On 2021-03-19 at 13:26:16 +, Patchwork wrote:
> == Series Details ==
>
> Series: drm/i915/hdcp: mst streams type1 capability check (rev2)
> URL : https://patchwork.freedesktop.org/series/86345/
> State : failure
>
> == Summary ==
>
> CI Bug Log - changes from CI_DRM_9874_full -> Patchwork_19809_full
>
>
> Summary
> ---
>
> **FAILURE**
>
> Serious unknown changes coming with Patchwork_19809_full absolutely need to
> be
> verified manually.
>
> If you think the reported changes have nothing to do with the changes
> introduced in Patchwork_19809_full, please notify your bug team to allow
> them
> to document this new failure mode, which will reduce false positives in CI.
>
>
>
> Possible new issues
> ---
>
> Here are the unknown changes that may have been introduced in
> Patchwork_19809_full:
>
> ### IGT changes ###
>
> Possible regressions
>
> * igt@kms_flip_tiling@flip-y-tiled@edp-1-pipe-c:
> - shard-skl: NOTRUN -> [FAIL][1]
>[1]:
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19809/shard-skl6/igt@kms_flip_tiling@flip-y-ti...@edp-1-pipe-c.html
Hi Lakshmi ,
Above CI-IGT failures are not related to this patch, this patch is just a
rebase and CI results were green at Rev1.
https://patchwork.freedesktop.org/series/86345/#rev1
Could please raise the issue for above failure and re-report the result.
Thanks,
Anshuman Gupta.
>
>
>
> ### Piglit changes ###
>
> Possible regressions
>
> *
> spec@glsl-4.20@execution@vs_in@vs-input-double_dmat3-uint_uvec3_array3-position
> (NEW):
> - {pig-icl-1065g7}: NOTRUN -> [CRASH][2] +1 similar issue
>[2]:
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19809/pig-icl-1065g7/spec@glsl-4.20@execution@vs_in@vs-input-double_dmat3-uint_uvec3_array3-position.html
>
> *
> spec@glsl-4.20@execution@vs_in@vs-input-ubyte_uvec4-short_ivec4-position-double_dmat3
> (NEW):
> - {pig-icl-1065g7}: NOTRUN -> [INCOMPLETE][3] +3 similar issues
>[3]:
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19809/pig-icl-1065g7/spec@glsl-4.20@execution@vs_in@vs-input-ubyte_uvec4-short_ivec4-position-double_dmat3.html
>
>
> New tests
> -
>
> New tests have been introduced between CI_DRM_9874_full and
> Patchwork_19809_full:
>
> ### New Piglit tests (6) ###
>
> *
> spec@glsl-4.20@execution@vs_in@vs-input-double_dmat2x3-position-double_dvec3:
> - Statuses : 1 incomplete(s)
> - Exec time: [0.0] s
>
> *
> spec@glsl-4.20@execution@vs_in@vs-input-double_dmat3-uint_uvec3_array3-position:
> - Statuses : 1 crash(s)
> - Exec time: [1.02] s
>
> * spec@glsl-4.20@execution@vs_in@vs-input-float_float-position-double_dvec3:
> - Statuses : 1 crash(s)
> - Exec time: [1.06] s
>
> *
> spec@glsl-4.20@execution@vs_in@vs-input-position-int_ivec4_array3-double_dvec2_array2:
> - Statuses : 1 incomplete(s)
> - Exec time: [0.0] s
>
> *
> spec@glsl-4.20@execution@vs_in@vs-input-ubyte_uvec3-short_int-position-double_dvec4:
> - Statuses : 1 incomplete(s)
> - Exec time: [0.0] s
>
> *
> spec@glsl-4.20@execution@vs_in@vs-input-ubyte_uvec4-short_ivec4-position-double_dmat3:
> - Statuses : 1 incomplete(s)
> - Exec time: [0.0] s
>
>
>
> Known issues
>
>
> Here are the changes found in Patchwork_19809_full that come from known
> issues:
>
> ### IGT changes ###
>
> Issues hit
>
> * igt@feature_discovery@chamelium:
> - shard-iclb: NOTRUN -> [SKIP][4] ([fdo#111827])
>[4]:
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19809/shard-iclb5/igt@feature_discov...@chamelium.html
>
> * igt@gem_create@create-massive:
> - shard-kbl: NOTRUN -> [DMESG-WARN][5] ([i915#3002])
>[5]:
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19809/shard-kbl2/igt@gem_cre...@create-massive.html
>
> * igt@gem_ctx_persistence@clone:
> - shard-snb: NOTRUN -> [SKIP][6] ([fdo#109271] / [i915#1099]) +6
> similar issues
>[6]:
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19809/shard-snb5/igt@gem_ctx_persiste...@clone.html
>
> * igt@gem_ctx_sseu@mmap-args:
> - shard-kbl: NOTRUN -> [SKIP][7] ([fdo#109271]) +11 similar
> issues
>[7]:
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19809/shard-kbl2/igt@gem_ctx_s...@mmap-args.html
>
> * igt@gem_eio@in-flight-contexts-10ms:
> - shard-tglb: [PASS][8] -> [TIMEOUT][9] ([i915#3063])
>[8]:
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9874/shard-tglb7/igt@gem_...@in-flight-contexts-10ms.html
>[9]:
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19809/shard-tglb1/igt@gem_...@in-flight-contexts-10ms.html
>
> * igt@gem_exec_fair@basic-deadline:
> - shard-skl: NOTRUN -> [FAIL][10] ([i915#2846])
>[10]:
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19809/shard-s
Re: [Intel-gfx] [PATCH v3 3/3] drm/i915/display: Configure HDMI2.1 Pcon for FRL only if Src-Ctl mode is available
> -Original Message- > From: Nautiyal, Ankit K > Sent: Tuesday, March 9, 2021 10:09 AM > To: intel-gfx@lists.freedesktop.org > Cc: dri-de...@lists.freedesktop.org; ville.syrj...@linux.intel.com; Shankar, > Uma > ; airl...@linux.ie; jani.nik...@linux.intel.com > Subject: [PATCH v3 3/3] drm/i915/display: Configure HDMI2.1 Pcon for FRL only > if > Src-Ctl mode is available > > Currently we see only the MAX FRL BW from PCON before going for FRL. > Also add the check if source control mode is supported by the PCON, before > starting > configuring PCON for FRL training. > > Signed-off-by: Ankit Nautiyal > --- > drivers/gpu/drm/i915/display/intel_dp.c | 3 ++- > 1 file changed, 2 insertions(+), 1 deletion(-) > > diff --git a/drivers/gpu/drm/i915/display/intel_dp.c > b/drivers/gpu/drm/i915/display/intel_dp.c > index 2e90359ce21f..8e401d3fd29d 100644 > --- a/drivers/gpu/drm/i915/display/intel_dp.c > +++ b/drivers/gpu/drm/i915/display/intel_dp.c > @@ -2638,7 +2638,8 @@ void intel_dp_check_frl_training(struct intel_dp > *intel_dp) > struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); > > /* Always go for FRL training if supported */ > - if (!intel_dp_is_hdmi_2_1_sink(intel_dp) || > + if (!(intel_dp->dpcd[2] & DP_PCON_SOURCE_CTL_MODE) || Would be good to add spec reference as well here. With that added, this is Reviewed-by: Uma Shankar > + !intel_dp_is_hdmi_2_1_sink(intel_dp) || > intel_dp->frl.is_trained) > return; > > -- > 2.29.2 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 0/7] drm/i915: Add state checker for CSC coeff values
In this patch series, added state checker to validate CSC. This reads hardware state, and compares the originally requested state(s/w). This is done for chv, ilk, glk and their variant platforms. Rest of the platforms will be enabled on top of this later. Signed-off-by: Bhanuprakash Modem Bhanuprakash Modem (7): drm/i915/display: Introduce vfunc read_csc() to create hw ctm drm/i915/display: Add func to compare hw/sw CSC matrix drm/i915/display: Add macro to compare hw/sw CSC matrix drm/i915/display: Extract chv_read_csc() drm/i915/display: Extract ilk_read_csc() drm/i915/display: Extract icl_read_csc() FOR_TESTING_ONLY: Print coeffs of hw and sw CTM drivers/gpu/drm/i915/display/intel_color.c | 209 ++- drivers/gpu/drm/i915/display/intel_color.h | 3 + drivers/gpu/drm/i915/display/intel_display.c | 31 +++ drivers/gpu/drm/i915/i915_drv.h | 1 + 4 files changed, 239 insertions(+), 5 deletions(-) -- 2.20.1 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 1/7] drm/i915/display: Introduce vfunc read_csc() to create hw ctm
In this patch, a vfunc read_csc() is introduced to create a hw ctm
i.e. ctm having values read from CSC registers which will later be
used to compare with sw ctm to validate CSC coeff values.
Cc: Swati Sharma
Cc: Uma Shankar
Signed-off-by: Bhanuprakash Modem
---
drivers/gpu/drm/i915/display/intel_color.c | 3 +++
drivers/gpu/drm/i915/i915_drv.h| 1 +
2 files changed, 4 insertions(+)
diff --git a/drivers/gpu/drm/i915/display/intel_color.c
b/drivers/gpu/drm/i915/display/intel_color.c
index ff7dcb7088bf..17bb08e9cf64 100644
--- a/drivers/gpu/drm/i915/display/intel_color.c
+++ b/drivers/gpu/drm/i915/display/intel_color.c
@@ -1209,6 +1209,9 @@ void intel_color_get_config(struct intel_crtc_state
*crtc_state)
if (dev_priv->display.read_luts)
dev_priv->display.read_luts(crtc_state);
+
+ if (dev_priv->display.read_csc)
+ dev_priv->display.read_csc(crtc_state);
}
static bool need_plane_update(struct intel_plane *plane,
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 214fe10eb092..a8b55aca5fc4 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -327,6 +327,7 @@ struct drm_i915_display_funcs {
*/
void (*load_luts)(const struct intel_crtc_state *crtc_state);
void (*read_luts)(struct intel_crtc_state *crtc_state);
+ void (*read_csc)(struct intel_crtc_state *crtc_state);
};
struct intel_csr {
--
2.20.1
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 2/7] drm/i915/display: Add func to compare hw/sw CSC matrix
Add func intel_csc_equal() to compare hw/sw CSC coeff values.
Cc: Swati Sharma
Cc: Uma Shankar
Signed-off-by: Bhanuprakash Modem
---
drivers/gpu/drm/i915/display/intel_color.c | 51 +++---
drivers/gpu/drm/i915/display/intel_color.h | 3 ++
2 files changed, 47 insertions(+), 7 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_color.c
b/drivers/gpu/drm/i915/display/intel_color.c
index 17bb08e9cf64..54dfd3523272 100644
--- a/drivers/gpu/drm/i915/display/intel_color.c
+++ b/drivers/gpu/drm/i915/display/intel_color.c
@@ -348,16 +348,11 @@ static void icl_load_csc_matrix(const struct
intel_crtc_state *crtc_state)
crtc_state->csc_mode);
}
-static void chv_load_cgm_csc(struct intel_crtc *crtc,
-const struct drm_property_blob *blob)
+static void chv_csc_convert_ctm(const struct drm_color_ctm *ctm, u16 coeffs[9])
{
- struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
- const struct drm_color_ctm *ctm = blob->data;
- enum pipe pipe = crtc->pipe;
- u16 coeffs[9];
int i;
- for (i = 0; i < ARRAY_SIZE(coeffs); i++) {
+ for (i = 0; i < 9; i++) {
u64 abs_coeff = ((1ULL << 63) - 1) & ctm->matrix[i];
/* Round coefficient. */
@@ -374,6 +369,17 @@ static void chv_load_cgm_csc(struct intel_crtc *crtc,
coeffs[i] |= ((abs_coeff >> 32) & 7) << 12;
coeffs[i] |= (abs_coeff >> 20) & 0xfff;
}
+}
+
+static void chv_load_cgm_csc(struct intel_crtc *crtc,
+const struct drm_property_blob *blob)
+{
+ struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
+ const struct drm_color_ctm *ctm = blob->data;
+ enum pipe pipe = crtc->pipe;
+ u16 coeffs[9];
+
+ chv_csc_convert_ctm(ctm, coeffs);
intel_de_write(dev_priv, CGM_PIPE_CSC_COEFF01(pipe),
coeffs[1] << 16 | coeffs[0]);
@@ -1792,6 +1798,37 @@ bool intel_color_lut_equal(struct drm_property_blob
*blob1,
return true;
}
+bool intel_csc_equal(const struct intel_crtc_state *current_config,
+struct drm_property_blob *blob1,
+struct drm_property_blob *blob2)
+{
+ struct drm_i915_private *dev_priv =
to_i915(current_config->uapi.crtc->dev);
+ struct drm_color_ctm *ctm1, *ctm2;
+ u16 coeffs[9];
+ int i;
+
+ if (!blob1 != !blob2)
+ return false;
+
+ if (!blob1)
+ return true;
+
+ ctm1 = blob1->data;
+ ctm2 = blob2->data;
+
+ if (IS_CHERRYVIEW(dev_priv))
+ chv_csc_convert_ctm(ctm1, coeffs);
+ else
+ ilk_csc_convert_ctm(current_config, coeffs);
+
+ for (i = 0; i < 9; i++) {
+ if (abs(coeffs[i] - ctm2->matrix[i]))
+ return false;
+ }
+
+ return true;
+}
+
static struct drm_property_blob *i9xx_read_lut_8(struct intel_crtc *crtc)
{
struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
diff --git a/drivers/gpu/drm/i915/display/intel_color.h
b/drivers/gpu/drm/i915/display/intel_color.h
index 173727aaa24d..e6bd9aa0c04a 100644
--- a/drivers/gpu/drm/i915/display/intel_color.h
+++ b/drivers/gpu/drm/i915/display/intel_color.h
@@ -21,5 +21,8 @@ int intel_color_get_gamma_bit_precision(const struct
intel_crtc_state *crtc_stat
bool intel_color_lut_equal(struct drm_property_blob *blob1,
struct drm_property_blob *blob2,
u32 gamma_mode, u32 bit_precision);
+bool intel_csc_equal(const struct intel_crtc_state *crtc_state,
+ struct drm_property_blob *blob1,
+ struct drm_property_blob *blob2);
#endif /* __INTEL_COLOR_H__ */
--
2.20.1
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 3/7] drm/i915/display: Add macro to compare hw/sw CSC matrix
Add macro to compare hw/sw CSC coeff values. First need to
check whether hw/sw csc enable and csc mode matches or not.
If not no need to compare coeff values, if matches then only
compare.
Cc: Swati Sharma
Cc: Uma Shankar
Signed-off-by: Bhanuprakash Modem
---
drivers/gpu/drm/i915/display/intel_display.c | 31
1 file changed, 31 insertions(+)
diff --git a/drivers/gpu/drm/i915/display/intel_display.c
b/drivers/gpu/drm/i915/display/intel_display.c
index 7b38b9a38b85..c4b9d4a238b9 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -8925,6 +8925,29 @@ intel_pipe_config_compare(const struct intel_crtc_state
*current_config,
} \
} while (0)
+#define PIPE_CONF_CHECK_CSC(name1, name2, name3) do { \
+ if (current_config->name1 != pipe_config->name1) { \
+ pipe_config_mismatch(fastset, crtc, __stringify(name1), \
+ "(expected %s, found %s, won't compare csc
coeffs)", \
+ yesno(current_config->name1), \
+ yesno(pipe_config->name1)); \
+ ret = false;\
+ } else if (current_config->name2 != pipe_config->name2) { \
+ pipe_config_mismatch(fastset, crtc, __stringify(name2), \
+ "(expected %i, found %i, won't compare csc
coeffs)", \
+ current_config->name2, \
+ pipe_config->name2); \
+ ret = false;\
+ } else { \
+ if (!intel_csc_equal(current_config, current_config->name3, \
+ pipe_config->name3)) { \
+ pipe_config_mismatch(fastset, crtc, __stringify(name3),
\
+ "hw_state doesn't match sw_state"); \
+ ret = false; \
+ } \
+ } \
+} while (0)
+
#define PIPE_CONF_QUIRK(quirk) \
((current_config->quirks | pipe_config->quirks) & (quirk))
@@ -9052,6 +9075,13 @@ intel_pipe_config_compare(const struct intel_crtc_state
*current_config,
bp_gamma = intel_color_get_gamma_bit_precision(pipe_config);
if (bp_gamma)
PIPE_CONF_CHECK_COLOR_LUT(gamma_mode, hw.gamma_lut,
bp_gamma);
+
+ if (HAS_GMCH(dev_priv)) {
+ if (IS_CHERRYVIEW(dev_priv))
+ PIPE_CONF_CHECK_CSC(csc_enable, cgm_mode,
hw.ctm);
+ } else {
+ PIPE_CONF_CHECK_CSC(csc_enable, csc_mode, hw.ctm);
+ }
}
PIPE_CONF_CHECK_BOOL(double_wide);
@@ -9143,6 +9173,7 @@ intel_pipe_config_compare(const struct intel_crtc_state
*current_config,
#undef PIPE_CONF_CHECK_FLAGS
#undef PIPE_CONF_CHECK_CLOCK_FUZZY
#undef PIPE_CONF_CHECK_COLOR_LUT
+#undef PIPE_CONF_CHECK_CSC
#undef PIPE_CONF_QUIRK
return ret;
--
2.20.1
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 4/7] drm/i915/display: Extract chv_read_csc()
For Cherryview, add hw read out to create hw blob of ctm coeff
values.
Cc: Swati Sharma
Cc: Uma Shankar
Signed-off-by: Bhanuprakash Modem
---
drivers/gpu/drm/i915/display/intel_color.c | 47 ++
1 file changed, 47 insertions(+)
diff --git a/drivers/gpu/drm/i915/display/intel_color.c
b/drivers/gpu/drm/i915/display/intel_color.c
index 54dfd3523272..15f97fbb77b3 100644
--- a/drivers/gpu/drm/i915/display/intel_color.c
+++ b/drivers/gpu/drm/i915/display/intel_color.c
@@ -1943,6 +1943,52 @@ static void chv_read_luts(struct intel_crtc_state
*crtc_state)
i965_read_luts(crtc_state);
}
+static struct drm_property_blob *chv_read_cgm_ctm(struct intel_crtc *crtc)
+{
+ struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
+ enum pipe pipe = crtc->pipe;
+ struct drm_property_blob *blob;
+ struct drm_color_ctm *ctm;
+ u32 temp;
+
+ blob = drm_property_create_blob(&dev_priv->drm,
+ sizeof(struct drm_color_ctm),
+ NULL);
+ if (IS_ERR(blob))
+ return NULL;
+
+ ctm = blob->data;
+
+ temp = intel_de_read(dev_priv, CGM_PIPE_CSC_COEFF01(pipe));
+ ctm->matrix[0] = (temp >> 16) & 0x;
+ ctm->matrix[1] = temp & 0x;
+
+ temp = intel_de_read(dev_priv, CGM_PIPE_CSC_COEFF23(pipe));
+ ctm->matrix[2] = (temp >> 16) & 0x;
+ ctm->matrix[3] = temp & 0x;
+
+ temp = intel_de_read(dev_priv, CGM_PIPE_CSC_COEFF45(pipe));
+ ctm->matrix[4] = (temp >> 16) & 0x;
+ ctm->matrix[5] = temp & 0x;
+
+ temp = intel_de_read(dev_priv, CGM_PIPE_CSC_COEFF67(pipe));
+ ctm->matrix[6] = (temp >> 16) & 0x;
+ ctm->matrix[7] = temp & 0x;
+
+ temp = intel_de_read(dev_priv, CGM_PIPE_CSC_COEFF8(pipe));
+ ctm->matrix[8] = (temp >> 16) & 0x;
+
+ return blob;
+}
+
+static void chv_read_csc(struct intel_crtc_state *crtc_state)
+{
+ struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
+
+ if (crtc_state->cgm_mode & CGM_PIPE_MODE_CSC)
+ crtc_state->hw.ctm = chv_read_cgm_ctm(crtc);
+}
+
static struct drm_property_blob *ilk_read_lut_8(struct intel_crtc *crtc)
{
struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
@@ -2145,6 +2191,7 @@ void intel_color_init(struct intel_crtc *crtc)
dev_priv->display.color_commit = i9xx_color_commit;
dev_priv->display.load_luts = chv_load_luts;
dev_priv->display.read_luts = chv_read_luts;
+ dev_priv->display.read_csc = chv_read_csc;
} else if (INTEL_GEN(dev_priv) >= 4) {
dev_priv->display.color_check = i9xx_color_check;
dev_priv->display.color_commit = i9xx_color_commit;
--
2.20.1
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 7/7] FOR_TESTING_ONLY: Print coeffs of hw and sw CTM
Signed-off-by: Bhanuprakash Modem
---
drivers/gpu/drm/i915/display/intel_color.c | 5 +
1 file changed, 5 insertions(+)
diff --git a/drivers/gpu/drm/i915/display/intel_color.c
b/drivers/gpu/drm/i915/display/intel_color.c
index 8f9727553c45..caf4c3442b9e 100644
--- a/drivers/gpu/drm/i915/display/intel_color.c
+++ b/drivers/gpu/drm/i915/display/intel_color.c
@@ -1909,6 +1909,8 @@ bool intel_csc_equal(const struct intel_crtc_state
*current_config,
u16 coeffs[9];
int i;
+ DRM_DEBUG_KMS("Bhanu debug--> sw_ctm[%s] hw_ctm[%s]", yesno(!!blob1),
yesno(!!blob2));
+
if (!blob1 != !blob2)
return false;
@@ -1923,6 +1925,9 @@ bool intel_csc_equal(const struct intel_crtc_state
*current_config,
else
ilk_csc_convert_ctm(current_config, coeffs);
+ for (i = 0; i < 9; i++)
+ DRM_DEBUG_KMS("Bhanu debug--> sw_ctm[%d]=0x%x
hw_ctm[%d]=0x%llx", i, coeffs[i], i, ctm2->matrix[i]);
+
for (i = 0; i < 9; i++) {
if (abs(coeffs[i] - ctm2->matrix[i]))
return false;
--
2.20.1
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 6/7] drm/i915/display: Extract icl_read_csc()
For icl+, add hw read out to create hw blob of ctm coeff values.
Cc: Swati Sharma
Cc: Uma Shankar
Signed-off-by: Bhanuprakash Modem
---
drivers/gpu/drm/i915/display/intel_color.c | 55 ++
1 file changed, 55 insertions(+)
diff --git a/drivers/gpu/drm/i915/display/intel_color.c
b/drivers/gpu/drm/i915/display/intel_color.c
index 877833f294bb..8f9727553c45 100644
--- a/drivers/gpu/drm/i915/display/intel_color.c
+++ b/drivers/gpu/drm/i915/display/intel_color.c
@@ -396,6 +396,60 @@ static void icl_load_csc_matrix(const struct
intel_crtc_state *crtc_state)
crtc_state->csc_mode);
}
+static struct drm_property_blob *icl_read_output_csc_matrix(struct intel_crtc
*crtc)
+{
+ struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
+ enum pipe pipe = crtc->pipe;
+ struct drm_property_blob *blob;
+ struct drm_color_ctm *ctm;
+ u32 temp;
+
+ blob = drm_property_create_blob(&dev_priv->drm,
+ sizeof(struct drm_color_ctm),
+ NULL);
+ if (IS_ERR(blob))
+ return NULL;
+
+ ctm = blob->data;
+
+ temp = intel_de_read(dev_priv, PIPE_CSC_OUTPUT_COEFF_RY_GY(pipe));
+ ctm->matrix[0] = (temp >> 16) & 0x;
+ ctm->matrix[1] = temp & 0x;
+
+ temp = intel_de_read(dev_priv, PIPE_CSC_OUTPUT_COEFF_BY(pipe));
+ ctm->matrix[2] = (temp >> 16) & 0x;
+
+ temp = intel_de_read(dev_priv, PIPE_CSC_OUTPUT_COEFF_RU_GU(pipe));
+ ctm->matrix[3] = (temp >> 16) & 0x;
+ ctm->matrix[4] = temp & 0x;
+
+ temp = intel_de_read(dev_priv, PIPE_CSC_OUTPUT_COEFF_BU(pipe));
+ ctm->matrix[5] = (temp >> 16) & 0x;
+
+ temp = intel_de_read(dev_priv, PIPE_CSC_OUTPUT_COEFF_RV_GV(pipe));
+ ctm->matrix[6] = (temp >> 16) & 0x;
+ ctm->matrix[7] = temp & 0x;
+
+ temp = intel_de_read(dev_priv, PIPE_CSC_OUTPUT_COEFF_BV(pipe));
+ ctm->matrix[8] = (temp >> 16) & 0x;
+
+ return blob;
+}
+
+static void icl_read_csc(struct intel_crtc_state *crtc_state)
+{
+ struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
+
+ if (!crtc_state->csc_enable)
+ return;
+
+ if (crtc_state->csc_mode & ICL_CSC_ENABLE)
+ crtc_state->hw.ctm = ilk_read_csc_matrix(crtc);
+
+ if (crtc_state->csc_mode & ICL_OUTPUT_CSC_ENABLE)
+ crtc_state->hw.ctm = icl_read_output_csc_matrix(crtc);
+}
+
static void chv_csc_convert_ctm(const struct drm_color_ctm *ctm, u16 coeffs[9])
{
int i;
@@ -2271,6 +2325,7 @@ void intel_color_init(struct intel_crtc *crtc)
if (INTEL_GEN(dev_priv) >= 11) {
dev_priv->display.load_luts = icl_load_luts;
dev_priv->display.read_luts = icl_read_luts;
+ dev_priv->display.read_csc = icl_read_csc;
} else if (IS_CANNONLAKE(dev_priv) || IS_GEMINILAKE(dev_priv)) {
dev_priv->display.load_luts = glk_load_luts;
dev_priv->display.read_luts = glk_read_luts;
--
2.20.1
___
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 5/7] drm/i915/display: Extract ilk_read_csc()
For ilk+, add hw read out to create hw blob of ctm coeff values.
Cc: Swati Sharma
Cc: Uma Shankar
Signed-off-by: Bhanuprakash Modem
---
drivers/gpu/drm/i915/display/intel_color.c | 52 ++
1 file changed, 52 insertions(+)
diff --git a/drivers/gpu/drm/i915/display/intel_color.c
b/drivers/gpu/drm/i915/display/intel_color.c
index 15f97fbb77b3..877833f294bb 100644
--- a/drivers/gpu/drm/i915/display/intel_color.c
+++ b/drivers/gpu/drm/i915/display/intel_color.c
@@ -321,6 +321,54 @@ static void ilk_load_csc_matrix(const struct
intel_crtc_state *crtc_state)
crtc_state->csc_mode);
}
+static struct drm_property_blob *ilk_read_csc_matrix(struct intel_crtc *crtc)
+{
+ struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
+ enum pipe pipe = crtc->pipe;
+ struct drm_property_blob *blob;
+ struct drm_color_ctm *ctm;
+ u32 temp;
+
+ blob = drm_property_create_blob(&dev_priv->drm,
+ sizeof(struct drm_color_ctm),
+ NULL);
+ if (IS_ERR(blob))
+ return NULL;
+
+ ctm = blob->data;
+
+ temp = intel_de_read(dev_priv, PIPE_CSC_COEFF_RY_GY(pipe));
+ ctm->matrix[0] = (temp >> 16) & 0x;
+ ctm->matrix[1] = temp & 0x;
+
+ temp = intel_de_read(dev_priv, PIPE_CSC_COEFF_BY(pipe));
+ ctm->matrix[2] = (temp >> 16) & 0x;
+
+ temp = intel_de_read(dev_priv, PIPE_CSC_COEFF_RU_GU(pipe));
+ ctm->matrix[3] = (temp >> 16) & 0x;
+ ctm->matrix[4] = temp & 0x;
+
+ temp = intel_de_read(dev_priv, PIPE_CSC_COEFF_BU(pipe));
+ ctm->matrix[5] = (temp >> 16) & 0x;
+
+ temp = intel_de_read(dev_priv, PIPE_CSC_COEFF_RV_GV(pipe));
+ ctm->matrix[6] = (temp >> 16) & 0x;
+ ctm->matrix[7] = temp & 0x;
+
+ temp = intel_de_read(dev_priv, PIPE_CSC_COEFF_BV(pipe));
+ ctm->matrix[8] = (temp >> 16) & 0x;
+
+ return blob;
+}
+
+static void ilk_read_csc(struct intel_crtc_state *crtc_state)
+{
+ struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
+
+ if (crtc_state->csc_enable)
+ crtc_state->hw.ctm = ilk_read_csc_matrix(crtc);
+}
+
static void icl_load_csc_matrix(const struct intel_crtc_state *crtc_state)
{
struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
@@ -2226,13 +2274,17 @@ void intel_color_init(struct intel_crtc *crtc)
} else if (IS_CANNONLAKE(dev_priv) || IS_GEMINILAKE(dev_priv)) {
dev_priv->display.load_luts = glk_load_luts;
dev_priv->display.read_luts = glk_read_luts;
+ dev_priv->display.read_csc = ilk_read_csc;
} else if (INTEL_GEN(dev_priv) >= 8) {
dev_priv->display.load_luts = bdw_load_luts;
+ dev_priv->display.read_csc = ilk_read_csc;
} else if (INTEL_GEN(dev_priv) >= 7) {
dev_priv->display.load_luts = ivb_load_luts;
+ dev_priv->display.read_csc = ilk_read_csc;
} else {
dev_priv->display.load_luts = ilk_load_luts;
dev_priv->display.read_luts = ilk_read_luts;
+ dev_priv->display.read_csc = ilk_read_csc;
}
}
--
2.20.1
___
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] ✗ Fi.CI.IGT: failure for drm/i915/hdcp: mst streams type1 capability check (rev2)
Below CI-IGT failures are unrelated
Pushed to drm-intel-next.
> -Original Message-
> From: Anshuman Gupta
> Sent: Monday, March 22, 2021 10:49 AM
> To: intel-gfx@lists.freedesktop.org; Vudum, Lakshminarayana
>
> Subject: Re: ✗ Fi.CI.IGT: failure for drm/i915/hdcp: mst streams type1
> capability
> check (rev2)
>
> On 2021-03-19 at 13:26:16 +, Patchwork wrote:
> > == Series Details ==
> >
> > Series: drm/i915/hdcp: mst streams type1 capability check (rev2)
> > URL : https://patchwork.freedesktop.org/series/86345/
> > State : failure
> >
> > == Summary ==
> >
> > CI Bug Log - changes from CI_DRM_9874_full -> Patchwork_19809_full
> >
> >
> > Summary
> > ---
> >
> > **FAILURE**
> >
> > Serious unknown changes coming with Patchwork_19809_full absolutely
> need to be
> > verified manually.
> >
> > If you think the reported changes have nothing to do with the changes
> > introduced in Patchwork_19809_full, please notify your bug team to allow
> them
> > to document this new failure mode, which will reduce false positives in
> > CI.
> >
> >
> >
> > Possible new issues
> > ---
> >
> > Here are the unknown changes that may have been introduced in
> Patchwork_19809_full:
> >
> > ### IGT changes ###
> >
> > Possible regressions
> >
> > * igt@kms_flip_tiling@flip-y-tiled@edp-1-pipe-c:
> > - shard-skl: NOTRUN -> [FAIL][1]
> >[1]:
> > https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19809/shard-skl6/ig
> > t@kms_flip_tiling@flip-y-ti...@edp-1-pipe-c.html
> Hi Lakshmi ,
> Above CI-IGT failures are not related to this patch, this patch is just a
> rebase and
> CI results were green at Rev1.
> https://patchwork.freedesktop.org/series/86345/#rev1
> Could please raise the issue for above failure and re-report the result.
>
> Thanks,
> Anshuman Gupta.
> >
> >
> >
> > ### Piglit changes ###
> >
> > Possible regressions
> >
> > * spec@glsl-4.20@execution@vs_in@vs-input-double_dmat3-
> uint_uvec3_array3-position (NEW):
> > - {pig-icl-1065g7}: NOTRUN -> [CRASH][2] +1 similar issue
> >[2]:
> > https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19809/pig-icl-1065g
> > 7/spec@glsl-4.20@execution@vs_in@vs-input-double_dmat3-
> uint_uvec3_arra
> > y3-position.html
> >
> > * spec@glsl-4.20@execution@vs_in@vs-input-ubyte_uvec4-short_ivec4-
> position-double_dmat3 (NEW):
> > - {pig-icl-1065g7}: NOTRUN -> [INCOMPLETE][3] +3 similar issues
> >[3]:
> > https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19809/pig-icl-1065g
> > 7/spec@glsl-4.20@execution@vs_in@vs-input-ubyte_uvec4-short_ivec4-posi
> > tion-double_dmat3.html
> >
> >
> > New tests
> > -
> >
> > New tests have been introduced between CI_DRM_9874_full and
> Patchwork_19809_full:
> >
> > ### New Piglit tests (6) ###
> >
> > * spec@glsl-4.20@execution@vs_in@vs-input-double_dmat2x3-position-
> double_dvec3:
> > - Statuses : 1 incomplete(s)
> > - Exec time: [0.0] s
> >
> > * spec@glsl-4.20@execution@vs_in@vs-input-double_dmat3-
> uint_uvec3_array3-position:
> > - Statuses : 1 crash(s)
> > - Exec time: [1.02] s
> >
> > * spec@glsl-4.20@execution@vs_in@vs-input-float_float-position-
> double_dvec3:
> > - Statuses : 1 crash(s)
> > - Exec time: [1.06] s
> >
> > * spec@glsl-4.20@execution@vs_in@vs-input-position-int_ivec4_array3-
> double_dvec2_array2:
> > - Statuses : 1 incomplete(s)
> > - Exec time: [0.0] s
> >
> > * spec@glsl-4.20@execution@vs_in@vs-input-ubyte_uvec3-short_int-
> position-double_dvec4:
> > - Statuses : 1 incomplete(s)
> > - Exec time: [0.0] s
> >
> > * spec@glsl-4.20@execution@vs_in@vs-input-ubyte_uvec4-short_ivec4-
> position-double_dmat3:
> > - Statuses : 1 incomplete(s)
> > - Exec time: [0.0] s
> >
> >
> >
> > Known issues
> >
> >
> > Here are the changes found in Patchwork_19809_full that come from known
> issues:
> >
> > ### IGT changes ###
> >
> > Issues hit
> >
> > * igt@feature_discovery@chamelium:
> > - shard-iclb: NOTRUN -> [SKIP][4] ([fdo#111827])
> >[4]:
> > https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19809/shard-iclb5/i
> > gt@feature_discov...@chamelium.html
> >
> > * igt@gem_create@create-massive:
> > - shard-kbl: NOTRUN -> [DMESG-WARN][5] ([i915#3002])
> >[5]:
> > https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19809/shard-kbl2/ig
> > t@gem_cre...@create-massive.html
> >
> > * igt@gem_ctx_persistence@clone:
> > - shard-snb: NOTRUN -> [SKIP][6] ([fdo#109271] / [i915#1099])
> > +6
> similar issues
> >[6]:
> > https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19809/shard-snb5/ig
> > t@gem_ctx_persiste...@clone.html
> >
> > * igt@gem_ctx_sseu@mmap-args:
> > - shard-kbl: NOTRUN -> [SKIP][7] ([fdo#109271]) +11 similar
> > issues
> >[7]:
> > https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19809/shard-kbl2/ig
Re: [Intel-gfx] i915: v5.10.23: kernel hangs at boot when external monitor is connected?!
Hi, On Sun, Mar 21, 2021 at 12:44:24PM +0100, Thomas Meyer wrote: > Hi, > > when booting with an external monitor connected the boot process seems to stop > in the kernel. No additional output is show, it just hangs. > > kernel is 5.10.23 and driver is i915. When unplugging and reset computer, the > system starts normal. Any ideas what could be the culprit and what to enable > in kernel config to get a bit more insight what's probably going on? Thanks for the report. Please open a ticket at https://gitlab.freedesktop.org/drm/intel/-/issues/new You can capture a dmesg log by booting with drm.debug=0x1e, and either configuring netconsole as built-in, passing the required netconsole= boot params for it [1], or building i915 as a module and modprobing it only from the console (by booting with modprobe.blacklist=i915,snd_hda_intel). --Imre [1] https://www.kernel.org/doc/Documentation/networking/netconsole.txt > > mfg > thomas > ___ > Intel-gfx mailing list > Intel-gfx@lists.freedesktop.org > https://lists.freedesktop.org/mailman/listinfo/intel-gfx ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
