[Intel-gfx] [PATCH 5/7] drm/i915/display: Extract ilk_read_csc()

[Bhanuprakash Modem]

For ilk+, add hw read out to create hw blob of ctm coeff values.

Cc: Swati Sharma <swati2.sha...@intel.com>
Cc: Uma Shankar <uma.shan...@intel.com>
Signed-off-by: Bhanuprakash Modem <bhanuprakash.mo...@intel.com>
---
 drivers/gpu/drm/i915/display/intel_color.c | 52 ++++++++++++++++++++++
 1 file changed, 52 insertions(+)

diff --git a/drivers/gpu/drm/i915/display/intel_color.c 
b/drivers/gpu/drm/i915/display/intel_color.c
index 15f97fbb77b3..877833f294bb 100644
--- a/drivers/gpu/drm/i915/display/intel_color.c
+++ b/drivers/gpu/drm/i915/display/intel_color.c
@@ -321,6 +321,54 @@ static void ilk_load_csc_matrix(const struct 
intel_crtc_state *crtc_state)
                       crtc_state->csc_mode);
 }
 
+static struct drm_property_blob *ilk_read_csc_matrix(struct intel_crtc *crtc)
+{
+       struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
+       enum pipe pipe = crtc->pipe;
+       struct drm_property_blob *blob;
+       struct drm_color_ctm *ctm;
+       u32 temp;
+
+       blob = drm_property_create_blob(&dev_priv->drm,
+                                       sizeof(struct drm_color_ctm),
+                                       NULL);
+       if (IS_ERR(blob))
+               return NULL;
+
+       ctm = blob->data;
+
+       temp = intel_de_read(dev_priv, PIPE_CSC_COEFF_RY_GY(pipe));
+       ctm->matrix[0] = (temp >> 16) & 0xffff;
+       ctm->matrix[1] = temp & 0xffff;
+
+       temp = intel_de_read(dev_priv, PIPE_CSC_COEFF_BY(pipe));
+       ctm->matrix[2] = (temp >> 16) & 0xffff;
+
+       temp = intel_de_read(dev_priv, PIPE_CSC_COEFF_RU_GU(pipe));
+       ctm->matrix[3] = (temp >> 16) & 0xffff;
+       ctm->matrix[4] = temp & 0xffff;
+
+       temp = intel_de_read(dev_priv, PIPE_CSC_COEFF_BU(pipe));
+       ctm->matrix[5] = (temp >> 16) & 0xffff;
+
+       temp = intel_de_read(dev_priv, PIPE_CSC_COEFF_RV_GV(pipe));
+       ctm->matrix[6] = (temp >> 16) & 0xffff;
+       ctm->matrix[7] = temp & 0xffff;
+
+       temp = intel_de_read(dev_priv, PIPE_CSC_COEFF_BV(pipe));
+       ctm->matrix[8] = (temp >> 16) & 0xffff;
+
+       return blob;
+}
+
+static void ilk_read_csc(struct intel_crtc_state *crtc_state)
+{
+       struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
+
+       if (crtc_state->csc_enable)
+               crtc_state->hw.ctm = ilk_read_csc_matrix(crtc);
+}
+
 static void icl_load_csc_matrix(const struct intel_crtc_state *crtc_state)
 {
        struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
@@ -2226,13 +2274,17 @@ void intel_color_init(struct intel_crtc *crtc)
                } else if (IS_CANNONLAKE(dev_priv) || IS_GEMINILAKE(dev_priv)) {
                        dev_priv->display.load_luts = glk_load_luts;
                        dev_priv->display.read_luts = glk_read_luts;
+                       dev_priv->display.read_csc = ilk_read_csc;
                } else if (INTEL_GEN(dev_priv) >= 8) {
                        dev_priv->display.load_luts = bdw_load_luts;
+                       dev_priv->display.read_csc = ilk_read_csc;
                } else if (INTEL_GEN(dev_priv) >= 7) {
                        dev_priv->display.load_luts = ivb_load_luts;
+                       dev_priv->display.read_csc = ilk_read_csc;
                } else {
                        dev_priv->display.load_luts = ilk_load_luts;
                        dev_priv->display.read_luts = ilk_read_luts;
+                       dev_priv->display.read_csc = ilk_read_csc;
                }
        }
 
-- 
2.20.1

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