[Intel-gfx] [PATCH v2] drm/i915: Check for fused or unused pipes
We may have fused or unused pipes in our system. Let's check that the pipe
in question is within limits of accessible pipes. In case, that we are not
able to access the pipe, we return early with a warning.
v2: Rephrasing of the commit message (Jani)
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=103206
Reported-by: Thomas Gleixner
Tested-by: Jaswinder Singh Rajput
Suggested-by: Jani Nikula
Reviewed-by: Jani Nikula
Signed-off-by: Mika Kahola
---
drivers/gpu/drm/i915/intel_audio.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/intel_audio.c
b/drivers/gpu/drm/i915/intel_audio.c
index f1502a0..522d54f 100644
--- a/drivers/gpu/drm/i915/intel_audio.c
+++ b/drivers/gpu/drm/i915/intel_audio.c
@@ -779,7 +779,7 @@ static struct intel_encoder *get_saved_enc(struct
drm_i915_private *dev_priv,
{
struct intel_encoder *encoder;
- if (WARN_ON(pipe >= INTEL_INFO(dev_priv)->num_pipes))
+ if (WARN_ON(pipe >= ARRAY_SIZE(dev_priv->av_enc_map)))
return NULL;
/* MST */
--
2.7.4
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Re: [Intel-gfx] Linux kernel: drivers/gpu/drm/i915/i915_gem.c: i915_gem_pread_ioctl similar Double-Fetch bug
On Sat, 16 Dec 2017, sohu0106 wrote: > I found a similar Double-Fetch bug in drivers/gpu/drm/i915/i915_gem.c > when I was examining the source code. Similar to what? > In function i915_gem_pread_ioctl(), the driver check user space data > by pointer data_ptr via access_ok() in line 694, and after run a > while, in function shmem_pread_slow in line 657 or shmem_pread_fast in > line 639, finally it use __copy_to_user with no check user space > pointer. > > If the args->data_ptr is modified by a user thread under race > condition between the check and __copy_to_user operations, for example > changing to a kernel address, this will lead to Arbitrary kernel > address writing(caused by __copy_to_user() ). See drm_ioctl() for why this is not a possible scenario. BR, Jani. -- Jani Nikula, Intel Open Source Technology Center ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 04/45] gpu: drm: remove duplicate includes
These duplicate includes have been found with scripts/checkincludes.pl but they have been removed manually to avoid removing false positives. Signed-off-by: Pravin Shedge --- drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c | 1 - drivers/gpu/drm/amd/amdgpu/mxgpu_vi.c | 1 - drivers/gpu/drm/amd/amdgpu/vce_v3_0.c | 1 - drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager_vi.c | 1 - drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 3 --- drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c | 1 - drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c | 1 - drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c | 1 - drivers/gpu/drm/amd/powerplay/smumgr/rv_smumgr.c | 1 - drivers/gpu/drm/bridge/panel.c| 1 - drivers/gpu/drm/drm_drv.c | 1 - drivers/gpu/drm/i915/intel_dsi_vbt.c | 1 - drivers/gpu/drm/nouveau/nvkm/subdev/bus/nv04.c| 2 -- drivers/gpu/drm/panel/panel-raspberrypi-touchscreen.c | 1 - 14 files changed, 17 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c index 9ecdf62..7fd0599 100644 --- a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c @@ -44,7 +44,6 @@ #include "gca/gfx_8_0_d.h" #include "gca/gfx_8_0_enum.h" #include "gca/gfx_8_0_sh_mask.h" -#include "gca/gfx_8_0_enum.h" #include "dce/dce_10_0_d.h" #include "dce/dce_10_0_sh_mask.h" diff --git a/drivers/gpu/drm/amd/amdgpu/mxgpu_vi.c b/drivers/gpu/drm/amd/amdgpu/mxgpu_vi.c index c25a831..aad4134 100644 --- a/drivers/gpu/drm/amd/amdgpu/mxgpu_vi.c +++ b/drivers/gpu/drm/amd/amdgpu/mxgpu_vi.c @@ -37,7 +37,6 @@ #include "gmc/gmc_8_2_sh_mask.h" #include "oss/oss_3_0_d.h" #include "oss/oss_3_0_sh_mask.h" -#include "gca/gfx_8_0_sh_mask.h" #include "dce/dce_10_0_d.h" #include "dce/dce_10_0_sh_mask.h" #include "smu/smu_7_1_3_d.h" diff --git a/drivers/gpu/drm/amd/amdgpu/vce_v3_0.c b/drivers/gpu/drm/amd/amdgpu/vce_v3_0.c index cf81065..b526623 100644 --- a/drivers/gpu/drm/amd/amdgpu/vce_v3_0.c +++ b/drivers/gpu/drm/amd/amdgpu/vce_v3_0.c @@ -34,7 +34,6 @@ #include "vce/vce_3_0_sh_mask.h" #include "oss/oss_3_0_d.h" #include "oss/oss_3_0_sh_mask.h" -#include "gca/gfx_8_0_d.h" #include "smu/smu_7_1_2_d.h" #include "smu/smu_7_1_2_sh_mask.h" #include "gca/gfx_8_0_d.h" diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager_vi.c b/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager_vi.c index 2fbce57..8266a3f 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager_vi.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager_vi.c @@ -24,7 +24,6 @@ #include "kfd_device_queue_manager.h" #include "gca/gfx_8_0_enum.h" #include "gca/gfx_8_0_sh_mask.h" -#include "gca/gfx_8_0_enum.h" #include "oss/oss_3_0_sh_mask.h" static bool set_cache_memory_policy_vi(struct device_queue_manager *dqm, diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c index f71fe6d..b825dcb 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c @@ -23,7 +23,6 @@ * */ -#include "dm_services_types.h" #include "dc.h" #include "dc/inc/core_types.h" @@ -66,8 +65,6 @@ #include "soc15_common.h" #endif -#include "modules/inc/mod_freesync.h" - #include "i2caux_interface.h" /* basic init/fini API */ diff --git a/drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c b/drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c index 9c18efd..3f55dbc 100644 --- a/drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c +++ b/drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c @@ -40,7 +40,6 @@ #include "dce/dce_mem_input.h" #include "dce/dce_link_encoder.h" #include "dce/dce_stream_encoder.h" -#include "dce/dce_mem_input.h" #include "dce/dce_ipp.h" #include "dce/dce_transform.h" #include "dce/dce_opp.h" diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c index 961ad5c..8d5d4c2 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c +++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c @@ -39,7 +39,6 @@ #include "ipp.h" #include "mpc.h" #include "reg_helper.h" -#include "custom_float.h" #include "dcn10_hubp.h" #define CTX \ diff --git a/drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c b/drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c index bd6be77..ebbe8a1 100644 --- a/drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c +++ b/drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c @@ -44,7 +44,6 @@ #include "smu7_hwmgr.h" #include "hardwaremanager.h" -#include "ppatomctrl.h" #include "atombios.h" #include "pppcielanes.h" diff --git a/drivers/gpu/drm/amd/powerplay/smumgr/rv_smumgr.c b/drivers/gpu/drm/amd/powerplay/smum
Re: [Intel-gfx] Warning in i915/intel_audio.c
On Fri, 2017-12-15 at 16:23 +0200, Mika Kahola wrote: > On Fri, 2017-12-15 at 19:20 +0530, Jaswinder Singh Rajput wrote: > > > > On Fri, 2017-12-15 at 14:44 +0200, Mika Kahola wrote: > > > > > > > > > Hi, > > > > > > This is a known issue. Could you try out this patch to see if > > > that > > > would fix this issue for you? > > > > > > https://patchwork.freedesktop.org/series/35389/ > > > > > Yes, Thanks. It works :-) > Great that it worked for you! > > > > > > > When this patch will merge with linus kernel. > If you can, you may add a Tested-by tag on the patch. It will help > the > review process. This patch needs a review before its merged to our > drm- > tip tree and eventually further on to Linus tree. > Sure, kindly add me in CC and add my tag to the patch: Tested-by: Jaswinder Singh Rajput > > > > > > Thanks, > > -- > > Jaswinder Singh Rajput > > > > > > > > > > > On Fri, 2017-12-15 at 17:08 +0530, Jaswinder Singh Rajput wrote: > > > > > > > > > > > > > > > > Hello friends, > > > > > > > > I am getting multiple warnings in i915/intel_audio.c . I am > > > > attaching > > > > dmesg, config and lsmod for your reference. > > > > > > > > > > > > [0.390606] WARN_ON(pipe >= intel_info((dev_priv))- > > > > >num_pipes) > > > > [0.390619] WARNING: CPU: 1 PID: 1051 at > > > > drivers/gpu/drm/i915/intel_audio.c:757 get_saved_enc+0x74/0x80 > > > > [0.390620] Modules linked in: > > > > [0.390621] CPU: 1 PID: 1051 Comm: kworker/1:2 Not tainted > > > > 4.15.0-rc3+ #13 > > > > [0.390622] Hardware name: Gigabyte Technology Co., Ltd. > > > > H81M-S/H81M-S, BIOS F2 08/19/2015 > > > > [0.390624] Workqueue: events azx_probe_work > > > > [0.390625] RIP: 0010:get_saved_enc+0x74/0x80 > > > > [0.390626] RSP: 0018:9b650061fba8 EFLAGS: 00010292 > > > > [0.390627] RAX: 0032 RBX: 888e17384cb8 > > > > RCX: > > > > > > > > [0.390627] RDX: 0001 RSI: 0002 > > > > RDI: > > > > 97032bb0 > > > > [0.390627] RBP: 888e1738 R08: 0032 > > > > R09: > > > > 0032 > > > > [0.390628] R10: 888e19cc3840 R11: 000344e0 > > > > R12: > > > > 0100 > > > > [0.390628] R13: 0001 R14: 888e168fba08 > > > > R15: > > > > 888e168fba10 > > > > [0.390629] FS: () > > > > GS:888e1f30() > > > > knlGS: > > > > [0.390629] CS: 0010 DS: ES: CR0: > > > > 80050033 > > > > [0.390630] CR2: 7f7dd01c6914 CR3: 3da0a001 > > > > CR4: > > > > 000606e0 > > > > [0.390630] Call Trace: > > > > [0.390633] i915_audio_component_get_eld+0x43/0xe0 > > > > [0.390635] hdmi_present_sense+0x95/0x330 > > > > [0.390636] generic_hdmi_build_controls+0x143/0x1e0 > > > > [0.390638] snd_hda_codec_build_controls+0x178/0x1c0 > > > > [0.390639] ? snd_hda_codec_build_pcms+0x14f/0x1a0 > > > > [0.390641] hda_codec_driver_probe+0x76/0x100 > > > > [0.390644] driver_probe_device+0x27d/0x310 > > > > [0.390645] ? __driver_attach+0xa0/0xa0 > > > > [0.390646] bus_for_each_drv+0x50/0x80 > > > > [0.390647] __device_attach+0xb0/0x110 > > > > [0.390649] bus_probe_device+0x82/0x90 > > > > [0.390650] device_add+0x2dc/0x570 > > > > [0.390652] snd_hdac_device_register+0xd/0x40 > > > > [0.390654] snd_hda_codec_configure+0x32/0x120 > > > > [0.390655] azx_codec_configure+0x2a/0x60 > > > > [0.390656] azx_probe_work+0x40c/0x860 > > > > [0.390659] process_one_work+0x1d2/0x3c0 > > > > [0.390660] worker_thread+0x42/0x3e0 > > > > [0.390661] kthread+0xf0/0x130 > > > > [0.390663] ? > > > > trace_event_raw_event_workqueue_work+0x80/0x80 > > > > [0.390664] ? kthread_create_worker_on_cpu+0x40/0x40 > > > > [0.390665] ? call_usermodehelper_exec_async+0x11c/0x120 > > > > [0.390667] ret_from_fork+0x1f/0x30 > > > > [0.390668] Code: 83 c2 01 39 d1 7f e0 31 c0 c3 83 78 70 0b > > > > 74 > > > > f9 > > > > 31 > > > > c0 85 d2 74 cb eb f1 48 c7 c6 d0 c0 df 96 48 c7 c7 57 dd db 96 > > > > e8 > > > > 9c > > > > 2d > > > > bf ff <0f> ff 31 c0 c3 0f 1f 80 00 00 00 00 41 57 4d 89 c7 41 > > > > 56 > > > > 49 > > > > 89 > > > > [0.390679] ---[ end trace 9a14f34c58dc94ff ]--- > > > > > > > > > > > > Thanks, > > > > -- > > > > Jaswinder Singh Rajput > > > > ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH i-g-t] trace.pl: handle request tracepoint fields regardless of their order
On 15/12/2017 18:04, Lionel Landwerlin wrote:
It doesn't look like tracepoint have any guarantee to have always the
same ordering of their parameter. Instead of relying on a predefined
regexp, let's split the parameters on commas and access the values
through a map.
Signed-off-by: Lionel Landwerlin
---
scripts/trace.pl | 30 --
1 file changed, 20 insertions(+), 10 deletions(-)
diff --git a/scripts/trace.pl b/scripts/trace.pl
index aed9b20d..41b1ae46 100755
--- a/scripts/trace.pl
+++ b/scripts/trace.pl
@@ -302,15 +302,25 @@ die if scalar(@args);
@ARGV = @args;
+sub params_to_map
+{
+my @arr = split /,\s*/, $_;
shift @_ instead of $_ or unexpected things happen.
+my %keyvals = ();
No need to init to nothing.
+foreach my $el (@arr) {
+my @keyval = split /=/, $el;
+$keyvals{$keyval[0]} = $keyval[1];
+}
+return %keyvals;
+}
+
sub parse_req
{
my ($line, $tp) = @_;
- state %cache;
-
- $cache{$tp} = qr/(\d+)\.(\d+):.*$tp.*ring=(\d+), ctx=(\d+), seqno=(\d+),
global(?:_seqno)?=(\d+)/ unless exists $cache{$tp}; >
- if ($line =~ $cache{$tp}) {
- return ($1, $2, $3, $4, $5, $6);
I was worried about regexp cache removal, since it was very important
for performance. So I tried with this patch and indeed the script was
~2.4x slower.
I'll see if I can do better.
Regards,
Tvrtko
+ if ($line =~ /(\d+)\.(\d+):.*$tp:\s*(.*)/) {
+ my %params = params_to_map($3);
+ return ($1, $2, $params{"ring"}, $params{"ctx"},
$params{"seqno"},
+ exists $params{"global"} ? $params{"global"} :
$params{"global_seqno"});
} else {
return undef;
}
@@ -319,12 +329,12 @@ sub parse_req
sub parse_req_hw
{
my ($line, $tp) = @_;
- state %cache;
-
- $cache{$tp} = qr/(\d+)\.(\d+):.*$tp.*ring=(\d+), ctx=(\d+),
seqno=(\d+), global(?:_seqno)?=(\d+), port=(\d+)/ unless exists $cache{$tp};
- if ($line =~ $cache{$tp}) {
- return ($1, $2, $3, $4, $5, $6, $7);
+ if ($line =~ /(\d+)\.(\d+):.*$tp:\s*(.*)/) {
+ my %params = params_to_map($3);
+ return ($1, $2, $params{"ring"}, $params{"ctx"},
$params{"seqno"},
+ exists $params{"global"} ? $params{"global"} :
$params{"global_seqno"},
+ $params{"port"});
} else {
return undef;
}
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Re: [Intel-gfx] Warning in i915/intel_audio.c
On Fri, 2017-12-15 at 14:44 +0200, Mika Kahola wrote: > Hi, > > This is a known issue. Could you try out this patch to see if that > would fix this issue for you? > > https://patchwork.freedesktop.org/series/35389/ > Yes, Thanks. It works :-) When this patch will merge with linus kernel. Thanks, -- Jaswinder Singh Rajput > On Fri, 2017-12-15 at 17:08 +0530, Jaswinder Singh Rajput wrote: > > > > Hello friends, > > > > I am getting multiple warnings in i915/intel_audio.c . I am > > attaching > > dmesg, config and lsmod for your reference. > > > > > > [0.390606] WARN_ON(pipe >= intel_info((dev_priv))->num_pipes) > > [0.390619] WARNING: CPU: 1 PID: 1051 at > > drivers/gpu/drm/i915/intel_audio.c:757 get_saved_enc+0x74/0x80 > > [0.390620] Modules linked in: > > [0.390621] CPU: 1 PID: 1051 Comm: kworker/1:2 Not tainted > > 4.15.0-rc3+ #13 > > [0.390622] Hardware name: Gigabyte Technology Co., Ltd. > > H81M-S/H81M-S, BIOS F2 08/19/2015 > > [0.390624] Workqueue: events azx_probe_work > > [0.390625] RIP: 0010:get_saved_enc+0x74/0x80 > > [0.390626] RSP: 0018:9b650061fba8 EFLAGS: 00010292 > > [0.390627] RAX: 0032 RBX: 888e17384cb8 RCX: > > > > [0.390627] RDX: 0001 RSI: 0002 RDI: > > 97032bb0 > > [0.390627] RBP: 888e1738 R08: 0032 R09: > > 0032 > > [0.390628] R10: 888e19cc3840 R11: 000344e0 R12: > > 0100 > > [0.390628] R13: 0001 R14: 888e168fba08 R15: > > 888e168fba10 > > [0.390629] FS: () > > GS:888e1f30() > > knlGS: > > [0.390629] CS: 0010 DS: ES: CR0: 80050033 > > [0.390630] CR2: 7f7dd01c6914 CR3: 3da0a001 CR4: > > 000606e0 > > [0.390630] Call Trace: > > [0.390633] i915_audio_component_get_eld+0x43/0xe0 > > [0.390635] hdmi_present_sense+0x95/0x330 > > [0.390636] generic_hdmi_build_controls+0x143/0x1e0 > > [0.390638] snd_hda_codec_build_controls+0x178/0x1c0 > > [0.390639] ? snd_hda_codec_build_pcms+0x14f/0x1a0 > > [0.390641] hda_codec_driver_probe+0x76/0x100 > > [0.390644] driver_probe_device+0x27d/0x310 > > [0.390645] ? __driver_attach+0xa0/0xa0 > > [0.390646] bus_for_each_drv+0x50/0x80 > > [0.390647] __device_attach+0xb0/0x110 > > [0.390649] bus_probe_device+0x82/0x90 > > [0.390650] device_add+0x2dc/0x570 > > [0.390652] snd_hdac_device_register+0xd/0x40 > > [0.390654] snd_hda_codec_configure+0x32/0x120 > > [0.390655] azx_codec_configure+0x2a/0x60 > > [0.390656] azx_probe_work+0x40c/0x860 > > [0.390659] process_one_work+0x1d2/0x3c0 > > [0.390660] worker_thread+0x42/0x3e0 > > [0.390661] kthread+0xf0/0x130 > > [0.390663] ? trace_event_raw_event_workqueue_work+0x80/0x80 > > [0.390664] ? kthread_create_worker_on_cpu+0x40/0x40 > > [0.390665] ? call_usermodehelper_exec_async+0x11c/0x120 > > [0.390667] ret_from_fork+0x1f/0x30 > > [0.390668] Code: 83 c2 01 39 d1 7f e0 31 c0 c3 83 78 70 0b 74 > > f9 > > 31 > > c0 85 d2 74 cb eb f1 48 c7 c6 d0 c0 df 96 48 c7 c7 57 dd db 96 e8 > > 9c > > 2d > > bf ff <0f> ff 31 c0 c3 0f 1f 80 00 00 00 00 41 57 4d 89 c7 41 56 49 > > 89 > > [0.390679] ---[ end trace 9a14f34c58dc94ff ]--- > > > > > > Thanks, > > -- > > Jaswinder Singh Rajput > > ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] Linux kernel: drivers/gpu/drm/i915/i915_gem.c: i915_gem_pread_ioctl similar Double-Fetch bug
Hi, I found a similar Double-Fetch bug in drivers/gpu/drm/i915/i915_gem.c when I was examining the source code. In function i915_gem_pread_ioctl(), the driver check user space data by pointer data_ptr via access_ok() in line 694, and after run a while, in function shmem_pread_slow in line 657 or shmem_pread_fast in line 639, finally it use __copy_to_user with no check user space pointer. If the args->data_ptr is modified by a user thread under race condition between the check and __copy_to_user operations, for example changing to a kernel address, this will lead to Arbitrary kernel address writing(caused by __copy_to_user() ). I am looking forward to a reply on this, thank you! ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915: Check for fused or unused pipes (rev3)
== Series Details == Series: drm/i915: Check for fused or unused pipes (rev3) URL : https://patchwork.freedesktop.org/series/35389/ State : success == Summary == Series 35389v3 drm/i915: Check for fused or unused pipes https://patchwork.freedesktop.org/api/1.0/series/35389/revisions/3/mbox/ Test debugfs_test: Subgroup read_all_entries: dmesg-warn -> PASS (fi-elk-e7500) fdo#103989 +1 Test kms_psr_sink_crc: Subgroup psr_basic: dmesg-warn -> PASS (fi-skl-6700hq) fdo#101144 fdo#103989 https://bugs.freedesktop.org/show_bug.cgi?id=103989 fdo#101144 https://bugs.freedesktop.org/show_bug.cgi?id=101144 fi-bdw-5557u total:288 pass:267 dwarn:0 dfail:0 fail:0 skip:21 time:433s fi-bdw-gvtdvmtotal:288 pass:264 dwarn:0 dfail:0 fail:0 skip:24 time:439s fi-blb-e6850 total:288 pass:223 dwarn:1 dfail:0 fail:0 skip:64 time:386s fi-bsw-n3050 total:288 pass:242 dwarn:0 dfail:0 fail:0 skip:46 time:498s fi-bwr-2160 total:288 pass:183 dwarn:0 dfail:0 fail:0 skip:105 time:277s fi-bxt-dsi total:288 pass:258 dwarn:0 dfail:0 fail:0 skip:30 time:495s fi-bxt-j4205 total:288 pass:259 dwarn:0 dfail:0 fail:0 skip:29 time:493s fi-byt-j1900 total:288 pass:253 dwarn:0 dfail:0 fail:0 skip:35 time:478s fi-elk-e7500 total:224 pass:163 dwarn:15 dfail:0 fail:0 skip:45 fi-gdg-551 total:7pass:5dwarn:1 dfail:0 fail:0 skip:0 fi-glk-1 total:288 pass:260 dwarn:0 dfail:0 fail:0 skip:28 time:538s fi-hsw-4770 total:288 pass:261 dwarn:0 dfail:0 fail:0 skip:27 time:407s fi-hsw-4770r total:288 pass:261 dwarn:0 dfail:0 fail:0 skip:27 time:414s fi-ivb-3520m total:288 pass:259 dwarn:0 dfail:0 fail:0 skip:29 time:466s fi-ivb-3770 total:288 pass:255 dwarn:0 dfail:0 fail:0 skip:33 time:428s fi-kbl-7500u total:288 pass:263 dwarn:1 dfail:0 fail:0 skip:24 time:480s fi-kbl-7560u total:288 pass:268 dwarn:1 dfail:0 fail:0 skip:19 time:520s fi-kbl-7567u total:288 pass:268 dwarn:0 dfail:0 fail:0 skip:20 time:467s fi-kbl-r total:288 pass:260 dwarn:1 dfail:0 fail:0 skip:27 time:530s fi-pnv-d510 total:288 pass:222 dwarn:1 dfail:0 fail:0 skip:65 time:588s fi-skl-6260u total:288 pass:268 dwarn:0 dfail:0 fail:0 skip:20 time:443s fi-skl-6600u total:288 pass:260 dwarn:1 dfail:0 fail:0 skip:27 time:527s fi-skl-6700hqtotal:288 pass:262 dwarn:0 dfail:0 fail:0 skip:26 time:564s fi-skl-6700k2total:288 pass:264 dwarn:0 dfail:0 fail:0 skip:24 time:507s fi-skl-6770hqtotal:288 pass:268 dwarn:0 dfail:0 fail:0 skip:20 time:504s fi-skl-gvtdvmtotal:288 pass:265 dwarn:0 dfail:0 fail:0 skip:23 time:446s fi-snb-2520m total:288 pass:248 dwarn:0 dfail:0 fail:0 skip:40 time:548s fi-snb-2600 total:288 pass:248 dwarn:0 dfail:0 fail:0 skip:40 time:416s Blacklisted hosts: fi-cfl-s2total:288 pass:262 dwarn:0 dfail:0 fail:0 skip:26 time:582s fi-cnl-y total:288 pass:262 dwarn:0 dfail:0 fail:0 skip:26 time:638s fi-glk-dsi total:166 pass:56 dwarn:0 dfail:2 fail:0 skip:107 b415f7d96ee2a0a2870e367c7e43f4d9f0af1ba5 drm-tip: 2017y-12m-17d-19h-00m-50s UTC integration manifest c6f0c07d5ba9 drm/i915: Check for fused or unused pipes == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_7521/issues.html ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✗ Fi.CI.IGT: failure for drm/i915: Check for fused or unused pipes (rev3)
== Series Details == Series: drm/i915: Check for fused or unused pipes (rev3) URL : https://patchwork.freedesktop.org/series/35389/ State : failure == Summary == Test kms_chv_cursor_fail: Subgroup pipe-c-64x64-bottom-edge: pass -> INCOMPLETE (shard-hsw) Test drv_suspend: Subgroup fence-restore-untiled: pass -> INCOMPLETE (shard-hsw) fdo#103540 +1 Test drv_module_reload: Subgroup basic-reload: dmesg-warn -> PASS (shard-snb) fdo#102848 dmesg-warn -> PASS (shard-hsw) fdo#102707 Test kms_setmode: Subgroup clone-exclusive-crtc: warn -> PASS (shard-snb) fdo#104312 Test kms_flip: Subgroup wf_vblank-vs-dpms: pass -> DMESG-WARN (shard-hsw) fdo#102614 Test kms_frontbuffer_tracking: Subgroup fbc-1p-offscren-pri-shrfb-draw-blt: pass -> FAIL (shard-snb) fdo#101623 Test gem_tiled_swapping: Subgroup non-threaded: pass -> INCOMPLETE (shard-snb) fdo#104218 +1 fdo#103540 https://bugs.freedesktop.org/show_bug.cgi?id=103540 fdo#102848 https://bugs.freedesktop.org/show_bug.cgi?id=102848 fdo#102707 https://bugs.freedesktop.org/show_bug.cgi?id=102707 fdo#104312 https://bugs.freedesktop.org/show_bug.cgi?id=104312 fdo#102614 https://bugs.freedesktop.org/show_bug.cgi?id=102614 fdo#101623 https://bugs.freedesktop.org/show_bug.cgi?id=101623 fdo#104218 https://bugs.freedesktop.org/show_bug.cgi?id=104218 shard-hswtotal:2518 pass:1423 dwarn:2 dfail:0 fail:10 skip:1079 time:8174s shard-snbtotal:2620 pass:1248 dwarn:1 dfail:0 fail:12 skip:1357 time:7494s Blacklisted hosts: shard-apltotal:2712 pass:1687 dwarn:1 dfail:1 fail:22 skip:1001 time:13896s shard-kbltotal:2712 pass:1805 dwarn:1 dfail:1 fail:25 skip:880 time:11086s == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_7521/shards.html ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [CI v2 2/5] drm/vblank: Restoring vblank counts after device runtime PM events.
The HW frame counter can get reset when devices enters low power
states and this messes up any following vblank count updates. So, compute
the missed vblank interrupts for that low power state duration using time
stamps. This is similar to _crtc_vblank_on() except that it doesn't enable
vblank interrupts because this function is expected to be called from
the driver _enable_vblank() vfunc.
Signed-off-by: Dhinakaran Pandiyan
---
drivers/gpu/drm/drm_vblank.c | 33 +
include/drm/drm_vblank.h | 1 +
2 files changed, 34 insertions(+)
diff --git a/drivers/gpu/drm/drm_vblank.c b/drivers/gpu/drm/drm_vblank.c
index 7eee82c06ed8..494e2cff6e55 100644
--- a/drivers/gpu/drm/drm_vblank.c
+++ b/drivers/gpu/drm/drm_vblank.c
@@ -1230,6 +1230,39 @@ void drm_crtc_vblank_on(struct drm_crtc *crtc)
}
EXPORT_SYMBOL(drm_crtc_vblank_on);
+void drm_crtc_vblank_restore(struct drm_device *dev, unsigned int pipe)
+{
+ ktime_t t_vblank;
+ struct drm_vblank_crtc *vblank;
+ int framedur_ns;
+ u64 diff_ns;
+ u32 cur_vblank, diff = 1;
+ int count = DRM_TIMESTAMP_MAXRETRIES;
+
+ if (WARN_ON(pipe >= dev->num_crtcs))
+ return;
+
+ vblank = &dev->vblank[pipe];
+ WARN_ONCE((drm_debug & DRM_UT_VBL) && !vblank->framedur_ns,
+ "Cannot compute missed vblanks without frame duration\n");
+ framedur_ns = vblank->framedur_ns;
+
+ do {
+ cur_vblank = __get_vblank_counter(dev, pipe);
+ drm_get_last_vbltimestamp(dev, pipe, &t_vblank, false);
+ } while (cur_vblank != __get_vblank_counter(dev, pipe) && --count > 0);
+
+ diff_ns = ktime_to_ns(ktime_sub(t_vblank, vblank->time));
+ if (framedur_ns)
+ diff = DIV_ROUND_CLOSEST_ULL(diff_ns, framedur_ns);
+
+
+ DRM_DEBUG_VBL("missed %d vblanks in %lld ns, frame duration=%d ns,
hw_diff=%d\n",
+ diff, diff_ns, framedur_ns, cur_vblank - vblank->last);
+ store_vblank(dev, pipe, diff, t_vblank, cur_vblank);
+}
+EXPORT_SYMBOL(drm_crtc_vblank_restore);
+
static void drm_legacy_vblank_pre_modeset(struct drm_device *dev,
unsigned int pipe)
{
diff --git a/include/drm/drm_vblank.h b/include/drm/drm_vblank.h
index 848b463a0af5..aafcbef91bd7 100644
--- a/include/drm/drm_vblank.h
+++ b/include/drm/drm_vblank.h
@@ -180,6 +180,7 @@ void drm_crtc_vblank_off(struct drm_crtc *crtc);
void drm_crtc_vblank_reset(struct drm_crtc *crtc);
void drm_crtc_vblank_on(struct drm_crtc *crtc);
u32 drm_crtc_accurate_vblank_count(struct drm_crtc *crtc);
+void drm_crtc_vblank_restore(struct drm_device *dev, unsigned int pipe);
bool drm_calc_vbltimestamp_from_scanoutpos(struct drm_device *dev,
unsigned int pipe, int *max_error,
--
2.11.0
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[Intel-gfx] [CI v2 4/5] drm/i915: Introduce a non-blocking power domain for vblank interrupts
When DC states are enabled and PSR is active, the hardware enters DC5/DC6
states resulting in frame counter resets. The frame counter resets mess
up the vblank counting logic. So in order to disable DC states when
vblank interrupts are required and to disallow DC states when vblanks
interrupts are already enabled, introduce a new power domain. Since this
power domain reference needs to be acquired and released in atomic context,
the corresponding _get() and _put() methods skip the power_domain mutex.
Signed-off-by: Dhinakaran Pandiyan
---
drivers/gpu/drm/i915/i915_drv.h | 8 ++
drivers/gpu/drm/i915/intel_drv.h| 3 +
drivers/gpu/drm/i915/intel_runtime_pm.c | 196 +---
3 files changed, 193 insertions(+), 14 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index a10f31c9e4a9..5494582fdfea 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -397,6 +397,7 @@ enum intel_display_power_domain {
POWER_DOMAIN_AUX_C,
POWER_DOMAIN_AUX_D,
POWER_DOMAIN_GMBUS,
+ POWER_DOMAIN_VBLANK,
POWER_DOMAIN_MODESET,
POWER_DOMAIN_GT_IRQ,
POWER_DOMAIN_INIT,
@@ -1476,7 +1477,14 @@ struct i915_power_well {
bool has_vga:1;
bool has_fuses:1;
} hsw;
+ struct {
+ bool was_disabled;
+ } dc_off;
};
+
+ spinlock_t lock;
+ bool supports_atomic_ctx;
+
const struct i915_power_well_ops *ops;
};
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index 30f791f89d64..164e62cb047b 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -1797,6 +1797,9 @@ bool intel_display_power_get_if_enabled(struct
drm_i915_private *dev_priv,
enum intel_display_power_domain domain);
void intel_display_power_put(struct drm_i915_private *dev_priv,
enum intel_display_power_domain domain);
+void intel_display_power_vblank_get(struct drm_i915_private *dev_priv,
+ bool *needs_restore);
+void intel_display_power_vblank_put(struct drm_i915_private *dev_priv);
static inline void
assert_rpm_device_not_suspended(struct drm_i915_private *dev_priv)
diff --git a/drivers/gpu/drm/i915/intel_runtime_pm.c
b/drivers/gpu/drm/i915/intel_runtime_pm.c
index 992caec1fbc4..9cbb332cb418 100644
--- a/drivers/gpu/drm/i915/intel_runtime_pm.c
+++ b/drivers/gpu/drm/i915/intel_runtime_pm.c
@@ -56,6 +56,16 @@ static struct i915_power_well *
lookup_power_well(struct drm_i915_private *dev_priv,
enum i915_power_well_id power_well_id);
+/* optimize for the case when this function is called from atomic context,
+ * although this is unlikely */
+#define power_well_lock(power_well, flags) \
+ if (likely(power_well->supports_atomic_ctx))\
+ spin_lock_irqsave(&power_well->lock, flags)
+
+#define power_well_unlock(power_well, flags) \
+ if (likely(power_well->supports_atomic_ctx))\
+ spin_unlock_irqrestore(&power_well->lock, flags)
+
const char *
intel_display_power_domain_str(enum intel_display_power_domain domain)
{
@@ -126,6 +136,8 @@ intel_display_power_domain_str(enum
intel_display_power_domain domain)
return "AUX_D";
case POWER_DOMAIN_GMBUS:
return "GMBUS";
+ case POWER_DOMAIN_VBLANK:
+ return "VBLANK";
case POWER_DOMAIN_INIT:
return "INIT";
case POWER_DOMAIN_MODESET:
@@ -141,6 +153,9 @@ intel_display_power_domain_str(enum
intel_display_power_domain domain)
static void intel_power_well_enable(struct drm_i915_private *dev_priv,
struct i915_power_well *power_well)
{
+ if (power_well->supports_atomic_ctx)
+ assert_spin_locked(&power_well->lock);
+
DRM_DEBUG_KMS("enabling %s\n", power_well->name);
power_well->ops->enable(dev_priv, power_well);
power_well->hw_enabled = true;
@@ -149,19 +164,34 @@ static void intel_power_well_enable(struct
drm_i915_private *dev_priv,
static void intel_power_well_disable(struct drm_i915_private *dev_priv,
struct i915_power_well *power_well)
{
+ if (power_well->supports_atomic_ctx)
+ assert_spin_locked(&power_well->lock);
+
DRM_DEBUG_KMS("disabling %s\n", power_well->name);
power_well->hw_enabled = false;
power_well->ops->disable(dev_priv, power_well);
}
-static void intel_power_well_get(struct drm_i915_private *dev_priv,
+
+static void __intel_power_well_get(struct drm_i915_private *dev_priv,
struct i915_power_well *power_well)
{
if (!power_well->count++)
[Intel-gfx] [CI v2 1/5] drm/vblank: Do not update vblank counts if vblanks are already disabled.
Updating the vblank counts requires register reads and these reads may not
return meaningful values after the vblank interrupts are disabled as the
device may go to low power state. An additional change would be to allow
the driver to save the vblank counts before entering a low power state, but
that's for the future.
Also, disable vblanks after reading the HW counter in the case where
_crtc_vblank_off() is disabling vblanks.
Signed-off-by: Dhinakaran Pandiyan
---
drivers/gpu/drm/drm_vblank.c | 23 +--
1 file changed, 9 insertions(+), 14 deletions(-)
diff --git a/drivers/gpu/drm/drm_vblank.c b/drivers/gpu/drm/drm_vblank.c
index 32d9bcf5be7f..7eee82c06ed8 100644
--- a/drivers/gpu/drm/drm_vblank.c
+++ b/drivers/gpu/drm/drm_vblank.c
@@ -347,23 +347,14 @@ void drm_vblank_disable_and_save(struct drm_device *dev,
unsigned int pipe)
spin_lock_irqsave(&dev->vblank_time_lock, irqflags);
/*
-* Only disable vblank interrupts if they're enabled. This avoids
-* calling the ->disable_vblank() operation in atomic context with the
-* hardware potentially runtime suspended.
-*/
- if (vblank->enabled) {
- __disable_vblank(dev, pipe);
- vblank->enabled = false;
- }
-
- /*
-* Always update the count and timestamp to maintain the
+* Update the count and timestamp to maintain the
* appearance that the counter has been ticking all along until
* this time. This makes the count account for the entire time
* between drm_crtc_vblank_on() and drm_crtc_vblank_off().
*/
drm_update_vblank_count(dev, pipe, false);
-
+ __disable_vblank(dev, pipe);
+ vblank->enabled = false;
spin_unlock_irqrestore(&dev->vblank_time_lock, irqflags);
}
@@ -1122,8 +1113,12 @@ void drm_crtc_vblank_off(struct drm_crtc *crtc)
pipe, vblank->enabled, vblank->inmodeset);
/* Avoid redundant vblank disables without previous
-* drm_crtc_vblank_on(). */
- if (drm_core_check_feature(dev, DRIVER_ATOMIC) || !vblank->inmodeset)
+* drm_crtc_vblank_on() and only disable them if they're enabled. This
+* avoids calling the ->disable_vblank() operation in atomic context
+* with the hardware potentially runtime suspended.
+*/
+ if ((drm_core_check_feature(dev, DRIVER_ATOMIC) || !vblank->inmodeset)
&&
+ vblank->enabled)
drm_vblank_disable_and_save(dev, pipe);
wake_up(&vblank->queue);
--
2.11.0
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[Intel-gfx] [CI v2 3/5] drm/i915: Use an atomic_t array to track power domain use count.
Convert the power_domains->domain_use_count array that tracks per-domain
use count to atomic_t type. This is needed to be able to read/write the use
counts outside of the power domain mutex.
Signed-off-by: Dhinakaran Pandiyan
---
drivers/gpu/drm/i915/i915_debugfs.c | 2 +-
drivers/gpu/drm/i915/i915_drv.h | 2 +-
drivers/gpu/drm/i915/intel_runtime_pm.c | 11 +--
3 files changed, 7 insertions(+), 8 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_debugfs.c
b/drivers/gpu/drm/i915/i915_debugfs.c
index d8c6ec3cca71..2c4fd5149ffc 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -2772,7 +2772,7 @@ static int i915_power_domain_info(struct seq_file *m,
void *unused)
for_each_power_domain(power_domain, power_well->domains)
seq_printf(m, " %-23s %d\n",
intel_display_power_domain_str(power_domain),
-power_domains->domain_use_count[power_domain]);
+
atomic_read(&power_domains->domain_use_count[power_domain]));
}
mutex_unlock(&power_domains->lock);
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 61196ff93901..a10f31c9e4a9 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -1490,7 +1490,7 @@ struct i915_power_domains {
int power_well_count;
struct mutex lock;
- int domain_use_count[POWER_DOMAIN_NUM];
+ atomic_t domain_use_count[POWER_DOMAIN_NUM];
struct i915_power_well *power_wells;
};
diff --git a/drivers/gpu/drm/i915/intel_runtime_pm.c
b/drivers/gpu/drm/i915/intel_runtime_pm.c
index 96ab74f3d101..992caec1fbc4 100644
--- a/drivers/gpu/drm/i915/intel_runtime_pm.c
+++ b/drivers/gpu/drm/i915/intel_runtime_pm.c
@@ -1453,7 +1453,7 @@ __intel_display_power_get_domain(struct drm_i915_private
*dev_priv,
for_each_power_domain_well(dev_priv, power_well, BIT_ULL(domain))
intel_power_well_get(dev_priv, power_well);
- power_domains->domain_use_count[domain]++;
+ atomic_inc(&power_domains->domain_use_count[domain]);
}
/**
@@ -1539,10 +1539,9 @@ void intel_display_power_put(struct drm_i915_private
*dev_priv,
mutex_lock(&power_domains->lock);
- WARN(!power_domains->domain_use_count[domain],
-"Use count on domain %s is already zero\n",
+ WARN(atomic_dec_return(&power_domains->domain_use_count[domain]) < 0,
+"Use count on domain %s was already zero\n",
intel_display_power_domain_str(domain));
- power_domains->domain_use_count[domain]--;
for_each_power_domain_well_rev(dev_priv, power_well, BIT_ULL(domain))
intel_power_well_put(dev_priv, power_well);
@@ -3049,7 +3048,7 @@ static void intel_power_domains_dump_info(struct
drm_i915_private *dev_priv)
for_each_power_domain(domain, power_well->domains)
DRM_DEBUG_DRIVER(" %-23s %d\n",
intel_display_power_domain_str(domain),
-
power_domains->domain_use_count[domain]);
+
atomic_read(&power_domains->domain_use_count[domain]));
}
}
@@ -3092,7 +3091,7 @@ void intel_power_domains_verify_state(struct
drm_i915_private *dev_priv)
domains_count = 0;
for_each_power_domain(domain, power_well->domains)
- domains_count +=
power_domains->domain_use_count[domain];
+ domains_count +=
atomic_read(&power_domains->domain_use_count[domain]);
if (power_well->count != domains_count) {
DRM_ERROR("power well %s refcount/domain refcount
mismatch "
--
2.11.0
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[Intel-gfx] [CI v2 5/5] drm/i915: Use the vblank power domain disallow or disable DC states.
Disable DC states before enabling vblank interrupts and conversely
enable DC states after disabling. Since the frame counter may have got
reset between disabling and enabling, use drm_crtc_vblank_restore() to
compute the missed vblanks.
Signed-off-by: Dhinakaran Pandiyan
---
drivers/gpu/drm/i915/i915_irq.c | 6 ++
1 file changed, 6 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index 3517c6548e2c..88b4ceac55d0 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -2963,6 +2963,11 @@ static int gen8_enable_vblank(struct drm_device *dev,
unsigned int pipe)
{
struct drm_i915_private *dev_priv = to_i915(dev);
unsigned long irqflags;
+ bool needs_restore = false;
+
+ intel_display_power_vblank_get(dev_priv, &needs_restore);
+ if (needs_restore)
+ drm_crtc_vblank_restore(dev, pipe);
spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
bdw_enable_pipe_irq(dev_priv, pipe, GEN8_PIPE_VBLANK);
@@ -3015,6 +3020,7 @@ static void gen8_disable_vblank(struct drm_device *dev,
unsigned int pipe)
spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
bdw_disable_pipe_irq(dev_priv, pipe, GEN8_PIPE_VBLANK);
spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
+ intel_display_power_vblank_put(dev_priv);
}
static void ibx_irq_reset(struct drm_i915_private *dev_priv)
--
2.11.0
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[Intel-gfx] [PATCH] drm/i915: prefer i915_gem_object_has_pages()
We have an existing helper for testing obj->mm.pages, so use it.
Signed-off-by: Matthew Auld
Cc: Chris Wilson
---
drivers/gpu/drm/i915/i915_gem.c | 2 +-
drivers/gpu/drm/i915/selftests/huge_pages.c | 2 +-
2 files changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
index dca15c13af35..5b4cfb20de97 100644
--- a/drivers/gpu/drm/i915/i915_gem.c
+++ b/drivers/gpu/drm/i915/i915_gem.c
@@ -2596,7 +2596,7 @@ static int i915_gem_object_get_pages(struct
drm_i915_gem_object *obj)
}
err = obj->ops->get_pages(obj);
- GEM_BUG_ON(!err && IS_ERR_OR_NULL(obj->mm.pages));
+ GEM_BUG_ON(!err && !i915_gem_object_has_pages(obj));
return err;
}
diff --git a/drivers/gpu/drm/i915/selftests/huge_pages.c
b/drivers/gpu/drm/i915/selftests/huge_pages.c
index e6b31041cc88..2ea69394f428 100644
--- a/drivers/gpu/drm/i915/selftests/huge_pages.c
+++ b/drivers/gpu/drm/i915/selftests/huge_pages.c
@@ -1637,7 +1637,7 @@ static int igt_shrink_thp(void *arg)
* shmem to truncate our pages.
*/
i915_gem_shrink_all(i915);
- if (!IS_ERR_OR_NULL(obj->mm.pages)) {
+ if (i915_gem_object_has_pages(obj)) {
pr_err("shrink-all didn't truncate the pages\n");
err = -EINVAL;
goto out_close;
--
2.14.3
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Re: [Intel-gfx] [PATCH v2] drm/i915: Protect DDI port to DPLL map from theoretical race.
Op 15-12-17 om 23:43 schreef Rodrigo Vivi:
> In case we have multiple modesets for different connectors
> happening in parallel we could have a race on the RMW on these
> shared registers.
>
> This possibility was initially raised by Paulo when reviewing
> commit '555e38d27317 ("drm/i915/cnl: DDI - PLL mapping")'
> but the original possibility comes from commit '5416d871136d
> ("drm/i915/skl: Set the eDP link rate on DPLL0")'. Or maybe
> later when atomic commits entered into picture.
>
> Apparently the discussion around this topic showed that the
> right solution would be on serializing the atomic commits in
> a way that we don't have the possibility of races here since
> if that parallel modeset happenings apparently many other
> things will be on fire.
>
> Code is there since SKL and there was no report of issue,
> but since we never looked back to that serialization possibility,
> and also we don't have an igt case for that it is better to at
> least protect this corner.
>
> Suggested-by: Paulo Zanoni
> Fixes: 555e38d27317 ("drm/i915/cnl: DDI - PLL mapping")
> Fixes: 5416d871136d ("drm/i915/skl: Set the eDP link rate on DPLL0")
> Cc: Paulo Zanoni
> Cc: Ville Syrjälä
> Cc: Maarten Lankhorst maarten.lankho...@linux.intel.com
> Signed-off-by: Rodrigo Vivi
> ---
> drivers/gpu/drm/i915/intel_ddi.c | 4
> 1 file changed, 4 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/intel_ddi.c
> b/drivers/gpu/drm/i915/intel_ddi.c
> index 369f780588fb..f624ba8e23be 100644
> --- a/drivers/gpu/drm/i915/intel_ddi.c
> +++ b/drivers/gpu/drm/i915/intel_ddi.c
> @@ -2095,6 +2095,8 @@ static void intel_ddi_clk_select(struct intel_encoder
> *encoder,
> if (WARN_ON(!pll))
> return;
>
> + mutex_lock(&dev_priv->dpll_lock);
> +
> if (IS_CANNONLAKE(dev_priv)) {
> /* Configure DPCLKA_CFGCR0 to map the DPLL to the DDI. */
> val = I915_READ(DPCLKA_CFGCR0);
> @@ -2124,6 +2126,8 @@ static void intel_ddi_clk_select(struct intel_encoder
> *encoder,
> } else if (INTEL_INFO(dev_priv)->gen < 9) {
> I915_WRITE(PORT_CLK_SEL(port), hsw_pll_to_ddi_pll_sel(pll));
> }
> +
> + mutex_unlock(&dev_priv->dpll_lock);
> }
>
> static void intel_ddi_clk_disable(struct intel_encoder *encoder)
What is the difference between v1 and this? Changelog would be nice, or a
comment that you resent it. :)
Patch looks sane, so Reviewed-by: Maarten Lankhorst
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Re: [Intel-gfx] [PATCH] drm/i915: prefer i915_gem_object_has_pages()
Quoting Matthew Auld (2017-12-18 10:38:55) > We have an existing helper for testing obj->mm.pages, so use it. > > Signed-off-by: Matthew Auld > Cc: Chris Wilson Reviewed-by: Chris Wilson -Chris ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✗ Fi.CI.BAT: failure for series starting with [CI,v2,1/5] drm/vblank: Do not update vblank counts if vblanks are already disabled.
== Series Details == Series: series starting with [CI,v2,1/5] drm/vblank: Do not update vblank counts if vblanks are already disabled. URL : https://patchwork.freedesktop.org/series/35501/ State : failure == Summary == Series 35501v1 series starting with [CI,v2,1/5] drm/vblank: Do not update vblank counts if vblanks are already disabled. https://patchwork.freedesktop.org/api/1.0/series/35501/revisions/1/mbox/ Test debugfs_test: Subgroup read_all_entries: pass -> INCOMPLETE (fi-snb-2520m) fdo#103713 Test gem_exec_suspend: Subgroup basic-s3: pass -> INCOMPLETE (fi-bxt-j4205) Test kms_psr_sink_crc: Subgroup psr_basic: dmesg-warn -> PASS (fi-skl-6700hq) fdo#101144 fdo#103713 https://bugs.freedesktop.org/show_bug.cgi?id=103713 fdo#101144 https://bugs.freedesktop.org/show_bug.cgi?id=101144 fi-bdw-5557u total:288 pass:267 dwarn:0 dfail:0 fail:0 skip:21 time:432s fi-bdw-gvtdvmtotal:288 pass:264 dwarn:0 dfail:0 fail:0 skip:24 time:435s fi-blb-e6850 total:288 pass:223 dwarn:1 dfail:0 fail:0 skip:64 time:391s fi-bsw-n3050 total:288 pass:242 dwarn:0 dfail:0 fail:0 skip:46 time:496s fi-bwr-2160 total:288 pass:183 dwarn:0 dfail:0 fail:0 skip:105 time:275s fi-bxt-dsi total:288 pass:258 dwarn:0 dfail:0 fail:0 skip:30 time:495s fi-bxt-j4205 total:108 pass:96 dwarn:0 dfail:0 fail:0 skip:11 fi-byt-j1900 total:288 pass:253 dwarn:0 dfail:0 fail:0 skip:35 time:479s fi-byt-n2820 total:288 pass:249 dwarn:0 dfail:0 fail:0 skip:39 time:466s fi-elk-e7500 total:224 pass:163 dwarn:15 dfail:0 fail:0 skip:45 fi-gdg-551 total:7pass:5dwarn:1 dfail:0 fail:0 skip:0 fi-glk-1 total:288 pass:260 dwarn:0 dfail:0 fail:0 skip:28 time:533s fi-hsw-4770 total:288 pass:261 dwarn:0 dfail:0 fail:0 skip:27 time:403s fi-hsw-4770r total:288 pass:261 dwarn:0 dfail:0 fail:0 skip:27 time:412s fi-ilk-650 total:288 pass:228 dwarn:0 dfail:0 fail:0 skip:60 time:384s fi-ivb-3520m total:288 pass:259 dwarn:0 dfail:0 fail:0 skip:29 time:466s fi-ivb-3770 total:288 pass:255 dwarn:0 dfail:0 fail:0 skip:33 time:431s fi-kbl-7500u total:288 pass:263 dwarn:1 dfail:0 fail:0 skip:24 time:479s fi-kbl-7560u total:288 pass:268 dwarn:1 dfail:0 fail:0 skip:19 time:515s fi-kbl-7567u total:288 pass:268 dwarn:0 dfail:0 fail:0 skip:20 time:466s fi-kbl-r total:288 pass:260 dwarn:1 dfail:0 fail:0 skip:27 time:520s fi-pnv-d510 total:288 pass:222 dwarn:1 dfail:0 fail:0 skip:65 time:579s fi-skl-6260u total:288 pass:268 dwarn:0 dfail:0 fail:0 skip:20 time:443s fi-skl-6600u total:288 pass:260 dwarn:1 dfail:0 fail:0 skip:27 time:535s fi-skl-6700hqtotal:288 pass:262 dwarn:0 dfail:0 fail:0 skip:26 time:557s fi-skl-6700k2total:288 pass:264 dwarn:0 dfail:0 fail:0 skip:24 time:506s fi-skl-6770hqtotal:288 pass:268 dwarn:0 dfail:0 fail:0 skip:20 time:503s fi-skl-gvtdvmtotal:288 pass:265 dwarn:0 dfail:0 fail:0 skip:23 time:443s fi-snb-2520m total:3pass:2dwarn:0 dfail:0 fail:0 skip:0 fi-snb-2600 total:288 pass:248 dwarn:0 dfail:0 fail:0 skip:40 time:415s Blacklisted hosts: fi-cfl-s2total:288 pass:262 dwarn:0 dfail:0 fail:0 skip:26 time:596s fi-glk-dsi total:20 pass:19 dwarn:0 dfail:0 fail:0 skip:0 780afbc71018cfa8cca45143c55b2051330402b6 drm-tip: 2017y-12m-18d-09h-33m-33s UTC integration manifest bea77cd5e63e drm/i915: Use the vblank power domain disallow or disable DC states. 43de979e3ce8 drm/i915: Introduce a non-blocking power domain for vblank interrupts 5c292379a9e9 drm/i915: Use an atomic_t array to track power domain use count. fabd57888ef8 drm/vblank: Restoring vblank counts after device runtime PM events. 673aa493d715 drm/vblank: Do not update vblank counts if vblanks are already disabled. == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_7522/issues.html ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915: prefer i915_gem_object_has_pages()
== Series Details == Series: drm/i915: prefer i915_gem_object_has_pages() URL : https://patchwork.freedesktop.org/series/35502/ State : success == Summary == Series 35502v1 drm/i915: prefer i915_gem_object_has_pages() https://patchwork.freedesktop.org/api/1.0/series/35502/revisions/1/mbox/ Test debugfs_test: Subgroup read_all_entries: dmesg-warn -> PASS (fi-elk-e7500) fdo#103989 +1 pass -> INCOMPLETE (fi-snb-2520m) fdo#103713 fdo#103989 https://bugs.freedesktop.org/show_bug.cgi?id=103989 fdo#103713 https://bugs.freedesktop.org/show_bug.cgi?id=103713 fi-bdw-5557u total:288 pass:267 dwarn:0 dfail:0 fail:0 skip:21 time:432s fi-bdw-gvtdvmtotal:288 pass:264 dwarn:0 dfail:0 fail:0 skip:24 time:437s fi-blb-e6850 total:288 pass:223 dwarn:1 dfail:0 fail:0 skip:64 time:387s fi-bsw-n3050 total:288 pass:242 dwarn:0 dfail:0 fail:0 skip:46 time:502s fi-bwr-2160 total:288 pass:183 dwarn:0 dfail:0 fail:0 skip:105 time:275s fi-bxt-dsi total:288 pass:258 dwarn:0 dfail:0 fail:0 skip:30 time:494s fi-bxt-j4205 total:288 pass:259 dwarn:0 dfail:0 fail:0 skip:29 time:492s fi-byt-j1900 total:288 pass:253 dwarn:0 dfail:0 fail:0 skip:35 time:477s fi-byt-n2820 total:288 pass:249 dwarn:0 dfail:0 fail:0 skip:39 time:463s fi-elk-e7500 total:224 pass:163 dwarn:15 dfail:0 fail:0 skip:45 fi-gdg-551 total:7pass:5dwarn:1 dfail:0 fail:0 skip:0 fi-glk-1 total:288 pass:260 dwarn:0 dfail:0 fail:0 skip:28 time:526s fi-hsw-4770 total:288 pass:261 dwarn:0 dfail:0 fail:0 skip:27 time:408s fi-hsw-4770r total:288 pass:261 dwarn:0 dfail:0 fail:0 skip:27 time:415s fi-ilk-650 total:288 pass:228 dwarn:0 dfail:0 fail:0 skip:60 time:383s fi-ivb-3520m total:288 pass:259 dwarn:0 dfail:0 fail:0 skip:29 time:477s fi-ivb-3770 total:288 pass:255 dwarn:0 dfail:0 fail:0 skip:33 time:425s fi-kbl-7500u total:288 pass:263 dwarn:1 dfail:0 fail:0 skip:24 time:471s fi-kbl-7560u total:288 pass:268 dwarn:1 dfail:0 fail:0 skip:19 time:519s fi-kbl-7567u total:288 pass:268 dwarn:0 dfail:0 fail:0 skip:20 time:467s fi-kbl-r total:288 pass:260 dwarn:1 dfail:0 fail:0 skip:27 time:523s fi-pnv-d510 total:288 pass:222 dwarn:1 dfail:0 fail:0 skip:65 time:585s fi-skl-6260u total:288 pass:268 dwarn:0 dfail:0 fail:0 skip:20 time:439s fi-skl-6600u total:288 pass:260 dwarn:1 dfail:0 fail:0 skip:27 time:529s fi-skl-6700hqtotal:288 pass:261 dwarn:1 dfail:0 fail:0 skip:26 time:550s fi-skl-6700k2total:288 pass:264 dwarn:0 dfail:0 fail:0 skip:24 time:505s fi-skl-6770hqtotal:288 pass:268 dwarn:0 dfail:0 fail:0 skip:20 time:502s fi-skl-gvtdvmtotal:288 pass:265 dwarn:0 dfail:0 fail:0 skip:23 time:445s fi-snb-2520m total:3pass:2dwarn:0 dfail:0 fail:0 skip:0 fi-snb-2600 total:288 pass:248 dwarn:0 dfail:0 fail:0 skip:40 time:406s Blacklisted hosts: fi-cfl-s2total:288 pass:262 dwarn:0 dfail:0 fail:0 skip:26 time:592s fi-cnl-y total:210 pass:189 dwarn:0 dfail:0 fail:0 skip:20 fi-glk-dsi total:152 pass:138 dwarn:0 dfail:0 fail:0 skip:13 780afbc71018cfa8cca45143c55b2051330402b6 drm-tip: 2017y-12m-18d-09h-33m-33s UTC integration manifest b882bdbff832 drm/i915: prefer i915_gem_object_has_pages() == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_7523/issues.html ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH 1/3] drm/i915: Re-enable GGTT earlier after GPU reset
On 17/12/2017 13:28, Chris Wilson wrote:
Inside i915_gem_reset(), we start touching the HW and so require the
low-level HW to be re-enabled, in particular the PCI BARs.
Fixes: 7b6da818d86f ("drm/i915: Restore the kernel context after a GPU reset on an
idle engine")
Testcase: igt/drv_hangman # i915g/i915gm
Signed-off-by: Chris Wilson
Cc: Mika Kuoppala
Cc: Joonas Lahtinen
Cc: Michel Thierry
---
drivers/gpu/drm/i915/i915_drv.c | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index 6d39fdf2b604..72bea281edb7 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -1924,9 +1924,6 @@ void i915_reset(struct drm_i915_private *i915, unsigned
int flags)
goto taint;
}
- i915_gem_reset(i915);
- intel_overlay_reset(i915);
-
/* Ok, now get things going again... */
/*
@@ -1939,6 +1936,9 @@ void i915_reset(struct drm_i915_private *i915, unsigned
int flags)
goto error;
}
+ i915_gem_reset(i915);
+ intel_overlay_reset(i915);
+
/*
* Next we need to restore the context, but we don't use those
* yet either...
Looks fine to me.
Reviewed-by: Tvrtko Ursulin
Regards,
Tvrtko
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Re: [Intel-gfx] [PATCH 2/3] drm/i915: Show IPEIR and IPEHR in the engine dump
On 17/12/2017 13:28, Chris Wilson wrote:
A useful bit of information for inspecting GPU stalls from
intel_engine_dump() are the error registers, IPEIR and IPEHR.
Signed-off-by: Chris Wilson
Cc: Mika Kuoppala
Cc: Joonas Lahtinen
---
drivers/gpu/drm/i915/intel_engine_cs.c | 7 +++
1 file changed, 7 insertions(+)
diff --git a/drivers/gpu/drm/i915/intel_engine_cs.c
b/drivers/gpu/drm/i915/intel_engine_cs.c
index 510e0bc3a377..05bd9e17452c 100644
--- a/drivers/gpu/drm/i915/intel_engine_cs.c
+++ b/drivers/gpu/drm/i915/intel_engine_cs.c
@@ -1757,6 +1757,13 @@ void intel_engine_dump(struct intel_engine_cs *engine,
addr = intel_engine_get_last_batch_head(engine);
drm_printf(m, "\tBBADDR: 0x%08x_%08x\n",
upper_32_bits(addr), lower_32_bits(addr));
+ addr = I915_READ(RING_DMA_FADD(engine->mmio_base));
+ drm_printf(m, "\tDMA_FADDR: 0x%08x_%08x\n",
+ upper_32_bits(addr), lower_32_bits(addr));
ERror capture handles this register a bit differently.
+ drm_printf(m, "\tIPEIR: 0x%08x\n",
+ I915_READ(RING_IPEIR(engine->mmio_base)));
+ drm_printf(m, "\tIPEHR: 0x%08x\n",
+ I915_READ(RING_IPEHR(engine->mmio_base)));
This one as well two code paths depending on the gen.
Regards,
Tvrtko
if (HAS_EXECLISTS(dev_priv)) {
const u32 *hws =
&engine->status_page.page_addr[I915_HWS_CSB_BUF0_INDEX];
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Re: [Intel-gfx] [PATCH 2/3] drm/i915: Show IPEIR and IPEHR in the engine dump
Quoting Chris Wilson (2017-12-17 13:28:51) > A useful bit of information for inspecting GPU stalls from > intel_engine_dump() are the error registers, IPEIR and IPEHR. > > Signed-off-by: Chris Wilson > Cc: Mika Kuoppala > Cc: Joonas Lahtinen > --- > drivers/gpu/drm/i915/intel_engine_cs.c | 7 +++ > 1 file changed, 7 insertions(+) > > diff --git a/drivers/gpu/drm/i915/intel_engine_cs.c > b/drivers/gpu/drm/i915/intel_engine_cs.c > index 510e0bc3a377..05bd9e17452c 100644 > --- a/drivers/gpu/drm/i915/intel_engine_cs.c > +++ b/drivers/gpu/drm/i915/intel_engine_cs.c > @@ -1757,6 +1757,13 @@ void intel_engine_dump(struct intel_engine_cs *engine, > addr = intel_engine_get_last_batch_head(engine); > drm_printf(m, "BBADDR: 0x%08x_%08x\n", >upper_32_bits(addr), lower_32_bits(addr)); > + addr = I915_READ(RING_DMA_FADD(engine->mmio_base)); if (GEN >= 8) addr |= (u64)I915_READ(RING_DMA_FADD_UDW) << 32; -Chris ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH 2/3] drm/i915: Show IPEIR and IPEHR in the engine dump
Quoting Tvrtko Ursulin (2017-12-18 11:14:19) > > On 17/12/2017 13:28, Chris Wilson wrote: > > A useful bit of information for inspecting GPU stalls from > > intel_engine_dump() are the error registers, IPEIR and IPEHR. > > > > Signed-off-by: Chris Wilson > > Cc: Mika Kuoppala > > Cc: Joonas Lahtinen > > --- > > drivers/gpu/drm/i915/intel_engine_cs.c | 7 +++ > > 1 file changed, 7 insertions(+) > > > > diff --git a/drivers/gpu/drm/i915/intel_engine_cs.c > > b/drivers/gpu/drm/i915/intel_engine_cs.c > > index 510e0bc3a377..05bd9e17452c 100644 > > --- a/drivers/gpu/drm/i915/intel_engine_cs.c > > +++ b/drivers/gpu/drm/i915/intel_engine_cs.c > > @@ -1757,6 +1757,13 @@ void intel_engine_dump(struct intel_engine_cs > > *engine, > > addr = intel_engine_get_last_batch_head(engine); > > drm_printf(m, "BBADDR: 0x%08x_%08x\n", > > upper_32_bits(addr), lower_32_bits(addr)); > > + addr = I915_READ(RING_DMA_FADD(engine->mmio_base)); > > + drm_printf(m, "DMA_FADDR: 0x%08x_%08x\n", > > +upper_32_bits(addr), lower_32_bits(addr)); > > ERror capture handles this register a bit differently. > > > + drm_printf(m, "IPEIR: 0x%08x\n", > > +I915_READ(RING_IPEIR(engine->mmio_base))); > > + drm_printf(m, "IPEHR: 0x%08x\n", > > +I915_READ(RING_IPEHR(engine->mmio_base))); > > This one as well two code paths depending on the gen. My bad for assuming it was the same location, just per-engine-ified. -Chris ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH 1/3] drm/i915: Re-enable GGTT earlier after GPU reset
Quoting Tvrtko Ursulin (2017-12-18 11:11:49)
>
> On 17/12/2017 13:28, Chris Wilson wrote:
> > Inside i915_gem_reset(), we start touching the HW and so require the
> > low-level HW to be re-enabled, in particular the PCI BARs.
> >
> > Fixes: 7b6da818d86f ("drm/i915: Restore the kernel context after a GPU
> > reset on an idle engine")
> > Testcase: igt/drv_hangman # i915g/i915gm
> > Signed-off-by: Chris Wilson
> > Cc: Mika Kuoppala
> > Cc: Joonas Lahtinen
> > Cc: Michel Thierry
> > ---
> > drivers/gpu/drm/i915/i915_drv.c | 6 +++---
> > 1 file changed, 3 insertions(+), 3 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/i915_drv.c
> > b/drivers/gpu/drm/i915/i915_drv.c
> > index 6d39fdf2b604..72bea281edb7 100644
> > --- a/drivers/gpu/drm/i915/i915_drv.c
> > +++ b/drivers/gpu/drm/i915/i915_drv.c
> > @@ -1924,9 +1924,6 @@ void i915_reset(struct drm_i915_private *i915,
> > unsigned int flags)
> > goto taint;
> > }
> >
> > - i915_gem_reset(i915);
> > - intel_overlay_reset(i915);
> > -
> > /* Ok, now get things going again... */
> >
> > /*
> > @@ -1939,6 +1936,9 @@ void i915_reset(struct drm_i915_private *i915,
> > unsigned int flags)
> > goto error;
> > }
> >
> > + i915_gem_reset(i915);
> > + intel_overlay_reset(i915);
> > +
> > /*
> >* Next we need to restore the context, but we don't use those
> >* yet either...
> >
>
> Looks fine to me.
>
> Reviewed-by: Tvrtko Ursulin
Ta, pushed this one by itself so we can bring gdg back online.
-Chris
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[Intel-gfx] [PATCH v2] drm/i915: Show IPEIR and IPEHR in the engine dump
A useful bit of information for inspecting GPU stalls from
intel_engine_dump() are the error registers, IPEIR and IPEHR.
v2: Fixup gen changes in register offsets (Tvrtko)
Signed-off-by: Chris Wilson
Cc: Mika Kuoppala
Cc: Joonas Lahtinen
Cc: Tvrtko Ursulin
---
drivers/gpu/drm/i915/intel_engine_cs.c | 14 ++
1 file changed, 14 insertions(+)
diff --git a/drivers/gpu/drm/i915/intel_engine_cs.c
b/drivers/gpu/drm/i915/intel_engine_cs.c
index 510e0bc3a377..92b9e0dd6378 100644
--- a/drivers/gpu/drm/i915/intel_engine_cs.c
+++ b/drivers/gpu/drm/i915/intel_engine_cs.c
@@ -1757,6 +1757,20 @@ void intel_engine_dump(struct intel_engine_cs *engine,
addr = intel_engine_get_last_batch_head(engine);
drm_printf(m, "\tBBADDR: 0x%08x_%08x\n",
upper_32_bits(addr), lower_32_bits(addr));
+ addr = I915_READ(RING_DMA_FADD(engine->mmio_base));
+ if (INTEL_GEN(dev_priv) >= 8)
+ addr |= (u64)I915_READ(RING_DMA_FADD_UDW(engine->mmio_base)) <<
32;
+ drm_printf(m, "\tDMA_FADDR: 0x%08x_%08x\n",
+ upper_32_bits(addr), lower_32_bits(addr));
+ if (INTEL_GEN(dev_priv) >= 4) {
+ drm_printf(m, "\tIPEIR: 0x%08x\n",
+ I915_READ(RING_IPEIR(engine->mmio_base)));
+ drm_printf(m, "\tIPEHR: 0x%08x\n",
+ I915_READ(RING_IPEHR(engine->mmio_base)));
+ } else {
+ drm_printf(m, "\tIPEIR: 0x%08x\n", I915_READ(IPEIR));
+ drm_printf(m, "\tIPEHR: 0x%08x\n", I915_READ(IPEHR));
+ }
if (HAS_EXECLISTS(dev_priv)) {
const u32 *hws =
&engine->status_page.page_addr[I915_HWS_CSB_BUF0_INDEX];
--
2.15.1
___
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Re: [Intel-gfx] Question about CCS modifier on GLK
On Sun, Dec 17, 2017 at 10:45:13PM -0200, Gabriel Krisman Bertazi wrote: > > Hi Ben and list folks, > > I've been investigating some CI failures with the kms_ccs testcase in > the GLK hardware. The original bug is linked below, but there are other > more basic tests failing when trying CCS on pipe C. > > https://bugs.freedesktop.org/show_bug.cgi?id=104096 > > The reason for the failure is very straightforward, the function > skl_check_ccs_aux_surface() in intel_display.c rejects CCS modifiers for > PIPE_C, since that is not supported for SKL, KBL and as far as I can > tell APL as well. > > But, since I don't have the specs for GLK yet (it's not available in > 01.org), I can't tell if GLK will support it and the kernel must be > changed or if the testcase itself is bogus. My money is on the later, > but I could use a confirmation before writing down the patch. > > In short, does pipe C support render compression (ccs modifier) in glk? No. But the current code is somewhat busted anyway. See https://patchwork.freedesktop.org/series/29308/ -- Ville Syrjälä Intel OTC ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH i-g-t] intel_vbt_decode: Typo fixes
On Fri, Dec 15, 2017 at 02:59:36PM -0500, Adam Jackson wrote: > Signed-off-by: Adam Jackson > --- > tools/intel_vbt_decode.c | 4 ++-- > tools/intel_vbt_defs.h | 6 +++--- > 2 files changed, 5 insertions(+), 5 deletions(-) This mail was rejected by Patchwork because of "X-Mailer" header, indicating that it was sent with git send-email, is missing. I forced it through manually, so we will have CI feedback soon (so very necessary for this complex patch :-P). May I ask why is the header missing from your patch? I wonder whether should we relax patchwork's checks. -- Cheers, Arek ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915: prefer i915_gem_object_has_pages()
== Series Details == Series: drm/i915: prefer i915_gem_object_has_pages() URL : https://patchwork.freedesktop.org/series/35502/ State : success == Summary == Test kms_frontbuffer_tracking: Subgroup fbc-1p-offscren-pri-shrfb-draw-render: pass -> FAIL (shard-snb) fdo#101623 Test perf: Subgroup polling: fail -> PASS (shard-hsw) fdo#102252 Test drv_suspend: Subgroup debugfs-reader: skip -> PASS (shard-hsw) Test kms_setmode: Subgroup basic: pass -> FAIL (shard-hsw) fdo#99912 Test drv_selftest: Subgroup live_hangcheck: pass -> INCOMPLETE (shard-snb) fdo#104313 fdo#101623 https://bugs.freedesktop.org/show_bug.cgi?id=101623 fdo#102252 https://bugs.freedesktop.org/show_bug.cgi?id=102252 fdo#99912 https://bugs.freedesktop.org/show_bug.cgi?id=99912 fdo#104313 https://bugs.freedesktop.org/show_bug.cgi?id=104313 shard-hswtotal:2712 pass:1536 dwarn:2 dfail:0 fail:10 skip:1164 time:9369s shard-snbtotal:2694 pass:1288 dwarn:2 dfail:0 fail:12 skip:1391 time:7844s Blacklisted hosts: shard-apltotal:2690 pass:1664 dwarn:1 dfail:0 fail:23 skip:1001 time:13370s shard-kbltotal:2712 pass:1805 dwarn:2 dfail:1 fail:23 skip:881 time:11025s == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_7523/shards.html ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915: prefer i915_gem_object_has_pages()
Quoting Patchwork (2017-12-18 11:52:05) > == Series Details == > > Series: drm/i915: prefer i915_gem_object_has_pages() > URL : https://patchwork.freedesktop.org/series/35502/ > State : success > > == Summary == > > Test kms_frontbuffer_tracking: > Subgroup fbc-1p-offscren-pri-shrfb-draw-render: > pass -> FAIL (shard-snb) fdo#101623 > Test perf: > Subgroup polling: > fail -> PASS (shard-hsw) fdo#102252 > Test drv_suspend: > Subgroup debugfs-reader: > skip -> PASS (shard-hsw) > Test kms_setmode: > Subgroup basic: > pass -> FAIL (shard-hsw) fdo#99912 > Test drv_selftest: > Subgroup live_hangcheck: > pass -> INCOMPLETE (shard-snb) fdo#104313 > > fdo#101623 https://bugs.freedesktop.org/show_bug.cgi?id=101623 > fdo#102252 https://bugs.freedesktop.org/show_bug.cgi?id=102252 > fdo#99912 https://bugs.freedesktop.org/show_bug.cgi?id=99912 > fdo#104313 https://bugs.freedesktop.org/show_bug.cgi?id=104313 > > shard-hswtotal:2712 pass:1536 dwarn:2 dfail:0 fail:10 skip:1164 > time:9369s > shard-snbtotal:2694 pass:1288 dwarn:2 dfail:0 fail:12 skip:1391 > time:7844s > Blacklisted hosts: > shard-apltotal:2690 pass:1664 dwarn:1 dfail:0 fail:23 skip:1001 > time:13370s > shard-kbltotal:2712 pass:1805 dwarn:2 dfail:1 fail:23 skip:881 > time:11025s > > == Logs == > > For more details see: > https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_7523/shards.html And pushed, thanks for the patch. -Chris ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] 回复: Linux kernel: drivers/gpu/drm/i915/i915_gem.c: i915_gem_pread_ioctl similar Double-Fetch bug
发自我的华为手机i have see copy user pointer to a kernel temp struct before call i915_gem_pead_ioctl thanks for your reply 原始邮件 主题：Re: Linux kernel: drivers/gpu/drm/i915/i915_gem.c: i915_gem_pread_ioctl similar Double-Fetch bug发件人：Jani Nikula 收件人：sohu0106 ,joonas.lahti...@linux.intel.com,rodrigo.v...@intel.com抄送：intel-gfx@lists.freedesktop.orgOn Sat, 16 Dec 2017, sohu0106 wrote:> I found a similar Double-Fetch bug in drivers/gpu/drm/i915/i915_gem.c> when I was examining the source code. Similar to what?> In function i915_gem_pread_ioctl(), the driver check user space data> by pointer data_ptr via access_ok() in line 694, and after run a> while, in function shmem_pread_slow in line 657 or shmem_pread_fast in> line 639, finally it use __copy_to_user with no check user space> pointer.>> If the args->data_ptr is modified by a user thread under race> condition between the check and __copy_to_user operations, for example> changing to a kernel address, this will lead to Arbitrary kernel> address writing(caused by __copy_to_user() ).See drm_ioctl() for why this is not a possible scenario.BR,Jani.-- Jani Nikula, Intel Open Source Technology Center___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH i-g-t] scripts/trace.pl: Auto-detect tracepoint field order
From: Tvrtko Ursulin
Instead of hard-coding the order of key-value pairs into regular
expressions, auto-detect them as we go.
At the same time re-factor the code so it is smaller and even
slightly faster (10-15% by a quick measurement).
Signed-off-by: Tvrtko Ursulin
Cc: Lionel Landwerlin
Cc: John Harrison
---
scripts/trace.pl | 223 ++-
1 file changed, 71 insertions(+), 152 deletions(-)
diff --git a/scripts/trace.pl b/scripts/trace.pl
index aed9b20d8407..9b3fb6486fec 100755
--- a/scripts/trace.pl
+++ b/scripts/trace.pl
@@ -302,74 +302,6 @@ die if scalar(@args);
@ARGV = @args;
-sub parse_req
-{
- my ($line, $tp) = @_;
- state %cache;
-
- $cache{$tp} = qr/(\d+)\.(\d+):.*$tp.*ring=(\d+), ctx=(\d+),
seqno=(\d+), global(?:_seqno)?=(\d+)/ unless exists $cache{$tp};
-
- if ($line =~ $cache{$tp}) {
- return ($1, $2, $3, $4, $5, $6);
- } else {
- return undef;
- }
-}
-
-sub parse_req_hw
-{
- my ($line, $tp) = @_;
- state %cache;
-
- $cache{$tp} = qr/(\d+)\.(\d+):.*$tp.*ring=(\d+), ctx=(\d+),
seqno=(\d+), global(?:_seqno)?=(\d+), port=(\d+)/ unless exists $cache{$tp};
-
- if ($line =~ $cache{$tp}) {
- return ($1, $2, $3, $4, $5, $6, $7);
- } else {
- return undef;
- }
-}
-
-sub parse_req_wait_begin
-{
- my ($line, $tp) = @_;
-
- if ($line =~ /(\d+)\.(\d+):.*i915_gem_request_wait_begin.*ring=(\d+),
ctx=(\d+), seqno=(\d+)/) {
- return ($1, $2, $3, $4, $5);
- } else {
- return undef;
- }
-}
-
-sub parse_notify
-{
- my ($line) = @_;
-
- if ($line =~ /(\d+)\.(\d+):.*intel_engine_notify.*ring=(\d+),
seqno=(\d+)/) {
- return ($1, $2, $3, $4);
- } else {
- return undef;
- }
-}
-
-sub parse_freq
-{
- my ($line) = @_;
-
- if ($line =~ /(\d+)\.(\d+):.*intel_gpu_freq_change.*new_freq=(\d+)/) {
- return ($1, $2, $3);
- } else {
- return undef;
- }
-}
-
-sub us
-{
- my ($s, $us) = @_;
-
- return $s * 100 + $us;
-}
-
sub db_key
{
my ($ring, $ctx, $seqno) = @_;
@@ -425,86 +357,87 @@ my $prev_freq_ts = 0;
my $oldkernelwa = 0;
my ($no_queue, $no_in);
while (<>) {
- my ($s, $us, $ring, $ctx, $seqno, $global_seqno, $port);
- my $freq;
+ my @fields;
+ my @tmp;
+ my $tp_name;
+ my $time;
+ my %tp;
my $key;
chomp;
+ @fields = split ' ';
- ($s, $us, $ring, $ctx, $seqno) = parse_req_wait_begin($_);
- if (defined $s) {
- my %rw;
+ $tp_name = $fields[4];
+ @tmp = split ':', $tp_name, 2;
+ next unless $tmp[0] eq 'i915';
+ $tp_name = $tmp[1];
+ chop $tp_name;
- next if exists $ignore_ring{$ring};
+ chop $fields[3];
+ $time = $fields[3] * 100.0;
+ splice @fields, 0, 5;
- $ctx = sanitize_ctx($ctx, $ring);
- $key = db_key($ring, $ctx, $seqno);
+ foreach my $f (@fields) {
+ my @kv = split '=|,', $f;
- next if exists $reqwait{$key};
+ $kv[0] = 'global' if $kv[0] eq 'global_seqno';
- $rw{'key'} = $key;
- $rw{'ring'} = $ring;
- $rw{'seqno'} = $seqno;
- $rw{'ctx'} = $ctx;
- $rw{'start'} = us($s, $us);
- $reqwait{$key} = \%rw;
- next;
+ $tp{$kv[0]} = $kv[1];
}
- ($s, $us, $ring, $ctx, $seqno, $global_seqno) = parse_req($_,
'i915:i915_gem_request_wait_end');
- if (defined $s) {
- next if exists $ignore_ring{$ring};
+ return undef if exists $tp{'ring'} and exists $ignore_ring{$tp{'ring'}};
+
+ if ($tp_name eq 'i915_gem_request_wait_begin') {
+ my %rw;
- $ctx = sanitize_ctx($ctx, $ring);
- $key = db_key($ring, $ctx, $seqno);
+ $tp{'ctx'} = sanitize_ctx($tp{'ctx'}, $tp{'ring'});
+ $key = db_key($tp{'ring'}, $tp{'ctx'}, $tp{'seqno'});
- next unless exists $reqwait{$key};
+ next if exists $reqwait{$key};
- $reqwait{$key}->{'end'} = us($s, $us);
+ $rw{'key'} = $key;
+ $rw{'ring'} = $tp{'ring'};
+ $rw{'seqno'} = $tp{'seqno'};
+ $rw{'ctx'} = $tp{'ctx'};
+ $rw{'start'} = $time;
+ $reqwait{$key} = \%rw;
next;
- }
+ } elsif ($tp_name eq 'i915_gem_request_wait_end') {
+ $tp{'ctx'} = sanitize_ctx($tp{'ctx'}, $tp{'ring'});
+ $key = db_key($tp{'ring'}, $tp{'ctx'}, $tp{'seqno'});
- ($s, $us, $ring, $ctx, $seqno, $global_seqno) = parse_req($_,
'i915:i915_gem_request_add');
- if (defined $s) {
- my $orig_ctx = $ctx;
+
Re: [Intel-gfx] [PATCH v2] drm/i915: Show IPEIR and IPEHR in the engine dump
On 18/12/2017 11:26, Chris Wilson wrote:
A useful bit of information for inspecting GPU stalls from
intel_engine_dump() are the error registers, IPEIR and IPEHR.
v2: Fixup gen changes in register offsets (Tvrtko)
Signed-off-by: Chris Wilson
Cc: Mika Kuoppala
Cc: Joonas Lahtinen
Cc: Tvrtko Ursulin
---
drivers/gpu/drm/i915/intel_engine_cs.c | 14 ++
1 file changed, 14 insertions(+)
diff --git a/drivers/gpu/drm/i915/intel_engine_cs.c
b/drivers/gpu/drm/i915/intel_engine_cs.c
index 510e0bc3a377..92b9e0dd6378 100644
--- a/drivers/gpu/drm/i915/intel_engine_cs.c
+++ b/drivers/gpu/drm/i915/intel_engine_cs.c
@@ -1757,6 +1757,20 @@ void intel_engine_dump(struct intel_engine_cs *engine,
addr = intel_engine_get_last_batch_head(engine);
drm_printf(m, "\tBBADDR: 0x%08x_%08x\n",
upper_32_bits(addr), lower_32_bits(addr));
+ addr = I915_READ(RING_DMA_FADD(engine->mmio_base));
+ if (INTEL_GEN(dev_priv) >= 8)
+ addr |= (u64)I915_READ(RING_DMA_FADD_UDW(engine->mmio_base)) <<
32;
+ drm_printf(m, "\tDMA_FADDR: 0x%08x_%08x\n",
+ upper_32_bits(addr), lower_32_bits(addr));
< gen4 case not interesting here? Error capture reads DMA_FADD_I8XX in
that case. Doesn't look like the same offset to me.
Regards,
Tvrtko
+ if (INTEL_GEN(dev_priv) >= 4) {
+ drm_printf(m, "\tIPEIR: 0x%08x\n",
+ I915_READ(RING_IPEIR(engine->mmio_base)));
+ drm_printf(m, "\tIPEHR: 0x%08x\n",
+ I915_READ(RING_IPEHR(engine->mmio_base)));
+ } else {
+ drm_printf(m, "\tIPEIR: 0x%08x\n", I915_READ(IPEIR));
+ drm_printf(m, "\tIPEHR: 0x%08x\n", I915_READ(IPEHR));
+ }
if (HAS_EXECLISTS(dev_priv)) {
const u32 *hws =
&engine->status_page.page_addr[I915_HWS_CSB_BUF0_INDEX];
___
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[Intel-gfx] [PATCH 2/2] drm/i915/trace: add hw_id to gem requests trace points
When monitoring the GPU with i915 perf, reports are tagged with a hw
id. Gem context creation tracepoints already have a hw_id field,
unfortunately you only get this correlation between a process id and a
hw context id once when the context is created. It doesn't help if you
started monitoring after the process was initialized or if the drm fd
was transfered from one process to another.
This change adds the hw_id field to gem requests, so that correlation
can also be done on submission.
v2: Place hw_id at the end of the tracepoint to not disrupt too much
existing tools (Chris)
v3: Reorder hw_id field again (Chris)
Signed-off-by: Lionel Landwerlin
---
drivers/gpu/drm/i915/i915_trace.h | 26 --
1 file changed, 16 insertions(+), 10 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_trace.h
b/drivers/gpu/drm/i915/i915_trace.h
index 321f74bae0e1..042c43a4bd59 100644
--- a/drivers/gpu/drm/i915/i915_trace.h
+++ b/drivers/gpu/drm/i915/i915_trace.h
@@ -616,6 +616,7 @@ TRACE_EVENT(i915_gem_request_queue,
TP_STRUCT__entry(
__field(u32, dev)
+__field(u32, hw_id)
__field(u32, ring)
__field(u32, ctx)
__field(u32, seqno)
@@ -624,15 +625,16 @@ TRACE_EVENT(i915_gem_request_queue,
TP_fast_assign(
__entry->dev = req->i915->drm.primary->index;
+ __entry->hw_id = req->ctx->hw_id;
__entry->ring = req->engine->id;
__entry->ctx = req->fence.context;
__entry->seqno = req->fence.seqno;
__entry->flags = flags;
),
- TP_printk("dev=%u, ring=%u, ctx=%u, seqno=%u, flags=0x%x",
- __entry->dev, __entry->ring, __entry->ctx, __entry->seqno,
- __entry->flags)
+ TP_printk("dev=%u, hw_id=%u, ring=%u, ctx=%u, seqno=%u, flags=0x%x",
+ __entry->dev, __entry->hw_id, __entry->ring, __entry->ctx,
+ __entry->seqno, __entry->flags)
);
DECLARE_EVENT_CLASS(i915_gem_request,
@@ -641,6 +643,7 @@ DECLARE_EVENT_CLASS(i915_gem_request,
TP_STRUCT__entry(
__field(u32, dev)
+__field(u32, hw_id)
__field(u32, ring)
__field(u32, ctx)
__field(u32, seqno)
@@ -649,15 +652,16 @@ DECLARE_EVENT_CLASS(i915_gem_request,
TP_fast_assign(
__entry->dev = req->i915->drm.primary->index;
+ __entry->hw_id = req->ctx->hw_id;
__entry->ring = req->engine->id;
__entry->ctx = req->fence.context;
__entry->seqno = req->fence.seqno;
__entry->global = req->global_seqno;
),
- TP_printk("dev=%u, ring=%u, ctx=%u, seqno=%u, global=%u",
- __entry->dev, __entry->ring, __entry->ctx, __entry->seqno,
- __entry->global)
+ TP_printk("dev=%u, hw_id=%u, ring=%u, ctx=%u, seqno=%u, global=%u",
+ __entry->dev, __entry->hw_id, __entry->ring, __entry->ctx,
+ __entry->seqno, __entry->global)
);
DEFINE_EVENT(i915_gem_request, i915_gem_request_add,
@@ -683,6 +687,7 @@ DECLARE_EVENT_CLASS(i915_gem_request_hw,
TP_STRUCT__entry(
__field(u32, dev)
+__field(u32, hw_id)
__field(u32, ring)
__field(u32, ctx)
__field(u32, seqno)
@@ -692,6 +697,7 @@ DECLARE_EVENT_CLASS(i915_gem_request_hw,
TP_fast_assign(
__entry->dev = req->i915->drm.primary->index;
+ __entry->hw_id = req->ctx->hw_id;
__entry->ring = req->engine->id;
__entry->ctx = req->fence.context;
__entry->seqno = req->fence.seqno;
@@ -699,10 +705,10 @@ DECLARE_EVENT_CLASS(i915_gem_request_hw,
__entry->port = port;
),
- TP_printk("dev=%u, ring=%u, ctx=%u, seqno=%u, global=%u,
port=%u",
- __entry->dev, __entry->ring, __entry->ctx,
- __entry->seqno, __entry->global_seqno,
- __entry->port)
+ TP_printk("dev=%u, hw_id=%u, ring=%u, ctx=%u, seqno=%u,
global=%u, port=%u",
+ __entry->dev, __entry->hw_id, __entry->r
[Intel-gfx] [PATCH 1/2] drm/i915: reorder field in gem_request tracepoints
Let's make the order of the fields of the tracepoints involving gem request match across i915. This makes userspace processing of tracepoint a bit easier. Suggested-by: Chris Wilson Signed-off-by: Lionel Landwerlin --- drivers/gpu/drm/i915/i915_trace.h | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/i915/i915_trace.h b/drivers/gpu/drm/i915/i915_trace.h index 4e76768ffa95..321f74bae0e1 100644 --- a/drivers/gpu/drm/i915/i915_trace.h +++ b/drivers/gpu/drm/i915/i915_trace.h @@ -641,8 +641,8 @@ DECLARE_EVENT_CLASS(i915_gem_request, TP_STRUCT__entry( __field(u32, dev) -__field(u32, ctx) __field(u32, ring) +__field(u32, ctx) __field(u32, seqno) __field(u32, global) ), @@ -684,9 +684,9 @@ DECLARE_EVENT_CLASS(i915_gem_request_hw, TP_STRUCT__entry( __field(u32, dev) __field(u32, ring) +__field(u32, ctx) __field(u32, seqno) __field(u32, global_seqno) -__field(u32, ctx) __field(u32, port) ), -- 2.15.1 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 0/2] drm/i915: improve tracepoints for process/hw_id tracking
Hi, These are just a couple of changes to allow process/hw_id correlation when using i915 perf to monitor the workloads on the GPU. Cheers, Lionel Landwerlin (2): drm/i915: reorder field in gem_request tracepoints drm/i915/trace: add hw_id to gem requests trace points drivers/gpu/drm/i915/i915_trace.h | 30 ++ 1 file changed, 18 insertions(+), 12 deletions(-) -- 2.15.1 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH v3] drm/i915: Show IPEIR and IPEHR in the engine dump
A useful bit of information for inspecting GPU stalls from
intel_engine_dump() are the error registers, IPEIR and IPEHR.
v2: Fixup gen changes in register offsets (Tvrtko)
v3: Old FADDR location as well
Signed-off-by: Chris Wilson
Cc: Mika Kuoppala
Cc: Joonas Lahtinen
Cc: Tvrtko Ursulin
---
drivers/gpu/drm/i915/intel_engine_cs.c | 20
1 file changed, 20 insertions(+)
diff --git a/drivers/gpu/drm/i915/intel_engine_cs.c
b/drivers/gpu/drm/i915/intel_engine_cs.c
index 510e0bc3a377..257b03a67e1c 100644
--- a/drivers/gpu/drm/i915/intel_engine_cs.c
+++ b/drivers/gpu/drm/i915/intel_engine_cs.c
@@ -1757,6 +1757,26 @@ void intel_engine_dump(struct intel_engine_cs *engine,
addr = intel_engine_get_last_batch_head(engine);
drm_printf(m, "\tBBADDR: 0x%08x_%08x\n",
upper_32_bits(addr), lower_32_bits(addr));
+ if (INTEL_GEN(dev_priv) >= 4) {
+ if (INTEL_GEN(dev_priv) >= 8) {
+ addr = I915_READ(RING_DMA_FADD_UDW(engine->mmio_base));
+ addr <<= 32;
+ }
+ addr = I915_READ(RING_DMA_FADD(engine->mmio_base));
+ } else {
+ addr = I915_READ(DMA_FADD_I8XX);
+ }
+ drm_printf(m, "\tDMA_FADDR: 0x%08x_%08x\n",
+ upper_32_bits(addr), lower_32_bits(addr));
+ if (INTEL_GEN(dev_priv) >= 4) {
+ drm_printf(m, "\tIPEIR: 0x%08x\n",
+ I915_READ(RING_IPEIR(engine->mmio_base)));
+ drm_printf(m, "\tIPEHR: 0x%08x\n",
+ I915_READ(RING_IPEHR(engine->mmio_base)));
+ } else {
+ drm_printf(m, "\tIPEIR: 0x%08x\n", I915_READ(IPEIR));
+ drm_printf(m, "\tIPEHR: 0x%08x\n", I915_READ(IPEHR));
+ }
if (HAS_EXECLISTS(dev_priv)) {
const u32 *hws =
&engine->status_page.page_addr[I915_HWS_CSB_BUF0_INDEX];
--
2.15.1
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Re: [Intel-gfx] [PATCH 4/4] drm/i915: push shared dpll enable to encoders on DDI platforms
> -Original Message-
> From: Intel-gfx [mailto:intel-gfx-boun...@lists.freedesktop.org] On Behalf Of
> Jani Nikula
> Sent: Thursday, October 12, 2017 9:36 PM
> To: intel-gfx@lists.freedesktop.org
> Cc: Nikula, Jani ; Daniel Vetter
>
> Subject: [Intel-gfx] [PATCH 4/4] drm/i915: push shared dpll enable to
> encoders on DDI platforms
>
> As we move more encoder specific stuff to encoders on DDI platforms,
> follow suit with shared dpll enable. In the future, we'll need this
> refactoring
> for further encoder specific details in the middle of the enable sequence.
>
> v2: drop ifs around the intel_enable_shared_dpll calls (Daniel)
>
> Cc: Daniel Vetter
> Signed-off-by: Jani Nikula
> ---
> drivers/gpu/drm/i915/intel_crt.c | 2 ++
> drivers/gpu/drm/i915/intel_ddi.c | 16
> drivers/gpu/drm/i915/intel_display.c | 3 ---
> 3 files changed, 18 insertions(+), 3 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_crt.c
> b/drivers/gpu/drm/i915/intel_crt.c
> index 67f771f24608..65f28062cb51 100644
> --- a/drivers/gpu/drm/i915/intel_crt.c
> +++ b/drivers/gpu/drm/i915/intel_crt.c
> @@ -255,6 +255,8 @@ static void hsw_pre_pll_enable_crt(struct
> intel_encoder *encoder,
> WARN_ON(!intel_crtc->config->has_pch_encoder);
>
> intel_set_pch_fifo_underrun_reporting(dev_priv, PIPE_A, false);
> +
> + intel_enable_shared_dpll(intel_crtc);
> }
>
> static void hsw_pre_enable_crt(struct intel_encoder *encoder, diff --git
> a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c
> index 9819e51fa160..05f9db9c3d52 100644
> --- a/drivers/gpu/drm/i915/intel_ddi.c
> +++ b/drivers/gpu/drm/i915/intel_ddi.c
> @@ -2416,13 +2416,27 @@ static void intel_disable_ddi(struct intel_encoder
> *intel_encoder,
> }
> }
>
> +static void intel_ddi_pre_pll_enable(struct intel_encoder *encoder,
> + const struct intel_crtc_state *pipe_config,
> + const struct drm_connector_state
> *conn_state) {
> + struct drm_crtc *crtc = pipe_config->base.crtc;
> + struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
> +
> + intel_enable_shared_dpll(intel_crtc);
> +}
> +
Shouldn’t we add this code (and below as well) inside enable() or pre_enable()
functions
of struct intel_encoder as pre_pll_enable() function should have some code
prior to enabling PLL.
Regards,
Madhav
> static void bxt_ddi_pre_pll_enable(struct intel_encoder *encoder,
> const struct intel_crtc_state *pipe_config,
> const struct drm_connector_state
> *conn_state) {
> + struct drm_crtc *crtc = pipe_config->base.crtc;
> + struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
> uint8_t mask = pipe_config->lane_lat_optim_mask;
>
> bxt_ddi_phy_set_lane_optim_mask(encoder, mask);
> +
> + intel_enable_shared_dpll(intel_crtc);
> }
>
> void intel_ddi_prepare_link_retrain(struct intel_dp *intel_dp) @@ -2730,6
> +2744,8 @@ void intel_ddi_init(struct drm_i915_private *dev_priv, enum
> port port)
> intel_encoder->enable = intel_enable_ddi;
> if (IS_GEN9_LP(dev_priv))
> intel_encoder->pre_pll_enable = bxt_ddi_pre_pll_enable;
> + else
> + intel_encoder->pre_pll_enable = intel_ddi_pre_pll_enable;
> intel_encoder->pre_enable = intel_ddi_pre_enable;
> intel_encoder->disable = intel_disable_ddi;
> intel_encoder->post_disable = intel_ddi_post_disable; diff --git
> a/drivers/gpu/drm/i915/intel_display.c
> b/drivers/gpu/drm/i915/intel_display.c
> index 6ed299670f27..d9ccde0a8097 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -5481,9 +5481,6 @@ static void haswell_crtc_enable(struct
> intel_crtc_state *pipe_config,
>
> intel_encoders_pre_pll_enable(crtc, pipe_config, old_state);
>
> - if (intel_crtc->config->shared_dpll)
> - intel_enable_shared_dpll(intel_crtc);
> -
> if (intel_crtc_has_dp_encoder(intel_crtc->config))
> intel_dp_set_m_n(intel_crtc, M1_N1);
>
> --
> 2.11.0
>
> ___
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Re: [Intel-gfx] [PATCH v3] drm/i915: Show IPEIR and IPEHR in the engine dump
On 18/12/2017 12:17, Chris Wilson wrote:
A useful bit of information for inspecting GPU stalls from
intel_engine_dump() are the error registers, IPEIR and IPEHR.
v2: Fixup gen changes in register offsets (Tvrtko)
v3: Old FADDR location as well
Signed-off-by: Chris Wilson
Cc: Mika Kuoppala
Cc: Joonas Lahtinen
Cc: Tvrtko Ursulin
---
drivers/gpu/drm/i915/intel_engine_cs.c | 20
1 file changed, 20 insertions(+)
diff --git a/drivers/gpu/drm/i915/intel_engine_cs.c
b/drivers/gpu/drm/i915/intel_engine_cs.c
index 510e0bc3a377..257b03a67e1c 100644
--- a/drivers/gpu/drm/i915/intel_engine_cs.c
+++ b/drivers/gpu/drm/i915/intel_engine_cs.c
@@ -1757,6 +1757,26 @@ void intel_engine_dump(struct intel_engine_cs *engine,
addr = intel_engine_get_last_batch_head(engine);
drm_printf(m, "\tBBADDR: 0x%08x_%08x\n",
upper_32_bits(addr), lower_32_bits(addr));
+ if (INTEL_GEN(dev_priv) >= 4) {
+ if (INTEL_GEN(dev_priv) >= 8) {
+ addr = I915_READ(RING_DMA_FADD_UDW(engine->mmio_base));
+ addr <<= 32;
+ }
+ addr = I915_READ(RING_DMA_FADD(engine->mmio_base));
|=, or better reverse order to avoid having to init addr.
Regards,
Tvrtko
+ } else {
+ addr = I915_READ(DMA_FADD_I8XX);
+ }
+ drm_printf(m, "\tDMA_FADDR: 0x%08x_%08x\n",
+ upper_32_bits(addr), lower_32_bits(addr));
+ if (INTEL_GEN(dev_priv) >= 4) {
+ drm_printf(m, "\tIPEIR: 0x%08x\n",
+ I915_READ(RING_IPEIR(engine->mmio_base)));
+ drm_printf(m, "\tIPEHR: 0x%08x\n",
+ I915_READ(RING_IPEHR(engine->mmio_base)));
+ } else {
+ drm_printf(m, "\tIPEIR: 0x%08x\n", I915_READ(IPEIR));
+ drm_printf(m, "\tIPEHR: 0x%08x\n", I915_READ(IPEHR));
+ }
if (HAS_EXECLISTS(dev_priv)) {
const u32 *hws =
&engine->status_page.page_addr[I915_HWS_CSB_BUF0_INDEX];
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Re: [Intel-gfx] [PATCH v3] drm/i915: Show IPEIR and IPEHR in the engine dump
Quoting Tvrtko Ursulin (2017-12-18 12:32:37)
>
> On 18/12/2017 12:17, Chris Wilson wrote:
> > A useful bit of information for inspecting GPU stalls from
> > intel_engine_dump() are the error registers, IPEIR and IPEHR.
> >
> > v2: Fixup gen changes in register offsets (Tvrtko)
> > v3: Old FADDR location as well
> >
> > Signed-off-by: Chris Wilson
> > Cc: Mika Kuoppala
> > Cc: Joonas Lahtinen
> > Cc: Tvrtko Ursulin
> > ---
> > drivers/gpu/drm/i915/intel_engine_cs.c | 20
> > 1 file changed, 20 insertions(+)
> >
> > diff --git a/drivers/gpu/drm/i915/intel_engine_cs.c
> > b/drivers/gpu/drm/i915/intel_engine_cs.c
> > index 510e0bc3a377..257b03a67e1c 100644
> > --- a/drivers/gpu/drm/i915/intel_engine_cs.c
> > +++ b/drivers/gpu/drm/i915/intel_engine_cs.c
> > @@ -1757,6 +1757,26 @@ void intel_engine_dump(struct intel_engine_cs
> > *engine,
> > addr = intel_engine_get_last_batch_head(engine);
> > drm_printf(m, "BBADDR: 0x%08x_%08x\n",
> > upper_32_bits(addr), lower_32_bits(addr));
> > + if (INTEL_GEN(dev_priv) >= 4) {
> > + if (INTEL_GEN(dev_priv) >= 8) {
> > + addr =
> > I915_READ(RING_DMA_FADD_UDW(engine->mmio_base));
> > + addr <<= 32;
> > + }
> > + addr = I915_READ(RING_DMA_FADD(engine->mmio_base));
>
> |=, or better reverse order to avoid having to init addr.
|= otherwise it's back to the ugly (u64) << 32;
Pick your poison. Or maybe if I started paying attention we wouldn't
need to be going round in some many circles.
-Chris
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[Intel-gfx] [PATCH v4] drm/i915: Show IPEIR and IPEHR in the engine dump
A useful bit of information for inspecting GPU stalls from
intel_engine_dump() are the error registers, IPEIR and IPEHR.
v2: Fixup gen changes in register offsets (Tvrtko)
v3: Old FADDR location as well
v4: Use I915_READ64_2x32
Signed-off-by: Chris Wilson
Cc: Mika Kuoppala
Cc: Joonas Lahtinen
Cc: Tvrtko Ursulin
---
drivers/gpu/drm/i915/intel_engine_cs.c | 18 ++
1 file changed, 18 insertions(+)
diff --git a/drivers/gpu/drm/i915/intel_engine_cs.c
b/drivers/gpu/drm/i915/intel_engine_cs.c
index 510e0bc3a377..b4807497e92d 100644
--- a/drivers/gpu/drm/i915/intel_engine_cs.c
+++ b/drivers/gpu/drm/i915/intel_engine_cs.c
@@ -1757,6 +1757,24 @@ void intel_engine_dump(struct intel_engine_cs *engine,
addr = intel_engine_get_last_batch_head(engine);
drm_printf(m, "\tBBADDR: 0x%08x_%08x\n",
upper_32_bits(addr), lower_32_bits(addr));
+ if (INTEL_GEN(dev_priv) >= 8)
+ addr = I915_READ64_2x32(RING_DMA_FADD(engine->mmio_base),
+ RING_DMA_FADD_UDW(engine->mmio_base));
+ else if (INTEL_GEN(dev_priv) >= 4)
+ addr = I915_READ(RING_DMA_FADD(engine->mmio_base));
+ else
+ addr = I915_READ(DMA_FADD_I8XX);
+ drm_printf(m, "\tDMA_FADDR: 0x%08x_%08x\n",
+ upper_32_bits(addr), lower_32_bits(addr));
+ if (INTEL_GEN(dev_priv) >= 4) {
+ drm_printf(m, "\tIPEIR: 0x%08x\n",
+ I915_READ(RING_IPEIR(engine->mmio_base)));
+ drm_printf(m, "\tIPEHR: 0x%08x\n",
+ I915_READ(RING_IPEHR(engine->mmio_base)));
+ } else {
+ drm_printf(m, "\tIPEIR: 0x%08x\n", I915_READ(IPEIR));
+ drm_printf(m, "\tIPEHR: 0x%08x\n", I915_READ(IPEHR));
+ }
if (HAS_EXECLISTS(dev_priv)) {
const u32 *hws =
&engine->status_page.page_addr[I915_HWS_CSB_BUF0_INDEX];
--
2.15.1
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Re: [Intel-gfx] [PATCH 4/4] drm/i915: push shared dpll enable to encoders on DDI platforms
On Mon, 18 Dec 2017, "Chauhan, Madhav" wrote:
>> -Original Message-
>> From: Intel-gfx [mailto:intel-gfx-boun...@lists.freedesktop.org] On Behalf Of
>> Jani Nikula
>> Sent: Thursday, October 12, 2017 9:36 PM
>> To: intel-gfx@lists.freedesktop.org
>> Cc: Nikula, Jani ; Daniel Vetter
>>
>> Subject: [Intel-gfx] [PATCH 4/4] drm/i915: push shared dpll enable to
>> encoders on DDI platforms
>>
>> As we move more encoder specific stuff to encoders on DDI platforms,
>> follow suit with shared dpll enable. In the future, we'll need this
>> refactoring
>> for further encoder specific details in the middle of the enable sequence.
>>
>> v2: drop ifs around the intel_enable_shared_dpll calls (Daniel)
>>
>> Cc: Daniel Vetter
>> Signed-off-by: Jani Nikula
>> ---
>> drivers/gpu/drm/i915/intel_crt.c | 2 ++
>> drivers/gpu/drm/i915/intel_ddi.c | 16
>> drivers/gpu/drm/i915/intel_display.c | 3 ---
>> 3 files changed, 18 insertions(+), 3 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/i915/intel_crt.c
>> b/drivers/gpu/drm/i915/intel_crt.c
>> index 67f771f24608..65f28062cb51 100644
>> --- a/drivers/gpu/drm/i915/intel_crt.c
>> +++ b/drivers/gpu/drm/i915/intel_crt.c
>> @@ -255,6 +255,8 @@ static void hsw_pre_pll_enable_crt(struct
>> intel_encoder *encoder,
>> WARN_ON(!intel_crtc->config->has_pch_encoder);
>>
>> intel_set_pch_fifo_underrun_reporting(dev_priv, PIPE_A, false);
>> +
>> +intel_enable_shared_dpll(intel_crtc);
>> }
>>
>> static void hsw_pre_enable_crt(struct intel_encoder *encoder, diff --git
>> a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c
>> index 9819e51fa160..05f9db9c3d52 100644
>> --- a/drivers/gpu/drm/i915/intel_ddi.c
>> +++ b/drivers/gpu/drm/i915/intel_ddi.c
>> @@ -2416,13 +2416,27 @@ static void intel_disable_ddi(struct intel_encoder
>> *intel_encoder,
>> }
>> }
>>
>> +static void intel_ddi_pre_pll_enable(struct intel_encoder *encoder,
>> + const struct intel_crtc_state *pipe_config,
>> + const struct drm_connector_state
>> *conn_state) {
>> +struct drm_crtc *crtc = pipe_config->base.crtc;
>> +struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
>> +
>> +intel_enable_shared_dpll(intel_crtc);
>> +}
>> +
>
> Shouldn’t we add this code (and below as well) inside enable() or
> pre_enable() functions
> of struct intel_encoder as pre_pll_enable() function should have some code
> prior to enabling PLL.
The first step should be pushing the calls down to encoder hooks while
keeping the modeset sequence as close as possible to before. After that,
we can start tweaking the order where applicable. Always make minimal
changes so you see where stuff breaks.
BR
Jani.
>
> Regards,
> Madhav
>
>> static void bxt_ddi_pre_pll_enable(struct intel_encoder *encoder,
>> const struct intel_crtc_state *pipe_config,
>> const struct drm_connector_state
>> *conn_state) {
>> +struct drm_crtc *crtc = pipe_config->base.crtc;
>> +struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
>> uint8_t mask = pipe_config->lane_lat_optim_mask;
>>
>> bxt_ddi_phy_set_lane_optim_mask(encoder, mask);
>> +
>> +intel_enable_shared_dpll(intel_crtc);
>> }
>>
>> void intel_ddi_prepare_link_retrain(struct intel_dp *intel_dp) @@ -2730,6
>> +2744,8 @@ void intel_ddi_init(struct drm_i915_private *dev_priv, enum
>> port port)
>> intel_encoder->enable = intel_enable_ddi;
>> if (IS_GEN9_LP(dev_priv))
>> intel_encoder->pre_pll_enable = bxt_ddi_pre_pll_enable;
>> +else
>> +intel_encoder->pre_pll_enable = intel_ddi_pre_pll_enable;
>> intel_encoder->pre_enable = intel_ddi_pre_enable;
>> intel_encoder->disable = intel_disable_ddi;
>> intel_encoder->post_disable = intel_ddi_post_disable; diff --git
>> a/drivers/gpu/drm/i915/intel_display.c
>> b/drivers/gpu/drm/i915/intel_display.c
>> index 6ed299670f27..d9ccde0a8097 100644
>> --- a/drivers/gpu/drm/i915/intel_display.c
>> +++ b/drivers/gpu/drm/i915/intel_display.c
>> @@ -5481,9 +5481,6 @@ static void haswell_crtc_enable(struct
>> intel_crtc_state *pipe_config,
>>
>> intel_encoders_pre_pll_enable(crtc, pipe_config, old_state);
>>
>> -if (intel_crtc->config->shared_dpll)
>> -intel_enable_shared_dpll(intel_crtc);
>> -
>> if (intel_crtc_has_dp_encoder(intel_crtc->config))
>> intel_dp_set_m_n(intel_crtc, M1_N1);
>>
>> --
>> 2.11.0
>>
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--
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[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915: improve tracepoints for process/hw_id tracking
== Series Details == Series: drm/i915: improve tracepoints for process/hw_id tracking URL : https://patchwork.freedesktop.org/series/35506/ State : success == Summary == Series 35506v1 drm/i915: improve tracepoints for process/hw_id tracking https://patchwork.freedesktop.org/api/1.0/series/35506/revisions/1/mbox/ Test gem_exec_reloc: Subgroup basic-gtt-cpu: pass -> INCOMPLETE (fi-byt-j1900) fdo#102657 Test kms_pipe_crc_basic: Subgroup suspend-read-crc-pipe-a: dmesg-warn -> PASS (fi-kbl-r) fdo#104172 Test kms_psr_sink_crc: Subgroup psr_basic: dmesg-warn -> PASS (fi-skl-6700hq) fdo#101144 fdo#102657 https://bugs.freedesktop.org/show_bug.cgi?id=102657 fdo#104172 https://bugs.freedesktop.org/show_bug.cgi?id=104172 fdo#101144 https://bugs.freedesktop.org/show_bug.cgi?id=101144 fi-bdw-5557u total:288 pass:267 dwarn:0 dfail:0 fail:0 skip:21 time:432s fi-bdw-gvtdvmtotal:288 pass:264 dwarn:0 dfail:0 fail:0 skip:24 time:441s fi-blb-e6850 total:288 pass:223 dwarn:1 dfail:0 fail:0 skip:64 time:384s fi-bsw-n3050 total:288 pass:242 dwarn:0 dfail:0 fail:0 skip:46 time:497s fi-bwr-2160 total:288 pass:183 dwarn:0 dfail:0 fail:0 skip:105 time:275s fi-bxt-dsi total:288 pass:258 dwarn:0 dfail:0 fail:0 skip:30 time:490s fi-bxt-j4205 total:288 pass:259 dwarn:0 dfail:0 fail:0 skip:29 time:501s fi-byt-j1900 total:74 pass:64 dwarn:0 dfail:0 fail:0 skip:9 fi-byt-n2820 total:288 pass:249 dwarn:0 dfail:0 fail:0 skip:39 time:469s fi-elk-e7500 total:224 pass:163 dwarn:15 dfail:0 fail:0 skip:45 fi-gdg-551 total:288 pass:179 dwarn:1 dfail:0 fail:0 skip:108 time:262s fi-glk-1 total:288 pass:260 dwarn:0 dfail:0 fail:0 skip:28 time:529s fi-hsw-4770 total:288 pass:261 dwarn:0 dfail:0 fail:0 skip:27 time:403s fi-hsw-4770r total:288 pass:261 dwarn:0 dfail:0 fail:0 skip:27 time:415s fi-ilk-650 total:288 pass:228 dwarn:0 dfail:0 fail:0 skip:60 time:383s fi-ivb-3520m total:288 pass:259 dwarn:0 dfail:0 fail:0 skip:29 time:480s fi-ivb-3770 total:288 pass:255 dwarn:0 dfail:0 fail:0 skip:33 time:425s fi-kbl-7500u total:288 pass:263 dwarn:1 dfail:0 fail:0 skip:24 time:479s fi-kbl-7560u total:288 pass:268 dwarn:1 dfail:0 fail:0 skip:19 time:511s fi-kbl-7567u total:288 pass:268 dwarn:0 dfail:0 fail:0 skip:20 time:463s fi-kbl-r total:288 pass:261 dwarn:0 dfail:0 fail:0 skip:27 time:526s fi-pnv-d510 total:288 pass:222 dwarn:1 dfail:0 fail:0 skip:65 time:582s fi-skl-6260u total:288 pass:268 dwarn:0 dfail:0 fail:0 skip:20 time:444s fi-skl-6600u total:288 pass:260 dwarn:1 dfail:0 fail:0 skip:27 time:530s fi-skl-6700hqtotal:288 pass:262 dwarn:0 dfail:0 fail:0 skip:26 time:552s fi-skl-6700k2total:288 pass:264 dwarn:0 dfail:0 fail:0 skip:24 time:506s fi-skl-6770hqtotal:288 pass:268 dwarn:0 dfail:0 fail:0 skip:20 time:489s fi-skl-gvtdvmtotal:288 pass:265 dwarn:0 dfail:0 fail:0 skip:23 time:448s fi-snb-2520m total:288 pass:248 dwarn:0 dfail:0 fail:0 skip:40 time:544s fi-snb-2600 total:288 pass:248 dwarn:0 dfail:0 fail:0 skip:40 time:410s Blacklisted hosts: fi-cfl-s2total:288 pass:262 dwarn:0 dfail:0 fail:0 skip:26 time:599s fi-cnl-y total:288 pass:262 dwarn:0 dfail:0 fail:0 skip:26 time:614s fi-glk-dsi total:132 pass:65 dwarn:0 dfail:1 fail:0 skip:65 bf5cdf9e055a88559a6fc707b6e89e88077a2124 drm-tip: 2017y-12m-18d-11h-53m-39s UTC integration manifest e3fedfb57294 drm/i915/trace: add hw_id to gem requests trace points 294ba5538aec drm/i915: reorder field in gem_request tracepoints == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_7524/issues.html ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH v4] drm/i915: Show IPEIR and IPEHR in the engine dump
On 18/12/2017 12:39, Chris Wilson wrote:
A useful bit of information for inspecting GPU stalls from
intel_engine_dump() are the error registers, IPEIR and IPEHR.
v2: Fixup gen changes in register offsets (Tvrtko)
v3: Old FADDR location as well
v4: Use I915_READ64_2x32
Signed-off-by: Chris Wilson
Cc: Mika Kuoppala
Cc: Joonas Lahtinen
Cc: Tvrtko Ursulin
---
drivers/gpu/drm/i915/intel_engine_cs.c | 18 ++
1 file changed, 18 insertions(+)
diff --git a/drivers/gpu/drm/i915/intel_engine_cs.c
b/drivers/gpu/drm/i915/intel_engine_cs.c
index 510e0bc3a377..b4807497e92d 100644
--- a/drivers/gpu/drm/i915/intel_engine_cs.c
+++ b/drivers/gpu/drm/i915/intel_engine_cs.c
@@ -1757,6 +1757,24 @@ void intel_engine_dump(struct intel_engine_cs *engine,
addr = intel_engine_get_last_batch_head(engine);
drm_printf(m, "\tBBADDR: 0x%08x_%08x\n",
upper_32_bits(addr), lower_32_bits(addr));
+ if (INTEL_GEN(dev_priv) >= 8)
+ addr = I915_READ64_2x32(RING_DMA_FADD(engine->mmio_base),
+ RING_DMA_FADD_UDW(engine->mmio_base));
+ else if (INTEL_GEN(dev_priv) >= 4)
+ addr = I915_READ(RING_DMA_FADD(engine->mmio_base));
+ else
+ addr = I915_READ(DMA_FADD_I8XX);
+ drm_printf(m, "\tDMA_FADDR: 0x%08x_%08x\n",
+ upper_32_bits(addr), lower_32_bits(addr));
+ if (INTEL_GEN(dev_priv) >= 4) {
+ drm_printf(m, "\tIPEIR: 0x%08x\n",
+ I915_READ(RING_IPEIR(engine->mmio_base)));
+ drm_printf(m, "\tIPEHR: 0x%08x\n",
+ I915_READ(RING_IPEHR(engine->mmio_base)));
+ } else {
+ drm_printf(m, "\tIPEIR: 0x%08x\n", I915_READ(IPEIR));
+ drm_printf(m, "\tIPEHR: 0x%08x\n", I915_READ(IPEHR));
+ }
if (HAS_EXECLISTS(dev_priv)) {
const u32 *hws =
&engine->status_page.page_addr[I915_HWS_CSB_BUF0_INDEX];
Reviewed-by: Tvrtko Ursulin
Regards,
Tvrtko
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Re: [Intel-gfx] [PATCH 4/4] drm/i915: push shared dpll enable to encoders on DDI platforms
> -Original Message-
> From: Nikula, Jani
> Sent: Monday, December 18, 2017 6:21 PM
> To: Chauhan, Madhav ; intel-
> g...@lists.freedesktop.org
> Cc: Daniel Vetter
> Subject: RE: [Intel-gfx] [PATCH 4/4] drm/i915: push shared dpll enable to
> encoders on DDI platforms
>
> On Mon, 18 Dec 2017, "Chauhan, Madhav"
> wrote:
> >> -Original Message-
> >> From: Intel-gfx [mailto:intel-gfx-boun...@lists.freedesktop.org] On
> >> Behalf Of Jani Nikula
> >> Sent: Thursday, October 12, 2017 9:36 PM
> >> To: intel-gfx@lists.freedesktop.org
> >> Cc: Nikula, Jani ; Daniel Vetter
> >>
> >> Subject: [Intel-gfx] [PATCH 4/4] drm/i915: push shared dpll enable to
> >> encoders on DDI platforms
> >>
> >> As we move more encoder specific stuff to encoders on DDI platforms,
> >> follow suit with shared dpll enable. In the future, we'll need this
> >> refactoring for further encoder specific details in the middle of the
> >> enable
> sequence.
> >>
> >> v2: drop ifs around the intel_enable_shared_dpll calls (Daniel)
> >>
> >> Cc: Daniel Vetter
> >> Signed-off-by: Jani Nikula
> >> ---
> >> drivers/gpu/drm/i915/intel_crt.c | 2 ++
> >> drivers/gpu/drm/i915/intel_ddi.c | 16
> >> drivers/gpu/drm/i915/intel_display.c | 3 ---
> >> 3 files changed, 18 insertions(+), 3 deletions(-)
> >>
> >> diff --git a/drivers/gpu/drm/i915/intel_crt.c
> >> b/drivers/gpu/drm/i915/intel_crt.c
> >> index 67f771f24608..65f28062cb51 100644
> >> --- a/drivers/gpu/drm/i915/intel_crt.c
> >> +++ b/drivers/gpu/drm/i915/intel_crt.c
> >> @@ -255,6 +255,8 @@ static void hsw_pre_pll_enable_crt(struct
> >> intel_encoder *encoder,
> >>WARN_ON(!intel_crtc->config->has_pch_encoder);
> >>
> >>intel_set_pch_fifo_underrun_reporting(dev_priv, PIPE_A, false);
> >> +
> >> + intel_enable_shared_dpll(intel_crtc);
> >> }
> >>
> >> static void hsw_pre_enable_crt(struct intel_encoder *encoder, diff
> >> --git a/drivers/gpu/drm/i915/intel_ddi.c
> >> b/drivers/gpu/drm/i915/intel_ddi.c
> >> index 9819e51fa160..05f9db9c3d52 100644
> >> --- a/drivers/gpu/drm/i915/intel_ddi.c
> >> +++ b/drivers/gpu/drm/i915/intel_ddi.c
> >> @@ -2416,13 +2416,27 @@ static void intel_disable_ddi(struct
> >> intel_encoder *intel_encoder,
> >>}
> >> }
> >>
> >> +static void intel_ddi_pre_pll_enable(struct intel_encoder *encoder,
> >> + const struct intel_crtc_state *pipe_config,
> >> + const struct drm_connector_state
> >> *conn_state) {
> >> + struct drm_crtc *crtc = pipe_config->base.crtc;
> >> + struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
> >> +
> >> + intel_enable_shared_dpll(intel_crtc);
> >> +}
> >> +
> >
> > Shouldn’t we add this code (and below as well) inside enable() or
> > pre_enable() functions of struct intel_encoder as pre_pll_enable() function
> should have some code prior to enabling PLL.
>
> The first step should be pushing the calls down to encoder hooks while
> keeping the modeset sequence as close as possible to before. After that, we
> can start tweaking the order where applicable. Always make minimal
> changes so you see where stuff breaks.
Sure. Let's tweak them once initial thing works fine.
Thanks!!
Madhav
>
> BR
> Jani.
>
>
> >
> > Regards,
> > Madhav
> >
> >> static void bxt_ddi_pre_pll_enable(struct intel_encoder *encoder,
> >> const struct intel_crtc_state *pipe_config,
> >> const struct drm_connector_state
> >> *conn_state) {
> >> + struct drm_crtc *crtc = pipe_config->base.crtc;
> >> + struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
> >>uint8_t mask = pipe_config->lane_lat_optim_mask;
> >>
> >>bxt_ddi_phy_set_lane_optim_mask(encoder, mask);
> >> +
> >> + intel_enable_shared_dpll(intel_crtc);
> >> }
> >>
> >> void intel_ddi_prepare_link_retrain(struct intel_dp *intel_dp) @@
> >> -2730,6
> >> +2744,8 @@ void intel_ddi_init(struct drm_i915_private *dev_priv,
> >> +enum
> >> port port)
> >>intel_encoder->enable = intel_enable_ddi;
> >>if (IS_GEN9_LP(dev_priv))
> >>intel_encoder->pre_pll_enable = bxt_ddi_pre_pll_enable;
> >> + else
> >> + intel_encoder->pre_pll_enable = intel_ddi_pre_pll_enable;
> >>intel_encoder->pre_enable = intel_ddi_pre_enable;
> >>intel_encoder->disable = intel_disable_ddi;
> >>intel_encoder->post_disable = intel_ddi_post_disable; diff --git
> >> a/drivers/gpu/drm/i915/intel_display.c
> >> b/drivers/gpu/drm/i915/intel_display.c
> >> index 6ed299670f27..d9ccde0a8097 100644
> >> --- a/drivers/gpu/drm/i915/intel_display.c
> >> +++ b/drivers/gpu/drm/i915/intel_display.c
> >> @@ -5481,9 +5481,6 @@ static void haswell_crtc_enable(struct
> >> intel_crtc_state *pipe_config,
> >>
> >>intel_encoders_pre_pll_enable(crtc, pipe_config, old_state);
> >>
> >> - if (intel_crtc->config->shared_dpll)
> >> - intel_enable_shared_dpll(intel_crtc);
> >> -
> >>if (intel_crtc_has_dp_encoder(intel_crtc-
[Intel-gfx] ✗ Fi.CI.BAT: failure for series starting with [1/3] drm/i915: Re-enable GGTT earlier after GPU reset (rev4)
== Series Details == Series: series starting with [1/3] drm/i915: Re-enable GGTT earlier after GPU reset (rev4) URL : https://patchwork.freedesktop.org/series/35471/ State : failure == Summary == Series 35471v4 series starting with [1/3] drm/i915: Re-enable GGTT earlier after GPU reset https://patchwork.freedesktop.org/api/1.0/series/35471/revisions/4/mbox/ Test kms_pipe_crc_basic: Subgroup read-crc-pipe-b: pass -> FAIL (fi-skl-6700k2) Subgroup suspend-read-crc-pipe-a: dmesg-warn -> PASS (fi-kbl-r) fdo#104172 +1 Subgroup suspend-read-crc-pipe-b: pass -> INCOMPLETE (fi-snb-2520m) fdo#103713 Test kms_psr_sink_crc: Subgroup psr_basic: dmesg-warn -> PASS (fi-skl-6700hq) fdo#101144 fdo#104172 https://bugs.freedesktop.org/show_bug.cgi?id=104172 fdo#103713 https://bugs.freedesktop.org/show_bug.cgi?id=103713 fdo#101144 https://bugs.freedesktop.org/show_bug.cgi?id=101144 fi-bdw-5557u total:288 pass:267 dwarn:0 dfail:0 fail:0 skip:21 time:433s fi-bdw-gvtdvmtotal:288 pass:264 dwarn:0 dfail:0 fail:0 skip:24 time:439s fi-blb-e6850 total:288 pass:223 dwarn:1 dfail:0 fail:0 skip:64 time:381s fi-bsw-n3050 total:288 pass:242 dwarn:0 dfail:0 fail:0 skip:46 time:489s fi-bwr-2160 total:288 pass:183 dwarn:0 dfail:0 fail:0 skip:105 time:276s fi-bxt-dsi total:288 pass:258 dwarn:0 dfail:0 fail:0 skip:30 time:496s fi-bxt-j4205 total:288 pass:259 dwarn:0 dfail:0 fail:0 skip:29 time:498s fi-byt-j1900 total:288 pass:253 dwarn:0 dfail:0 fail:0 skip:35 time:475s fi-byt-n2820 total:288 pass:249 dwarn:0 dfail:0 fail:0 skip:39 time:460s fi-elk-e7500 total:224 pass:163 dwarn:15 dfail:0 fail:0 skip:45 fi-gdg-551 total:288 pass:179 dwarn:1 dfail:0 fail:0 skip:108 time:262s fi-glk-1 total:288 pass:260 dwarn:0 dfail:0 fail:0 skip:28 time:529s fi-hsw-4770 total:288 pass:261 dwarn:0 dfail:0 fail:0 skip:27 time:405s fi-hsw-4770r total:288 pass:261 dwarn:0 dfail:0 fail:0 skip:27 time:411s fi-ilk-650 total:288 pass:228 dwarn:0 dfail:0 fail:0 skip:60 time:390s fi-ivb-3520m total:288 pass:259 dwarn:0 dfail:0 fail:0 skip:29 time:469s fi-ivb-3770 total:288 pass:255 dwarn:0 dfail:0 fail:0 skip:33 time:427s fi-kbl-7500u total:288 pass:263 dwarn:1 dfail:0 fail:0 skip:24 time:480s fi-kbl-7560u total:288 pass:268 dwarn:1 dfail:0 fail:0 skip:19 time:520s fi-kbl-7567u total:288 pass:268 dwarn:0 dfail:0 fail:0 skip:20 time:471s fi-kbl-r total:288 pass:260 dwarn:1 dfail:0 fail:0 skip:27 time:519s fi-pnv-d510 total:288 pass:222 dwarn:1 dfail:0 fail:0 skip:65 time:595s fi-skl-6260u total:288 pass:268 dwarn:0 dfail:0 fail:0 skip:20 time:443s fi-skl-6600u total:288 pass:260 dwarn:1 dfail:0 fail:0 skip:27 time:525s fi-skl-6700hqtotal:288 pass:262 dwarn:0 dfail:0 fail:0 skip:26 time:558s fi-skl-6700k2total:288 pass:263 dwarn:0 dfail:0 fail:1 skip:24 time:505s fi-skl-6770hqtotal:288 pass:268 dwarn:0 dfail:0 fail:0 skip:20 time:495s fi-skl-gvtdvmtotal:288 pass:265 dwarn:0 dfail:0 fail:0 skip:23 time:441s fi-snb-2520m total:245 pass:211 dwarn:0 dfail:0 fail:0 skip:33 fi-snb-2600 total:288 pass:248 dwarn:0 dfail:0 fail:0 skip:40 time:415s Blacklisted hosts: fi-cfl-s2total:288 pass:262 dwarn:0 dfail:0 fail:0 skip:26 time:591s fi-glk-dsi total:288 pass:256 dwarn:0 dfail:0 fail:2 skip:30 time:496s bf5cdf9e055a88559a6fc707b6e89e88077a2124 drm-tip: 2017y-12m-18d-11h-53m-39s UTC integration manifest d60eefb6e585 drm/i915/selftests: Fix up igt_reset_engine 46fc9d5cbe36 drm/i915: Show IPEIR and IPEHR in the engine dump == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_7525/issues.html ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH v5] drm/i915/userptr: Probe vma range before gup
On 15/12/2017 14:48, Chris Wilson wrote:
We want to exclude any GGTT objects from being present on our internal
lists to avoid the deadlock we may run into with our requirement for
struct_mutex during invalidate. However, if the gup_fast fails, we put
the userptr onto the workqueue and mark it as active, so that we
remember to serialise the worker upon mmu_invalidate.
v2: Hold mmap_sem to prevent modifications to the mm while we probe and
add ourselves to the interval-tree for notificiation.
v3: Rely on mmap_sem for a simpler patch.
v4: Mark up the mmap_sem nesting
v5: Don't deactivate on -EAGAIN as that means the worker is queued
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=104209
Signed-off-by: Chris Wilson
Cc: Tvrtko Ursulin
Cc: Michał Winiarski
---
drivers/gpu/drm/i915/i915_gem_userptr.c | 55 +++--
1 file changed, 45 insertions(+), 10 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_gem_userptr.c
b/drivers/gpu/drm/i915/i915_gem_userptr.c
index 382a77a1097e..b16b8e226e40 100644
--- a/drivers/gpu/drm/i915/i915_gem_userptr.c
+++ b/drivers/gpu/drm/i915/i915_gem_userptr.c
@@ -598,13 +598,43 @@ __i915_gem_userptr_get_pages_schedule(struct
drm_i915_gem_object *obj)
return ERR_PTR(-EAGAIN);
}
+static int
+probe_range(struct mm_struct *mm, unsigned long addr, unsigned long len)
+{
+ const unsigned long end = addr + len;
+ struct vm_area_struct *vma;
+ int ret = -EFAULT;
+
+ for (vma = find_vma(mm, addr); vma; vma = vma->vm_next) {
+ if (vma->vm_start > addr)
+ break;
+
+ /*
+* Exclude any VMA that is backed only by struct_page, i.e.
+* IO regions that include our own GGTT mmaps. We cannot handle
+* such ranges, as we may encounter deadlocks around our
+* struct_mutex on mmu_invalidate_range.
+*/
+ if (vma->vm_flags & (VM_PFNMAP | VM_MIXEDMAP))
+ break;
+
+ if (vma->vm_end >= end) {
+ ret = 0;
+ break;
+ }
+
+ addr = vma->vm_end;
+ }
+
+ return ret;
+}
+
static int i915_gem_userptr_get_pages(struct drm_i915_gem_object *obj)
{
const int num_pages = obj->base.size >> PAGE_SHIFT;
struct mm_struct *mm = obj->userptr.mm->mm;
struct page **pvec;
struct sg_table *pages;
- bool active;
int pinned;
/* If userspace should engineer that these pages are replaced in
@@ -634,7 +664,6 @@ static int i915_gem_userptr_get_pages(struct
drm_i915_gem_object *obj)
pvec = NULL;
pinned = 0;
-
if (mm == current->mm) {
pvec = kvmalloc_array(num_pages, sizeof(struct page *),
GFP_KERNEL |
@@ -647,19 +676,25 @@ static int i915_gem_userptr_get_pages(struct
drm_i915_gem_object *obj)
pvec);
}
- active = false;
+ down_read_nested(&mm->mmap_sem, SINGLE_DEPTH_NESTING);
Big fat comment here? Something about the gem fault path?
if (pinned < 0) {
pages = ERR_PTR(pinned);
pinned = 0;
- } else if (pinned < num_pages) {
- pages = __i915_gem_userptr_get_pages_schedule(obj);
- active = pages == ERR_PTR(-EAGAIN);
+ } else if (pinned < num_pages &&
+ probe_range(mm, obj->userptr.ptr, obj->base.size)) {
Keep going back to remind on the return value semantics. Rename to
range_invalid or something?
+ pages = ERR_PTR(-EFAULT);
+ } else if (__i915_gem_userptr_set_active(obj, true)) {
Isn't this the normal path now, I mean the path where pinned ==
num_pages? So it sets the active to true, which is a bit evil to do in
the condition check, and then fall through to the else block to finish
the job.
I'll see if I can come up with something perhaps more readable in the
background.
+ pages = ERR_PTR(-EAGAI > } else {
- pages = __i915_gem_userptr_alloc_pages(obj, pvec, num_pages);
- active = !IS_ERR(pages);
+ if (pinned < num_pages)
+ pages = __i915_gem_userptr_get_pages_schedule(obj);
+ else
+ pages = __i915_gem_userptr_alloc_pages(obj,
+ pvec, num_pages);
+ if (IS_ERR(pages) && pages != ERR_PTR(-EAGAIN))
+ __i915_gem_userptr_set_active(obj, false);
}
- if (active)
- __i915_gem_userptr_set_active(obj, true);
+ up_read(&mm->mmap_sem);
if (IS_ERR(pages))
release_pages(pvec, pinned);
Regards,
Tvrtko
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Re: [Intel-gfx] [PATCH v4] drm/i915: Show IPEIR and IPEHR in the engine dump
Quoting Tvrtko Ursulin (2017-12-18 12:58:51)
>
> On 18/12/2017 12:39, Chris Wilson wrote:
> > A useful bit of information for inspecting GPU stalls from
> > intel_engine_dump() are the error registers, IPEIR and IPEHR.
> >
> > v2: Fixup gen changes in register offsets (Tvrtko)
> > v3: Old FADDR location as well
> > v4: Use I915_READ64_2x32
> >
> > Signed-off-by: Chris Wilson
> > Cc: Mika Kuoppala
> > Cc: Joonas Lahtinen
> > Cc: Tvrtko Ursulin
> > ---
> > drivers/gpu/drm/i915/intel_engine_cs.c | 18 ++
> > 1 file changed, 18 insertions(+)
> >
> > diff --git a/drivers/gpu/drm/i915/intel_engine_cs.c
> > b/drivers/gpu/drm/i915/intel_engine_cs.c
> > index 510e0bc3a377..b4807497e92d 100644
> > --- a/drivers/gpu/drm/i915/intel_engine_cs.c
> > +++ b/drivers/gpu/drm/i915/intel_engine_cs.c
> > @@ -1757,6 +1757,24 @@ void intel_engine_dump(struct intel_engine_cs
> > *engine,
> > addr = intel_engine_get_last_batch_head(engine);
> > drm_printf(m, "BBADDR: 0x%08x_%08x\n",
> > upper_32_bits(addr), lower_32_bits(addr));
> > + if (INTEL_GEN(dev_priv) >= 8)
> > + addr = I915_READ64_2x32(RING_DMA_FADD(engine->mmio_base),
> > + RING_DMA_FADD_UDW(engine->mmio_base));
> > + else if (INTEL_GEN(dev_priv) >= 4)
> > + addr = I915_READ(RING_DMA_FADD(engine->mmio_base));
> > + else
> > + addr = I915_READ(DMA_FADD_I8XX);
> > + drm_printf(m, "DMA_FADDR: 0x%08x_%08x\n",
> > +upper_32_bits(addr), lower_32_bits(addr));
> > + if (INTEL_GEN(dev_priv) >= 4) {
> > + drm_printf(m, "IPEIR: 0x%08x\n",
> > +I915_READ(RING_IPEIR(engine->mmio_base)));
> > + drm_printf(m, "IPEHR: 0x%08x\n",
> > +I915_READ(RING_IPEHR(engine->mmio_base)));
> > + } else {
> > + drm_printf(m, "IPEIR: 0x%08x\n", I915_READ(IPEIR));
> > + drm_printf(m, "IPEHR: 0x%08x\n", I915_READ(IPEHR));
> > + }
> >
> > if (HAS_EXECLISTS(dev_priv)) {
> > const u32 *hws =
> > &engine->status_page.page_addr[I915_HWS_CSB_BUF0_INDEX];
> >
>
> Reviewed-by: Tvrtko Ursulin
Thanks for the review, lots of fixes in such a small patch.
Pushed, so just the selftest for per-engine resets remaining, which I
hope Michel will pick up later.
-Chris
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[Intel-gfx] ✗ Fi.CI.BAT: warning for intel_vbt_decode: Typo fixes
== Series Details == Series: intel_vbt_decode: Typo fixes URL : https://patchwork.freedesktop.org/series/35441/ State : warning == Summary == IGT patchset tested on top of latest successful build c0be3310715e2f744b892c51f09e62273bcc8e57 tests/kms_frontbuffer_tracking: Correctly handle debugfs errors with latest DRM-Tip kernel build CI_DRM_3540 bf5cdf9e055a drm-tip: 2017y-12m-18d-11h-53m-39s UTC integration manifest No testlist changes. Test gem_mmap_gtt: Subgroup basic-small-bo-tiledx: pass -> FAIL (fi-gdg-551) fdo#102575 Test gem_ringfill: Subgroup basic-default: pass -> SKIP (fi-bsw-n3050) Test kms_pipe_crc_basic: Subgroup suspend-read-crc-pipe-a: dmesg-warn -> PASS (fi-kbl-r) fdo#104172 +1 Test kms_psr_sink_crc: Subgroup psr_basic: dmesg-warn -> PASS (fi-skl-6700hq) fdo#101144 fdo#102575 https://bugs.freedesktop.org/show_bug.cgi?id=102575 fdo#104172 https://bugs.freedesktop.org/show_bug.cgi?id=104172 fdo#101144 https://bugs.freedesktop.org/show_bug.cgi?id=101144 fi-bdw-5557u total:288 pass:267 dwarn:0 dfail:0 fail:0 skip:21 time:439s fi-bdw-gvtdvmtotal:288 pass:264 dwarn:0 dfail:0 fail:0 skip:24 time:443s fi-blb-e6850 total:288 pass:223 dwarn:1 dfail:0 fail:0 skip:64 time:390s fi-bsw-n3050 total:288 pass:241 dwarn:0 dfail:0 fail:0 skip:47 time:498s fi-bwr-2160 total:288 pass:183 dwarn:0 dfail:0 fail:0 skip:105 time:276s fi-bxt-dsi total:288 pass:258 dwarn:0 dfail:0 fail:0 skip:30 time:492s fi-bxt-j4205 total:288 pass:259 dwarn:0 dfail:0 fail:0 skip:29 time:502s fi-byt-j1900 total:288 pass:253 dwarn:0 dfail:0 fail:0 skip:35 time:485s fi-byt-n2820 total:288 pass:249 dwarn:0 dfail:0 fail:0 skip:39 time:472s fi-elk-e7500 total:224 pass:163 dwarn:15 dfail:0 fail:0 skip:45 fi-gdg-551 total:288 pass:178 dwarn:1 dfail:0 fail:1 skip:108 time:263s fi-glk-1 total:288 pass:260 dwarn:0 dfail:0 fail:0 skip:28 time:531s fi-hsw-4770 total:288 pass:261 dwarn:0 dfail:0 fail:0 skip:27 time:408s fi-hsw-4770r total:288 pass:261 dwarn:0 dfail:0 fail:0 skip:27 time:419s fi-ilk-650 total:288 pass:228 dwarn:0 dfail:0 fail:0 skip:60 time:396s fi-ivb-3520m total:288 pass:259 dwarn:0 dfail:0 fail:0 skip:29 time:478s fi-ivb-3770 total:288 pass:255 dwarn:0 dfail:0 fail:0 skip:33 time:429s fi-kbl-7500u total:288 pass:263 dwarn:1 dfail:0 fail:0 skip:24 time:480s fi-kbl-7560u total:288 pass:268 dwarn:1 dfail:0 fail:0 skip:19 time:527s fi-kbl-7567u total:288 pass:268 dwarn:0 dfail:0 fail:0 skip:20 time:472s fi-kbl-r total:288 pass:260 dwarn:1 dfail:0 fail:0 skip:27 time:522s fi-pnv-d510 total:288 pass:222 dwarn:1 dfail:0 fail:0 skip:65 time:609s fi-skl-6260u total:288 pass:268 dwarn:0 dfail:0 fail:0 skip:20 time:442s fi-skl-6600u total:288 pass:260 dwarn:1 dfail:0 fail:0 skip:27 time:532s fi-skl-6700hqtotal:288 pass:262 dwarn:0 dfail:0 fail:0 skip:26 time:557s fi-skl-6700k2total:288 pass:264 dwarn:0 dfail:0 fail:0 skip:24 time:509s fi-skl-6770hqtotal:288 pass:268 dwarn:0 dfail:0 fail:0 skip:20 time:505s fi-skl-gvtdvmtotal:288 pass:265 dwarn:0 dfail:0 fail:0 skip:23 time:448s fi-snb-2520m total:288 pass:248 dwarn:0 dfail:0 fail:0 skip:40 time:545s fi-snb-2600 total:288 pass:248 dwarn:0 dfail:0 fail:0 skip:40 time:414s Blacklisted hosts: fi-cfl-s2total:288 pass:262 dwarn:0 dfail:0 fail:0 skip:26 time:593s fi-cnl-y total:288 pass:262 dwarn:0 dfail:0 fail:0 skip:26 time:641s fi-glk-dsi total:288 pass:181 dwarn:1 dfail:4 fail:0 skip:102 time:366s == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_690/issues.html ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH 1/2] drm/i915: reorder field in gem_request tracepoints
Quoting Lionel Landwerlin (2017-12-18 12:12:47) > Let's make the order of the fields of the tracepoints involving gem > request match across i915. This makes userspace processing of > tracepoint a bit easier. > > Suggested-by: Chris Wilson > Signed-off-by: Lionel Landwerlin We could argue for days upon the preferred ordering of ctx/ring/seqno, but I think the best compromise is indeed hw_id/ring/ctx/seqno. I couldn't see any remaining inconsistencies, Reviewed-by: Chris Wilson -Chris ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH 2/2] drm/i915/trace: add hw_id to gem requests trace points
Quoting Lionel Landwerlin (2017-12-18 12:12:48)
> When monitoring the GPU with i915 perf, reports are tagged with a hw
> id. Gem context creation tracepoints already have a hw_id field,
> unfortunately you only get this correlation between a process id and a
> hw context id once when the context is created. It doesn't help if you
> started monitoring after the process was initialized or if the drm fd
> was transfered from one process to another.
>
> This change adds the hw_id field to gem requests, so that correlation
> can also be done on submission.
>
> v2: Place hw_id at the end of the tracepoint to not disrupt too much
> existing tools (Chris)
>
> v3: Reorder hw_id field again (Chris)
>
> Signed-off-by: Lionel Landwerlin
> ---
> drivers/gpu/drm/i915/i915_trace.h | 26 --
> 1 file changed, 16 insertions(+), 10 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_trace.h
> b/drivers/gpu/drm/i915/i915_trace.h
> index 321f74bae0e1..042c43a4bd59 100644
> --- a/drivers/gpu/drm/i915/i915_trace.h
> +++ b/drivers/gpu/drm/i915/i915_trace.h
> @@ -616,6 +616,7 @@ TRACE_EVENT(i915_gem_request_queue,
>
> TP_STRUCT__entry(
> __field(u32, dev)
> +__field(u32, hw_id)
> __field(u32, ring)
> __field(u32, ctx)
> __field(u32, seqno)
> @@ -624,15 +625,16 @@ TRACE_EVENT(i915_gem_request_queue,
>
> TP_fast_assign(
>__entry->dev = req->i915->drm.primary->index;
> + __entry->hw_id = req->ctx->hw_id;
>__entry->ring = req->engine->id;
>__entry->ctx = req->fence.context;
>__entry->seqno = req->fence.seqno;
>__entry->flags = flags;
>),
>
> - TP_printk("dev=%u, ring=%u, ctx=%u, seqno=%u, flags=0x%x",
> - __entry->dev, __entry->ring, __entry->ctx,
> __entry->seqno,
> - __entry->flags)
> + TP_printk("dev=%u, hw_id=%u, ring=%u, ctx=%u, seqno=%u,
> flags=0x%x",
> + __entry->dev, __entry->hw_id, __entry->ring,
> __entry->ctx,
> + __entry->seqno, __entry->flags)
> );
>
> DECLARE_EVENT_CLASS(i915_gem_request,
> @@ -641,6 +643,7 @@ DECLARE_EVENT_CLASS(i915_gem_request,
>
> TP_STRUCT__entry(
> __field(u32, dev)
> +__field(u32, hw_id)
> __field(u32, ring)
> __field(u32, ctx)
> __field(u32, seqno)
> @@ -649,15 +652,16 @@ DECLARE_EVENT_CLASS(i915_gem_request,
>
> TP_fast_assign(
>__entry->dev = req->i915->drm.primary->index;
> + __entry->hw_id = req->ctx->hw_id;
>__entry->ring = req->engine->id;
>__entry->ctx = req->fence.context;
>__entry->seqno = req->fence.seqno;
>__entry->global = req->global_seqno;
>),
>
> - TP_printk("dev=%u, ring=%u, ctx=%u, seqno=%u, global=%u",
> - __entry->dev, __entry->ring, __entry->ctx,
> __entry->seqno,
> - __entry->global)
> + TP_printk("dev=%u, hw_id=%u, ring=%u, ctx=%u, seqno=%u,
> global=%u",
> + __entry->dev, __entry->hw_id, __entry->ring,
> __entry->ctx,
> + __entry->seqno, __entry->global)
> );
>
> DEFINE_EVENT(i915_gem_request, i915_gem_request_add,
> @@ -683,6 +687,7 @@ DECLARE_EVENT_CLASS(i915_gem_request_hw,
>
> TP_STRUCT__entry(
> __field(u32, dev)
> +__field(u32, hw_id)
> __field(u32, ring)
> __field(u32, ctx)
> __field(u32, seqno)
> @@ -692,6 +697,7 @@ DECLARE_EVENT_CLASS(i915_gem_request_hw,
>
> TP_fast_assign(
>__entry->dev =
> req->i915->drm.primary->index;
> + __entry->hw_id = req->ctx->hw_id;
>__entry->ring = req->engine->id;
>__entry->ctx = req->fence.context;
>__entry->seqno = req->fence.seqno;
> @@ -699,10 +705,10 @@ DECLARE_EVENT_CLASS(i915_gem_request_hw,
>__entry->port = port;
> ),
>
> - TP_printk("dev=%u, ring=%u, ctx=%u, seqno=%u, global=%u,
> port=%u",
> - __entry->dev, __entry->ring, __entry->ctx,
> -
[Intel-gfx] ✓ Fi.CI.BAT: success for scripts/trace.pl: Auto-detect tracepoint field order
== Series Details == Series: scripts/trace.pl: Auto-detect tracepoint field order URL : https://patchwork.freedesktop.org/series/35504/ State : success == Summary == IGT patchset tested on top of latest successful build c0be3310715e2f744b892c51f09e62273bcc8e57 tests/kms_frontbuffer_tracking: Correctly handle debugfs errors with latest DRM-Tip kernel build CI_DRM_3541 913d6a0d4d78 drm-tip: 2017y-12m-18d-13h-25m-28s UTC integration manifest No testlist changes. Test kms_busy: Subgroup basic-flip-a: pass -> DMESG-WARN (fi-elk-e7500) fdo#103989 Test kms_pipe_crc_basic: Subgroup suspend-read-crc-pipe-a: dmesg-warn -> PASS (fi-kbl-r) fdo#104172 +1 Subgroup suspend-read-crc-pipe-c: incomplete -> PASS (fi-bdw-5557u) fdo#104162 fdo#103989 https://bugs.freedesktop.org/show_bug.cgi?id=103989 fdo#104172 https://bugs.freedesktop.org/show_bug.cgi?id=104172 fdo#104162 https://bugs.freedesktop.org/show_bug.cgi?id=104162 fi-bdw-5557u total:288 pass:267 dwarn:0 dfail:0 fail:0 skip:21 time:433s fi-bdw-gvtdvmtotal:288 pass:264 dwarn:0 dfail:0 fail:0 skip:24 time:444s fi-blb-e6850 total:288 pass:223 dwarn:1 dfail:0 fail:0 skip:64 time:383s fi-bsw-n3050 total:288 pass:242 dwarn:0 dfail:0 fail:0 skip:46 time:499s fi-bwr-2160 total:288 pass:183 dwarn:0 dfail:0 fail:0 skip:105 time:277s fi-bxt-dsi total:288 pass:258 dwarn:0 dfail:0 fail:0 skip:30 time:495s fi-bxt-j4205 total:288 pass:259 dwarn:0 dfail:0 fail:0 skip:29 time:501s fi-byt-j1900 total:288 pass:253 dwarn:0 dfail:0 fail:0 skip:35 time:482s fi-byt-n2820 total:288 pass:249 dwarn:0 dfail:0 fail:0 skip:39 time:477s fi-elk-e7500 total:224 pass:163 dwarn:15 dfail:0 fail:0 skip:45 fi-gdg-551 total:288 pass:178 dwarn:1 dfail:0 fail:1 skip:108 time:262s fi-glk-1 total:288 pass:260 dwarn:0 dfail:0 fail:0 skip:28 time:533s fi-hsw-4770 total:288 pass:261 dwarn:0 dfail:0 fail:0 skip:27 time:403s fi-hsw-4770r total:288 pass:261 dwarn:0 dfail:0 fail:0 skip:27 time:416s fi-ilk-650 total:288 pass:228 dwarn:0 dfail:0 fail:0 skip:60 time:389s fi-ivb-3520m total:288 pass:259 dwarn:0 dfail:0 fail:0 skip:29 time:477s fi-ivb-3770 total:288 pass:255 dwarn:0 dfail:0 fail:0 skip:33 time:427s fi-kbl-7500u total:288 pass:263 dwarn:1 dfail:0 fail:0 skip:24 time:487s fi-kbl-7560u total:288 pass:268 dwarn:1 dfail:0 fail:0 skip:19 time:518s fi-kbl-7567u total:288 pass:268 dwarn:0 dfail:0 fail:0 skip:20 time:471s fi-kbl-r total:288 pass:260 dwarn:1 dfail:0 fail:0 skip:27 time:524s fi-pnv-d510 total:288 pass:222 dwarn:1 dfail:0 fail:0 skip:65 time:595s fi-skl-6260u total:288 pass:268 dwarn:0 dfail:0 fail:0 skip:20 time:452s fi-skl-6600u total:288 pass:260 dwarn:1 dfail:0 fail:0 skip:27 time:533s fi-skl-6700hqtotal:288 pass:262 dwarn:0 dfail:0 fail:0 skip:26 time:558s fi-skl-6700k2total:288 pass:264 dwarn:0 dfail:0 fail:0 skip:24 time:506s fi-skl-6770hqtotal:288 pass:268 dwarn:0 dfail:0 fail:0 skip:20 time:491s fi-skl-gvtdvmtotal:288 pass:265 dwarn:0 dfail:0 fail:0 skip:23 time:446s fi-snb-2520m total:288 pass:248 dwarn:0 dfail:0 fail:0 skip:40 time:544s fi-snb-2600 total:288 pass:248 dwarn:0 dfail:0 fail:0 skip:40 time:412s Blacklisted hosts: fi-cfl-s2total:288 pass:262 dwarn:0 dfail:0 fail:0 skip:26 time:592s fi-cnl-y total:288 pass:262 dwarn:0 dfail:0 fail:0 skip:26 time:617s fi-glk-dsi total:59 pass:51 dwarn:0 dfail:0 fail:0 skip:7 == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_691/issues.html ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH 2/2] drm/i915/trace: add hw_id to gem requests trace points
On 18/12/17 13:35, Chris Wilson wrote:
Quoting Lionel Landwerlin (2017-12-18 12:12:48)
When monitoring the GPU with i915 perf, reports are tagged with a hw
id. Gem context creation tracepoints already have a hw_id field,
unfortunately you only get this correlation between a process id and a
hw context id once when the context is created. It doesn't help if you
started monitoring after the process was initialized or if the drm fd
was transfered from one process to another.
This change adds the hw_id field to gem requests, so that correlation
can also be done on submission.
v2: Place hw_id at the end of the tracepoint to not disrupt too much
existing tools (Chris)
v3: Reorder hw_id field again (Chris)
Signed-off-by: Lionel Landwerlin
---
drivers/gpu/drm/i915/i915_trace.h | 26 --
1 file changed, 16 insertions(+), 10 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_trace.h
b/drivers/gpu/drm/i915/i915_trace.h
index 321f74bae0e1..042c43a4bd59 100644
--- a/drivers/gpu/drm/i915/i915_trace.h
+++ b/drivers/gpu/drm/i915/i915_trace.h
@@ -616,6 +616,7 @@ TRACE_EVENT(i915_gem_request_queue,
TP_STRUCT__entry(
__field(u32, dev)
+__field(u32, hw_id)
__field(u32, ring)
__field(u32, ctx)
__field(u32, seqno)
@@ -624,15 +625,16 @@ TRACE_EVENT(i915_gem_request_queue,
TP_fast_assign(
__entry->dev = req->i915->drm.primary->index;
+ __entry->hw_id = req->ctx->hw_id;
__entry->ring = req->engine->id;
__entry->ctx = req->fence.context;
__entry->seqno = req->fence.seqno;
__entry->flags = flags;
),
- TP_printk("dev=%u, ring=%u, ctx=%u, seqno=%u, flags=0x%x",
- __entry->dev, __entry->ring, __entry->ctx, __entry->seqno,
- __entry->flags)
+ TP_printk("dev=%u, hw_id=%u, ring=%u, ctx=%u, seqno=%u, flags=0x%x",
+ __entry->dev, __entry->hw_id, __entry->ring, __entry->ctx,
+ __entry->seqno, __entry->flags)
);
DECLARE_EVENT_CLASS(i915_gem_request,
@@ -641,6 +643,7 @@ DECLARE_EVENT_CLASS(i915_gem_request,
TP_STRUCT__entry(
__field(u32, dev)
+__field(u32, hw_id)
__field(u32, ring)
__field(u32, ctx)
__field(u32, seqno)
@@ -649,15 +652,16 @@ DECLARE_EVENT_CLASS(i915_gem_request,
TP_fast_assign(
__entry->dev = req->i915->drm.primary->index;
+ __entry->hw_id = req->ctx->hw_id;
__entry->ring = req->engine->id;
__entry->ctx = req->fence.context;
__entry->seqno = req->fence.seqno;
__entry->global = req->global_seqno;
),
- TP_printk("dev=%u, ring=%u, ctx=%u, seqno=%u, global=%u",
- __entry->dev, __entry->ring, __entry->ctx, __entry->seqno,
- __entry->global)
+ TP_printk("dev=%u, hw_id=%u, ring=%u, ctx=%u, seqno=%u, global=%u",
+ __entry->dev, __entry->hw_id, __entry->ring, __entry->ctx,
+ __entry->seqno, __entry->global)
);
DEFINE_EVENT(i915_gem_request, i915_gem_request_add,
@@ -683,6 +687,7 @@ DECLARE_EVENT_CLASS(i915_gem_request_hw,
TP_STRUCT__entry(
__field(u32, dev)
+__field(u32, hw_id)
__field(u32, ring)
__field(u32, ctx)
__field(u32, seqno)
@@ -692,6 +697,7 @@ DECLARE_EVENT_CLASS(i915_gem_request_hw,
TP_fast_assign(
__entry->dev =
req->i915->drm.primary->index;
+ __entry->hw_id = req->ctx->hw_id;
__entry->ring = req->engine->id;
__entry->ctx = req->fence.context;
__entry->seqno = req->fence.seqno;
@@ -699,10 +705,10 @@ DECLARE_EVENT_CLASS(i915_gem_request_hw,
__entry->port = port;
),
- TP_printk("dev=%u, ring=%u, ctx=%u, seqno=%u, global=%u, port=%u",
- __entry->dev, __entry->ring, __entry->ctx,
- __entry->seqno, __entry->global_seqno,
- __entry->port)
+
[Intel-gfx] ✗ Fi.CI.BAT: failure for intel_vbt_decode: Typo fixes
== Series Details == Series: intel_vbt_decode: Typo fixes URL : https://patchwork.freedesktop.org/series/35441/ State : failure == Summary == IGT patchset tested on top of latest successful build c0be3310715e2f744b892c51f09e62273bcc8e57 tests/kms_frontbuffer_tracking: Correctly handle debugfs errors with latest DRM-Tip kernel build CI_DRM_3541 913d6a0d4d78 drm-tip: 2017y-12m-18d-13h-25m-28s UTC integration manifest No testlist changes. Test debugfs_test: Subgroup read_all_entries: dmesg-warn -> DMESG-FAIL (fi-elk-e7500) fdo#103989 +1 Test gem_mmap_gtt: Subgroup basic-small-bo-tiledx: fail -> PASS (fi-gdg-551) fdo#102575 Test kms_pipe_crc_basic: Subgroup suspend-read-crc-pipe-a: dmesg-warn -> PASS (fi-kbl-r) fdo#104172 +1 Subgroup suspend-read-crc-pipe-c: incomplete -> PASS (fi-bdw-5557u) fdo#104162 pass -> FAIL (fi-skl-6700k2) Test kms_psr_sink_crc: Subgroup psr_basic: pass -> DMESG-WARN (fi-skl-6700hq) fdo#101144 fdo#103989 https://bugs.freedesktop.org/show_bug.cgi?id=103989 fdo#102575 https://bugs.freedesktop.org/show_bug.cgi?id=102575 fdo#104172 https://bugs.freedesktop.org/show_bug.cgi?id=104172 fdo#104162 https://bugs.freedesktop.org/show_bug.cgi?id=104162 fdo#101144 https://bugs.freedesktop.org/show_bug.cgi?id=101144 fi-bdw-5557u total:288 pass:267 dwarn:0 dfail:0 fail:0 skip:21 time:432s fi-bdw-gvtdvmtotal:288 pass:264 dwarn:0 dfail:0 fail:0 skip:24 time:437s fi-blb-e6850 total:288 pass:223 dwarn:1 dfail:0 fail:0 skip:64 time:381s fi-bsw-n3050 total:288 pass:242 dwarn:0 dfail:0 fail:0 skip:46 time:504s fi-bwr-2160 total:288 pass:183 dwarn:0 dfail:0 fail:0 skip:105 time:278s fi-bxt-dsi total:288 pass:258 dwarn:0 dfail:0 fail:0 skip:30 time:498s fi-bxt-j4205 total:288 pass:259 dwarn:0 dfail:0 fail:0 skip:29 time:500s fi-byt-j1900 total:288 pass:253 dwarn:0 dfail:0 fail:0 skip:35 time:479s fi-byt-n2820 total:288 pass:249 dwarn:0 dfail:0 fail:0 skip:39 time:470s fi-elk-e7500 total:224 pass:163 dwarn:14 dfail:1 fail:0 skip:45 fi-gdg-551 total:288 pass:179 dwarn:1 dfail:0 fail:0 skip:108 time:264s fi-glk-1 total:288 pass:260 dwarn:0 dfail:0 fail:0 skip:28 time:533s fi-hsw-4770 total:288 pass:261 dwarn:0 dfail:0 fail:0 skip:27 time:408s fi-hsw-4770r total:288 pass:261 dwarn:0 dfail:0 fail:0 skip:27 time:415s fi-ilk-650 total:288 pass:228 dwarn:0 dfail:0 fail:0 skip:60 time:388s fi-ivb-3520m total:288 pass:259 dwarn:0 dfail:0 fail:0 skip:29 time:477s fi-ivb-3770 total:288 pass:255 dwarn:0 dfail:0 fail:0 skip:33 time:429s fi-kbl-7500u total:288 pass:263 dwarn:1 dfail:0 fail:0 skip:24 time:482s fi-kbl-7560u total:288 pass:268 dwarn:1 dfail:0 fail:0 skip:19 time:519s fi-kbl-7567u total:288 pass:268 dwarn:0 dfail:0 fail:0 skip:20 time:467s fi-kbl-r total:288 pass:260 dwarn:1 dfail:0 fail:0 skip:27 time:524s fi-pnv-d510 total:288 pass:222 dwarn:1 dfail:0 fail:0 skip:65 time:581s fi-skl-6260u total:288 pass:268 dwarn:0 dfail:0 fail:0 skip:20 time:444s fi-skl-6600u total:288 pass:260 dwarn:1 dfail:0 fail:0 skip:27 time:535s fi-skl-6700hqtotal:288 pass:261 dwarn:1 dfail:0 fail:0 skip:26 time:557s fi-skl-6700k2total:288 pass:263 dwarn:0 dfail:0 fail:1 skip:24 time:510s fi-skl-6770hqtotal:288 pass:268 dwarn:0 dfail:0 fail:0 skip:20 time:500s fi-skl-gvtdvmtotal:288 pass:265 dwarn:0 dfail:0 fail:0 skip:23 time:449s fi-snb-2520m total:288 pass:248 dwarn:0 dfail:0 fail:0 skip:40 time:554s fi-snb-2600 total:288 pass:248 dwarn:0 dfail:0 fail:0 skip:40 time:410s Blacklisted hosts: fi-cfl-s2total:288 pass:262 dwarn:0 dfail:0 fail:0 skip:26 time:598s fi-cnl-y total:288 pass:262 dwarn:0 dfail:0 fail:0 skip:26 time:644s fi-glk-dsi total:288 pass:256 dwarn:0 dfail:0 fail:2 skip:30 time:484s == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_692/issues.html ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH v2 1/2] drm/i915: reorder field in gem_request tracepoints
Let's make the order of the fields of the tracepoints involving gem request match across i915. This makes userspace processing of tracepoint a bit easier. Suggested-by: Chris Wilson Signed-off-by: Lionel Landwerlin Reviewed-by: Chris Wilson --- drivers/gpu/drm/i915/i915_trace.h | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/i915/i915_trace.h b/drivers/gpu/drm/i915/i915_trace.h index 4e76768ffa95..321f74bae0e1 100644 --- a/drivers/gpu/drm/i915/i915_trace.h +++ b/drivers/gpu/drm/i915/i915_trace.h @@ -641,8 +641,8 @@ DECLARE_EVENT_CLASS(i915_gem_request, TP_STRUCT__entry( __field(u32, dev) -__field(u32, ctx) __field(u32, ring) +__field(u32, ctx) __field(u32, seqno) __field(u32, global) ), @@ -684,9 +684,9 @@ DECLARE_EVENT_CLASS(i915_gem_request_hw, TP_STRUCT__entry( __field(u32, dev) __field(u32, ring) +__field(u32, ctx) __field(u32, seqno) __field(u32, global_seqno) -__field(u32, ctx) __field(u32, port) ), -- 2.15.1 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH v2 2/2] drm/i915/trace: add hw_id to gem requests trace points
When monitoring the GPU with i915 perf, reports are tagged with a hw
id. Gem context creation tracepoints already have a hw_id field,
unfortunately you only get this correlation between a process id and a
hw context id once when the context is created. It doesn't help if you
started monitoring after the process was initialized or if the drm fd
was transfered from one process to another.
This change adds the hw_id field to gem requests, so that correlation
can also be done on submission.
v2: Place hw_id at the end of the tracepoint to not disrupt too much
existing tools (Chris)
v3: Reorder hw_id field again (Chris)
v4: Add missing hw_id to i915_gem_request_wait_begin tracepoint (Chris)
Signed-off-by: Lionel Landwerlin
---
drivers/gpu/drm/i915/i915_trace.h | 36 ++--
1 file changed, 22 insertions(+), 14 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_trace.h
b/drivers/gpu/drm/i915/i915_trace.h
index 321f74bae0e1..e1169c02eb2b 100644
--- a/drivers/gpu/drm/i915/i915_trace.h
+++ b/drivers/gpu/drm/i915/i915_trace.h
@@ -616,6 +616,7 @@ TRACE_EVENT(i915_gem_request_queue,
TP_STRUCT__entry(
__field(u32, dev)
+__field(u32, hw_id)
__field(u32, ring)
__field(u32, ctx)
__field(u32, seqno)
@@ -624,15 +625,16 @@ TRACE_EVENT(i915_gem_request_queue,
TP_fast_assign(
__entry->dev = req->i915->drm.primary->index;
+ __entry->hw_id = req->ctx->hw_id;
__entry->ring = req->engine->id;
__entry->ctx = req->fence.context;
__entry->seqno = req->fence.seqno;
__entry->flags = flags;
),
- TP_printk("dev=%u, ring=%u, ctx=%u, seqno=%u, flags=0x%x",
- __entry->dev, __entry->ring, __entry->ctx, __entry->seqno,
- __entry->flags)
+ TP_printk("dev=%u, hw_id=%u, ring=%u, ctx=%u, seqno=%u, flags=0x%x",
+ __entry->dev, __entry->hw_id, __entry->ring, __entry->ctx,
+ __entry->seqno, __entry->flags)
);
DECLARE_EVENT_CLASS(i915_gem_request,
@@ -641,6 +643,7 @@ DECLARE_EVENT_CLASS(i915_gem_request,
TP_STRUCT__entry(
__field(u32, dev)
+__field(u32, hw_id)
__field(u32, ring)
__field(u32, ctx)
__field(u32, seqno)
@@ -649,15 +652,16 @@ DECLARE_EVENT_CLASS(i915_gem_request,
TP_fast_assign(
__entry->dev = req->i915->drm.primary->index;
+ __entry->hw_id = req->ctx->hw_id;
__entry->ring = req->engine->id;
__entry->ctx = req->fence.context;
__entry->seqno = req->fence.seqno;
__entry->global = req->global_seqno;
),
- TP_printk("dev=%u, ring=%u, ctx=%u, seqno=%u, global=%u",
- __entry->dev, __entry->ring, __entry->ctx, __entry->seqno,
- __entry->global)
+ TP_printk("dev=%u, hw_id=%u, ring=%u, ctx=%u, seqno=%u, global=%u",
+ __entry->dev, __entry->hw_id, __entry->ring, __entry->ctx,
+ __entry->seqno, __entry->global)
);
DEFINE_EVENT(i915_gem_request, i915_gem_request_add,
@@ -683,6 +687,7 @@ DECLARE_EVENT_CLASS(i915_gem_request_hw,
TP_STRUCT__entry(
__field(u32, dev)
+__field(u32, hw_id)
__field(u32, ring)
__field(u32, ctx)
__field(u32, seqno)
@@ -692,6 +697,7 @@ DECLARE_EVENT_CLASS(i915_gem_request_hw,
TP_fast_assign(
__entry->dev = req->i915->drm.primary->index;
+ __entry->hw_id = req->ctx->hw_id;
__entry->ring = req->engine->id;
__entry->ctx = req->fence.context;
__entry->seqno = req->fence.seqno;
@@ -699,10 +705,10 @@ DECLARE_EVENT_CLASS(i915_gem_request_hw,
__entry->port = port;
),
- TP_printk("dev=%u, ring=%u, ctx=%u, seqno=%u, global=%u,
port=%u",
- __entry->dev, __entry->ring, __entry->ctx,
- __entry->seqno, __entry->global_seqno,
- __entry->port)
+ TP_printk("dev=%u, hw_id=%u, ring=%u, ctx=%u, seqno=%u,
global=%
[Intel-gfx] [PATCH v2 0/2] drm/i915: improve tracepoints for process/hw_id tracking
Hey, I did miss a tracepoint in patch 2. Fixed! Cheers, Lionel Landwerlin (2): drm/i915: reorder field in gem_request tracepoints drm/i915/trace: add hw_id to gem requests trace points drivers/gpu/drm/i915/i915_trace.h | 40 +++ 1 file changed, 24 insertions(+), 16 deletions(-) -- 2.15.1 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH v2 2/2] drm/i915/trace: add hw_id to gem requests trace points
Quoting Lionel Landwerlin (2017-12-18 15:19:59) > When monitoring the GPU with i915 perf, reports are tagged with a hw > id. Gem context creation tracepoints already have a hw_id field, > unfortunately you only get this correlation between a process id and a > hw context id once when the context is created. It doesn't help if you > started monitoring after the process was initialized or if the drm fd > was transfered from one process to another. > > This change adds the hw_id field to gem requests, so that correlation > can also be done on submission. > > v2: Place hw_id at the end of the tracepoint to not disrupt too much > existing tools (Chris) > > v3: Reorder hw_id field again (Chris) > > v4: Add missing hw_id to i915_gem_request_wait_begin tracepoint (Chris) > > Signed-off-by: Lionel Landwerlin Reviewed-by: Chris Wilson -Chris ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 0/6] drm/i915: expose RCS topology to userspace
Hi all, This series a respin of a few attempts ([1], [2], [3]) to expose RCS topology to userspace. The motivation for this is to be able to monitor part of the GPU using i915 perf and have detailled knowledge about what execution units are fused off. Let's say you monitor slice 1, knowing how many EUs are actually usuable on that slice is critical to provide normalized numbers (like average busyness of the EUs on slice1) on that particular part of the GPU. Currently numbers returned like I915_PARAM_EU_TOTAL don't give us that information. This series introduces a new uAPI to query information from i915. It's partially inspired by the amdgpu_cs_ioctl, although we don't allow setting values onto the device, only queries. There is a good chance this new uAPI will be reused for exposing available engines (Tvrtko was looking into this). Thanks, [1]: https://patchwork.freedesktop.org/patch/185959/ [2]: https://patchwork.freedesktop.org/series/33436/ [3]: https://patchwork.freedesktop.org/series/33950/ Lionel Landwerlin (6): drm/i915: store all subslice masks drm/i915/debugfs: reuse max slice/subslices already stored in sseu drm/i915/debugfs: add rcs topology entry drm/i915: add rcs topology to error state drm/i915: add query uAPI drm/i915: expose rcs topology through query uAPI drivers/gpu/drm/i915/Makefile| 1 + drivers/gpu/drm/i915/i915_debugfs.c | 87 ++- drivers/gpu/drm/i915/i915_drv.c | 3 +- drivers/gpu/drm/i915/i915_drv.h | 26 - drivers/gpu/drm/i915/i915_gpu_error.c| 35 ++ drivers/gpu/drm/i915/i915_query.c| 186 +++ drivers/gpu/drm/i915/intel_device_info.c | 169 drivers/gpu/drm/i915/intel_lrc.c | 2 +- drivers/gpu/drm/i915/intel_query_info.c | 88 +++ drivers/gpu/drm/i915/intel_ringbuffer.h | 2 +- include/uapi/drm/i915_drm.h | 76 + 11 files changed, 598 insertions(+), 77 deletions(-) create mode 100644 drivers/gpu/drm/i915/i915_query.c create mode 100644 drivers/gpu/drm/i915/intel_query_info.c -- 2.15.1 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 1/6] drm/i915: store all subslice masks
Up to now, subslice mask was assumed to be uniform across slices. But
starting with Cannonlake, slices can be asymetric (for example slice0
has different number of subslices as slice1+). This change stores all
subslices masks for all slices rather than having a single mask that
applies to all slices.
Signed-off-by: Lionel Landwerlin
---
drivers/gpu/drm/i915/i915_debugfs.c | 24 +++--
drivers/gpu/drm/i915/i915_drv.c | 2 +-
drivers/gpu/drm/i915/i915_drv.h | 23 -
drivers/gpu/drm/i915/intel_device_info.c | 169 ++-
drivers/gpu/drm/i915/intel_lrc.c | 2 +-
drivers/gpu/drm/i915/intel_ringbuffer.h | 2 +-
6 files changed, 161 insertions(+), 61 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_debugfs.c
b/drivers/gpu/drm/i915/i915_debugfs.c
index 0ddce72552bf..0c7890b695c5 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -4293,7 +4293,7 @@ static void cherryview_sseu_device_status(struct
drm_i915_private *dev_priv,
continue;
sseu->slice_mask = BIT(0);
- sseu->subslice_mask |= BIT(ss);
+ sseu->subslices_mask[0] |= BIT(ss);
eu_cnt = ((sig1[ss] & CHV_EU08_PG_ENABLE) ? 0 : 2) +
((sig1[ss] & CHV_EU19_PG_ENABLE) ? 0 : 2) +
((sig1[ss] & CHV_EU210_PG_ENABLE) ? 0 : 2) +
@@ -4340,7 +4340,7 @@ static void gen10_sseu_device_status(struct
drm_i915_private *dev_priv,
continue;
sseu->slice_mask |= BIT(s);
- sseu->subslice_mask = info->sseu.subslice_mask;
+ sseu->subslices_mask[s] = info->sseu.subslices_mask[s];
for (ss = 0; ss < ss_max; ss++) {
unsigned int eu_cnt;
@@ -4395,8 +4395,8 @@ static void gen9_sseu_device_status(struct
drm_i915_private *dev_priv,
sseu->slice_mask |= BIT(s);
if (IS_GEN9_BC(dev_priv))
- sseu->subslice_mask =
- INTEL_INFO(dev_priv)->sseu.subslice_mask;
+ sseu->subslices_mask[s] =
+ INTEL_INFO(dev_priv)->sseu.subslices_mask[s];
for (ss = 0; ss < ss_max; ss++) {
unsigned int eu_cnt;
@@ -4406,7 +4406,7 @@ static void gen9_sseu_device_status(struct
drm_i915_private *dev_priv,
/* skip disabled subslice */
continue;
- sseu->subslice_mask |= BIT(ss);
+ sseu->subslices_mask[s] |= BIT(ss);
}
eu_cnt = 2 * hweight32(eu_reg[2*s + ss/2] &
@@ -4428,9 +4428,12 @@ static void broadwell_sseu_device_status(struct
drm_i915_private *dev_priv,
sseu->slice_mask = slice_info & GEN8_LSLICESTAT_MASK;
if (sseu->slice_mask) {
- sseu->subslice_mask = INTEL_INFO(dev_priv)->sseu.subslice_mask;
sseu->eu_per_subslice =
INTEL_INFO(dev_priv)->sseu.eu_per_subslice;
+ for (s = 0; s < fls(sseu->slice_mask); s++) {
+ sseu->subslices_mask[s] =
+ INTEL_INFO(dev_priv)->sseu.subslices_mask[s];
+ }
sseu->eu_total = sseu->eu_per_subslice *
sseu_subslice_total(sseu);
@@ -4449,6 +4452,7 @@ static void i915_print_sseu_info(struct seq_file *m, bool
is_available_info,
{
struct drm_i915_private *dev_priv = node_to_i915(m->private);
const char *type = is_available_info ? "Available" : "Enabled";
+ int s;
seq_printf(m, " %s Slice Mask: %04x\n", type,
sseu->slice_mask);
@@ -4456,10 +4460,10 @@ static void i915_print_sseu_info(struct seq_file *m,
bool is_available_info,
hweight8(sseu->slice_mask));
seq_printf(m, " %s Subslice Total: %u\n", type,
sseu_subslice_total(sseu));
- seq_printf(m, " %s Subslice Mask: %04x\n", type,
- sseu->subslice_mask);
- seq_printf(m, " %s Subslice Per Slice: %u\n", type,
- hweight8(sseu->subslice_mask));
+ for (s = 0; s < fls(sseu->slice_mask); s++) {
+ seq_printf(m, " %s Slice%i Subslice Mask: %04x\n", type,
+ s, sseu->subslices_mask[s]);
+ }
seq_printf(m, " %s EU Total: %u\n", type,
sseu->eu_total);
seq_printf(m, " %s EU Per Subslice: %u\n", type,
diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index 72bea281edb7..8b99e415c345 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -414,7 +414,7 @@ static int i915_getparam(struct drm_device *dev, void *data,
return -
[Intel-gfx] [PATCH 3/6] drm/i915/debugfs: add rcs topology entry
While the end goal is to make this information available to userspace
through a new ioctl, there is no reason we can't display it in a human
readable fashion through debugfs.
slice0 (subslice_mask=0x7):
subslice0:
eu_mask: 0xff (8)
subslice1:
eu_mask: 0xff (8)
subslice2:
eu_mask: 0xff (8)
subslice3:
eu_mask: 0x0 (0)
slice1 (subslice_mask=0x7):
subslice0:
eu_mask: 0xff (8)
subslice1:
eu_mask: 0xff (8)
subslice2:
eu_mask: 0xff (8)
subslice3:
eu_mask: 0x0 (0)
slice2 (subslice_mask=0x7):
subslice0:
eu_mask: 0xff (8)
subslice1:
eu_mask: 0xff (8)
subslice2:
eu_mask: 0xff (8)
subslice3:
eu_mask: 0x0 (0)
Suggested-by: Chris Wilson
Signed-off-by: Lionel Landwerlin
---
drivers/gpu/drm/i915/i915_debugfs.c | 37 +
1 file changed, 37 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_debugfs.c
b/drivers/gpu/drm/i915/i915_debugfs.c
index 6ec7543e698f..79ca6e9f9ec9 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -3173,6 +3173,42 @@ static int i915_engine_info(struct seq_file *m, void
*unused)
return 0;
}
+static int i915_rcs_topology(struct seq_file *m, void *unused)
+{
+ struct drm_i915_private *dev_priv = node_to_i915(m->private);
+ const struct sseu_dev_info *sseu = &INTEL_INFO(dev_priv)->sseu;
+ int s, ss;
+ int subslice_stride = ALIGN(sseu->max_eus_per_subslice, 8) / 8;
+ int slice_stride = sseu->max_subslices * subslice_stride;
+
+ if (sseu->max_slices == 0) {
+ seq_printf(m, "Unavailable\n");
+ return 0;
+ }
+
+ for (s = 0; s < sseu->max_slices; s++) {
+ seq_printf(m, "slice%i (subslice_mask=0x%x):\n",
+ s, sseu->subslices_mask[s]);
+
+ for (ss = 0; ss < slice_stride / subslice_stride; ss++) {
+ int eu, n_subslice_eus = 0;
+
+ seq_printf(m, "\tsubslice%i:\n", ss);
+
+ seq_printf(m, "\t\teu_mask:");
+ for (eu = 0; eu < subslice_stride; eu++) {
+ u8 val = sseu->eu_mask[s * slice_stride +
+ ss * subslice_stride +
eu];
+ seq_printf(m, " 0x%x", val);
+ n_subslice_eus += hweight8(val);
+ }
+ seq_printf(m, " (%i)\n", n_subslice_eus);
+ }
+ }
+
+ return 0;
+}
+
static int i915_shrinker_info(struct seq_file *m, void *unused)
{
struct drm_i915_private *i915 = node_to_i915(m->private);
@@ -4658,6 +4694,7 @@ static const struct drm_info_list i915_debugfs_list[] = {
{"i915_dmc_info", i915_dmc_info, 0},
{"i915_display_info", i915_display_info, 0},
{"i915_engine_info", i915_engine_info, 0},
+ {"i915_rcs_topology", i915_rcs_topology, 0},
{"i915_shrinker_info", i915_shrinker_info, 0},
{"i915_shared_dplls_info", i915_shared_dplls_info, 0},
{"i915_dp_mst_info", i915_dp_mst_info, 0},
--
2.15.1
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 2/6] drm/i915/debugfs: reuse max slice/subslices already stored in sseu
Now that we have that information in topology fields, let's just reused it.
Signed-off-by: Lionel Landwerlin
---
drivers/gpu/drm/i915/i915_debugfs.c | 26 ++
1 file changed, 10 insertions(+), 16 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_debugfs.c
b/drivers/gpu/drm/i915/i915_debugfs.c
index 0c7890b695c5..6ec7543e698f 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -4308,11 +4308,11 @@ static void gen10_sseu_device_status(struct
drm_i915_private *dev_priv,
struct sseu_dev_info *sseu)
{
const struct intel_device_info *info = INTEL_INFO(dev_priv);
- int s_max = 6, ss_max = 4;
int s, ss;
- u32 s_reg[s_max], eu_reg[2 * s_max], eu_mask[2];
+ u32 s_reg[info->sseu.max_slices],
+ eu_reg[2 * info->sseu.max_subslices], eu_mask[2];
- for (s = 0; s < s_max; s++) {
+ for (s = 0; s < info->sseu.max_slices; s++) {
/*
* FIXME: Valid SS Mask respects the spec and read
* only valid bits for those registers, excluding reserverd
@@ -4334,7 +4334,7 @@ static void gen10_sseu_device_status(struct
drm_i915_private *dev_priv,
GEN9_PGCTL_SSB_EU210_ACK |
GEN9_PGCTL_SSB_EU311_ACK;
- for (s = 0; s < s_max; s++) {
+ for (s = 0; s < info->sseu.max_slices; s++) {
if ((s_reg[s] & GEN9_PGCTL_SLICE_ACK) == 0)
/* skip disabled slice */
continue;
@@ -4342,7 +4342,7 @@ static void gen10_sseu_device_status(struct
drm_i915_private *dev_priv,
sseu->slice_mask |= BIT(s);
sseu->subslices_mask[s] = info->sseu.subslices_mask[s];
- for (ss = 0; ss < ss_max; ss++) {
+ for (ss = 0; ss < info->sseu.max_subslices; ss++) {
unsigned int eu_cnt;
if (!(s_reg[s] & (GEN9_PGCTL_SS_ACK(ss
@@ -4362,17 +4362,11 @@ static void gen10_sseu_device_status(struct
drm_i915_private *dev_priv,
static void gen9_sseu_device_status(struct drm_i915_private *dev_priv,
struct sseu_dev_info *sseu)
{
- int s_max = 3, ss_max = 4;
+ const struct intel_device_info *info = INTEL_INFO(dev_priv);
int s, ss;
- u32 s_reg[s_max], eu_reg[2*s_max], eu_mask[2];
-
- /* BXT has a single slice and at most 3 subslices. */
- if (IS_GEN9_LP(dev_priv)) {
- s_max = 1;
- ss_max = 3;
- }
+ u32 s_reg[info->sseu.max_slices], eu_reg[2*info->sseu.max_subslices],
eu_mask[2];
- for (s = 0; s < s_max; s++) {
+ for (s = 0; s < info->sseu.max_slices; s++) {
s_reg[s] = I915_READ(GEN9_SLICE_PGCTL_ACK(s));
eu_reg[2*s] = I915_READ(GEN9_SS01_EU_PGCTL_ACK(s));
eu_reg[2*s + 1] = I915_READ(GEN9_SS23_EU_PGCTL_ACK(s));
@@ -4387,7 +4381,7 @@ static void gen9_sseu_device_status(struct
drm_i915_private *dev_priv,
GEN9_PGCTL_SSB_EU210_ACK |
GEN9_PGCTL_SSB_EU311_ACK;
- for (s = 0; s < s_max; s++) {
+ for (s = 0; s < info->sseu.max_slices; s++) {
if ((s_reg[s] & GEN9_PGCTL_SLICE_ACK) == 0)
/* skip disabled slice */
continue;
@@ -4398,7 +4392,7 @@ static void gen9_sseu_device_status(struct
drm_i915_private *dev_priv,
sseu->subslices_mask[s] =
INTEL_INFO(dev_priv)->sseu.subslices_mask[s];
- for (ss = 0; ss < ss_max; ss++) {
+ for (ss = 0; ss < info->sseu.max_subslices; ss++) {
unsigned int eu_cnt;
if (IS_GEN9_LP(dev_priv)) {
--
2.15.1
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 6/6] drm/i915: expose rcs topology through query uAPI
With the introduction of asymetric slices in CNL, we cannot rely on
the previous SUBSLICE_MASK getparam to tell userspace what subslices
are available. Here we introduce a more detailed way of querying the
Gen's GPU topology that doesn't aggregate numbers.
This is essential for monitoring parts of the GPU with the OA unit,
because counters need to be normalized to the number of
EUs/subslices/slices. The current aggregated numbers like EU_TOTAL do
not gives us sufficient information.
As a bonus we can draw representations of the GPU :
https://imgur.com/a/vuqpa
Signed-off-by: Lionel Landwerlin
---
drivers/gpu/drm/i915/i915_query.c | 134
drivers/gpu/drm/i915/intel_query_info.c | 88 +
include/uapi/drm/i915_drm.h | 45 +++
3 files changed, 267 insertions(+)
create mode 100644 drivers/gpu/drm/i915/intel_query_info.c
diff --git a/drivers/gpu/drm/i915/i915_query.c
b/drivers/gpu/drm/i915/i915_query.c
index 227a28978190..7c0eb09d3aac 100644
--- a/drivers/gpu/drm/i915/i915_query.c
+++ b/drivers/gpu/drm/i915/i915_query.c
@@ -25,24 +25,158 @@
#include "i915_drv.h"
#include
+static int query_slices_mask(struct drm_i915_private *dev_priv,
+struct drm_i915_query_item *query_item)
+{
+ const struct sseu_dev_info *sseu = &INTEL_INFO(dev_priv)->sseu;
+ struct drm_i915_query_slices_mask slices_info;
+ u32 data_length, length;
+
+ if (sseu->max_slices == 0)
+ return -ENODEV;
+
+ memset(&slices_info, 0, sizeof(slices_info));
+
+ slices_info.n_slices = sseu->max_slices;
+
+ data_length = sizeof(u8);
+ length = sizeof(struct drm_i915_query_slices_mask) + data_length;
+
+ /*
+* If we ever change the internal slice mask data type, we'll need to
+* update this function.
+*/
+ BUILD_BUG_ON(sizeof(u8) != sizeof(sseu->slice_mask));
+
+ if (query_item->length == 0) {
+ query_item->length = length;
+ return 0;
+ }
+
+ if (query_item->length != length)
+ return -EINVAL;
+
+ if (copy_to_user(u64_to_user_ptr(query_item->data_ptr), &slices_info,
+sizeof(slices_info)))
+ return -EFAULT;
+
+ if (copy_to_user(u64_to_user_ptr(query_item->data_ptr +
+offsetof(struct
drm_i915_query_slices_mask, data)),
+&sseu->slice_mask, data_length))
+ return -EFAULT;
+
+ return 0;
+}
+
+static int query_subslices_mask(struct drm_i915_private *dev_priv,
+ struct drm_i915_query_item *query_item)
+{
+ const struct sseu_dev_info *sseu = &INTEL_INFO(dev_priv)->sseu;
+ struct drm_i915_query_subslices_mask subslices_info;
+ u32 data_length, length;
+
+ if (sseu->max_slices == 0)
+ return -ENODEV;
+
+ memset(&subslices_info, 0, sizeof(subslices_info));
+
+ subslices_info.n_slices = sseu->max_slices;
+ subslices_info.slice_stride = ALIGN(sseu->max_subslices, 8) / 8;
+
+ data_length = subslices_info.n_slices * subslices_info.slice_stride;
+ length = sizeof(struct drm_i915_query_subslices_mask) + data_length;
+
+ if (query_item->length == 0) {
+ query_item->length = length;
+ return 0;
+ }
+
+ if (query_item->length != length)
+ return -EINVAL;
+
+ if (copy_to_user(u64_to_user_ptr(query_item->data_ptr), &subslices_info,
+sizeof(subslices_info)))
+ return -EFAULT;
+
+ if (copy_to_user(u64_to_user_ptr(query_item->data_ptr +
+offsetof(struct
drm_i915_query_subslices_mask, data)),
+sseu->subslices_mask, data_length))
+ return -EFAULT;
+
+ return 0;
+}
+
+static int query_eus_mask(struct drm_i915_private *dev_priv,
+ struct drm_i915_query_item *query_item)
+{
+ const struct sseu_dev_info *sseu = &INTEL_INFO(dev_priv)->sseu;
+ struct drm_i915_query_eus_mask eus_info;
+ u32 data_length, length;
+
+ if (sseu->max_slices == 0)
+ return -ENODEV;
+
+ memset(&eus_info, 0, sizeof(eus_info));
+
+ eus_info.subslice_stride = ALIGN(sseu->max_eus_per_subslice, 8) / 8;
+ eus_info.slice_stride = sseu->max_subslices * eus_info.subslice_stride;
+ eus_info.n_slices = sseu->max_slices;
+
+ data_length = eus_info.n_slices * eus_info.slice_stride;
+ length = sizeof(struct drm_i915_query_eus_mask) + data_length;
+
+ if (query_item->length == 0) {
+ query_item->length = length;
+ return 0;
+ }
+
+ if (query_item->length != length)
+ return -EINVAL;
+
+ if (copy_to_user(u64_to_user_ptr(query_item->data_ptr), &eus_info,
+
[Intel-gfx] [PATCH 4/6] drm/i915: add rcs topology to error state
This might be useful information for developers looking at an error
state.
Signed-off-by: Lionel Landwerlin
---
drivers/gpu/drm/i915/i915_gpu_error.c | 35 +++
1 file changed, 35 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_gpu_error.c
b/drivers/gpu/drm/i915/i915_gpu_error.c
index aba50aa613f1..ba0e4cd082c4 100644
--- a/drivers/gpu/drm/i915/i915_gpu_error.c
+++ b/drivers/gpu/drm/i915/i915_gpu_error.c
@@ -621,6 +621,40 @@ static void err_print_uc(struct drm_i915_error_state_buf
*m,
print_error_obj(m, NULL, "GuC log buffer", error_uc->guc_log);
}
+static void err_print_rcs_topology(struct drm_i915_error_state_buf *m,
+ const struct sseu_dev_info *sseu)
+{
+ int s, ss;
+ int subslice_stride = ALIGN(sseu->max_eus_per_subslice, 8) / 8;
+ int slice_stride = sseu->max_subslices * subslice_stride;
+
+ /* Unavailable prior to Gen 8. */
+ if (sseu->max_slices == 0)
+ return;
+
+ err_printf(m, "RCS topology:\n");
+
+ for (s = 0; s < sseu->max_slices; s++) {
+ err_printf(m, " slice%i (subslice_mask=0x%x):\n",
+ s, sseu->subslices_mask[s]);
+
+ for (ss = 0; ss < slice_stride / subslice_stride; ss++) {
+ int eu, n_subslice_eus = 0;
+
+ err_printf(m, "subslice%i:\n", ss);
+
+ err_printf(m, " eu_mask:");
+ for (eu = 0; eu < subslice_stride; eu++) {
+ u8 val = sseu->eu_mask[s * slice_stride +
+ ss * subslice_stride +
eu];
+ err_printf(m, " 0x%x", val);
+ n_subslice_eus += hweight8(val);
+ }
+ err_printf(m, " (%i)\n", n_subslice_eus);
+ }
+ }
+}
+
int i915_error_state_to_str(struct drm_i915_error_state_buf *m,
const struct i915_gpu_state *error)
{
@@ -657,6 +691,7 @@ int i915_error_state_to_str(struct drm_i915_error_state_buf
*m,
err_printf(m, "Suspend count: %u\n", error->suspend_count);
err_printf(m, "Platform: %s\n",
intel_platform_name(error->device_info.platform));
err_print_pciid(m, error->i915);
+ err_print_rcs_topology(m, &INTEL_INFO(dev_priv)->sseu);
err_printf(m, "IOMMU enabled?: %d\n", error->iommu);
--
2.15.1
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 5/6] drm/i915: add query uAPI
There are a number of information that are readable from hardware
registers and that we would like to make accessible to userspace. One
particular example is the topology of the execution units (how are
execution units grouped in subslices and slices and also which ones
have been fused off for die recovery).
At the moment the GET_PARAM ioctl covers some basic needs, but
generally is only able to return a single value for each defined
parameter. This is a bit problematic with topology descriptions which
are array/maps of available units.
This change introduces a new ioctl that can deal with requests to fill
structures of potentially variable lengths. The user is expected fill
a query with length fields set at 0 on the first call, the kernel then
sets the length fields to the their expected values. A second call to
the kernel with length fields at their expected values will trigger a
copy of the data to the pointed memory locations.
The scope of this uAPI is only to provide information to userspace,
not to allow configuration of the device.
Signed-off-by: Lionel Landwerlin
---
drivers/gpu/drm/i915/Makefile | 1 +
drivers/gpu/drm/i915/i915_drv.c | 1 +
drivers/gpu/drm/i915/i915_drv.h | 3 +++
drivers/gpu/drm/i915/i915_query.c | 52 +++
include/uapi/drm/i915_drm.h | 31 +++
5 files changed, 88 insertions(+)
create mode 100644 drivers/gpu/drm/i915/i915_query.c
diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makefile
index 091aef281963..9627e7e309dc 100644
--- a/drivers/gpu/drm/i915/Makefile
+++ b/drivers/gpu/drm/i915/Makefile
@@ -69,6 +69,7 @@ i915-y += i915_cmd_parser.o \
i915_gem_timeline.o \
i915_gem_userptr.o \
i915_gemfs.o \
+ i915_query.o \
i915_trace_points.o \
i915_vma.o \
intel_breadcrumbs.o \
diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index 8b99e415c345..a90ed9f2b759 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -2814,6 +2814,7 @@ static const struct drm_ioctl_desc i915_ioctls[] = {
DRM_IOCTL_DEF_DRV(I915_PERF_OPEN, i915_perf_open_ioctl,
DRM_RENDER_ALLOW),
DRM_IOCTL_DEF_DRV(I915_PERF_ADD_CONFIG, i915_perf_add_config_ioctl,
DRM_UNLOCKED|DRM_RENDER_ALLOW),
DRM_IOCTL_DEF_DRV(I915_PERF_REMOVE_CONFIG,
i915_perf_remove_config_ioctl, DRM_UNLOCKED|DRM_RENDER_ALLOW),
+ DRM_IOCTL_DEF_DRV(I915_QUERY, i915_query_ioctl,
DRM_UNLOCKED|DRM_RENDER_ALLOW),
};
static struct drm_driver driver = {
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 82fc59078c6a..3415a3d2399c 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -4084,6 +4084,9 @@ extern void i915_perf_fini(struct drm_i915_private
*dev_priv);
extern void i915_perf_register(struct drm_i915_private *dev_priv);
extern void i915_perf_unregister(struct drm_i915_private *dev_priv);
+/* i915_query.c */
+int i915_query_ioctl(struct drm_device *dev, void *data, struct drm_file
*file);
+
/* i915_suspend.c */
extern int i915_save_state(struct drm_i915_private *dev_priv);
extern int i915_restore_state(struct drm_i915_private *dev_priv);
diff --git a/drivers/gpu/drm/i915/i915_query.c
b/drivers/gpu/drm/i915/i915_query.c
new file mode 100644
index ..227a28978190
--- /dev/null
+++ b/drivers/gpu/drm/i915/i915_query.c
@@ -0,0 +1,52 @@
+/*
+ * Copyright © 2017 Intel Corporation
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the next
+ * paragraph) shall be included in all copies or substantial portions of the
+ * Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
+ * IN THE SOFTWARE.
+ *
+ */
+
+#include "i915_drv.h"
+#include
+
+int i915_query_ioctl(struct drm_device *dev, void *data, struct drm_file *file)
+{
+ struct drm_i915_query *args = data;
+ u32 i;
+
+ for (i = 0; i < args->num_items; i++) {
+ struct drm_i915_query_item item;
+ u64 item_user_ptr = args->item
[Intel-gfx] [PATCH i-g-t] tests: add i915 query tests
Signed-off-by: Lionel Landwerlin
---
tests/Makefile.sources | 1 +
tests/meson.build | 1 +
tests/query.c | 262 +
3 files changed, 264 insertions(+)
create mode 100644 tests/query.c
diff --git a/tests/Makefile.sources b/tests/Makefile.sources
index e4e06d01..390cc82b 100644
--- a/tests/Makefile.sources
+++ b/tests/Makefile.sources
@@ -227,6 +227,7 @@ TESTS_progs = \
prime_self_import \
prime_udl \
prime_vgem \
+ query \
sw_sync \
syncobj_basic \
syncobj_wait \
diff --git a/tests/meson.build b/tests/meson.build
index 191ac4ce..f3ef6198 100644
--- a/tests/meson.build
+++ b/tests/meson.build
@@ -204,6 +204,7 @@ test_progs = [
'prime_self_import',
'prime_udl',
'prime_vgem',
+ 'query',
'sw_sync',
'syncobj_basic',
'syncobj_wait',
diff --git a/tests/query.c b/tests/query.c
new file mode 100644
index ..6da500f7
--- /dev/null
+++ b/tests/query.c
@@ -0,0 +1,262 @@
+/*
+ * Copyright © 2017 Intel Corporation
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the next
+ * paragraph) shall be included in all copies or substantial portions of the
+ * Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
+ * IN THE SOFTWARE.
+ */
+
+#include "igt.h"
+
+IGT_TEST_DESCRIPTION("Testing the query uAPI.");
+
+static bool has_query_supports(int fd)
+{
+ struct drm_i915_query query = {};
+
+ return igt_ioctl(fd, DRM_IOCTL_I915_QUERY, &query) == 0;
+}
+
+static void test_query_garbage(int fd)
+{
+ struct drm_i915_query query;
+ struct drm_i915_query_item items[2];
+
+ memset(&query, 0, sizeof(query));
+ query.num_items = 1;
+ query.items_ptr = 0x;
+ do_ioctl_err(fd, DRM_IOCTL_I915_QUERY, &query, EFAULT);
+
+ memset(&query, 0, sizeof(query));
+ query.num_items = 1;
+ query.items_ptr = 0;
+ do_ioctl_err(fd, DRM_IOCTL_I915_QUERY, &query, EFAULT);
+
+ memset(&query, 0, sizeof(query));
+ query.num_items = 2;
+ query.items_ptr = (uintptr_t) items;
+ memset(items, 0, sizeof(items));
+ items[0].query_id = 0x;
+ do_ioctl_err(fd, DRM_IOCTL_I915_QUERY, &query, EINVAL);
+
+ memset(&query, 0, sizeof(query));
+ query.num_items = 2;
+ query.items_ptr = (uintptr_t) items;
+ memset(items, 0, sizeof(items));
+ do_ioctl_err(fd, DRM_IOCTL_I915_QUERY, &query, EINVAL);
+
+ memset(&query, 0, sizeof(query));
+ query.num_items = 2;
+ query.items_ptr = (uintptr_t) items;
+ memset(items, 0, sizeof(items));
+ items[0].query_id = DRM_I915_QUERY_ID_SLICES_MASK;
+ items[0].length = 0x;
+ items[1].query_id = DRM_I915_QUERY_ID_SUBSLICES_MASK;
+ do_ioctl_err(fd, DRM_IOCTL_I915_QUERY, &query, EINVAL);
+}
+
+static bool query_topology_supported(int fd)
+{
+ struct drm_i915_query query;
+ struct drm_i915_query_item item;
+
+ memset(&query, 0, sizeof(query));
+ query.num_items = 1;
+ query.items_ptr = (uintptr_t) &item;
+
+ memset(&item, 0, sizeof(item));
+ item.query_id = DRM_I915_QUERY_ID_SLICES_MASK;
+
+ return igt_ioctl(fd, DRM_IOCTL_I915_QUERY, &query) == 0;
+}
+
+static void test_query_topology_pre_gen8(int fd)
+{
+ struct drm_i915_query query;
+ struct drm_i915_query_item item;
+
+ memset(&query, 0, sizeof(query));
+ query.num_items = 1;
+ query.items_ptr = (uintptr_t) &item;
+
+ memset(&item, 0, sizeof(item));
+ item.query_id = DRM_I915_QUERY_ID_SLICES_MASK;
+
+ do_ioctl_err(fd, DRM_IOCTL_I915_QUERY, &query, ENODEV);
+}
+
+static void
+test_query_topology_coherent_slice_mask(int fd)
+{
+ struct drm_i915_query query;
+ struct drm_i915_query_item item;
+ struct drm_i915_query_slices_mask *slices_mask;
+ struct drm_i915_query_subslices_mask *subslices_mask;
+ drm_i915_getparam_t gp;
+ int slice_mask, subslice_mask;
+ int i, topology_slices, top
Re: [Intel-gfx] [PATCH 4/6] drm/i915: add rcs topology to error state
Quoting Lionel Landwerlin (2017-12-18 15:35:18)
> This might be useful information for developers looking at an error
> state.
>
> Signed-off-by: Lionel Landwerlin
> ---
> drivers/gpu/drm/i915/i915_gpu_error.c | 35
> +++
> 1 file changed, 35 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/i915_gpu_error.c
> b/drivers/gpu/drm/i915/i915_gpu_error.c
> index aba50aa613f1..ba0e4cd082c4 100644
> --- a/drivers/gpu/drm/i915/i915_gpu_error.c
> +++ b/drivers/gpu/drm/i915/i915_gpu_error.c
> @@ -621,6 +621,40 @@ static void err_print_uc(struct drm_i915_error_state_buf
> *m,
> print_error_obj(m, NULL, "GuC log buffer", error_uc->guc_log);
> }
>
> +static void err_print_rcs_topology(struct drm_i915_error_state_buf *m,
> + const struct sseu_dev_info *sseu)
> +{
> + int s, ss;
> + int subslice_stride = ALIGN(sseu->max_eus_per_subslice, 8) / 8;
> + int slice_stride = sseu->max_subslices * subslice_stride;
> +
> + /* Unavailable prior to Gen 8. */
> + if (sseu->max_slices == 0)
> + return;
> +
> + err_printf(m, "RCS topology:\n");
> +
> + for (s = 0; s < sseu->max_slices; s++) {
> + err_printf(m, " slice%i (subslice_mask=0x%x):\n",
> + s, sseu->subslices_mask[s]);
> +
> + for (ss = 0; ss < slice_stride / subslice_stride; ss++) {
> + int eu, n_subslice_eus = 0;
> +
> + err_printf(m, "subslice%i:\n", ss);
> +
> + err_printf(m, " eu_mask:");
> + for (eu = 0; eu < subslice_stride; eu++) {
> + u8 val = sseu->eu_mask[s * slice_stride +
> + ss * subslice_stride +
> eu];
> + err_printf(m, " 0x%x", val);
> + n_subslice_eus += hweight8(val);
> + }
> + err_printf(m, " (%i)\n", n_subslice_eus);
> + }
> + }
> +}
> +
> int i915_error_state_to_str(struct drm_i915_error_state_buf *m,
> const struct i915_gpu_state *error)
> {
> @@ -657,6 +691,7 @@ int i915_error_state_to_str(struct
> drm_i915_error_state_buf *m,
> err_printf(m, "Suspend count: %u\n", error->suspend_count);
> err_printf(m, "Platform: %s\n",
> intel_platform_name(error->device_info.platform));
> err_print_pciid(m, error->i915);
> + err_print_rcs_topology(m, &INTEL_INFO(dev_priv)->sseu);
I don't think it's going to be that crucial (that it needs to be at the
start of the error-state, in your face). More likely down in the platform
capabilities after the user state.
-Chris
___
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915: improve tracepoints for process/hw_id tracking (rev2)
== Series Details == Series: drm/i915: improve tracepoints for process/hw_id tracking (rev2) URL : https://patchwork.freedesktop.org/series/35506/ State : success == Summary == Series 35506v2 drm/i915: improve tracepoints for process/hw_id tracking https://patchwork.freedesktop.org/api/1.0/series/35506/revisions/2/mbox/ Test debugfs_test: Subgroup read_all_entries: dmesg-warn -> DMESG-FAIL (fi-elk-e7500) fdo#103989 +1 Test kms_pipe_crc_basic: Subgroup suspend-read-crc-pipe-a: dmesg-warn -> PASS (fi-kbl-r) fdo#104172 +1 Subgroup suspend-read-crc-pipe-c: incomplete -> PASS (fi-bdw-5557u) fdo#104162 Test kms_psr_sink_crc: Subgroup psr_basic: pass -> DMESG-WARN (fi-skl-6700hq) fdo#101144 fdo#103989 https://bugs.freedesktop.org/show_bug.cgi?id=103989 fdo#104172 https://bugs.freedesktop.org/show_bug.cgi?id=104172 fdo#104162 https://bugs.freedesktop.org/show_bug.cgi?id=104162 fdo#101144 https://bugs.freedesktop.org/show_bug.cgi?id=101144 fi-bdw-5557u total:288 pass:267 dwarn:0 dfail:0 fail:0 skip:21 time:432s fi-bdw-gvtdvmtotal:288 pass:264 dwarn:0 dfail:0 fail:0 skip:24 time:443s fi-blb-e6850 total:288 pass:223 dwarn:1 dfail:0 fail:0 skip:64 time:380s fi-bsw-n3050 total:288 pass:242 dwarn:0 dfail:0 fail:0 skip:46 time:492s fi-bwr-2160 total:288 pass:183 dwarn:0 dfail:0 fail:0 skip:105 time:275s fi-bxt-dsi total:288 pass:258 dwarn:0 dfail:0 fail:0 skip:30 time:494s fi-bxt-j4205 total:288 pass:259 dwarn:0 dfail:0 fail:0 skip:29 time:491s fi-byt-j1900 total:288 pass:253 dwarn:0 dfail:0 fail:0 skip:35 time:479s fi-byt-n2820 total:288 pass:249 dwarn:0 dfail:0 fail:0 skip:39 time:462s fi-elk-e7500 total:224 pass:163 dwarn:14 dfail:1 fail:0 skip:45 fi-gdg-551 total:288 pass:178 dwarn:1 dfail:0 fail:1 skip:108 time:264s fi-glk-1 total:288 pass:260 dwarn:0 dfail:0 fail:0 skip:28 time:528s fi-hsw-4770 total:288 pass:261 dwarn:0 dfail:0 fail:0 skip:27 time:404s fi-hsw-4770r total:288 pass:261 dwarn:0 dfail:0 fail:0 skip:27 time:409s fi-ilk-650 total:288 pass:228 dwarn:0 dfail:0 fail:0 skip:60 time:383s fi-ivb-3520m total:288 pass:259 dwarn:0 dfail:0 fail:0 skip:29 time:477s fi-ivb-3770 total:288 pass:255 dwarn:0 dfail:0 fail:0 skip:33 time:423s fi-kbl-7500u total:288 pass:263 dwarn:1 dfail:0 fail:0 skip:24 time:481s fi-kbl-7560u total:288 pass:268 dwarn:1 dfail:0 fail:0 skip:19 time:522s fi-kbl-7567u total:288 pass:268 dwarn:0 dfail:0 fail:0 skip:20 time:469s fi-kbl-r total:288 pass:260 dwarn:1 dfail:0 fail:0 skip:27 time:518s fi-pnv-d510 total:288 pass:222 dwarn:1 dfail:0 fail:0 skip:65 time:580s fi-skl-6260u total:288 pass:268 dwarn:0 dfail:0 fail:0 skip:20 time:446s fi-skl-6600u total:288 pass:260 dwarn:1 dfail:0 fail:0 skip:27 time:538s fi-skl-6700hqtotal:288 pass:261 dwarn:1 dfail:0 fail:0 skip:26 time:562s fi-skl-6700k2total:288 pass:264 dwarn:0 dfail:0 fail:0 skip:24 time:501s fi-skl-6770hqtotal:288 pass:268 dwarn:0 dfail:0 fail:0 skip:20 time:498s fi-skl-gvtdvmtotal:288 pass:265 dwarn:0 dfail:0 fail:0 skip:23 time:444s fi-snb-2520m total:288 pass:248 dwarn:0 dfail:0 fail:0 skip:40 time:547s fi-snb-2600 total:288 pass:248 dwarn:0 dfail:0 fail:0 skip:40 time:406s Blacklisted hosts: fi-cfl-s2total:288 pass:262 dwarn:0 dfail:0 fail:0 skip:26 time:590s fi-cnl-y total:288 pass:262 dwarn:0 dfail:0 fail:0 skip:26 time:608s fi-glk-dsi total:288 pass:190 dwarn:1 dfail:4 fail:0 skip:93 time:418s 913d6a0d4d78fba4cb62a1ac14d539d959fe422a drm-tip: 2017y-12m-18d-13h-25m-28s UTC integration manifest 8a4b5e5e1aa9 drm/i915/trace: add hw_id to gem requests trace points 8d7362e4f3c5 drm/i915: reorder field in gem_request tracepoints == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_7526/issues.html ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 2/2] drm/i915: Add pretty printer for modparams
We dump modparams in few places (debugfs, gpu_error) using different
functions. Lets add reusable function to avoid code duplication.
add/remove: 1/0 grow/shrink: 0/2 up/down: 1096/-2339 (-1243)
Function old new delta
i915_params_dump -1096 +1096
i915_capabilities 1353 185 -1168
i915_error_state_to_str 55074336 -1171
Total: Before=1285716, After=1284473, chg -0.10%
Signed-off-by: Michal Wajdeczko
Cc: Chris Wilson
---
drivers/gpu/drm/i915/i915_debugfs.c | 21 +
drivers/gpu/drm/i915/i915_gpu_error.c | 25 -
drivers/gpu/drm/i915/i915_params.c| 31 +++
drivers/gpu/drm/i915/i915_params.h| 3 +++
4 files changed, 39 insertions(+), 41 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_debugfs.c
b/drivers/gpu/drm/i915/i915_debugfs.c
index e384e28..c4780f0 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -37,23 +37,6 @@ static inline struct drm_i915_private *node_to_i915(struct
drm_info_node *node)
return to_i915(node->minor->dev);
}
-static __always_inline void seq_print_param(struct seq_file *m,
- const char *name,
- const char *type,
- const void *x)
-{
- if (!__builtin_strcmp(type, "bool"))
- seq_printf(m, "i915.%s=%s\n", name, yesno(*(const bool *)x));
- else if (!__builtin_strcmp(type, "int"))
- seq_printf(m, "i915.%s=%d\n", name, *(const int *)x);
- else if (!__builtin_strcmp(type, "unsigned int"))
- seq_printf(m, "i915.%s=%u\n", name, *(const unsigned int *)x);
- else if (!__builtin_strcmp(type, "char *"))
- seq_printf(m, "i915.%s=%s\n", name, *(const char **)x);
- else
- BUILD_BUG();
-}
-
static int i915_capabilities(struct seq_file *m, void *data)
{
struct drm_i915_private *dev_priv = node_to_i915(m->private);
@@ -67,9 +50,7 @@ static int i915_capabilities(struct seq_file *m, void *data)
intel_device_info_dump_flags(info, &p);
kernel_param_lock(THIS_MODULE);
-#define PRINT_PARAM(T, x, ...) seq_print_param(m, #x, #T, &i915_modparams.x);
- I915_PARAMS_FOR_EACH(PRINT_PARAM);
-#undef PRINT_PARAM
+ i915_params_dump(&i915_modparams, &p);
kernel_param_unlock(THIS_MODULE);
return 0;
diff --git a/drivers/gpu/drm/i915/i915_gpu_error.c
b/drivers/gpu/drm/i915/i915_gpu_error.c
index 664f55c..84831e9 100644
--- a/drivers/gpu/drm/i915/i915_gpu_error.c
+++ b/drivers/gpu/drm/i915/i915_gpu_error.c
@@ -569,29 +569,12 @@ static void err_print_capabilities(struct
drm_i915_error_state_buf *m,
intel_device_info_dump_flags(info, &p);
}
-static __always_inline void err_print_param(struct drm_i915_error_state_buf *m,
- const char *name,
- const char *type,
- const void *x)
-{
- if (!__builtin_strcmp(type, "bool"))
- err_printf(m, "i915.%s=%s\n", name, yesno(*(const bool *)x));
- else if (!__builtin_strcmp(type, "int"))
- err_printf(m, "i915.%s=%d\n", name, *(const int *)x);
- else if (!__builtin_strcmp(type, "unsigned int"))
- err_printf(m, "i915.%s=%u\n", name, *(const unsigned int *)x);
- else if (!__builtin_strcmp(type, "char *"))
- err_printf(m, "i915.%s=%s\n", name, *(const char **)x);
- else
- BUILD_BUG();
-}
-
static void err_print_params(struct drm_i915_error_state_buf *m,
-const struct i915_params *p)
+const struct i915_params *params)
{
-#define PRINT(T, x, ...) err_print_param(m, #x, #T, &p->x);
- I915_PARAMS_FOR_EACH(PRINT);
-#undef PRINT
+ struct drm_printer p = i915_error_printer(m);
+
+ i915_params_dump(params, &p);
}
static void err_print_pciid(struct drm_i915_error_state_buf *m,
diff --git a/drivers/gpu/drm/i915/i915_params.c
b/drivers/gpu/drm/i915/i915_params.c
index 8dfea03..d8d7189 100644
--- a/drivers/gpu/drm/i915/i915_params.c
+++ b/drivers/gpu/drm/i915/i915_params.c
@@ -172,3 +172,34 @@ struct i915_params i915_modparams __read_mostly = {
i915_param_named(enable_gvt, bool, 0400,
"Enable support for Intel GVT-g graphics virtualization host
support(default:false)");
+
+static __always_inline void _print_param(struct drm_printer *p,
+const char *name,
+const char *type,
+const void *x)
+{
+ if (!__builtin_strcmp(type, "bool"))
+ drm_printf(p, "i915.%s=%s\n", name, yesno(*(const bool *)x));
+
[Intel-gfx] [PATCH 1/2] drm/i915: Add pretty printer for device info flags
We dump device flags in few places (init_early, debugfs, gpu_error)
using different functions. Lets add reusable function to avoid
code duplication.
add/remove: 1/0 grow/shrink: 0/3 up/down: 1296/-3572 (-2276)
Function old new delta
intel_device_info_dump_flags -1296 +1296
i915_capabilities 24351353 -1082
i915_error_state_to_str 66425507 -1135
intel_device_info_dump 1507 152 -1355
Total: Before=1287992, After=1285716, chg -0.18%
Signed-off-by: Michal Wajdeczko
Cc: Chris Wilson
---
drivers/gpu/drm/i915/i915_debugfs.c | 5 ++---
drivers/gpu/drm/i915/i915_drv.h | 2 ++
drivers/gpu/drm/i915/i915_gpu_error.c| 6 +++---
drivers/gpu/drm/i915/intel_device_info.c | 20
4 files changed, 23 insertions(+), 10 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_debugfs.c
b/drivers/gpu/drm/i915/i915_debugfs.c
index 0ddce72..e384e28 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -58,14 +58,13 @@ static int i915_capabilities(struct seq_file *m, void *data)
{
struct drm_i915_private *dev_priv = node_to_i915(m->private);
const struct intel_device_info *info = INTEL_INFO(dev_priv);
+ struct drm_printer p = drm_seq_file_printer(m);
seq_printf(m, "gen: %d\n", INTEL_GEN(dev_priv));
seq_printf(m, "platform: %s\n", intel_platform_name(info->platform));
seq_printf(m, "pch: %d\n", INTEL_PCH_TYPE(dev_priv));
-#define PRINT_FLAG(x) seq_printf(m, #x ": %s\n", yesno(info->x))
- DEV_INFO_FOR_EACH_FLAG(PRINT_FLAG);
-#undef PRINT_FLAG
+ intel_device_info_dump_flags(info, &p);
kernel_param_lock(THIS_MODULE);
#define PRINT_PARAM(T, x, ...) seq_print_param(m, #x, #T, &i915_modparams.x);
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 1aba565..26ebc70 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -4165,6 +4165,8 @@ static inline int intel_opregion_get_panel_type(struct
drm_i915_private *dev)
const char *intel_platform_name(enum intel_platform platform);
void intel_device_info_runtime_init(struct drm_i915_private *dev_priv);
void intel_device_info_dump(struct drm_i915_private *dev_priv);
+void intel_device_info_dump_flags(const struct intel_device_info *info,
+ struct drm_printer *p);
/* modesetting */
extern void intel_modeset_init_hw(struct drm_device *dev);
diff --git a/drivers/gpu/drm/i915/i915_gpu_error.c
b/drivers/gpu/drm/i915/i915_gpu_error.c
index aba50aa..664f55c 100644
--- a/drivers/gpu/drm/i915/i915_gpu_error.c
+++ b/drivers/gpu/drm/i915/i915_gpu_error.c
@@ -564,9 +564,9 @@ static void print_error_obj(struct drm_i915_error_state_buf
*m,
static void err_print_capabilities(struct drm_i915_error_state_buf *m,
const struct intel_device_info *info)
{
-#define PRINT_FLAG(x) err_printf(m, #x ": %s\n", yesno(info->x))
- DEV_INFO_FOR_EACH_FLAG(PRINT_FLAG);
-#undef PRINT_FLAG
+ struct drm_printer p = i915_error_printer(m);
+
+ intel_device_info_dump_flags(info, &p);
}
static __always_inline void err_print_param(struct drm_i915_error_state_buf *m,
diff --git a/drivers/gpu/drm/i915/intel_device_info.c
b/drivers/gpu/drm/i915/intel_device_info.c
index f478be3..5a385a9 100644
--- a/drivers/gpu/drm/i915/intel_device_info.c
+++ b/drivers/gpu/drm/i915/intel_device_info.c
@@ -22,6 +22,8 @@
*
*/
+#include
+
#include "i915_drv.h"
#define PLATFORM_NAME(x) [INTEL_##x] = #x
@@ -67,6 +69,14 @@ const char *intel_platform_name(enum intel_platform platform)
return platform_names[platform];
}
+void intel_device_info_dump_flags(const struct intel_device_info *info,
+ struct drm_printer *p)
+{
+#define PRINT_FLAG(name) drm_printf(p, "%s: %s\n", #name, yesno(info->name));
+ DEV_INFO_FOR_EACH_FLAG(PRINT_FLAG);
+#undef PRINT_FLAG
+}
+
void intel_device_info_dump(struct drm_i915_private *dev_priv)
{
const struct intel_device_info *info = &dev_priv->info;
@@ -76,10 +86,12 @@ void intel_device_info_dump(struct drm_i915_private
*dev_priv)
info->gen,
dev_priv->drm.pdev->device,
dev_priv->drm.pdev->revision);
-#define PRINT_FLAG(name) \
- DRM_DEBUG_DRIVER("i915 device info: " #name ": %s", yesno(info->name))
- DEV_INFO_FOR_EACH_FLAG(PRINT_FLAG);
-#undef PRINT_FLAG
+
+ if (drm_debug & DRM_UT_DRIVER) {
+ struct drm_printer p = drm_debug_printer("i915 device info: ");
+
+ intel_device_info_dump_flags(info, &p);
+ }
}
static void gen10_sseu_info_init(struct drm_i915_private *dev_priv)
--
1.9.1
___
Intel-gfx mailing list
Intel-gfx@lists.free
Re: [Intel-gfx] [PATCH i-g-t] scripts/trace.pl: Auto-detect tracepoint field order
On 18/12/17 12:02, Tvrtko Ursulin wrote:
From: Tvrtko Ursulin
Instead of hard-coding the order of key-value pairs into regular
expressions, auto-detect them as we go.
At the same time re-factor the code so it is smaller and even
slightly faster (10-15% by a quick measurement).
Signed-off-by: Tvrtko Ursulin
Cc: Lionel Landwerlin
Cc: John Harrison
Tested-by: Lionel Landwerlin
---
scripts/trace.pl | 223 ++-
1 file changed, 71 insertions(+), 152 deletions(-)
diff --git a/scripts/trace.pl b/scripts/trace.pl
index aed9b20d8407..9b3fb6486fec 100755
--- a/scripts/trace.pl
+++ b/scripts/trace.pl
@@ -302,74 +302,6 @@ die if scalar(@args);
@ARGV = @args;
-sub parse_req
-{
- my ($line, $tp) = @_;
- state %cache;
-
- $cache{$tp} = qr/(\d+)\.(\d+):.*$tp.*ring=(\d+), ctx=(\d+),
seqno=(\d+), global(?:_seqno)?=(\d+)/ unless exists $cache{$tp};
-
- if ($line =~ $cache{$tp}) {
- return ($1, $2, $3, $4, $5, $6);
- } else {
- return undef;
- }
-}
-
-sub parse_req_hw
-{
- my ($line, $tp) = @_;
- state %cache;
-
- $cache{$tp} = qr/(\d+)\.(\d+):.*$tp.*ring=(\d+), ctx=(\d+),
seqno=(\d+), global(?:_seqno)?=(\d+), port=(\d+)/ unless exists $cache{$tp};
-
- if ($line =~ $cache{$tp}) {
- return ($1, $2, $3, $4, $5, $6, $7);
- } else {
- return undef;
- }
-}
-
-sub parse_req_wait_begin
-{
- my ($line, $tp) = @_;
-
- if ($line =~ /(\d+)\.(\d+):.*i915_gem_request_wait_begin.*ring=(\d+),
ctx=(\d+), seqno=(\d+)/) {
- return ($1, $2, $3, $4, $5);
- } else {
- return undef;
- }
-}
-
-sub parse_notify
-{
- my ($line) = @_;
-
- if ($line =~ /(\d+)\.(\d+):.*intel_engine_notify.*ring=(\d+),
seqno=(\d+)/) {
- return ($1, $2, $3, $4);
- } else {
- return undef;
- }
-}
-
-sub parse_freq
-{
- my ($line) = @_;
-
- if ($line =~ /(\d+)\.(\d+):.*intel_gpu_freq_change.*new_freq=(\d+)/) {
- return ($1, $2, $3);
- } else {
- return undef;
- }
-}
-
-sub us
-{
- my ($s, $us) = @_;
-
- return $s * 100 + $us;
-}
-
sub db_key
{
my ($ring, $ctx, $seqno) = @_;
@@ -425,86 +357,87 @@ my $prev_freq_ts = 0;
my $oldkernelwa = 0;
my ($no_queue, $no_in);
while (<>) {
- my ($s, $us, $ring, $ctx, $seqno, $global_seqno, $port);
- my $freq;
+ my @fields;
+ my @tmp;
+ my $tp_name;
+ my $time;
+ my %tp;
my $key;
chomp;
+ @fields = split ' ';
- ($s, $us, $ring, $ctx, $seqno) = parse_req_wait_begin($_);
- if (defined $s) {
- my %rw;
+ $tp_name = $fields[4];
+ @tmp = split ':', $tp_name, 2;
+ next unless $tmp[0] eq 'i915';
+ $tp_name = $tmp[1];
+ chop $tp_name;
- next if exists $ignore_ring{$ring};
+ chop $fields[3];
+ $time = $fields[3] * 100.0;
+ splice @fields, 0, 5;
- $ctx = sanitize_ctx($ctx, $ring);
- $key = db_key($ring, $ctx, $seqno);
+ foreach my $f (@fields) {
+ my @kv = split '=|,', $f;
- next if exists $reqwait{$key};
+ $kv[0] = 'global' if $kv[0] eq 'global_seqno';
- $rw{'key'} = $key;
- $rw{'ring'} = $ring;
- $rw{'seqno'} = $seqno;
- $rw{'ctx'} = $ctx;
- $rw{'start'} = us($s, $us);
- $reqwait{$key} = \%rw;
- next;
+ $tp{$kv[0]} = $kv[1];
}
- ($s, $us, $ring, $ctx, $seqno, $global_seqno) = parse_req($_, 'i915:i915_gem_request_wait_end');
- if (defined $s) {
- next if exists $ignore_ring{$ring};
+ return undef if exists $tp{'ring'} and exists $ignore_ring{$tp{'ring'}};
+
+ if ($tp_name eq 'i915_gem_request_wait_begin') {
+ my %rw;
- $ctx = sanitize_ctx($ctx, $ring);
- $key = db_key($ring, $ctx, $seqno);
+ $tp{'ctx'} = sanitize_ctx($tp{'ctx'}, $tp{'ring'});
+ $key = db_key($tp{'ring'}, $tp{'ctx'}, $tp{'seqno'});
- next unless exists $reqwait{$key};
+ next if exists $reqwait{$key};
- $reqwait{$key}->{'end'} = us($s, $us);
+ $rw{'key'} = $key;
+ $rw{'ring'} = $tp{'ring'};
+ $rw{'seqno'} = $tp{'seqno'};
+ $rw{'ctx'} = $tp{'ctx'};
+ $rw{'start'} = $time;
+ $reqwait{$key} = \%rw;
next;
- }
+ } elsif ($tp_name eq 'i915_gem_request_wait_end') {
+ $tp{'ctx'} = sanitize_ctx($tp{'ctx'}, $tp{'ring'});
+ $key = db_key($tp{'ring'}, $tp{'ctx'}, $tp{'seqno'});
- ($s, $us, $ring, $ctx, $seqno, $global_seqno) = parse_req($_, 'i915:i915_gem_request_add');
- if (defined $s) {
- my $orig_ctx = $ctx;
+
[Intel-gfx] ✗ Fi.CI.BAT: warning for drm/i915: expose RCS topology to userspace
== Series Details == Series: drm/i915: expose RCS topology to userspace URL : https://patchwork.freedesktop.org/series/35519/ State : warning == Summary == Series 35519v1 drm/i915: expose RCS topology to userspace https://patchwork.freedesktop.org/api/1.0/series/35519/revisions/1/mbox/ Test kms_busy: Subgroup basic-flip-a: pass -> DMESG-WARN (fi-elk-e7500) fdo#103989 Test kms_flip: Subgroup basic-flip-vs-modeset: pass -> DMESG-WARN (fi-hsw-4770) Test kms_force_connector_basic: Subgroup prune-stale-modes: pass -> SKIP (fi-snb-2600) Test kms_pipe_crc_basic: Subgroup suspend-read-crc-pipe-c: incomplete -> PASS (fi-bdw-5557u) fdo#104162 Test kms_psr_sink_crc: Subgroup psr_basic: pass -> DMESG-WARN (fi-skl-6700hq) fdo#101144 fdo#103989 https://bugs.freedesktop.org/show_bug.cgi?id=103989 fdo#104162 https://bugs.freedesktop.org/show_bug.cgi?id=104162 fdo#101144 https://bugs.freedesktop.org/show_bug.cgi?id=101144 fi-bdw-5557u total:288 pass:267 dwarn:0 dfail:0 fail:0 skip:21 time:431s fi-bdw-gvtdvmtotal:288 pass:264 dwarn:0 dfail:0 fail:0 skip:24 time:444s fi-blb-e6850 total:288 pass:223 dwarn:1 dfail:0 fail:0 skip:64 time:380s fi-bsw-n3050 total:288 pass:242 dwarn:0 dfail:0 fail:0 skip:46 time:498s fi-bwr-2160 total:288 pass:183 dwarn:0 dfail:0 fail:0 skip:105 time:276s fi-bxt-dsi total:288 pass:258 dwarn:0 dfail:0 fail:0 skip:30 time:497s fi-bxt-j4205 total:288 pass:259 dwarn:0 dfail:0 fail:0 skip:29 time:499s fi-byt-j1900 total:288 pass:253 dwarn:0 dfail:0 fail:0 skip:35 time:479s fi-byt-n2820 total:288 pass:249 dwarn:0 dfail:0 fail:0 skip:39 time:467s fi-elk-e7500 total:224 pass:163 dwarn:15 dfail:0 fail:0 skip:45 fi-gdg-551 total:288 pass:178 dwarn:1 dfail:0 fail:1 skip:108 time:264s fi-glk-1 total:288 pass:260 dwarn:0 dfail:0 fail:0 skip:28 time:528s fi-hsw-4770 total:288 pass:260 dwarn:1 dfail:0 fail:0 skip:27 time:401s fi-hsw-4770r total:288 pass:261 dwarn:0 dfail:0 fail:0 skip:27 time:414s fi-ilk-650 total:288 pass:228 dwarn:0 dfail:0 fail:0 skip:60 time:387s fi-ivb-3520m total:288 pass:259 dwarn:0 dfail:0 fail:0 skip:29 time:476s fi-ivb-3770 total:288 pass:255 dwarn:0 dfail:0 fail:0 skip:33 time:429s fi-kbl-7500u total:288 pass:263 dwarn:1 dfail:0 fail:0 skip:24 time:473s fi-kbl-7560u total:288 pass:268 dwarn:1 dfail:0 fail:0 skip:19 time:515s fi-kbl-7567u total:288 pass:268 dwarn:0 dfail:0 fail:0 skip:20 time:466s fi-kbl-r total:288 pass:260 dwarn:1 dfail:0 fail:0 skip:27 time:520s fi-pnv-d510 total:288 pass:222 dwarn:1 dfail:0 fail:0 skip:65 time:586s fi-skl-6260u total:288 pass:268 dwarn:0 dfail:0 fail:0 skip:20 time:442s fi-skl-6600u total:288 pass:260 dwarn:1 dfail:0 fail:0 skip:27 time:533s fi-skl-6700hqtotal:288 pass:261 dwarn:1 dfail:0 fail:0 skip:26 time:558s fi-skl-6700k2total:288 pass:264 dwarn:0 dfail:0 fail:0 skip:24 time:503s fi-skl-6770hqtotal:288 pass:268 dwarn:0 dfail:0 fail:0 skip:20 time:509s fi-skl-gvtdvmtotal:288 pass:265 dwarn:0 dfail:0 fail:0 skip:23 time:455s fi-snb-2520m total:288 pass:248 dwarn:0 dfail:0 fail:0 skip:40 time:547s fi-snb-2600 total:288 pass:247 dwarn:0 dfail:0 fail:0 skip:41 time:410s Blacklisted hosts: fi-cfl-s2total:288 pass:262 dwarn:0 dfail:0 fail:0 skip:26 time:587s fi-cnl-y total:288 pass:262 dwarn:0 dfail:0 fail:0 skip:26 time:618s fi-glk-dsi total:288 pass:178 dwarn:1 dfail:4 fail:0 skip:105 time:343s 913d6a0d4d78fba4cb62a1ac14d539d959fe422a drm-tip: 2017y-12m-18d-13h-25m-28s UTC integration manifest 647a50323213 drm/i915: expose rcs topology through query uAPI 2b45997096c4 drm/i915: add query uAPI c81319176c97 drm/i915: add rcs topology to error state 17481e1146b6 drm/i915/debugfs: add rcs topology entry fe927a0631fb drm/i915/debugfs: reuse max slice/subslices already stored in sseu da15e9f295cf drm/i915: store all subslice masks == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_7527/issues.html ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH 1/2] drm/i915: Add pretty printer for device info flags
Quoting Michal Wajdeczko (2017-12-18 15:51:31)
> We dump device flags in few places (init_early, debugfs, gpu_error)
> using different functions. Lets add reusable function to avoid
> code duplication.
>
> add/remove: 1/0 grow/shrink: 0/3 up/down: 1296/-3572 (-2276)
> Function old new delta
> intel_device_info_dump_flags -1296 +1296
> i915_capabilities 24351353 -1082
> i915_error_state_to_str 66425507 -1135
> intel_device_info_dump 1507 152 -1355
> Total: Before=1287992, After=1285716, chg -0.18%
>
> Signed-off-by: Michal Wajdeczko
> Cc: Chris Wilson
> ---
> drivers/gpu/drm/i915/i915_debugfs.c | 5 ++---
> drivers/gpu/drm/i915/i915_drv.h | 2 ++
> drivers/gpu/drm/i915/i915_gpu_error.c| 6 +++---
> drivers/gpu/drm/i915/intel_device_info.c | 20
> 4 files changed, 23 insertions(+), 10 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_debugfs.c
> b/drivers/gpu/drm/i915/i915_debugfs.c
> index 0ddce72..e384e28 100644
> --- a/drivers/gpu/drm/i915/i915_debugfs.c
> +++ b/drivers/gpu/drm/i915/i915_debugfs.c
> @@ -58,14 +58,13 @@ static int i915_capabilities(struct seq_file *m, void
> *data)
> {
> struct drm_i915_private *dev_priv = node_to_i915(m->private);
> const struct intel_device_info *info = INTEL_INFO(dev_priv);
> + struct drm_printer p = drm_seq_file_printer(m);
>
> seq_printf(m, "gen: %d\n", INTEL_GEN(dev_priv));
> seq_printf(m, "platform: %s\n", intel_platform_name(info->platform));
> seq_printf(m, "pch: %d\n", INTEL_PCH_TYPE(dev_priv));
>
> -#define PRINT_FLAG(x) seq_printf(m, #x ": %s\n", yesno(info->x))
> - DEV_INFO_FOR_EACH_FLAG(PRINT_FLAG);
> -#undef PRINT_FLAG
> + intel_device_info_dump_flags(info, &p);
>
> kernel_param_lock(THIS_MODULE);
> #define PRINT_PARAM(T, x, ...) seq_print_param(m, #x, #T, &i915_modparams.x);
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index 1aba565..26ebc70 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -4165,6 +4165,8 @@ static inline int intel_opregion_get_panel_type(struct
> drm_i915_private *dev)
> const char *intel_platform_name(enum intel_platform platform);
> void intel_device_info_runtime_init(struct drm_i915_private *dev_priv);
> void intel_device_info_dump(struct drm_i915_private *dev_priv);
> +void intel_device_info_dump_flags(const struct intel_device_info *info,
> + struct drm_printer *p);
>
> /* modesetting */
> extern void intel_modeset_init_hw(struct drm_device *dev);
> diff --git a/drivers/gpu/drm/i915/i915_gpu_error.c
> b/drivers/gpu/drm/i915/i915_gpu_error.c
> index aba50aa..664f55c 100644
> --- a/drivers/gpu/drm/i915/i915_gpu_error.c
> +++ b/drivers/gpu/drm/i915/i915_gpu_error.c
> @@ -564,9 +564,9 @@ static void print_error_obj(struct
> drm_i915_error_state_buf *m,
> static void err_print_capabilities(struct drm_i915_error_state_buf *m,
>const struct intel_device_info *info)
> {
> -#define PRINT_FLAG(x) err_printf(m, #x ": %s\n", yesno(info->x))
> - DEV_INFO_FOR_EACH_FLAG(PRINT_FLAG);
> -#undef PRINT_FLAG
> + struct drm_printer p = i915_error_printer(m);
> +
> + intel_device_info_dump_flags(info, &p);
> }
>
> static __always_inline void err_print_param(struct drm_i915_error_state_buf
> *m,
> diff --git a/drivers/gpu/drm/i915/intel_device_info.c
> b/drivers/gpu/drm/i915/intel_device_info.c
> index f478be3..5a385a9 100644
> --- a/drivers/gpu/drm/i915/intel_device_info.c
> +++ b/drivers/gpu/drm/i915/intel_device_info.c
> @@ -22,6 +22,8 @@
> *
> */
>
> +#include
> +
> #include "i915_drv.h"
>
> #define PLATFORM_NAME(x) [INTEL_##x] = #x
> @@ -67,6 +69,14 @@ const char *intel_platform_name(enum intel_platform
> platform)
> return platform_names[platform];
> }
>
> +void intel_device_info_dump_flags(const struct intel_device_info *info,
> + struct drm_printer *p)
> +{
> +#define PRINT_FLAG(name) drm_printf(p, "%s: %s\n", #name, yesno(info->name));
> + DEV_INFO_FOR_EACH_FLAG(PRINT_FLAG);
> +#undef PRINT_FLAG
> +}
> +
> void intel_device_info_dump(struct drm_i915_private *dev_priv)
> {
> const struct intel_device_info *info = &dev_priv->info;
> @@ -76,10 +86,12 @@ void intel_device_info_dump(struct drm_i915_private
> *dev_priv)
> info->gen,
> dev_priv->drm.pdev->device,
> dev_priv->drm.pdev->revision);
> -#define PRINT_FLAG(name) \
> - DRM_DEBUG_DRIVER("i915 device info: " #name ": %s", yesno(info->name))
> - DEV_INFO_FOR_EACH_FLAG(PRINT_FLAG);
> -#undef PRINT_FLAG
> +
> + if (drm_debug & DRM_UT_DRIVER) {
> + struct drm_printer
Re: [Intel-gfx] [PATCH 4/5] drm/atomic: document how to handle driver private objects
Hi Alex, On Friday, 15 December 2017 03:57:48 EET Alex Deucher wrote: > On Thu, Dec 14, 2017 at 3:30 PM, Daniel Vetter wrote: > > DK put some nice docs into the commit introducing driver private > > state, but in the git history alone it'll be lost. > > > > Also, since Ville remove the void* usage it's a good opportunity to > > give the driver private stuff some tlc on the doc front. > > > > Finally try to explain why the "let's just subclass drm_atomic_state" > > approach wasn't the greatest, and annotate all those functions as > > deprecated in favour of more standardized driver private states. Also > > note where we could/should extend driver private states going forward > > (atm neither locking nor synchronization is handled in core/helpers, > > which isn't really all that great). > > > > Cc: Harry Wentland > > Cc: Dhinakaran Pandiyan > > Cc: Maarten Lankhorst > > Cc: Ville Syrjälä > > Cc: Laurent Pinchart > > Cc: Rob Clark > > Cc: Alex Deucher > > Cc: Ben Skeggs > > Signed-off-by: Daniel Vetter > > --- > > > > Documentation/gpu/drm-kms.rst | 6 ++ > > drivers/gpu/drm/drm_atomic.c | 45 +++--- > > include/drm/drm_atomic.h | 28 +++ > > include/drm/drm_mode_config.h | 9 + > > 4 files changed, 85 insertions(+), 3 deletions(-) [snip] > > diff --git a/drivers/gpu/drm/drm_atomic.c b/drivers/gpu/drm/drm_atomic.c > > index 37445d50816a..15e1a35c74a8 100644 > > --- a/drivers/gpu/drm/drm_atomic.c > > +++ b/drivers/gpu/drm/drm_atomic.c [snip] > > +/** > > + * DOC: handling driver private state > > + * > > + * Very often the DRM objects exposed to userspace in the atomic modeset > > api + * (&drm_connector, &drm_crtc and &drm_plane) do not map neatly to > > the + * underlying hardware. Especially for any kind of shared resources > > (e.g. shared + * clocks, scaler units, bandwidth and fifo limits shared > > among a group of + * planes or CRTCs, and so on) it makes sense to model > > these as independent + * objects. Drivers then need to similar state > > tracking and commit ordering for + * such private (since not exposed to > > userpace) objects as the atomic core and + * helpers already provide for > > connectors, planes and CRTCs. > > This last sentence doesn't quite parse. I think it should be as follows: > > Drivers then need to do similar state tracking and commit ordering for > such private (since not exposed to userpace) objects as the atomic core that > helpers already provide for DRM objects (connectors, planes and CRTCs). I think Daniel meant "Drivers then need similar state tracking and commit ordering for such private (since not exposed to userpace) objects as the atomic core and helpers already provide for connectors, planes and CRTCs." [snip] -- Regards, Laurent Pinchart ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH 2/2] drm/i915: Add pretty printer for modparams
Quoting Michal Wajdeczko (2017-12-18 15:51:32)
> We dump modparams in few places (debugfs, gpu_error) using different
> functions. Lets add reusable function to avoid code duplication.
>
> add/remove: 1/0 grow/shrink: 0/2 up/down: 1096/-2339 (-1243)
> Function old new delta
> i915_params_dump -1096 +1096
> i915_capabilities 1353 185 -1168
> i915_error_state_to_str 55074336 -1171
> Total: Before=1285716, After=1284473, chg -0.10%
>
> Signed-off-by: Michal Wajdeczko
> Cc: Chris Wilson
> ---
> drivers/gpu/drm/i915/i915_debugfs.c | 21 +
> drivers/gpu/drm/i915/i915_gpu_error.c | 25 -
> drivers/gpu/drm/i915/i915_params.c| 31 +++
> drivers/gpu/drm/i915/i915_params.h| 3 +++
> 4 files changed, 39 insertions(+), 41 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_debugfs.c
> b/drivers/gpu/drm/i915/i915_debugfs.c
> index e384e28..c4780f0 100644
> --- a/drivers/gpu/drm/i915/i915_debugfs.c
> +++ b/drivers/gpu/drm/i915/i915_debugfs.c
> @@ -37,23 +37,6 @@ static inline struct drm_i915_private *node_to_i915(struct
> drm_info_node *node)
> return to_i915(node->minor->dev);
> }
>
> -static __always_inline void seq_print_param(struct seq_file *m,
> - const char *name,
> - const char *type,
> - const void *x)
> -{
> - if (!__builtin_strcmp(type, "bool"))
> - seq_printf(m, "i915.%s=%s\n", name, yesno(*(const bool *)x));
> - else if (!__builtin_strcmp(type, "int"))
> - seq_printf(m, "i915.%s=%d\n", name, *(const int *)x);
> - else if (!__builtin_strcmp(type, "unsigned int"))
> - seq_printf(m, "i915.%s=%u\n", name, *(const unsigned int *)x);
> - else if (!__builtin_strcmp(type, "char *"))
> - seq_printf(m, "i915.%s=%s\n", name, *(const char **)x);
> - else
> - BUILD_BUG();
> -}
> -
> static int i915_capabilities(struct seq_file *m, void *data)
> {
> struct drm_i915_private *dev_priv = node_to_i915(m->private);
> @@ -67,9 +50,7 @@ static int i915_capabilities(struct seq_file *m, void *data)
> intel_device_info_dump_flags(info, &p);
>
> kernel_param_lock(THIS_MODULE);
> -#define PRINT_PARAM(T, x, ...) seq_print_param(m, #x, #T, &i915_modparams.x);
> - I915_PARAMS_FOR_EACH(PRINT_PARAM);
> -#undef PRINT_PARAM
> + i915_params_dump(&i915_modparams, &p);
> kernel_param_unlock(THIS_MODULE);
>
> return 0;
> diff --git a/drivers/gpu/drm/i915/i915_gpu_error.c
> b/drivers/gpu/drm/i915/i915_gpu_error.c
> index 664f55c..84831e9 100644
> --- a/drivers/gpu/drm/i915/i915_gpu_error.c
> +++ b/drivers/gpu/drm/i915/i915_gpu_error.c
> @@ -569,29 +569,12 @@ static void err_print_capabilities(struct
> drm_i915_error_state_buf *m,
> intel_device_info_dump_flags(info, &p);
> }
>
> -static __always_inline void err_print_param(struct drm_i915_error_state_buf
> *m,
> - const char *name,
> - const char *type,
> - const void *x)
> -{
> - if (!__builtin_strcmp(type, "bool"))
> - err_printf(m, "i915.%s=%s\n", name, yesno(*(const bool *)x));
> - else if (!__builtin_strcmp(type, "int"))
> - err_printf(m, "i915.%s=%d\n", name, *(const int *)x);
> - else if (!__builtin_strcmp(type, "unsigned int"))
> - err_printf(m, "i915.%s=%u\n", name, *(const unsigned int *)x);
> - else if (!__builtin_strcmp(type, "char *"))
> - err_printf(m, "i915.%s=%s\n", name, *(const char **)x);
> - else
> - BUILD_BUG();
> -}
> -
> static void err_print_params(struct drm_i915_error_state_buf *m,
> -const struct i915_params *p)
> +const struct i915_params *params)
> {
> -#define PRINT(T, x, ...) err_print_param(m, #x, #T, &p->x);
> - I915_PARAMS_FOR_EACH(PRINT);
> -#undef PRINT
> + struct drm_printer p = i915_error_printer(m);
> +
> + i915_params_dump(params, &p);
> }
>
> static void err_print_pciid(struct drm_i915_error_state_buf *m,
> diff --git a/drivers/gpu/drm/i915/i915_params.c
> b/drivers/gpu/drm/i915/i915_params.c
> index 8dfea03..d8d7189 100644
> --- a/drivers/gpu/drm/i915/i915_params.c
> +++ b/drivers/gpu/drm/i915/i915_params.c
> @@ -172,3 +172,34 @@ struct i915_params i915_modparams __read_mostly = {
>
> i915_param_named(enable_gvt, bool, 0400,
> "Enable support for Intel GVT-g graphics virtualization host
> support(default:false)");
> +
> +static __always_inline void _print_param(struct drm_printer *p,
> +
Re: [Intel-gfx] [PATCH 4/5] drm/atomic: document how to handle driver private objects
Hi Daniel,
Thank you for the patch.
On Thursday, 14 December 2017 22:30:53 EET Daniel Vetter wrote:
> DK put some nice docs into the commit introducing driver private
> state, but in the git history alone it'll be lost.
You might want to spell DK's name fully.
> Also, since Ville remove the void* usage it's a good opportunity to
> give the driver private stuff some tlc on the doc front.
>
> Finally try to explain why the "let's just subclass drm_atomic_state"
> approach wasn't the greatest, and annotate all those functions as
> deprecated in favour of more standardized driver private states. Also
> note where we could/should extend driver private states going forward
> (atm neither locking nor synchronization is handled in core/helpers,
> which isn't really all that great).
>
> Cc: Harry Wentland
> Cc: Dhinakaran Pandiyan
> Cc: Maarten Lankhorst
> Cc: Ville Syrjälä
> Cc: Laurent Pinchart
> Cc: Rob Clark
> Cc: Alex Deucher
> Cc: Ben Skeggs
> Signed-off-by: Daniel Vetter
> ---
> Documentation/gpu/drm-kms.rst | 6 ++
> drivers/gpu/drm/drm_atomic.c | 45 +---
> include/drm/drm_atomic.h | 28 +++
> include/drm/drm_mode_config.h | 9 +
> 4 files changed, 85 insertions(+), 3 deletions(-)
>
> diff --git a/Documentation/gpu/drm-kms.rst b/Documentation/gpu/drm-kms.rst
> index 307284125d7a..420025bd6a9b 100644
> --- a/Documentation/gpu/drm-kms.rst
> +++ b/Documentation/gpu/drm-kms.rst
> @@ -271,6 +271,12 @@ Taken all together there's two consequences for the
> atomic design: Read on in this chapter, and also in
> :ref:`drm_atomic_helper` for more detailed coverage of specific topics.
>
> +Handling Driver Private State
> +-
> +
> +.. kernel-doc:: drivers/gpu/drm/drm_atomic.c
> + :doc: handling driver private state
> +
> Atomic Mode Setting Function Reference
> --
>
> diff --git a/drivers/gpu/drm/drm_atomic.c b/drivers/gpu/drm/drm_atomic.c
> index 37445d50816a..15e1a35c74a8 100644
> --- a/drivers/gpu/drm/drm_atomic.c
> +++ b/drivers/gpu/drm/drm_atomic.c
> @@ -50,7 +50,8 @@ EXPORT_SYMBOL(__drm_crtc_commit_free);
> * @state: atomic state
> *
> * Free all the memory allocated by drm_atomic_state_init.
> - * This is useful for drivers that subclass the atomic state.
> + * This should only be used by drivers which are still subclassing
> + * &drm_atomic_state and haven't switched to &drm_private_state yet.
> */
> void drm_atomic_state_default_release(struct drm_atomic_state *state)
> {
> @@ -67,7 +68,8 @@ EXPORT_SYMBOL(drm_atomic_state_default_release);
> * @state: atomic state
> *
> * Default implementation for filling in a new atomic state.
> - * This is useful for drivers that subclass the atomic state.
> + * This should only be used by drivers which are still subclassing
> + * &drm_atomic_state and haven't switched to &drm_private_state yet.
> */
> int
> drm_atomic_state_init(struct drm_device *dev, struct drm_atomic_state
> *state)
> @@ -132,7 +134,8 @@ EXPORT_SYMBOL(drm_atomic_state_alloc);
> * @state: atomic state
> *
> * Default implementation for clearing atomic state.
> - * This is useful for drivers that subclass the atomic state.
> + * This should only be used by drivers which are still subclassing
> + * &drm_atomic_state and haven't switched to &drm_private_state yet.
> */
> void drm_atomic_state_default_clear(struct drm_atomic_state *state)
> {
> @@ -946,6 +949,42 @@ static void drm_atomic_plane_print_state(struct
> drm_printer *p, plane->funcs->atomic_print_state(p, state);
> }
>
> +/**
> + * DOC: handling driver private state
> + *
> + * Very often the DRM objects exposed to userspace in the atomic modeset
> api
s/api/API/
> + * (&drm_connector, &drm_crtc and &drm_plane) do not map neatly to the
> + * underlying hardware. Especially for any kind of shared resources (e.g.
> shared
> + * clocks, scaler units, bandwidth and fifo limits shared among a group of
> + * planes or CRTCs, and so on) it makes sense to model these as independent
> + * objects. Drivers then need to similar state tracking and commit ordering
> for
> + * such private (since not exposed to userpace) objects as the atomic core
> and
> + * helpers already provide for connectors, planes and CRTCs.
>
> + * To make this easier on drivers the atomic core provides some support to
> track
> + * driver private state objects using struct &drm_private_obj, with the
> + * associated state struct &drm_private_state.
> + *
> + * Similar to userspace-exposed objects, state structures can be acquired
> by
> + * calling drm_atomic_get_private_obj_state(). Since this function does not
> take
> + * care of locking, drivers should wrap it for each type of private state
> object
> + * they have with the required call to drm_modeset_lock() for the
> corresponding
> + * &drm_modeset_lock.
This paragraph could benefit from an explanation of what the corresponding
Re: [Intel-gfx] [PATCH v2 2/2] drm/i915/trace: add hw_id to gem requests trace points
On 18/12/17 15:22, Chris Wilson wrote: Quoting Lionel Landwerlin (2017-12-18 15:19:59) When monitoring the GPU with i915 perf, reports are tagged with a hw id. Gem context creation tracepoints already have a hw_id field, unfortunately you only get this correlation between a process id and a hw context id once when the context is created. It doesn't help if you started monitoring after the process was initialized or if the drm fd was transfered from one process to another. This change adds the hw_id field to gem requests, so that correlation can also be done on submission. v2: Place hw_id at the end of the tracepoint to not disrupt too much existing tools (Chris) v3: Reorder hw_id field again (Chris) v4: Add missing hw_id to i915_gem_request_wait_begin tracepoint (Chris) Signed-off-by: Lionel Landwerlin Reviewed-by: Chris Wilson -Chris Thanks a bunch, both patches are pushed to dinq. ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✓ Fi.CI.BAT: success for series starting with [1/2] drm/i915: Add pretty printer for device info flags
== Series Details == Series: series starting with [1/2] drm/i915: Add pretty printer for device info flags URL : https://patchwork.freedesktop.org/series/35521/ State : success == Summary == Series 35521v1 series starting with [1/2] drm/i915: Add pretty printer for device info flags https://patchwork.freedesktop.org/api/1.0/series/35521/revisions/1/mbox/ Test kms_busy: Subgroup basic-flip-a: pass -> DMESG-WARN (fi-elk-e7500) fdo#103989 Test kms_flip: Subgroup basic-flip-vs-wf_vblank: pass -> FAIL (fi-hsw-4770r) fdo#100368 Test kms_pipe_crc_basic: Subgroup suspend-read-crc-pipe-a: dmesg-warn -> PASS (fi-kbl-r) fdo#104172 +1 Subgroup suspend-read-crc-pipe-c: incomplete -> PASS (fi-bdw-5557u) fdo#104162 fdo#103989 https://bugs.freedesktop.org/show_bug.cgi?id=103989 fdo#100368 https://bugs.freedesktop.org/show_bug.cgi?id=100368 fdo#104172 https://bugs.freedesktop.org/show_bug.cgi?id=104172 fdo#104162 https://bugs.freedesktop.org/show_bug.cgi?id=104162 fi-bdw-5557u total:288 pass:267 dwarn:0 dfail:0 fail:0 skip:21 time:431s fi-bdw-gvtdvmtotal:288 pass:264 dwarn:0 dfail:0 fail:0 skip:24 time:438s fi-blb-e6850 total:288 pass:223 dwarn:1 dfail:0 fail:0 skip:64 time:382s fi-bsw-n3050 total:288 pass:242 dwarn:0 dfail:0 fail:0 skip:46 time:490s fi-bwr-2160 total:288 pass:183 dwarn:0 dfail:0 fail:0 skip:105 time:275s fi-bxt-dsi total:288 pass:258 dwarn:0 dfail:0 fail:0 skip:30 time:492s fi-bxt-j4205 total:288 pass:259 dwarn:0 dfail:0 fail:0 skip:29 time:494s fi-byt-j1900 total:288 pass:253 dwarn:0 dfail:0 fail:0 skip:35 time:480s fi-byt-n2820 total:288 pass:249 dwarn:0 dfail:0 fail:0 skip:39 time:468s fi-elk-e7500 total:224 pass:163 dwarn:15 dfail:0 fail:0 skip:45 fi-gdg-551 total:288 pass:178 dwarn:1 dfail:0 fail:1 skip:108 time:262s fi-glk-1 total:288 pass:260 dwarn:0 dfail:0 fail:0 skip:28 time:529s fi-hsw-4770 total:288 pass:261 dwarn:0 dfail:0 fail:0 skip:27 time:402s fi-hsw-4770r total:288 pass:260 dwarn:0 dfail:0 fail:1 skip:27 time:402s fi-ilk-650 total:288 pass:228 dwarn:0 dfail:0 fail:0 skip:60 time:393s fi-ivb-3520m total:288 pass:259 dwarn:0 dfail:0 fail:0 skip:29 time:477s fi-ivb-3770 total:288 pass:255 dwarn:0 dfail:0 fail:0 skip:33 time:424s fi-kbl-7500u total:288 pass:263 dwarn:1 dfail:0 fail:0 skip:24 time:479s fi-kbl-7560u total:288 pass:268 dwarn:1 dfail:0 fail:0 skip:19 time:516s fi-kbl-7567u total:288 pass:268 dwarn:0 dfail:0 fail:0 skip:20 time:466s fi-kbl-r total:288 pass:260 dwarn:1 dfail:0 fail:0 skip:27 time:521s fi-pnv-d510 total:288 pass:222 dwarn:1 dfail:0 fail:0 skip:65 time:588s fi-skl-6260u total:288 pass:268 dwarn:0 dfail:0 fail:0 skip:20 time:450s fi-skl-6600u total:288 pass:260 dwarn:1 dfail:0 fail:0 skip:27 time:534s fi-skl-6700hqtotal:288 pass:262 dwarn:0 dfail:0 fail:0 skip:26 time:556s fi-skl-6700k2total:288 pass:264 dwarn:0 dfail:0 fail:0 skip:24 time:507s fi-skl-6770hqtotal:288 pass:268 dwarn:0 dfail:0 fail:0 skip:20 time:503s fi-skl-gvtdvmtotal:288 pass:265 dwarn:0 dfail:0 fail:0 skip:23 time:445s fi-snb-2520m total:288 pass:248 dwarn:0 dfail:0 fail:0 skip:40 time:556s fi-snb-2600 total:288 pass:248 dwarn:0 dfail:0 fail:0 skip:40 time:408s Blacklisted hosts: fi-cfl-s2total:288 pass:262 dwarn:0 dfail:0 fail:0 skip:26 time:598s fi-cnl-y total:288 pass:262 dwarn:0 dfail:0 fail:0 skip:26 time:612s fi-glk-dsi total:288 pass:181 dwarn:1 dfail:4 fail:2 skip:100 time:385s 913d6a0d4d78fba4cb62a1ac14d539d959fe422a drm-tip: 2017y-12m-18d-13h-25m-28s UTC integration manifest c58426754088 drm/i915: Add pretty printer for modparams 9ae562ebfe10 drm/i915: Add pretty printer for device info flags == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_7528/issues.html ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✗ Fi.CI.BAT: failure for tests: add i915 query tests
== Series Details == Series: tests: add i915 query tests URL : https://patchwork.freedesktop.org/series/35520/ State : failure == Summary == IGT patchset build failed on latest successful build c0be3310715e2f744b892c51f09e62273bcc8e57 tests/kms_frontbuffer_tracking: Correctly handle debugfs errors struct drm_i915_query_item item; ^~~~ query.c:190:18: error: ‘DRM_I915_QUERY_ID_EUS_MASK’ undeclared (first use in this function) item.query_id = DRM_I915_QUERY_ID_EUS_MASK; ^~ In file included from ./../lib/intel_batchbuffer.h:8:0, from ./../lib/drmtest.h:39, from ./../lib/igt.h:27, from query.c:24: query.c:191:15: error: ‘DRM_IOCTL_I915_QUERY’ undeclared (first use in this function) do_ioctl(fd, DRM_IOCTL_I915_QUERY, &query); ^ ./../lib/igt_core.h:396:15: note: in definition of macro ‘igt_assert_cmpint’ int __n1 = (n1), __n2 = (n2); \ ^~ ./../lib/drmtest.h:103:2: note: in expansion of macro ‘igt_assert_eq’ igt_assert_eq(igt_ioctl((fd), (ioc), (ioc_data)), 0); \ ^ query.c:191:2: note: in expansion of macro ‘do_ioctl’ do_ioctl(fd, DRM_IOCTL_I915_QUERY, &query); ^~~~ query.c:199:13: error: dereferencing pointer to incomplete type ‘struct drm_i915_query_eus_mask’ eus_mask->n_slices, eus_mask->slice_stride, eus_mask->subslice_stride); ^ ./../lib/igt_core.h:795:64: note: in definition of macro ‘igt_debug’ #define igt_debug(f...) igt_log(IGT_LOG_DOMAIN, IGT_LOG_DEBUG, f) ^ query.c:176:29: warning: unused variable ‘item’ [-Wunused-variable] struct drm_i915_query_item item; ^~~~ query.c:175:24: warning: unused variable ‘query’ [-Wunused-variable] struct drm_i915_query query; ^ query.c: In function ‘has_query_supports’: query.c:33:1: error: control reaches end of non-void function [-Werror=return-type] } ^ query.c: In function ‘query_topology_supported’: query.c:86:1: error: control reaches end of non-void function [-Werror=return-type] } ^ cc1: some warnings being treated as errors Makefile:3922: recipe for target 'query.o' failed make[3]: *** [query.o] Error 1 Makefile:4323: recipe for target 'all-recursive' failed make[2]: *** [all-recursive] Error 1 Makefile:531: recipe for target 'all-recursive' failed make[1]: *** [all-recursive] Error 1 Makefile:463: recipe for target 'all' failed make: *** [all] Error 2 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] ✗ Fi.CI.BAT: failure for tests: add i915 query tests
Oops, forgot to send the patch dumping the i915 headers :( On 18/12/17 16:49, Patchwork wrote: == Series Details == Series: tests: add i915 query tests URL : https://patchwork.freedesktop.org/series/35520/ State : failure == Summary == IGT patchset build failed on latest successful build c0be3310715e2f744b892c51f09e62273bcc8e57 tests/kms_frontbuffer_tracking: Correctly handle debugfs errors struct drm_i915_query_item item; ^~~~ query.c:190:18: error: ‘DRM_I915_QUERY_ID_EUS_MASK’ undeclared (first use in this function) item.query_id = DRM_I915_QUERY_ID_EUS_MASK; ^~ In file included from ./../lib/intel_batchbuffer.h:8:0, from ./../lib/drmtest.h:39, from ./../lib/igt.h:27, from query.c:24: query.c:191:15: error: ‘DRM_IOCTL_I915_QUERY’ undeclared (first use in this function) do_ioctl(fd, DRM_IOCTL_I915_QUERY, &query); ^ ./../lib/igt_core.h:396:15: note: in definition of macro ‘igt_assert_cmpint’ int __n1 = (n1), __n2 = (n2); \ ^~ ./../lib/drmtest.h:103:2: note: in expansion of macro ‘igt_assert_eq’ igt_assert_eq(igt_ioctl((fd), (ioc), (ioc_data)), 0); \ ^ query.c:191:2: note: in expansion of macro ‘do_ioctl’ do_ioctl(fd, DRM_IOCTL_I915_QUERY, &query); ^~~~ query.c:199:13: error: dereferencing pointer to incomplete type ‘struct drm_i915_query_eus_mask’ eus_mask->n_slices, eus_mask->slice_stride, eus_mask->subslice_stride); ^ ./../lib/igt_core.h:795:64: note: in definition of macro ‘igt_debug’ #define igt_debug(f...) igt_log(IGT_LOG_DOMAIN, IGT_LOG_DEBUG, f) ^ query.c:176:29: warning: unused variable ‘item’ [-Wunused-variable] struct drm_i915_query_item item; ^~~~ query.c:175:24: warning: unused variable ‘query’ [-Wunused-variable] struct drm_i915_query query; ^ query.c: In function ‘has_query_supports’: query.c:33:1: error: control reaches end of non-void function [-Werror=return-type] } ^ query.c: In function ‘query_topology_supported’: query.c:86:1: error: control reaches end of non-void function [-Werror=return-type] } ^ cc1: some warnings being treated as errors Makefile:3922: recipe for target 'query.o' failed make[3]: *** [query.o] Error 1 Makefile:4323: recipe for target 'all-recursive' failed make[2]: *** [all-recursive] Error 1 Makefile:531: recipe for target 'all-recursive' failed make[1]: *** [all-recursive] Error 1 Makefile:463: recipe for target 'all' failed make: *** [all] Error 2 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✗ Fi.CI.IGT: failure for drm/i915: improve tracepoints for process/hw_id tracking (rev2)
== Series Details == Series: drm/i915: improve tracepoints for process/hw_id tracking (rev2) URL : https://patchwork.freedesktop.org/series/35506/ State : failure == Summary == Test kms_pipe_crc_basic: Subgroup suspend-read-crc-pipe-a: pass -> SKIP (shard-snb) fdo#103375 +1 Test kms_flip: Subgroup flip-vs-panning-interruptible: pass -> INCOMPLETE (shard-snb) Test drv_suspend: Subgroup debugfs-reader: pass -> SKIP (shard-hsw) Test kms_setmode: Subgroup basic: pass -> FAIL (shard-hsw) fdo#99912 Test perf: Subgroup blocking: fail -> PASS (shard-hsw) fdo#102252 Test kms_frontbuffer_tracking: Subgroup fbc-1p-offscren-pri-shrfb-draw-render: fail -> PASS (shard-snb) fdo#101623 fdo#103375 https://bugs.freedesktop.org/show_bug.cgi?id=103375 fdo#99912 https://bugs.freedesktop.org/show_bug.cgi?id=99912 fdo#102252 https://bugs.freedesktop.org/show_bug.cgi?id=102252 fdo#101623 https://bugs.freedesktop.org/show_bug.cgi?id=101623 shard-hswtotal:2712 pass:1535 dwarn:1 dfail:0 fail:10 skip:1166 time:9330s shard-snbtotal:2675 pass:1277 dwarn:1 dfail:0 fail:12 skip:1383 time:7665s Blacklisted hosts: shard-apltotal:2636 pass:1640 dwarn:1 dfail:1 fail:23 skip:971 time:13215s shard-kbltotal:2331 pass:1555 dwarn:1 dfail:1 fail:21 skip:753 time:9311s == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_7526/shards.html ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH i-g-t] scripts/trace.pl: Remove some old code
From: Tvrtko Ursulin
Remove some inactive code which was only uised to support the old execlists
implementation. It is hidden behind a toggle which is not user accesible
anyway.
Signed-off-by: Tvrtko Ursulin
Cc: John Harrison
---
scripts/trace.pl | 31 ---
1 file changed, 31 deletions(-)
diff --git a/scripts/trace.pl b/scripts/trace.pl
index 9b3fb6486fec..588126ad46ab 100755
--- a/scripts/trace.pl
+++ b/scripts/trace.pl
@@ -354,8 +354,6 @@ sub ts
# trace using a hash of requests and some auxilliary data structures.
my $prev_freq = 0;
my $prev_freq_ts = 0;
-my $oldkernelwa = 0;
-my ($no_queue, $no_in);
while (<>) {
my @fields;
my @tmp;
@@ -440,10 +438,6 @@ while (<>) {
$key = db_key($tp{'ring'}, $tp{'ctx'}, $tp{'seqno'});
die if exists $db{$key};
- if (not exists $queue{$key} and $oldkernelwa) {
- $no_queue++;
- next;
- }
die unless exists $queue{$key};
die unless exists $submit{$key};
@@ -467,10 +461,6 @@ while (<>) {
$tp{'ctx'} = sanitize_ctx($tp{'ctx'}, $tp{'ring'});
$key = db_key($tp{'ring'}, $tp{'ctx'}, $tp{'seqno'});
- if (not exists $db{$key} and $oldkernelwa) {
- $no_in++;
- next;
- }
die unless exists $db{$key};
die unless exists $db{$key}->{'start'};
die if exists $db{$key}->{'end'};
@@ -574,27 +564,6 @@ foreach my $key (sort {$db{$a}->{'start'} <=>
$db{$b}->{'start'}} keys %db) {
$first_ts = $db{$key}->{'queue'} if not defined $first_ts or
$db{$key}->{'queue'} < $first_ts;
$last_ts = $end if $end > $last_ts;
- # Adjust batch start with legacy execlists.
- # Port == 2 mean batch was merged udring queuing and hasn't actually
- # been submitted to the gpu until the batch with port < 2 is found.
- if ($correct_durations and $oldkernelwa and $db{$key}->{'port'} == 2) {
- my $ctx = $db{$key}->{'ctx'};
- my $seqno = $db{$key}->{'seqno'};
- my $next_key;
- my $i = 1;
-
- do {
- $next_key = db_key($ring, $ctx, $seqno + $i);
- $i++;
- } until ((exists $db{$next_key} and $db{$next_key}->{'port'} <
2) or $i > scalar(keys(%db))); # ugly stop hack
-
- if (exists $db{$next_key}) {
- $db{$key}->{'start'} = $db{$next_key}->{'start'};
- $db{$key}->{'end'} = $db{$next_key}->{'end'};
- die if $db{$key}->{'start'} > $db{$key}->{'end'};
- }
- }
-
$running{$ring} += $end - $db{$key}->{'start'} unless exists
$db{$key}->{'no-end'};
$runnable{$ring} += $db{$key}->{'execute-delay'};
$queued{$ring} += $db{$key}->{'start'} - $db{$key}->{'execute-delay'} -
$db{$key}->{'queue'};
--
2.14.1
___
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[Intel-gfx] ✓ Fi.CI.IGT: success for series starting with [1/2] drm/i915: Add pretty printer for device info flags
== Series Details == Series: series starting with [1/2] drm/i915: Add pretty printer for device info flags URL : https://patchwork.freedesktop.org/series/35521/ State : success == Summary == Test drv_selftest: Subgroup live_hangcheck: incomplete -> PASS (shard-snb) fdo#104313 Test kms_frontbuffer_tracking: Subgroup fbc-1p-offscren-pri-shrfb-draw-render: fail -> PASS (shard-snb) fdo#101623 Test perf: Subgroup blocking: fail -> PASS (shard-hsw) fdo#102252 Test kms_plane: Subgroup plane-panning-bottom-right-suspend-pipe-c-planes: pass -> SKIP (shard-hsw) fdo#103375 Test kms_setmode: Subgroup basic: pass -> FAIL (shard-hsw) fdo#99912 fdo#104313 https://bugs.freedesktop.org/show_bug.cgi?id=104313 fdo#101623 https://bugs.freedesktop.org/show_bug.cgi?id=101623 fdo#102252 https://bugs.freedesktop.org/show_bug.cgi?id=102252 fdo#103375 https://bugs.freedesktop.org/show_bug.cgi?id=103375 fdo#99912 https://bugs.freedesktop.org/show_bug.cgi?id=99912 shard-hswtotal:2712 pass:1536 dwarn:1 dfail:0 fail:10 skip:1165 time:9375s shard-snbtotal:2712 pass:1308 dwarn:1 dfail:0 fail:12 skip:1391 time:7973s Blacklisted hosts: shard-apltotal:2693 pass:1669 dwarn:1 dfail:1 fail:24 skip:997 time:13477s shard-kbltotal:2712 pass:1791 dwarn:12 dfail:6 fail:23 skip:880 time:11178s == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_7528/shards.html ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] 995d11c4c0 ("drm: rework delayed connector cleanup in .."): WARNING: possible circular locking dependency detected
Op 18-12-17 om 08:08 schreef Daniel Vetter:
> Hm, the bisect looks funny. Only way I can explain that is that my
> patch fixed a pre-existing lockdep splat, and uncovered the issue in
> the ww-mutex self tests. That one is uncovered by the new
> cross-release lockdep checks in 4.15.
>
> Anyway I think this is an issue with the ww-mutex tests, not my patch
> (none of the code I touched is anywhere in the backtraces), adding
> relevant people.
> -Daniel
>
>
> On Sat, Dec 16, 2017 at 11:42 AM, kernel test robot
> wrote:
>> Greetings,
>>
>> 0day kernel testing robot got the below dmesg and the first bad commit is
>>
>> https://github.com/0day-ci/linux/commits/Daniel-Vetter/drm-rework-delayed-connector-cleanup-in-connector_iter/20171216-120456
>>
>> commit 995d11c4c0f1aa99d0f97fb747a4e0d04121cde2
>> Author: Daniel Vetter
>> AuthorDate: Wed Dec 13 11:45:53 2017 +0100
>> Commit: 0day robot
>> CommitDate: Sat Dec 16 12:04:58 2017 +0800
>>
>> drm: rework delayed connector cleanup in connector_iter
>>
>> PROBE_DEFER also uses system_wq to reprobe drivers, which means when
>> that again fails, and we try to flush the overall system_wq (to get
>> all the delayed connectore cleanup work_struct completed), we
>> deadlock.
>>
>> Fix this by using just a single cleanup work, so that we can only
>> flush that one and don't block on anything else. That means a free
>> list plus locking, a standard pattern.
>>
>> Fixes: a703c55004e1 ("drm: safely free connectors from connector_iter")
>> Fixes: 613051dac40d ("drm: locking&new iterators for connector_list")
>> Cc: Ben Widawsky
>> Cc: Dave Airlie
>> Cc: Chris Wilson
>> Cc: Sean Paul
>> Cc: # v4.11+: 613051dac40d ("drm: locking&new
>> iterators for connector_list"
>> Cc: # v4.11+
>> Cc: Daniel Vetter
>> Cc: Jani Nikula
>> Cc: Gustavo Padovan
>> Cc: David Airlie
>> Cc: Javier Martinez Canillas
>> Cc: Shuah Khan
>> Cc: Guillaume Tucker
>> Cc: Mark Brown
>> Cc: Kevin Hilman
>> Cc: Matt Hart
>> Cc: Thierry Escande
>> Cc: Tomeu Vizoso
>> Cc: Enric Balletbo i Serra
>> Signed-off-by: Daniel Vetter
>>
>> 50c4c4e268 Linux 4.15-rc3
>> 995d11c4c0 drm: rework delayed connector cleanup in connector_iter
>> +---+---++
>> | | v4.15-rc3 |
>> 995d11c4c0 |
>> +---+---++
>> | boot_successes| 1 | 0
>> |
>> | boot_failures | 82| 15
>> |
>> | WARNING:possible_circular_locking_dependency_detected | 82| 15
>> |
>> | kernel_BUG_at_lib/list_debug.c| 0 | 15
>> |
>> | invalid_opcode:#[##] | 0 | 15
>> |
>> | RIP:__list_add_valid | 0 | 15
>> |
>> | Kernel_panic-not_syncing:Fatal_exception | 0 | 15
>> |
>> +---+---++
>>
>> [3.252870] CPU feature 'AVX registers' is not supported.
>> [3.261404] AVX2 or AES-NI instructions are not detected.
>> [3.262708] AVX2 instructions are not detected.
>> [3.770347]
>> [3.773471] ==
>> [3.773471] WARNING: possible circular locking dependency detected
>> [3.773471] 4.15.0-rc3-1-g995d11c #1 Not tainted
>> [3.773471] --
>> [3.773471] swapper/0/1 is trying to acquire lock:
>> [3.773471] (ww_class_mutex){+.+.}, at: [<134bc923>]
>> test_abba+0x120/0x21e
>> [3.773471]
>> [3.773471] but now in release context of a crosslock acquired at the
>> following:
>> [3.773471] ((completion)&abba.a_ready){+.+.}, at: []
>> test_abba_work+0x43/0xab
>> [3.773471]
>> [3.773471] which lock already depends on the new lock.
>> [3.773471]
>> [3.773471] the existing dependency chain (in reverse order) is:
>> [3.773471]
>> [3.773471] -> #1 ((completion)&abba.a_ready){+.+.}:
>> [3.773471]__wait_for_common+0x55/0x1fe
>> [3.773471]test_abba_work+0x43/0xab
>> [3.773471]process_one_work+0x1d4/0x310
>> [3.773471]worker_thread+0x1aa/0x25d
>> [3.773471]kthread+0x120/0x128
>> [3.773471]ret_from_fork+0x24/0x30
>> [3.773471]
>> [3.773471] -> #0 (ww_class_mutex){+.+.}:
>> [3.773471]test_abba+0x120/0x21e
>> [3.773471]test_ww_mutex_init+0x88/0x2fd
>> [3.773471]do_one_initcall+0x94/0x149
>> [3.773471]kernel_init_freeable+0x12a/0x1a6
>> [3.773471]kernel_ini
Re: [Intel-gfx] [PATCH 1/2] drm/i915: Add pretty printer for device info flags
On Mon, 18 Dec 2017, Chris Wilson wrote:
> Quoting Michal Wajdeczko (2017-12-18 15:51:31)
>> We dump device flags in few places (init_early, debugfs, gpu_error)
>> using different functions. Lets add reusable function to avoid
>> code duplication.
>>
>> add/remove: 1/0 grow/shrink: 0/3 up/down: 1296/-3572 (-2276)
>> Function old new delta
>> intel_device_info_dump_flags -1296 +1296
>> i915_capabilities 24351353 -1082
>> i915_error_state_to_str 66425507 -1135
>> intel_device_info_dump 1507 152 -1355
>> Total: Before=1287992, After=1285716, chg -0.18%
>>
>> Signed-off-by: Michal Wajdeczko
>> Cc: Chris Wilson
>> ---
>> drivers/gpu/drm/i915/i915_debugfs.c | 5 ++---
>> drivers/gpu/drm/i915/i915_drv.h | 2 ++
>> drivers/gpu/drm/i915/i915_gpu_error.c| 6 +++---
>> drivers/gpu/drm/i915/intel_device_info.c | 20
>> 4 files changed, 23 insertions(+), 10 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/i915/i915_debugfs.c
>> b/drivers/gpu/drm/i915/i915_debugfs.c
>> index 0ddce72..e384e28 100644
>> --- a/drivers/gpu/drm/i915/i915_debugfs.c
>> +++ b/drivers/gpu/drm/i915/i915_debugfs.c
>> @@ -58,14 +58,13 @@ static int i915_capabilities(struct seq_file *m, void
>> *data)
>> {
>> struct drm_i915_private *dev_priv = node_to_i915(m->private);
>> const struct intel_device_info *info = INTEL_INFO(dev_priv);
>> + struct drm_printer p = drm_seq_file_printer(m);
>>
>> seq_printf(m, "gen: %d\n", INTEL_GEN(dev_priv));
>> seq_printf(m, "platform: %s\n", intel_platform_name(info->platform));
>> seq_printf(m, "pch: %d\n", INTEL_PCH_TYPE(dev_priv));
>>
>> -#define PRINT_FLAG(x) seq_printf(m, #x ": %s\n", yesno(info->x))
>> - DEV_INFO_FOR_EACH_FLAG(PRINT_FLAG);
>> -#undef PRINT_FLAG
>> + intel_device_info_dump_flags(info, &p);
>>
>> kernel_param_lock(THIS_MODULE);
>> #define PRINT_PARAM(T, x, ...) seq_print_param(m, #x, #T,
>> &i915_modparams.x);
>> diff --git a/drivers/gpu/drm/i915/i915_drv.h
>> b/drivers/gpu/drm/i915/i915_drv.h
>> index 1aba565..26ebc70 100644
>> --- a/drivers/gpu/drm/i915/i915_drv.h
>> +++ b/drivers/gpu/drm/i915/i915_drv.h
>> @@ -4165,6 +4165,8 @@ static inline int intel_opregion_get_panel_type(struct
>> drm_i915_private *dev)
>> const char *intel_platform_name(enum intel_platform platform);
>> void intel_device_info_runtime_init(struct drm_i915_private *dev_priv);
>> void intel_device_info_dump(struct drm_i915_private *dev_priv);
>> +void intel_device_info_dump_flags(const struct intel_device_info *info,
>> + struct drm_printer *p);
>>
>> /* modesetting */
>> extern void intel_modeset_init_hw(struct drm_device *dev);
>> diff --git a/drivers/gpu/drm/i915/i915_gpu_error.c
>> b/drivers/gpu/drm/i915/i915_gpu_error.c
>> index aba50aa..664f55c 100644
>> --- a/drivers/gpu/drm/i915/i915_gpu_error.c
>> +++ b/drivers/gpu/drm/i915/i915_gpu_error.c
>> @@ -564,9 +564,9 @@ static void print_error_obj(struct
>> drm_i915_error_state_buf *m,
>> static void err_print_capabilities(struct drm_i915_error_state_buf *m,
>>const struct intel_device_info *info)
>> {
>> -#define PRINT_FLAG(x) err_printf(m, #x ": %s\n", yesno(info->x))
>> - DEV_INFO_FOR_EACH_FLAG(PRINT_FLAG);
>> -#undef PRINT_FLAG
>> + struct drm_printer p = i915_error_printer(m);
>> +
>> + intel_device_info_dump_flags(info, &p);
>> }
>>
>> static __always_inline void err_print_param(struct drm_i915_error_state_buf
>> *m,
>> diff --git a/drivers/gpu/drm/i915/intel_device_info.c
>> b/drivers/gpu/drm/i915/intel_device_info.c
>> index f478be3..5a385a9 100644
>> --- a/drivers/gpu/drm/i915/intel_device_info.c
>> +++ b/drivers/gpu/drm/i915/intel_device_info.c
>> @@ -22,6 +22,8 @@
>> *
>> */
>>
>> +#include
>> +
>> #include "i915_drv.h"
>>
>> #define PLATFORM_NAME(x) [INTEL_##x] = #x
>> @@ -67,6 +69,14 @@ const char *intel_platform_name(enum intel_platform
>> platform)
>> return platform_names[platform];
>> }
>>
>> +void intel_device_info_dump_flags(const struct intel_device_info *info,
>> + struct drm_printer *p)
>> +{
>> +#define PRINT_FLAG(name) drm_printf(p, "%s: %s\n", #name,
>> yesno(info->name));
>> + DEV_INFO_FOR_EACH_FLAG(PRINT_FLAG);
>> +#undef PRINT_FLAG
>> +}
>> +
>> void intel_device_info_dump(struct drm_i915_private *dev_priv)
>> {
>> const struct intel_device_info *info = &dev_priv->info;
>> @@ -76,10 +86,12 @@ void intel_device_info_dump(struct drm_i915_private
>> *dev_priv)
>> info->gen,
>> dev_priv->drm.pdev->device,
>> dev_priv->drm.pdev->revision);
>> -#define PRINT_FLAG(name) \
>> - DRM_DEBUG_DRIVER("i915 device info: " #name ": %s"
Re: [Intel-gfx] [PATCH] kthread: finer-grained lockdep/cross-release completion
On Sun, Dec 17, 2017 at 11:11 PM, Daniel Vetter wrote: > > This didn't seem to have made it into -rc4. Anything needed to get it > going? Do you actually see the problem in -rc4? Because we ended up removing the cross-release checking due to other developers complaining. It seemed to need a lot more work before it was ready. So I suspect the patch is simply not relevant any more (even if it's not necessarily wrong either). Linus ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✓ Fi.CI.BAT: success for scripts/trace.pl: Remove some old code
== Series Details == Series: scripts/trace.pl: Remove some old code URL : https://patchwork.freedesktop.org/series/35526/ State : success == Summary == IGT patchset tested on top of latest successful build cfb711c046c22c3881d2334f0b43ec4eb0b9a5fc scripts/trace.pl: Auto-detect tracepoint field order with latest DRM-Tip kernel build CI_DRM_3542 dcb649c7cee0 drm-tip: 2017y-12m-18d-16h-15m-16s UTC integration manifest No testlist changes. Test kms_pipe_crc_basic: Subgroup suspend-read-crc-pipe-b: pass -> INCOMPLETE (fi-snb-2520m) fdo#103713 fdo#103713 https://bugs.freedesktop.org/show_bug.cgi?id=103713 fi-bdw-5557u total:288 pass:267 dwarn:0 dfail:0 fail:0 skip:21 time:439s fi-bdw-gvtdvmtotal:288 pass:264 dwarn:0 dfail:0 fail:0 skip:24 time:443s fi-blb-e6850 total:288 pass:223 dwarn:1 dfail:0 fail:0 skip:64 time:386s fi-bsw-n3050 total:288 pass:242 dwarn:0 dfail:0 fail:0 skip:46 time:500s fi-bwr-2160 total:288 pass:183 dwarn:0 dfail:0 fail:0 skip:105 time:276s fi-bxt-dsi total:288 pass:258 dwarn:0 dfail:0 fail:0 skip:30 time:495s fi-bxt-j4205 total:288 pass:259 dwarn:0 dfail:0 fail:0 skip:29 time:496s fi-byt-j1900 total:288 pass:253 dwarn:0 dfail:0 fail:0 skip:35 time:482s fi-byt-n2820 total:288 pass:249 dwarn:0 dfail:0 fail:0 skip:39 time:466s fi-elk-e7500 total:224 pass:163 dwarn:15 dfail:0 fail:0 skip:45 fi-gdg-551 total:288 pass:178 dwarn:1 dfail:0 fail:1 skip:108 time:266s fi-glk-1 total:288 pass:260 dwarn:0 dfail:0 fail:0 skip:28 time:532s fi-hsw-4770 total:288 pass:261 dwarn:0 dfail:0 fail:0 skip:27 time:407s fi-hsw-4770r total:288 pass:261 dwarn:0 dfail:0 fail:0 skip:27 time:415s fi-ilk-650 total:288 pass:228 dwarn:0 dfail:0 fail:0 skip:60 time:403s fi-ivb-3520m total:288 pass:259 dwarn:0 dfail:0 fail:0 skip:29 time:478s fi-ivb-3770 total:288 pass:255 dwarn:0 dfail:0 fail:0 skip:33 time:435s fi-kbl-7500u total:288 pass:263 dwarn:1 dfail:0 fail:0 skip:24 time:482s fi-kbl-7560u total:288 pass:268 dwarn:1 dfail:0 fail:0 skip:19 time:524s fi-kbl-7567u total:288 pass:268 dwarn:0 dfail:0 fail:0 skip:20 time:470s fi-kbl-r total:288 pass:261 dwarn:0 dfail:0 fail:0 skip:27 time:525s fi-pnv-d510 total:288 pass:222 dwarn:1 dfail:0 fail:0 skip:65 time:579s fi-skl-6260u total:288 pass:268 dwarn:0 dfail:0 fail:0 skip:20 time:434s fi-skl-6600u total:288 pass:260 dwarn:1 dfail:0 fail:0 skip:27 time:535s fi-skl-6700hqtotal:288 pass:262 dwarn:0 dfail:0 fail:0 skip:26 time:554s fi-skl-6700k2total:288 pass:264 dwarn:0 dfail:0 fail:0 skip:24 time:509s fi-skl-6770hqtotal:288 pass:268 dwarn:0 dfail:0 fail:0 skip:20 time:505s fi-skl-gvtdvmtotal:288 pass:265 dwarn:0 dfail:0 fail:0 skip:23 time:450s fi-snb-2520m total:245 pass:211 dwarn:0 dfail:0 fail:0 skip:33 fi-snb-2600 total:288 pass:248 dwarn:0 dfail:0 fail:0 skip:40 time:416s Blacklisted hosts: fi-cfl-s2total:288 pass:262 dwarn:0 dfail:0 fail:0 skip:26 time:593s fi-glk-dsi total:22 pass:16 dwarn:5 dfail:0 fail:0 skip:0 == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_694/issues.html ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH i-g-t] tests/gem_ctx_param: Update invalid param
On 15/12/17 16:14, Chris Wilson wrote:
Quoting Antonio Argenziano (2017-12-15 19:01:11)
Since commit: drm/i915/scheduler: Support user-defined priorities, the
driver support an extra context param to set context's priority. Add
tests for that interface and update invalid tests.
Signed-off-by: Antonio Argenziano
Cc: Chris Wilson
Cc: Michal Winiarski
---
tests/gem_ctx_param.c | 77 ++-
1 file changed, 76 insertions(+), 1 deletion(-)
diff --git a/tests/gem_ctx_param.c b/tests/gem_ctx_param.c
index c20ae1ee..9a222e60 100644
--- a/tests/gem_ctx_param.c
+++ b/tests/gem_ctx_param.c
@@ -25,6 +25,7 @@
*/
#include "igt.h"
+#include
IGT_TEST_DESCRIPTION("Basic test for context set/get param input validation.");
@@ -136,11 +137,85 @@ igt_main
gem_context_set_param(fd, &arg);
}
+#define MAX_PRIO 1023
+#define MIN_PRIO -MAX_PRIO
+#define DEF_PRIO 0
Take these from the uapi header.
+
+ arg.param = I915_CONTEXT_PARAM_PRIORITY;
+
+ igt_subtest("root-set-priority") {
+ arg.ctx_id = ctx;
+ arg.size = 0;
+
Bonus points for CAP_SYS_NICE checking.
arg.size validation checking. > arg.value > u32 (checking for overflows)
What is the expectation for overflows? It looks like we only cast value
to int.
gem_context_get_param() of a new context should return DEF_PRIO
set_param on older machines returns -ENODEV
And that's not even trying to fuzz bad values beyond the sanity checks
of I915_CONTEXT_PARAM_PRIORITY.
+ for (int i = MIN_PRIO; i <= MAX_PRIO; i += 1023) {
It's a couple of ioctls, do all 1024. Do them in a random order, trust
no one.
Do we have a lib for doing that (generate a random permutation) already?
+ arg.value = i;
+ gem_context_set_param(fd, &arg);
+
+ gem_context_get_param(fd, &arg);
+ igt_assert(arg.value == i); /* Verify prio was set */
igt_assert_eq(arg.value, i);
But doesn't verify the priority does anything. Just the RTT in the API,
which is a nice verification nevertheless.
+ }
+ }
+
+ igt_subtest("root-set-priority-invalid-value") {
+ int prio_levels[] = {INT_MIN, MIN_PRIO - 1, MAX_PRIO + 1,
INT_MAX};
+ int old_value;
+ arg.ctx_id = ctx;
+
+ gem_context_get_param(fd, &arg);
+ old_value = arg.value;
+
+ for (int i = 0; i < (sizeof(prio_levels) / sizeof(int)); i++) {
ARRAY_SIZE(prio_levels);
+ arg.value = prio_levels[i];
+ igt_assert_eq(__gem_context_set_param(fd, &arg),
-EINVAL);
+
+ gem_context_get_param(fd, &arg);
+ igt_assert(arg.value == old_value); /* Verify prio was
not set */
+ }
+ }
+
+ igt_subtest("user-set-priority") {
+ arg.size = 0;
+
+ igt_fork(child, 1) {
+ igt_drop_root();
+ for (int i = MIN_PRIO; i <= DEF_PRIO; i += 1023) {
+ arg.value = i;
+ gem_context_set_param(fd, &arg);
+
+ gem_context_get_param(fd, &arg);
+ igt_assert(arg.value == i); /* Verify prio was
set */
I wonder if the CAP_SYS_NICE limit might be adjusted in the future.
Certainly preemption rules are flexible, as we haven't told anyone about
them yet.
I guess when the change comes we will have a new constant we could swap
DEF_PRIO with.
-Antonio
-Chris
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH] drm/i915/guc : Decoupling ADS and logs from submission
The Additional Data Struct (ADS) contains objects that are required by
GuC post FW load and are not necessarily submission-only. Even with
submission disabled we may require something inside the ADS, so it
makes more sense for them to be always created.
Similarly, we still want to access GuC logs and even if GuC submission
is disable to debug issues with GuC loading or with whatever we're using
GuC for. To make a concrete example, the pages used by GuC to save state
during suspend are allocated as part of the ADS.
Signed-off-by: Sujaritha Sundaresan
Cc: Daniele Ceraolo Spurio
Cc: Michal Wajdeczko
Cc: Oscar Mateo
Cc: Sagar Arun Kamble
---
drivers/gpu/drm/i915/Makefile | 1 +
drivers/gpu/drm/i915/intel_guc.c| 18
drivers/gpu/drm/i915/intel_guc_ads.c| 151
drivers/gpu/drm/i915/intel_guc_ads.h| 33 ++
drivers/gpu/drm/i915/intel_guc_submission.c | 134
5 files changed, 203 insertions(+), 134 deletions(-)
create mode 100644 drivers/gpu/drm/i915/intel_guc_ads.c
create mode 100644 drivers/gpu/drm/i915/intel_guc_ads.h
diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makefile
index 091aef2..4d9e2f8 100644
--- a/drivers/gpu/drm/i915/Makefile
+++ b/drivers/gpu/drm/i915/Makefile
@@ -83,6 +83,7 @@ i915-y += i915_cmd_parser.o \
i915-y += intel_uc.o \
intel_uc_fw.o \
intel_guc.o \
+ intel_guc_ads.o \
intel_guc_ct.o \
intel_guc_fw.o \
intel_guc_log.o \
diff --git a/drivers/gpu/drm/i915/intel_guc.c b/drivers/gpu/drm/i915/intel_guc.c
index 3c6bf5a..50b4725 100644
--- a/drivers/gpu/drm/i915/intel_guc.c
+++ b/drivers/gpu/drm/i915/intel_guc.c
@@ -23,6 +23,7 @@
*/
#include "intel_guc.h"
+#include "intel_guc_ads.h"
#include "intel_guc_submission.h"
#include "i915_drv.h"
@@ -163,10 +164,25 @@ int intel_guc_init(struct intel_guc *guc)
return ret;
GEM_BUG_ON(!guc->shared_data);
+ ret = intel_guc_log_create(guc);
+ if (ret)
+ goto err_shared;
+
+ ret = intel_guc_ads_create(guc);
+ if (ret)
+ goto err_log;
+ GEM_BUG_ON(!guc->ads_vma);
+
/* We need to notify the guc whenever we change the GGTT */
i915_ggtt_enable_guc(dev_priv);
return 0;
+
+err_log:
+ intel_guc_log_destroy(guc);
+err_shared:
+ guc_shared_data_destroy(guc);
+ return ret;
}
void intel_guc_fini(struct intel_guc *guc)
@@ -174,6 +190,8 @@ void intel_guc_fini(struct intel_guc *guc)
struct drm_i915_private *dev_priv = guc_to_i915(guc);
i915_ggtt_disable_guc(dev_priv);
+ intel_guc_ads_destroy(guc);
+ intel_guc_log_destroy(guc);
guc_shared_data_destroy(guc);
}
diff --git a/drivers/gpu/drm/i915/intel_guc_ads.c
b/drivers/gpu/drm/i915/intel_guc_ads.c
new file mode 100644
index 000..f6066bc
--- /dev/null
+++ b/drivers/gpu/drm/i915/intel_guc_ads.c
@@ -0,0 +1,151 @@
+/*
+ * Copyright © 2014-2017 Intel Corporation
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the next
+ * paragraph) shall be included in all copies or substantial portions of the
+ * Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
+ * IN THE SOFTWARE.
+ *
+ */
+
+#include "intel_guc_ads.h"
+#include "intel_uc.h"
+#include "i915_drv.h"
+
+/*
+ * The Additional Data Struct (ADS) has pointers for different buffers used by
+ * the GuC. One single gem object contains the ADS struct itself (guc_ads), the
+ * scheduling policies (guc_policies), a structure describing a collection of
+ * register sets (guc_mmio_reg_state) and some extra pages for the GuC to save
+ * its internal state for sleep.
+ */
+
+static void guc_policy_init(struct guc_policy *policy)
+{
+ policy->execution_quantum = POLICY_DEFAULT_EXECUTION_QUANTUM_US;
+ policy->preemption_time = POLICY_DEFAULT_PREEMPTION_TIME_US;
+ policy->fault_time = POLICY_DEFAULT_FAULT_TIME_US;
+ policy->policy_flags = 0;
+}
+
+static void guc_policies_init(struct guc_policies *
Re: [Intel-gfx] [PATCH 4/5] drm/i915: Write AVI infoframes for Parade LSPCON
Op 14-11-17 om 16:17 schreef Shashank Sharma:
> Different LSPCON vendors specify their custom methods to pass
> AVI infoframes to the LSPCON chip, so does Parade tech.
>
> This patch adds functions to arrange and write AVI infoframes
> into Parade LSPCON chips.
>
> Signed-off-by: Shashank Sharma
> ---
> drivers/gpu/drm/i915/intel_lspcon.c | 119
> +++-
> 1 file changed, 118 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_lspcon.c
> b/drivers/gpu/drm/i915/intel_lspcon.c
> index 1ac4c47..77f0687 100644
> --- a/drivers/gpu/drm/i915/intel_lspcon.c
> +++ b/drivers/gpu/drm/i915/intel_lspcon.c
> @@ -37,6 +37,12 @@
> #define LSPCON_MCA_AVI_IF_KICKOFF (1 << 0)
> #define LSPCON_MCA_AVI_IF_HANDLED (1 << 1)
>
> +/* AUX addresses to write Parade AVI IF */
> +#define LSPCON_PARADE_AVI_IF_WRITE_OFFSET 0x516
> +#define LSPCON_PARADE_AVI_IF_CTRL 0x51E
> +#define LSPCON_PARADE_AVI_IF_KICKOFF (1 << 7)
> +#define LSPCON_PARADE_AVI_IF_DATA_SIZE 32
> +
> static struct intel_dp *lspcon_to_intel_dp(struct intel_lspcon *lspcon)
> {
> struct intel_digital_port *dig_port =
> @@ -241,6 +247,113 @@ static void lspcon_resume_in_pcon_wa(struct
> intel_lspcon *lspcon)
> DRM_DEBUG_KMS("LSPCON DP descriptor mismatch after resume\n");
> }
>
> +static bool lspcon_parade_fw_ready(struct drm_dp_aux *aux)
> +{
> + u8 avi_if_ctrl;
> + u8 retry;
> + ssize_t ret;
> +
> + /* Check if LSPCON FW is ready for data */
> + for (retry = 0; retry < 5; retry++) {
> +
> + if (retry)
> + usleep_range(200, 300);
> +
> + ret = drm_dp_dpcd_read(aux, LSPCON_PARADE_AVI_IF_CTRL,
> +&avi_if_ctrl, 1);
> + if (ret < 0) {
> + DRM_ERROR("Failed to read AVI IF control\n");
> + return false;
> + }
> +
> + if ((avi_if_ctrl & LSPCON_PARADE_AVI_IF_KICKOFF) == 0)
> + return true;
> + }
> +
> + DRM_ERROR("Parade FW not ready to accept AVI IF\n");
> + return false;
> +}
> +
> +static bool _lspcon_parade_write_infoframe_blocks(struct drm_dp_aux *aux,
> +uint8_t *avi_buf)
> +{
> + u8 avi_if_ctrl;
> + u8 block_count = 0;
> + u8 *data;
> + uint16_t reg;
> + ssize_t ret;
> +
> + while (block_count < 4) {
> +
> + if (!lspcon_parade_fw_ready(aux)) {
> + DRM_DEBUG_KMS("LSPCON FW not ready, block %d\n",
> +block_count);
> + return false;
> + }
> +
> + reg = LSPCON_PARADE_AVI_IF_WRITE_OFFSET;
> + data = avi_buf + block_count * 8;
> + ret = drm_dp_dpcd_write(aux, reg, data, 8);
> + if (ret < 0) {
> + DRM_ERROR("Failed to write AVI IF block %d\n",
> +block_count);
> + return false;
> + }
> +
> + /*
> + * Once a block of data is written, we have to inform the FW
> + * about this by writing into avi infoframe control register:
> + * - set the kickoff bit[7] to 1
> + * - write the block no. to bits[1:0]
> + */
> + reg = LSPCON_PARADE_AVI_IF_CTRL;
> + avi_if_ctrl = LSPCON_PARADE_AVI_IF_KICKOFF | block_count;
> + ret = drm_dp_dpcd_write(aux, reg, &avi_if_ctrl, 1);
> + if (ret < 0) {
> + DRM_ERROR("Failed to update (0x%x), block %d\n",
> + reg, block_count);
> + return false;
> + }
> +
> + block_count++;
> + }
> +
> + DRM_DEBUG_KMS("Wrote AVI IF blocks successfully\n");
> + return true;
> +}
> +
> +static bool _lspcon_write_avi_infoframe_parade(struct drm_dp_aux *aux,
> +const uint8_t *frame,
> +ssize_t len)
> +{
> + uint8_t avi_if[LSPCON_PARADE_AVI_IF_DATA_SIZE] = {1, };
> +
> + /*
> + * Parade's frames contains 32 bytes of data, divided
> + * into 4 frames:
> + * Token byte (first byte of first frame, must be non-zero)
> + * HB0 to HB2 from AVI IF (3 bytes header)
> + * PB0 to PB27 from AVI IF (28 bytes data)
> + * So it should look like this
> + * first block: ||
> + * next 3 blocks:
> + */
> +
> + if (len > LSPCON_PARADE_AVI_IF_DATA_SIZE - 1) {
> + DRM_ERROR("Invalid length of infoframes\n");
> + return false;
> + }
> +
> + memcpy(&avi_if[1], frame, len);
> +
> + if (!_lspcon_parade_write_infoframe_blocks(aux, avi_if)) {
> + DRM_DEBUG_KMS("Failed to write infoframe blocks\n");
> + return false;
> + }
> +
> + return true;
> +}
>
Re: [Intel-gfx] [PATCH 5/5] drm/i915: Add YCBCR 4:2:0 support for LSPCON
Op 14-11-17 om 16:17 schreef Shashank Sharma:
> LSPCON chips are capable of generating YCBCR 4:2:0 outputs, if asked
> nicely :). In order to generate YCBCR 4:2:0 outputs, a source must:
> - send YCBCR 4:4:4 signals to LSPCON
> - program color space as 4:2:0 in AVI infoframes
>
> This will indicate LSPCON FW to start scaling down from YCBCR 4:4:4
> and generate YCBCR 4:2:0 output. Unlike HDMI 2.0 native case, as the
> scaling is done by LSPCON device, we need not to reserve a scaler for
> 4:2:0 outputs.
>
> Signed-off-by: Shashank Sharma
> ---
> drivers/gpu/drm/i915/i915_reg.h | 2 ++
> drivers/gpu/drm/i915/intel_ddi.c | 8
> drivers/gpu/drm/i915/intel_display.c | 15 +++
> drivers/gpu/drm/i915/intel_dp.c | 7 ++-
> drivers/gpu/drm/i915/intel_drv.h | 2 ++
> drivers/gpu/drm/i915/intel_lspcon.c | 22 ++
> 6 files changed, 51 insertions(+), 5 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index f0f8f60..ea6ef5e 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -8495,6 +8495,8 @@ enum skl_power_gate {
> #define TRANS_MSA_MISC(tran) _MMIO_TRANS2(tran, _TRANSA_MSA_MISC)
>
> #define TRANS_MSA_SYNC_CLK (1<<0)
> +#define TRANS_MSA_SAMPLING_444(2<<1)
> +#define TRANS_MSA_CLRSP_YCBCR (2<<3)
> #define TRANS_MSA_6_BPC (0<<5)
> #define TRANS_MSA_8_BPC (1<<5)
> #define TRANS_MSA_10_BPC(2<<5)
> diff --git a/drivers/gpu/drm/i915/intel_ddi.c
> b/drivers/gpu/drm/i915/intel_ddi.c
> index 9e2ab02..3fd839d 100644
> --- a/drivers/gpu/drm/i915/intel_ddi.c
> +++ b/drivers/gpu/drm/i915/intel_ddi.c
> @@ -1499,6 +1499,14 @@ void intel_ddi_set_pipe_settings(const struct
> intel_crtc_state *crtc_state)
> break;
> }
>
> + /*
> + * To get YCBCR 420 output from LSPCON, we should send YCBCR 444
> + * signals. And as per DP 1.2 spec section 2.3.4.3 while sending
> + * YCBCR 444 signals we should program MSA MISC1/0 fields with
> + * colorspace information.
> + */
> + if (crtc_state->lspcon_active && crtc_state->ycbcr420)
> + temp |= TRANS_MSA_SAMPLING_444 | TRANS_MSA_CLRSP_YCBCR;
> I915_WRITE(TRANS_MSA_MISC(cpu_transcoder), temp);
> }
>
> diff --git a/drivers/gpu/drm/i915/intel_display.c
> b/drivers/gpu/drm/i915/intel_display.c
> index 737de25..787119b 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -4638,7 +4638,8 @@ skl_update_scaler(struct intel_crtc_state *crtc_state,
> bool force_detach,
>*/
> need_scaling = src_w != dst_w || src_h != dst_h;
>
> - if (crtc_state->ycbcr420 && scaler_user == SKL_CRTC_INDEX)
> + if (crtc_state->ycbcr420 && scaler_user == SKL_CRTC_INDEX &&
> + !crtc_state->lspcon_active)
> need_scaling = true;
>
> /*
> @@ -8133,9 +8134,15 @@ static void haswell_set_pipemisc(struct drm_crtc *crtc)
> val |= PIPEMISC_DITHER_ENABLE | PIPEMISC_DITHER_TYPE_SP;
>
> if (config->ycbcr420) {
> - val |= PIPEMISC_OUTPUT_COLORSPACE_YUV |
> - PIPEMISC_YUV420_ENABLE |
> - PIPEMISC_YUV420_MODE_FULL_BLEND;
> + val |= PIPEMISC_OUTPUT_COLORSPACE_YUV;
> + /*
> + * LSPCON doesn't need scaling/blending to be done in
> + * pipe. It just needs YCBCR444 input and proper AVI
> + * infoframes for 4:2:0 output enabling.
> + */
> + if (!config->lspcon_active)
> + val |= PIPEMISC_YUV420_ENABLE |
> +PIPEMISC_YUV420_MODE_FULL_BLEND;
> }
>
> I915_WRITE(PIPEMISC(intel_crtc->pipe), val);
> diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
> index fa9e5e6..1d4b669 100644
> --- a/drivers/gpu/drm/i915/intel_dp.c
> +++ b/drivers/gpu/drm/i915/intel_dp.c
> @@ -1657,8 +1657,13 @@ intel_dp_compute_config(struct intel_encoder *encoder,
> intel_dp->max_link_rate);
>
> /* LSPCON needs special handling to drive YCBCR420 outputs */
> - if (lspcon->active)
> + if (lspcon->active) {
> + struct drm_connector *connector = &intel_connector->base;
> +
> pipe_config->lspcon_active = true;
> + pipe_config->ycbcr420 = lspcon_ycbcr420_config(connector,
> +pipe_config);
> + }
>
> /* No common link rates between source and sink */
> WARN_ON(common_len <= 0);
> diff --git a/drivers/gpu/drm/i915/intel_drv.h
> b/drivers/gpu/drm/i915/intel_drv.h
> index a468dd6..f271967 100644
> --- a/drivers/gpu/drm/i915
Re: [Intel-gfx] [PATCH] drm/i915/glk: Disable Guc and HuC on GLK
>-Original Message-
>From: Vivi, Rodrigo
>Sent: Friday, December 15, 2017 3:03 PM
>To: Wajdeczko, Michal
>Cc: intel-gfx@lists.freedesktop.org; Srivatsa, Anusha
>
>Subject: Re: [Intel-gfx] [PATCH] drm/i915/glk: Disable Guc and HuC on GLK
>
>On Fri, Dec 15, 2017 at 06:07:27AM +, Michal Wajdeczko wrote:
>> On Thu, 14 Dec 2017 23:30:56 +0100, Srivatsa, Anusha
>> wrote:
>>
>> >
>> >
>> > > -Original Message-
>> > > From: Wajdeczko, Michal
>> > > Sent: Thursday, December 14, 2017 2:18 PM
>> > > To: intel-gfx@lists.freedesktop.org; Srivatsa, Anusha
>> > >
>> > > Cc: Vivi, Rodrigo
>> > > Subject: Re: [Intel-gfx] [PATCH] drm/i915/glk: Disable Guc and HuC
>> > > on GLK
>> > >
>> > > On Thu, 14 Dec 2017 22:58:37 +0100, Anusha Srivatsa
>> > > wrote:
>> > >
>> > > > Since the firmwares are released yet to public repo, disable
>> > > > them on Geminilake.
>> > > >
>> > > > Cc: Rodrigo Vivi
>> > > > Signed-off-by: Anusha Srivatsa
>> > > > ---
>> > > > drivers/gpu/drm/i915/i915_pci.c | 5 +
>> > > > 1 file changed, 5 insertions(+)
>> > > >
>> > > > diff --git a/drivers/gpu/drm/i915/i915_pci.c
>> > > > b/drivers/gpu/drm/i915/i915_pci.c index fa67d3d..ddf7530 100644
>> > > > --- a/drivers/gpu/drm/i915/i915_pci.c
>> > > > +++ b/drivers/gpu/drm/i915/i915_pci.c
>> > > > @@ -521,6 +521,11 @@ static const struct intel_device_info
>> > > > intel_geminilake_info __initconst = {
>> > > >GEN9_LP_FEATURES,
>> > > >.platform = INTEL_GEMINILAKE,
>> > > >.ddb_size = 1024,
>> > > > + /* FIXME Geminilake supports GuC but currently firmwares
>> > > > + * have not made it to public repo. Lets disable the support
>> > > > + * as a temporary fix.
>> > > > + */
>> > > > + .has_guc = 0,
>> > >
>> > > Maybe better place to put this fix is __get_platform_enable_guc()
>> > > like in [1] [1] https://patchwork.freedesktop.org/patch/192006/
>> >
>> > Michal,
>> > Hmm the reference patch is controlling guc/huc through a module
>> > parameter but wont the above approach be neater platform wise?
>>
>> With your patch it would be impossible to check even preliminary
>> firmwares from non-public repo without recompilation of the driver.
>>
>> While with variant below it would just require changing modparams like:
>> enable_guc=1
>> guc_firmware_path=preliminary/glk.bin
>
>This is a fair point imo. With has_guc=0 you remove the possibility of testing
>preliminary GuC/HuC without a kernel patch...
>
>>
>> Note that auto mode (enable_guc=-1) will still keep GuC disabled for GLK.
>
>... but I believe that the main point here is that if we don't have a public
>image it
>doesn't exist from the upstream perspective.
Correct
>The ideal is not need this patch and releasing firmware sooner. I see same
>happening for all upcoming platforms...
>
>So, whatever we decide for this case needs to cover future cases as well.
I agree. While both the places discussed is good to make this change, I am
inclining towards making at the platform definition level. I do need more
feedback on this since we want that to be the norm moving forward.
Anusha
>Thanks,
>Rodrigo.
>
>>
>> Michal
>>
>> >
>> > Anusha
>> > > diff --git a/drivers/gpu/drm/i915/intel_uc.c
>> > > b/drivers/gpu/drm/i915/intel_uc.c index 49bccc9..22b0afe 100644
>> > > --- a/drivers/gpu/drm/i915/intel_uc.c
>> > > +++ b/drivers/gpu/drm/i915/intel_uc.c
>> > > @@ -60,6 +60,8 @@ static int __get_platform_enable_guc(struct
>> > > drm_i915_private *dev_priv)
>> > > enable_guc |= ENABLE_GUC_LOAD_HUC;
>> > >
>> > > /* Any platform specific fine-tuning can be done here */
>> > > +if (IS_GEMINILAKE(dev_priv))
>> > > +enable_guc = 0; /* no firmware on CI machines */
>> > >
>> > > return enable_guc;
>> > > }
>> > >
>> > >
>> > > >GLK_COLORS,
>> > > > };
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✗ Fi.CI.IGT: warning for scripts/trace.pl: Remove some old code
== Series Details == Series: scripts/trace.pl: Remove some old code URL : https://patchwork.freedesktop.org/series/35526/ State : warning == Summary == Test kms_frontbuffer_tracking: Subgroup fbc-1p-offscren-pri-shrfb-draw-render: fail -> PASS (shard-snb) fdo#101623 +1 Test drv_suspend: Subgroup debugfs-reader: skip -> PASS (shard-hsw) Test kms_fbcon_fbt: Subgroup fbc-suspend: pass -> SKIP (shard-snb) Test drv_selftest: Subgroup live_hangcheck: incomplete -> PASS (shard-snb) fdo#104313 fdo#101623 https://bugs.freedesktop.org/show_bug.cgi?id=101623 fdo#104313 https://bugs.freedesktop.org/show_bug.cgi?id=104313 shard-hswtotal:2712 pass:1537 dwarn:1 dfail:0 fail:10 skip:1164 time:9412s shard-snbtotal:2712 pass:1308 dwarn:1 dfail:0 fail:11 skip:1392 time:7964s Blacklisted hosts: shard-apltotal:2690 pass:1663 dwarn:1 dfail:0 fail:23 skip:1001 time:13311s shard-kbltotal:2691 pass:1782 dwarn:3 dfail:1 fail:25 skip:879 time:10261s == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_694/shards.html ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/guc : Decoupling ADS and logs from submission
== Series Details == Series: drm/i915/guc : Decoupling ADS and logs from submission URL : https://patchwork.freedesktop.org/series/35530/ State : success == Summary == Series 35530v1 drm/i915/guc : Decoupling ADS and logs from submission https://patchwork.freedesktop.org/api/1.0/series/35530/revisions/1/mbox/ Test gem_mmap_gtt: Subgroup basic-small-bo-tiledx: fail -> PASS (fi-gdg-551) fdo#102575 Test kms_pipe_crc_basic: Subgroup suspend-read-crc-pipe-a: pass -> DMESG-WARN (fi-kbl-r) fdo#104172 Test kms_psr_sink_crc: Subgroup psr_basic: pass -> DMESG-WARN (fi-skl-6700hq) fdo#101144 fdo#102575 https://bugs.freedesktop.org/show_bug.cgi?id=102575 fdo#104172 https://bugs.freedesktop.org/show_bug.cgi?id=104172 fdo#101144 https://bugs.freedesktop.org/show_bug.cgi?id=101144 fi-bdw-5557u total:288 pass:267 dwarn:0 dfail:0 fail:0 skip:21 time:435s fi-bdw-gvtdvmtotal:288 pass:264 dwarn:0 dfail:0 fail:0 skip:24 time:439s fi-blb-e6850 total:288 pass:223 dwarn:1 dfail:0 fail:0 skip:64 time:383s fi-bsw-n3050 total:288 pass:242 dwarn:0 dfail:0 fail:0 skip:46 time:493s fi-bwr-2160 total:288 pass:183 dwarn:0 dfail:0 fail:0 skip:105 time:276s fi-bxt-dsi total:288 pass:258 dwarn:0 dfail:0 fail:0 skip:30 time:491s fi-bxt-j4205 total:288 pass:259 dwarn:0 dfail:0 fail:0 skip:29 time:494s fi-byt-j1900 total:288 pass:253 dwarn:0 dfail:0 fail:0 skip:35 time:472s fi-byt-n2820 total:288 pass:249 dwarn:0 dfail:0 fail:0 skip:39 time:467s fi-elk-e7500 total:224 pass:163 dwarn:15 dfail:0 fail:0 skip:45 fi-gdg-551 total:288 pass:179 dwarn:1 dfail:0 fail:0 skip:108 time:261s fi-glk-1 total:288 pass:260 dwarn:0 dfail:0 fail:0 skip:28 time:529s fi-hsw-4770 total:288 pass:261 dwarn:0 dfail:0 fail:0 skip:27 time:403s fi-hsw-4770r total:288 pass:261 dwarn:0 dfail:0 fail:0 skip:27 time:415s fi-ilk-650 total:288 pass:228 dwarn:0 dfail:0 fail:0 skip:60 time:387s fi-ivb-3520m total:288 pass:259 dwarn:0 dfail:0 fail:0 skip:29 time:474s fi-ivb-3770 total:288 pass:255 dwarn:0 dfail:0 fail:0 skip:33 time:426s fi-kbl-7500u total:288 pass:263 dwarn:1 dfail:0 fail:0 skip:24 time:483s fi-kbl-7560u total:288 pass:268 dwarn:1 dfail:0 fail:0 skip:19 time:519s fi-kbl-7567u total:288 pass:268 dwarn:0 dfail:0 fail:0 skip:20 time:467s fi-kbl-r total:288 pass:260 dwarn:1 dfail:0 fail:0 skip:27 time:525s fi-pnv-d510 total:288 pass:222 dwarn:1 dfail:0 fail:0 skip:65 time:576s fi-skl-6260u total:288 pass:268 dwarn:0 dfail:0 fail:0 skip:20 time:443s fi-skl-6600u total:288 pass:260 dwarn:1 dfail:0 fail:0 skip:27 time:529s fi-skl-6700hqtotal:288 pass:261 dwarn:1 dfail:0 fail:0 skip:26 time:553s fi-skl-6700k2total:288 pass:264 dwarn:0 dfail:0 fail:0 skip:24 time:516s fi-skl-6770hqtotal:288 pass:268 dwarn:0 dfail:0 fail:0 skip:20 time:497s fi-skl-gvtdvmtotal:288 pass:265 dwarn:0 dfail:0 fail:0 skip:23 time:442s fi-snb-2520m total:288 pass:248 dwarn:0 dfail:0 fail:0 skip:40 time:534s fi-snb-2600 total:288 pass:248 dwarn:0 dfail:0 fail:0 skip:40 time:407s Blacklisted hosts: fi-cfl-s2total:288 pass:262 dwarn:0 dfail:0 fail:0 skip:26 time:596s fi-cnl-y total:288 pass:262 dwarn:0 dfail:0 fail:0 skip:26 time:633s fi-glk-dsi total:288 pass:258 dwarn:0 dfail:0 fail:0 skip:30 time:484s dcb649c7cee0af1ed444d25c2230f18fa4bad49e drm-tip: 2017y-12m-18d-16h-15m-16s UTC integration manifest 7067d800ecef drm/i915/guc : Decoupling ADS and logs from submission == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_7529/issues.html ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH v4 0/9] drm/i915: Implement HDCP
On Thu, Dec 7, 2017 at 5:38 AM, Jose Abreu wrote: > Hi Sean, > > On 07-12-2017 00:00, Sean Paul wrote: >> Welcome to version 4 of the patchset. I think we're nearing the finish line >> (hopefully) now. This set addresses the review feedback from v3. I applied >> some >> R-b's from v3 review, and converted others to Cc since other changes were >> made >> to the patch, and I didn't want to speak for reviewers. >> >> Thanks for all the review feedback! > > Thanks for your patches, nice to see HDCP patches making it into DRM! > > I'm not familiar with i915 driver/hw but I do am familiar with > HDCP for HDMI. Here goes a few notes: Hi Jose, Thanks for your feedback. Apologies for the delay, I was out of town on vacation. > - You should make sure that you are streaming valid TMDS data > after reading the BKSV. I think by spec you can read BKSV at any > point but the remaining operations need to be done *after* you > start sending video, otherwise you can end up with wrong Ri's > because Ri rotation is done using TMDS clock... HDCP is occurring after modeset and link training (in DP case), so we're fine in this respect. > - Also according to spec you should make sure BSTATUS reports DVI > state in first read (i.e. before start sending video) I can't find this in the spec. Can you provide a pointer? > and that > HDMI_RESERVED field is tied to one. I don't think this is required by the spec, and the bit doesn't exist for HDCP over DP. > - I think you should clearly indicate that this is for HDCP 1.4 > because HDCP 2.2 is a lot different. HDCP version is coming in a follow-on set. See previous versions of this set for the discussion. > > Also, is there any possibility to port any of these functions for > main DRM core? I mean, not the shim ops which seem very specific > for your HW, but at least a .enable, .disable, .link_check > callbacks would be useful to help others to also implement HDCP ... > This was also discussed in previous versions. Hardware HDCP implementations vary wildly, so there's not much to share. For the time being, let's keep this in i915 until we have another platform that can benefit from shared code. Thanks again for your review! Sean > Best Regards, > Jose Miguel Abreu > >> >> Sean >> >> Sean Paul (9): >> drm: Fix link-status kerneldoc line lengths >> drm/i915: Add more control to wait_for routines >> drm: Add Content Protection property >> drm: Add some HDCP related #defines >> drm/i915: Add HDCP framework + base implementation >> drm/i915: Make use of indexed write GMBUS feature >> drm/i915: Add function to output Aksv over GMBUS >> drm/i915: Implement HDCP for HDMI >> drm/i915: Implement HDCP for DisplayPort >> >> drivers/gpu/drm/drm_atomic.c | 8 + >> drivers/gpu/drm/drm_connector.c | 87 - >> drivers/gpu/drm/drm_sysfs.c | 1 + >> drivers/gpu/drm/i915/Makefile| 1 + >> drivers/gpu/drm/i915/i915_drv.h | 1 + >> drivers/gpu/drm/i915/i915_reg.h | 85 >> drivers/gpu/drm/i915/intel_atomic.c | 2 + >> drivers/gpu/drm/i915/intel_ddi.c | 36 ++ >> drivers/gpu/drm/i915/intel_display.c | 4 + >> drivers/gpu/drm/i915/intel_dp.c | 244 +++- >> drivers/gpu/drm/i915/intel_drv.h | 106 - >> drivers/gpu/drm/i915/intel_hdcp.c| 735 >> +++ >> drivers/gpu/drm/i915/intel_hdmi.c| 250 >> drivers/gpu/drm/i915/intel_i2c.c | 81 +++- >> drivers/gpu/drm/i915/intel_uncore.c | 23 +- >> drivers/gpu/drm/i915/intel_uncore.h | 14 +- >> include/drm/drm_connector.h | 16 + >> include/drm/drm_dp_helper.h | 17 + >> include/drm/drm_hdcp.h | 56 +++ >> include/uapi/drm/drm_mode.h | 4 + >> 20 files changed, 1728 insertions(+), 43 deletions(-) >> create mode 100644 drivers/gpu/drm/i915/intel_hdcp.c >> create mode 100644 include/drm/drm_hdcp.h >> > ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PULL] drm-intel-next
Hi Dave,
I expect to have one more pile next week for rc6. But for now consider
already applying this one.
On this one here we had one backmerge for a reconciliation drm_print.h
between us and drm-misc-next. But that should be transparent to you.
On the GVT side it is worth to highlight that among other things
listed below we received a VFIO addition of a new ABI for mdev display
dma-buf operation, which have been reviewed by VFIO devs and acked by its
maintainer including "acked to push through gvt merge".
We also have x86/early-quirks changes coming from us, but acked by X86
Maintainers.
Here goes drm-intel-next-2017-12-14:
- Fix documentation build issues (Randy, Markus)
- Fix timestamp frequency calculation for perf on CNL (Lionel)
- New DMC firmware for Skylake (Anusha)
- GTT flush fixes and other GGTT write track and refactors (Chris)
- Taint kernel when GPU reset fails (Chris)
- Display workarounds organization (Lucas)
- GuC and HuC initialization clean-up and fixes (Michal)
- Other fixes around GuC submission (Michal)
- Execlist clean-ups like caching ELSP reg offset and improving log readability
(Chri\
s)
- Many other improvements on our logs and dumps (Chris)
- Restore GT performance in headless mode with DMC loaded (Tvrtko)
- Stop updating legacy fb parameters since FBC is not using anymore (Daniel)
- More selftest improvements (Chris)
- Preemption fixes and improvements (Chris)
- x86/early-quirks improvements for Intel graphics stolen memory. (Joonas,
Matthew)
- Other improvements on Stolen Memory code to be resource centric. (Matthew)
- Improvements and fixes on fence allocation/release (Chris).
GVT:
- fixes for two coverity scan errors (Colin)
- mmio switch code refine (Changbin)
- more virtual display dmabuf fixes (Tina/Gustavo)
- misc cleanups (Pei)
- VFIO mdev display dmabuf interface and gvt support (Tina)
- VFIO mdev opregion support/fixes (Tina/Xiong/Chris)
- workload scheduling optimization (Changbin)
- preemption fix and temporal workaround (Zhenyu)
- and misc fixes after refactor (Chris)
Thanks,
Rodrigo.
The following changes since commit 3f1f0b1c57dd617e9b0ded50efb8d6c011b85b20:
Merge tag 'drm-intel-next-2017-12-01' of
git://anongit.freedesktop.org/drm/drm-intel into drm-next (2017-12-08 08:41:22
+1000)
are available in the git repository at:
git://anongit.freedesktop.org/drm/drm-intel tags/drm-intel-next-2017-12-14
for you to fetch changes up to ee5b5bf351ec8cd8f11c631cb76b30f602e866ee:
drm/i915: Update DRIVER_DATE to 20171214 (2017-12-14 12:10:02 -0800)
- Fix documentation build issues (Randy, Markus)
- Fix timestamp frequency calculation for perf on CNL (Lionel)
- New DMC firmware for Skylake (Anusha)
- GTT flush fixes and other GGTT write track and refactors (Chris)
- Taint kernel when GPU reset fails (Chris)
- Display workarounds organization (Lucas)
- GuC and HuC initialization clean-up and fixes (Michal)
- Other fixes around GuC submission (Michal)
- Execlist clean-ups like caching ELSP reg offset and improving log readability
(Chri\
s)
- Many other improvements on our logs and dumps (Chris)
- Restore GT performance in headless mode with DMC loaded (Tvrtko)
- Stop updating legacy fb parameters since FBC is not using anymore (Daniel)
- More selftest improvements (Chris)
- Preemption fixes and improvements (Chris)
- x86/early-quirks improvements for Intel graphics stolen memory. (Joonas,
Matthew)
- Other improvements on Stolen Memory code to be resource centric. (Matthew)
- Improvements and fixes on fence allocation/release (Chris).
GVT:
- fixes for two coverity scan errors (Colin)
- mmio switch code refine (Changbin)
- more virtual display dmabuf fixes (Tina/Gustavo)
- misc cleanups (Pei)
- VFIO mdev display dmabuf interface and gvt support (Tina)
- VFIO mdev opregion support/fixes (Tina/Xiong/Chris)
- workload scheduling optimization (Changbin)
- preemption fix and temporal workaround (Zhenyu)
- and misc fixes after refactor (Chris)
Anusha Srivatsa (1):
drm/i915/skl: DMC firmware for skylake v1.27
Changbin Du (6):
drm/i915/gvt: Convert macro queue_workload to a function
drm/i915/gvt: Kick scheduler when new workload queued
drm/i915/gvt: Refine the ring mmio list definition
drm/i915/gvt: Select appropriate mmio list at initialization time
drm/i915/gvt: Remove MMIO barrier in MMIO switch
drm/i915/gvt: Rename file render.{c, h} to mmio_context.{c, h}
Chris Wilson (31):
drm/i915/gvt: Cleanup unwanted public symbols
drm/i915/gvt: Fix out-of-bounds buffer write into opregion->signature[]
drm/i915: Flush pending GTT writes before unbinding
drm/i915: Taint (TAINT_WARN) the kernel if the GPU reset fails
drm/i915: Remove vma from object on destroy, not close
drm/i915: Track GGTT writes on the vma
drm/i915: Refactor common list iteration over G
[Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915/guc : Decoupling ADS and logs from submission
== Series Details == Series: drm/i915/guc : Decoupling ADS and logs from submission URL : https://patchwork.freedesktop.org/series/35530/ State : success == Summary == Test drv_suspend: Subgroup debugfs-reader: skip -> PASS (shard-hsw) Test kms_frontbuffer_tracking: Subgroup fbc-1p-offscren-pri-shrfb-draw-render: fail -> PASS (shard-snb) fdo#101623 +1 Test kms_cursor_crc: Subgroup cursor-128x128-suspend: pass -> SKIP (shard-hsw) fdo#103375 fdo#101623 https://bugs.freedesktop.org/show_bug.cgi?id=101623 fdo#103375 https://bugs.freedesktop.org/show_bug.cgi?id=103375 shard-hswtotal:2712 pass:1536 dwarn:1 dfail:0 fail:10 skip:1165 time:9351s shard-snbtotal:2694 pass:1290 dwarn:1 dfail:0 fail:11 skip:1391 time:7918s Blacklisted hosts: shard-apltotal:2712 pass:1686 dwarn:1 dfail:1 fail:23 skip:1001 time:13914s shard-kbltotal:2688 pass:1788 dwarn:1 dfail:1 fail:24 skip:873 time:10850s == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_7529/shards.html ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH i-g-t] tests/gem_ctx_param: Update invalid param
Quoting Antonio Argenziano (2017-12-18 18:15:35)
>
>
> On 15/12/17 16:14, Chris Wilson wrote:
> > Quoting Antonio Argenziano (2017-12-15 19:01:11)
> >> + arg.param = I915_CONTEXT_PARAM_PRIORITY;
> >> +
> >> + igt_subtest("root-set-priority") {
> >> + arg.ctx_id = ctx;
> >> + arg.size = 0;
> >> +
> >
> > Bonus points for CAP_SYS_NICE checking.
> >
> > arg.size validation checking. > arg.value > u32 (checking for overflows)
>
> What is the expectation for overflows? It looks like we only cast value
> to int.
That was my point. We could create 1<<32 + prio, so we really should be
failing with -EINVAL rather than setting the parameter to prio. Trust
nothing, least of all the kernel.
> > gem_context_get_param() of a new context should return DEF_PRIO
> >
> > set_param on older machines returns -ENODEV
> >
> > And that's not even trying to fuzz bad values beyond the sanity checks
> > of I915_CONTEXT_PARAM_PRIORITY.
> >
> >> + for (int i = MIN_PRIO; i <= MAX_PRIO; i += 1023) {
> >
> > It's a couple of ioctls, do all 1024. Do them in a random order, trust
> > no one.
>
> Do we have a lib for doing that (generate a random permutation) already?
See igt_permute_array. Maybe igt_random_array(count, prng_state).
> >> + arg.value = prio_levels[i];
> >> + igt_assert_eq(__gem_context_set_param(fd, &arg),
> >> -EINVAL);
> >> +
> >> + gem_context_get_param(fd, &arg);
> >> + igt_assert(arg.value == old_value); /* Verify prio
> >> was not set */
> >> + }
> >> + }
> >> +
> >> + igt_subtest("user-set-priority") {
> >> + arg.size = 0;
> >> +
> >> + igt_fork(child, 1) {
> >> + igt_drop_root();
> >> + for (int i = MIN_PRIO; i <= DEF_PRIO; i += 1023) {
> >> + arg.value = i;
> >> + gem_context_set_param(fd, &arg);
> >> +
> >> + gem_context_get_param(fd, &arg);
> >> + igt_assert(arg.value == i); /* Verify prio
> >> was set */
> >
> > I wonder if the CAP_SYS_NICE limit might be adjusted in the future.
> > Certainly preemption rules are flexible, as we haven't told anyone about
> > them yet.
>
> I guess when the change comes we will have a new constant we could swap
> DEF_PRIO with.
The question is whether it is ABI, as it may be changed. If its not,
don't enshrine it into law.
-Chris
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Re: [Intel-gfx] [PATCH] drm/i915/glk: Disable Guc and HuC on GLK
On Mon, 18 Dec 2017 20:25:17 +0100, Srivatsa, Anusha
wrote:
-Original Message-
From: Vivi, Rodrigo
Sent: Friday, December 15, 2017 3:03 PM
To: Wajdeczko, Michal
Cc: intel-gfx@lists.freedesktop.org; Srivatsa, Anusha
Subject: Re: [Intel-gfx] [PATCH] drm/i915/glk: Disable Guc and HuC on
GLK
On Fri, Dec 15, 2017 at 06:07:27AM +, Michal Wajdeczko wrote:
On Thu, 14 Dec 2017 23:30:56 +0100, Srivatsa, Anusha
wrote:
>
>
> > -Original Message-
> > From: Wajdeczko, Michal
> > Sent: Thursday, December 14, 2017 2:18 PM
> > To: intel-gfx@lists.freedesktop.org; Srivatsa, Anusha
> >
> > Cc: Vivi, Rodrigo
> > Subject: Re: [Intel-gfx] [PATCH] drm/i915/glk: Disable Guc and HuC
> > on GLK
> >
> > On Thu, 14 Dec 2017 22:58:37 +0100, Anusha Srivatsa
> > wrote:
> >
> > > Since the firmwares are released yet to public repo, disable
> > > them on Geminilake.
> > >
> > > Cc: Rodrigo Vivi
> > > Signed-off-by: Anusha Srivatsa
> > > ---
> > > drivers/gpu/drm/i915/i915_pci.c | 5 +
> > > 1 file changed, 5 insertions(+)
> > >
> > > diff --git a/drivers/gpu/drm/i915/i915_pci.c
> > > b/drivers/gpu/drm/i915/i915_pci.c index fa67d3d..ddf7530 100644
> > > --- a/drivers/gpu/drm/i915/i915_pci.c
> > > +++ b/drivers/gpu/drm/i915/i915_pci.c
> > > @@ -521,6 +521,11 @@ static const struct intel_device_info
> > > intel_geminilake_info __initconst = {
> > > GEN9_LP_FEATURES,
> > > .platform = INTEL_GEMINILAKE,
> > > .ddb_size = 1024,
> > > +/* FIXME Geminilake supports GuC but currently firmwares
> > > + * have not made it to public repo. Lets disable the support
> > > + * as a temporary fix.
> > > + */
> > > +.has_guc = 0,
> >
> > Maybe better place to put this fix is __get_platform_enable_guc()
> > like in [1] [1] https://patchwork.freedesktop.org/patch/192006/
>
> Michal,
> Hmm the reference patch is controlling guc/huc through a module
> parameter but wont the above approach be neater platform wise?
With your patch it would be impossible to check even preliminary
firmwares from non-public repo without recompilation of the driver.
While with variant below it would just require changing modparams like:
enable_guc=1
guc_firmware_path=preliminary/glk.bin
This is a fair point imo. With has_guc=0 you remove the possibility of
testing
preliminary GuC/HuC without a kernel patch...
Note that auto mode (enable_guc=-1) will still keep GuC disabled for
GLK.
... but I believe that the main point here is that if we don't have a
public image it
doesn't exist from the upstream perspective.
Correct
The ideal is not need this patch and releasing firmware sooner. I see
same
happening for all upcoming platforms...
So, whatever we decide for this case needs to cover future cases as
well.
I agree. While both the places discussed is good to make this change, I
am inclining towards making at the platform definition level. I do need
more feedback on this since we want that to be the norm moving forward.
There is a yet another option for now: remove GuC/Huc firmware names.
} else if (IS_GEMINILAKE(dev_priv)) {
- guc_fw->path = I915_GLK_GUC_UCODE;
- guc_fw->major_ver_wanted = GLK_FW_MAJOR;
- guc_fw->minor_ver_wanted = GLK_FW_MINOR;
} else {
And the norm for the future: do not define GuC/HuC firmware names without
having those images available in public.
Michal
Anusha
Thanks,
Rodrigo.
Michal
>
> Anusha
> > diff --git a/drivers/gpu/drm/i915/intel_uc.c
> > b/drivers/gpu/drm/i915/intel_uc.c index 49bccc9..22b0afe 100644
> > --- a/drivers/gpu/drm/i915/intel_uc.c
> > +++ b/drivers/gpu/drm/i915/intel_uc.c
> > @@ -60,6 +60,8 @@ static int __get_platform_enable_guc(struct
> > drm_i915_private *dev_priv)
> > enable_guc |= ENABLE_GUC_LOAD_HUC;
> >
> > /* Any platform specific fine-tuning can be done here */
> > + if (IS_GEMINILAKE(dev_priv))
> > + enable_guc = 0; /* no firmware on CI machines */
> >
> > return enable_guc;
> > }
> >
> >
> > > GLK_COLORS,
> > > };
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Re: [Intel-gfx] [PATCH 1/2] drm/i915: Add pretty printer for device info flags
Quoting Jani Nikula (2017-12-18 17:37:13) > On Mon, 18 Dec 2017, Chris Wilson wrote: > > Looks good, I'm thinking we might push the drm_printer to the caller of > > intel_device_info_dump(), but this is already a substantial improvement > > Param ordering seems a bit surprising in both patches. Target first? The param order at the moment tries to be (object-doing-the-dump, stream-as-parameter). I don't think it is quite so backwards as it first appears, when compared to printf(stderr, fmt,...) or even seq_printf(m, fmt, ..). In both of those printf cases, it is the stream that can be argued is providing the object (even more so if you create your own stream using cookie_io_functions_t). But for us, it is clearer to argue that the object we control is the object providing the method to output into the stream. -Chris ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [RFC] drm/i915: Add a new modparam for customized ring multiplier
From: Zhipeng Gong
SKL platforms requires a higher ring multiplier when there's massive
GPU load. Current driver doesn't provide a way to override the ring
multiplier.
This patch adds a new module parameter to allow the overriding of
ring multiplier for Gen9 platforms.
Cc: Ben Widawsky
Cc: Chris Wilson
Cc: Oscar Mateo
Cc: Sagar Arun Kamble
Cc: Dmitry Rogozhkin
Cc: Zhipeng Gong
Signed-off-by: Jackie Li
---
drivers/gpu/drm/i915/i915_params.c | 4 +++
drivers/gpu/drm/i915/i915_params.h | 1 +
drivers/gpu/drm/i915/intel_pm.c| 57 --
3 files changed, 53 insertions(+), 9 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_params.c
b/drivers/gpu/drm/i915/i915_params.c
index 8dfea03..f3dd179 100644
--- a/drivers/gpu/drm/i915/i915_params.c
+++ b/drivers/gpu/drm/i915/i915_params.c
@@ -101,6 +101,10 @@ i915_param_named_unsafe(disable_power_well, int, 0400,
"Disable display power wells when possible "
"(-1=auto [default], 0=power wells always on, 1=power wells disabled
when possible)");
+i915_param_named_unsafe(ring_multiplier, uint, 0400,
+ "Override Ring/GT frequency multiplier."
+ "(2=2x ring multiplier [defaut], 3=3x ring multiplier)");
+
i915_param_named_unsafe(enable_ips, int, 0600, "Enable IPS (default: true)");
i915_param_named(fastboot, bool, 0600,
diff --git a/drivers/gpu/drm/i915/i915_params.h
b/drivers/gpu/drm/i915/i915_params.h
index 792ce26..6073d1c 100644
--- a/drivers/gpu/drm/i915/i915_params.h
+++ b/drivers/gpu/drm/i915/i915_params.h
@@ -43,6 +43,7 @@
param(int, enable_ppgtt, -1) \
param(int, enable_psr, -1) \
param(int, disable_power_well, -1) \
+ param(unsigned int, ring_multiplier, 2) \
param(int, enable_ips, 1) \
param(int, invert_brightness, 0) \
param(int, enable_guc, 0) \
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index a349c4f..080051b 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -6818,6 +6818,34 @@ static void gen6_enable_rps(struct drm_i915_private
*dev_priv)
intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
}
+static inline void sanitize_ring_multiplier(struct drm_i915_private *i915)
+{
+ unsigned int m = i915_modparams.ring_multiplier;
+
+ /* Currently, only support 2x or 3x multipliers */
+ if (m != 2 && m != 3)
+ i915_modparams.ring_multiplier = 2;
+}
+
+static inline void get_ring_multiplier(struct drm_i915_private *i915,
+ unsigned int *numer,
+ unsigned int *denom)
+{
+ sanitize_ring_multiplier(i915);
+
+ if (IS_GEN9(i915)) {
+ *numer = i915_modparams.ring_multiplier;
+ *denom = 1;
+ } else if IS_HASWELL(i915) {
+ *numer = 5;
+ *denom = 2;
+ } else {
+ /* Use a 2x ring multiplier by default */
+ *numer = 2;
+ *denom = 1;
+ }
+}
+
static void gen6_update_ring_freq(struct drm_i915_private *dev_priv)
{
struct intel_rps *rps = &dev_priv->gt_pm.rps;
@@ -6825,6 +6853,8 @@ static void gen6_update_ring_freq(struct drm_i915_private
*dev_priv)
unsigned int gpu_freq;
unsigned int max_ia_freq, min_ring_freq;
unsigned int max_gpu_freq, min_gpu_freq;
+ unsigned int ring_mul_numer, ring_mul_denom;
+ unsigned int ring_request_freq;
int scaling_factor = 180;
struct cpufreq_policy *policy;
@@ -6858,6 +6888,9 @@ static void gen6_update_ring_freq(struct drm_i915_private
*dev_priv)
max_gpu_freq = rps->max_freq;
}
+
+ get_ring_multiplier(dev_priv, &ring_mul_numer, &ring_mul_denom);
+
/*
* For each potential GPU frequency, load a ring frequency we'd like
* to use for memory access. We do this by specifying the IA frequency
@@ -6867,18 +6900,24 @@ static void gen6_update_ring_freq(struct
drm_i915_private *dev_priv)
int diff = max_gpu_freq - gpu_freq;
unsigned int ia_freq = 0, ring_freq = 0;
+ /*
+* ring_request_freq = ring_multiplier * GPU frequency.
+* Ring freq is in 100MHz units while GPU frequency is in 50MHz
+* units.
+*/
+ ring_request_freq = mult_frac(gpu_freq, ring_mul_numer,
+ 2 * ring_mul_denom);
+
if (IS_GEN9_BC(dev_priv) || IS_CANNONLAKE(dev_priv)) {
/*
-* ring_freq = 2 * GT. ring_freq is in 100MHz units
-* No floor required for ring frequency on SKL.
+* ring_freq = ring request freq. No floor required for
+* ring frequency on SKL.
*/
- ring_freq = gpu_freq;
-
