[Intel-gfx] [CI 5/9] drm/i915: Add background commentary to "waitboosting"
Describe the intent of boosting the GPU frequency to maximum before
waiting on the GPU.
RPS waitboosting was introduced with commit b29c19b64528 ("drm/i915:
Boost RPS frequency for CPU stalls") but lacked a concise comment in the
code to explain itself.
Signed-off-by: Chris Wilson
Reviewed-by: Daniel Vetter
---
drivers/gpu/drm/i915/i915_gem.c | 15 +++
1 file changed, 15 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
index 037b26e2a960..b11884d656cf 100644
--- a/drivers/gpu/drm/i915/i915_gem.c
+++ b/drivers/gpu/drm/i915/i915_gem.c
@@ -1462,6 +1462,21 @@ int __i915_wait_request(struct drm_i915_gem_request *req,
trace_i915_gem_request_wait_begin(req);
+ /* This client is about to stall waiting for the GPU. In many cases
+* this is undesirable and limits the throughput of the system, as
+* many clients cannot continue processing user input/output whilst
+* blocked. RPS autotuning may take tens of milliseconds to respond
+* to the GPU load and thus incurs additional latency for the client.
+* We can circumvent that by promoting the GPU frequency to maximum
+* before we wait. This makes the GPU throttle up much more quickly
+* (good for benchmarks and user experience, e.g. window animations),
+* but at a cost of spending more power processing the workload
+* (bad for battery). Not all clients even want their results
+* immediately and for them we should just let the GPU select its own
+* frequency to maximise efficiency. To prevent a single client from
+* forcing the clocks too high for the whole system, we only allow
+* each client to waitboost once in a busy period.
+*/
if (INTEL_INFO(req->i915)->gen >= 6)
gen6_rps_boost(req->i915, rps, req->emitted_jiffies);
--
2.8.1
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[Intel-gfx] [CI 2/9] drm/i915: Do not keep postponing the idle-work
Rather than persistently postponing the idle-work everytime somebody calls i915_gem_retire_requests() (potentially ensuring that we never reach the idle state), queue the work the first time we detect all requests are complete. Then if in 100ms, more requests have been queued, we will abort the idle-worker and wait again until all the new requests have been completed. Of course, this does depend upon the idle worker cancelling itself gracefully from the previous patch. Signed-off-by: Chris Wilson Reviewed-by: Joonas Lahtinen --- drivers/gpu/drm/i915/i915_gem.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c index 133060c0f96f..78057fafd4bc 100644 --- a/drivers/gpu/drm/i915/i915_gem.c +++ b/drivers/gpu/drm/i915/i915_gem.c @@ -3255,9 +3255,9 @@ void i915_gem_retire_requests(struct drm_i915_private *dev_priv) } if (dev_priv->gt.active_engines == 0) - mod_delayed_work(dev_priv->wq, -&dev_priv->gt.idle_work, -msecs_to_jiffies(100)); + queue_delayed_work(dev_priv->wq, + &dev_priv->gt.idle_work, + msecs_to_jiffies(100)); } static void -- 2.8.1 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [CI 4/9] drm/i915: Restore waitboost credit to the synchronous waiter
Ideally, we want to automagically have the GPU respond to the
instantaneous load by reclocking itself. However, reclocking occurs
relatively slowly, and to the client waiting for a result from the GPU,
too late. To compensate and reduce the client latency, we allow the
first wait from a client to boost the GPU clocks to maximum. This
overcomes the lag in autoreclocking, at the expense of forcing the GPU
clocks too high. So to offset the excessive power usage, we currently
allow a client to only boost the clocks once before we detect the GPU
is idle again. This works reasonably for say the first frame in a
benchmark, but for many more synchronous workloads (like OpenCL) we find
the GPU clocks remain too low. By noting a wait which would idle the GPU
(i.e. we just waited upon the last known request), we can give that
client the idle boost credit (for their next wait) without the 100ms
delay required for us to detect the GPU idle state. The intention is to
boost clients that are stalling in the process of feeding the GPU more
work (and who in doing so let the GPU idle), without granting boost
credits to clients that are throttling themselves (such as compositors).
Signed-off-by: Chris Wilson
Cc: "Zou, Nanhai"
Cc: Jesse Barnes
Reviewed-by: Jesse Barnes
Reviewed-by: Daniel Vetter
---
drivers/gpu/drm/i915/i915_gem.c | 16
1 file changed, 16 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
index e6675b981e0e..037b26e2a960 100644
--- a/drivers/gpu/drm/i915/i915_gem.c
+++ b/drivers/gpu/drm/i915/i915_gem.c
@@ -1542,6 +1542,22 @@ complete:
*timeout = 0;
}
+ if (rps && req->seqno == req->engine->last_submitted_seqno) {
+ /* The GPU is now idle and this client has stalled.
+* Since no other client has submitted a request in the
+* meantime, assume that this client is the only one
+* supplying work to the GPU but is unable to keep that
+* work supplied because it is waiting. Since the GPU is
+* then never kept fully busy, RPS autoclocking will
+* keep the clocks relatively low, causing further delays.
+* Compensate by giving the synchronous client credit for
+* a waitboost next time.
+*/
+ spin_lock(&req->i915->rps.client_lock);
+ list_del_init(&rps->link);
+ spin_unlock(&req->i915->rps.client_lock);
+ }
+
return ret;
}
--
2.8.1
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[Intel-gfx] [CI 7/9] drm/i915: Remove stop-rings debugfs interface
Now that we have (near) universal GPU recovery code, we can inject a
real hang from userspace and not need any fakery. Not only does this
mean that the testing is far more realistic, but we can simplify the
kernel in the process.
Signed-off-by: Chris Wilson
Reviewed-by: Arun Siluvery
---
drivers/gpu/drm/i915/i915_debugfs.c | 35 --
drivers/gpu/drm/i915/i915_drv.c | 17 ++---
drivers/gpu/drm/i915/i915_drv.h | 19 --
drivers/gpu/drm/i915/i915_gem.c | 44 ++---
drivers/gpu/drm/i915/intel_lrc.c| 3 ---
drivers/gpu/drm/i915/intel_ringbuffer.c | 8 --
drivers/gpu/drm/i915/intel_ringbuffer.h | 1 -
7 files changed, 15 insertions(+), 112 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_debugfs.c
b/drivers/gpu/drm/i915/i915_debugfs.c
index 17b343923b42..e4409ddc60e5 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -4831,40 +4831,6 @@ DEFINE_SIMPLE_ATTRIBUTE(i915_wedged_fops,
"%llu\n");
static int
-i915_ring_stop_get(void *data, u64 *val)
-{
- struct drm_device *dev = data;
- struct drm_i915_private *dev_priv = dev->dev_private;
-
- *val = dev_priv->gpu_error.stop_rings;
-
- return 0;
-}
-
-static int
-i915_ring_stop_set(void *data, u64 val)
-{
- struct drm_device *dev = data;
- struct drm_i915_private *dev_priv = dev->dev_private;
- int ret;
-
- DRM_DEBUG_DRIVER("Stopping rings 0x%08llx\n", val);
-
- ret = mutex_lock_interruptible(&dev->struct_mutex);
- if (ret)
- return ret;
-
- dev_priv->gpu_error.stop_rings = val;
- mutex_unlock(&dev->struct_mutex);
-
- return 0;
-}
-
-DEFINE_SIMPLE_ATTRIBUTE(i915_ring_stop_fops,
- i915_ring_stop_get, i915_ring_stop_set,
- "0x%08llx\n");
-
-static int
i915_ring_missed_irq_get(void *data, u64 *val)
{
struct drm_device *dev = data;
@@ -5493,7 +5459,6 @@ static const struct i915_debugfs_files {
{"i915_max_freq", &i915_max_freq_fops},
{"i915_min_freq", &i915_min_freq_fops},
{"i915_cache_sharing", &i915_cache_sharing_fops},
- {"i915_ring_stop", &i915_ring_stop_fops},
{"i915_ring_missed_irq", &i915_ring_missed_irq_fops},
{"i915_ring_test_irq", &i915_ring_test_irq_fops},
{"i915_gem_drop_caches", &i915_drop_caches_fops},
diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index 40521a3e8b8f..7b9b6f90ca69 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -2159,24 +2159,11 @@ int i915_reset(struct drm_i915_private *dev_priv)
goto error;
}
+ pr_notice("drm/i915: Resetting chip after gpu hang\n");
+
i915_gem_reset(dev);
ret = intel_gpu_reset(dev_priv, ALL_ENGINES);
-
- /* Also reset the gpu hangman. */
- if (error->stop_rings != 0) {
- DRM_INFO("Simulated gpu hang, resetting stop_rings\n");
- error->stop_rings = 0;
- if (ret == -ENODEV) {
- DRM_INFO("Reset not implemented, but ignoring "
-"error for simulated gpu hangs\n");
- ret = 0;
- }
- }
-
- if (i915_stop_ring_allow_warn(dev_priv))
- pr_notice("drm/i915: Resetting chip after gpu hang\n");
-
if (ret) {
if (ret != -ENODEV)
DRM_ERROR("Failed to reset chip: %i\n", ret);
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 79ac130606ec..488891853cb5 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -1402,13 +1402,6 @@ struct i915_gpu_error {
*/
wait_queue_head_t reset_queue;
- /* Userspace knobs for gpu hang simulation;
-* combines both a ring mask, and extra flags
-*/
- u32 stop_rings;
-#define I915_STOP_RING_ALLOW_BAN (1 << 31)
-#define I915_STOP_RING_ALLOW_WARN (1 << 30)
-
/* For missed irq/seqno simulation. */
unsigned long test_irq_rings;
};
@@ -3360,18 +3353,6 @@ static inline u32 i915_reset_count(struct i915_gpu_error
*error)
return ((i915_reset_counter(error) & ~I915_WEDGED) + 1) / 2;
}
-static inline bool i915_stop_ring_allow_ban(struct drm_i915_private *dev_priv)
-{
- return dev_priv->gpu_error.stop_rings == 0 ||
- dev_priv->gpu_error.stop_rings & I915_STOP_RING_ALLOW_BAN;
-}
-
-static inline bool i915_stop_ring_allow_warn(struct drm_i915_private *dev_priv)
-{
- return dev_priv->gpu_error.stop_rings == 0 ||
- dev_priv->gpu_error.stop_rings & I915_STOP_RING_ALLOW_WARN;
-}
-
void i915_gem_reset(struct drm_device *dev);
bool i915_gem_clflush_object(struct drm_i915_gem_object *obj, bool force);
int __must_check i915_gem_init(st
[Intel-gfx] [CI 3/9] drm/i915: Remove redundant queue_delayed_work() from throttle ioctl
We know, by design, that whilst the GPU is active (and thus we are throttling) the retire_worker is queued. Therefore attempting to requeue it with queue_delayed_work() is a no-op and we can safely remove it. Signed-off-by: Chris Wilson Reviewed-by: Joonas Lahtinen --- drivers/gpu/drm/i915/i915_gem.c | 3 --- 1 file changed, 3 deletions(-) diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c index 78057fafd4bc..e6675b981e0e 100644 --- a/drivers/gpu/drm/i915/i915_gem.c +++ b/drivers/gpu/drm/i915/i915_gem.c @@ -4467,9 +4467,6 @@ i915_gem_ring_throttle(struct drm_device *dev, struct drm_file *file) return 0; ret = __i915_wait_request(target, true, NULL, NULL); - if (ret == 0) - queue_delayed_work(dev_priv->wq, &dev_priv->gt.retire_work, 0); - i915_gem_request_unreference(target); return ret; -- 2.8.1 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [CI 1/9] drm/i915: Only start retire worker when idle
The retire worker is a low frequency task that makes sure we retire
outstanding requests if userspace is being lax. We only need to start it
once as it remains active until the GPU is idle, so do a cheap test
before the more expensive queue_work(). A consequence of this is that we
need correct locking in the worker to make the hot path of request
submission cheap. To keep the symmetry and keep hangcheck strictly bound
by the GPU's wakelock, we move the cancel_sync(hangcheck) to the idle
worker before dropping the wakelock.
v2: Guard against RCU fouling the breadcrumbs bottom-half whilst we kick
the waiter.
v3: Remove the wakeref assertion squelching (now we hold a wakeref for
the hangcheck, any rpm error there is genuine).
v4: To prevent excess work when retiring requests, we split the busy
flag into two, a boolean to denote whether we hold the wakeref and a
bitmask of active engines.
v5: Reorder cancelling hangcheck upon idling to avoid a race where we
might cancel a hangcheck after being preempted by a new task
Signed-off-by: Chris Wilson
References: https://bugs.freedesktop.org/show_bug.cgi?id=88437
Reviewed-by: Joonas Lahtinen
---
drivers/gpu/drm/i915/i915_debugfs.c| 5 +-
drivers/gpu/drm/i915/i915_drv.c| 2 -
drivers/gpu/drm/i915/i915_drv.h| 56 ++--
drivers/gpu/drm/i915/i915_gem.c| 135 +++--
drivers/gpu/drm/i915/i915_gem_execbuffer.c | 6 ++
drivers/gpu/drm/i915/i915_irq.c| 15 +---
drivers/gpu/drm/i915/intel_display.c | 25 --
drivers/gpu/drm/i915/intel_pm.c| 2 +-
drivers/gpu/drm/i915/intel_ringbuffer.h| 4 +-
9 files changed, 135 insertions(+), 115 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_debugfs.c
b/drivers/gpu/drm/i915/i915_debugfs.c
index abc4ae8ad498..17b343923b42 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -2442,7 +2442,8 @@ static int i915_rps_boost_info(struct seq_file *m, void
*data)
struct drm_file *file;
seq_printf(m, "RPS enabled? %d\n", dev_priv->rps.enabled);
- seq_printf(m, "GPU busy? %d\n", dev_priv->mm.busy);
+ seq_printf(m, "GPU busy? %s [%x]\n",
+ yesno(dev_priv->gt.awake), dev_priv->gt.active_engines);
seq_printf(m, "CPU waiting? %d\n", count_irq_waiters(dev_priv));
seq_printf(m, "Frequency requested %d; min hard:%d, soft:%d; max
soft:%d, hard:%d\n",
intel_gpu_freq(dev_priv, dev_priv->rps.cur_freq),
@@ -2786,7 +2787,7 @@ static int i915_runtime_pm_status(struct seq_file *m,
void *unused)
if (!HAS_RUNTIME_PM(dev_priv))
seq_puts(m, "Runtime power management not supported\n");
- seq_printf(m, "GPU idle: %s\n", yesno(!dev_priv->mm.busy));
+ seq_printf(m, "GPU idle: %s\n", yesno(!dev_priv->gt.awake));
seq_printf(m, "IRQs disabled: %s\n",
yesno(!intel_irqs_enabled(dev_priv)));
#ifdef CONFIG_PM
diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index 6fa9c0338b1b..2b6494b19869 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -2735,8 +2735,6 @@ static int intel_runtime_suspend(struct device *device)
i915_gem_release_all_mmaps(dev_priv);
mutex_unlock(&dev->struct_mutex);
- cancel_delayed_work_sync(&dev_priv->gpu_error.hangcheck_work);
-
intel_guc_suspend(dev);
intel_suspend_gt_powersave(dev_priv);
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 0dcc43d2994b..79ac130606ec 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -1314,37 +1314,11 @@ struct i915_gem_mm {
struct list_head fence_list;
/**
-* We leave the user IRQ off as much as possible,
-* but this means that requests will finish and never
-* be retired once the system goes idle. Set a timer to
-* fire periodically while the ring is running. When it
-* fires, go retire requests.
-*/
- struct delayed_work retire_work;
-
- /**
-* When we detect an idle GPU, we want to turn on
-* powersaving features. So once we see that there
-* are no more requests outstanding and no more
-* arrive within a small period of time, we fire
-* off the idle_work.
-*/
- struct delayed_work idle_work;
-
- /**
* Are we in a non-interruptible section of code like
* modesetting?
*/
bool interruptible;
- /**
-* Is the GPU currently considered idle, or busy executing userspace
-* requests? Whilst idle, we attempt to power down the hardware and
-* display clocks. In order to reduce the effect on performance, there
-* is a slight delay before we do so.
-*/
- bool busy;
-
/* the indicator for dispatch video commands
[Intel-gfx] [CI 8/9] drm/i915: Record the ringbuffer associated with the request
The request tells us where to read the ringbuf from, so use that
information to simplify the error capture. If no request was active at
the time of the hang, the ring is idle and there is no information
inside the ring pertaining to the hang.
Note carefully that this will reduce the amount of information stored in
the error state - any ring without an active request will not be
recorded.
Signed-off-by: Chris Wilson
Reviewed-by: Dave Gordon
---
drivers/gpu/drm/i915/i915_gpu_error.c | 28
1 file changed, 8 insertions(+), 20 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_gpu_error.c
b/drivers/gpu/drm/i915/i915_gpu_error.c
index 3a46a84fe3e3..1be63590a7fe 100644
--- a/drivers/gpu/drm/i915/i915_gpu_error.c
+++ b/drivers/gpu/drm/i915/i915_gpu_error.c
@@ -1077,7 +1077,6 @@ static void i915_gem_record_rings(struct drm_i915_private
*dev_priv,
for (i = 0; i < I915_NUM_ENGINES; i++) {
struct intel_engine_cs *engine = &dev_priv->engine[i];
- struct intel_ringbuffer *rbuf;
error->ring[i].pid = -1;
@@ -1092,6 +1091,7 @@ static void i915_gem_record_rings(struct drm_i915_private
*dev_priv,
request = i915_gem_find_active_request(engine);
if (request) {
struct i915_address_space *vm;
+ struct intel_ringbuffer *rb;
vm = request->ctx && request->ctx->ppgtt ?
&request->ctx->ppgtt->base :
@@ -1122,26 +1122,14 @@ static void i915_gem_record_rings(struct
drm_i915_private *dev_priv,
}
rcu_read_unlock();
}
- }
- if (i915.enable_execlists) {
- /* TODO: This is only a small fix to keep basic error
-* capture working, but we need to add more information
-* for it to be useful (e.g. dump the context being
-* executed).
-*/
- if (request)
- rbuf = request->ctx->engine[engine->id].ringbuf;
- else
- rbuf =
dev_priv->kernel_context->engine[engine->id].ringbuf;
- } else
- rbuf = engine->buffer;
-
- error->ring[i].cpu_ring_head = rbuf->head;
- error->ring[i].cpu_ring_tail = rbuf->tail;
-
- error->ring[i].ringbuffer =
- i915_error_ggtt_object_create(dev_priv, rbuf->obj);
+ rb = request->ringbuf;
+ error->ring[i].cpu_ring_head = rb->head;
+ error->ring[i].cpu_ring_tail = rb->tail;
+ error->ring[i].ringbuffer =
+ i915_error_ggtt_object_create(dev_priv,
+ rb->obj);
+ }
error->ring[i].hws_page =
i915_error_ggtt_object_create(dev_priv,
--
2.8.1
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[Intel-gfx] [CI 6/9] drm/i915: Flush the RPS bottom-half when the GPU idles
Make sure that the RPS bottom-half is flushed before we set the idle
frequency when we decide the GPU is idle. This should prevent any races
with the bottom-half and setting the idle frequency, and ensures that
the bottom-half is bounded by the GPU's rpm reference taken for when it
is active (i.e. between gen6_rps_busy() and gen6_rps_idle()).
v2: Avoid recursively using the i915->wq - RPS does not touch the
struct_mutex so has no place being on the ordered i915->wq.
v3: Enable/disable interrupts for RPS busy/idle in order to prevent
further HW access from RPS outside of the wakeref.
Signed-off-by: Chris Wilson
Cc: Imre Deak
Cc: Jesse Barnes
References: https://bugs.freedesktop.org/show_bug.cgi?id=89728
Reviewed-by: Michał Winiarski
---
drivers/gpu/drm/i915/i915_drv.c | 3 ---
drivers/gpu/drm/i915/i915_irq.c | 32
drivers/gpu/drm/i915/intel_pm.c | 11 ++-
3 files changed, 22 insertions(+), 24 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index 2b6494b19869..40521a3e8b8f 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -2737,7 +2737,6 @@ static int intel_runtime_suspend(struct device *device)
intel_guc_suspend(dev);
- intel_suspend_gt_powersave(dev_priv);
intel_runtime_pm_disable_interrupts(dev_priv);
ret = 0;
@@ -2852,8 +2851,6 @@ static int intel_runtime_resume(struct device *device)
if (!IS_VALLEYVIEW(dev_priv) && !IS_CHERRYVIEW(dev_priv))
intel_hpd_init(dev_priv);
- intel_enable_gt_powersave(dev_priv);
-
enable_rpm_wakeref_asserts(dev_priv);
if (ret)
diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index 80d162acda1b..f0535df41dfd 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -351,9 +351,8 @@ void gen6_reset_rps_interrupts(struct drm_i915_private
*dev_priv)
void gen6_enable_rps_interrupts(struct drm_i915_private *dev_priv)
{
spin_lock_irq(&dev_priv->irq_lock);
-
- WARN_ON(dev_priv->rps.pm_iir);
- WARN_ON(I915_READ(gen6_pm_iir(dev_priv)) & dev_priv->pm_rps_events);
+ WARN_ON_ONCE(dev_priv->rps.pm_iir);
+ WARN_ON_ONCE(I915_READ(gen6_pm_iir(dev_priv)) &
dev_priv->pm_rps_events);
dev_priv->rps.interrupts_enabled = true;
I915_WRITE(gen6_pm_ier(dev_priv), I915_READ(gen6_pm_ier(dev_priv)) |
dev_priv->pm_rps_events);
@@ -371,11 +370,6 @@ void gen6_disable_rps_interrupts(struct drm_i915_private
*dev_priv)
{
spin_lock_irq(&dev_priv->irq_lock);
dev_priv->rps.interrupts_enabled = false;
- spin_unlock_irq(&dev_priv->irq_lock);
-
- cancel_work_sync(&dev_priv->rps.work);
-
- spin_lock_irq(&dev_priv->irq_lock);
I915_WRITE(GEN6_PMINTRMSK, gen6_sanitize_rps_pm_mask(dev_priv, ~0));
@@ -384,8 +378,15 @@ void gen6_disable_rps_interrupts(struct drm_i915_private
*dev_priv)
~dev_priv->pm_rps_events);
spin_unlock_irq(&dev_priv->irq_lock);
-
synchronize_irq(dev_priv->dev->irq);
+
+ /* Now that we will not be generating any more work, flush any
+* outsanding tasks. As we are called on the RPS idle path,
+* we will reset the GPU to minimum frequencies, so the current
+* state of the worker can be discarded.
+*/
+ cancel_work_sync(&dev_priv->rps.work);
+ gen6_reset_rps_interrupts(dev_priv);
}
/**
@@ -1082,13 +1083,6 @@ static void gen6_pm_rps_work(struct work_struct *work)
return;
}
- /*
-* The RPS work is synced during runtime suspend, we don't require a
-* wakeref. TODO: instead of disabling the asserts make sure that we
-* always hold an RPM reference while the work is running.
-*/
- DISABLE_RPM_WAKEREF_ASSERTS(dev_priv);
-
pm_iir = dev_priv->rps.pm_iir;
dev_priv->rps.pm_iir = 0;
/* Make sure not to corrupt PMIMR state used by ringbuffer on GEN6 */
@@ -1101,7 +1095,7 @@ static void gen6_pm_rps_work(struct work_struct *work)
WARN_ON(pm_iir & ~dev_priv->pm_rps_events);
if ((pm_iir & dev_priv->pm_rps_events) == 0 && !client_boost)
- goto out;
+ return;
mutex_lock(&dev_priv->rps.hw_lock);
@@ -1156,8 +1150,6 @@ static void gen6_pm_rps_work(struct work_struct *work)
intel_set_rps(dev_priv, new_delay);
mutex_unlock(&dev_priv->rps.hw_lock);
-out:
- ENABLE_RPM_WAKEREF_ASSERTS(dev_priv);
}
@@ -1597,7 +1589,7 @@ static void gen6_rps_irq_handler(struct drm_i915_private
*dev_priv, u32 pm_iir)
gen6_disable_pm_irq(dev_priv, pm_iir & dev_priv->pm_rps_events);
if (dev_priv->rps.interrupts_enabled) {
dev_priv->rps.pm_iir |= pm_iir &
dev_priv->pm_rps_events;
- queue_work(dev_p
[Intel-gfx] [CI 9/9] drm/i915: Allow userspace to request no-error-capture upon GPU hangs
igt likes to inject GPU hangs into its command streams. However, as we
expect these hangs, we don't actually want them recorded in the dmesg
output or stored in the i915_error_state (usually). To accommodate this
allow userspace to set a flag on the context that any hang emanating
from that context will not be recorded. We still do the error capture
(otherwise how do we find the guilty context and know its intent?) as
part of the reason for random GPU hang injection is to exercise the race
conditions between the error capture and normal execution.
v2: Split out the request->ringbuf error capture changes.
v3: Move the flag defines next to the intel_context->flags definition
Signed-off-by: Chris Wilson
Acked-by: Daniel Vetter
Reviewed-by: Dave Gordon
---
drivers/gpu/drm/i915/i915_drv.h | 4 +++-
drivers/gpu/drm/i915/i915_gem_context.c | 13 +
drivers/gpu/drm/i915/i915_gpu_error.c | 20
include/uapi/drm/i915_drm.h | 1 +
4 files changed, 29 insertions(+), 9 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 488891853cb5..251a08d8808d 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -475,6 +475,7 @@ struct drm_i915_error_state {
struct timeval time;
char error_msg[128];
+ bool simulated;
int iommu;
u32 reset_count;
u32 suspend_count;
@@ -875,9 +876,10 @@ struct i915_gem_context {
/* Unique identifier for this context, used by the hw for tracking */
unsigned long flags;
+#define CONTEXT_NO_ZEROMAP BIT(0)
+#define CONTEXT_NO_ERROR_CAPTURE BIT(1)
unsigned hw_id;
u32 user_handle;
-#define CONTEXT_NO_ZEROMAP (1<<0)
u32 ggtt_alignment;
diff --git a/drivers/gpu/drm/i915/i915_gem_context.c
b/drivers/gpu/drm/i915/i915_gem_context.c
index 3a6594b70900..8e952b1a31b3 100644
--- a/drivers/gpu/drm/i915/i915_gem_context.c
+++ b/drivers/gpu/drm/i915/i915_gem_context.c
@@ -1026,6 +1026,9 @@ int i915_gem_context_getparam_ioctl(struct drm_device
*dev, void *data,
else
args->value = to_i915(dev)->ggtt.base.total;
break;
+ case I915_CONTEXT_PARAM_NO_ERROR_CAPTURE:
+ args->value = !!(ctx->flags & CONTEXT_NO_ERROR_CAPTURE);
+ break;
default:
ret = -EINVAL;
break;
@@ -1071,6 +1074,16 @@ int i915_gem_context_setparam_ioctl(struct drm_device
*dev, void *data,
ctx->flags |= args->value ? CONTEXT_NO_ZEROMAP : 0;
}
break;
+ case I915_CONTEXT_PARAM_NO_ERROR_CAPTURE:
+ if (args->size) {
+ ret = -EINVAL;
+ } else {
+ if (args->value)
+ ctx->flags |= CONTEXT_NO_ERROR_CAPTURE;
+ else
+ ctx->flags &= ~CONTEXT_NO_ERROR_CAPTURE;
+ }
+ break;
default:
ret = -EINVAL;
break;
diff --git a/drivers/gpu/drm/i915/i915_gpu_error.c
b/drivers/gpu/drm/i915/i915_gpu_error.c
index 1be63590a7fe..c6e05cccbedf 100644
--- a/drivers/gpu/drm/i915/i915_gpu_error.c
+++ b/drivers/gpu/drm/i915/i915_gpu_error.c
@@ -1093,9 +1093,8 @@ static void i915_gem_record_rings(struct drm_i915_private
*dev_priv,
struct i915_address_space *vm;
struct intel_ringbuffer *rb;
- vm = request->ctx && request->ctx->ppgtt ?
- &request->ctx->ppgtt->base :
- &ggtt->base;
+ vm = request->ctx->ppgtt ?
+ &request->ctx->ppgtt->base : &ggtt->base;
/* We need to copy these to an anonymous buffer
* as the simplest method to avoid being overwritten
@@ -1123,6 +1122,9 @@ static void i915_gem_record_rings(struct drm_i915_private
*dev_priv,
rcu_read_unlock();
}
+ error->simulated |=
+ request->ctx->flags & CONTEXT_NO_ERROR_CAPTURE;
+
rb = request->ringbuf;
error->ring[i].cpu_ring_head = rb->head;
error->ring[i].cpu_ring_tail = rb->tail;
@@ -1422,12 +1424,14 @@ void i915_capture_error_state(struct drm_i915_private
*dev_priv,
i915_error_capture_msg(dev_priv, error, engine_mask, error_msg);
DRM_INFO("%s\n", error->error_msg);
- spin_lock_irqsave(&dev_priv->gpu_error.lock, flags);
- if (dev_priv->gpu_error.first_error == NULL) {
- dev_priv->gpu_error.first_error = error;
- error = NULL;
+ if (!error->simulated) {
+ spin_lock_irqsave(&dev_priv-
[Intel-gfx] ✗ Ro.CI.BAT: warning for series starting with [CI,1/9] drm/i915: Only start retire worker when idle
== Series Details == Series: series starting with [CI,1/9] drm/i915: Only start retire worker when idle URL : https://patchwork.freedesktop.org/series/9446/ State : warning == Summary == Series 9446v1 Series without cover letter http://patchwork.freedesktop.org/api/1.0/series/9446/revisions/1/mbox Test gem_exec_flush: Subgroup basic-batch-kernel-default-uc: dmesg-fail -> PASS (fi-skl-i5-6260u) Test kms_pipe_crc_basic: Subgroup hang-read-crc-pipe-a: skip -> PASS (fi-skl-i5-6260u) Subgroup nonblocking-crc-pipe-b-frame-sequence: pass -> SKIP (fi-skl-i5-6260u) Test prime_busy: Subgroup basic-after-default: dmesg-fail -> FAIL (fi-skl-i5-6260u) Subgroup basic-before-default: dmesg-fail -> FAIL (fi-skl-i5-6260u) fi-kbl-qkkr total:231 pass:160 dwarn:29 dfail:1 fail:2 skip:39 fi-skl-i5-6260u total:231 pass:203 dwarn:0 dfail:0 fail:2 skip:26 fi-skl-i7-6700k total:231 pass:190 dwarn:0 dfail:0 fail:2 skip:39 fi-snb-i7-2600 total:231 pass:176 dwarn:0 dfail:0 fail:2 skip:53 ro-bdw-i5-5250u total:229 pass:204 dwarn:1 dfail:1 fail:0 skip:23 ro-bdw-i7-5557U total:229 pass:204 dwarn:1 dfail:1 fail:0 skip:23 ro-bdw-i7-5600u total:229 pass:190 dwarn:0 dfail:1 fail:0 skip:38 ro-byt-n2820 total:229 pass:180 dwarn:0 dfail:1 fail:3 skip:45 ro-hsw-i3-4010u total:229 pass:197 dwarn:0 dfail:1 fail:0 skip:31 ro-hsw-i7-4770r total:229 pass:197 dwarn:0 dfail:1 fail:0 skip:31 ro-ilk-i7-620lm total:229 pass:157 dwarn:0 dfail:1 fail:1 skip:70 ro-ilk1-i5-650 total:224 pass:157 dwarn:0 dfail:1 fail:1 skip:65 ro-ivb-i7-3770 total:229 pass:188 dwarn:0 dfail:1 fail:0 skip:40 ro-skl3-i5-6260u total:229 pass:208 dwarn:1 dfail:1 fail:0 skip:19 ro-snb-i7-2620M total:229 pass:179 dwarn:0 dfail:1 fail:1 skip:48 ro-bsw-n3050 failed to connect after reboot Results at /archive/results/CI_IGT_test/RO_Patchwork_1391/ 2fe5da8 drm-intel-nightly: 2016y-07m-02d-18h-31m-39s UTC integration manifest 9ea3c9e drm/i915: Allow userspace to request no-error-capture upon GPU hangs 3effc19 drm/i915: Record the ringbuffer associated with the request 653b882 drm/i915: Remove stop-rings debugfs interface 61ec7c4 drm/i915: Flush the RPS bottom-half when the GPU idles 8c45419 drm/i915: Add background commentary to "waitboosting" 0f01c45 drm/i915: Restore waitboost credit to the synchronous waiter daa0a6c drm/i915: Remove redundant queue_delayed_work() from throttle ioctl a074f36 drm/i915: Do not keep postponing the idle-work c13bfcc drm/i915: Only start retire worker when idle ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 2/4] drm/i915: Remove superfluous powersave work flushing
Instead of flushing the outstanding enabling, remember the requested
frequency to apply when the powersave work runs.
Signed-off-by: Chris Wilson
Cc: Ville Syrjälä
---
drivers/gpu/drm/i915/i915_debugfs.c | 30 ++
drivers/gpu/drm/i915/i915_sysfs.c | 42 +++--
2 files changed, 10 insertions(+), 62 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_debugfs.c
b/drivers/gpu/drm/i915/i915_debugfs.c
index e4409ddc60e5..7c4a60b87eb5 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -1205,8 +1205,6 @@ static int i915_frequency_info(struct seq_file *m, void
*unused)
intel_runtime_pm_get(dev_priv);
- flush_delayed_work(&dev_priv->rps.delayed_resume_work);
-
if (IS_GEN5(dev)) {
u16 rgvswctl = I915_READ16(MEMSWCTL);
u16 rgvstat = I915_READ16(MEMSTAT_ILK);
@@ -1896,8 +1894,6 @@ static int i915_ring_freq_table(struct seq_file *m, void
*unused)
intel_runtime_pm_get(dev_priv);
- flush_delayed_work(&dev_priv->rps.delayed_resume_work);
-
ret = mutex_lock_interruptible(&dev_priv->rps.hw_lock);
if (ret)
goto out;
@@ -4957,20 +4953,11 @@ i915_max_freq_get(void *data, u64 *val)
{
struct drm_device *dev = data;
struct drm_i915_private *dev_priv = dev->dev_private;
- int ret;
if (INTEL_INFO(dev)->gen < 6)
return -ENODEV;
- flush_delayed_work(&dev_priv->rps.delayed_resume_work);
-
- ret = mutex_lock_interruptible(&dev_priv->rps.hw_lock);
- if (ret)
- return ret;
-
*val = intel_gpu_freq(dev_priv, dev_priv->rps.max_freq_softlimit);
- mutex_unlock(&dev_priv->rps.hw_lock);
-
return 0;
}
@@ -4985,8 +4972,6 @@ i915_max_freq_set(void *data, u64 val)
if (INTEL_INFO(dev)->gen < 6)
return -ENODEV;
- flush_delayed_work(&dev_priv->rps.delayed_resume_work);
-
DRM_DEBUG_DRIVER("Manually setting max freq to %llu\n", val);
ret = mutex_lock_interruptible(&dev_priv->rps.hw_lock);
@@ -5024,20 +5009,11 @@ i915_min_freq_get(void *data, u64 *val)
{
struct drm_device *dev = data;
struct drm_i915_private *dev_priv = dev->dev_private;
- int ret;
- if (INTEL_INFO(dev)->gen < 6)
+ if (INTEL_GEN(dev_priv) < 6)
return -ENODEV;
- flush_delayed_work(&dev_priv->rps.delayed_resume_work);
-
- ret = mutex_lock_interruptible(&dev_priv->rps.hw_lock);
- if (ret)
- return ret;
-
*val = intel_gpu_freq(dev_priv, dev_priv->rps.min_freq_softlimit);
- mutex_unlock(&dev_priv->rps.hw_lock);
-
return 0;
}
@@ -5049,11 +5025,9 @@ i915_min_freq_set(void *data, u64 val)
u32 hw_max, hw_min;
int ret;
- if (INTEL_INFO(dev)->gen < 6)
+ if (INTEL_GEN(dev_priv) < 6)
return -ENODEV;
- flush_delayed_work(&dev_priv->rps.delayed_resume_work);
-
DRM_DEBUG_DRIVER("Manually setting min freq to %llu\n", val);
ret = mutex_lock_interruptible(&dev_priv->rps.hw_lock);
diff --git a/drivers/gpu/drm/i915/i915_sysfs.c
b/drivers/gpu/drm/i915/i915_sysfs.c
index a6e90fe05a1e..915e97cdc4d5 100644
--- a/drivers/gpu/drm/i915/i915_sysfs.c
+++ b/drivers/gpu/drm/i915/i915_sysfs.c
@@ -271,8 +271,6 @@ static ssize_t gt_act_freq_mhz_show(struct device *kdev,
struct drm_i915_private *dev_priv = dev->dev_private;
int ret;
- flush_delayed_work(&dev_priv->rps.delayed_resume_work);
-
intel_runtime_pm_get(dev_priv);
mutex_lock(&dev_priv->rps.hw_lock);
@@ -303,19 +301,9 @@ static ssize_t gt_cur_freq_mhz_show(struct device *kdev,
struct drm_minor *minor = dev_to_drm_minor(kdev);
struct drm_device *dev = minor->dev;
struct drm_i915_private *dev_priv = dev->dev_private;
- int ret;
- flush_delayed_work(&dev_priv->rps.delayed_resume_work);
-
- intel_runtime_pm_get(dev_priv);
-
- mutex_lock(&dev_priv->rps.hw_lock);
- ret = intel_gpu_freq(dev_priv, dev_priv->rps.cur_freq);
- mutex_unlock(&dev_priv->rps.hw_lock);
-
- intel_runtime_pm_put(dev_priv);
-
- return snprintf(buf, PAGE_SIZE, "%d\n", ret);
+ return snprintf(buf, PAGE_SIZE, "%d\n",
+ intel_gpu_freq(dev_priv, dev_priv->rps.cur_freq));
}
static ssize_t vlv_rpe_freq_mhz_show(struct device *kdev,
@@ -335,15 +323,10 @@ static ssize_t gt_max_freq_mhz_show(struct device *kdev,
struct device_attribute
struct drm_minor *minor = dev_to_drm_minor(kdev);
struct drm_device *dev = minor->dev;
struct drm_i915_private *dev_priv = dev->dev_private;
- int ret;
-
- flush_delayed_work(&dev_priv->rps.delayed_resume_work);
- mutex_lock(&dev_priv->rps.hw_lock);
- ret = intel_gpu_freq(dev_priv, dev_priv->rps.max_freq_softlimit);
- mutex_unlock(
[Intel-gfx] [PATCH 4/4] drm/i915: Remove temporary RPM wakeref assert disables
Now that the last couple of hacks have been removed from the runtime powermanagement users, we can fully enable the asserts. Signed-off-by: Chris Wilson --- drivers/gpu/drm/i915/intel_drv.h | 7 --- 1 file changed, 7 deletions(-) diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h index 094426c69fc5..c45cb0f3ea60 100644 --- a/drivers/gpu/drm/i915/intel_drv.h +++ b/drivers/gpu/drm/i915/intel_drv.h @@ -1654,13 +1654,6 @@ enable_rpm_wakeref_asserts(struct drm_i915_private *dev_priv) atomic_dec(&dev_priv->pm.wakeref_count); } -/* TODO: convert users of these to rely instead on proper RPM refcounting */ -#define DISABLE_RPM_WAKEREF_ASSERTS(dev_priv) \ - disable_rpm_wakeref_asserts(dev_priv) - -#define ENABLE_RPM_WAKEREF_ASSERTS(dev_priv) \ - enable_rpm_wakeref_asserts(dev_priv) - void intel_runtime_pm_get(struct drm_i915_private *dev_priv); bool intel_runtime_pm_get_if_in_use(struct drm_i915_private *dev_priv); void intel_runtime_pm_get_noresume(struct drm_i915_private *dev_priv); -- 2.8.1 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 1/4] drm/i915: Preserve current RPS frequency across init
Select idle frequency during initialisation, then reset the last known
frequency when re-enabling. This allows us to preserve the user selected
frequency across resets.
v2: Stop CHV from overriding the user's choice in cherryview_enable_rps()
Signed-off-by: Chris Wilson
Cc: Ville Syrjälä
Cc: Mika Kuoppala
Reviewed-by: Mika Kuoppala
---
drivers/gpu/drm/i915/intel_pm.c | 48 +++--
1 file changed, 22 insertions(+), 26 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 814b0dfaf640..98bab11bd0b2 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -5148,6 +5148,7 @@ static void gen6_init_rps_frequencies(struct
drm_i915_private *dev_priv)
}
dev_priv->rps.idle_freq = dev_priv->rps.min_freq;
+ dev_priv->rps.cur_freq = dev_priv->rps.idle_freq;
/* Preserve min/max settings in case of re-init */
if (dev_priv->rps.max_freq_softlimit == 0)
@@ -5164,6 +5165,20 @@ static void gen6_init_rps_frequencies(struct
drm_i915_private *dev_priv)
}
}
+static void reset_rps(struct drm_i915_private *dev_priv,
+ void (*set)(struct drm_i915_private *, u8))
+{
+ u8 freq;
+
+ freq = dev_priv->rps.cur_freq;
+
+ /* force a reset */
+ dev_priv->rps.power = -1;
+ dev_priv->rps.cur_freq = -1;
+
+ set(dev_priv, freq);
+}
+
/* See the Gen9_GT_PM_Programming_Guide doc for the below */
static void gen9_enable_rps(struct drm_i915_private *dev_priv)
{
@@ -5200,8 +5215,7 @@ static void gen9_enable_rps(struct drm_i915_private
*dev_priv)
/* Leaning on the below call to gen6_set_rps to program/setup the
* Up/Down EI & threshold registers, as well as the RP_CONTROL,
* RP_INTERRUPT_LIMITS & RPNSWREQ registers */
- dev_priv->rps.power = HIGH_POWER; /* force a reset */
- gen6_set_rps(dev_priv, dev_priv->rps.idle_freq);
+ reset_rps(dev_priv, gen6_set_rps);
intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
}
@@ -5347,8 +5361,7 @@ static void gen8_enable_rps(struct drm_i915_private
*dev_priv)
/* 6: Ring frequency + overclocking (our driver does this later */
- dev_priv->rps.power = HIGH_POWER; /* force a reset */
- gen6_set_rps(dev_priv, dev_priv->rps.idle_freq);
+ reset_rps(dev_priv, gen6_set_rps);
intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
}
@@ -5441,8 +5454,7 @@ static void gen6_enable_rps(struct drm_i915_private
*dev_priv)
dev_priv->rps.max_freq = pcu_mbox & 0xff;
}
- dev_priv->rps.power = HIGH_POWER; /* force a reset */
- gen6_set_rps(dev_priv, dev_priv->rps.idle_freq);
+ reset_rps(dev_priv, gen6_set_rps);
rc6vids = 0;
ret = sandybridge_pcode_read(dev_priv, GEN6_PCODE_READ_RC6VIDS,
&rc6vids);
@@ -5806,6 +5818,7 @@ static void valleyview_init_gt_powersave(struct
drm_i915_private *dev_priv)
dev_priv->rps.min_freq);
dev_priv->rps.idle_freq = dev_priv->rps.min_freq;
+ dev_priv->rps.cur_freq = dev_priv->rps.idle_freq;
/* Preserve min/max settings in case of re-init */
if (dev_priv->rps.max_freq_softlimit == 0)
@@ -5870,6 +5883,7 @@ static void cherryview_init_gt_powersave(struct
drm_i915_private *dev_priv)
"Odd GPU freq values\n");
dev_priv->rps.idle_freq = dev_priv->rps.min_freq;
+ dev_priv->rps.cur_freq = dev_priv->rps.idle_freq;
/* Preserve min/max settings in case of re-init */
if (dev_priv->rps.max_freq_softlimit == 0)
@@ -5969,16 +5983,7 @@ static void cherryview_enable_rps(struct
drm_i915_private *dev_priv)
DRM_DEBUG_DRIVER("GPLL enabled? %s\n", yesno(val & GPLLENABLE));
DRM_DEBUG_DRIVER("GPU status: 0x%08x\n", val);
- dev_priv->rps.cur_freq = (val >> 8) & 0xff;
- DRM_DEBUG_DRIVER("current GPU freq: %d MHz (%u)\n",
-intel_gpu_freq(dev_priv, dev_priv->rps.cur_freq),
-dev_priv->rps.cur_freq);
-
- DRM_DEBUG_DRIVER("setting GPU freq to %d MHz (%u)\n",
-intel_gpu_freq(dev_priv, dev_priv->rps.idle_freq),
-dev_priv->rps.idle_freq);
-
- valleyview_set_rps(dev_priv, dev_priv->rps.idle_freq);
+ reset_rps(dev_priv, valleyview_set_rps);
intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
}
@@ -6058,16 +6063,7 @@ static void valleyview_enable_rps(struct
drm_i915_private *dev_priv)
DRM_DEBUG_DRIVER("GPLL enabled? %s\n", yesno(val & GPLLENABLE));
DRM_DEBUG_DRIVER("GPU status: 0x%08x\n", val);
- dev_priv->rps.cur_freq = (val >> 8) & 0xff;
- DRM_DEBUG_DRIVER("current GPU freq: %d MHz (%u)\n",
-intel_gpu_freq(dev_priv, dev_priv->rps.cur_freq),
-dev_priv->rps.cur_freq);
-
- DRM_DEBUG_DRIVER("setting GPU freq to %d MH
[Intel-gfx] [PATCH 3/4] drm/i915: Defer enabling rc6 til after we submit the first batch/context
Some hardware requires a valid render context before it can initiate
rc6 power gating of the GPU; the default state of the GPU is not
sufficient and may lead to undefined behaviour. The first execution of
any batch will load the "golden render state", at which point it is safe
to enable rc6. As we do not forcibly load the kernel context at resume,
we have to hook into the batch submission to be sure that the render
state is setup before enabling rc6.
However, since we don't enable powersaving until that first batch, we
queued a delayed task in order to guarantee that the batch is indeed
submitted.
v2: Rearrange intel_disable_gt_powersave() to match.
v3: Apply user specified cur_freq (or idle_freq if not set).
v4: Give in, and supply a delayed work to autoenable rc6
Signed-off-by: Chris Wilson
Cc: Mika Kuoppala
Cc: Ville Syrjälä
---
drivers/gpu/drm/i915/i915_drv.c | 5 +-
drivers/gpu/drm/i915/i915_gem.c | 1 +
drivers/gpu/drm/i915/intel_display.c | 2 +-
drivers/gpu/drm/i915/intel_drv.h | 2 +
drivers/gpu/drm/i915/intel_pm.c | 148 ---
drivers/gpu/drm/i915/intel_uncore.c | 2 +-
6 files changed, 94 insertions(+), 66 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index 7b9b6f90ca69..5a27f97684b3 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -2019,6 +2019,7 @@ static int i915_drm_resume(struct drm_device *dev)
intel_opregion_notify_adapter(dev_priv, PCI_D0);
+ intel_autoenable_gt_powersave(dev_priv);
drm_kms_helper_poll_enable(dev);
enable_rpm_wakeref_asserts(dev_priv);
@@ -2202,8 +2203,7 @@ int i915_reset(struct drm_i915_private *dev_priv)
* previous concerns that it doesn't respond well to some forms
* of re-init after reset.
*/
- if (INTEL_INFO(dev)->gen > 5)
- intel_enable_gt_powersave(dev_priv);
+ intel_autoenable_gt_powersave(dev_priv);
return 0;
@@ -2826,7 +2826,6 @@ static int intel_runtime_resume(struct device *device)
* we can do is to hope that things will still work (and disable RPM).
*/
i915_gem_init_swizzling(dev);
- gen6_update_ring_freq(dev_priv);
intel_runtime_pm_enable_interrupts(dev_priv);
diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
index 94d68f9c3a08..22df6a59421d 100644
--- a/drivers/gpu/drm/i915/i915_gem.c
+++ b/drivers/gpu/drm/i915/i915_gem.c
@@ -2851,6 +2851,7 @@ static void i915_gem_mark_busy(const struct
intel_engine_cs *engine)
intel_runtime_pm_get_noresume(dev_priv);
dev_priv->gt.awake = true;
+ intel_enable_gt_powersave(dev_priv);
i915_update_gfx_val(dev_priv);
if (INTEL_GEN(dev_priv) >= 6)
gen6_rps_busy(dev_priv);
diff --git a/drivers/gpu/drm/i915/intel_display.c
b/drivers/gpu/drm/i915/intel_display.c
index acb89e7edd61..a761f952398a 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -15553,7 +15553,6 @@ void intel_modeset_init_hw(struct drm_device *dev)
dev_priv->atomic_cdclk_freq = dev_priv->cdclk_freq;
intel_init_clock_gating(dev);
- intel_enable_gt_powersave(dev_priv);
}
/*
@@ -16348,6 +16347,7 @@ void intel_modeset_cleanup(struct drm_device *dev)
{
struct drm_i915_private *dev_priv = dev->dev_private;
+ intel_suspend_gt_powersave(dev_priv);
intel_disable_gt_powersave(dev_priv);
/*
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index 98a5be4ec8c5..094426c69fc5 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -1686,7 +1686,9 @@ void intel_gpu_ips_init(struct drm_i915_private
*dev_priv);
void intel_gpu_ips_teardown(void);
void intel_init_gt_powersave(struct drm_i915_private *dev_priv);
void intel_cleanup_gt_powersave(struct drm_i915_private *dev_priv);
+void intel_sanitize_gt_powersave(struct drm_i915_private *dev_priv);
void intel_enable_gt_powersave(struct drm_i915_private *dev_priv);
+void intel_autoenable_gt_powersave(struct drm_i915_private *dev_priv);
void intel_disable_gt_powersave(struct drm_i915_private *dev_priv);
void intel_suspend_gt_powersave(struct drm_i915_private *dev_priv);
void intel_reset_gt_powersave(struct drm_i915_private *dev_priv);
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 98bab11bd0b2..8e9ae5e86991 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -6577,13 +6577,6 @@ void intel_cleanup_gt_powersave(struct drm_i915_private
*dev_priv)
intel_runtime_pm_put(dev_priv);
}
-static void gen6_suspend_rps(struct drm_i915_private *dev_priv)
-{
- flush_delayed_work(&dev_priv->rps.delayed_resume_work);
-
- gen6_disable_rps_interrupts(dev_priv);
-}
-
/**
* intel_suspend_gt_powersave -
[Intel-gfx] [PATCH 1/3] drm/i915: Amalgamate gen6_mm_switch() and vgpu_mm_switch()
These are identical, so let's just use the same vfunc.
Signed-off-by: Chris Wilson
---
drivers/gpu/drm/i915/i915_gem_gtt.c | 29 +
1 file changed, 5 insertions(+), 24 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c
b/drivers/gpu/drm/i915/i915_gem_gtt.c
index 0bb18b88dc7a..fd249f5a82f0 100644
--- a/drivers/gpu/drm/i915/i915_gem_gtt.c
+++ b/drivers/gpu/drm/i915/i915_gem_gtt.c
@@ -1683,17 +1683,6 @@ static int hsw_mm_switch(struct i915_hw_ppgtt *ppgtt,
return 0;
}
-static int vgpu_mm_switch(struct i915_hw_ppgtt *ppgtt,
- struct drm_i915_gem_request *req)
-{
- struct intel_engine_cs *engine = req->engine;
- struct drm_i915_private *dev_priv = to_i915(ppgtt->base.dev);
-
- I915_WRITE(RING_PP_DIR_DCLV(engine), PP_DIR_DCLV_2G);
- I915_WRITE(RING_PP_DIR_BASE(engine), get_pd_offset(ppgtt));
- return 0;
-}
-
static int gen7_mm_switch(struct i915_hw_ppgtt *ppgtt,
struct drm_i915_gem_request *req)
{
@@ -1731,15 +1720,10 @@ static int gen6_mm_switch(struct i915_hw_ppgtt *ppgtt,
struct drm_i915_gem_request *req)
{
struct intel_engine_cs *engine = req->engine;
- struct drm_device *dev = ppgtt->base.dev;
- struct drm_i915_private *dev_priv = dev->dev_private;
-
+ struct drm_i915_private *dev_priv = req->i915;
I915_WRITE(RING_PP_DIR_DCLV(engine), PP_DIR_DCLV_2G);
I915_WRITE(RING_PP_DIR_BASE(engine), get_pd_offset(ppgtt));
-
- POSTING_READ(RING_PP_DIR_DCLV(engine));
-
return 0;
}
@@ -2074,18 +2058,15 @@ static int gen6_ppgtt_init(struct i915_hw_ppgtt *ppgtt)
int ret;
ppgtt->base.pte_encode = ggtt->base.pte_encode;
- if (IS_GEN6(dev)) {
+ if (intel_vgpu_active(dev_priv) || IS_GEN6(dev))
ppgtt->switch_mm = gen6_mm_switch;
- } else if (IS_HASWELL(dev)) {
+ else if (IS_HASWELL(dev))
ppgtt->switch_mm = hsw_mm_switch;
- } else if (IS_GEN7(dev)) {
+ else if (IS_GEN7(dev))
ppgtt->switch_mm = gen7_mm_switch;
- } else
+ else
BUG();
- if (intel_vgpu_active(dev_priv))
- ppgtt->switch_mm = vgpu_mm_switch;
-
ret = gen6_ppgtt_alloc(ppgtt);
if (ret)
return ret;
--
2.8.1
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 2/3] drm/i915: Clean up GPU hang message
Remove some redundant kernel messages as we deduce a hung GPU and
capture the error state.
v2: Fix "hang" vs "no progress" message whilst I was there
v3: s/snprintf/scnprintf/
Signed-off-by: Chris Wilson
Cc: Mika Kuoppala
---
drivers/gpu/drm/i915/i915_irq.c | 41 ++---
1 file changed, 26 insertions(+), 15 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index f0535df41dfd..0e0710acf7f1 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -3084,9 +3084,8 @@ static void i915_hangcheck_elapsed(struct work_struct
*work)
container_of(work, typeof(*dev_priv),
gpu_error.hangcheck_work.work);
struct intel_engine_cs *engine;
- enum intel_engine_id id;
- int busy_count = 0, rings_hung = 0;
- bool stuck[I915_NUM_ENGINES] = { 0 };
+ unsigned int hung = 0, stuck = 0;
+ int busy_count = 0;
#define BUSY 1
#define KICK 5
#define HUNG 20
@@ -3104,7 +3103,7 @@ static void i915_hangcheck_elapsed(struct work_struct
*work)
*/
intel_uncore_arm_unclaimed_mmio_detection(dev_priv);
- for_each_engine_id(engine, dev_priv, id) {
+ for_each_engine(engine, dev_priv) {
bool busy = intel_engine_has_waiter(engine);
u64 acthd;
u32 seqno;
@@ -3167,10 +3166,15 @@ static void i915_hangcheck_elapsed(struct work_struct
*work)
break;
case HANGCHECK_HUNG:
engine->hangcheck.score += HUNG;
- stuck[id] = true;
break;
}
}
+
+ if (engine->hangcheck.score >=
HANGCHECK_SCORE_RING_HUNG) {
+ hung |= intel_engine_flag(engine);
+ if (engine->hangcheck.action != HANGCHECK_HUNG)
+ stuck |= intel_engine_flag(engine);
+ }
} else {
engine->hangcheck.action = HANGCHECK_ACTIVE;
@@ -3195,17 +3199,24 @@ static void i915_hangcheck_elapsed(struct work_struct
*work)
busy_count += busy;
}
- for_each_engine_id(engine, dev_priv, id) {
- if (engine->hangcheck.score >= HANGCHECK_SCORE_RING_HUNG) {
- DRM_INFO("%s on %s\n",
-stuck[id] ? "stuck" : "no progress",
-engine->name);
- rings_hung |= intel_engine_flag(engine);
- }
- }
+ if (hung) {
+ char msg[80];
+ int len;
- if (rings_hung)
- i915_handle_error(dev_priv, rings_hung, "Engine(s) hung");
+ /* If some rings hung but others were still busy, only
+* blame the hanging rings in the synopsis.
+*/
+ if (stuck != hung)
+ hung &= ~stuck;
+ len = scnprintf(msg, sizeof(msg),
+ "%s on ", stuck == hung ? "No progress" :
"Hang");
+ for_each_engine_masked(engine, dev_priv, hung)
+ len += scnprintf(msg + len, sizeof(msg) - len,
+"%s, ", engine->name);
+ msg[len-2] = '\0';
+
+ return i915_handle_error(dev_priv, hung, msg);
+ }
/* Reset timer in case GPU hangs without another request being added */
if (busy_count)
--
2.8.1
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 04/13] drm/i915: Disable waitboosting for fence_wait()
We want to restrict waitboosting to known process contexts, where we can
track which clients are receiving waitboosts and prevent excessive power
wasting. For fence_wait() we do not have any client tracking and so that
leaves it open to abuse.
Signed-off-by: Chris Wilson
---
drivers/gpu/drm/i915/i915_gem_request.c | 7 ---
drivers/gpu/drm/i915/i915_gem_request.h | 1 +
2 files changed, 5 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_gem_request.c
b/drivers/gpu/drm/i915/i915_gem_request.c
index 3c4b1af42a46..dcb98945c9fc 100644
--- a/drivers/gpu/drm/i915/i915_gem_request.c
+++ b/drivers/gpu/drm/i915/i915_gem_request.c
@@ -76,7 +76,7 @@ static signed long i915_fence_wait(struct fence *fence,
ret = __i915_wait_request(to_i915_request(fence),
interruptible, timeout,
- NULL);
+ NO_WAITBOOST);
if (ret == -ETIME)
return 0;
@@ -647,7 +647,7 @@ int __i915_wait_request(struct drm_i915_gem_request *req,
* forcing the clocks too high for the whole system, we only allow
* each client to waitboost once in a busy period.
*/
- if (INTEL_GEN(req->i915) >= 6)
+ if (!IS_ERR(rps) && INTEL_GEN(req->i915) >= 6)
gen6_rps_boost(req->i915, rps, req->emitted_jiffies);
/* Optimistic spin for the next ~jiffie before touching IRQs */
@@ -727,7 +727,8 @@ complete:
*timeout = 0;
}
- if (rps && req->fence.seqno == req->engine->last_submitted_seqno) {
+ if (!IS_ERR_OR_NULL(rps) &&
+ req->fence.seqno == req->engine->last_submitted_seqno) {
/* The GPU is now idle and this client has stalled.
* Since no other client has submitted a request in the
* meantime, assume that this client is the only one
diff --git a/drivers/gpu/drm/i915/i915_gem_request.h
b/drivers/gpu/drm/i915/i915_gem_request.h
index 6f2c820785f3..f7f497a07893 100644
--- a/drivers/gpu/drm/i915/i915_gem_request.h
+++ b/drivers/gpu/drm/i915/i915_gem_request.h
@@ -206,6 +206,7 @@ void __i915_add_request(struct drm_i915_gem_request *req,
__i915_add_request(req, NULL, false)
struct intel_rps_client;
+#define NO_WAITBOOST ERR_PTR(-1)
int __i915_wait_request(struct drm_i915_gem_request *req,
bool interruptible,
--
2.8.1
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 3/3] drm/i915: Skip capturing an error state if we already have one
As we only ever keep the first error state around, we can avoid some
work that can be quite intrusive if we don't record the error the second
time around. This does move the race whereby the user could discard one
error state as the second is being captured, but that race exists in the
current code and we hope that recapturing error state is only done for
debugging.
Note that as we discard the error state for simulated errors, igt that
exercise error capture continue to function.
Signed-off-by: Chris Wilson
---
drivers/gpu/drm/i915/i915_gpu_error.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_gpu_error.c
b/drivers/gpu/drm/i915/i915_gpu_error.c
index c6e05cccbedf..3a43b434c92e 100644
--- a/drivers/gpu/drm/i915/i915_gpu_error.c
+++ b/drivers/gpu/drm/i915/i915_gpu_error.c
@@ -1401,6 +1401,9 @@ void i915_capture_error_state(struct drm_i915_private
*dev_priv,
struct drm_i915_error_state *error;
unsigned long flags;
+ if (READ_ONCE(dev_priv->gpu_error.first_error))
+ return;
+
/* Account for pipe specific data like PIPE*STAT */
error = kzalloc(sizeof(*error), GFP_ATOMIC);
if (!error) {
--
2.8.1
___
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https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 05/13] drm/i915: Disable waitboosting for mmioflips/semaphores
Since commit a6f766f39751 ("drm/i915: Limit ring synchronisation (sw
sempahores) RPS boosts") and commit bcafc4e38b6a ("drm/i915: Limit mmio
flip RPS boosts") we have limited the waitboosting for semaphores and
flips. Ideally we do not want to boost in either of these instances as no
consumer is waiting upon the results. With the introduction of NO_WAITBOOST
in the previous patch, we can finally disable these needless boosts.
Signed-off-by: Chris Wilson
---
drivers/gpu/drm/i915/i915_debugfs.c | 8 +---
drivers/gpu/drm/i915/i915_drv.h | 2 --
drivers/gpu/drm/i915/i915_gem.c | 2 +-
drivers/gpu/drm/i915/intel_display.c | 2 +-
drivers/gpu/drm/i915/intel_pm.c | 2 --
5 files changed, 3 insertions(+), 13 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_debugfs.c
b/drivers/gpu/drm/i915/i915_debugfs.c
index ec0162585238..8b12dca5a2f0 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -2463,13 +2463,7 @@ static int i915_rps_boost_info(struct seq_file *m, void
*data)
list_empty(&file_priv->rps.link) ? "" : ", active");
rcu_read_unlock();
}
- seq_printf(m, "Semaphore boosts: %d%s\n",
- dev_priv->rps.semaphores.boosts,
- list_empty(&dev_priv->rps.semaphores.link) ? "" : ",
active");
- seq_printf(m, "MMIO flip boosts: %d%s\n",
- dev_priv->rps.mmioflips.boosts,
- list_empty(&dev_priv->rps.mmioflips.link) ? "" : ", active");
- seq_printf(m, "Kernel boosts: %d\n", dev_priv->rps.boosts);
+ seq_printf(m, "Kernel (anonymous) boosts: %d\n", dev_priv->rps.boosts);
spin_unlock(&dev_priv->rps.client_lock);
mutex_unlock(&dev->filelist_mutex);
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 1726146d8be3..733da62ed179 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -1185,8 +1185,6 @@ struct intel_gen6_power_mgmt {
struct delayed_work delayed_resume_work;
unsigned boosts;
- struct intel_rps_client semaphores, mmioflips;
-
/* manual wa residency calculations */
struct intel_rps_ei up_ei, down_ei;
diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
index f0acc06e9567..2a2c4001dc07 100644
--- a/drivers/gpu/drm/i915/i915_gem.c
+++ b/drivers/gpu/drm/i915/i915_gem.c
@@ -2840,7 +2840,7 @@ __i915_gem_object_sync(struct drm_i915_gem_object *obj,
ret = __i915_wait_request(from_req,
i915->mm.interruptible,
NULL,
- &i915->rps.semaphores);
+ NO_WAITBOOST);
if (ret)
return ret;
diff --git a/drivers/gpu/drm/i915/intel_display.c
b/drivers/gpu/drm/i915/intel_display.c
index a761f952398a..d10af1566e70 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -11560,7 +11560,7 @@ static void intel_mmio_flip_work_func(struct
work_struct *w)
if (work->flip_queued_req)
WARN_ON(__i915_wait_request(work->flip_queued_req,
false, NULL,
- &dev_priv->rps.mmioflips));
+ NO_WAITBOOST));
/* For framebuffer backed by dmabuf, wait for fence */
resv = i915_gem_object_get_dmabuf_resv(obj);
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 8e9ae5e86991..0bccd40e6b27 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -7842,8 +7842,6 @@ void intel_pm_setup(struct drm_device *dev)
INIT_DELAYED_WORK(&dev_priv->rps.delayed_resume_work,
__intel_autoenable_gt_powersave);
INIT_LIST_HEAD(&dev_priv->rps.clients);
- INIT_LIST_HEAD(&dev_priv->rps.semaphores.link);
- INIT_LIST_HEAD(&dev_priv->rps.mmioflips.link);
dev_priv->pm.suspended = false;
atomic_set(&dev_priv->pm.wakeref_count, 0);
--
2.8.1
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 11/13] drm/i915: Wrap drm_gem_object_reference in i915_gem_object_get
Signed-off-by: Chris Wilson
---
drivers/gpu/drm/i915/i915_drv.h| 11 +++
drivers/gpu/drm/i915/i915_gem.c| 4 ++--
drivers/gpu/drm/i915/i915_gem_dmabuf.c | 3 +--
drivers/gpu/drm/i915/i915_gem_evict.c | 2 +-
drivers/gpu/drm/i915/i915_gem_execbuffer.c | 4 ++--
drivers/gpu/drm/i915/i915_gem_shrinker.c | 2 +-
drivers/gpu/drm/i915/i915_gem_userptr.c| 3 +--
drivers/gpu/drm/i915/intel_display.c | 3 +--
8 files changed, 20 insertions(+), 12 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index bdcc2e1fe240..0aad09981da0 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -2298,6 +2298,17 @@ __deprecated
extern struct drm_gem_object *
drm_gem_object_lookup(struct drm_file *file, u32 handle);
+__attribute__((nonnull))
+static inline struct drm_i915_gem_object *
+i915_gem_object_get(struct drm_i915_gem_object *obj)
+{
+ drm_gem_object_reference(&obj->base);
+ return obj;
+}
+
+__deprecated
+extern void drm_gem_object_reference(struct drm_gem_object *);
+
static inline bool
i915_gem_object_has_struct_page(const struct drm_i915_gem_object *obj)
{
diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
index 8f9031560ce4..b7b7f92c9a32 100644
--- a/drivers/gpu/drm/i915/i915_gem.c
+++ b/drivers/gpu/drm/i915/i915_gem.c
@@ -287,7 +287,7 @@ drop_pages(struct drm_i915_gem_object *obj)
struct i915_vma *vma, *next;
int ret;
- drm_gem_object_reference(&obj->base);
+ i915_gem_object_get(obj);
list_for_each_entry_safe(vma, next, &obj->vma_list, obj_link)
if (i915_vma_unbind(vma))
break;
@@ -2349,7 +2349,7 @@ void i915_vma_move_to_active(struct i915_vma *vma,
/* Add a reference if we're newly entering the active list. */
if (obj->active == 0)
- drm_gem_object_reference(&obj->base);
+ i915_gem_object_get(obj);
obj->active |= intel_engine_flag(engine);
list_move_tail(&obj->engine_list[engine->id], &engine->active_list);
diff --git a/drivers/gpu/drm/i915/i915_gem_dmabuf.c
b/drivers/gpu/drm/i915/i915_gem_dmabuf.c
index 12e360cc3377..4c23a2f217dc 100644
--- a/drivers/gpu/drm/i915/i915_gem_dmabuf.c
+++ b/drivers/gpu/drm/i915/i915_gem_dmabuf.c
@@ -312,8 +312,7 @@ struct drm_gem_object *i915_gem_prime_import(struct
drm_device *dev,
* Importing dmabuf exported from out own gem increases
* refcount on gem itself instead of f_count of dmabuf.
*/
- drm_gem_object_reference(&obj->base);
- return &obj->base;
+ return &i915_gem_object_get(obj)->base;
}
}
diff --git a/drivers/gpu/drm/i915/i915_gem_evict.c
b/drivers/gpu/drm/i915/i915_gem_evict.c
index 3c1280ec7ff6..d5777a0750f0 100644
--- a/drivers/gpu/drm/i915/i915_gem_evict.c
+++ b/drivers/gpu/drm/i915/i915_gem_evict.c
@@ -214,7 +214,7 @@ found:
exec_list);
if (drm_mm_scan_remove_block(&vma->node)) {
list_move(&vma->exec_list, &eviction_list);
- drm_gem_object_reference(&vma->obj->base);
+ i915_gem_object_get(vma->obj);
continue;
}
list_del_init(&vma->exec_list);
diff --git a/drivers/gpu/drm/i915/i915_gem_execbuffer.c
b/drivers/gpu/drm/i915/i915_gem_execbuffer.c
index 2209f1ff7e9a..e09c658e09de 100644
--- a/drivers/gpu/drm/i915/i915_gem_execbuffer.c
+++ b/drivers/gpu/drm/i915/i915_gem_execbuffer.c
@@ -126,7 +126,7 @@ eb_lookup_vmas(struct eb_vmas *eb,
goto err;
}
- drm_gem_object_reference(&obj->base);
+ i915_gem_object_get(obj);
list_add_tail(&obj->obj_exec_link, &objects);
}
spin_unlock(&file->table_lock);
@@ -1229,7 +1229,7 @@ i915_gem_execbuffer_parse(struct intel_engine_cs *engine,
vma = i915_gem_obj_to_ggtt(shadow_batch_obj);
vma->exec_entry = shadow_exec_entry;
vma->exec_entry->flags = __EXEC_OBJECT_HAS_PIN;
- drm_gem_object_reference(&shadow_batch_obj->base);
+ i915_gem_object_get(shadow_batch_obj);
list_add_tail(&vma->exec_list, &eb->vmas);
shadow_batch_obj->base.pending_read_domains = I915_GEM_DOMAIN_COMMAND;
diff --git a/drivers/gpu/drm/i915/i915_gem_shrinker.c
b/drivers/gpu/drm/i915/i915_gem_shrinker.c
index 1bf14544d8ad..416eaaece776 100644
--- a/drivers/gpu/drm/i915/i915_gem_shrinker.c
+++ b/drivers/gpu/drm/i915/i915_gem_shrinker.c
@@ -190,7 +190,7 @@ i915_gem_shrink(struct drm_i915_private *dev_priv,
if (!can_release_pages(obj))
continue;
- drm_gem_object_reference(&obj->base);
+
[Intel-gfx] [PATCH 01/13] drm/i915: Move GEM request routines to i915_gem_request.c
Migrate the request operations out of the main body of i915_gem.c and
into their own C file for easier expansion.
v2: Move __i915_add_request() across as well
Signed-off-by: Chris Wilson
---
drivers/gpu/drm/i915/Makefile | 1 +
drivers/gpu/drm/i915/i915_drv.h | 209 +-
drivers/gpu/drm/i915/i915_gem.c | 660 +--
drivers/gpu/drm/i915/i915_gem_request.c | 667
drivers/gpu/drm/i915/i915_gem_request.h | 244
5 files changed, 920 insertions(+), 861 deletions(-)
create mode 100644 drivers/gpu/drm/i915/i915_gem_request.c
create mode 100644 drivers/gpu/drm/i915/i915_gem_request.h
diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makefile
index 618293c8c9d9..e94ae31433b8 100644
--- a/drivers/gpu/drm/i915/Makefile
+++ b/drivers/gpu/drm/i915/Makefile
@@ -32,6 +32,7 @@ i915-y += i915_cmd_parser.o \
i915_gem_gtt.o \
i915_gem.o \
i915_gem_render_state.o \
+ i915_gem_request.o \
i915_gem_shrinker.o \
i915_gem_stolen.o \
i915_gem_tiling.o \
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 251a08d8808d..1726146d8be3 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -61,6 +61,7 @@
#include "i915_gem.h"
#include "i915_gem_gtt.h"
#include "i915_gem_render_state.h"
+#include "i915_gem_request.h"
#include "intel_gvt.h"
@@ -2357,171 +2358,6 @@ static inline struct scatterlist *__sg_next(struct
scatterlist *sg)
(((__iter).curr += PAGE_SIZE) < (__iter).max) || \
((__iter) = __sgt_iter(__sg_next((__iter).sgp), false), 0))
-/**
- * Request queue structure.
- *
- * The request queue allows us to note sequence numbers that have been emitted
- * and may be associated with active buffers to be retired.
- *
- * By keeping this list, we can avoid having to do questionable sequence
- * number comparisons on buffer last_read|write_seqno. It also allows an
- * emission time to be associated with the request for tracking how far ahead
- * of the GPU the submission is.
- *
- * The requests are reference counted, so upon creation they should have an
- * initial reference taken using kref_init
- */
-struct drm_i915_gem_request {
- struct kref ref;
-
- /** On Which ring this request was generated */
- struct drm_i915_private *i915;
- struct intel_engine_cs *engine;
- struct intel_signal_node signaling;
-
-/** GEM sequence number associated with the previous request,
- * when the HWS breadcrumb is equal to this the GPU is processing
- * this request.
- */
- u32 previous_seqno;
-
-/** GEM sequence number associated with this request,
- * when the HWS breadcrumb is equal or greater than this the GPU
- * has finished processing this request.
- */
- u32 seqno;
-
- /** Position in the ringbuffer of the start of the request */
- u32 head;
-
- /**
-* Position in the ringbuffer of the start of the postfix.
-* This is required to calculate the maximum available ringbuffer
-* space without overwriting the postfix.
-*/
-u32 postfix;
-
- /** Position in the ringbuffer of the end of the whole request */
- u32 tail;
-
- /** Preallocate space in the ringbuffer for the emitting the request */
- u32 reserved_space;
-
- /**
-* Context and ring buffer related to this request
-* Contexts are refcounted, so when this request is associated with a
-* context, we must increment the context's refcount, to guarantee that
-* it persists while any request is linked to it. Requests themselves
-* are also refcounted, so the request will only be freed when the last
-* reference to it is dismissed, and the code in
-* i915_gem_request_free() will then decrement the refcount on the
-* context.
-*/
- struct i915_gem_context *ctx;
- struct intel_ringbuffer *ringbuf;
-
- /**
-* Context related to the previous request.
-* As the contexts are accessed by the hardware until the switch is
-* completed to a new context, the hardware may still be writing
-* to the context object after the breadcrumb is visible. We must
-* not unpin/unbind/prune that object whilst still active and so
-* we keep the previous context pinned until the following (this)
-* request is retired.
-*/
- struct i915_gem_context *previous_context;
-
- /** Batch buffer related to this request if any (used for
- error state dump only) */
- struct drm_i915_gem_object *batch_obj;
-
- /** Time at which this request was emitted, in jiffies. */
- unsigned long emitted_jiffies;
-
- /** global list entry for this request */
-
[Intel-gfx] [PATCH 08/13] drm/i915: Rename request reference/unreference to get/put
Now that we derive requests from struct fence, swap over to its
nomenclature for references. It's shorter and more idiomatic across the
kernel.
s/i915_gem_request_reference/i915_gem_request_get/
s/i915_gem_request_unreference/i915_gem_request_put/
Signed-off-by: Chris Wilson
Reviewed-by: Daniel Vetter
---
drivers/gpu/drm/i915/i915_gem.c | 14 +++---
drivers/gpu/drm/i915/i915_gem_request.c | 2 +-
drivers/gpu/drm/i915/i915_gem_request.h | 8
drivers/gpu/drm/i915/i915_gem_userptr.c | 4 ++--
drivers/gpu/drm/i915/intel_breadcrumbs.c | 4 ++--
drivers/gpu/drm/i915/intel_display.c | 5 ++---
drivers/gpu/drm/i915/intel_lrc.c | 10 +-
drivers/gpu/drm/i915/intel_pm.c | 5 ++---
8 files changed, 25 insertions(+), 27 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
index 2a2c4001dc07..b56a3a080da4 100644
--- a/drivers/gpu/drm/i915/i915_gem.c
+++ b/drivers/gpu/drm/i915/i915_gem.c
@@ -1410,7 +1410,7 @@ i915_gem_object_wait_rendering__nonblocking(struct
drm_i915_gem_object *obj,
if (req == NULL)
return 0;
- requests[n++] = i915_gem_request_reference(req);
+ requests[n++] = i915_gem_request_get(req);
} else {
for (i = 0; i < I915_NUM_ENGINES; i++) {
struct drm_i915_gem_request *req;
@@ -1419,7 +1419,7 @@ i915_gem_object_wait_rendering__nonblocking(struct
drm_i915_gem_object *obj,
if (req == NULL)
continue;
- requests[n++] = i915_gem_request_reference(req);
+ requests[n++] = i915_gem_request_get(req);
}
}
@@ -1432,7 +1432,7 @@ i915_gem_object_wait_rendering__nonblocking(struct
drm_i915_gem_object *obj,
for (i = 0; i < n; i++) {
if (ret == 0)
i915_gem_object_retire_request(obj, requests[i]);
- i915_gem_request_unreference(requests[i]);
+ i915_gem_request_put(requests[i]);
}
return ret;
@@ -2799,7 +2799,7 @@ i915_gem_wait_ioctl(struct drm_device *dev, void *data,
struct drm_file *file)
if (obj->last_read_req[i] == NULL)
continue;
- req[n++] = i915_gem_request_reference(obj->last_read_req[i]);
+ req[n++] = i915_gem_request_get(obj->last_read_req[i]);
}
mutex_unlock(&dev->struct_mutex);
@@ -2809,7 +2809,7 @@ i915_gem_wait_ioctl(struct drm_device *dev, void *data,
struct drm_file *file)
ret = __i915_wait_request(req[i], true,
args->timeout_ns > 0 ?
&args->timeout_ns : NULL,
to_rps_client(file));
- i915_gem_request_unreference(req[i]);
+ i915_gem_request_put(req[i]);
}
return ret;
@@ -3824,14 +3824,14 @@ i915_gem_ring_throttle(struct drm_device *dev, struct
drm_file *file)
target = request;
}
if (target)
- i915_gem_request_reference(target);
+ i915_gem_request_get(target);
spin_unlock(&file_priv->mm.lock);
if (target == NULL)
return 0;
ret = __i915_wait_request(target, true, NULL, NULL);
- i915_gem_request_unreference(target);
+ i915_gem_request_put(target);
return ret;
}
diff --git a/drivers/gpu/drm/i915/i915_gem_request.c
b/drivers/gpu/drm/i915/i915_gem_request.c
index dcb98945c9fc..40adade29aad 100644
--- a/drivers/gpu/drm/i915/i915_gem_request.c
+++ b/drivers/gpu/drm/i915/i915_gem_request.c
@@ -187,7 +187,7 @@ static void i915_gem_request_retire(struct
drm_i915_gem_request *request)
}
i915_gem_context_unreference(request->ctx);
- i915_gem_request_unreference(request);
+ i915_gem_request_put(request);
}
void i915_gem_request_retire_upto(struct drm_i915_gem_request *req)
diff --git a/drivers/gpu/drm/i915/i915_gem_request.h
b/drivers/gpu/drm/i915/i915_gem_request.h
index f7f497a07893..ed3f34dfeecd 100644
--- a/drivers/gpu/drm/i915/i915_gem_request.h
+++ b/drivers/gpu/drm/i915/i915_gem_request.h
@@ -174,13 +174,13 @@ to_request(struct fence *fence)
}
static inline struct drm_i915_gem_request *
-i915_gem_request_reference(struct drm_i915_gem_request *req)
+i915_gem_request_get(struct drm_i915_gem_request *req)
{
return to_request(fence_get(&req->fence));
}
static inline void
-i915_gem_request_unreference(struct drm_i915_gem_request *req)
+i915_gem_request_put(struct drm_i915_gem_request *req)
{
fence_put(&req->fence);
}
@@ -189,10 +189,10 @@ static inline void i915_gem_request_assign(struct
drm_i915_gem_request **pdst,
struct drm_i915_gem_request *src)
{
if (src)
- i915_
[Intel-gfx] [PATCH 06/13] drm/i915: Export our request as a dma-buf fence on the reservation object
If the GEM objects being rendered with in this request have been
exported via dma-buf to a third party, hook ourselves into the dma-buf
reservation object so that the third party can serialise with our
rendering via the dma-buf fences.
Testcase: igt/prime_busy
Signed-off-by: Chris Wilson
---
drivers/gpu/drm/i915/i915_gem_dmabuf.c | 40 +++---
drivers/gpu/drm/i915/i915_gem_execbuffer.c | 30 --
2 files changed, 65 insertions(+), 5 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_gem_dmabuf.c
b/drivers/gpu/drm/i915/i915_gem_dmabuf.c
index 80bbe43a2e92..8a5f88aef6e8 100644
--- a/drivers/gpu/drm/i915/i915_gem_dmabuf.c
+++ b/drivers/gpu/drm/i915/i915_gem_dmabuf.c
@@ -23,9 +23,13 @@
* Authors:
* Dave Airlie
*/
+
+#include
+#include
+
#include
+
#include "i915_drv.h"
-#include
static struct drm_i915_gem_object *dma_buf_to_obj(struct dma_buf *buf)
{
@@ -218,25 +222,55 @@ static const struct dma_buf_ops i915_dmabuf_ops = {
.end_cpu_access = i915_gem_end_cpu_access,
};
+static void export_fences(struct drm_i915_gem_object *obj,
+ struct dma_buf *dma_buf)
+{
+ struct reservation_object *resv = dma_buf->resv;
+ struct drm_i915_gem_request *req;
+ int idx;
+
+ mutex_lock(&obj->base.dev->struct_mutex);
+
+ for (idx = 0; idx < ARRAY_SIZE(obj->last_read_req); idx++) {
+ req = obj->last_read_req[idx];
+ if (!req)
+ continue;
+
+ if (reservation_object_reserve_shared(resv) == 0)
+ reservation_object_add_shared_fence(resv, &req->fence);
+ }
+
+ req = obj->last_write_req;
+ if (req)
+ reservation_object_add_excl_fence(resv, &req->fence);
+
+ mutex_unlock(&obj->base.dev->struct_mutex);
+}
+
struct dma_buf *i915_gem_prime_export(struct drm_device *dev,
struct drm_gem_object *gem_obj, int flags)
{
struct drm_i915_gem_object *obj = to_intel_bo(gem_obj);
DEFINE_DMA_BUF_EXPORT_INFO(exp_info);
+ struct dma_buf *dma_buf;
exp_info.ops = &i915_dmabuf_ops;
exp_info.size = gem_obj->size;
exp_info.flags = flags;
exp_info.priv = gem_obj;
-
if (obj->ops->dmabuf_export) {
int ret = obj->ops->dmabuf_export(obj);
if (ret)
return ERR_PTR(ret);
}
- return dma_buf_export(&exp_info);
+ dma_buf = dma_buf_export(&exp_info);
+ if (IS_ERR(dma_buf))
+ return dma_buf;
+
+ export_fences(obj, dma_buf);
+ return dma_buf;
}
static int i915_gem_object_get_pages_dmabuf(struct drm_i915_gem_object *obj)
diff --git a/drivers/gpu/drm/i915/i915_gem_execbuffer.c
b/drivers/gpu/drm/i915/i915_gem_execbuffer.c
index 39c53d97833a..1cc4ba7e87a4 100644
--- a/drivers/gpu/drm/i915/i915_gem_execbuffer.c
+++ b/drivers/gpu/drm/i915/i915_gem_execbuffer.c
@@ -26,13 +26,17 @@
*
*/
+#include
+#include
+#include
+
#include
#include
+
#include "i915_drv.h"
+#include "i915_gem_dmabuf.h"
#include "i915_trace.h"
#include "intel_drv.h"
-#include
-#include
#define __EXEC_OBJECT_HAS_PIN (1<<31)
#define __EXEC_OBJECT_HAS_FENCE (1<<30)
@@ -1086,6 +1090,27 @@ i915_gem_validate_context(struct drm_device *dev, struct
drm_file *file,
return ctx;
}
+static void eb_export_fence(struct drm_i915_gem_object *obj,
+ struct drm_i915_gem_request *req)
+{
+ struct reservation_object *resv;
+
+ resv = i915_gem_object_get_dmabuf_resv(obj);
+ if (!resv)
+ return;
+
+ /* Ignore errors from failing to allocate the new fence, we can't
+* handle an error right now. Worst case should be missed
+* synchronisation leading to rendering corruption.
+*/
+ mutex_lock(&resv->lock.base);
+ if (obj->base.write_domain)
+ reservation_object_add_excl_fence(resv, &req->fence);
+ else if (reservation_object_reserve_shared(resv) == 0)
+ reservation_object_add_shared_fence(resv, &req->fence);
+ mutex_unlock(&resv->lock.base);
+}
+
void
i915_gem_execbuffer_move_to_active(struct list_head *vmas,
struct drm_i915_gem_request *req)
@@ -1106,6 +1131,7 @@ i915_gem_execbuffer_move_to_active(struct list_head *vmas,
obj->base.read_domains = obj->base.pending_read_domains;
i915_vma_move_to_active(vma, req);
+ eb_export_fence(obj, req);
if (obj->base.write_domain) {
i915_gem_request_assign(&obj->last_write_req, req);
--
2.8.1
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 02/13] drm/i915: Retire oldest completed request before allocating next
In order to keep the memory allocated for requests reasonably tight, try
to reuse the oldest request (so long as it is completed and has no
external references) for the next allocation.
Signed-off-by: Chris Wilson
---
drivers/gpu/drm/i915/i915_gem_request.c | 7 +++
1 file changed, 7 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_gem_request.c
b/drivers/gpu/drm/i915/i915_gem_request.c
index f4eebce97003..25fd91aad74b 100644
--- a/drivers/gpu/drm/i915/i915_gem_request.c
+++ b/drivers/gpu/drm/i915/i915_gem_request.c
@@ -226,6 +226,13 @@ __i915_gem_request_alloc(struct intel_engine_cs *engine,
if (ret)
return ret;
+ if (!list_empty(&engine->request_list)) {
+ req = list_first_entry(&engine->request_list,
+ typeof(*req), list);
+ if (i915_gem_request_completed(req))
+ i915_gem_request_retire(req);
+ }
+
req = kmem_cache_zalloc(dev_priv->requests, GFP_KERNEL);
if (!req)
return -ENOMEM;
--
2.8.1
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 12/13] drm/i915: Rename drm_gem_object_unreference in preparation for lockless free
Signed-off-by: Chris Wilson
---
drivers/gpu/drm/i915/i915_drv.h | 10 ++
drivers/gpu/drm/i915/i915_gem.c | 26 +-
drivers/gpu/drm/i915/i915_gem_batch_pool.c | 4 ++--
drivers/gpu/drm/i915/i915_gem_context.c | 4 ++--
drivers/gpu/drm/i915/i915_gem_evict.c| 7 ---
drivers/gpu/drm/i915/i915_gem_execbuffer.c | 6 +++---
drivers/gpu/drm/i915/i915_gem_render_state.c | 4 ++--
drivers/gpu/drm/i915/i915_gem_shrinker.c | 2 +-
drivers/gpu/drm/i915/i915_gem_stolen.c | 2 +-
drivers/gpu/drm/i915/i915_gem_tiling.c | 4 ++--
drivers/gpu/drm/i915/i915_gem_userptr.c | 4 ++--
drivers/gpu/drm/i915/i915_guc_submission.c | 6 +++---
drivers/gpu/drm/i915/intel_display.c | 6 +++---
drivers/gpu/drm/i915/intel_fbdev.c | 2 +-
drivers/gpu/drm/i915/intel_guc_loader.c | 8 +---
drivers/gpu/drm/i915/intel_lrc.c | 6 +++---
drivers/gpu/drm/i915/intel_overlay.c | 8
drivers/gpu/drm/i915/intel_pm.c | 2 +-
drivers/gpu/drm/i915/intel_ringbuffer.c | 14 +++---
19 files changed, 69 insertions(+), 56 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 0aad09981da0..6511056c2bc6 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -2309,6 +2309,16 @@ i915_gem_object_get(struct drm_i915_gem_object *obj)
__deprecated
extern void drm_gem_object_reference(struct drm_gem_object *);
+__attribute__((nonnull))
+static inline void
+i915_gem_object_put(struct drm_i915_gem_object *obj)
+{
+ drm_gem_object_unreference(&obj->base);
+}
+
+__deprecated
+extern void drm_gem_object_unreference(struct drm_gem_object *);
+
static inline bool
i915_gem_object_has_struct_page(const struct drm_i915_gem_object *obj)
{
diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
index b7b7f92c9a32..e39affb8e47a 100644
--- a/drivers/gpu/drm/i915/i915_gem.c
+++ b/drivers/gpu/drm/i915/i915_gem.c
@@ -293,7 +293,7 @@ drop_pages(struct drm_i915_gem_object *obj)
break;
ret = i915_gem_object_put_pages(obj);
- drm_gem_object_unreference(&obj->base);
+ i915_gem_object_put(obj);
return ret;
}
@@ -884,7 +884,7 @@ i915_gem_pread_ioctl(struct drm_device *dev, void *data,
args->offset, args->data_ptr);
out:
- drm_gem_object_unreference(&obj->base);
+ i915_gem_object_put(obj);
unlock:
mutex_unlock(&dev->struct_mutex);
return ret;
@@ -1316,7 +1316,7 @@ i915_gem_pwrite_ioctl(struct drm_device *dev, void *data,
}
out:
- drm_gem_object_unreference(&obj->base);
+ i915_gem_object_put(obj);
unlock:
mutex_unlock(&dev->struct_mutex);
put_rpm:
@@ -1510,7 +1510,7 @@ i915_gem_set_domain_ioctl(struct drm_device *dev, void
*data,
intel_fb_obj_invalidate(obj, write_origin(obj, write_domain));
unref:
- drm_gem_object_unreference(&obj->base);
+ i915_gem_object_put(obj);
unlock:
mutex_unlock(&dev->struct_mutex);
return ret;
@@ -1544,7 +1544,7 @@ i915_gem_sw_finish_ioctl(struct drm_device *dev, void
*data,
if (obj->pin_display)
i915_gem_object_flush_cpu_write_domain(obj);
- drm_gem_object_unreference(&obj->base);
+ i915_gem_object_put(obj);
unlock:
mutex_unlock(&dev->struct_mutex);
return ret;
@@ -1975,7 +1975,7 @@ i915_gem_mmap_gtt(struct drm_file *file,
*offset = drm_vma_node_offset_addr(&obj->base.vma_node);
out:
- drm_gem_object_unreference(&obj->base);
+ i915_gem_object_put(obj);
unlock:
mutex_unlock(&dev->struct_mutex);
return ret;
@@ -2399,7 +2399,7 @@ i915_gem_object_retire__read(struct drm_i915_gem_object
*obj, int ring)
}
i915_gem_request_assign(&obj->last_fenced_req, NULL);
- drm_gem_object_unreference(&obj->base);
+ i915_gem_object_put(obj);
}
static bool i915_context_is_banned(const struct i915_gem_context *ctx)
@@ -2793,7 +2793,7 @@ i915_gem_wait_ioctl(struct drm_device *dev, void *data,
struct drm_file *file)
goto out;
}
- drm_gem_object_unreference(&obj->base);
+ i915_gem_object_put(obj);
for (i = 0; i < I915_NUM_ENGINES; i++) {
if (obj->last_read_req[i] == NULL)
@@ -2814,7 +2814,7 @@ i915_gem_wait_ioctl(struct drm_device *dev, void *data,
struct drm_file *file)
return ret;
out:
- drm_gem_object_unreference(&obj->base);
+ i915_gem_object_put(obj);
mutex_unlock(&dev->struct_mutex);
return ret;
}
@@ -3644,7 +3644,7 @@ int i915_gem_set_caching_ioctl(struct drm_device *dev,
void *data,
ret = i915_gem_object_set_cache_level(obj, level);
- drm_gem_object_unreference(&obj->base);
+ i915_gem_object_put(obj);
unlock:
[Intel-gfx] [PATCH 09/13] drm/i915: Rename i915_gem_context_reference/unreference()
As these are wrappers around kref_get/kref_put() it is preferable to
follow the naming convention and use the same verb get/put in our
wrapper names for manipulating a reference to the context.
Signed-off-by: Chris Wilson
Cc: Tvrtko Ursulin
Cc: Joonas Lahtinen
Reviewed-by: Joonas Lahtinen
---
drivers/gpu/drm/i915/i915_drv.h| 6 --
drivers/gpu/drm/i915/i915_gem_context.c| 22 ++
drivers/gpu/drm/i915/i915_gem_execbuffer.c | 6 +++---
drivers/gpu/drm/i915/i915_gem_request.c| 7 +++
drivers/gpu/drm/i915/intel_lrc.c | 4 ++--
drivers/gpu/drm/i915/intel_ringbuffer.c| 4 ++--
6 files changed, 24 insertions(+), 25 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 733da62ed179..d8630f7ce3a1 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -3316,12 +3316,14 @@ i915_gem_context_lookup(struct drm_i915_file_private
*file_priv, u32 id)
return ctx;
}
-static inline void i915_gem_context_reference(struct i915_gem_context *ctx)
+static inline struct i915_gem_context *
+i915_gem_context_get(struct i915_gem_context *ctx)
{
kref_get(&ctx->ref);
+ return ctx;
}
-static inline void i915_gem_context_unreference(struct i915_gem_context *ctx)
+static inline void i915_gem_context_put(struct i915_gem_context *ctx)
{
lockdep_assert_held(&ctx->i915->drm.struct_mutex);
kref_put(&ctx->ref, i915_gem_context_free);
diff --git a/drivers/gpu/drm/i915/i915_gem_context.c
b/drivers/gpu/drm/i915/i915_gem_context.c
index 8e952b1a31b3..11d498e2a593 100644
--- a/drivers/gpu/drm/i915/i915_gem_context.c
+++ b/drivers/gpu/drm/i915/i915_gem_context.c
@@ -305,7 +305,7 @@ __create_hw_context(struct drm_device *dev,
return ctx;
err_out:
- i915_gem_context_unreference(ctx);
+ i915_gem_context_put(ctx);
return ERR_PTR(ret);
}
@@ -333,7 +333,7 @@ i915_gem_create_context(struct drm_device *dev,
DRM_DEBUG_DRIVER("PPGTT setup failed (%ld)\n",
PTR_ERR(ppgtt));
idr_remove(&file_priv->context_idr, ctx->user_handle);
- i915_gem_context_unreference(ctx);
+ i915_gem_context_put(ctx);
return ERR_CAST(ppgtt);
}
@@ -390,7 +390,7 @@ static void i915_gem_context_unpin(struct i915_gem_context
*ctx,
if (ce->state)
i915_gem_object_ggtt_unpin(ce->state);
- i915_gem_context_unreference(ctx);
+ i915_gem_context_put(ctx);
}
}
@@ -504,7 +504,7 @@ void i915_gem_context_fini(struct drm_device *dev)
lockdep_assert_held(&dev->struct_mutex);
- i915_gem_context_unreference(dctx);
+ i915_gem_context_put(dctx);
dev_priv->kernel_context = NULL;
ida_destroy(&dev_priv->context_hw_ida);
@@ -515,7 +515,7 @@ static int context_idr_cleanup(int id, void *p, void *data)
struct i915_gem_context *ctx = p;
ctx->file_priv = ERR_PTR(-EBADF);
- i915_gem_context_unreference(ctx);
+ i915_gem_context_put(ctx);
return 0;
}
@@ -827,10 +827,9 @@ static int do_rcs_switch(struct drm_i915_gem_request *req)
/* obj is kept alive until the next request by its active ref */
i915_gem_object_ggtt_unpin(from->engine[RCS].state);
- i915_gem_context_unreference(from);
+ i915_gem_context_put(from);
}
- i915_gem_context_reference(to);
- engine->last_context = to;
+ engine->last_context = i915_gem_context_get(to);
/* GEN8 does *not* require an explicit reload if the PDPs have been
* setup, and we do not wish to move them.
@@ -914,10 +913,9 @@ int i915_switch_context(struct drm_i915_gem_request *req)
}
if (to != engine->last_context) {
- i915_gem_context_reference(to);
if (engine->last_context)
-
i915_gem_context_unreference(engine->last_context);
- engine->last_context = to;
+ i915_gem_context_put(engine->last_context);
+ engine->last_context = i915_gem_context_get(to);
}
return 0;
@@ -985,7 +983,7 @@ int i915_gem_context_destroy_ioctl(struct drm_device *dev,
void *data,
}
idr_remove(&file_priv->context_idr, ctx->user_handle);
- i915_gem_context_unreference(ctx);
+ i915_gem_context_put(ctx);
mutex_unlock(&dev->struct_mutex);
DRM_DEBUG_DRIVER("HW context %d destroyed\n", args->ctx_id);
diff --git a/drivers/gpu/drm/i915/i915_gem_execbuffer.c
b/drivers/gpu/drm/i915/i915_gem_execbuffer.c
index 1cc4ba7e87a4..2209f1ff7e9a 100644
--- a/drivers/gpu/drm/i915/i915_gem_execbuffer.c
+++ b/driver
[Intel-gfx] [PATCH 07/13] drm/i915: Mark imported dma-buf objects as being coherent
A foreign dma-buf does not share our cache domain tracking, and we rely on the producer ensuring cache coherency. Marking them as being in the CPU domain is incorrect. Signed-off-by: Chris Wilson --- drivers/gpu/drm/i915/i915_gem_dmabuf.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/gpu/drm/i915/i915_gem_dmabuf.c b/drivers/gpu/drm/i915/i915_gem_dmabuf.c index 8a5f88aef6e8..12e360cc3377 100644 --- a/drivers/gpu/drm/i915/i915_gem_dmabuf.c +++ b/drivers/gpu/drm/i915/i915_gem_dmabuf.c @@ -333,6 +333,8 @@ struct drm_gem_object *i915_gem_prime_import(struct drm_device *dev, drm_gem_private_object_init(dev, &obj->base, dma_buf->size); i915_gem_object_init(obj, &i915_gem_object_dmabuf_ops); obj->base.import_attach = attach; + obj->base.read_domains = I915_GEM_DOMAIN_GTT; + obj->base.write_domain = 0; return &obj->base; -- 2.8.1 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 03/13] drm/i915: Derive GEM requests from dma-fence
dma-buf provides a generic fence class for interoperation between
drivers. Internally we use the request structure as a fence, and so with
only a little bit of interfacing we can rebase those requests on top of
dma-buf fences. This will allow us, in the future, to pass those fences
back to userspace or between drivers.
v2: The fence_context needs to be globally unique, not just unique to
this device.
Signed-off-by: Chris Wilson
Cc: Jesse Barnes
Cc: Daniel Vetter
Reviewed-by: Daniel Vetter
---
drivers/gpu/drm/i915/i915_debugfs.c| 2 +-
drivers/gpu/drm/i915/i915_gem_request.c| 119 ++---
drivers/gpu/drm/i915/i915_gem_request.h| 43 ++-
drivers/gpu/drm/i915/i915_gpu_error.c | 2 +-
drivers/gpu/drm/i915/i915_guc_submission.c | 4 +-
drivers/gpu/drm/i915/i915_trace.h | 10 +--
drivers/gpu/drm/i915/intel_breadcrumbs.c | 7 +-
drivers/gpu/drm/i915/intel_lrc.c | 3 +-
drivers/gpu/drm/i915/intel_ringbuffer.c| 11 +--
drivers/gpu/drm/i915/intel_ringbuffer.h| 1 +
10 files changed, 153 insertions(+), 49 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_debugfs.c
b/drivers/gpu/drm/i915/i915_debugfs.c
index 7c4a60b87eb5..ec0162585238 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -768,7 +768,7 @@ static int i915_gem_request_info(struct seq_file *m, void
*data)
if (req->pid)
task = pid_task(req->pid, PIDTYPE_PID);
seq_printf(m, "%x @ %d: %s [%d]\n",
- req->seqno,
+ req->fence.seqno,
(int) (jiffies - req->emitted_jiffies),
task ? task->comm : "",
task ? task->pid : -1);
diff --git a/drivers/gpu/drm/i915/i915_gem_request.c
b/drivers/gpu/drm/i915/i915_gem_request.c
index 25fd91aad74b..3c4b1af42a46 100644
--- a/drivers/gpu/drm/i915/i915_gem_request.c
+++ b/drivers/gpu/drm/i915/i915_gem_request.c
@@ -24,6 +24,101 @@
#include "i915_drv.h"
+static inline struct drm_i915_gem_request *
+to_i915_request(struct fence *fence)
+{
+ return container_of(fence, struct drm_i915_gem_request, fence);
+}
+
+static const char *i915_fence_get_driver_name(struct fence *fence)
+{
+ return "i915";
+}
+
+static const char *i915_fence_get_timeline_name(struct fence *fence)
+{
+ /* Timelines are bound by eviction to a VM. However, since
+* we only have a global seqno at the moment, we only have
+* a single timeline. Note that each timeline will have
+* multiple execution contexts (fence contexts) as we allow
+* engines within a single timeline to execute in parallel.
+*/
+ return "global";
+}
+
+static bool i915_fence_signaled(struct fence *fence)
+{
+ return i915_gem_request_completed(to_i915_request(fence));
+}
+
+static bool i915_fence_enable_signaling(struct fence *fence)
+{
+ if (i915_fence_signaled(fence))
+ return false;
+
+ intel_engine_enable_signaling(to_i915_request(fence));
+ return true;
+}
+
+static signed long i915_fence_wait(struct fence *fence,
+ bool interruptible,
+ signed long timeout_jiffies)
+{
+ s64 timeout_ns, *timeout;
+ int ret;
+
+ if (timeout_jiffies != MAX_SCHEDULE_TIMEOUT) {
+ timeout_ns = jiffies_to_nsecs(timeout_jiffies);
+ timeout = &timeout_ns;
+ } else {
+ timeout = NULL;
+ }
+
+ ret = __i915_wait_request(to_i915_request(fence),
+ interruptible, timeout,
+ NULL);
+ if (ret == -ETIME)
+ return 0;
+
+ if (ret < 0)
+ return ret;
+
+ if (timeout_jiffies != MAX_SCHEDULE_TIMEOUT)
+ timeout_jiffies = nsecs_to_jiffies(timeout_ns);
+
+ return timeout_jiffies;
+}
+
+static void i915_fence_value_str(struct fence *fence, char *str, int size)
+{
+ snprintf(str, size, "%u", fence->seqno);
+}
+
+static void i915_fence_timeline_value_str(struct fence *fence, char *str,
+ int size)
+{
+ snprintf(str, size, "%u",
+intel_engine_get_seqno(to_i915_request(fence)->engine));
+}
+
+static void i915_fence_release(struct fence *fence)
+{
+ struct drm_i915_gem_request *req = to_i915_request(fence);
+
+ kmem_cache_free(req->i915->requests, req);
+}
+
+const struct fence_ops i915_fence_ops = {
+ .get_driver_name = i915_fence_get_driver_name,
+ .get_timeline_name = i915_fence_get_timeline_name,
+ .enable_signaling = i915_fence_enable_signaling,
+ .signaled = i915_fence_signaled,
+ .wait = i915_fence_wait,
+ .release = i915_fence_release,
+ .fenc
[Intel-gfx] [PATCH 13/13] drm/i915: Rename drm_gem_object_unreference_unlocked in preparation for lockless free
Signed-off-by: Chris Wilson
---
drivers/gpu/drm/i915/i915_drv.h | 10 ++
drivers/gpu/drm/i915/i915_gem.c | 10 +-
drivers/gpu/drm/i915/i915_gem_tiling.c | 2 +-
drivers/gpu/drm/i915/i915_gem_userptr.c | 2 +-
drivers/gpu/drm/i915/intel_display.c| 6 +++---
drivers/gpu/drm/i915/intel_overlay.c| 2 +-
6 files changed, 21 insertions(+), 11 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 6511056c2bc6..69fa25af072f 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -2319,6 +2319,16 @@ i915_gem_object_put(struct drm_i915_gem_object *obj)
__deprecated
extern void drm_gem_object_unreference(struct drm_gem_object *);
+__attribute__((nonnull))
+static inline void
+i915_gem_object_put_unlocked(struct drm_i915_gem_object *obj)
+{
+ drm_gem_object_unreference_unlocked(&obj->base);
+}
+
+__deprecated
+extern void drm_gem_object_unreference_unlocked(struct drm_gem_object *);
+
static inline bool
i915_gem_object_has_struct_page(const struct drm_i915_gem_object *obj)
{
diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
index e39affb8e47a..91661de1099a 100644
--- a/drivers/gpu/drm/i915/i915_gem.c
+++ b/drivers/gpu/drm/i915/i915_gem.c
@@ -408,7 +408,7 @@ i915_gem_create(struct drm_file *file,
ret = drm_gem_handle_create(file, &obj->base, &handle);
/* drop reference from allocate - handle holds it now */
- drm_gem_object_unreference_unlocked(&obj->base);
+ i915_gem_object_put_unlocked(obj);
if (ret)
return ret;
@@ -1592,7 +1592,7 @@ i915_gem_mmap_ioctl(struct drm_device *dev, void *data,
* pages from.
*/
if (!obj->base.filp) {
- drm_gem_object_unreference_unlocked(&obj->base);
+ i915_gem_object_put_unlocked(obj);
return -EINVAL;
}
@@ -1604,7 +1604,7 @@ i915_gem_mmap_ioctl(struct drm_device *dev, void *data,
struct vm_area_struct *vma;
if (down_write_killable(&mm->mmap_sem)) {
- drm_gem_object_unreference_unlocked(&obj->base);
+ i915_gem_object_put_unlocked(obj);
return -EINTR;
}
vma = find_vma(mm, addr);
@@ -1618,7 +1618,7 @@ i915_gem_mmap_ioctl(struct drm_device *dev, void *data,
/* This may race, but that's ok, it only gets set */
WRITE_ONCE(obj->has_wc_mmap, true);
}
- drm_gem_object_unreference_unlocked(&obj->base);
+ i915_gem_object_put_unlocked(obj);
if (IS_ERR((void *)addr))
return addr;
@@ -3594,7 +3594,7 @@ int i915_gem_get_caching_ioctl(struct drm_device *dev,
void *data,
break;
}
- drm_gem_object_unreference_unlocked(&obj->base);
+ i915_gem_object_put_unlocked(obj);
return 0;
}
diff --git a/drivers/gpu/drm/i915/i915_gem_tiling.c
b/drivers/gpu/drm/i915/i915_gem_tiling.c
index 9b096d1e8164..adeb0621e1f1 100644
--- a/drivers/gpu/drm/i915/i915_gem_tiling.c
+++ b/drivers/gpu/drm/i915/i915_gem_tiling.c
@@ -172,7 +172,7 @@ i915_gem_set_tiling(struct drm_device *dev, void *data,
if (!i915_tiling_ok(dev,
args->stride, obj->base.size, args->tiling_mode)) {
- drm_gem_object_unreference_unlocked(&obj->base);
+ i915_gem_object_put_unlocked(obj);
return -EINVAL;
}
diff --git a/drivers/gpu/drm/i915/i915_gem_userptr.c
b/drivers/gpu/drm/i915/i915_gem_userptr.c
index cd4af22b8c59..ca8b82ab93d6 100644
--- a/drivers/gpu/drm/i915/i915_gem_userptr.c
+++ b/drivers/gpu/drm/i915/i915_gem_userptr.c
@@ -845,7 +845,7 @@ i915_gem_userptr_ioctl(struct drm_device *dev, void *data,
struct drm_file *file
ret = drm_gem_handle_create(file, &obj->base, &handle);
/* drop reference from allocate - handle holds it now */
- drm_gem_object_unreference_unlocked(&obj->base);
+ i915_gem_object_put_unlocked(obj);
if (ret)
return ret;
diff --git a/drivers/gpu/drm/i915/intel_display.c
b/drivers/gpu/drm/i915/intel_display.c
index df2b20063a52..5ddc03f791b4 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -10529,7 +10529,7 @@ intel_framebuffer_create_for_mode(struct drm_device
*dev,
fb = intel_framebuffer_create(dev, &mode_cmd, obj);
if (IS_ERR(fb))
- drm_gem_object_unreference_unlocked(&obj->base);
+ i915_gem_object_put_unlocked(obj);
return fb;
}
@@ -11843,7 +11843,7 @@ cleanup:
crtc->primary->fb = old_fb;
update_state_fb(crtc->primary);
- drm_gem_object_unreference_unlocked(&obj->base);
+ i915_gem_object_put_unlocked(obj);
drm_framebuffer_unreference(work->old_fb);
spin_lock_irq(&dev->event_l
[Intel-gfx] [PATCH 10/13] drm/i915: Wrap drm_gem_object_lookup in i915_gem_object_lookup
For symmetry with a forthcoming i915_gem_object_get() and
i915_gem_object_pu().
Signed-off-by: Chris Wilson
---
drivers/gpu/drm/i915/i915_drv.h| 20 +++-
drivers/gpu/drm/i915/i915_gem.c| 58 +-
drivers/gpu/drm/i915/i915_gem_tiling.c | 8 ++---
drivers/gpu/drm/i915/intel_display.c | 4 +--
drivers/gpu/drm/i915/intel_overlay.c | 5 ++-
5 files changed, 56 insertions(+), 39 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index d8630f7ce3a1..bdcc2e1fe240 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -2278,7 +2278,25 @@ struct drm_i915_gem_object {
} userptr;
};
};
-#define to_intel_bo(x) container_of(x, struct drm_i915_gem_object, base)
+
+static inline struct drm_i915_gem_object *
+to_intel_bo(struct drm_gem_object *gem)
+{
+ /* Assert that to_intel_bo(NULL) == NULL */
+ BUILD_BUG_ON(offsetof(struct drm_i915_gem_object, base));
+
+ return container_of(gem, struct drm_i915_gem_object, base);
+}
+
+static inline struct drm_i915_gem_object *
+i915_gem_object_lookup(struct drm_file *file, u32 handle)
+{
+ return to_intel_bo(drm_gem_object_lookup(file, handle));
+}
+
+__deprecated
+extern struct drm_gem_object *
+drm_gem_object_lookup(struct drm_file *file, u32 handle);
static inline bool
i915_gem_object_has_struct_page(const struct drm_i915_gem_object *obj)
diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
index b56a3a080da4..8f9031560ce4 100644
--- a/drivers/gpu/drm/i915/i915_gem.c
+++ b/drivers/gpu/drm/i915/i915_gem.c
@@ -861,8 +861,8 @@ i915_gem_pread_ioctl(struct drm_device *dev, void *data,
if (ret)
return ret;
- obj = to_intel_bo(drm_gem_object_lookup(file, args->handle));
- if (&obj->base == NULL) {
+ obj = i915_gem_object_lookup(file, args->handle);
+ if (!obj) {
ret = -ENOENT;
goto unlock;
}
@@ -1276,8 +1276,8 @@ i915_gem_pwrite_ioctl(struct drm_device *dev, void *data,
if (ret)
goto put_rpm;
- obj = to_intel_bo(drm_gem_object_lookup(file, args->handle));
- if (&obj->base == NULL) {
+ obj = i915_gem_object_lookup(file, args->handle);
+ if (!obj) {
ret = -ENOENT;
goto unlock;
}
@@ -1485,8 +1485,8 @@ i915_gem_set_domain_ioctl(struct drm_device *dev, void
*data,
if (ret)
return ret;
- obj = to_intel_bo(drm_gem_object_lookup(file, args->handle));
- if (&obj->base == NULL) {
+ obj = i915_gem_object_lookup(file, args->handle);
+ if (!obj) {
ret = -ENOENT;
goto unlock;
}
@@ -1534,8 +1534,8 @@ i915_gem_sw_finish_ioctl(struct drm_device *dev, void
*data,
if (ret)
return ret;
- obj = to_intel_bo(drm_gem_object_lookup(file, args->handle));
- if (&obj->base == NULL) {
+ obj = i915_gem_object_lookup(file, args->handle);
+ if (!obj) {
ret = -ENOENT;
goto unlock;
}
@@ -1575,7 +1575,7 @@ i915_gem_mmap_ioctl(struct drm_device *dev, void *data,
struct drm_file *file)
{
struct drm_i915_gem_mmap *args = data;
- struct drm_gem_object *obj;
+ struct drm_i915_gem_object *obj;
unsigned long addr;
if (args->flags & ~(I915_MMAP_WC))
@@ -1584,19 +1584,19 @@ i915_gem_mmap_ioctl(struct drm_device *dev, void *data,
if (args->flags & I915_MMAP_WC && !boot_cpu_has(X86_FEATURE_PAT))
return -ENODEV;
- obj = drm_gem_object_lookup(file, args->handle);
- if (obj == NULL)
+ obj = i915_gem_object_lookup(file, args->handle);
+ if (!obj)
return -ENOENT;
/* prime objects have no backing filp to GEM mmap
* pages from.
*/
- if (!obj->filp) {
- drm_gem_object_unreference_unlocked(obj);
+ if (!obj->base.filp) {
+ drm_gem_object_unreference_unlocked(&obj->base);
return -EINVAL;
}
- addr = vm_mmap(obj->filp, 0, args->size,
+ addr = vm_mmap(obj->base.filp, 0, args->size,
PROT_READ | PROT_WRITE, MAP_SHARED,
args->offset);
if (args->flags & I915_MMAP_WC) {
@@ -1604,7 +1604,7 @@ i915_gem_mmap_ioctl(struct drm_device *dev, void *data,
struct vm_area_struct *vma;
if (down_write_killable(&mm->mmap_sem)) {
- drm_gem_object_unreference_unlocked(obj);
+ drm_gem_object_unreference_unlocked(&obj->base);
return -EINTR;
}
vma = find_vma(mm, addr);
@@ -1616,9 +1616,9 @@ i915_gem_mmap_ioctl(struct drm_device *dev, void *data,
up_write(&mm->mmap_sem);
[Intel-gfx] ✗ Ro.CI.BAT: failure for series starting with [1/4] drm/i915: Preserve current RPS frequency across init
== Series Details == Series: series starting with [1/4] drm/i915: Preserve current RPS frequency across init URL : https://patchwork.freedesktop.org/series/9448/ State : failure == Summary == Series 9448v1 Series without cover letter http://patchwork.freedesktop.org/api/1.0/series/9448/revisions/1/mbox Test drv_module_reload_basic: dmesg-warn -> PASS (ro-byt-n2820) Test gem_exec_flush: Subgroup basic-batch-kernel-default-uc: pass -> DMESG-FAIL (ro-bdw-i7-5557U) dmesg-fail -> PASS (fi-skl-i5-6260u) Subgroup basic-batch-kernel-default-wb: pass -> DMESG-FAIL (fi-skl-i5-6260u) Test kms_flip: Subgroup basic-flip-vs-wf_vblank: fail -> PASS (ro-bdw-i5-5250u) Test kms_pipe_crc_basic: Subgroup nonblocking-crc-pipe-b: fail -> PASS (fi-skl-i5-6260u) Subgroup nonblocking-crc-pipe-b-frame-sequence: pass -> SKIP (fi-skl-i5-6260u) Subgroup read-crc-pipe-c-frame-sequence: skip -> PASS (fi-skl-i5-6260u) Subgroup suspend-read-crc-pipe-b: skip -> DMESG-WARN (ro-bdw-i5-5250u) Subgroup suspend-read-crc-pipe-c: dmesg-warn -> SKIP (ro-bdw-i5-5250u) fi-kbl-qkkr total:231 pass:160 dwarn:29 dfail:0 fail:2 skip:40 fi-skl-i5-6260u total:231 pass:202 dwarn:0 dfail:1 fail:2 skip:26 fi-skl-i7-6700k total:231 pass:189 dwarn:0 dfail:1 fail:2 skip:39 fi-snb-i7-2600 total:231 pass:176 dwarn:0 dfail:0 fail:2 skip:53 ro-bdw-i5-5250u total:229 pass:204 dwarn:2 dfail:1 fail:0 skip:22 ro-bdw-i7-5557U total:229 pass:203 dwarn:1 dfail:2 fail:0 skip:23 ro-bdw-i7-5600u total:229 pass:190 dwarn:0 dfail:1 fail:0 skip:38 ro-bsw-n3050 total:229 pass:176 dwarn:0 dfail:1 fail:3 skip:49 ro-byt-n2820 total:229 pass:180 dwarn:0 dfail:1 fail:3 skip:45 ro-hsw-i3-4010u total:229 pass:197 dwarn:0 dfail:1 fail:0 skip:31 ro-hsw-i7-4770r total:229 pass:197 dwarn:0 dfail:1 fail:0 skip:31 ro-ilk-i7-620lm total:229 pass:157 dwarn:0 dfail:1 fail:1 skip:70 ro-ilk1-i5-650 total:224 pass:157 dwarn:0 dfail:1 fail:1 skip:65 ro-ivb-i7-3770 total:229 pass:188 dwarn:0 dfail:1 fail:0 skip:40 ro-skl3-i5-6260u total:229 pass:208 dwarn:1 dfail:1 fail:0 skip:19 ro-snb-i7-2620M total:229 pass:179 dwarn:0 dfail:1 fail:1 skip:48 Results at /archive/results/CI_IGT_test/RO_Patchwork_1392/ 49943b2 drm-intel-nightly: 2016y-07m-04d-07h-35m-36s UTC integration manifest 8e41766 drm/i915: Remove temporary RPM wakeref assert disables 649a2f3 drm/i915: Defer enabling rc6 til after we submit the first batch/context 3bd7940 drm/i915: Remove superfluous powersave work flushing d4e8f16 drm/i915: Preserve current RPS frequency across init ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH] drm/i915: Limit i915_ring_test_irq debugfs to actual rings
Chris Wilson writes:
> For simplicity in testing, only report known rings in the mask. This
> allows userspace to try and trigger a missed irq on every ring and do a
> comparison between i915_ring_test_irq and i915_ring_missed_irq to see if
> any rings failed.
>
> Signed-off-by: Chris Wilson
> Cc: Mika Kuoppala
> ---
> drivers/gpu/drm/i915/i915_debugfs.c | 9 +
> 1 file changed, 1 insertion(+), 8 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_debugfs.c
> b/drivers/gpu/drm/i915/i915_debugfs.c
> index 3da36db9c830..1da821479161 100644
> --- a/drivers/gpu/drm/i915/i915_debugfs.c
> +++ b/drivers/gpu/drm/i915/i915_debugfs.c
> @@ -4615,17 +4615,10 @@ i915_ring_test_irq_set(void *data, u64 val)
> {
> struct drm_device *dev = data;
> struct drm_i915_private *dev_priv = dev->dev_private;
> - int ret;
>
> DRM_DEBUG_DRIVER("Masking interrupts on rings 0x%08llx\n", val);
Moving this dbg message past masking would make more sense?
Reviewed-by: Mika Kuoppala
> -
> - /* Lock against concurrent debugfs callers */
> - ret = mutex_lock_interruptible(&dev->struct_mutex);
> - if (ret)
> - return ret;
> -
> + val &= INTEL_INFO(dev_priv)->ring_mask;
> dev_priv->gpu_error.test_irq_rings = val;
> - mutex_unlock(&dev->struct_mutex);
>
> return 0;
> }
> --
> 2.8.1
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[Intel-gfx] ✗ Ro.CI.BAT: failure for series starting with [1/3] drm/i915: Amalgamate gen6_mm_switch() and vgpu_mm_switch()
== Series Details == Series: series starting with [1/3] drm/i915: Amalgamate gen6_mm_switch() and vgpu_mm_switch() URL : https://patchwork.freedesktop.org/series/9449/ State : failure == Summary == Series 9449v1 Series without cover letter http://patchwork.freedesktop.org/api/1.0/series/9449/revisions/1/mbox Test drv_module_reload_basic: dmesg-warn -> PASS (ro-byt-n2820) Test gem_exec_flush: Subgroup basic-batch-kernel-default-cmd: fail -> PASS (ro-byt-n2820) Subgroup basic-batch-kernel-default-uc: dmesg-fail -> PASS (fi-skl-i7-6700k) Subgroup basic-batch-kernel-default-wb: pass -> DMESG-FAIL (ro-bdw-i7-5557U) Test kms_flip: Subgroup basic-flip-vs-wf_vblank: fail -> PASS (ro-bdw-i5-5250u) Test kms_pipe_crc_basic: Subgroup nonblocking-crc-pipe-b: fail -> PASS (fi-skl-i5-6260u) Subgroup nonblocking-crc-pipe-b-frame-sequence: pass -> INCOMPLETE (fi-skl-i5-6260u) fi-kbl-qkkr total:231 pass:160 dwarn:29 dfail:0 fail:2 skip:40 fi-skl-i5-6260u total:196 pass:184 dwarn:0 dfail:1 fail:0 skip:10 fi-skl-i7-6700k total:231 pass:190 dwarn:0 dfail:0 fail:2 skip:39 fi-snb-i7-2600 total:231 pass:176 dwarn:0 dfail:0 fail:2 skip:53 ro-bdw-i5-5250u total:229 pass:204 dwarn:2 dfail:1 fail:0 skip:22 ro-bdw-i7-5557U total:229 pass:203 dwarn:1 dfail:2 fail:0 skip:23 ro-bdw-i7-5600u total:229 pass:190 dwarn:0 dfail:1 fail:0 skip:38 ro-byt-n2820 total:229 pass:181 dwarn:0 dfail:1 fail:2 skip:45 ro-hsw-i3-4010u total:229 pass:197 dwarn:0 dfail:1 fail:0 skip:31 ro-hsw-i7-4770r total:229 pass:197 dwarn:0 dfail:1 fail:0 skip:31 ro-ilk-i7-620lm total:229 pass:157 dwarn:0 dfail:1 fail:1 skip:70 ro-ilk1-i5-650 total:224 pass:157 dwarn:0 dfail:1 fail:1 skip:65 ro-ivb-i7-3770 total:229 pass:188 dwarn:0 dfail:1 fail:0 skip:40 ro-skl3-i5-6260u total:229 pass:208 dwarn:1 dfail:1 fail:0 skip:19 ro-snb-i7-2620M total:229 pass:179 dwarn:0 dfail:1 fail:1 skip:48 ro-bsw-n3050 failed to connect after reboot Results at /archive/results/CI_IGT_test/RO_Patchwork_1393/ 49943b2 drm-intel-nightly: 2016y-07m-04d-07h-35m-36s UTC integration manifest 22fb51c drm/i915: Skip capturing an error state if we already have one 3898455 drm/i915: Clean up GPU hang message 5bf2752 drm/i915: Amalgamate gen6_mm_switch() and vgpu_mm_switch() ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✗ Ro.CI.BAT: failure for series starting with [01/13] drm/i915: Move GEM request routines to i915_gem_request.c
== Series Details == Series: series starting with [01/13] drm/i915: Move GEM request routines to i915_gem_request.c URL : https://patchwork.freedesktop.org/series/9450/ State : failure == Summary == Applying: drm/i915: Move GEM request routines to i915_gem_request.c fatal: sha1 information is lacking or useless (drivers/gpu/drm/i915/i915_gem.c). error: could not build fake ancestor Patch failed at 0001 drm/i915: Move GEM request routines to i915_gem_request.c The copy of the patch that failed is found in: .git/rebase-apply/patch When you have resolved this problem, run "git am --continue". If you prefer to skip this patch, run "git am --skip" instead. To restore the original branch and stop patching, run "git am --abort". ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH] drm/i915: Hold irq uncore.lock when initialising fw_domains
On 03/07/16 18:29, Chris Wilson wrote:
Acquiring the forcewake domain asserts that it is in an atomic section
(as we always expect to under the uncore.lock). This true expect for
initialising the domains on Ivybridge, and so we generate a warning.
Wrap the manual usage of fw_domains inside the spin_lock.
Signed-off-by: Chris Wilson
Cc: Tvrtko Ursulin
Cc: Mika Kuoppala
---
drivers/gpu/drm/i915/intel_uncore.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/drivers/gpu/drm/i915/intel_uncore.c
b/drivers/gpu/drm/i915/intel_uncore.c
index 7da3906badf3..1d65209c0998 100644
--- a/drivers/gpu/drm/i915/intel_uncore.c
+++ b/drivers/gpu/drm/i915/intel_uncore.c
@@ -1299,9 +1299,11 @@ static void intel_uncore_fw_domains_init(struct
drm_i915_private *dev_priv)
fw_domain_init(dev_priv, FW_DOMAIN_ID_RENDER,
FORCEWAKE_MT, FORCEWAKE_MT_ACK);
+ spin_lock_irq(&dev_priv->uncore.lock);
fw_domains_get_with_thread_status(dev_priv, FORCEWAKE_ALL);
ecobus = __raw_i915_read32(dev_priv, ECOBUS);
fw_domains_put_with_fifo(dev_priv, FORCEWAKE_ALL);
+ spin_unlock_irq(&dev_priv->uncore.lock);
if (!(ecobus & FORCEWAKE_MT_ENABLE)) {
DRM_INFO("No MT forcewake available on Ivybridge, this can
result in issues\n");
Reviewed-by: Tvrtko Ursulin
Regards,
Tvrtko
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Re: [Intel-gfx] [PATCH] drm/i915: Hold irq uncore.lock when initialising fw_domains
On Mon, Jul 04, 2016 at 10:06:14AM +0100, Tvrtko Ursulin wrote: > > On 03/07/16 18:29, Chris Wilson wrote: > >Acquiring the forcewake domain asserts that it is in an atomic section > >(as we always expect to under the uncore.lock). This true expect for > >initialising the domains on Ivybridge, and so we generate a warning. > >Wrap the manual usage of fw_domains inside the spin_lock. > > > >Signed-off-by: Chris Wilson > >Cc: Tvrtko Ursulin > >Cc: Mika Kuoppala > Reviewed-by: Tvrtko Ursulin Thanks, gave the changelog a once-over for grammar and pushed. -Chris -- Chris Wilson, Intel Open Source Technology Centre ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH] drm/i915: Limit i915_ring_test_irq debugfs to actual rings
On Mon, Jul 04, 2016 at 11:53:01AM +0300, Mika Kuoppala wrote:
> Chris Wilson writes:
> > diff --git a/drivers/gpu/drm/i915/i915_debugfs.c
> > b/drivers/gpu/drm/i915/i915_debugfs.c
> > index 3da36db9c830..1da821479161 100644
> > --- a/drivers/gpu/drm/i915/i915_debugfs.c
> > +++ b/drivers/gpu/drm/i915/i915_debugfs.c
> > @@ -4615,17 +4615,10 @@ i915_ring_test_irq_set(void *data, u64 val)
> > {
> > struct drm_device *dev = data;
> > struct drm_i915_private *dev_priv = dev->dev_private;
> > - int ret;
> >
> > DRM_DEBUG_DRIVER("Masking interrupts on rings 0x%08llx\n", val);
>
> Moving this dbg message past masking would make more sense?
Yes, it does. Done and pushed.
-Chris
--
Chris Wilson, Intel Open Source Technology Centre
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Re: [Intel-gfx] [PATCH] drm/i915: Hold irq uncore.lock when initialising fw_domains
Chris Wilson writes:
> Acquiring the forcewake domain asserts that it is in an atomic section
> (as we always expect to under the uncore.lock). This true expect for
> initialising the domains on Ivybridge, and so we generate a warning.
> Wrap the manual usage of fw_domains inside the spin_lock.
>
> Signed-off-by: Chris Wilson
> Cc: Tvrtko Ursulin
> Cc: Mika Kuoppala
Reviewed-by: Mika Kuoppala
> ---
> drivers/gpu/drm/i915/intel_uncore.c | 2 ++
> 1 file changed, 2 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/intel_uncore.c
> b/drivers/gpu/drm/i915/intel_uncore.c
> index 7da3906badf3..1d65209c0998 100644
> --- a/drivers/gpu/drm/i915/intel_uncore.c
> +++ b/drivers/gpu/drm/i915/intel_uncore.c
> @@ -1299,9 +1299,11 @@ static void intel_uncore_fw_domains_init(struct
> drm_i915_private *dev_priv)
> fw_domain_init(dev_priv, FW_DOMAIN_ID_RENDER,
> FORCEWAKE_MT, FORCEWAKE_MT_ACK);
>
> + spin_lock_irq(&dev_priv->uncore.lock);
> fw_domains_get_with_thread_status(dev_priv, FORCEWAKE_ALL);
> ecobus = __raw_i915_read32(dev_priv, ECOBUS);
> fw_domains_put_with_fifo(dev_priv, FORCEWAKE_ALL);
> + spin_unlock_irq(&dev_priv->uncore.lock);
>
> if (!(ecobus & FORCEWAKE_MT_ENABLE)) {
> DRM_INFO("No MT forcewake available on Ivybridge, this
> can result in issues\n");
> --
> 2.8.1
>
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Re: [Intel-gfx] [PATCH] drm/i915: Mass convert dev->dev_private to to_i915(dev)
On 01/07/16 16:26, Chris Wilson wrote: Since we now subclass struct drm_device, we can save pointer dances by noting the equivalence of struct drm_device and struct drm_i915_private, i.e. by using to_i915(). textdata bss dec hex filename 10738244562 416 1078802 107612 drivers/gpu/drm/i915/i915.ko 10689764562 416 1073954 106322 drivers/gpu/drm/i915/i915.ko Created by the coccinelle script: @@ expression E; identifier p; @@ - struct drm_i915_private *p = E->dev_private; + struct drm_i915_private *p = to_i915(E); Signed-off-by: Chris Wilson --- drivers/gpu/drm/i915/i915_debugfs.c| 176 +++ drivers/gpu/drm/i915/i915_drv.c| 36 ++-- drivers/gpu/drm/i915/i915_gem.c| 54 ++--- drivers/gpu/drm/i915/i915_gem_context.c| 10 +- drivers/gpu/drm/i915/i915_gem_execbuffer.c | 4 +- drivers/gpu/drm/i915/i915_gem_fence.c | 24 +-- drivers/gpu/drm/i915/i915_gem_gtt.c| 20 +- drivers/gpu/drm/i915/i915_gem_stolen.c | 6 +- drivers/gpu/drm/i915/i915_gem_tiling.c | 4 +- drivers/gpu/drm/i915/i915_gpu_error.c | 6 +- drivers/gpu/drm/i915/i915_guc_submission.c | 4 +- drivers/gpu/drm/i915/i915_irq.c| 92 drivers/gpu/drm/i915/i915_suspend.c| 8 +- drivers/gpu/drm/i915/i915_sysfs.c | 22 +- drivers/gpu/drm/i915/intel_audio.c | 18 +- drivers/gpu/drm/i915/intel_color.c | 18 +- drivers/gpu/drm/i915/intel_crt.c | 24 +-- drivers/gpu/drm/i915/intel_ddi.c | 36 ++-- drivers/gpu/drm/i915/intel_display.c | 286 - drivers/gpu/drm/i915/intel_dp.c| 107 + drivers/gpu/drm/i915/intel_dp_mst.c| 6 +- drivers/gpu/drm/i915/intel_dpio_phy.c | 10 +- drivers/gpu/drm/i915/intel_dpll_mgr.c | 12 +- drivers/gpu/drm/i915/intel_drv.h | 4 +- drivers/gpu/drm/i915/intel_dsi.c | 36 ++-- drivers/gpu/drm/i915/intel_dsi_dcs_backlight.c | 2 +- drivers/gpu/drm/i915/intel_dsi_panel_vbt.c | 6 +- drivers/gpu/drm/i915/intel_dsi_pll.c | 12 +- drivers/gpu/drm/i915/intel_dvo.c | 18 +- drivers/gpu/drm/i915/intel_fbc.c | 24 +-- drivers/gpu/drm/i915/intel_fbdev.c | 10 +- drivers/gpu/drm/i915/intel_fifo_underrun.c | 18 +- drivers/gpu/drm/i915/intel_guc_loader.c| 6 +- drivers/gpu/drm/i915/intel_hdmi.c | 48 ++--- drivers/gpu/drm/i915/intel_i2c.c | 6 +- drivers/gpu/drm/i915/intel_lrc.c | 4 +- drivers/gpu/drm/i915/intel_lvds.c | 16 +- drivers/gpu/drm/i915/intel_modes.c | 4 +- drivers/gpu/drm/i915/intel_overlay.c | 4 +- drivers/gpu/drm/i915/intel_panel.c | 6 +- drivers/gpu/drm/i915/intel_pm.c| 110 +- drivers/gpu/drm/i915/intel_psr.c | 36 ++-- drivers/gpu/drm/i915/intel_ringbuffer.c| 10 +- drivers/gpu/drm/i915/intel_sdvo.c | 22 +- drivers/gpu/drm/i915/intel_sprite.c| 18 +- drivers/gpu/drm/i915/intel_tv.c| 12 +- drivers/gpu/drm/i915/intel_uncore.c| 2 +- 47 files changed, 708 insertions(+), 709 deletions(-) Looks fine :) Reviewed-by: Dave Gordon I found three more to convert, plus one place where we can delete some entirely redundant locals, both 'dev' AND 'dev_priv' :) .Dave. ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH] drm/i915: convert a few more E->dev_private to to_i915(E)
Also remove some redundant dev and dev_priv locals
Signed-off-by: Dave Gordon
Cc: Chris Wilson
---
drivers/gpu/drm/i915/i915_gem.c | 4 ++--
drivers/gpu/drm/i915/intel_display.c| 4
drivers/gpu/drm/i915/intel_guc_loader.c | 2 +-
3 files changed, 3 insertions(+), 7 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
index 49f3ea7..1366d4e 100644
--- a/drivers/gpu/drm/i915/i915_gem.c
+++ b/drivers/gpu/drm/i915/i915_gem.c
@@ -4738,7 +4738,7 @@ void i915_gem_object_init(struct drm_i915_gem_object *obj,
obj->fence_reg = I915_FENCE_REG_NONE;
obj->madv = I915_MADV_WILLNEED;
- i915_gem_info_add_obj(obj->base.dev->dev_private, obj->base.size);
+ i915_gem_info_add_obj(to_i915(obj->base.dev), obj->base.size);
}
static const struct drm_i915_gem_object_ops i915_gem_object_ops = {
@@ -5377,7 +5377,7 @@ int i915_gem_open(struct drm_device *dev, struct drm_file
*file)
return -ENOMEM;
file->driver_priv = file_priv;
- file_priv->dev_priv = dev->dev_private;
+ file_priv->dev_priv = to_i915(dev);
file_priv->file = file;
INIT_LIST_HEAD(&file_priv->rps.link);
diff --git a/drivers/gpu/drm/i915/intel_display.c
b/drivers/gpu/drm/i915/intel_display.c
index 92152f2..2b60477 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -14170,15 +14170,11 @@ void intel_crtc_restore_mode(struct drm_crtc *crtc)
skl_max_scale(struct intel_crtc *intel_crtc, struct intel_crtc_state
*crtc_state)
{
int max_scale;
- struct drm_device *dev;
- struct drm_i915_private *dev_priv;
int crtc_clock, cdclk;
if (!intel_crtc || !crtc_state->base.enable)
return DRM_PLANE_HELPER_NO_SCALING;
- dev = intel_crtc->base.dev;
- dev_priv = dev->dev_private;
crtc_clock = crtc_state->base.adjusted_mode.crtc_clock;
cdclk = to_intel_atomic_state(crtc_state->base.state)->cdclk;
diff --git a/drivers/gpu/drm/i915/intel_guc_loader.c
b/drivers/gpu/drm/i915/intel_guc_loader.c
index cf9b2dc..cdf0fbc 100644
--- a/drivers/gpu/drm/i915/intel_guc_loader.c
+++ b/drivers/gpu/drm/i915/intel_guc_loader.c
@@ -605,7 +605,7 @@ static void guc_fw_fetch(struct drm_device *dev, struct
intel_guc_fw *guc_fw)
/* Header and uCode will be loaded to WOPCM. Size of the two. */
size = guc_fw->header_size + guc_fw->ucode_size;
- if (size > guc_wopcm_size(dev->dev_private)) {
+ if (size > guc_wopcm_size(to_i915(dev))) {
DRM_ERROR("Firmware is too large to fit in WOPCM\n");
goto fail;
}
--
1.9.1
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Re: [Intel-gfx] ✗ Ro.CI.BAT: failure for series starting with [1/2] Revert "drm/i915/kbl: drm/i915: Avoid GuC loading for now on Kabylake."
On 01/07/16 06:20, Patchwork wrote: == Series Details == Series: series starting with [1/2] Revert "drm/i915/kbl: drm/i915: Avoid GuC loading for now on Kabylake." URL : https://patchwork.freedesktop.org/series/9332/ State : failure == Summary == Series 9332v1 Series without cover letter http://patchwork.freedesktop.org/api/1.0/series/9332/revisions/1/mbox Test drv_hangman: Subgroup error-state-basic: pass -> FAIL (ro-skl3-i5-6260u) Test drv_module_reload_basic: dmesg-warn -> DMESG-FAIL (ro-skl3-i5-6260u) Test gem_busy: Subgroup basic-blt: pass -> SKIP (ro-skl3-i5-6260u) Subgroup basic-bsd: pass -> SKIP (ro-skl3-i5-6260u) Subgroup basic-bsd1: pass -> SKIP (ro-skl3-i5-6260u) Subgroup basic-bsd2: pass -> SKIP (ro-skl3-i5-6260u) Subgroup basic-parallel-blt: pass -> SKIP (ro-skl3-i5-6260u) Subgroup basic-parallel-bsd: pass -> SKIP (ro-skl3-i5-6260u) Subgroup basic-parallel-bsd1: pass -> SKIP (ro-skl3-i5-6260u) Subgroup basic-parallel-bsd2: pass -> SKIP (ro-skl3-i5-6260u) Subgroup basic-parallel-render: pass -> SKIP (ro-skl3-i5-6260u) Subgroup basic-parallel-vebox: pass -> SKIP (ro-skl3-i5-6260u) Subgroup basic-render: pass -> SKIP (ro-skl3-i5-6260u) Subgroup basic-vebox: pass -> SKIP (ro-skl3-i5-6260u) Test gem_cpu_reloc: Subgroup basic: pass -> FAIL (ro-skl3-i5-6260u) Test gem_cs_tlb: Subgroup basic-default: pass -> FAIL (ro-skl3-i5-6260u) Test gem_ctx_create: Subgroup basic-files: pass -> FAIL (ro-skl3-i5-6260u) Test gem_ctx_exec: Subgroup basic: pass -> FAIL (ro-skl3-i5-6260u) Test gem_ctx_switch: Subgroup basic-default: pass -> SKIP (ro-skl3-i5-6260u) Test gem_exec_basic: Subgroup basic-blt: pass -> FAIL (ro-skl3-i5-6260u) Subgroup basic-bsd: pass -> FAIL (ro-skl3-i5-6260u) Subgroup basic-bsd1: pass -> FAIL (ro-skl3-i5-6260u) Subgroup basic-bsd2: pass -> FAIL (ro-skl3-i5-6260u) Subgroup basic-default: pass -> FAIL (ro-skl3-i5-6260u) Subgroup basic-render: pass -> FAIL (ro-skl3-i5-6260u) Subgroup basic-vebox: pass -> FAIL (ro-skl3-i5-6260u) Subgroup gtt-blt: pass -> FAIL (ro-skl3-i5-6260u) Subgroup gtt-bsd: pass -> FAIL (ro-skl3-i5-6260u) Subgroup gtt-bsd1: pass -> FAIL (ro-skl3-i5-6260u) Subgroup gtt-bsd2: pass -> FAIL (ro-skl3-i5-6260u) Subgroup gtt-default: pass -> FAIL (ro-skl3-i5-6260u) Subgroup gtt-render: pass -> FAIL (ro-skl3-i5-6260u) Subgroup gtt-vebox: pass -> FAIL (ro-skl3-i5-6260u) Subgroup readonly-blt: pass -> FAIL (ro-skl3-i5-6260u) Subgroup readonly-bsd: pass -> FAIL (ro-skl3-i5-6260u) Subgroup readonly-bsd1: pass -> FAIL (ro-skl3-i5-6260u) Subgroup readonly-bsd2: pass -> FAIL (ro-skl3-i5-6260u) Subgroup readonly-default: pass -> FAIL (ro-skl3-i5-6260u) Subgroup readonly-render: pass -> FAIL (ro-skl3-i5-6260u) Subgroup readonly-vebox: pass -> FAIL (ro-skl3-i5-6260u) Test gem_exec_create: Subgroup basic: pass -> FAIL (ro-skl3-i5-6260u) Test gem_exec_flush: Subgroup basic-batch-kernel-default-cmd: pass -> FAIL (ro-byt-n2820) Subgroup basic-batch-kernel-default-uc: pass -> FAIL (ro-skl3-i5-6260u) Subgroup basic-batch-kernel-default-wb: WARNING: Long output truncated fi-hsw-i7-4770k failed to connect after reboot ro-bdw-i7-5557U failed to connect after reboot Results at /archive/results/CI_IGT_test/RO_Patchwork_1348/ b538380 drm-intel-nightly: 2016y-06m-30d-16h-21m-05s UTC integration manifest 1531fb6 i915/guc: Add Kabylake GuC Loading b3f31a8 Revert "drm/i915/kbl: drm/i915: Avoid GuC loading
[Intel-gfx] [PATCH 2/2] drm/i915/guc: Demote some firmware loading messages to debug
From: Tvrtko Ursulin
These messages are not errors unless GuC loading or submission is
in the mandatory mode and even then the final status will be
logged as error in intel_guc_setup.
Therefore demote the messages in guc_fw_fetch to DRM_DEBUG_DRIVER.
If more detail about the cause of the fail is required users will
be asked to dial up the debug level.
v2: Demote signature error in guc_ucode_xfer_dma as well.
Signed-off-by: Tvrtko Ursulin
Reported-by: Chris Wilson
Cc: Dave Gordon
Acked-by: Chris Wilson
---
drivers/gpu/drm/i915/intel_guc_loader.c | 16 +++-
1 file changed, 7 insertions(+), 9 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_guc_loader.c
b/drivers/gpu/drm/i915/intel_guc_loader.c
index e5fa3932bf54..5a646a1f16e5 100644
--- a/drivers/gpu/drm/i915/intel_guc_loader.c
+++ b/drivers/gpu/drm/i915/intel_guc_loader.c
@@ -300,7 +300,7 @@ static int guc_ucode_xfer_dma(struct drm_i915_private
*dev_priv)
I915_READ(DMA_CTRL), status);
if ((status & GS_BOOTROM_MASK) == GS_BOOTROM_RSA_FAILED) {
- DRM_ERROR("GuC firmware signature verification failed\n");
+ DRM_DEBUG_DRIVER("GuC firmware signature verification
failed\n");
ret = -ENOEXEC;
}
@@ -583,7 +583,7 @@ static void guc_fw_fetch(struct drm_device *dev, struct
intel_guc_fw *guc_fw)
/* Check the size of the blob before examining buffer contents */
if (fw->size < sizeof(struct guc_css_header)) {
- DRM_ERROR("Firmware header is missing\n");
+ DRM_DEBUG_DRIVER("Firmware header is missing\n");
goto fail;
}
@@ -595,7 +595,7 @@ static void guc_fw_fetch(struct drm_device *dev, struct
intel_guc_fw *guc_fw)
css->key_size_dw - css->exponent_size_dw) * sizeof(u32);
if (guc_fw->header_size != sizeof(struct guc_css_header)) {
- DRM_ERROR("CSS header definition mismatch\n");
+ DRM_DEBUG_DRIVER("CSS header definition mismatch\n");
goto fail;
}
@@ -605,7 +605,7 @@ static void guc_fw_fetch(struct drm_device *dev, struct
intel_guc_fw *guc_fw)
/* now RSA */
if (css->key_size_dw != UOS_RSA_SCRATCH_MAX_COUNT) {
- DRM_ERROR("RSA key size is bad\n");
+ DRM_DEBUG_DRIVER("RSA key size is bad\n");
goto fail;
}
guc_fw->rsa_offset = guc_fw->ucode_offset + guc_fw->ucode_size;
@@ -614,14 +614,14 @@ static void guc_fw_fetch(struct drm_device *dev, struct
intel_guc_fw *guc_fw)
/* At least, it should have header, uCode and RSA. Size of all three. */
size = guc_fw->header_size + guc_fw->ucode_size + guc_fw->rsa_size;
if (fw->size < size) {
- DRM_ERROR("Missing firmware components\n");
+ DRM_DEBUG_DRIVER("Missing firmware components\n");
goto fail;
}
/* Header and uCode will be loaded to WOPCM. Size of the two. */
size = guc_fw->header_size + guc_fw->ucode_size;
if (size > guc_wopcm_size(dev->dev_private)) {
- DRM_ERROR("Firmware is too large to fit in WOPCM\n");
+ DRM_DEBUG_DRIVER("Firmware is too large to fit in WOPCM\n");
goto fail;
}
@@ -636,7 +636,7 @@ static void guc_fw_fetch(struct drm_device *dev, struct
intel_guc_fw *guc_fw)
if (guc_fw->guc_fw_major_found != guc_fw->guc_fw_major_wanted ||
guc_fw->guc_fw_minor_found < guc_fw->guc_fw_minor_wanted) {
- DRM_ERROR("GuC firmware version %d.%d, required %d.%d\n",
+ DRM_DEBUG_DRIVER("GuC firmware version %d.%d, required %d.%d\n",
guc_fw->guc_fw_major_found, guc_fw->guc_fw_minor_found,
guc_fw->guc_fw_major_wanted,
guc_fw->guc_fw_minor_wanted);
err = -ENOEXEC;
@@ -668,8 +668,6 @@ static void guc_fw_fetch(struct drm_device *dev, struct
intel_guc_fw *guc_fw)
fail:
DRM_DEBUG_DRIVER("GuC fw fetch status FAIL; err %d, fw %p, obj %p\n",
err, fw, guc_fw->guc_fw_obj);
- DRM_ERROR("Failed to fetch GuC firmware from %s (error %d)\n",
- guc_fw->guc_fw_path, err);
mutex_lock(&dev->struct_mutex);
obj = guc_fw->guc_fw_obj;
--
1.9.1
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[Intel-gfx] [PATCH 1/2] drm/i915/guc: Consolidate firmware major-minor to one place
From: Tvrtko Ursulin
Currently to change the firmware one has to update the exported
module firmware string and the major-minor versions used for
verification after load. Consolidate that to a single place
defining correct major and minor versions per platform.
v2: Rebased for KBL.
Signed-off-by: Tvrtko Ursulin
Cc: Dave Gordon
Cc: Rodrigo Vivi
Cc: Peter Antoine
Cc: Michel Thierry
Reviewed-by: Dave Gordon (v1)
---
drivers/gpu/drm/i915/intel_guc_loader.c | 30 +-
1 file changed, 21 insertions(+), 9 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_guc_loader.c
b/drivers/gpu/drm/i915/intel_guc_loader.c
index d80b617ad9af..e5fa3932bf54 100644
--- a/drivers/gpu/drm/i915/intel_guc_loader.c
+++ b/drivers/gpu/drm/i915/intel_guc_loader.c
@@ -59,13 +59,25 @@
*
*/
-#define I915_SKL_GUC_UCODE "i915/skl_guc_ver6_1.bin"
+#define SKL_FW_MAJOR 6
+#define SKL_FW_MINOR 1
+
+#define BXT_FW_MAJOR 8
+#define BXT_FW_MINOR 7
+
+#define KBL_FW_MAJOR 9
+#define KBL_FW_MINOR 14
+
+#define GUC_FW_PATH(platform, major, minor) \
+ "i915/" __stringify(platform) "_guc_ver" __stringify(major) "_"
__stringify(minor) ".bin"
+
+#define I915_SKL_GUC_UCODE GUC_FW_PATH(skl, SKL_FW_MAJOR, SKL_FW_MINOR)
MODULE_FIRMWARE(I915_SKL_GUC_UCODE);
-#define I915_BXT_GUC_UCODE "i915/bxt_guc_ver8_7.bin"
+#define I915_BXT_GUC_UCODE GUC_FW_PATH(bxt, BXT_FW_MAJOR, BXT_FW_MINOR)
MODULE_FIRMWARE(I915_BXT_GUC_UCODE);
-#define I915_KBL_GUC_UCODE "i915/kbl_guc_ver9_14.bin"
+#define I915_KBL_GUC_UCODE GUC_FW_PATH(kbl, KBL_FW_MAJOR, KBL_FW_MINOR)
MODULE_FIRMWARE(I915_KBL_GUC_UCODE);
/* User-friendly representation of an enum */
@@ -695,16 +707,16 @@ void intel_guc_init(struct drm_device *dev)
fw_path = NULL;
} else if (IS_SKYLAKE(dev)) {
fw_path = I915_SKL_GUC_UCODE;
- guc_fw->guc_fw_major_wanted = 6;
- guc_fw->guc_fw_minor_wanted = 1;
+ guc_fw->guc_fw_major_wanted = SKL_FW_MAJOR;
+ guc_fw->guc_fw_minor_wanted = SKL_FW_MINOR;
} else if (IS_BROXTON(dev)) {
fw_path = I915_BXT_GUC_UCODE;
- guc_fw->guc_fw_major_wanted = 8;
- guc_fw->guc_fw_minor_wanted = 7;
+ guc_fw->guc_fw_major_wanted = BXT_FW_MAJOR;
+ guc_fw->guc_fw_minor_wanted = BXT_FW_MINOR;
} else if (IS_KABYLAKE(dev)) {
fw_path = I915_KBL_GUC_UCODE;
- guc_fw->guc_fw_major_wanted = 9;
- guc_fw->guc_fw_minor_wanted = 14;
+ guc_fw->guc_fw_major_wanted = KBL_FW_MAJOR;
+ guc_fw->guc_fw_minor_wanted = KBL_FW_MINOR;
} else {
fw_path = ""; /* unknown device */
}
--
1.9.1
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[Intel-gfx] [CI 2/2] drm/i915: convert a few more E->dev_private to to_i915(E)
From: Dave Gordon
Also remove some redundant dev and dev_priv locals
Signed-off-by: Dave Gordon
Cc: Chris Wilson
Link:
http://patchwork.freedesktop.org/patch/msgid/1467626365-29871-1-git-send-email-david.s.gor...@intel.com
Reviewed-by: Chris Wilson
Signed-off-by: Chris Wilson
---
drivers/gpu/drm/i915/i915_gem.c | 4 ++--
drivers/gpu/drm/i915/intel_display.c| 4
drivers/gpu/drm/i915/intel_guc_loader.c | 2 +-
3 files changed, 3 insertions(+), 7 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
index 7a88840b59fa..a7852dd0a3d4 100644
--- a/drivers/gpu/drm/i915/i915_gem.c
+++ b/drivers/gpu/drm/i915/i915_gem.c
@@ -4772,7 +4772,7 @@ void i915_gem_object_init(struct drm_i915_gem_object *obj,
obj->fence_reg = I915_FENCE_REG_NONE;
obj->madv = I915_MADV_WILLNEED;
- i915_gem_info_add_obj(obj->base.dev->dev_private, obj->base.size);
+ i915_gem_info_add_obj(to_i915(obj->base.dev), obj->base.size);
}
static const struct drm_i915_gem_object_ops i915_gem_object_ops = {
@@ -5398,7 +5398,7 @@ int i915_gem_open(struct drm_device *dev, struct drm_file
*file)
return -ENOMEM;
file->driver_priv = file_priv;
- file_priv->dev_priv = dev->dev_private;
+ file_priv->dev_priv = to_i915(dev);
file_priv->file = file;
INIT_LIST_HEAD(&file_priv->rps.link);
diff --git a/drivers/gpu/drm/i915/intel_display.c
b/drivers/gpu/drm/i915/intel_display.c
index c3c620b4f589..4ff6e9304ef1 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -14144,15 +14144,11 @@ int
skl_max_scale(struct intel_crtc *intel_crtc, struct intel_crtc_state
*crtc_state)
{
int max_scale;
- struct drm_device *dev;
- struct drm_i915_private *dev_priv;
int crtc_clock, cdclk;
if (!intel_crtc || !crtc_state->base.enable)
return DRM_PLANE_HELPER_NO_SCALING;
- dev = intel_crtc->base.dev;
- dev_priv = dev->dev_private;
crtc_clock = crtc_state->base.adjusted_mode.crtc_clock;
cdclk = to_intel_atomic_state(crtc_state->base.state)->cdclk;
diff --git a/drivers/gpu/drm/i915/intel_guc_loader.c
b/drivers/gpu/drm/i915/intel_guc_loader.c
index 7d8cc3e90b34..d925e2daeb24 100644
--- a/drivers/gpu/drm/i915/intel_guc_loader.c
+++ b/drivers/gpu/drm/i915/intel_guc_loader.c
@@ -608,7 +608,7 @@ static void guc_fw_fetch(struct drm_device *dev, struct
intel_guc_fw *guc_fw)
/* Header and uCode will be loaded to WOPCM. Size of the two. */
size = guc_fw->header_size + guc_fw->ucode_size;
- if (size > guc_wopcm_size(dev->dev_private)) {
+ if (size > guc_wopcm_size(to_i915(dev))) {
DRM_ERROR("Firmware is too large to fit in WOPCM\n");
goto fail;
}
--
2.8.1
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Re: [Intel-gfx] [PATCH] drm/i915: convert a few more E->dev_private to to_i915(E)
On Mon, Jul 04, 2016 at 10:59:25AM +0100, Dave Gordon wrote: > Also remove some redundant dev and dev_priv locals > > Signed-off-by: Dave Gordon > Cc: Chris Wilson Reviewed-by: Chris Wilson Picked up as a partner to the mass conversion, and resent to CI. -Chris -- Chris Wilson, Intel Open Source Technology Centre ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH] drm/i915: tidy up request alloc
On 04/07/16 05:08, Liu, Hong wrote:
On Fri, 2016-07-01 at 19:34 +0100, Chris Wilson wrote:
On Fri, Jul 01, 2016 at 05:58:18PM +0100, Dave Gordon wrote:
On 30/06/16 13:49, Tvrtko Ursulin wrote:
On 30/06/16 11:22, Chris Wilson wrote:
On Thu, Jun 30, 2016 at 09:50:20AM +0100, Tvrtko Ursulin wrote:
On 30/06/16 02:35, Hong Liu wrote:
Return the allocated request pointer directly to remove
the double pointer parameter.
Signed-off-by: Hong Liu
---
drivers/gpu/drm/i915/i915_gem.c | 25 +++
--
1 file changed, 7 insertions(+), 18 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_gem.c
b/drivers/gpu/drm/i915/i915_gem.c
index 1d98782..9881455 100644
--- a/drivers/gpu/drm/i915/i915_gem.c
+++ b/drivers/gpu/drm/i915/i915_gem.c
@@ -2988,32 +2988,26 @@ void i915_gem_request_free(struct
kref
*req_ref)
kmem_cache_free(req->i915->requests, req);
}
-static inline int
+static inline struct drm_i915_gem_request *
__i915_gem_request_alloc(struct intel_engine_cs *engine,
- struct i915_gem_context *ctx,
- struct drm_i915_gem_request **req_out)
+ struct i915_gem_context *ctx)
{
struct drm_i915_private *dev_priv = engine->i915;
unsigned reset_counter =
i915_reset_counter(&dev_priv->gpu_error);
struct drm_i915_gem_request *req;
int ret;
-if (!req_out)
-return -EINVAL;
-
-*req_out = NULL;
-
/* ABI: Before userspace accesses the GPU (e.g.
execbuffer),
report
* EIO if the GPU is already wedged, or EAGAIN to drop
the
struct_mutex
* and restart.
*/
ret = i915_gem_check_wedge(reset_counter,
dev_priv->mm.interruptible);
if (ret)
-return ret;
+return ERR_PTR(ret);
req = kmem_cache_zalloc(dev_priv->requests,
GFP_KERNEL);
if (req == NULL)
-return -ENOMEM;
+return ERR_PTR(-ENOMEM);
ret = i915_gem_get_seqno(engine->i915, &req->seqno);
if (ret)
@@ -3041,14 +3035,13 @@ __i915_gem_request_alloc(struct
intel_engine_cs *engine,
if (ret)
goto err_ctx;
-*req_out = req;
-return 0;
+return req;
err_ctx:
i915_gem_context_unreference(ctx);
err:
kmem_cache_free(dev_priv->requests, req);
-return ret;
+return ERR_PTR(ret);
}
/**
@@ -3067,13 +3060,9 @@ struct drm_i915_gem_request *
i915_gem_request_alloc(struct intel_engine_cs *engine,
struct i915_gem_context *ctx)
{
-struct drm_i915_gem_request *req;
-int err;
-
if (ctx == NULL)
ctx = engine->i915->kernel_context;
-err = __i915_gem_request_alloc(engine, ctx, &req);
-return err ? ERR_PTR(err) : req;
+return __i915_gem_request_alloc(engine, ctx);
}
struct drm_i915_gem_request *
Looks good to me. And have this feeling I've seen this
somewhere before.
Several times. This is not the full tidy, nor does it realise
the ramifactions of request alloc through the stack.
Hm I can't spot that it is doing anything wrong or making
anything worse. You don't want to let the small cleanup in?
Regards,
Tvrtko
It ought to make almost no difference, because the *only* place the
inner function is called is from the outer one, which passes a
pointer to a local for the returned object; and the inner one is
then inlined, so the compiler doesn't actually put it on the stack
and call to the inner allocator anyway.
Strangely, however, with this change the code becomes ~400 bytes
bigger!
Disassembly reveals that while the code for the externally-callable
outer function is indeed almost identical, a second copy of it has
also been inlined at the one callsite in this file:
__i915_gem_object_sync() ...
req = i915_gem_request_alloc(to, NULL);
I don't think that's a critical path and would rather have 400
bytes
smaller codespace. We can get that back by adding /noinline/ to the
outer function i915_gem_request_alloc() (not, of course, to the
inner one, that definitely *should* be inline).
__i915_gem_object_sync() should not be calling
i915_gem_request_alloc().
That's the issue with this patch, your patch and John's patch.
So we wrote the i915_gem_request_alloc() this way is to avoid being
inlined into callers like __i915_gem_object_sync()?
Not specifically, as the description of commit 268270883 says,
"... this patch renames the existing i915_gem_request_alloc(), and
makes it local (static inline), and replaces it with a wrapper that
provides a default if the context is NULL, and also has a nicer
calling convention (doesn't require a pointer to an output parameter).
Then we change all callers to use the new convention:
OLD:
err = i915_gem_request_alloc(ring, user_ctx, &req);
if (err) ...
NEW:
req = i915_gem_request_alloc(ring, user_ctx);
if (IS_ERR(req)) ...
OLD:
err = i915_gem_request_alloc(ring, ring->default_context, &req);
if (err) ...
NEW:
req = i915_gem_request_alloc(ring, NULL);
if (IS_
[Intel-gfx] ✗ Ro.CI.BAT: failure for drm/i915: Mass convert dev->dev_private to to_i915(dev) (rev2)
== Series Details == Series: drm/i915: Mass convert dev->dev_private to to_i915(dev) (rev2) URL : https://patchwork.freedesktop.org/series/9385/ State : failure == Summary == Series 9385v2 drm/i915: Mass convert dev->dev_private to to_i915(dev) http://patchwork.freedesktop.org/api/1.0/series/9385/revisions/2/mbox Test gem_exec_flush: Subgroup basic-batch-kernel-default-uc: pass -> DMESG-FAIL (ro-bdw-i7-5557U) Subgroup basic-batch-kernel-default-wb: dmesg-fail -> PASS (fi-skl-i5-6260u) Test kms_pipe_crc_basic: Subgroup nonblocking-crc-pipe-b-frame-sequence: pass -> FAIL (fi-skl-i5-6260u) fi-kbl-qkkr total:231 pass:161 dwarn:29 dfail:0 fail:2 skip:39 fi-skl-i5-6260u total:231 pass:203 dwarn:0 dfail:0 fail:3 skip:25 fi-skl-i7-6700k total:231 pass:190 dwarn:0 dfail:0 fail:2 skip:39 fi-snb-i7-2600 total:231 pass:176 dwarn:0 dfail:0 fail:2 skip:53 ro-bdw-i5-5250u total:229 pass:203 dwarn:1 dfail:1 fail:1 skip:23 ro-bdw-i7-5557U total:229 pass:203 dwarn:1 dfail:2 fail:0 skip:23 ro-bdw-i7-5600u total:229 pass:190 dwarn:0 dfail:1 fail:0 skip:38 ro-bsw-n3050 total:229 pass:177 dwarn:0 dfail:1 fail:2 skip:49 ro-byt-n2820 total:229 pass:180 dwarn:0 dfail:1 fail:3 skip:45 ro-hsw-i7-4770r total:229 pass:197 dwarn:0 dfail:1 fail:0 skip:31 ro-ilk-i7-620lm total:229 pass:157 dwarn:0 dfail:1 fail:1 skip:70 ro-ilk1-i5-650 total:224 pass:157 dwarn:0 dfail:1 fail:1 skip:65 ro-ivb-i7-3770 total:229 pass:188 dwarn:0 dfail:1 fail:0 skip:40 ro-skl3-i5-6260u total:229 pass:207 dwarn:1 dfail:2 fail:0 skip:19 ro-snb-i7-2620M total:229 pass:179 dwarn:0 dfail:1 fail:1 skip:48 Results at /archive/results/CI_IGT_test/RO_Patchwork_1395/ fd3dc6a drm-intel-nightly: 2016y-07m-04d-09h-34m-03s UTC integration manifest eb19db7 drm/i915: convert a few more E->dev_private to to_i915(E) ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✗ Ro.CI.BAT: failure for series starting with [1/2] drm/i915/guc: Consolidate firmware major-minor to one place
== Series Details == Series: series starting with [1/2] drm/i915/guc: Consolidate firmware major-minor to one place URL : https://patchwork.freedesktop.org/series/9457/ State : failure == Summary == Series 9457v1 Series without cover letter http://patchwork.freedesktop.org/api/1.0/series/9457/revisions/1/mbox Test gem_exec_flush: Subgroup basic-batch-kernel-default-cmd: pass -> FAIL (ro-byt-n2820) Subgroup basic-batch-kernel-default-uc: pass -> DMESG-FAIL (fi-skl-i7-6700k) Subgroup basic-batch-kernel-default-wb: pass -> DMESG-FAIL (ro-bdw-i7-5557U) Subgroup basic-wb-pro-default: pass -> DMESG-WARN (ro-ivb-i7-3770) Test kms_pipe_crc_basic: Subgroup read-crc-pipe-a-frame-sequence: fail -> PASS (ro-snb-i7-2620M) Subgroup suspend-read-crc-pipe-a: dmesg-warn -> SKIP (ro-bdw-i7-5557U) fi-kbl-qkkr total:231 pass:91 dwarn:21 dfail:3 fail:59 skip:57 fi-skl-i5-6260u total:231 pass:203 dwarn:0 dfail:1 fail:2 skip:25 fi-skl-i7-6700k total:231 pass:189 dwarn:0 dfail:1 fail:2 skip:39 fi-snb-i7-2600 total:231 pass:176 dwarn:0 dfail:0 fail:2 skip:53 ro-bdw-i5-5250u total:229 pass:204 dwarn:1 dfail:1 fail:0 skip:23 ro-bdw-i7-5557U total:229 pass:203 dwarn:1 dfail:2 fail:0 skip:23 ro-bdw-i7-5600u total:229 pass:190 dwarn:0 dfail:1 fail:0 skip:38 ro-bsw-n3050 total:229 pass:176 dwarn:0 dfail:1 fail:2 skip:50 ro-byt-n2820 total:229 pass:180 dwarn:0 dfail:1 fail:3 skip:45 ro-hsw-i3-4010u total:229 pass:197 dwarn:0 dfail:1 fail:0 skip:31 ro-hsw-i7-4770r total:229 pass:197 dwarn:0 dfail:1 fail:0 skip:31 ro-ilk-i7-620lm total:229 pass:157 dwarn:0 dfail:1 fail:1 skip:70 ro-ilk1-i5-650 total:224 pass:157 dwarn:0 dfail:1 fail:1 skip:65 ro-ivb-i7-3770 total:229 pass:187 dwarn:1 dfail:1 fail:0 skip:40 ro-skl3-i5-6260u total:229 pass:112 dwarn:3 dfail:2 fail:74 skip:38 ro-snb-i7-2620M total:229 pass:179 dwarn:0 dfail:1 fail:1 skip:48 Results at /archive/results/CI_IGT_test/RO_Patchwork_1396/ 79fa348 drm-intel-nightly: 2016y-07m-04d-10h-22m-11s UTC integration manifest ae1a1d3 drm/i915/guc: Demote some firmware loading messages to debug d4b44fb drm/i915/guc: Consolidate firmware major-minor to one place ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✗ Ro.CI.BAT: failure for series starting with [CI,1/2] drm/i915: Mass convert dev->dev_private to to_i915(dev)
== Series Details == Series: series starting with [CI,1/2] drm/i915: Mass convert dev->dev_private to to_i915(dev) URL : https://patchwork.freedesktop.org/series/9459/ State : failure == Summary == Series 9459v1 Series without cover letter http://patchwork.freedesktop.org/api/1.0/series/9459/revisions/1/mbox Test gem_exec_flush: Subgroup basic-batch-kernel-default-uc: pass -> DMESG-FAIL (ro-bdw-i7-5557U) dmesg-fail -> PASS (fi-skl-i5-6260u) Test gem_exec_suspend: Subgroup basic-s3: pass -> INCOMPLETE (fi-snb-i7-2600) Test kms_pipe_crc_basic: Subgroup read-crc-pipe-a-frame-sequence: fail -> PASS (ro-snb-i7-2620M) Subgroup suspend-read-crc-pipe-a: dmesg-warn -> SKIP (ro-bdw-i7-5557U) Subgroup suspend-read-crc-pipe-b: skip -> DMESG-WARN (ro-bdw-i5-5250u) fi-kbl-qkkr total:231 pass:91 dwarn:21 dfail:3 fail:59 skip:57 fi-skl-i5-6260u total:231 pass:204 dwarn:0 dfail:0 fail:2 skip:25 fi-skl-i7-6700k total:231 pass:190 dwarn:0 dfail:0 fail:2 skip:39 fi-snb-i7-2600 total:103 pass:72 dwarn:0 dfail:0 fail:0 skip:30 ro-bdw-i5-5250u total:229 pass:204 dwarn:2 dfail:1 fail:0 skip:22 ro-bdw-i7-5557U total:229 pass:203 dwarn:1 dfail:2 fail:0 skip:23 ro-bdw-i7-5600u total:229 pass:190 dwarn:0 dfail:1 fail:0 skip:38 ro-bsw-n3050 total:229 pass:177 dwarn:0 dfail:1 fail:2 skip:49 ro-byt-n2820 total:229 pass:181 dwarn:0 dfail:1 fail:2 skip:45 ro-hsw-i3-4010u total:229 pass:197 dwarn:0 dfail:1 fail:0 skip:31 ro-hsw-i7-4770r total:229 pass:197 dwarn:0 dfail:1 fail:0 skip:31 ro-ilk-i7-620lm total:229 pass:157 dwarn:0 dfail:1 fail:1 skip:70 ro-ilk1-i5-650 total:224 pass:157 dwarn:0 dfail:1 fail:1 skip:65 ro-ivb-i7-3770 total:229 pass:188 dwarn:0 dfail:1 fail:0 skip:40 ro-skl3-i5-6260u total:229 pass:112 dwarn:3 dfail:2 fail:74 skip:38 ro-snb-i7-2620M total:229 pass:179 dwarn:0 dfail:1 fail:1 skip:48 Results at /archive/results/CI_IGT_test/RO_Patchwork_1397/ 79fa348 drm-intel-nightly: 2016y-07m-04d-10h-22m-11s UTC integration manifest 3c028f4 drm/i915: convert a few more E->dev_private to to_i915(E) ba01f3d drm/i915: Mass convert dev->dev_private to to_i915(dev) ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] ✗ Ro.CI.BAT: failure for series starting with [CI,1/2] drm/i915: Mass convert dev->dev_private to to_i915(dev)
On Mon, Jul 04, 2016 at 11:45:57AM -, Patchwork wrote: > == Series Details == > > Series: series starting with [CI,1/2] drm/i915: Mass convert dev->dev_private > to to_i915(dev) > URL : https://patchwork.freedesktop.org/series/9459/ > State : failure > > == Summary == > > Series 9459v1 Series without cover letter > http://patchwork.freedesktop.org/api/1.0/series/9459/revisions/1/mbox > > Test gem_exec_flush: > Subgroup basic-batch-kernel-default-uc: > pass -> DMESG-FAIL (ro-bdw-i7-5557U) > dmesg-fail -> PASS (fi-skl-i5-6260u) > Test gem_exec_suspend: > Subgroup basic-s3: > pass -> INCOMPLETE (fi-snb-i7-2600) Known sporadic failure. No pain, no gain. Apologies to everyone who has to spend the rest of the day rebasing (like myself). -Chris -- Chris Wilson, Intel Open Source Technology Centre ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH driver/intel] sna/cursor: Make sure hw cursors are disabled before disabling secondary planes
On Tue, Jun 21, 2016 at 09:25:36PM +0100, Chris Wilson wrote: > On Tue, Jun 21, 2016 at 07:34:34PM +0200, Egbert Eich wrote: > > When the hw cursors are not disabled before the cursor planes get disabled > > we may lose the cursor later on. Thus make sure the cursors are disabled > > before the cursor planes are. > > The cursor would already be controlled by the xf86SetDesiredModes(), so > we can skip disabling entirely. What we should do instead is add the > paranoia check, but I can't see an easy way to inquire what the kernel > thinks the legacy cursor handle should be. > > commit f1c757e4518f6835bbff6c940269a5c6be75f202 > Author: Chris Wilson > Date: Tue Jun 21 21:17:15 2016 +0100 > > sna: Only shutdown unknown secondary planes on CRTC we control > > In a ZaphodHead scenario, we do not own all the CRTC and so we should > not be making changes outside of our zone of control. Also, we only want > to disable secondary overlay planes and ignore the secondary cursor > planes which are controlled through the normal modesetting. > > As we are now tracking all sprite planes on a CRTC, this leads to much > simpler code. Chris, thanks for the patch! I've been able to test it now - it works. Cheers, Egbert. ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH] drm/i915: Remove use of dev_priv->dev backpointer in __i915_printk()
As we can just directly use drm_dev->drm.dev, we do not need the
drm_dev->dev backpointer anymore and can also loose the warning about
order of __i915_printk() and our initialisation (which is now always
safe).
Signed-off-by: Chris Wilson
Cc: Imre Deak
---
drivers/gpu/drm/i915/i915_drv.c | 3 +--
1 file changed, 1 insertion(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index 695001ffd547..c83355f512ca 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -77,7 +77,7 @@ __i915_printk(struct drm_i915_private *dev_priv, const char
*level,
const char *fmt, ...)
{
static bool shown_bug_once;
- struct device *dev = dev_priv->dev->dev;
+ struct device *dev = dev_priv->drm.dev;
bool is_error = level[1] <= KERN_ERR[1];
bool is_debug = level[1] == KERN_DEBUG[1];
struct va_format vaf;
@@ -1603,7 +1603,6 @@ int i915_driver_load(struct pci_dev *pdev, const struct
pci_device_id *ent)
return ret;
}
- /* Must be set before calling __i915_printk */
dev_priv->drm.pdev = pdev;
dev_priv->drm.dev_private = dev_priv;
dev_priv->dev = &dev_priv->drm;
--
2.8.1
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[Intel-gfx] [PATCH] drm/i915:gen9: implement WaMediaPoolStateCmdInWABB
From: Tim Gore
This patch applies WaMediaPoolStateCmdInWABB which fixes
a problem with the restoration of thread counts on resuming
from RC6.
Signed-off-by: Tim Gore
---
drivers/gpu/drm/i915/intel_lrc.c | 25 +
1 file changed, 25 insertions(+)
diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c
index 676b532..017b25c 100644
--- a/drivers/gpu/drm/i915/intel_lrc.c
+++ b/drivers/gpu/drm/i915/intel_lrc.c
@@ -1296,6 +1296,31 @@ static int gen9_init_indirectctx_bb(struct
intel_engine_cs *engine,
wa_ctx_emit(batch, index, 0);
wa_ctx_emit(batch, index, 0);
}
+
+ /* WaMediaPoolStateCmdInWABB:bxt */
+ if (HAS_POOLED_EU(engine->i915)) {
+ /*
+* EU pool configuration is setup along with golden context
+* during context initialization. This value depends on
+* device type (2x6 or 3x6) and needs to be updated based
+* on which subslice is disabled especially for 2x6
+* devices, however it is safe to load default
+* configuration of 3x6 device instead of masking off
+* corresponding bits because HW ignores bits of a disabled
+* subslice and drops down to appropriate config. Please
+* see render_state_setup() in i915_gem_render_state.c for
+* possible configurations, to avoid duplication they are
+* not shown here again.
+*/
+ u32 eu_pool_config = 0x00777000;
+ wa_ctx_emit(batch, index, GEN9_MEDIA_POOL_STATE);
+ wa_ctx_emit(batch, index, GEN9_MEDIA_POOL_ENABLE);
+ wa_ctx_emit(batch, index, eu_pool_config);
+ wa_ctx_emit(batch, index, 0);
+ wa_ctx_emit(batch, index, 0);
+ wa_ctx_emit(batch, index, 0);
+ }
+
/* Pad to end of cacheline */
while (index % CACHELINE_DWORDS)
wa_ctx_emit(batch, index, MI_NOOP);
--
1.9.1
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[Intel-gfx] ✗ Ro.CI.BAT: failure for drm/i915: Remove use of dev_priv->dev backpointer in __i915_printk()
== Series Details == Series: drm/i915: Remove use of dev_priv->dev backpointer in __i915_printk() URL : https://patchwork.freedesktop.org/series/9463/ State : failure == Summary == Series 9463v1 drm/i915: Remove use of dev_priv->dev backpointer in __i915_printk() http://patchwork.freedesktop.org/api/1.0/series/9463/revisions/1/mbox Test drv_module_reload_basic: pass -> SKIP (fi-skl-i5-6260u) Test gem_exec_flush: Subgroup basic-batch-kernel-default-cmd: fail -> PASS (ro-byt-n2820) Subgroup basic-batch-kernel-default-uc: dmesg-fail -> PASS (ro-bdw-i7-5557U) pass -> DMESG-FAIL (fi-skl-i5-6260u) pass -> DMESG-FAIL (fi-skl-i7-6700k) Subgroup basic-batch-kernel-default-wb: pass -> DMESG-FAIL (ro-bdw-i7-5557U) Test kms_pipe_crc_basic: Subgroup suspend-read-crc-pipe-a: skip -> DMESG-WARN (ro-bdw-i5-5250u) Subgroup suspend-read-crc-pipe-b: dmesg-warn -> SKIP (ro-bdw-i5-5250u) fi-kbl-qkkr total:231 pass:91 dwarn:21 dfail:3 fail:59 skip:57 fi-skl-i5-6260u total:231 pass:202 dwarn:0 dfail:1 fail:2 skip:26 fi-skl-i7-6700k total:103 pass:78 dwarn:0 dfail:1 fail:0 skip:23 fi-snb-i7-2600 total:231 pass:176 dwarn:0 dfail:0 fail:2 skip:53 ro-bdw-i5-5250u total:229 pass:204 dwarn:2 dfail:1 fail:0 skip:22 ro-bdw-i7-5557U total:229 pass:203 dwarn:1 dfail:2 fail:0 skip:23 ro-bdw-i7-5600u total:229 pass:190 dwarn:0 dfail:1 fail:0 skip:38 ro-bsw-n3050 total:229 pass:177 dwarn:0 dfail:1 fail:2 skip:49 ro-byt-n2820 total:229 pass:181 dwarn:0 dfail:1 fail:2 skip:45 ro-hsw-i3-4010u total:229 pass:197 dwarn:0 dfail:1 fail:0 skip:31 ro-hsw-i7-4770r total:229 pass:197 dwarn:0 dfail:1 fail:0 skip:31 ro-ilk-i7-620lm total:229 pass:157 dwarn:0 dfail:1 fail:1 skip:70 ro-ilk1-i5-650 total:224 pass:157 dwarn:0 dfail:1 fail:1 skip:65 ro-ivb-i7-3770 total:229 pass:188 dwarn:0 dfail:1 fail:0 skip:40 ro-skl3-i5-6260u total:229 pass:112 dwarn:3 dfail:2 fail:74 skip:38 ro-snb-i7-2620M total:229 pass:179 dwarn:0 dfail:1 fail:1 skip:48 Results at /archive/results/CI_IGT_test/RO_Patchwork_1401/ 54c86e3 drm-intel-nightly: 2016y-07m-04d-11h-55m-58s UTC integration manifest 2aa190f drm/i915: Remove use of dev_priv->dev backpointer in __i915_printk() ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✗ Ro.CI.BAT: failure for drm/i915:gen9: implement WaMediaPoolStateCmdInWABB
== Series Details == Series: drm/i915:gen9: implement WaMediaPoolStateCmdInWABB URL : https://patchwork.freedesktop.org/series/9467/ State : failure == Summary == Series 9467v1 drm/i915:gen9: implement WaMediaPoolStateCmdInWABB http://patchwork.freedesktop.org/api/1.0/series/9467/revisions/1/mbox Test gem_exec_flush: Subgroup basic-batch-kernel-default-wb: pass -> DMESG-FAIL (fi-skl-i5-6260u) Test kms_flip: Subgroup basic-flip-vs-wf_vblank: pass -> FAIL (ro-bdw-i7-5600u) Test kms_pipe_crc_basic: Subgroup suspend-read-crc-pipe-b: dmesg-warn -> SKIP (ro-bdw-i5-5250u) fi-kbl-qkkr total:231 pass:91 dwarn:21 dfail:3 fail:59 skip:57 fi-skl-i5-6260u total:231 pass:203 dwarn:0 dfail:1 fail:2 skip:25 fi-skl-i7-6700k total:103 pass:79 dwarn:0 dfail:0 fail:0 skip:23 fi-snb-i7-2600 total:231 pass:176 dwarn:0 dfail:0 fail:2 skip:53 ro-bdw-i5-5250u total:229 pass:204 dwarn:1 dfail:1 fail:0 skip:23 ro-bdw-i7-5600u total:229 pass:189 dwarn:0 dfail:1 fail:1 skip:38 ro-byt-n2820 total:229 pass:180 dwarn:0 dfail:1 fail:3 skip:45 ro-hsw-i3-4010u total:229 pass:197 dwarn:0 dfail:1 fail:0 skip:31 ro-hsw-i7-4770r total:229 pass:197 dwarn:0 dfail:1 fail:0 skip:31 ro-ilk-i7-620lm total:229 pass:157 dwarn:0 dfail:1 fail:1 skip:70 ro-ilk1-i5-650 total:224 pass:157 dwarn:0 dfail:1 fail:1 skip:65 ro-ivb-i7-3770 total:229 pass:188 dwarn:0 dfail:1 fail:0 skip:40 ro-skl3-i5-6260u total:229 pass:112 dwarn:3 dfail:2 fail:74 skip:38 ro-snb-i7-2620M total:229 pass:179 dwarn:0 dfail:1 fail:1 skip:48 ro-bdw-i7-5557U failed to connect after reboot ro-bsw-n3050 failed to connect after reboot Results at /archive/results/CI_IGT_test/RO_Patchwork_1402/ 54c86e3 drm-intel-nightly: 2016y-07m-04d-11h-55m-58s UTC integration manifest 42110dd drm/i915:gen9: implement WaMediaPoolStateCmdInWABB ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH v2 i-g-t] demos/intel_sprite_on: Fix connector iteration bug
Applied.
On Wed, Jun 15, 2016 at 10:48:32AM -0700, Jim Bride wrote:
> Instead of looping until the first disconnected port is found,
> now go through all possible connectors, drawing the sprite on
> any connected display.
>
> v2: Print a message if we don't find any valid connectors.
>
> Signed-off-by: Jim Bride
> ---
> demos/intel_sprite_on.c | 11 +--
> 1 file changed, 9 insertions(+), 2 deletions(-)
>
> diff --git a/demos/intel_sprite_on.c b/demos/intel_sprite_on.c
> index 6ed..d3bd420 100644
> --- a/demos/intel_sprite_on.c
> +++ b/demos/intel_sprite_on.c
> @@ -518,6 +518,8 @@ static void ricochet(int tiled, int sprite_w, int
> sprite_h,
> charkey;
> int sprite_plane_count = 0;
> int i;
> + int found_count = 0;
> +
> // Open up I915 graphics device
> gfx_fd = drmOpen("i915", NULL);
> if (gfx_fd < 0) {
> @@ -564,10 +566,15 @@ static void ricochet(int tiled, int sprite_w, int
> sprite_h,
> // Find the native (preferred) display mode
> connector_find_preferred_mode(gfx_fd, gfx_resources,
> &curr_connector);
> if (curr_connector.mode_valid == 0) {
> - printf("No valid preferred mode detected\n");
> - goto out;
> +
> + if (((c_index + 1) == gfx_resources->count_connectors)
> &&
> + (found_count == 0))
> + printf("Failed to find any valid connections.");
> + continue;
> }
>
> + found_count++;
> +
> // Determine if sprite hardware is available on pipe
> // associated with this connector.
> sprite_plane_count = connector_find_plane(gfx_fd,
> &curr_connector,
> --
> 2.7.4
>
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Re: [Intel-gfx] [PATCH i-g-t] configure: update bugzilla URL
Applied. On Wed, Jun 22, 2016 at 07:08:03AM -0400, Mike Frysinger wrote: > Signed-off-by: Mike Frysinger > --- > configure.ac | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > > diff --git a/configure.ac b/configure.ac > index 2e2c3ab7a7b0..d84508b5f6f5 100644 > --- a/configure.ac > +++ b/configure.ac > @@ -23,7 +23,7 @@ > AC_PREREQ([2.60]) > AC_INIT([intel-gpu-tools], > [1.15], > - > [https://bugs.freedesktop.org/enter_bug.cgi?product=DRI&component=DRM/Intel], > + [https://bugs.freedesktop.org/enter_bug.cgi?product=DRI&component=IGT], > [intel-gpu-tools]) > > AC_CONFIG_SRCDIR([Makefile.am]) > -- > 2.8.2 > > ___ > Intel-gfx mailing list > Intel-gfx@lists.freedesktop.org > https://lists.freedesktop.org/mailman/listinfo/intel-gfx signature.asc Description: Digital signature ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH] drm/i915/guc: Protect against HAS_GUC_* returning true values other than one
From: Tvrtko Ursulin
At the moment HAS_GUC_UCODE == HAS_GUC == IS_GEN9 ==
(INTEL_INFO(dev)->gen_mask & BIT(8)), which is true but not one. And
module parameters are integers and not booleans so compiler will not
normalize the value for us.
Quick and easy fix for the GuC loading code and the whole area can
be evaluated afterwards.
Signed-off-by: Tvrtko Ursulin
Reported-by: Chris Wilson
Cc: Dave Gordon
---
drivers/gpu/drm/i915/intel_guc_loader.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_guc_loader.c
b/drivers/gpu/drm/i915/intel_guc_loader.c
index d925e2daeb24..72ea5b97e242 100644
--- a/drivers/gpu/drm/i915/intel_guc_loader.c
+++ b/drivers/gpu/drm/i915/intel_guc_loader.c
@@ -687,9 +687,9 @@ void intel_guc_init(struct drm_device *dev)
/* A negative value means "use platform default" */
if (i915.enable_guc_loading < 0)
- i915.enable_guc_loading = HAS_GUC_UCODE(dev);
+ i915.enable_guc_loading = !!HAS_GUC_UCODE(dev);
if (i915.enable_guc_submission < 0)
- i915.enable_guc_submission = HAS_GUC_SCHED(dev);
+ i915.enable_guc_submission = !!HAS_GUC_SCHED(dev);
if (!HAS_GUC_UCODE(dev)) {
fw_path = NULL;
--
1.9.1
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Re: [Intel-gfx] [PACTH i-g-t v1] lib/igt_gt: Fix unused variable warning for non-x86 targets
Applied.
On Mon, Jun 27, 2016 at 06:58:24AM -0400, robert.f...@collabora.com wrote:
> From: Robert Foss
>
> Moved variable declaration inside #if case to avoid unused variable warnings
> on non-x86 targets.
>
> Signed-off-by: Robert Foss
> ---
> lib/igt_gt.c | 3 ++-
> 1 file changed, 2 insertions(+), 1 deletion(-)
>
> diff --git a/lib/igt_gt.c b/lib/igt_gt.c
> index a3d6a73..8a53775 100644
> --- a/lib/igt_gt.c
> +++ b/lib/igt_gt.c
> @@ -383,9 +383,10 @@ int igt_open_forcewake_handle(void)
> return -1;
> return igt_debugfs_open("i915_forcewake_user", O_WRONLY);
> }
> -static unsigned int clflush_size;
>
> #if defined(__x86_64__) || defined(__i386__)
> +static unsigned int clflush_size;
> +
> int igt_setup_clflush(void)
> {
> FILE *file;
> --
> 2.7.4
>
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[Intel-gfx] [PATCH] drm/i915: Explicitly convert some macros to boolean values
From: Tvrtko Ursulin
Some IS_ and HAS_ macros can return any non-zero value for true.
One potential problem with that is that someone could assign
them to integers and be surprised with the result. Therefore it
is probably safer to do the conversion to 0/1 in the macros
themselves.
Luckily this does not seem to have an effect on code size.
Only one call site was getting bit by this and a patch for
that has been sent as "drm/i915/guc: Protect against HAS_GUC_*
returning true values other than one".
Signed-off-by: Tvrtko Ursulin
---
drivers/gpu/drm/i915/i915_drv.h | 20 ++--
1 file changed, 10 insertions(+), 10 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 04a7423cd67f..534b8a8f41bf 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -2762,14 +2762,14 @@ struct drm_i915_cmd_table {
* have their own (e.g. HAS_PCH_SPLIT for ILK+ display, IS_foo for particular
* chips, etc.).
*/
-#define IS_GEN2(dev) (INTEL_INFO(dev)->gen_mask & BIT(1))
-#define IS_GEN3(dev) (INTEL_INFO(dev)->gen_mask & BIT(2))
-#define IS_GEN4(dev) (INTEL_INFO(dev)->gen_mask & BIT(3))
-#define IS_GEN5(dev) (INTEL_INFO(dev)->gen_mask & BIT(4))
-#define IS_GEN6(dev) (INTEL_INFO(dev)->gen_mask & BIT(5))
-#define IS_GEN7(dev) (INTEL_INFO(dev)->gen_mask & BIT(6))
-#define IS_GEN8(dev) (INTEL_INFO(dev)->gen_mask & BIT(7))
-#define IS_GEN9(dev) (INTEL_INFO(dev)->gen_mask & BIT(8))
+#define IS_GEN2(dev) !!(INTEL_INFO(dev)->gen_mask & BIT(1))
+#define IS_GEN3(dev) !!(INTEL_INFO(dev)->gen_mask & BIT(2))
+#define IS_GEN4(dev) !!(INTEL_INFO(dev)->gen_mask & BIT(3))
+#define IS_GEN5(dev) !!(INTEL_INFO(dev)->gen_mask & BIT(4))
+#define IS_GEN6(dev) !!(INTEL_INFO(dev)->gen_mask & BIT(5))
+#define IS_GEN7(dev) !!(INTEL_INFO(dev)->gen_mask & BIT(6))
+#define IS_GEN8(dev) !!(INTEL_INFO(dev)->gen_mask & BIT(7))
+#define IS_GEN9(dev) !!(INTEL_INFO(dev)->gen_mask & BIT(8))
#define ENGINE_MASK(id)BIT(id)
#define RENDER_RINGENGINE_MASK(RCS)
@@ -2780,7 +2780,7 @@ struct drm_i915_cmd_table {
#define ALL_ENGINES(~0)
#define HAS_ENGINE(dev_priv, id) \
- (INTEL_INFO(dev_priv)->ring_mask & ENGINE_MASK(id))
+ !!(INTEL_INFO(dev_priv)->ring_mask & ENGINE_MASK(id))
#define HAS_BSD(dev_priv) HAS_ENGINE(dev_priv, VCS)
#define HAS_BSD2(dev_priv) HAS_ENGINE(dev_priv, VCS2)
@@ -2789,7 +2789,7 @@ struct drm_i915_cmd_table {
#define HAS_LLC(dev) (INTEL_INFO(dev)->has_llc)
#define HAS_SNOOP(dev) (INTEL_INFO(dev)->has_snoop)
-#define HAS_EDRAM(dev) (__I915__(dev)->edram_cap & EDRAM_ENABLED)
+#define HAS_EDRAM(dev) !!(__I915__(dev)->edram_cap & EDRAM_ENABLED)
#define HAS_WT(dev)((IS_HASWELL(dev) || IS_BROADWELL(dev)) && \
HAS_EDRAM(dev))
#define I915_NEED_GFX_HWS(dev) (INTEL_INFO(dev)->need_gfx_hws)
--
1.9.1
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Re: [Intel-gfx] [PATCH] drm/i915/guc: Protect against HAS_GUC_* returning true values other than one
On Mon, Jul 04, 2016 at 03:30:33PM +0100, Tvrtko Ursulin wrote: > From: Tvrtko Ursulin > > At the moment HAS_GUC_UCODE == HAS_GUC == IS_GEN9 == > (INTEL_INFO(dev)->gen_mask & BIT(8)), which is true but not one. And > module parameters are integers and not booleans so compiler will not > normalize the value for us. > > Quick and easy fix for the GuC loading code and the whole area can > be evaluated afterwards. > > Signed-off-by: Tvrtko Ursulin > Reported-by: Chris Wilson Tested-by: Chris Wilson I still have 3 message (not all error though) telling me it failed to load the firmware... -Chris -- Chris Wilson, Intel Open Source Technology Centre ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✗ Ro.CI.BAT: warning for drm/i915/guc: Protect against HAS_GUC_* returning true values other than one
== Series Details == Series: drm/i915/guc: Protect against HAS_GUC_* returning true values other than one URL : https://patchwork.freedesktop.org/series/9473/ State : warning == Summary == Series 9473v1 drm/i915/guc: Protect against HAS_GUC_* returning true values other than one http://patchwork.freedesktop.org/api/1.0/series/9473/revisions/1/mbox Test drv_hangman: Subgroup error-state-basic: fail -> PASS (ro-skl3-i5-6260u) Test drv_module_reload_basic: pass -> DMESG-WARN (ro-bdw-i7-5600u) dmesg-fail -> DMESG-WARN (ro-skl3-i5-6260u) Test gem_busy: Subgroup basic-blt: skip -> PASS (ro-skl3-i5-6260u) Subgroup basic-bsd: skip -> PASS (ro-skl3-i5-6260u) Subgroup basic-bsd1: skip -> PASS (ro-skl3-i5-6260u) Subgroup basic-bsd2: skip -> PASS (ro-skl3-i5-6260u) Subgroup basic-parallel-blt: skip -> PASS (ro-skl3-i5-6260u) Subgroup basic-parallel-bsd: skip -> PASS (ro-skl3-i5-6260u) Subgroup basic-parallel-bsd1: skip -> PASS (ro-skl3-i5-6260u) Subgroup basic-parallel-bsd2: skip -> PASS (ro-skl3-i5-6260u) Subgroup basic-parallel-render: skip -> PASS (ro-skl3-i5-6260u) Subgroup basic-parallel-vebox: skip -> PASS (ro-skl3-i5-6260u) Subgroup basic-render: skip -> PASS (ro-skl3-i5-6260u) Subgroup basic-vebox: skip -> PASS (ro-skl3-i5-6260u) Test gem_cpu_reloc: Subgroup basic: fail -> PASS (ro-skl3-i5-6260u) Test gem_cs_tlb: Subgroup basic-default: fail -> PASS (ro-skl3-i5-6260u) Test gem_ctx_create: Subgroup basic-files: fail -> PASS (ro-skl3-i5-6260u) Test gem_ctx_exec: Subgroup basic: fail -> PASS (ro-skl3-i5-6260u) Test gem_ctx_switch: Subgroup basic-default: skip -> PASS (ro-skl3-i5-6260u) Test gem_exec_basic: Subgroup basic-blt: fail -> PASS (ro-skl3-i5-6260u) Subgroup basic-bsd: fail -> PASS (ro-skl3-i5-6260u) Subgroup basic-bsd1: fail -> PASS (ro-skl3-i5-6260u) Subgroup basic-bsd2: fail -> PASS (ro-skl3-i5-6260u) Subgroup basic-default: fail -> PASS (ro-skl3-i5-6260u) Subgroup basic-render: fail -> PASS (ro-skl3-i5-6260u) Subgroup basic-vebox: fail -> PASS (ro-skl3-i5-6260u) Subgroup gtt-blt: fail -> PASS (ro-skl3-i5-6260u) Subgroup gtt-bsd: fail -> PASS (ro-skl3-i5-6260u) Subgroup gtt-bsd1: fail -> PASS (ro-skl3-i5-6260u) Subgroup gtt-bsd2: fail -> PASS (ro-skl3-i5-6260u) Subgroup gtt-default: fail -> PASS (ro-skl3-i5-6260u) Subgroup gtt-render: fail -> PASS (ro-skl3-i5-6260u) Subgroup gtt-vebox: fail -> PASS (ro-skl3-i5-6260u) Subgroup readonly-blt: fail -> PASS (ro-skl3-i5-6260u) Subgroup readonly-bsd: fail -> PASS (ro-skl3-i5-6260u) Subgroup readonly-bsd1: fail -> PASS (ro-skl3-i5-6260u) Subgroup readonly-bsd2: fail -> PASS (ro-skl3-i5-6260u) Subgroup readonly-default: fail -> PASS (ro-skl3-i5-6260u) Subgroup readonly-render: fail -> PASS (ro-skl3-i5-6260u) Subgroup readonly-vebox: fail -> PASS (ro-skl3-i5-6260u) Test gem_exec_create: Subgroup basic: fail -> PASS (ro-skl3-i5-6260u) Test gem_exec_flush: Subgroup basic-batch-kernel-default-uc: fail -> DMESG-FAIL (ro-skl3-i5-6260u) Subgroup basic-batch-kernel-default-wb: fail -> PASS (ro-skl3-i5-6260u) WARNING: Long output truncated fi-skl-i7-6700k failed to connect after reboot ro-ivb-i7-3770 failed to connect after reboot Results at /archive/results/CI_IGT_test/RO_Patchwork_1403/ 54c86e3 drm-intel-nightly: 2016y-07m-04d-11h-55m-58s UTC integration manifest 8a49606 drm/i915/guc: Protect against HAS_GUC_* returning true values other than one ___ Intel-gfx mailing list Intel-gfx@lists.freedeskto
Re: [Intel-gfx] [PATCH] drm/i915: Explicitly convert some macros to boolean values
On Mon, Jul 04, 2016 at 03:50:23PM +0100, Tvrtko Ursulin wrote: > From: Tvrtko Ursulin > > Some IS_ and HAS_ macros can return any non-zero value for true. > > One potential problem with that is that someone could assign > them to integers and be surprised with the result. Therefore it > is probably safer to do the conversion to 0/1 in the macros > themselves. > > Luckily this does not seem to have an effect on code size. Indeed, gcc is quite happy to remove the !! and combine e.g. IS_GEN6() || IS_GEN7() into a single testb. With that, Reviewed-by: Chris Wilson -Chris -- Chris Wilson, Intel Open Source Technology Centre ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✗ Ro.CI.BAT: failure for drm/i915: Explicitly convert some macros to boolean values
== Series Details == Series: drm/i915: Explicitly convert some macros to boolean values URL : https://patchwork.freedesktop.org/series/9475/ State : failure == Summary == Series 9475v1 drm/i915: Explicitly convert some macros to boolean values http://patchwork.freedesktop.org/api/1.0/series/9475/revisions/1/mbox Test drv_hangman: Subgroup error-state-basic: fail -> PASS (ro-skl3-i5-6260u) Test drv_module_reload_basic: dmesg-fail -> DMESG-WARN (ro-skl3-i5-6260u) Test gem_busy: Subgroup basic-blt: skip -> PASS (ro-skl3-i5-6260u) Subgroup basic-bsd: skip -> PASS (ro-skl3-i5-6260u) Subgroup basic-bsd1: skip -> PASS (ro-skl3-i5-6260u) Subgroup basic-bsd2: skip -> PASS (ro-skl3-i5-6260u) Subgroup basic-parallel-blt: skip -> PASS (ro-skl3-i5-6260u) Subgroup basic-parallel-bsd: skip -> PASS (ro-skl3-i5-6260u) Subgroup basic-parallel-bsd1: skip -> PASS (ro-skl3-i5-6260u) Subgroup basic-parallel-bsd2: skip -> PASS (ro-skl3-i5-6260u) Subgroup basic-parallel-render: skip -> PASS (ro-skl3-i5-6260u) Subgroup basic-parallel-vebox: skip -> PASS (ro-skl3-i5-6260u) Subgroup basic-render: skip -> PASS (ro-skl3-i5-6260u) Subgroup basic-vebox: skip -> PASS (ro-skl3-i5-6260u) Test gem_cpu_reloc: Subgroup basic: fail -> PASS (ro-skl3-i5-6260u) Test gem_cs_tlb: Subgroup basic-default: fail -> PASS (ro-skl3-i5-6260u) Test gem_ctx_create: Subgroup basic-files: fail -> PASS (ro-skl3-i5-6260u) Test gem_ctx_exec: Subgroup basic: fail -> PASS (ro-skl3-i5-6260u) Test gem_ctx_switch: Subgroup basic-default: skip -> PASS (ro-skl3-i5-6260u) Test gem_exec_basic: Subgroup basic-blt: fail -> PASS (ro-skl3-i5-6260u) Subgroup basic-bsd: fail -> PASS (ro-skl3-i5-6260u) Subgroup basic-bsd1: fail -> PASS (ro-skl3-i5-6260u) Subgroup basic-bsd2: fail -> PASS (ro-skl3-i5-6260u) Subgroup basic-default: fail -> PASS (ro-skl3-i5-6260u) Subgroup basic-render: fail -> PASS (ro-skl3-i5-6260u) Subgroup basic-vebox: fail -> PASS (ro-skl3-i5-6260u) Subgroup gtt-blt: fail -> PASS (ro-skl3-i5-6260u) Subgroup gtt-bsd: fail -> PASS (ro-skl3-i5-6260u) Subgroup gtt-bsd1: fail -> PASS (ro-skl3-i5-6260u) Subgroup gtt-bsd2: fail -> PASS (ro-skl3-i5-6260u) Subgroup gtt-default: fail -> PASS (ro-skl3-i5-6260u) Subgroup gtt-render: fail -> PASS (ro-skl3-i5-6260u) Subgroup gtt-vebox: fail -> PASS (ro-skl3-i5-6260u) Subgroup readonly-blt: fail -> PASS (ro-skl3-i5-6260u) Subgroup readonly-bsd: fail -> PASS (ro-skl3-i5-6260u) Subgroup readonly-bsd1: fail -> PASS (ro-skl3-i5-6260u) Subgroup readonly-bsd2: fail -> PASS (ro-skl3-i5-6260u) Subgroup readonly-default: fail -> PASS (ro-skl3-i5-6260u) Subgroup readonly-render: fail -> PASS (ro-skl3-i5-6260u) Subgroup readonly-vebox: fail -> PASS (ro-skl3-i5-6260u) Test gem_exec_create: Subgroup basic: fail -> PASS (ro-skl3-i5-6260u) Test gem_exec_flush: Subgroup basic-batch-kernel-default-uc: fail -> PASS (ro-skl3-i5-6260u) dmesg-fail -> PASS (ro-bdw-i7-5557U) pass -> DMESG-FAIL (fi-skl-i5-6260u) pass -> DMESG-FAIL (fi-skl-i7-6700k) WARNING: Long output truncated Results at /archive/results/CI_IGT_test/RO_Patchwork_1404/ 54c86e3 drm-intel-nightly: 2016y-07m-04d-11h-55m-58s UTC integration manifest 3b1ccef2 drm/i915: Explicitly convert some macros to boolean values ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] ✗ Ro.CI.BAT: failure for drm/i915: Explicitly convert some macros to boolean values
On 04/07/16 16:26, Patchwork wrote: == Series Details == Series: drm/i915: Explicitly convert some macros to boolean values URL : https://patchwork.freedesktop.org/series/9475/ State : failure == Summary == Series 9475v1 drm/i915: Explicitly convert some macros to boolean values http://patchwork.freedesktop.org/api/1.0/series/9475/revisions/1/mbox Test drv_hangman: Subgroup error-state-basic: fail -> PASS (ro-skl3-i5-6260u) Test drv_module_reload_basic: dmesg-fail -> DMESG-WARN (ro-skl3-i5-6260u) Raised https://bugs.freedesktop.org/show_bug.cgi?id=96805 to stop logging GuC fw fetch as an error when in fallback mode. Test gem_busy: Subgroup basic-blt: skip -> PASS (ro-skl3-i5-6260u) Subgroup basic-bsd: skip -> PASS (ro-skl3-i5-6260u) Subgroup basic-bsd1: skip -> PASS (ro-skl3-i5-6260u) Subgroup basic-bsd2: skip -> PASS (ro-skl3-i5-6260u) Subgroup basic-parallel-blt: skip -> PASS (ro-skl3-i5-6260u) Subgroup basic-parallel-bsd: skip -> PASS (ro-skl3-i5-6260u) Subgroup basic-parallel-bsd1: skip -> PASS (ro-skl3-i5-6260u) Subgroup basic-parallel-bsd2: skip -> PASS (ro-skl3-i5-6260u) Subgroup basic-parallel-render: skip -> PASS (ro-skl3-i5-6260u) Subgroup basic-parallel-vebox: skip -> PASS (ro-skl3-i5-6260u) Subgroup basic-render: skip -> PASS (ro-skl3-i5-6260u) Subgroup basic-vebox: skip -> PASS (ro-skl3-i5-6260u) Test gem_cpu_reloc: Subgroup basic: fail -> PASS (ro-skl3-i5-6260u) Test gem_cs_tlb: Subgroup basic-default: fail -> PASS (ro-skl3-i5-6260u) Test gem_ctx_create: Subgroup basic-files: fail -> PASS (ro-skl3-i5-6260u) Test gem_ctx_exec: Subgroup basic: fail -> PASS (ro-skl3-i5-6260u) Test gem_ctx_switch: Subgroup basic-default: skip -> PASS (ro-skl3-i5-6260u) Test gem_exec_basic: Subgroup basic-blt: fail -> PASS (ro-skl3-i5-6260u) Subgroup basic-bsd: fail -> PASS (ro-skl3-i5-6260u) Subgroup basic-bsd1: fail -> PASS (ro-skl3-i5-6260u) Subgroup basic-bsd2: fail -> PASS (ro-skl3-i5-6260u) Subgroup basic-default: fail -> PASS (ro-skl3-i5-6260u) Subgroup basic-render: fail -> PASS (ro-skl3-i5-6260u) Subgroup basic-vebox: fail -> PASS (ro-skl3-i5-6260u) Subgroup gtt-blt: fail -> PASS (ro-skl3-i5-6260u) Subgroup gtt-bsd: fail -> PASS (ro-skl3-i5-6260u) Subgroup gtt-bsd1: fail -> PASS (ro-skl3-i5-6260u) Subgroup gtt-bsd2: fail -> PASS (ro-skl3-i5-6260u) Subgroup gtt-default: fail -> PASS (ro-skl3-i5-6260u) Subgroup gtt-render: fail -> PASS (ro-skl3-i5-6260u) Subgroup gtt-vebox: fail -> PASS (ro-skl3-i5-6260u) Subgroup readonly-blt: fail -> PASS (ro-skl3-i5-6260u) Subgroup readonly-bsd: fail -> PASS (ro-skl3-i5-6260u) Subgroup readonly-bsd1: fail -> PASS (ro-skl3-i5-6260u) Subgroup readonly-bsd2: fail -> PASS (ro-skl3-i5-6260u) Subgroup readonly-default: fail -> PASS (ro-skl3-i5-6260u) Subgroup readonly-render: fail -> PASS (ro-skl3-i5-6260u) Subgroup readonly-vebox: fail -> PASS (ro-skl3-i5-6260u) Test gem_exec_create: Subgroup basic: fail -> PASS (ro-skl3-i5-6260u) Test gem_exec_flush: Subgroup basic-batch-kernel-default-uc: fail -> PASS (ro-skl3-i5-6260u) dmesg-fail -> PASS (ro-bdw-i7-5557U) pass -> DMESG-FAIL (fi-skl-i5-6260u) pass -> DMESG-FAIL (fi-skl-i7-6700k) Filed https://bugs.freedesktop.org/show_bug.cgi?id=96806 for this one. WARNING: Long output truncated Results at /archive/results/CI_IGT_test/RO_Patchwork_1404/ 54c86e3 drm-intel-nightly: 2016y-07m-04d-11h-55m-58s UT
Re: [Intel-gfx] [PATCH] drm/i915:gen9: implement WaMediaPoolStateCmdInWABB
On 04/07/2016 14:38, tim.g...@intel.com wrote:
From: Tim Gore
This patch applies WaMediaPoolStateCmdInWABB which fixes
a problem with the restoration of thread counts on resuming
from RC6.
Signed-off-by: Tim Gore
suggest adding hsd ref# to commit msg.
---
drivers/gpu/drm/i915/intel_lrc.c | 25 +
1 file changed, 25 insertions(+)
diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c
index 676b532..017b25c 100644
--- a/drivers/gpu/drm/i915/intel_lrc.c
+++ b/drivers/gpu/drm/i915/intel_lrc.c
@@ -1296,6 +1296,31 @@ static int gen9_init_indirectctx_bb(struct
intel_engine_cs *engine,
wa_ctx_emit(batch, index, 0);
wa_ctx_emit(batch, index, 0);
}
+
+ /* WaMediaPoolStateCmdInWABB:bxt */
+ if (HAS_POOLED_EU(engine->i915)) {
+ /*
+* EU pool configuration is setup along with golden context
+* during context initialization. This value depends on
+* device type (2x6 or 3x6) and needs to be updated based
+* on which subslice is disabled especially for 2x6
+* devices, however it is safe to load default
+* configuration of 3x6 device instead of masking off
+* corresponding bits because HW ignores bits of a disabled
+* subslice and drops down to appropriate config. Please
+* see render_state_setup() in i915_gem_render_state.c for
+* possible configurations, to avoid duplication they are
+* not shown here again.
+*/
+ u32 eu_pool_config = 0x00777000;
+ wa_ctx_emit(batch, index, GEN9_MEDIA_POOL_STATE);
+ wa_ctx_emit(batch, index, GEN9_MEDIA_POOL_ENABLE);
+ wa_ctx_emit(batch, index, eu_pool_config);
+ wa_ctx_emit(batch, index, 0);
+ wa_ctx_emit(batch, index, 0);
+ wa_ctx_emit(batch, index, 0);
+ }
+
/* Pad to end of cacheline */
while (index % CACHELINE_DWORDS)
wa_ctx_emit(batch, index, MI_NOOP);
looks good to me,
Reviewed-by: Arun Siluvery
regards
Arun
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[Intel-gfx] linux-next: build failure after merge of the tip tree (from the drm-intel tree)
Hi all,
After merging the tip tree, today's linux-next build (x86_64 allmodconfig)
failed like this:
In file included from include/uapi/linux/stddef.h:1:0,
from include/linux/stddef.h:4,
from include/uapi/linux/posix_types.h:4,
from include/uapi/linux/types.h:13,
from include/linux/types.h:5,
from include/linux/sysrq.h:18,
from drivers/gpu/drm/i915/i915_irq.c:31:
drivers/gpu/drm/i915/i915_irq.c: In function 'i915_hangcheck_elapsed':
include/linux/compiler.h:542:50: error: incompatible types when initializing
type 'const void * const' using type 'bool {aka _Bool}'
__maybe_unused const void * const _p2 = _p1; \
^
drivers/gpu/drm/i915/i915_irq.c:3098:7: note: in expansion of macro
'lockless_dereference'
if (!lockless_dereference(dev_priv->gt.awake))
^
Caused by commit
67d97da34917 ("drm/i915: Only start retire worker when idle")
from the drm-intel tree interacting with commit
331b6d8c7afc ("locking/barriers: Validate lockless_dereference() is used on a
pointer type")
from the tip tree.
From include/linux/compiler.h:
* lockless_dereference() - safely load a pointer for later dereference
* @p: The pointer to load
It looks like lockless_dererence() has been used incorrectly
in the drm-intel tree commit since its argument must be a
pointer to be dererenced later. The same thing is done in
drivers/gpu/drm/i915/i915_gem.c as well.
I have applied the following hack patch for now, but this needs to be
fixed properly.
From: Stephen Rothwell
Date: Tue, 5 Jul 2016 13:44:39 +1000
Subject: [PATCH] drm/i915: hack around bad use of lockless_dereference()
Signed-off-by: Stephen Rothwell
---
drivers/gpu/drm/i915/i915_gem.c | 2 +-
drivers/gpu/drm/i915/i915_irq.c | 2 +-
2 files changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
index d3502c0603e5..1f91f187b2a8 100644
--- a/drivers/gpu/drm/i915/i915_gem.c
+++ b/drivers/gpu/drm/i915/i915_gem.c
@@ -3290,7 +3290,7 @@ i915_gem_retire_work_handler(struct work_struct *work)
* We do not need to do this test under locking as in the worst-case
* we queue the retire worker once too often.
*/
- if (lockless_dereference(dev_priv->gt.awake))
+ if (/*lockless_dereference*/(dev_priv->gt.awake))
queue_delayed_work(dev_priv->wq,
&dev_priv->gt.retire_work,
round_jiffies_up_relative(HZ));
diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index f6de8dd567a2..2c1926418691 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -3095,7 +3095,7 @@ static void i915_hangcheck_elapsed(struct work_struct
*work)
if (!i915.enable_hangcheck)
return;
- if (!lockless_dereference(dev_priv->gt.awake))
+ if (!/*lockless_dereference*/(dev_priv->gt.awake))
return;
/* As enabling the GPU requires fairly extensive mmio access,
--
2.8.1
--
Cheers,
Stephen Rothwell
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