Re: [Intel-gfx] [PATCH] drm/i915: Push vblank enable/disable past encoder->enable/disable
On Wed, 07 Jan 2015, Daniel Vetter wrote:
> It is platform/output depenedent when exactly the pipe will start
> running. Sometimes we just need the (cpu) pipe enabled, in other cases
> the pch transcoder is enough and in yet other cases the (DP) port is
> sending the frame start signal.
>
> In a perfect world we'd put the drm_crtc_vblank_on call exactly where
> the pipe starts running, but due to cloning and similar things this
> will get messy. And the current approach of picking the most
> conservative place for all combinations also doesn't work since that
> results in legit vblank waits (in encoder->enable hooks, e.g. the 2
> vblank waits for sdvo) failing.
>
> Completely going back to the old world before
>
> commit 51e31d49c89055299e34b8f44d13f70e19d1
> Author: Daniel Vetter
> Date: Mon Sep 15 12:36:02 2014 +0200
>
> drm/i915: Use generic vblank wait# Please enter the commit message for
> your changes. Lines starting
>
> isn't great either since screaming when the vblank wait work because
> the pipe is off is kinda nice.
>
> Pick a compromise and move the drm_crtc_vblank_on right before the
> encoder->enable call. This is a lie on some outputs/platforms, but
> after the ->enable callback the pipe is guaranteed to run everywhere.
> So not that bad really. Suggested by Ville.
>
> v2: Same treatment for drm_crtc_vblank_off and encoder->disable: I've
> missed the ibx pipe B select w/a, which also has a vblank wait in the
> disable function (while the pipe is obviously still running).
>
> Cc: Ville Syrjälä
> Cc: Chris Wilson
> Acked-by: Ville Syrjälä
> Signed-off-by: Daniel Vetter
Should this be forwarded to stable 3.19?
BR,
Jani.
> ---
> drivers/gpu/drm/i915/intel_display.c | 42
> ++--
> 1 file changed, 21 insertions(+), 21 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_display.c
> b/drivers/gpu/drm/i915/intel_display.c
> index a1dbe747a372..e224820ea5a4 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -4301,15 +4301,15 @@ static void ironlake_crtc_enable(struct drm_crtc
> *crtc)
> if (intel_crtc->config.has_pch_encoder)
> ironlake_pch_enable(crtc);
>
> + assert_vblank_disabled(crtc);
> + drm_crtc_vblank_on(crtc);
> +
> for_each_encoder_on_crtc(dev, crtc, encoder)
> encoder->enable(encoder);
>
> if (HAS_PCH_CPT(dev))
> cpt_verify_modeset(dev, intel_crtc->pipe);
>
> - assert_vblank_disabled(crtc);
> - drm_crtc_vblank_on(crtc);
> -
> intel_crtc_enable_planes(crtc);
> }
>
> @@ -4421,14 +4421,14 @@ static void haswell_crtc_enable(struct drm_crtc *crtc)
> if (intel_crtc->config.dp_encoder_is_mst)
> intel_ddi_set_vc_payload_alloc(crtc, true);
>
> + assert_vblank_disabled(crtc);
> + drm_crtc_vblank_on(crtc);
> +
> for_each_encoder_on_crtc(dev, crtc, encoder) {
> encoder->enable(encoder);
> intel_opregion_notify_encoder(encoder, true);
> }
>
> - assert_vblank_disabled(crtc);
> - drm_crtc_vblank_on(crtc);
> -
> /* If we change the relative order between pipe/planes enabling, we need
>* to change the workaround. */
> haswell_mode_set_planes_workaround(intel_crtc);
> @@ -4479,12 +4479,12 @@ static void ironlake_crtc_disable(struct drm_crtc
> *crtc)
>
> intel_crtc_disable_planes(crtc);
>
> - drm_crtc_vblank_off(crtc);
> - assert_vblank_disabled(crtc);
> -
> for_each_encoder_on_crtc(dev, crtc, encoder)
> encoder->disable(encoder);
>
> + drm_crtc_vblank_off(crtc);
> + assert_vblank_disabled(crtc);
> +
> if (intel_crtc->config.has_pch_encoder)
> intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, false);
>
> @@ -4544,14 +4544,14 @@ static void haswell_crtc_disable(struct drm_crtc
> *crtc)
>
> intel_crtc_disable_planes(crtc);
>
> - drm_crtc_vblank_off(crtc);
> - assert_vblank_disabled(crtc);
> -
> for_each_encoder_on_crtc(dev, crtc, encoder) {
> intel_opregion_notify_encoder(encoder, false);
> encoder->disable(encoder);
> }
>
> + drm_crtc_vblank_off(crtc);
> + assert_vblank_disabled(crtc);
> +
> if (intel_crtc->config.has_pch_encoder)
> intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A,
> false);
> @@ -5021,12 +5021,12 @@ static void valleyview_crtc_enable(struct drm_crtc
> *crtc)
> intel_update_watermarks(crtc);
> intel_enable_pipe(intel_crtc);
>
> - for_each_encoder_on_crtc(dev, crtc, encoder)
> - encoder->enable(encoder);
> -
> assert_vblank_disabled(crtc);
> drm_crtc_vblank_on(crtc);
>
> + for_each_encoder_on_crtc(dev, crtc, encoder)
> + encoder->enable(encoder);
> +
> intel_crtc_enable_planes(crtc);
>
> /* Underrun
Re: [Intel-gfx] [PATCH] drm/i915: Align initial plane backing objects correctly
On Wed, 11 Feb 2015, Daniel Vetter wrote:
> Some bios really like to joke and start the planes at an offset ...
> hooray!
>
> Align start and end to fix this.
>
> v2: Fixup calculation of size, spotted by Chris Wilson.
>
> v3: Fix serious fumble I've just spotted.
>
> Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=86883
> Cc: sta...@vger.kernel.org
> Cc: Johannes W
> Cc: Chris Wilson
> Cc: Jani Nikula
> Reported-by: Johannes W
> Signed-off-by: Daniel Vetter
Tested-by: Johannes W
>
> --
>
> Johannes, can you please test this patch instead of the one from
> Chris?
>
> Thanks, Daniel
> ---
> drivers/gpu/drm/i915/i915_gem_stolen.c | 5 +
> drivers/gpu/drm/i915/intel_display.c | 18 --
> 2 files changed, 13 insertions(+), 10 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_gem_stolen.c
> b/drivers/gpu/drm/i915/i915_gem_stolen.c
> index 59401f3b902c..4382696087c9 100644
> --- a/drivers/gpu/drm/i915/i915_gem_stolen.c
> +++ b/drivers/gpu/drm/i915/i915_gem_stolen.c
> @@ -485,10 +485,7 @@ i915_gem_object_create_stolen_for_preallocated(struct
> drm_device *dev,
> stolen_offset, gtt_offset, size);
>
> /* KISS and expect everything to be page-aligned */
> - BUG_ON(stolen_offset & 4095);
> - BUG_ON(size & 4095);
> -
> - if (WARN_ON(size == 0))
> + if (WARN_ON(size == 0 || stolen_offset & 4095 || size & 4095))
> return NULL;
>
> stolen = kzalloc(sizeof(*stolen), GFP_KERNEL);
> diff --git a/drivers/gpu/drm/i915/intel_display.c
> b/drivers/gpu/drm/i915/intel_display.c
> index 2655b63d65e9..fc855b9548ec 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -2372,13 +2372,19 @@ intel_alloc_plane_obj(struct intel_crtc *crtc,
> struct drm_i915_gem_object *obj = NULL;
> struct drm_mode_fb_cmd2 mode_cmd = { 0 };
> struct drm_framebuffer *fb = &plane_config->fb->base;
> - u32 base = plane_config->base;
> + u32 base_aligned = round_down(plane_config->base, PAGE_SIZE);
> + u32 size_aligned = round_up(plane_config->base + plane_config->size,
> + PAGE_SIZE);
> +
> + size_aligned -= base_aligned;
>
> if (plane_config->size == 0)
> return false;
>
> - obj = i915_gem_object_create_stolen_for_preallocated(dev, base, base,
> -
> plane_config->size);
> + obj = i915_gem_object_create_stolen_for_preallocated(dev,
> + base_aligned,
> + base_aligned,
> + size_aligned);
> if (!obj)
> return false;
>
> @@ -6654,7 +6660,7 @@ i9xx_get_initial_plane_config(struct intel_crtc *crtc,
> aligned_height = intel_fb_align_height(dev, fb->height,
> plane_config->tiling);
>
> - plane_config->size = PAGE_ALIGN(fb->pitches[0] * aligned_height);
> + plane_config->size = fb->pitches[0] * aligned_height;
>
> DRM_DEBUG_KMS("pipe/plane %c/%d with fb: size=%dx%d@%d, offset=%x,
> pitch %d, size 0x%x\n",
> pipe_name(pipe), plane, fb->width, fb->height,
> @@ -7694,7 +7700,7 @@ skylake_get_initial_plane_config(struct intel_crtc
> *crtc,
> aligned_height = intel_fb_align_height(dev, fb->height,
> plane_config->tiling);
>
> - plane_config->size = ALIGN(fb->pitches[0] * aligned_height, PAGE_SIZE);
> + plane_config->size = fb->pitches[0] * aligned_height;
>
> DRM_DEBUG_KMS("pipe %c with fb: size=%dx%d@%d, offset=%x, pitch %d,
> size 0x%x\n",
> pipe_name(pipe), fb->width, fb->height,
> @@ -7787,7 +7793,7 @@ ironlake_get_initial_plane_config(struct intel_crtc
> *crtc,
> aligned_height = intel_fb_align_height(dev, fb->height,
> plane_config->tiling);
>
> - plane_config->size = PAGE_ALIGN(fb->pitches[0] * aligned_height);
> + plane_config->size = fb->pitches[0] * aligned_height;
>
> DRM_DEBUG_KMS("pipe %c with fb: size=%dx%d@%d, offset=%x, pitch %d,
> size 0x%x\n",
> pipe_name(pipe), fb->width, fb->height,
> --
> 2.1.4
>
--
Jani Nikula, Intel Open Source Technology Center
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[Intel-gfx] [v2 1/5] drm/i915: Add new PHY reg definitions for lock threshold
Added new PHY register definitions to control TDC buffer calibration and
digital lock threshold.
Signed-off-by: Vijay Purushothaman
---
drivers/gpu/drm/i915/i915_reg.h | 10 ++
1 file changed, 10 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 1dc91de..5814f67 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -1025,6 +1025,16 @@ enum skl_disp_power_wells {
#define DPIO_CHV_PROP_COEFF_SHIFT0
#define CHV_PLL_DW6(ch) _PIPE(ch, _CHV_PLL_DW6_CH0, _CHV_PLL_DW6_CH1)
+#define _CHV_PLL_DW8_CH0 0x8020
+#define _CHV_PLL_DW8_CH1 0x81A0
+#define CHV_PLL_DW8(ch) _PIPE(ch, _CHV_PLL_DW8_CH0, _CHV_PLL_DW8_CH1)
+
+#define _CHV_PLL_DW9_CH0 0x8024
+#define _CHV_PLL_DW9_CH1 0x81A4
+#define DPIO_CHV_INT_LOCK_THRESHOLD_SHIFT 1 /* 3 bits */
+#define DPIO_CHV_INT_LOCK_THRESHOLD_SEL_COARSE1 /* 1: coarse & 0 :
fine */
+#define CHV_PLL_DW9(ch) _PIPE(ch, _CHV_PLL_DW9_CH0, _CHV_PLL_DW9_CH1)
+
#define _CHV_CMN_DW5_CH0 0x8114
#define CHV_BUFRIGHTENA1_DISABLE (0 << 20)
#define CHV_BUFRIGHTENA1_NORMAL (1 << 20)
--
1.7.9.5
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[Intel-gfx] [v2 0/5] More DPIO magic for CHV HDMI & DP
Changes since version 1: Addressed Ville's review comments Decoded the magic numbers as much as possible Split the single patch into logical patch set Dropped the DPIO_CLK_EN changes Vijay Purushothaman (5): drm/i915: Add new PHY reg definitions for lock threshold drm/i915: Limit max VCO supported in CHV to 6.48GHz drm/i915: Disable M2 frac division for integer case drm/i915: Initialize CHV digital lock detect threshold drm/i915: Update prop, int co-eff and gain threshold for CHV drivers/gpu/drm/i915/i915_reg.h | 11 + drivers/gpu/drm/i915/intel_display.c | 78 +- 2 files changed, 70 insertions(+), 19 deletions(-) -- 1.7.9.5 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [v2 3/5] drm/i915: Disable M2 frac division for integer case
Handle M2 frac division for both M2 frac and int cases
Signed-off-by: Vijay Purushothaman
---
drivers/gpu/drm/i915/intel_display.c | 23 +--
1 file changed, 17 insertions(+), 6 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_display.c
b/drivers/gpu/drm/i915/intel_display.c
index 4e710f6..87d1721 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -6041,6 +6041,7 @@ static void chv_prepare_pll(struct intel_crtc *crtc,
enum dpio_channel port = vlv_pipe_to_channel(pipe);
u32 loopfilter, intcoeff;
u32 bestn, bestm1, bestm2, bestp1, bestp2, bestm2_frac;
+ u32 dpio_val;
int refclk;
bestn = pipe_config->dpll.n;
@@ -6049,6 +6050,7 @@ static void chv_prepare_pll(struct intel_crtc *crtc,
bestm2 = pipe_config->dpll.m2 >> 22;
bestp1 = pipe_config->dpll.p1;
bestp2 = pipe_config->dpll.p2;
+ dpio_val = 0;
/*
* Enable Refclk and SSC
@@ -6073,13 +6075,22 @@ static void chv_prepare_pll(struct intel_crtc *crtc,
DPIO_CHV_M1_DIV_BY_2 |
1 << DPIO_CHV_N_DIV_SHIFT);
- /* M2 fraction division */
- vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW2(port), bestm2_frac);
+ if (bestm2_frac) {
+ /* M2 fraction division */
+ vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW2(port), bestm2_frac);
- /* M2 fraction division enable */
- vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW3(port),
- DPIO_CHV_FRAC_DIV_EN |
- (2 << DPIO_CHV_FEEDFWD_GAIN_SHIFT));
+ /* M2 fraction division enable */
+ dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW3(port));
+ dpio_val |= DPIO_CHV_FRAC_DIV_EN;
+ dpio_val |= (2 << DPIO_CHV_FEEDFWD_GAIN_SHIFT);
+ vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW3(port), dpio_val);
+
+ } else {
+ /* M2 fraction division disable */
+ dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW3(port));
+ dpio_val &= ~(DPIO_CHV_FRAC_DIV_EN);
+ vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW3(port), dpio_val);
+ }
/* Loop filter */
refclk = i9xx_get_refclk(crtc, 0);
--
1.7.9.5
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[Intel-gfx] [v2 4/5] drm/i915: Initialize CHV digital lock detect threshold
Initialize lock detect threshold and select coarse threshold if M2 is
zero
Signed-off-by: Vijay Purushothaman
---
drivers/gpu/drm/i915/intel_display.c | 11 +++
1 file changed, 11 insertions(+)
diff --git a/drivers/gpu/drm/i915/intel_display.c
b/drivers/gpu/drm/i915/intel_display.c
index 87d1721..ae2a77f 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -6085,11 +6085,22 @@ static void chv_prepare_pll(struct intel_crtc *crtc,
dpio_val |= (2 << DPIO_CHV_FEEDFWD_GAIN_SHIFT);
vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW3(port), dpio_val);
+ /* Program digital lock detect threshold */
+ dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW9(port));
+ dpio_val |= (0x5 << DPIO_CHV_INT_LOCK_THRESHOLD_SHIFT);
+ vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW9(port), dpio_val);
+
} else {
/* M2 fraction division disable */
dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW3(port));
dpio_val &= ~(DPIO_CHV_FRAC_DIV_EN);
vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW3(port), dpio_val);
+
+ /* Program digital lock detect threshold */
+ dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW9(port));
+ dpio_val |= (0x5 << DPIO_CHV_INT_LOCK_THRESHOLD_SHIFT);
+ dpio_val |= DPIO_CHV_INT_LOCK_THRESHOLD_SEL_COARSE;
+ vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW9(port), dpio_val);
}
/* Loop filter */
--
1.7.9.5
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[Intel-gfx] [v2 5/5] drm/i915: Update prop, int co-eff and gain threshold for CHV
This patch implements latest PHY changes in Gain, prop and int co-efficients
based on the vco freq.
Signed-off-by: Vijay Purushothaman
---
drivers/gpu/drm/i915/i915_reg.h |1 +
drivers/gpu/drm/i915/intel_display.c | 42 --
2 files changed, 31 insertions(+), 12 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 5814f67..b5bce4e 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -1027,6 +1027,7 @@ enum skl_disp_power_wells {
#define _CHV_PLL_DW8_CH0 0x8020
#define _CHV_PLL_DW8_CH1 0x81A0
+#define DPIO_CHV_TDC_TARGET_CNT_SHIFT 0
#define CHV_PLL_DW8(ch) _PIPE(ch, _CHV_PLL_DW8_CH0, _CHV_PLL_DW8_CH1)
#define _CHV_PLL_DW9_CH0 0x8024
diff --git a/drivers/gpu/drm/i915/intel_display.c
b/drivers/gpu/drm/i915/intel_display.c
index ae2a77f..ca02cf7 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -6039,10 +6039,10 @@ static void chv_prepare_pll(struct intel_crtc *crtc,
int pipe = crtc->pipe;
int dpll_reg = DPLL(crtc->pipe);
enum dpio_channel port = vlv_pipe_to_channel(pipe);
- u32 loopfilter, intcoeff;
+ u32 loopfilter, tribuf_calcntr;
u32 bestn, bestm1, bestm2, bestp1, bestp2, bestm2_frac;
u32 dpio_val;
- int refclk;
+ int vco;
bestn = pipe_config->dpll.n;
bestm2_frac = pipe_config->dpll.m2 & 0x3f;
@@ -6050,7 +6050,9 @@ static void chv_prepare_pll(struct intel_crtc *crtc,
bestm2 = pipe_config->dpll.m2 >> 22;
bestp1 = pipe_config->dpll.p1;
bestp2 = pipe_config->dpll.p2;
+ vco = pipe_config->dpll.vco;
dpio_val = 0;
+ loopfilter = 0;
/*
* Enable Refclk and SSC
@@ -6104,18 +6106,34 @@ static void chv_prepare_pll(struct intel_crtc *crtc,
}
/* Loop filter */
- refclk = i9xx_get_refclk(crtc, 0);
- loopfilter = 5 << DPIO_CHV_PROP_COEFF_SHIFT |
- 2 << DPIO_CHV_GAIN_CTRL_SHIFT;
- if (refclk == 10)
- intcoeff = 11;
- else if (refclk == 38400)
- intcoeff = 10;
- else
- intcoeff = 9;
- loopfilter |= intcoeff << DPIO_CHV_INT_COEFF_SHIFT;
+ if (vco == 540) {
+ loopfilter |= (0x3 << DPIO_CHV_PROP_COEFF_SHIFT);
+ loopfilter |= (0x8 << DPIO_CHV_INT_COEFF_SHIFT);
+ loopfilter |= (0x1 << DPIO_CHV_GAIN_CTRL_SHIFT);
+ tribuf_calcntr = 0;
+ } else if (vco <= 620) {
+ loopfilter |= (0x5 << DPIO_CHV_PROP_COEFF_SHIFT);
+ loopfilter |= (0xB << DPIO_CHV_INT_COEFF_SHIFT);
+ loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT);
+ tribuf_calcntr = 0x9;
+ } else if (vco <= 648) {
+ loopfilter |= (0x4 << DPIO_CHV_PROP_COEFF_SHIFT);
+ loopfilter |= (0x9 << DPIO_CHV_INT_COEFF_SHIFT);
+ loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT);
+ tribuf_calcntr = 0x8;
+ } else {
+ /* Not supported. Apply the same limits as in the max case */
+ loopfilter |= (0x4 << DPIO_CHV_PROP_COEFF_SHIFT);
+ loopfilter |= (0x9 << DPIO_CHV_INT_COEFF_SHIFT);
+ loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT);
+ tribuf_calcntr = 0;
+ }
vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW6(port), loopfilter);
+ dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW8(pipe));
+ dpio_val |= (tribuf_calcntr << DPIO_CHV_TDC_TARGET_CNT_SHIFT);
+ vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW8(port), dpio_val);
+
/* AFC Recal */
vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port),
vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port)) |
--
1.7.9.5
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[Intel-gfx] [v2 2/5] drm/i915: Limit max VCO supported in CHV to 6.48GHz
As per the recommendation from PHY team, limit the max vco supported in CHV to
6.48 GHz
Signed-off-by: Vijay Purushothaman
---
drivers/gpu/drm/i915/intel_display.c |2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/intel_display.c
b/drivers/gpu/drm/i915/intel_display.c
index 3b0fe9f..4e710f6 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -390,7 +390,7 @@ static const intel_limit_t intel_limits_chv = {
* them would make no difference.
*/
.dot = { .min = 25000 * 5, .max = 54 * 5},
- .vco = { .min = 486, .max = 670 },
+ .vco = { .min = 486, .max = 648 },
.n = { .min = 1, .max = 1 },
.m1 = { .min = 2, .max = 2 },
.m2 = { .min = 24 << 22, .max = 175 << 22 },
--
1.7.9.5
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Re: [Intel-gfx] [PATCH] drm/i915: Fix a use after free, and unbalanced refcounting
> -Original Message-
> From: Intel-gfx [mailto:intel-gfx-boun...@lists.freedesktop.org] On Behalf Of
> Daniel Vetter
> Sent: Friday, February 13, 2015 1:50 PM
> To: Hoath, Nicholas
> Cc: intel-gfx@lists.freedesktop.org
> Subject: Re: [Intel-gfx] [PATCH] drm/i915: Fix a use after free, and
> unbalanced
> refcounting
>
> On Fri, Feb 13, 2015 at 01:30:35PM +, Nick Hoath wrote:
> > Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=88652
> >
> > When converting from implicitly tracked execlist queue items to ref counted
> > requests, not all free's of requests were replaced with unrefs, and
> > extraneous
> > refs/unrefs of contexts were added.
> > Correct the unbalanced refcount & replace the free's.
> >
> > Problem introduced in:
> > commit 6d3d8274bc45de4babb62d64562d92af984dd238
> > Author: Nick Hoath
> > AuthorDate: Thu Jan 15 13:10:39 2015 +
> >
> > drm/i915: Subsume intel_ctx_submit_request in to drm_i915_gem_request
>
> Imo the commit message should be ammended with a short paragraph explainig
> the various pointers and implied and explicit references we now have
> around requests and contexts. That way review of this will get a bit
> easier and we'll avoid another misunderstanding.
>
> I even think we should add a comment in the header to request.ctx to
> explain the rules since apparently they've not been fully clear.
Agree that more documentation around these ctx refs would be good to have to
clear up confusion.
For example, I initially thought that this patch introduced a new
use-after-free because of the removal of the ctx ref in
execlists_context_queue().
>
> > Signed-off-by: Nick Hoath
>
> But yeah this makes a lot more sense imo. Please feed this to QA for
> stress-testing in all the relevant bugs. Today I have my head full with
> kms code so not a good time for a full in-depth review. But I think it'd
> be good if other people take a look anyway, so please throw this at a few
> ppl from the vpg core team too.
I guess that would be me...
The code changes look OK, would like to see the updated comments and QA results.
Cheers,
Thomas.
> Thanks, Daniel
>
> > ---
> > drivers/gpu/drm/i915/i915_gem.c | 3 +--
> > drivers/gpu/drm/i915/intel_lrc.c | 3 +--
> > 2 files changed, 2 insertions(+), 4 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/i915_gem.c
> b/drivers/gpu/drm/i915/i915_gem.c
> > index 1765989..79e48b2 100644
> > --- a/drivers/gpu/drm/i915/i915_gem.c
> > +++ b/drivers/gpu/drm/i915/i915_gem.c
> > @@ -2660,8 +2660,7 @@ static void i915_gem_reset_ring_cleanup(struct
> drm_i915_private *dev_priv,
> > if (submit_req->ctx != ring->default_context)
> > intel_lr_context_unpin(ring, submit_req->ctx);
> >
> > - i915_gem_context_unreference(submit_req->ctx);
> > - kfree(submit_req);
> > + i915_gem_request_unreference(submit_req);
> > }
> >
> > /*
> > diff --git a/drivers/gpu/drm/i915/intel_lrc.c
> > b/drivers/gpu/drm/i915/intel_lrc.c
> > index aafcef3..a18925d 100644
> > --- a/drivers/gpu/drm/i915/intel_lrc.c
> > +++ b/drivers/gpu/drm/i915/intel_lrc.c
> > @@ -518,12 +518,12 @@ static int execlists_context_queue(struct
> intel_engine_cs *ring,
> > return -ENOMEM;
> > request->ring = ring;
> > request->ctx = to;
> > + i915_gem_context_reference(request->ctx);
> > } else {
> > WARN_ON(to != request->ctx);
> > }
> > request->tail = tail;
> > i915_gem_request_reference(request);
> > - i915_gem_context_reference(request->ctx);
> >
> > intel_runtime_pm_get(dev_priv);
> >
> > @@ -740,7 +740,6 @@ void intel_execlists_retire_requests(struct
> intel_engine_cs *ring)
> > if (ctx_obj && (ctx != ring->default_context))
> > intel_lr_context_unpin(ring, ctx);
> > intel_runtime_pm_put(dev_priv);
> > - i915_gem_context_unreference(ctx);
> > list_del(&req->execlist_link);
> > i915_gem_request_unreference(req);
> > }
> > --
> > 2.1.1
> >
>
> --
> Daniel Vetter
> Software Engineer, Intel Corporation
> +41 (0) 79 365 57 48 - http://blog.ffwll.ch
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Re: [Intel-gfx] [v2 1/5] drm/i915: Add new PHY reg definitions for lock threshold
On Mon, Feb 16, 2015 at 03:07:58PM +0530, Vijay Purushothaman wrote:
> Added new PHY register definitions to control TDC buffer calibration and
> digital lock threshold.
>
> Signed-off-by: Vijay Purushothaman
Reviewed-by: Ville Syrjälä
> ---
> drivers/gpu/drm/i915/i915_reg.h | 10 ++
> 1 file changed, 10 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 1dc91de..5814f67 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -1025,6 +1025,16 @@ enum skl_disp_power_wells {
> #define DPIO_CHV_PROP_COEFF_SHIFT 0
> #define CHV_PLL_DW6(ch) _PIPE(ch, _CHV_PLL_DW6_CH0, _CHV_PLL_DW6_CH1)
>
> +#define _CHV_PLL_DW8_CH0 0x8020
> +#define _CHV_PLL_DW8_CH1 0x81A0
> +#define CHV_PLL_DW8(ch) _PIPE(ch, _CHV_PLL_DW8_CH0, _CHV_PLL_DW8_CH1)
> +
> +#define _CHV_PLL_DW9_CH0 0x8024
> +#define _CHV_PLL_DW9_CH1 0x81A4
> +#define DPIO_CHV_INT_LOCK_THRESHOLD_SHIFT 1 /* 3 bits */
> +#define DPIO_CHV_INT_LOCK_THRESHOLD_SEL_COARSE 1 /* 1: coarse & 0 :
> fine */
> +#define CHV_PLL_DW9(ch) _PIPE(ch, _CHV_PLL_DW9_CH0, _CHV_PLL_DW9_CH1)
> +
> #define _CHV_CMN_DW5_CH0 0x8114
> #define CHV_BUFRIGHTENA1_DISABLE (0 << 20)
> #define CHV_BUFRIGHTENA1_NORMAL(1 << 20)
> --
> 1.7.9.5
>
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Re: [Intel-gfx] [v2 2/5] drm/i915: Limit max VCO supported in CHV to 6.48GHz
On Mon, Feb 16, 2015 at 03:07:59PM +0530, Vijay Purushothaman wrote:
> As per the recommendation from PHY team, limit the max vco supported in CHV
> to 6.48 GHz
>
> Signed-off-by: Vijay Purushothaman
> ---
> drivers/gpu/drm/i915/intel_display.c |2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_display.c
> b/drivers/gpu/drm/i915/intel_display.c
> index 3b0fe9f..4e710f6 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -390,7 +390,7 @@ static const intel_limit_t intel_limits_chv = {
>* them would make no difference.
>*/
> .dot = { .min = 25000 * 5, .max = 54 * 5},
> - .vco = { .min = 486, .max = 670 },
> + .vco = { .min = 486, .max = 648 },
I have a patch here to reduce the minimum to 4.80 GHz, otherwise I can't
get my 2560x1440 HDMI display working (241.5 MHz clock). With that change
we still have a gap (233-240 MHz) in the frequencies we can produce.
Reducing the max to 6.48 GHz will increase that gap to 216-240 MHz, which
is a bit unfortunate. But if that's the recommendation we should follow
it I suppose, and hope no HDMI displays will want such frequencies.
Is there an updated spreadsheet available with the new limits? Quite a
few of the frequencies in the original spreadsheet did have vco>6.48
GHz.
I any case this seems OK, so
Acked-by: Ville Syrjälä
> .n = { .min = 1, .max = 1 },
> .m1 = { .min = 2, .max = 2 },
> .m2 = { .min = 24 << 22, .max = 175 << 22 },
> --
> 1.7.9.5
>
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Re: [Intel-gfx] [v2 3/5] drm/i915: Disable M2 frac division for integer case
On Mon, Feb 16, 2015 at 03:08:00PM +0530, Vijay Purushothaman wrote:
> Handle M2 frac division for both M2 frac and int cases
>
> Signed-off-by: Vijay Purushothaman
> ---
> drivers/gpu/drm/i915/intel_display.c | 23 +--
> 1 file changed, 17 insertions(+), 6 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_display.c
> b/drivers/gpu/drm/i915/intel_display.c
> index 4e710f6..87d1721 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -6041,6 +6041,7 @@ static void chv_prepare_pll(struct intel_crtc *crtc,
> enum dpio_channel port = vlv_pipe_to_channel(pipe);
> u32 loopfilter, intcoeff;
> u32 bestn, bestm1, bestm2, bestp1, bestp2, bestm2_frac;
> + u32 dpio_val;
> int refclk;
>
> bestn = pipe_config->dpll.n;
> @@ -6049,6 +6050,7 @@ static void chv_prepare_pll(struct intel_crtc *crtc,
> bestm2 = pipe_config->dpll.m2 >> 22;
> bestp1 = pipe_config->dpll.p1;
> bestp2 = pipe_config->dpll.p2;
> + dpio_val = 0;
>
> /*
>* Enable Refclk and SSC
> @@ -6073,13 +6075,22 @@ static void chv_prepare_pll(struct intel_crtc *crtc,
> DPIO_CHV_M1_DIV_BY_2 |
> 1 << DPIO_CHV_N_DIV_SHIFT);
>
> - /* M2 fraction division */
> - vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW2(port), bestm2_frac);
> + if (bestm2_frac) {
> + /* M2 fraction division */
> + vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW2(port), bestm2_frac);
>
> - /* M2 fraction division enable */
> - vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW3(port),
> -DPIO_CHV_FRAC_DIV_EN |
> -(2 << DPIO_CHV_FEEDFWD_GAIN_SHIFT));
> + /* M2 fraction division enable */
> + dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW3(port));
> + dpio_val |= DPIO_CHV_FRAC_DIV_EN;
> + dpio_val |= (2 << DPIO_CHV_FEEDFWD_GAIN_SHIFT);
Will need to mask out the bits first if you want to use RMW.
> + vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW3(port), dpio_val);
> +
> + } else {
> + /* M2 fraction division disable */
> + dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW3(port));
> + dpio_val &= ~(DPIO_CHV_FRAC_DIV_EN);
Useless parens.
> + vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW3(port), dpio_val);
> + }
>
> /* Loop filter */
> refclk = i9xx_get_refclk(crtc, 0);
> --
> 1.7.9.5
>
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Re: [Intel-gfx] [v2 4/5] drm/i915: Initialize CHV digital lock detect threshold
On Mon, Feb 16, 2015 at 03:08:01PM +0530, Vijay Purushothaman wrote:
> Initialize lock detect threshold and select coarse threshold if M2 is
> zero
"if M2 fractional part is zero"?
>
> Signed-off-by: Vijay Purushothaman
> ---
> drivers/gpu/drm/i915/intel_display.c | 11 +++
> 1 file changed, 11 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/intel_display.c
> b/drivers/gpu/drm/i915/intel_display.c
> index 87d1721..ae2a77f 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -6085,11 +6085,22 @@ static void chv_prepare_pll(struct intel_crtc *crtc,
> dpio_val |= (2 << DPIO_CHV_FEEDFWD_GAIN_SHIFT);
> vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW3(port), dpio_val);
>
> + /* Program digital lock detect threshold */
> + dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW9(port));
> + dpio_val |= (0x5 << DPIO_CHV_INT_LOCK_THRESHOLD_SHIFT);
Again need to clear out the old bits first.
> + vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW9(port), dpio_val);
> +
> } else {
> /* M2 fraction division disable */
> dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW3(port));
> dpio_val &= ~(DPIO_CHV_FRAC_DIV_EN);
> vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW3(port), dpio_val);
> +
> + /* Program digital lock detect threshold */
> + dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW9(port));
> + dpio_val |= (0x5 << DPIO_CHV_INT_LOCK_THRESHOLD_SHIFT);
Ditto.
> + dpio_val |= DPIO_CHV_INT_LOCK_THRESHOLD_SEL_COARSE;
> + vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW9(port), dpio_val);
> }
>
> /* Loop filter */
> --
> 1.7.9.5
>
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Re: [Intel-gfx] [v2 5/5] drm/i915: Update prop, int co-eff and gain threshold for CHV
On Mon, Feb 16, 2015 at 03:08:02PM +0530, Vijay Purushothaman wrote:
> This patch implements latest PHY changes in Gain, prop and int co-efficients
> based on the vco freq.
>
> Signed-off-by: Vijay Purushothaman
> ---
> drivers/gpu/drm/i915/i915_reg.h |1 +
> drivers/gpu/drm/i915/intel_display.c | 42
> --
> 2 files changed, 31 insertions(+), 12 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 5814f67..b5bce4e 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -1027,6 +1027,7 @@ enum skl_disp_power_wells {
>
> #define _CHV_PLL_DW8_CH0 0x8020
> #define _CHV_PLL_DW8_CH1 0x81A0
> +#define DPIO_CHV_TDC_TARGET_CNT_SHIFT 0
> #define CHV_PLL_DW8(ch) _PIPE(ch, _CHV_PLL_DW8_CH0, _CHV_PLL_DW8_CH1)
>
> #define _CHV_PLL_DW9_CH0 0x8024
> diff --git a/drivers/gpu/drm/i915/intel_display.c
> b/drivers/gpu/drm/i915/intel_display.c
> index ae2a77f..ca02cf7 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -6039,10 +6039,10 @@ static void chv_prepare_pll(struct intel_crtc *crtc,
> int pipe = crtc->pipe;
> int dpll_reg = DPLL(crtc->pipe);
> enum dpio_channel port = vlv_pipe_to_channel(pipe);
> - u32 loopfilter, intcoeff;
> + u32 loopfilter, tribuf_calcntr;
> u32 bestn, bestm1, bestm2, bestp1, bestp2, bestm2_frac;
> u32 dpio_val;
> - int refclk;
> + int vco;
>
> bestn = pipe_config->dpll.n;
> bestm2_frac = pipe_config->dpll.m2 & 0x3f;
> @@ -6050,7 +6050,9 @@ static void chv_prepare_pll(struct intel_crtc *crtc,
> bestm2 = pipe_config->dpll.m2 >> 22;
> bestp1 = pipe_config->dpll.p1;
> bestp2 = pipe_config->dpll.p2;
> + vco = pipe_config->dpll.vco;
> dpio_val = 0;
> + loopfilter = 0;
>
> /*
>* Enable Refclk and SSC
> @@ -6104,18 +6106,34 @@ static void chv_prepare_pll(struct intel_crtc *crtc,
> }
>
> /* Loop filter */
> - refclk = i9xx_get_refclk(crtc, 0);
> - loopfilter = 5 << DPIO_CHV_PROP_COEFF_SHIFT |
> - 2 << DPIO_CHV_GAIN_CTRL_SHIFT;
> - if (refclk == 10)
> - intcoeff = 11;
> - else if (refclk == 38400)
> - intcoeff = 10;
> - else
> - intcoeff = 9;
> - loopfilter |= intcoeff << DPIO_CHV_INT_COEFF_SHIFT;
> + if (vco == 540) {
> + loopfilter |= (0x3 << DPIO_CHV_PROP_COEFF_SHIFT);
> + loopfilter |= (0x8 << DPIO_CHV_INT_COEFF_SHIFT);
> + loopfilter |= (0x1 << DPIO_CHV_GAIN_CTRL_SHIFT);
> + tribuf_calcntr = 0;
In your original patch tribuf_calcntr was 9 here. Which is correct?
> + } else if (vco <= 620) {
> + loopfilter |= (0x5 << DPIO_CHV_PROP_COEFF_SHIFT);
> + loopfilter |= (0xB << DPIO_CHV_INT_COEFF_SHIFT);
> + loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT);
> + tribuf_calcntr = 0x9;
> + } else if (vco <= 648) {
> + loopfilter |= (0x4 << DPIO_CHV_PROP_COEFF_SHIFT);
> + loopfilter |= (0x9 << DPIO_CHV_INT_COEFF_SHIFT);
> + loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT);
> + tribuf_calcntr = 0x8;
> + } else {
> + /* Not supported. Apply the same limits as in the max case */
> + loopfilter |= (0x4 << DPIO_CHV_PROP_COEFF_SHIFT);
> + loopfilter |= (0x9 << DPIO_CHV_INT_COEFF_SHIFT);
> + loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT);
These too were different in your original patch, but I guess it doens't
matter either way that much since we should never get here.
> + tribuf_calcntr = 0;
> + }
> vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW6(port), loopfilter);
>
> + dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW8(pipe));
> + dpio_val |= (tribuf_calcntr << DPIO_CHV_TDC_TARGET_CNT_SHIFT);
Need to clear out the old bits again. Seems to be 10bits by the looks of it.
> + vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW8(port), dpio_val);
> +
> /* AFC Recal */
> vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port),
> vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port)) |
> --
> 1.7.9.5
>
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Re: [Intel-gfx] [PATCH] drm/i915/skl: handle all pixel formats in skylake_update_primary_plane()
On Tue, Feb 10, 2015 at 01:43:39PM +0200, Ville Syrjälä wrote: > On Tue, Feb 10, 2015 at 01:15:49PM +0200, Jani Nikula wrote: > > skylake_update_primary_plane() did not handle all pixel formats returned > > by skl_format_to_fourcc(). Handle alpha similar to skl_update_plane(). > > > > Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=89052 > > Signed-off-by: Jani Nikula > > > > --- > > > > This is purely cargo culting to avoid the BUG. > > --- > > drivers/gpu/drm/i915/intel_display.c | 9 + > > 1 file changed, 9 insertions(+) > > > > diff --git a/drivers/gpu/drm/i915/intel_display.c > > b/drivers/gpu/drm/i915/intel_display.c > > index 3fe95982be93..cede05256d56 100644 > > --- a/drivers/gpu/drm/i915/intel_display.c > > +++ b/drivers/gpu/drm/i915/intel_display.c > > @@ -2751,10 +2751,19 @@ static void skylake_update_primary_plane(struct > > drm_crtc *crtc, > > case DRM_FORMAT_XRGB: > > plane_ctl |= PLANE_CTL_FORMAT_XRGB_; > > break; > > + case DRM_FORMAT_ARGB: > > + plane_ctl |= PLANE_CTL_FORMAT_XRGB_; > > + plane_ctl |= PLANE_CTL_ALPHA_SW_PREMULTIPLY; > > We don't do alpha blending yet properly so we should just ignore alpha > for now. And someone should rip out that bit from skl_update_plane() as > well. We currently expose ARGB planes for VLV. Looking at the VLV Diplay Cluster HAS the blending done in VLV (and so CHV I'm guessing?) is src + (1 - src_a) * dst Clearly suitable for pre-multiplied framebuffers (it's also stated so). So, we already expose a default blendig mode suitable for pre-multiplied FBs. This would be just doing the same and provide a (IMHO sensible) default for fbs with alpha. So we could go with this? maybe? -- Damien ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 1/2] drm/i915: Move drm_framebuffer_unreference out of struct_mutex for flips
intel_user_framebuffer_destroy() requires the struct_mutex for its object bookkeeping, so this means that all calls to drm_framebuffer_reference must be held without that lock. Regression from commit ab8d66752a9c28cd6c94fa173feacdfc1554aa03 Author: Tvrtko Ursulin Date: Mon Feb 2 15:44:15 2015 + drm/i915: Track old framebuffer instead of object Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=89166 Cc: Tvrtko Ursulin Signed-off-by: Chris Wilson --- drivers/gpu/drm/i915/intel_display.c | 17 + 1 file changed, 9 insertions(+), 8 deletions(-) diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c index 3b0fe9f1f3c9..6e1da7da5cca 100644 --- a/drivers/gpu/drm/i915/intel_display.c +++ b/drivers/gpu/drm/i915/intel_display.c @@ -9107,7 +9107,6 @@ static void intel_unpin_work_fn(struct work_struct *__work) mutex_lock(&dev->struct_mutex); intel_unpin_fb_obj(intel_fb_obj(work->old_fb)); drm_gem_object_unreference(&work->pending_flip_obj->base); - drm_framebuffer_unreference(work->old_fb); intel_fbc_update(dev); @@ -9116,6 +9115,7 @@ static void intel_unpin_work_fn(struct work_struct *__work) mutex_unlock(&dev->struct_mutex); intel_frontbuffer_flip_complete(dev, INTEL_FRONTBUFFER_PRIMARY(pipe)); + drm_framebuffer_unreference(work->old_fb); BUG_ON(atomic_read(&to_intel_crtc(work->crtc)->unpin_work_count) == 0); atomic_dec(&to_intel_crtc(work->crtc)->unpin_work_count); @@ -9778,10 +9778,6 @@ static int intel_crtc_page_flip(struct drm_crtc *crtc, if (atomic_read(&intel_crtc->unpin_work_count) >= 2) flush_workqueue(dev_priv->wq); - ret = i915_mutex_lock_interruptible(dev); - if (ret) - goto cleanup; - /* Reference the objects for the scheduled work. */ drm_framebuffer_reference(work->old_fb); drm_gem_object_reference(&obj->base); @@ -9791,6 +9787,10 @@ static int intel_crtc_page_flip(struct drm_crtc *crtc, work->pending_flip_obj = obj; + ret = i915_mutex_lock_interruptible(dev); + if (ret) + goto cleanup; + atomic_inc(&intel_crtc->unpin_work_count); intel_crtc->reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter); @@ -9855,13 +9855,14 @@ cleanup_unpin: intel_unpin_fb_obj(obj); cleanup_pending: atomic_dec(&intel_crtc->unpin_work_count); + mutex_unlock(&dev->struct_mutex); +cleanup: crtc->primary->fb = old_fb; update_state_fb(crtc->primary); + + drm_gem_object_unreference_unlocked(&obj->base); drm_framebuffer_unreference(work->old_fb); - drm_gem_object_unreference(&obj->base); - mutex_unlock(&dev->struct_mutex); -cleanup: spin_lock_irq(&dev->event_lock); intel_crtc->unpin_work = NULL; spin_unlock_irq(&dev->event_lock); -- 2.1.4 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 2/2] drm/i915: Move drm_framebuffer_unreference out of struct_mutex for takeover
intel_user_framebuffer_destroy() requires the struct_mutex for its
object bookkeeping, so this means that all calls to
drm_framebuffer_reference must be held without that lock.
References: https://bugs.freedesktop.org/show_bug.cgi?id=89166
Signed-off-by: Chris Wilson
---
drivers/gpu/drm/i915/intel_display.c | 13 ++---
1 file changed, 10 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_display.c
b/drivers/gpu/drm/i915/intel_display.c
index 6e1da7da5cca..aba36662d511 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -13672,6 +13672,8 @@ void intel_modeset_gem_init(struct drm_device *dev)
struct drm_i915_private *dev_priv = dev->dev_private;
struct drm_crtc *c;
struct drm_i915_gem_object *obj;
+ struct drm_plane *unused[I915_MAX_PIPES];
+ int n_unused = 0;
mutex_lock(&dev->struct_mutex);
intel_init_gt_powersave(dev);
@@ -13707,13 +13709,18 @@ void intel_modeset_gem_init(struct drm_device *dev)
NULL)) {
DRM_ERROR("failed to pin boot fb on pipe %d\n",
to_intel_crtc(c)->pipe);
- drm_framebuffer_unreference(c->primary->fb);
- c->primary->fb = NULL;
- update_state_fb(c->primary);
+ unused[n_unused++] = c->primary;
}
}
mutex_unlock(&dev->struct_mutex);
+ while (n_unused--) {
+ struct drm_plane *p = unused[n_unused];
+ drm_framebuffer_unreference(p->fb);
+ p->fb = NULL;
+ update_state_fb(p);
+ }
+
intel_backlight_register(dev);
}
--
2.1.4
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[Intel-gfx] [PATCH] drm: Fix the CRTC_STEREO_DOUBLE_ONLY define to include stero modes
The CRTC_STEREO_DOUBLE_ONLY define was introduced in commit:
commit ecb7e16bf187bc369cf6a5cd108582c01329980d
Author: Gustavo Padovan
Date: Mon Dec 1 15:40:09 2014 -0800
drm: add helper to get crtc timings (v5)
but if we want the stereo h/v adjustments, we need to set the
CRTC_STEREO_DOUBLE flag. Otherwise, we'll get the wrong h/v for frame packing
stereo 3d modes.
Cc: Gustavo Padovan
Cc: Matt Roper
Cc: Ander Conselvan de Oliveira
Signed-off-by: Damien Lespiau
---
include/drm/drm_modes.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/include/drm/drm_modes.h b/include/drm/drm_modes.h
index d92f6dd..0616188 100644
--- a/include/drm/drm_modes.h
+++ b/include/drm/drm_modes.h
@@ -92,7 +92,7 @@ enum drm_mode_status {
#define CRTC_STEREO_DOUBLE (1 << 1) /* adjust timings for stereo modes */
#define CRTC_NO_DBLSCAN(1 << 2) /* don't adjust doublescan */
#define CRTC_NO_VSCAN (1 << 3) /* don't adjust doublescan */
-#define CRTC_STEREO_DOUBLE_ONLY(CRTC_NO_DBLSCAN | CRTC_NO_VSCAN)
+#define CRTC_STEREO_DOUBLE_ONLY(CRTC_STEREO_DOUBLE | CRTC_NO_DBLSCAN |
CRTC_NO_VSCAN)
#define DRM_MODE_FLAG_3D_MAX DRM_MODE_FLAG_3D_SIDE_BY_SIDE_HALF
--
1.8.3.1
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Re: [Intel-gfx] [PATCH] drm/i915/skl: handle all pixel formats in skylake_update_primary_plane()
On Mon, Feb 16, 2015 at 02:22:20PM +, Damien Lespiau wrote: > On Tue, Feb 10, 2015 at 01:43:39PM +0200, Ville Syrjälä wrote: > > On Tue, Feb 10, 2015 at 01:15:49PM +0200, Jani Nikula wrote: > > > skylake_update_primary_plane() did not handle all pixel formats returned > > > by skl_format_to_fourcc(). Handle alpha similar to skl_update_plane(). > > > > > > Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=89052 > > > Signed-off-by: Jani Nikula > > > > > > --- > > > > > > This is purely cargo culting to avoid the BUG. > > > --- > > > drivers/gpu/drm/i915/intel_display.c | 9 + > > > 1 file changed, 9 insertions(+) > > > > > > diff --git a/drivers/gpu/drm/i915/intel_display.c > > > b/drivers/gpu/drm/i915/intel_display.c > > > index 3fe95982be93..cede05256d56 100644 > > > --- a/drivers/gpu/drm/i915/intel_display.c > > > +++ b/drivers/gpu/drm/i915/intel_display.c > > > @@ -2751,10 +2751,19 @@ static void skylake_update_primary_plane(struct > > > drm_crtc *crtc, > > > case DRM_FORMAT_XRGB: > > > plane_ctl |= PLANE_CTL_FORMAT_XRGB_; > > > break; > > > + case DRM_FORMAT_ARGB: > > > + plane_ctl |= PLANE_CTL_FORMAT_XRGB_; > > > + plane_ctl |= PLANE_CTL_ALPHA_SW_PREMULTIPLY; > > > > We don't do alpha blending yet properly so we should just ignore alpha > > for now. And someone should rip out that bit from skl_update_plane() as > > well. > > We currently expose ARGB planes for VLV. Looking at the VLV Diplay > Cluster HAS the blending done in VLV (and so CHV I'm guessing?) is > > src + (1 - src_a) * dst > > Clearly suitable for pre-multiplied framebuffers (it's also stated so). > So, we already expose a default blendig mode suitable for pre-multiplied > FBs. This would be just doing the same and provide a (IMHO sensible) > default for fbs with alpha. > > So we could go with this? maybe? I thought we had a separate bit for actually enabling alpha blending. But I guess we don't? If so, we've maybe made a bit of a mess of things already. And anyway we've made an even bigger mess by exposing cursor planes before we have any alpha blending props. But yeah if we make the default blending mode '1*Sc + (1-Sa)*Dc, no extra premultiplication' for any alpha blending capable plane, it should mostly come out all right... I hope. And for any non alpha capable planes we obviously make the default (and only supported value) '1*Sc + 0*Dc'. If anyone has been using the A formats with non-alpha blending capable planes, well they already get something a bit iffty as the output when they feed it premultiplied data (assuming alpha < 1.0 obviously), and that wouldn't change with the addition of the alpha blending props. -- Ville Syrjälä Intel OTC ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH] drm/i915: Reset logical ring contexts' head and tail during GPU reset
Work was getting left behind in LRC contexts during reset. This causes a hang
if the GPU is reset when HEAD==TAIL because the context's ringbuffer head and
tail don't get reset and retiring a request doesn't alter them, so the ring
still appears full.
Added a function intel_lr_context_reset() to reset head and tail on a LRC and
its ringbuffer.
Call intel_lr_context_reset() for each context in i915_gem_context_reset() when
in execlists mode.
Testcase: igt/pm_rps --run-subtest reset #bdw
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=88096
Signed-off-by: Thomas Daniel
---
drivers/gpu/drm/i915/i915_gem_context.c | 12 +++
drivers/gpu/drm/i915/intel_lrc.c| 34 +++
drivers/gpu/drm/i915/intel_lrc.h|2 ++
3 files changed, 44 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_gem_context.c
b/drivers/gpu/drm/i915/i915_gem_context.c
index 8603bf4..70346b0 100644
--- a/drivers/gpu/drm/i915/i915_gem_context.c
+++ b/drivers/gpu/drm/i915/i915_gem_context.c
@@ -296,11 +296,15 @@ void i915_gem_context_reset(struct drm_device *dev)
struct drm_i915_private *dev_priv = dev->dev_private;
int i;
- /* In execlists mode we will unreference the context when the execlist
-* queue is cleared and the requests destroyed.
-*/
- if (i915.enable_execlists)
+ if (i915.enable_execlists) {
+ struct intel_context *ctx;
+
+ list_for_each_entry(ctx, &dev_priv->context_list, link) {
+ intel_lr_context_reset(dev, ctx);
+ }
+
return;
+ }
for (i = 0; i < I915_NUM_RINGS; i++) {
struct intel_engine_cs *ring = &dev_priv->ring[i];
diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c
index aafcef3..1946bb9 100644
--- a/drivers/gpu/drm/i915/intel_lrc.c
+++ b/drivers/gpu/drm/i915/intel_lrc.c
@@ -1950,3 +1950,37 @@ error_unpin_ctx:
drm_gem_object_unreference(&ctx_obj->base);
return ret;
}
+
+void intel_lr_context_reset(struct drm_device *dev,
+ struct intel_context *ctx)
+{
+ struct drm_i915_private *dev_priv = dev->dev_private;
+ struct intel_engine_cs *ring;
+ int i;
+
+ for_each_ring(ring, dev_priv, i) {
+ struct drm_i915_gem_object *ctx_obj =
+ ctx->engine[ring->id].state;
+ if (ctx_obj) {
+ struct intel_ringbuffer *ringbuf =
+ ctx->engine[ring->id].ringbuf;
+ uint32_t *reg_state;
+ struct page *page;
+
+ if (i915_gem_object_get_pages(ctx_obj)) {
+ WARN(1, "Failed get_pages for context obj\n");
+ continue;
+ }
+ page = i915_gem_object_get_page(ctx_obj, 1);
+ reg_state = kmap_atomic(page);
+
+ reg_state[CTX_RING_HEAD+1] = 0;
+ reg_state[CTX_RING_TAIL+1] = 0;
+
+ kunmap_atomic(reg_state);
+
+ ringbuf->head = 0;
+ ringbuf->tail = 0;
+ }
+ }
+}
diff --git a/drivers/gpu/drm/i915/intel_lrc.h b/drivers/gpu/drm/i915/intel_lrc.h
index f635735..5dd0eca 100644
--- a/drivers/gpu/drm/i915/intel_lrc.h
+++ b/drivers/gpu/drm/i915/intel_lrc.h
@@ -73,6 +73,8 @@ int intel_lr_context_deferred_create(struct intel_context
*ctx,
struct intel_engine_cs *ring);
void intel_lr_context_unpin(struct intel_engine_cs *ring,
struct intel_context *ctx);
+void intel_lr_context_reset(struct drm_device *dev,
+ struct intel_context *ctx);
/* Execlists */
int intel_sanitize_enable_execlists(struct drm_device *dev, int
enable_execlists);
--
1.7.9.5
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Re: [Intel-gfx] [PATCH] drm/i915/skl: handle all pixel formats in skylake_update_primary_plane()
On Tue, Feb 10, 2015 at 01:15:49PM +0200, Jani Nikula wrote: > skylake_update_primary_plane() did not handle all pixel formats returned > by skl_format_to_fourcc(). Handle alpha similar to skl_update_plane(). > > Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=89052 > Signed-off-by: Jani Nikula Given the discussion with Ville, it's quite likely we'll default to alpha blending for pre-multiplied fbs (for plane supporting alpha), even with the blending properties added. In that context, we can provide a single, fixed, (but useful) blending mode before we get to implement the full thing. So: Reviewed-by: Damien Lespiau -- Damien > --- > > This is purely cargo culting to avoid the BUG. > --- > drivers/gpu/drm/i915/intel_display.c | 9 + > 1 file changed, 9 insertions(+) > > diff --git a/drivers/gpu/drm/i915/intel_display.c > b/drivers/gpu/drm/i915/intel_display.c > index 3fe95982be93..cede05256d56 100644 > --- a/drivers/gpu/drm/i915/intel_display.c > +++ b/drivers/gpu/drm/i915/intel_display.c > @@ -2751,10 +2751,19 @@ static void skylake_update_primary_plane(struct > drm_crtc *crtc, > case DRM_FORMAT_XRGB: > plane_ctl |= PLANE_CTL_FORMAT_XRGB_; > break; > + case DRM_FORMAT_ARGB: > + plane_ctl |= PLANE_CTL_FORMAT_XRGB_; > + plane_ctl |= PLANE_CTL_ALPHA_SW_PREMULTIPLY; > + break; > case DRM_FORMAT_XBGR: > plane_ctl |= PLANE_CTL_ORDER_RGBX; > plane_ctl |= PLANE_CTL_FORMAT_XRGB_; > break; > + case DRM_FORMAT_ABGR: > + plane_ctl |= PLANE_CTL_ORDER_RGBX; > + plane_ctl |= PLANE_CTL_FORMAT_XRGB_; > + plane_ctl |= PLANE_CTL_ALPHA_SW_PREMULTIPLY; > + break; > case DRM_FORMAT_XRGB2101010: > plane_ctl |= PLANE_CTL_FORMAT_XRGB_2101010; > break; > -- > 2.1.4 > > ___ > Intel-gfx mailing list > Intel-gfx@lists.freedesktop.org > http://lists.freedesktop.org/mailman/listinfo/intel-gfx ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 2/2] drm/i915: Don't try to set INSTPM for the _ABSOLUTE constant buffer address
Gen9 bit to control whether the 3DSTATE_CONSTANT_* address should be an
offset against the Dynamic State Base Address Vs an absolute address has
moved to a different register.
As no-one complained yet and I don't see any use of the
I915_EXEC_CONSTANTS_ABSOLUTE flag in either the DDX, mesa, libdrm or
libva, I'm taking the opportunity to deprecate the flag on gen9 (it
never worked in the first place).
Signed-off-by: Damien Lespiau
---
drivers/gpu/drm/i915/intel_lrc.c | 13 -
include/uapi/drm/i915_drm.h | 2 +-
2 files changed, 13 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c
index 896641a..836356a 100644
--- a/drivers/gpu/drm/i915/intel_lrc.c
+++ b/drivers/gpu/drm/i915/intel_lrc.c
@@ -647,6 +647,16 @@ int intel_execlists_submission(struct drm_device *dev,
struct drm_file *file,
case I915_EXEC_CONSTANTS_REL_GENERAL:
case I915_EXEC_CONSTANTS_ABSOLUTE:
case I915_EXEC_CONSTANTS_REL_SURFACE:
+ if (instp_mode != 0 && INTEL_INFO(dev)->gen >= 9) {
+ /*
+* While it's possible to implement _ABSOLUTE, noone
+* complained when it was broken, so let's simplify the
+* driver by not supporting it until further notice.
+*/
+ DRM_DEBUG("no rel constants on gen9+\n");
+ return -EINVAL;
+ }
+
if (instp_mode != 0 && ring != &dev_priv->ring[RCS]) {
DRM_DEBUG("non-0 rel constants mode on non-RCS\n");
return -EINVAL;
@@ -691,7 +701,8 @@ int intel_execlists_submission(struct drm_device *dev,
struct drm_file *file,
if (ret)
return ret;
- if (instp_mode != dev_priv->relative_constants_mode &&
+ /* We deprecated the I915_EXEC_CONSTANTS on gen9+, for lack of user */
+ if (instp_mode != dev_priv->relative_constants_mode && IS_GEN8(dev) &&
ring == &dev_priv->ring[RCS]) {
ret = intel_logical_ring_begin(ringbuf, ctx, 4);
if (ret)
diff --git a/include/uapi/drm/i915_drm.h b/include/uapi/drm/i915_drm.h
index 6eed16b..d7c17b7 100644
--- a/include/uapi/drm/i915_drm.h
+++ b/include/uapi/drm/i915_drm.h
@@ -715,7 +715,7 @@ struct drm_i915_gem_execbuffer2 {
*/
#define I915_EXEC_CONSTANTS_MASK (3<<6)
#define I915_EXEC_CONSTANTS_REL_GENERAL (0<<6) /* default */
-#define I915_EXEC_CONSTANTS_ABSOLUTE (1<<6)
+#define I915_EXEC_CONSTANTS_ABSOLUTE (1<<6) /* gen 4/5/6/7/8 only */
#define I915_EXEC_CONSTANTS_REL_SURFACE (2<<6) /* gen4/5 only */
__u64 flags;
__u64 rsvd1; /* now used for context info */
--
1.8.3.1
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[Intel-gfx] [PATCH 1/2] drm/i915: Re-order some checks to do the unlikely one first
instpm_mode != relative_constants_mode is quite unlikely to happen, so
we can test it first to use C's && short-circuiting and not test on
'ring'.
I know, probably a useless micro-optimisation in the big scheme of
things, but I'm going to add another test here, so might as well do it.
Signed-off-by: Damien Lespiau
---
drivers/gpu/drm/i915/intel_lrc.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c
index aafcef3..896641a 100644
--- a/drivers/gpu/drm/i915/intel_lrc.c
+++ b/drivers/gpu/drm/i915/intel_lrc.c
@@ -691,8 +691,8 @@ int intel_execlists_submission(struct drm_device *dev,
struct drm_file *file,
if (ret)
return ret;
- if (ring == &dev_priv->ring[RCS] &&
- instp_mode != dev_priv->relative_constants_mode) {
+ if (instp_mode != dev_priv->relative_constants_mode &&
+ ring == &dev_priv->ring[RCS]) {
ret = intel_logical_ring_begin(ringbuf, ctx, 4);
if (ret)
return ret;
--
1.8.3.1
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Re: [Intel-gfx] [PATCH 1/7] drm/i915/skl: Added new macros
On Fri, Feb 06, 2015 at 08:26:32PM +0530, akash.g...@intel.com wrote:
> From: Akash Goel
>
> For SKL, register definition for RPNSWREQ (A008), RPSTAT1(A01C)
> have changed slightly. Also on SKL, frequency is specified in
> units of 16.66 MHZ, compared to 50 MHZ for most of the earlier
> platforms and the time values are expressed in units of 1.33 us,
> compared to 1.28 us for earlier platforms.
> Added new macros for the aforementioned changes.
>
> Signed-off-by: Akash Goel
We try to put the relevant defines in the patch using them (for next
time :). Everything looks correct though:
Reviewed-by: Damien Lespiau
--
Damien
> ---
> drivers/gpu/drm/i915/i915_drv.h | 1 +
> drivers/gpu/drm/i915/i915_reg.h | 9 +
> 2 files changed, 10 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index ca64b99..529b9b2 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -2485,6 +2485,7 @@ struct drm_i915_cmd_table {
> #define NUM_L3_SLICES(dev) (IS_HSW_GT3(dev) ? 2 : HAS_L3_DPF(dev))
>
> #define GT_FREQUENCY_MULTIPLIER 50
> +#define GEN9_FREQ_SCALER 3
>
> #include "i915_trace.h"
>
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index cd3430f9..c4a4c58 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -2389,6 +2389,12 @@ enum skl_disp_power_wells {
> #define GEN6_RP_STATE_LIMITS (MCHBAR_MIRROR_BASE_SNB + 0x5994)
> #define GEN6_RP_STATE_CAP(MCHBAR_MIRROR_BASE_SNB + 0x5998)
>
> +#define FREQ_1_28_US(us) (((us) * 100) >> 7)
> +#define FREQ_1_33_US(us) (((us) * 3) >> 2)
> +#define GT_FREQ_FROM_PERIOD(us, dev) (IS_GEN9(dev) ? \
> + FREQ_1_33_US(us) : \
> + FREQ_1_28_US(us))
> +
> /*
> * Logical Context regs
> */
> @@ -6023,6 +6029,7 @@ enum skl_disp_power_wells {
> #define GEN6_TURBO_DISABLE (1<<31)
> #define GEN6_FREQUENCY(x) ((x)<<25)
> #define HSW_FREQUENCY(x) ((x)<<24)
> +#define GEN9_FREQUENCY(x) ((x)<<23)
> #define GEN6_OFFSET(x) ((x)<<19)
> #define GEN6_AGGRESSIVE_TURBO (0<<15)
> #define GEN6_RC_VIDEO_FREQ 0xA00C
> @@ -6041,8 +6048,10 @@ enum skl_disp_power_wells {
> #define GEN6_RPSTAT1 0xA01C
> #define GEN6_CAGF_SHIFT8
> #define HSW_CAGF_SHIFT 7
> +#define GEN9_CAGF_SHIFT23
> #define GEN6_CAGF_MASK (0x7f << GEN6_CAGF_SHIFT)
> #define HSW_CAGF_MASK (0x7f << HSW_CAGF_SHIFT)
> +#define GEN9_CAGF_MASK (0x1ff << GEN9_CAGF_SHIFT)
> #define GEN6_RP_CONTROL 0xA024
> #define GEN6_RP_MEDIA_TURBO(1<<11)
> #define GEN6_RP_MEDIA_MODE_MASK(3<<9)
> --
> 1.9.2
>
___
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Re: [Intel-gfx] [PATCH 1/2] drm/i915: Re-order some checks to do the unlikely one first
On Mon, Feb 16, 2015 at 06:25:10PM +, Damien Lespiau wrote: > instpm_mode != relative_constants_mode is quite unlikely to happen, so > we can test it first to use C's && short-circuiting and not test on > 'ring'. > > I know, probably a useless micro-optimisation in the big scheme of > things, but I'm going to add another test here, so might as well do it. If you want to get pedantic, we want to move this to per-context :) -Chris -- Chris Wilson, Intel Open Source Technology Centre ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH 2/2] drm/i915: Move drm_framebuffer_unreference out of struct_mutex for takeover
Tested-By: PRC QA PRTS (Patch Regression Test System Contact: shuang...@intel.com) Task id: 5783 -Summary- Platform Delta drm-intel-nightly Series Applied PNV -1 277/277 276/277 ILK 313/313 313/313 SNB -1 309/309 308/309 IVB 382/382 382/382 BYT 296/296 296/296 HSW 425/425 425/425 BDW -1 318/318 317/318 -Detailed- Platform Testdrm-intel-nightly Series Applied *PNV igt_drm_vma_limiter_cached NRUN(1)PASS(1) NO_RESULT(1)PASS(1) *SNB igt_kms_plane_plane-position-covered-pipe-B-plane-1 PASS(2) DMESG_WARN(1)PASS(1) *BDW igt_gem_gtt_hog PASS(5) DMESG_WARN(1)PASS(1) Note: You need to pay more attention to line start with '*' ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH] drm: Fix the CRTC_STEREO_DOUBLE_ONLY define to include stero modes
Tested-By: PRC QA PRTS (Patch Regression Test System Contact: shuang...@intel.com) Task id: 5784 -Summary- Platform Delta drm-intel-nightly Series Applied PNV -36 277/277 241/277 ILK 313/313 313/313 SNB 309/309 309/309 IVB -1 382/382 381/382 BYT 296/296 296/296 HSW 425/425 425/425 BDW -1 318/318 317/318 -Detailed- Platform Testdrm-intel-nightly Series Applied *PNV igt_gem_persistent_relocs_forked-faulting-reloc-thrashing PASS(2) NRUN(1) *PNV igt_gem_persistent_relocs_forked-interruptible PASS(2) NRUN(1) *PNV igt_gem_pwrite_pread_display-copy-correctness PASS(2) NRUN(1) *PNV igt_gem_reloc_overflow_source-offset-negative-reloc-gtt PASS(2) NRUN(1) *PNV igt_gem_reloc_overflow_source-offset-unaligned-reloc-gtt PASS(2) NRUN(1) *PNV igt_gem_reloc_vs_gpu_faulting-reloc-interruptible PASS(2) NRUN(1) *PNV igt_gem_set_tiling_vs_blt_tiled-to-untiled PASS(2) NRUN(1) *PNV igt_gem_tiling_max_stride NO_RESULT(1)PASS(1) NRUN(1) *PNV igt_gem_userptr_blits_coherency-sync PASS(3) NRUN(1) *PNV igt_gem_userptr_blits_forked-sync-swapping-multifd-mempressure-interruptible PASS(2) NRUN(1) *PNV igt_gem_userptr_blits_forked-sync-swapping-multifd-mempressure-normal PASS(2) NRUN(1) *PNV igt_gem_userptr_blits_minor-unsync-normal PASS(2) NRUN(1) *PNV igt_gem_userptr_blits_process-exit PASS(2) NRUN(1) *PNV igt_gem_userptr_blits_sync-overlap PASS(2) NRUN(1) *PNV igt_gem_userptr_blits_sync-unmap PASS(2) NRUN(1) *PNV igt_gem_userptr_blits_sync-unmap-after-close PASS(2) NRUN(1) *PNV igt_gem_userptr_blits_unsync-unmap PASS(2) NRUN(1) *PNV igt_gem_userptr_blits_unsync-unmap-cycles PASS(2) NRUN(1) *PNV igt_gem_userptr_blits_usage-restrictions PASS(2) NRUN(1) *PNV igt_kms_addfb_bad-pitch-1024 PASS(2) NRUN(1) *PNV igt_kms_addfb_bad-pitch-128 PASS(2) NRUN(1) *PNV igt_kms_addfb_bad-pitch-256 PASS(2) NRUN(1) *PNV igt_kms_addfb_bad-pitch-32 PASS(2) NRUN(1) *PNV igt_kms_addfb_bad-pitch-65536 PASS(2) NRUN(1) *PNV igt_kms_addfb_bo-too-small-due-to-tiling PASS(2) NRUN(1) *PNV igt_kms_addfb_framebuffer-vs-set-tiling PASS(2) NRUN(1) *PNV igt_kms_addfb_normal PASS(2) NRUN(1) *PNV igt_kms_addfb_size-max PASS(2) NRUN(1) *PNV igt_kms_addfb_small-bo PASS(2) NRUN(1) *PNV igt_kms_addfb_too-high PASS(2) NRUN(1) *PNV igt_kms_addfb_too-wide PASS(2) NRUN(1) *PNV igt_kms_pipe_crc_basic_bad-nb-words-1 PASS(2) NRUN(1) *PNV igt_prime_self_import_reimport-vs-gem_close-race PASS(2) NRUN(1) *PNV igt_template_A PASS(2) NRUN(1) *PNV igt_gem_partial_pwrite_pread_reads PASS(2) NRUN(1) *PNV igt_gem_partial_pwrite_pread_reads-display PASS(2) NO_RESULT(1) *IVB igt_gem_storedw_batches_loop_normal PASS(3) DMESG_WARN(1)PASS(1) *BDW igt_gem_gtt_hog PASS(5) DMESG_WARN(1)PASS(1) Note: You need to pay more attention to line start with '*' ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH] drm/i915: Reset logical ring contexts' head and tail during GPU reset
Tested-By: PRC QA PRTS (Patch Regression Test System Contact: shuang...@intel.com) Task id: 5785 -Summary- Platform Delta drm-intel-nightly Series Applied PNV -5 277/277 272/277 ILK 313/313 313/313 SNB -1 309/309 308/309 IVB -1 382/382 381/382 BYT 296/296 296/296 HSW 425/425 425/425 BDW -1 318/318 317/318 -Detailed- Platform Testdrm-intel-nightly Series Applied *PNV igt_gem_fence_thrash_bo-write-verify-none NRUN(1)PASS(2) FAIL(1)PASS(1) *PNV igt_gem_fence_thrash_bo-write-verify-x PASS(3) FAIL(1)PASS(1) *PNV igt_gem_fence_thrash_bo-write-verify-y PASS(3) FAIL(1)PASS(1) PNV igt_gem_userptr_blits_coherency-sync CRASH(1)PASS(3) CRASH(1)PASS(1) PNV igt_gem_userptr_blits_coherency-unsync CRASH(1)PASS(2) CRASH(1)PASS(1) *SNB igt_kms_pipe_crc_basic_read-crc-pipe-A PASS(2) DMESG_WARN(1)PASS(1) *IVB igt_gem_storedw_batches_loop_normal PASS(3) DMESG_WARN(1)PASS(1) *BDW igt_gem_gtt_hog PASS(5) DMESG_WARN(1)PASS(1) Note: You need to pay more attention to line start with '*' ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH 2/2] drm/i915: Don't try to set INSTPM for the _ABSOLUTE constant buffer address
Tested-By: PRC QA PRTS (Patch Regression Test System Contact: shuang...@intel.com) Task id: 5786 -Summary- Platform Delta drm-intel-nightly Series Applied PNV -5 277/277 272/277 ILK 313/313 313/313 SNB -1 309/309 308/309 IVB 382/382 382/382 BYT 296/296 296/296 HSW 425/425 425/425 BDW -1 318/318 317/318 -Detailed- Platform Testdrm-intel-nightly Series Applied *PNV igt_gem_fence_thrash_bo-write-verify-none NRUN(1)PASS(2) FAIL(1)PASS(1) *PNV igt_gem_fence_thrash_bo-write-verify-x PASS(3) FAIL(1)NO_RESULT(1) *PNV igt_gem_fence_thrash_bo-write-verify-y PASS(3) FAIL(1)PASS(1) *PNV igt_gem_userptr_blits_coherency-sync CRASH(1)PASS(3) NO_RESULT(1)CRASH(1) PNV igt_gem_userptr_blits_coherency-unsync CRASH(1)PASS(2) CRASH(2) *SNB igt_kms_plane_plane-panning-top-left-pipe-B-plane-1 PASS(2) TIMEOUT(1)PASS(1) *BDW igt_gem_gtt_hog PASS(5) DMESG_WARN(1)PASS(1) Note: You need to pay more attention to line start with '*' ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx
